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From: Stuart Summers <stuart.summers@intel.com>
Cc: intel-xe@lists.freedesktop.org, rodrigo.vivi@intel.com,
	matthew.brost@intel.com, matthew.d.roper@intel.com,
	fei.yang@intel.com, Stuart Summers <stuart.summers@intel.com>
Subject: [PATCH 04/11] drm/xe: Guard per-tile primary GT accesses
Date: Tue, 10 Nov 2026 23:14:46 +0000	[thread overview]
Message-ID: <20261110231442.218721-17-stuart.summers@intel.com> (raw)
In-Reply-To: <20261110231442.218721-13-stuart.summers@intel.com>

A tile's primary GT is now optional, just like its media GT already was.
The TLB invalidation and memory interrupt paths walk both GTs of a tile
but only test the media one for presence, so they would dereference NULL
on a device whose graphics IP is absent.  Mirror the existing media
checks for the primary GT.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/xe/xe_memirq.c    |  9 +++----
 drivers/gpu/drm/xe/xe_tlb_inval.c | 41 ++++++++++++++++---------------
 2 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_memirq.c b/drivers/gpu/drm/xe/xe_memirq.c
index 3433518cc095..315f28661c63 100644
--- a/drivers/gpu/drm/xe/xe_memirq.c
+++ b/drivers/gpu/drm/xe/xe_memirq.c
@@ -578,16 +578,15 @@ void xe_memirq_handler(struct xe_memirq *memirq)
 
 	/* GuC and media GuC (if present) must be checked separately */
 
-	if (memirq_received(memirq, &memirq->source, ilog2(INTR_GUC), "SRC")) {
+	if (tile->primary_gt &&
+	    memirq_received(memirq, &memirq->source, ilog2(INTR_GUC), "SRC")) {
 		map = IOSYS_MAP_INIT_OFFSET(&memirq->bo->vmap,
 					    XE_MEMIRQ_VECTOR_OFFSET(0, ilog2(INTR_GUC)));
 		memirq_dispatch_guc(memirq, &map, &tile->primary_gt->uc.guc);
 	}
 
-	if (!tile->media_gt)
-		return;
-
-	if (memirq_received(memirq, &memirq->source, ilog2(INTR_MGUC), "SRC")) {
+	if (tile->media_gt &&
+	    memirq_received(memirq, &memirq->source, ilog2(INTR_MGUC), "SRC")) {
 		map = IOSYS_MAP_INIT_OFFSET(&memirq->bo->vmap,
 					    XE_MEMIRQ_VECTOR_OFFSET(0, ilog2(INTR_MGUC)));
 		memirq_dispatch_guc(memirq, &map, &tile->media_gt->uc.guc);
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.c b/drivers/gpu/drm/xe/xe_tlb_inval.c
index c9cc5842d65b..32b62b76e6b0 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval.c
@@ -624,28 +624,29 @@ int xe_tlb_inval_range_tilemask_submit(struct xe_device *xe, u32 asid,
 		if (!(tile_mask & BIT(id)))
 			continue;
 
-		xe_tlb_inval_fence_init(&tile->primary_gt->tlb_inval,
-					&fence[fence_id], true);
-
-		err = xe_tlb_inval_range(&tile->primary_gt->tlb_inval,
-					 &fence[fence_id], start, end,
-					 asid, NULL);
-		if (err)
-			goto wait;
-		++fence_id;
-
-		if (!tile->media_gt)
-			continue;
+		if (tile->primary_gt) {
+			xe_tlb_inval_fence_init(&tile->primary_gt->tlb_inval,
+						&fence[fence_id], true);
+
+			err = xe_tlb_inval_range(&tile->primary_gt->tlb_inval,
+						 &fence[fence_id], start, end,
+						 asid, NULL);
+			if (err)
+				goto wait;
+			++fence_id;
+		}
 
-		xe_tlb_inval_fence_init(&tile->media_gt->tlb_inval,
-					&fence[fence_id], true);
+		if (tile->media_gt) {
+			xe_tlb_inval_fence_init(&tile->media_gt->tlb_inval,
+						&fence[fence_id], true);
 
-		err = xe_tlb_inval_range(&tile->media_gt->tlb_inval,
-					 &fence[fence_id], start, end,
-					 asid, NULL);
-		if (err)
-			goto wait;
-		++fence_id;
+			err = xe_tlb_inval_range(&tile->media_gt->tlb_inval,
+						 &fence[fence_id], start, end,
+						 asid, NULL);
+			if (err)
+				goto wait;
+			++fence_id;
+		}
 	}
 
 wait:
-- 
2.43.0


  parent reply	other threads:[~2026-11-10 23:15 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-10 23:14 [PATCH 00/11] Allow boot with only media GT Stuart Summers
2026-11-10 23:14 ` [PATCH 01/11] drm/xe: Detect each GMD_ID IP in a loop Stuart Summers
2026-11-10 23:14 ` [PATCH 02/11] drm/xe: Tolerate a missing graphics IP in xe_info_init() Stuart Summers
2026-11-10 23:14 ` [PATCH 03/11] drm/xe: Verify IP presence against GU_CNTL Stuart Summers
2026-11-10 23:14 ` Stuart Summers [this message]
2026-11-10 23:14 ` [PATCH 05/11] drm/xe: Stop assuming the root tile has a primary GT Stuart Summers
2026-11-11  2:59   ` sashiko-bot
2026-11-10 23:14 ` [PATCH 06/11] drm/xe: Do not claim flat CCS without a graphics IP Stuart Summers
2026-11-11  3:21   ` sashiko-bot
2026-11-10 23:14 ` [PATCH 07/11] drm/xe: Run page table updates on the media GT when there is no primary Stuart Summers
2026-11-11  3:53   ` sashiko-bot
2026-11-10 23:14 ` [PATCH 08/11] drm/xe: Document that gt_types_allowed=media now probes Stuart Summers
2026-11-10 23:14 ` [PATCH 09/11] drm/xe: Fall back to CPU copies when the tile cannot blit Stuart Summers
2026-11-11  4:25   ` sashiko-bot
2026-11-10 23:14 ` [PATCH 10/11] drm/xe: Require a fully visible VRAM BAR without a primary GT Stuart Summers
2026-11-11  4:38   ` sashiko-bot
2026-11-10 23:14 ` [PATCH 11/11] drm/xe: Allow probe " Stuart Summers
2026-11-11  4:57   ` sashiko-bot
2026-11-10 23:39 ` ✓ CI.KUnit: success for Allow boot with only media GT Patchwork
2026-11-11  0:14 ` ✓ Xe.CI.BAT: " Patchwork
2026-11-11  4:17 ` ✓ Xe.CI.FULL: " Patchwork
2026-11-12 12:21 ` [PATCH 00/11] " Piotr Piórkowski

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