[PATCH 03/10] drm/i915/display: Add strength and winsize register

[PATCH 03/10] drm/i915/display: Add strength and winsize register

[Nemesa Garg]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 8594 bytes --]

The sharpness strength value is determined by user input,
while the winsize is based on the resolution.
The casf_enable flag should be set if the platform supports
sharpness adjustments and the user API strength is not zero.
Once sharpness is enabled, update the strength bit of the
register whenever the user changes the strength value,
as the enable bit and winsize bit remain constant.

v2: Introduce get_config for casf[Ankit]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_casf.c     | 102 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_casf.h     |  17 +++
 .../gpu/drm/i915/display/intel_casf_regs.h    |  22 ++++
 .../drm/i915/display/intel_display_types.h    |   7 ++
 drivers/gpu/drm/i915/display/skl_scaler.c     |   1 +
 drivers/gpu/drm/xe/Makefile                   |   1 +
 7 files changed, 151 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf_regs.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c8fc271b33b7..a955960d09ec 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -230,6 +230,7 @@ i915-y += \
 	display/intel_bios.o \
 	display/intel_bo.o \
 	display/intel_bw.o \
+	display/intel_casf.o \
 	display/intel_cdclk.o \
 	display/intel_cmtg.o \
 	display/intel_color.o \
diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
new file mode 100644
index 000000000000..79a59e768c32
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ *
+ */
+
+#include <drm/drm_print.h>
+
+#include "i915_reg.h"
+#include "intel_casf.h"
+#include "intel_casf_regs.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+
+#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
+#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)
+
+/**
+ * DOC: Content Adaptive Sharpness Filter (CASF)
+ *
+ * Starting from LNL the display engine supports an
+ * adaptive sharpening filter, enhancing the image
+ * quality. The display hardware utilizes one of the
+ * pipe scaler for implementing CASF.
+ * This filter operates on a region of pixels based
+ * on the tap size. Coefficients are used to generate
+ * an alpha value which blends the sharpened image to
+ * original image.
+ */
+
+void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), 0,
+		     FILTER_STRENGTH(crtc_state->hw.casf_params.strength));
+}
+
+static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
+{
+	const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
+	u16 total_pixels = mode->hdisplay * mode->vdisplay;
+
+	if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3;
+	else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5;
+	else
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7;
+}
+
+int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!HAS_CASF(display))
+		return 0;
+
+	if (crtc_state->uapi.sharpness_strength == 0) {
+		crtc_state->hw.casf_params.casf_enable = false;
+		crtc_state->hw.casf_params.strength = 0;
+		return 0;
+	}
+
+	crtc_state->hw.casf_params.casf_enable = true;
+
+	/*
+	 * HW takes a value in form (1.0 + strength) in 4.4 fixed format.
+	 * Strength is from 0.0-14.9375 ie from 0-239.
+	 * User can give value from 0-255 but is clamped to 239.
+	 * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
+	 * 6.3125 in 4.4 format is b01100101 which is equal to 101.
+	 * Also 85 + 16 = 101.
+	 */
+	crtc_state->hw.casf_params.strength =
+		min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
+
+	intel_casf_compute_win_size(crtc_state);
+
+	return 0;
+}
+
+void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	u32 sharp;
+
+	sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));
+	if (sharp & FILTER_EN) {
+		if (drm_WARN_ON(display->drm,
+				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16))
+			crtc_state->hw.casf_params.strength = 0;
+		else
+			crtc_state->hw.casf_params.strength =
+				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp);
+		crtc_state->hw.casf_params.casf_enable = true;
+		crtc_state->hw.casf_params.win_size =
+			REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h
new file mode 100644
index 000000000000..83523fe66c48
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_CASF_H__
+#define __INTEL_CASF_H__
+
+#include <linux/types.h>
+
+struct intel_crtc_state;
+
+int intel_casf_compute_config(struct intel_crtc_state *crtc_state);
+void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state);
+void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state);
+
+#endif /* __INTEL_CASF_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h
new file mode 100644
index 000000000000..c24ba281ae37
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_CASF_REGS_H__
+#define __INTEL_CASF_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _SHARPNESS_CTL_A               0x682B0
+#define _SHARPNESS_CTL_B               0x68AB0
+#define SHARPNESS_CTL(pipe)            _MMIO_PIPE(pipe, _SHARPNESS_CTL_A, _SHARPNESS_CTL_B)
+#define   FILTER_EN                    REG_BIT(31)
+#define   FILTER_STRENGTH_MASK         REG_GENMASK(15, 8)
+#define   FILTER_STRENGTH(x)           REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x))
+#define   FILTER_SIZE_MASK             REG_GENMASK(1, 0)
+#define   SHARPNESS_FILTER_SIZE_3X3    REG_FIELD_PREP(FILTER_SIZE_MASK, 0)
+#define   SHARPNESS_FILTER_SIZE_5X5    REG_FIELD_PREP(FILTER_SIZE_MASK, 1)
+#define   SHARPNESS_FILTER_SIZE_7X7    REG_FIELD_PREP(FILTER_SIZE_MASK, 2)
+
+#endif /* __INTEL_CASF_REGS__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 367b53a9eae2..f920143920cd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -931,6 +931,12 @@ struct intel_csc_matrix {
 	u16 postoff[3];
 };
 
+struct intel_casf {
+	u8 strength;
+	u8 win_size;
+	bool casf_enable;
+};
+
 void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val);
 
 typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val);
@@ -971,6 +977,7 @@ struct intel_crtc_state {
 		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
 		struct drm_display_mode mode, pipe_mode, adjusted_mode;
 		enum drm_scaling_filter scaling_filter;
+		struct intel_casf casf_params;
 	} hw;
 
 	/* actual state of LUTs */
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index ee81220a7c88..f0cf966211c9 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -5,6 +5,7 @@
 
 #include "i915_drv.h"
 #include "i915_reg.h"
+#include "intel_casf_regs.h"
 #include "intel_de.h"
 #include "intel_display_trace.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 72eaadc4cbee..fb6d8e4edd91 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -210,6 +210,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_backlight.o \
 	i915-display/intel_bios.o \
 	i915-display/intel_bw.o \
+	i915-display/intel_casf.o \
 	i915-display/intel_cdclk.o \
 	i915-display/intel_cmtg.o \
 	i915-display/intel_color.o \
-- 
2.25.1

Re: [PATCH 03/10] drm/i915/display: Add strength and winsize register

[Nautiyal, Ankit K]

On 4/2/2025 6:26 PM, Nemesa Garg wrote:
> The sharpness strength value is determined by user input,
> while the winsize is based on the resolution.
> The casf_enable flag should be set if the platform supports
> sharpness adjustments and the user API strength is not zero.
> Once sharpness is enabled, update the strength bit of the
> register whenever the user changes the strength value,
> as the enable bit and winsize bit remain constant.
>
> v2: Introduce get_config for casf[Ankit]
>
> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>   drivers/gpu/drm/i915/Makefile                 |   1 +
>   drivers/gpu/drm/i915/display/intel_casf.c     | 102 ++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_casf.h     |  17 +++
>   .../gpu/drm/i915/display/intel_casf_regs.h    |  22 ++++
>   .../drm/i915/display/intel_display_types.h    |   7 ++
>   drivers/gpu/drm/i915/display/skl_scaler.c     |   1 +
>   drivers/gpu/drm/xe/Makefile                   |   1 +
>   7 files changed, 151 insertions(+)
>   create mode 100644 drivers/gpu/drm/i915/display/intel_casf.c
>   create mode 100644 drivers/gpu/drm/i915/display/intel_casf.h
>   create mode 100644 drivers/gpu/drm/i915/display/intel_casf_regs.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index c8fc271b33b7..a955960d09ec 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -230,6 +230,7 @@ i915-y += \
>   	display/intel_bios.o \
>   	display/intel_bo.o \
>   	display/intel_bw.o \
> +	display/intel_casf.o \
>   	display/intel_cdclk.o \
>   	display/intel_cmtg.o \
>   	display/intel_color.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
> new file mode 100644
> index 000000000000..79a59e768c32
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_casf.c
> @@ -0,0 +1,102 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + *
> + */
> +
> +#include <drm/drm_print.h>
> +
> +#include "i915_reg.h"
> +#include "intel_casf.h"
> +#include "intel_casf_regs.h"
> +#include "intel_de.h"
> +#include "intel_display_types.h"
> +
> +#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
> +#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)
> +
> +/**
> + * DOC: Content Adaptive Sharpness Filter (CASF)
> + *
> + * Starting from LNL the display engine supports an
> + * adaptive sharpening filter, enhancing the image
> + * quality. The display hardware utilizes one of the
> + * pipe scaler for implementing CASF.
> + * This filter operates on a region of pixels based
> + * on the tap size. Coefficients are used to generate
> + * an alpha value which blends the sharpened image to
> + * original image.
> + */
> +
> +void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> +	intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), 0,
> +		     FILTER_STRENGTH(crtc_state->hw.casf_params.strength));

Need to clear FILTER_SIZE_MASK instead of passing 0.

Regards,

Ankit

> +}
> +
> +static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
> +{
> +	const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
> +	u16 total_pixels = mode->hdisplay * mode->vdisplay;
> +
> +	if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
> +		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3;
> +	else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
> +		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5;
> +	else
> +		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7;
> +}
> +
> +int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (!HAS_CASF(display))
> +		return 0;
> +
> +	if (crtc_state->uapi.sharpness_strength == 0) {
> +		crtc_state->hw.casf_params.casf_enable = false;
> +		crtc_state->hw.casf_params.strength = 0;
> +		return 0;
> +	}
> +
> +	crtc_state->hw.casf_params.casf_enable = true;
> +
> +	/*
> +	 * HW takes a value in form (1.0 + strength) in 4.4 fixed format.
> +	 * Strength is from 0.0-14.9375 ie from 0-239.
> +	 * User can give value from 0-255 but is clamped to 239.
> +	 * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
> +	 * 6.3125 in 4.4 format is b01100101 which is equal to 101.
> +	 * Also 85 + 16 = 101.
> +	 */
> +	crtc_state->hw.casf_params.strength =
> +		min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
> +
> +	intel_casf_compute_win_size(crtc_state);
> +
> +	return 0;
> +}
> +
> +void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	u32 sharp;
> +
> +	sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));
> +	if (sharp & FILTER_EN) {
> +		if (drm_WARN_ON(display->drm,
> +				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16))
> +			crtc_state->hw.casf_params.strength = 0;
> +		else
> +			crtc_state->hw.casf_params.strength =
> +				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp);
> +		crtc_state->hw.casf_params.casf_enable = true;
> +		crtc_state->hw.casf_params.win_size =
> +			REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
> +	}
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h
> new file mode 100644
> index 000000000000..83523fe66c48
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_casf.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_CASF_H__
> +#define __INTEL_CASF_H__
> +
> +#include <linux/types.h>
> +
> +struct intel_crtc_state;
> +
> +int intel_casf_compute_config(struct intel_crtc_state *crtc_state);
> +void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state);
> +void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state);
> +
> +#endif /* __INTEL_CASF_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h
> new file mode 100644
> index 000000000000..c24ba281ae37
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_CASF_REGS_H__
> +#define __INTEL_CASF_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define _SHARPNESS_CTL_A               0x682B0
> +#define _SHARPNESS_CTL_B               0x68AB0
> +#define SHARPNESS_CTL(pipe)            _MMIO_PIPE(pipe, _SHARPNESS_CTL_A, _SHARPNESS_CTL_B)
> +#define   FILTER_EN                    REG_BIT(31)
> +#define   FILTER_STRENGTH_MASK         REG_GENMASK(15, 8)
> +#define   FILTER_STRENGTH(x)           REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x))
> +#define   FILTER_SIZE_MASK             REG_GENMASK(1, 0)
> +#define   SHARPNESS_FILTER_SIZE_3X3    REG_FIELD_PREP(FILTER_SIZE_MASK, 0)
> +#define   SHARPNESS_FILTER_SIZE_5X5    REG_FIELD_PREP(FILTER_SIZE_MASK, 1)
> +#define   SHARPNESS_FILTER_SIZE_7X7    REG_FIELD_PREP(FILTER_SIZE_MASK, 2)
> +
> +#endif /* __INTEL_CASF_REGS__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 367b53a9eae2..f920143920cd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -931,6 +931,12 @@ struct intel_csc_matrix {
>   	u16 postoff[3];
>   };
>   
> +struct intel_casf {
> +	u8 strength;
> +	u8 win_size;
> +	bool casf_enable;
> +};
> +
>   void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val);
>   
>   typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val);
> @@ -971,6 +977,7 @@ struct intel_crtc_state {
>   		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
>   		struct drm_display_mode mode, pipe_mode, adjusted_mode;
>   		enum drm_scaling_filter scaling_filter;
> +		struct intel_casf casf_params;
>   	} hw;
>   
>   	/* actual state of LUTs */
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index ee81220a7c88..f0cf966211c9 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -5,6 +5,7 @@
>   
>   #include "i915_drv.h"
>   #include "i915_reg.h"
> +#include "intel_casf_regs.h"
>   #include "intel_de.h"
>   #include "intel_display_trace.h"
>   #include "intel_display_types.h"
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 72eaadc4cbee..fb6d8e4edd91 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -210,6 +210,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>   	i915-display/intel_backlight.o \
>   	i915-display/intel_bios.o \
>   	i915-display/intel_bw.o \
> +	i915-display/intel_casf.o \
>   	i915-display/intel_cdclk.o \
>   	i915-display/intel_cmtg.o \
>   	i915-display/intel_color.o \

[PATCH 03/10] drm/i915/display: Add strength and winsize register

[Nemesa Garg]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 8661 bytes --]

The sharpness strength value is determined by user input,
while the winsize is based on the resolution.
The casf_enable flag should be set if the platform supports
sharpness adjustments and the user API strength is not zero.
Once sharpness is enabled, update the strength bit of the
register whenever the user changes the strength value,
as the enable bit and winsize bit remain constant.

v2: Introduce get_config for casf[Ankit]
v3: Replace 0 with FILTER_STRENGTH_MASK[Ankit] 

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_casf.c     | 102 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_casf.h     |  17 +++
 .../gpu/drm/i915/display/intel_casf_regs.h    |  22 ++++
 .../drm/i915/display/intel_display_types.h    |   7 ++
 drivers/gpu/drm/i915/display/skl_scaler.c     |   1 +
 drivers/gpu/drm/xe/Makefile                   |   1 +
 7 files changed, 151 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf_regs.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c8fc271b33b7..a955960d09ec 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -230,6 +230,7 @@ i915-y += \
 	display/intel_bios.o \
 	display/intel_bo.o \
 	display/intel_bw.o \
+	display/intel_casf.o \
 	display/intel_cdclk.o \
 	display/intel_cmtg.o \
 	display/intel_color.o \
diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
new file mode 100644
index 000000000000..576dce477339
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ *
+ */
+
+#include <drm/drm_print.h>
+
+#include "i915_reg.h"
+#include "intel_casf.h"
+#include "intel_casf_regs.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+
+#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
+#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)
+
+/**
+ * DOC: Content Adaptive Sharpness Filter (CASF)
+ *
+ * Starting from LNL the display engine supports an
+ * adaptive sharpening filter, enhancing the image
+ * quality. The display hardware utilizes one of the
+ * pipe scaler for implementing CASF.
+ * This filter operates on a region of pixels based
+ * on the tap size. Coefficients are used to generate
+ * an alpha value which blends the sharpened image to
+ * original image.
+ */
+
+void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), FILTER_STRENGTH_MASK,
+		     FILTER_STRENGTH(crtc_state->hw.casf_params.strength));
+}
+
+static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
+{
+	const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
+	u16 total_pixels = mode->hdisplay * mode->vdisplay;
+
+	if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3;
+	else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5;
+	else
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7;
+}
+
+int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!HAS_CASF(display))
+		return 0;
+
+	if (crtc_state->uapi.sharpness_strength == 0) {
+		crtc_state->hw.casf_params.casf_enable = false;
+		crtc_state->hw.casf_params.strength = 0;
+		return 0;
+	}
+
+	crtc_state->hw.casf_params.casf_enable = true;
+
+	/*
+	 * HW takes a value in form (1.0 + strength) in 4.4 fixed format.
+	 * Strength is from 0.0-14.9375 ie from 0-239.
+	 * User can give value from 0-255 but is clamped to 239.
+	 * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
+	 * 6.3125 in 4.4 format is b01100101 which is equal to 101.
+	 * Also 85 + 16 = 101.
+	 */
+	crtc_state->hw.casf_params.strength =
+		min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
+
+	intel_casf_compute_win_size(crtc_state);
+
+	return 0;
+}
+
+void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	u32 sharp;
+
+	sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));
+	if (sharp & FILTER_EN) {
+		if (drm_WARN_ON(display->drm,
+				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16))
+			crtc_state->hw.casf_params.strength = 0;
+		else
+			crtc_state->hw.casf_params.strength =
+				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp);
+		crtc_state->hw.casf_params.casf_enable = true;
+		crtc_state->hw.casf_params.win_size =
+			REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h
new file mode 100644
index 000000000000..83523fe66c48
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_CASF_H__
+#define __INTEL_CASF_H__
+
+#include <linux/types.h>
+
+struct intel_crtc_state;
+
+int intel_casf_compute_config(struct intel_crtc_state *crtc_state);
+void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state);
+void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state);
+
+#endif /* __INTEL_CASF_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h
new file mode 100644
index 000000000000..c24ba281ae37
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_CASF_REGS_H__
+#define __INTEL_CASF_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _SHARPNESS_CTL_A               0x682B0
+#define _SHARPNESS_CTL_B               0x68AB0
+#define SHARPNESS_CTL(pipe)            _MMIO_PIPE(pipe, _SHARPNESS_CTL_A, _SHARPNESS_CTL_B)
+#define   FILTER_EN                    REG_BIT(31)
+#define   FILTER_STRENGTH_MASK         REG_GENMASK(15, 8)
+#define   FILTER_STRENGTH(x)           REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x))
+#define   FILTER_SIZE_MASK             REG_GENMASK(1, 0)
+#define   SHARPNESS_FILTER_SIZE_3X3    REG_FIELD_PREP(FILTER_SIZE_MASK, 0)
+#define   SHARPNESS_FILTER_SIZE_5X5    REG_FIELD_PREP(FILTER_SIZE_MASK, 1)
+#define   SHARPNESS_FILTER_SIZE_7X7    REG_FIELD_PREP(FILTER_SIZE_MASK, 2)
+
+#endif /* __INTEL_CASF_REGS__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 94468a9d2e0d..3af73e7ffdeb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -931,6 +931,12 @@ struct intel_csc_matrix {
 	u16 postoff[3];
 };
 
+struct intel_casf {
+	u8 strength;
+	u8 win_size;
+	bool casf_enable;
+};
+
 void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val);
 
 typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val);
@@ -971,6 +977,7 @@ struct intel_crtc_state {
 		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
 		struct drm_display_mode mode, pipe_mode, adjusted_mode;
 		enum drm_scaling_filter scaling_filter;
+		struct intel_casf casf_params;
 	} hw;
 
 	/* actual state of LUTs */
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index ee81220a7c88..f0cf966211c9 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -5,6 +5,7 @@
 
 #include "i915_drv.h"
 #include "i915_reg.h"
+#include "intel_casf_regs.h"
 #include "intel_de.h"
 #include "intel_display_trace.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 72eaadc4cbee..fb6d8e4edd91 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -210,6 +210,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_backlight.o \
 	i915-display/intel_bios.o \
 	i915-display/intel_bw.o \
+	i915-display/intel_casf.o \
 	i915-display/intel_cdclk.o \
 	i915-display/intel_cmtg.o \
 	i915-display/intel_color.o \
-- 
2.25.1

[PATCH 03/10] drm/i915/display: Add strength and winsize register

[Nemesa Garg]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 8939 bytes --]

The sharpness strength value is determined by user input,
while the winsize is based on the resolution.
The casf_enable flag should be set if the platform supports
sharpness adjustments and the user API strength is not zero.
Once sharpness is enabled, update the strength bit of the
register whenever the user changes the strength value,
as the enable bit and winsize bit remain constant.

v2: Introduce get_config for casf[Ankit]
v3: Replace 0 with FILTER_STRENGTH_MASK[Ankit]
v4: After updating strength add win_sz register

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_casf.c     | 109 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_casf.h     |  17 +++
 .../gpu/drm/i915/display/intel_casf_regs.h    |  22 ++++
 .../drm/i915/display/intel_display_types.h    |   7 ++
 drivers/gpu/drm/i915/display/skl_scaler.c     |   1 +
 drivers/gpu/drm/xe/Makefile                   |   1 +
 7 files changed, 158 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf_regs.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1a90eb1f180a..87c4c3d28243 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -229,6 +229,7 @@ i915-y += \
 	display/intel_bios.o \
 	display/intel_bo.o \
 	display/intel_bw.o \
+	display/intel_casf.o \
 	display/intel_cdclk.o \
 	display/intel_cmtg.o \
 	display/intel_color.o \
diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
new file mode 100644
index 000000000000..314d3fe19884
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ *
+ */
+
+#include <drm/drm_print.h>
+
+#include "i915_reg.h"
+#include "intel_casf.h"
+#include "intel_casf_regs.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+
+#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
+#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)
+
+/**
+ * DOC: Content Adaptive Sharpness Filter (CASF)
+ *
+ * Starting from LNL the display engine supports an
+ * adaptive sharpening filter, enhancing the image
+ * quality. The display hardware utilizes the second
+ * pipe scaler for implementing CASF.
+ * If sharpness is being enabled then pipe scaling
+ * cannot be used.
+ * This filter operates on a region of pixels based
+ * on the tap size. Coefficients are used to generate
+ * an alpha value which blends the sharpened image to
+ * original image.
+ */
+
+void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	int win_size;
+
+	intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), FILTER_STRENGTH_MASK,
+		     FILTER_STRENGTH(crtc_state->hw.casf_params.strength));
+
+	win_size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, 1));
+
+	intel_de_write_fw(display, SKL_PS_WIN_SZ(crtc->pipe, 1), win_size);
+}
+
+static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
+{
+	const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
+	u16 total_pixels = mode->hdisplay * mode->vdisplay;
+
+	if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3;
+	else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5;
+	else
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7;
+}
+
+int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!HAS_CASF(display))
+		return 0;
+
+	if (crtc_state->uapi.sharpness_strength == 0) {
+		crtc_state->hw.casf_params.casf_enable = false;
+		crtc_state->hw.casf_params.strength = 0;
+		return 0;
+	}
+
+	crtc_state->hw.casf_params.casf_enable = true;
+
+	/*
+	 * HW takes a value in form (1.0 + strength) in 4.4 fixed format.
+	 * Strength is from 0.0-14.9375 ie from 0-239.
+	 * User can give value from 0-255 but is clamped to 239.
+	 * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
+	 * 6.3125 in 4.4 format is b01100101 which is equal to 101.
+	 * Also 85 + 16 = 101.
+	 */
+	crtc_state->hw.casf_params.strength =
+		min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
+
+	intel_casf_compute_win_size(crtc_state);
+
+	return 0;
+}
+
+void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	u32 sharp;
+
+	sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));
+	if (sharp & FILTER_EN) {
+		if (drm_WARN_ON(display->drm,
+				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16))
+			crtc_state->hw.casf_params.strength = 0;
+		else
+			crtc_state->hw.casf_params.strength =
+				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp);
+		crtc_state->hw.casf_params.casf_enable = true;
+		crtc_state->hw.casf_params.win_size =
+			REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h
new file mode 100644
index 000000000000..83523fe66c48
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_CASF_H__
+#define __INTEL_CASF_H__
+
+#include <linux/types.h>
+
+struct intel_crtc_state;
+
+int intel_casf_compute_config(struct intel_crtc_state *crtc_state);
+void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state);
+void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state);
+
+#endif /* __INTEL_CASF_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h
new file mode 100644
index 000000000000..c24ba281ae37
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_CASF_REGS_H__
+#define __INTEL_CASF_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _SHARPNESS_CTL_A               0x682B0
+#define _SHARPNESS_CTL_B               0x68AB0
+#define SHARPNESS_CTL(pipe)            _MMIO_PIPE(pipe, _SHARPNESS_CTL_A, _SHARPNESS_CTL_B)
+#define   FILTER_EN                    REG_BIT(31)
+#define   FILTER_STRENGTH_MASK         REG_GENMASK(15, 8)
+#define   FILTER_STRENGTH(x)           REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x))
+#define   FILTER_SIZE_MASK             REG_GENMASK(1, 0)
+#define   SHARPNESS_FILTER_SIZE_3X3    REG_FIELD_PREP(FILTER_SIZE_MASK, 0)
+#define   SHARPNESS_FILTER_SIZE_5X5    REG_FIELD_PREP(FILTER_SIZE_MASK, 1)
+#define   SHARPNESS_FILTER_SIZE_7X7    REG_FIELD_PREP(FILTER_SIZE_MASK, 2)
+
+#endif /* __INTEL_CASF_REGS__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 056219272c36..3a2e2bdfd356 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -935,6 +935,12 @@ struct intel_csc_matrix {
 	u16 postoff[3];
 };
 
+struct intel_casf {
+	u8 strength;
+	u8 win_size;
+	bool casf_enable;
+};
+
 void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val);
 
 typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val);
@@ -975,6 +981,7 @@ struct intel_crtc_state {
 		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
 		struct drm_display_mode mode, pipe_mode, adjusted_mode;
 		enum drm_scaling_filter scaling_filter;
+		struct intel_casf casf_params;
 	} hw;
 
 	/* actual state of LUTs */
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index c855426544cf..3af481ee914e 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -7,6 +7,7 @@
 
 #include "i915_reg.h"
 #include "i915_utils.h"
+#include "intel_casf_regs.h"
 #include "intel_de.h"
 #include "intel_display_trace.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index e4bf484d4121..1520f34d1daa 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -209,6 +209,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_backlight.o \
 	i915-display/intel_bios.o \
 	i915-display/intel_bw.o \
+	i915-display/intel_casf.o \
 	i915-display/intel_cdclk.o \
 	i915-display/intel_cmtg.o \
 	i915-display/intel_color.o \
-- 
2.25.1

Re: [PATCH 03/10] drm/i915/display: Add strength and winsize register

[kernel test robot]

Hi Nemesa,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20250516]
[cannot apply to linus/master drm-intel/for-linux-next-fixes drm-tip/drm-tip v6.15-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Nemesa-Garg/drm-i915-display-Introduce-sharpness-strength-property/20250519-203316
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
patch link:    https://lore.kernel.org/r/20250519122644.3685679-4-nemesa.garg%40intel.com
patch subject: [PATCH 03/10] drm/i915/display: Add strength and winsize register
config: x86_64-randconfig-161-20250520 (https://download.01.org/0day-ci/archive/20250520/202505201824.ifVWlBHl-lkp@intel.com/config)
compiler: clang version 20.1.2 (https://github.com/llvm/llvm-project 58df0ef89dd64126512e4ee27b4ac3fd8ddf6247)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505201824.ifVWlBHl-lkp@intel.com/

New smatch warnings:
drivers/gpu/drm/i915/display/intel_casf.c:52 intel_casf_compute_win_size() warn: always true condition '(total_pixels <= (1920 * 1080)) => (0-u16max <= 2073600)'

Old smatch warnings:
drivers/gpu/drm/i915/display/intel_casf.c:54 intel_casf_compute_win_size() warn: always true condition '(total_pixels <= (3840 * 2160)) => (0-u16max <= 8294400)'

vim +52 drivers/gpu/drm/i915/display/intel_casf.c

    46	
    47	static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
    48	{
    49		const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
    50		u16 total_pixels = mode->hdisplay * mode->vdisplay;
    51	
  > 52		if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
    53			crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3;
    54		else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
    55			crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5;
    56		else
    57			crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7;
    58	}
    59	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 03/10] drm/i915/display: Add strength and winsize register

[kernel test robot]

Hi Nemesa,

kernel test robot noticed the following build errors:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20250522]
[cannot apply to linus/master drm-intel/for-linux-next-fixes drm-tip/drm-tip v6.15-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Nemesa-Garg/drm-i915-display-Introduce-sharpness-strength-property/20250519-203316
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
patch link:    https://lore.kernel.org/r/20250519122644.3685679-4-nemesa.garg%40intel.com
patch subject: [PATCH 03/10] drm/i915/display: Add strength and winsize register
config: i386-randconfig-004-20250522 (https://download.01.org/0day-ci/archive/20250523/202505230242.YWyBlwSE-lkp@intel.com/config)
compiler: clang version 20.1.2 (https://github.com/llvm/llvm-project 58df0ef89dd64126512e4ee27b4ac3fd8ddf6247)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250523/202505230242.YWyBlwSE-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505230242.YWyBlwSE-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/i915/display/intel_casf.c:52:19: error: result of comparison of constant 2073600 with expression of type 'u16' (aka 'unsigned short') is always true [-Werror,-Wtautological-constant-out-of-range-compare]
      52 |         if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
         |             ~~~~~~~~~~~~ ^  ~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_casf.c:54:24: error: result of comparison of constant 8294400 with expression of type 'u16' (aka 'unsigned short') is always true [-Werror,-Wtautological-constant-out-of-range-compare]
      54 |         else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
         |                  ~~~~~~~~~~~~ ^  ~~~~~~~~~~~~~~~~~~~~~~~~~~~
   2 errors generated.


vim +52 drivers/gpu/drm/i915/display/intel_casf.c

    46	
    47	static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
    48	{
    49		const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
    50		u16 total_pixels = mode->hdisplay * mode->vdisplay;
    51	
  > 52		if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
    53			crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3;
    54		else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
    55			crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5;
    56		else
    57			crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7;
    58	}
    59	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[PATCH 03/10] drm/i915/display: Add strength and winsize register

[Nemesa Garg]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=a, Size: 8984 bytes --]

The sharpness strength value is determined by user input,
while the winsize is based on the resolution.
The casf_enable flag should be set if the platform supports
sharpness adjustments and the user API strength is not zero.
Once sharpness is enabled, update the strength bit of the
register whenever the user changes the strength value,
as the enable bit and winsize bit remain constant.

v2: Introduce get_config for casf[Ankit]
v3: Replace 0 with FILTER_STRENGTH_MASK[Ankit]
v4: After updating strength add win_sz register
v5: Replace u16 with u32 for total_pixel

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_casf.c     | 109 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_casf.h     |  17 +++
 .../gpu/drm/i915/display/intel_casf_regs.h    |  22 ++++
 .../drm/i915/display/intel_display_types.h    |   7 ++
 drivers/gpu/drm/i915/display/skl_scaler.c     |   1 +
 drivers/gpu/drm/xe/Makefile                   |   1 +
 7 files changed, 158 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf_regs.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 853543443072..56b5aec496f3 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -227,6 +227,7 @@ i915-y += \
 	display/intel_bios.o \
 	display/intel_bo.o \
 	display/intel_bw.o \
+	display/intel_casf.o \
 	display/intel_cdclk.o \
 	display/intel_cmtg.o \
 	display/intel_color.o \
diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
new file mode 100644
index 000000000000..6a877c7c76fa
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ *
+ */
+
+#include <drm/drm_print.h>
+
+#include "i915_reg.h"
+#include "intel_casf.h"
+#include "intel_casf_regs.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+
+#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
+#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)
+
+/**
+ * DOC: Content Adaptive Sharpness Filter (CASF)
+ *
+ * Starting from LNL the display engine supports an
+ * adaptive sharpening filter, enhancing the image
+ * quality. The display hardware utilizes the second
+ * pipe scaler for implementing CASF.
+ * If sharpness is being enabled then pipe scaling
+ * cannot be used.
+ * This filter operates on a region of pixels based
+ * on the tap size. Coefficients are used to generate
+ * an alpha value which blends the sharpened image to
+ * original image.
+ */
+
+void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	int win_size;
+
+	intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), FILTER_STRENGTH_MASK,
+		     FILTER_STRENGTH(crtc_state->hw.casf_params.strength));
+
+	win_size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, 1));
+
+	intel_de_write_fw(display, SKL_PS_WIN_SZ(crtc->pipe, 1), win_size);
+}
+
+static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
+{
+	const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
+	u32 total_pixels = mode->hdisplay * mode->vdisplay;
+
+	if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3;
+	else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5;
+	else
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7;
+}
+
+int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!HAS_CASF(display))
+		return 0;
+
+	if (crtc_state->uapi.sharpness_strength == 0) {
+		crtc_state->hw.casf_params.casf_enable = false;
+		crtc_state->hw.casf_params.strength = 0;
+		return 0;
+	}
+
+	crtc_state->hw.casf_params.casf_enable = true;
+
+	/*
+	 * HW takes a value in form (1.0 + strength) in 4.4 fixed format.
+	 * Strength is from 0.0-14.9375 ie from 0-239.
+	 * User can give value from 0-255 but is clamped to 239.
+	 * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
+	 * 6.3125 in 4.4 format is b01100101 which is equal to 101.
+	 * Also 85 + 16 = 101.
+	 */
+	crtc_state->hw.casf_params.strength =
+		min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
+
+	intel_casf_compute_win_size(crtc_state);
+
+	return 0;
+}
+
+void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	u32 sharp;
+
+	sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));
+	if (sharp & FILTER_EN) {
+		if (drm_WARN_ON(display->drm,
+				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16))
+			crtc_state->hw.casf_params.strength = 0;
+		else
+			crtc_state->hw.casf_params.strength =
+				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp);
+		crtc_state->hw.casf_params.casf_enable = true;
+		crtc_state->hw.casf_params.win_size =
+			REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h
new file mode 100644
index 000000000000..83523fe66c48
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_CASF_H__
+#define __INTEL_CASF_H__
+
+#include <linux/types.h>
+
+struct intel_crtc_state;
+
+int intel_casf_compute_config(struct intel_crtc_state *crtc_state);
+void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state);
+void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state);
+
+#endif /* __INTEL_CASF_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h
new file mode 100644
index 000000000000..c24ba281ae37
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_CASF_REGS_H__
+#define __INTEL_CASF_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _SHARPNESS_CTL_A               0x682B0
+#define _SHARPNESS_CTL_B               0x68AB0
+#define SHARPNESS_CTL(pipe)            _MMIO_PIPE(pipe, _SHARPNESS_CTL_A, _SHARPNESS_CTL_B)
+#define   FILTER_EN                    REG_BIT(31)
+#define   FILTER_STRENGTH_MASK         REG_GENMASK(15, 8)
+#define   FILTER_STRENGTH(x)           REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x))
+#define   FILTER_SIZE_MASK             REG_GENMASK(1, 0)
+#define   SHARPNESS_FILTER_SIZE_3X3    REG_FIELD_PREP(FILTER_SIZE_MASK, 0)
+#define   SHARPNESS_FILTER_SIZE_5X5    REG_FIELD_PREP(FILTER_SIZE_MASK, 1)
+#define   SHARPNESS_FILTER_SIZE_7X7    REG_FIELD_PREP(FILTER_SIZE_MASK, 2)
+
+#endif /* __INTEL_CASF_REGS__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8f8019d40d77..a4649669f538 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -943,6 +943,12 @@ struct intel_csc_matrix {
 	u16 postoff[3];
 };
 
+struct intel_casf {
+	u8 strength;
+	u8 win_size;
+	bool casf_enable;
+};
+
 void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val);
 
 typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val);
@@ -983,6 +989,7 @@ struct intel_crtc_state {
 		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
 		struct drm_display_mode mode, pipe_mode, adjusted_mode;
 		enum drm_scaling_filter scaling_filter;
+		struct intel_casf casf_params;
 	} hw;
 
 	/* actual state of LUTs */
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 4cc55f4e1f9f..12d5fe42fb3a 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -6,6 +6,7 @@
 #include <drm/drm_print.h>
 
 #include "i915_utils.h"
+#include "intel_casf_regs.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_trace.h"
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index a6c42485149a..5fedaf0adeef 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -220,6 +220,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_backlight.o \
 	i915-display/intel_bios.o \
 	i915-display/intel_bw.o \
+	i915-display/intel_casf.o \
 	i915-display/intel_cdclk.o \
 	i915-display/intel_cmtg.o \
 	i915-display/intel_color.o \
-- 
2.25.1

[PATCH 03/10] drm/i915/display: Add strength and winsize register

[Nemesa Garg]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 8945 bytes --]

The sharpness strength value is determined by user input,
while the winsize is based on the resolution.
The casf_enable flag should be set if the platform supports
sharpness adjustments and the user API strength is not zero.
Once sharpness is enabled, update the strength bit of the
register whenever the user changes the strength value,
as the enable bit and winsize bit remain constant.

v2: Introduce get_config for casf[Ankit]
v3: Replace 0 with FILTER_STRENGTH_MASK[Ankit]
v4: After updating strength add win_sz register
v5: Replace u16 with u32 for total_pixel

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_casf.c     | 109 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_casf.h     |  17 +++
 .../gpu/drm/i915/display/intel_casf_regs.h    |  22 ++++
 .../drm/i915/display/intel_display_types.h    |   7 ++
 drivers/gpu/drm/i915/display/skl_scaler.c     |   1 +
 drivers/gpu/drm/xe/Makefile                   |   1 +
 7 files changed, 158 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf_regs.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 853543443072..56b5aec496f3 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -227,6 +227,7 @@ i915-y += \
 	display/intel_bios.o \
 	display/intel_bo.o \
 	display/intel_bw.o \
+	display/intel_casf.o \
 	display/intel_cdclk.o \
 	display/intel_cmtg.o \
 	display/intel_color.o \
diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
new file mode 100644
index 000000000000..6a877c7c76fa
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ *
+ */
+
+#include <drm/drm_print.h>
+
+#include "i915_reg.h"
+#include "intel_casf.h"
+#include "intel_casf_regs.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+
+#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
+#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)
+
+/**
+ * DOC: Content Adaptive Sharpness Filter (CASF)
+ *
+ * Starting from LNL the display engine supports an
+ * adaptive sharpening filter, enhancing the image
+ * quality. The display hardware utilizes the second
+ * pipe scaler for implementing CASF.
+ * If sharpness is being enabled then pipe scaling
+ * cannot be used.
+ * This filter operates on a region of pixels based
+ * on the tap size. Coefficients are used to generate
+ * an alpha value which blends the sharpened image to
+ * original image.
+ */
+
+void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	int win_size;
+
+	intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), FILTER_STRENGTH_MASK,
+		     FILTER_STRENGTH(crtc_state->hw.casf_params.strength));
+
+	win_size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, 1));
+
+	intel_de_write_fw(display, SKL_PS_WIN_SZ(crtc->pipe, 1), win_size);
+}
+
+static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
+{
+	const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
+	u32 total_pixels = mode->hdisplay * mode->vdisplay;
+
+	if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3;
+	else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5;
+	else
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7;
+}
+
+int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!HAS_CASF(display))
+		return 0;
+
+	if (crtc_state->uapi.sharpness_strength == 0) {
+		crtc_state->hw.casf_params.casf_enable = false;
+		crtc_state->hw.casf_params.strength = 0;
+		return 0;
+	}
+
+	crtc_state->hw.casf_params.casf_enable = true;
+
+	/*
+	 * HW takes a value in form (1.0 + strength) in 4.4 fixed format.
+	 * Strength is from 0.0-14.9375 ie from 0-239.
+	 * User can give value from 0-255 but is clamped to 239.
+	 * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
+	 * 6.3125 in 4.4 format is b01100101 which is equal to 101.
+	 * Also 85 + 16 = 101.
+	 */
+	crtc_state->hw.casf_params.strength =
+		min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
+
+	intel_casf_compute_win_size(crtc_state);
+
+	return 0;
+}
+
+void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	u32 sharp;
+
+	sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));
+	if (sharp & FILTER_EN) {
+		if (drm_WARN_ON(display->drm,
+				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16))
+			crtc_state->hw.casf_params.strength = 0;
+		else
+			crtc_state->hw.casf_params.strength =
+				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp);
+		crtc_state->hw.casf_params.casf_enable = true;
+		crtc_state->hw.casf_params.win_size =
+			REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h
new file mode 100644
index 000000000000..83523fe66c48
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_CASF_H__
+#define __INTEL_CASF_H__
+
+#include <linux/types.h>
+
+struct intel_crtc_state;
+
+int intel_casf_compute_config(struct intel_crtc_state *crtc_state);
+void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state);
+void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state);
+
+#endif /* __INTEL_CASF_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h
new file mode 100644
index 000000000000..c24ba281ae37
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_CASF_REGS_H__
+#define __INTEL_CASF_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _SHARPNESS_CTL_A               0x682B0
+#define _SHARPNESS_CTL_B               0x68AB0
+#define SHARPNESS_CTL(pipe)            _MMIO_PIPE(pipe, _SHARPNESS_CTL_A, _SHARPNESS_CTL_B)
+#define   FILTER_EN                    REG_BIT(31)
+#define   FILTER_STRENGTH_MASK         REG_GENMASK(15, 8)
+#define   FILTER_STRENGTH(x)           REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x))
+#define   FILTER_SIZE_MASK             REG_GENMASK(1, 0)
+#define   SHARPNESS_FILTER_SIZE_3X3    REG_FIELD_PREP(FILTER_SIZE_MASK, 0)
+#define   SHARPNESS_FILTER_SIZE_5X5    REG_FIELD_PREP(FILTER_SIZE_MASK, 1)
+#define   SHARPNESS_FILTER_SIZE_7X7    REG_FIELD_PREP(FILTER_SIZE_MASK, 2)
+
+#endif /* __INTEL_CASF_REGS__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 35596f3921e8..b62a07236913 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -943,6 +943,12 @@ struct intel_csc_matrix {
 	u16 postoff[3];
 };
 
+struct intel_casf {
+	u8 strength;
+	u8 win_size;
+	bool casf_enable;
+};
+
 struct intel_crtc_state {
 	/*
 	 * uapi (drm) state. This is the software state shown to userspace.
@@ -979,6 +985,7 @@ struct intel_crtc_state {
 		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
 		struct drm_display_mode mode, pipe_mode, adjusted_mode;
 		enum drm_scaling_filter scaling_filter;
+		struct intel_casf casf_params;
 	} hw;
 
 	/* actual state of LUTs */
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index cd7ebbeb9508..375b8c644923 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -6,6 +6,7 @@
 #include <drm/drm_print.h>
 
 #include "i915_utils.h"
+#include "intel_casf_regs.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_trace.h"
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 8e0c3412a757..5e10377b15c2 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -223,6 +223,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_backlight.o \
 	i915-display/intel_bios.o \
 	i915-display/intel_bw.o \
+	i915-display/intel_casf.o \
 	i915-display/intel_cdclk.o \
 	i915-display/intel_cmtg.o \
 	i915-display/intel_color.o \
-- 
2.25.1

[PATCH 00/10] Introduce drm sharpness property

[Nemesa Garg]

 Many a times images are blurred or upscaled content is also not as
crisp as original rendered image. Traditional sharpening techniques often
apply a uniform level of enhancement across entire image, which sometimes
result in over-sharpening of some areas and potential loss of natural details.

Intel has come up with Display Engine based adaptive sharpening filter
with minimal power and performance impact. From LNL onwards, the Display
hardware can use one of the pipe scaler for adaptive sharpness filter.
This can be used for both gaming and non-gaming use cases like photos,
image viewing. It works on a region of pixels depending on the tap size.

This is an attempt to introduce an adaptive sharpness solution which
helps in improving the image quality. For this new CRTC property is added.
The user can set this property with desired sharpness strength value with
0-255. A value of 1 representing minimum sharpening strength and 255
representing maximum sharpness strength. A strength value of 0 means no
sharpening or sharpening feature disabled.
It works on a region of pixels depending on the tap size. The coefficients
are used to generate an alpha value which is used to blend the sharpened
image to original image.

Middleware MR link: https://gitlab.gnome.org/GNOME/mutter/-/merge_requests/3665
IGT patchwork link: https://patchwork.freedesktop.org/series/130218/

Continuing discussions from:  https://patchwork.freedesktop.org/series/129888/

https://invent.kde.org/plasma/kwin/-/merge_requests/7689
Got ack from kwin maintainer on the UAPI patch.

Minor changes in patch 3, 4 and 5 hence require rb.

Nemesa Garg (10):
  drm/drm_crtc: Introduce sharpness strength property
  drm/i915/display: Introduce HAS_CASF for sharpness support
  drm/i915/display: Add strength and winsize register
  drm/i915/display: Add filter lut values
  drm/i915/display: Compute the scaler coefficients
  drm/i915/display: Add and compute scaler parameter
  drm/i915/display: Configure the second scaler
  drm/i915/display: Set and get the casf config
  drm/i915/display: Enable/disable casf
  drm/i915/display: Expose sharpness strength property

 drivers/gpu/drm/drm_atomic_uapi.c             |   4 +
 drivers/gpu/drm/drm_crtc.c                    |  35 +++
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_casf.c     | 293 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_casf.h     |  24 ++
 .../gpu/drm/i915/display/intel_casf_regs.h    |  33 ++
 drivers/gpu/drm/i915/display/intel_crtc.c     |   3 +
 .../drm/i915/display/intel_crtc_state_dump.c  |   5 +
 drivers/gpu/drm/i915/display/intel_display.c  |  37 ++-
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |  15 +
 drivers/gpu/drm/i915/display/skl_scaler.c     |  91 +++++-
 drivers/gpu/drm/i915/display/skl_scaler.h     |   2 +
 drivers/gpu/drm/xe/Makefile                   |   1 +
 include/drm/drm_crtc.h                        |  18 ++
 15 files changed, 550 insertions(+), 13 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf_regs.h

-- 
2.25.1

[PATCH 01/10] drm/drm_crtc: Introduce sharpness strength property

[Nemesa Garg]

Introduce a new crtc property "SHARPNESS_STRENGTH" that allows
the user to set the intensity so as to get the sharpness effect.
The value of this property can be set from 0-255.
It is useful in scenario when the output is blurry and user
want to sharpen the pixels. User can increase/decrease the
sharpness level depending on the content displayed.

v2: Rename crtc property variable [Arun]
    Add modeset detail in uapi doc[Uma]
v3: Fix build issue
v4: Modify the subject line[Ankit]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Tested-by: Adarsh G M <Adarsh.g.m@intel.com>
Acked-by: Simona Vetter <simona.vetter@ffwll.ch>
---
 drivers/gpu/drm/drm_atomic_uapi.c |  4 ++++
 drivers/gpu/drm/drm_crtc.c        | 35 +++++++++++++++++++++++++++++++
 include/drm/drm_crtc.h            | 18 ++++++++++++++++
 3 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
index 85dbdaa4a2e2..b2cb5ae5a139 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -419,6 +419,8 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
 		set_out_fence_for_crtc(state->state, crtc, fence_ptr);
 	} else if (property == crtc->scaling_filter_property) {
 		state->scaling_filter = val;
+	} else if (property == crtc->sharpness_strength_property) {
+		state->sharpness_strength = val;
 	} else if (crtc->funcs->atomic_set_property) {
 		return crtc->funcs->atomic_set_property(crtc, state, property, val);
 	} else {
@@ -456,6 +458,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
 		*val = 0;
 	else if (property == crtc->scaling_filter_property)
 		*val = state->scaling_filter;
+	else if (property == crtc->sharpness_strength_property)
+		*val = state->sharpness_strength;
 	else if (crtc->funcs->atomic_get_property)
 		return crtc->funcs->atomic_get_property(crtc, state, property, val);
 	else {
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 46655339003d..a7797d260f1e 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -229,6 +229,25 @@ struct dma_fence *drm_crtc_create_fence(struct drm_crtc *crtc)
  * 		Driver's default scaling filter
  * 	Nearest Neighbor:
  * 		Nearest Neighbor scaling filter
+ * SHARPNESS_STRENGTH:
+ *	Atomic property for setting the sharpness strength/intensity by userspace.
+ *
+ *	The value of this property is set as an integer value ranging
+ *	from 0 - 255 where:
+ *
+ *	0: Sharpness feature is disabled(default value).
+ *
+ *	1: Minimum sharpness.
+ *
+ *	255: Maximum sharpness.
+ *
+ *	User can gradually increase or decrease the sharpness level and can
+ *	set the optimum value depending on content.
+ *	This value will be passed to kernel through the UAPI.
+ *	The setting of this property does not require modeset.
+ *	The sharpness effect takes place post blending on the final composed output.
+ *	If the feature is disabled, the content remains same without any sharpening effect
+ *	and when this feature is applied, it enhances the clarity of the content.
  */
 
 __printf(6, 0)
@@ -940,6 +959,22 @@ int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc,
 }
 EXPORT_SYMBOL(drm_crtc_create_scaling_filter_property);
 
+int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_property *prop =
+		drm_property_create_range(dev, 0, "SHARPNESS_STRENGTH", 0, 255);
+
+	if (!prop)
+		return -ENOMEM;
+
+	crtc->sharpness_strength_property = prop;
+	drm_object_attach_property(&crtc->base, prop, 0);
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_crtc_create_sharpness_strength_property);
+
 /**
  * drm_crtc_in_clone_mode - check if the given CRTC state is in clone mode
  *
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index caa56e039da2..bcdbde681986 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -317,6 +317,17 @@ struct drm_crtc_state {
 	 */
 	enum drm_scaling_filter scaling_filter;
 
+	/**
+	 * @sharpness_strength:
+	 *
+	 * Used by the user to set the sharpness intensity.
+	 * The value ranges from 0-255.
+	 * Default value is 0 which disable the sharpness feature.
+	 * Any value greater than 0 enables sharpening with the
+	 * specified strength.
+	 */
+	u8 sharpness_strength;
+
 	/**
 	 * @event:
 	 *
@@ -1088,6 +1099,12 @@ struct drm_crtc {
 	 */
 	struct drm_property *scaling_filter_property;
 
+	/**
+	 * @sharpness_strength_property: property to apply
+	 * the intensity of the sharpness requested.
+	 */
+	struct drm_property *sharpness_strength_property;
+
 	/**
 	 * @state:
 	 *
@@ -1324,4 +1341,5 @@ static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev,
 int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc,
 					    unsigned int supported_filters);
 bool drm_crtc_in_clone_mode(struct drm_crtc_state *crtc_state);
+int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc);
 #endif /* __DRM_CRTC_H__ */
-- 
2.25.1

[PATCH 02/10] drm/i915/display: Introduce HAS_CASF for sharpness support

[Nemesa Garg]

Add HAS_CASF macro to check whether platform supports
the content adaptive sharpness capability or not.

v2: Update commit message[Ankit]
v3: Remove \n from middle[Jani]
v4: Remove the logging part

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 0e062753cf9b..e91907b34d43 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -146,6 +146,7 @@ struct intel_display_platforms {
 #define HAS_ASYNC_FLIPS(__display)	(DISPLAY_VER(__display) >= 5)
 #define HAS_AS_SDP(__display)		(DISPLAY_VER(__display) >= 13)
 #define HAS_BIGJOINER(__display)	(DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))
+#define HAS_CASF(__display)		(DISPLAY_VER(__display) >= 20)
 #define HAS_CDCLK_CRAWL(__display)	(DISPLAY_INFO(__display)->has_cdclk_crawl)
 #define HAS_CDCLK_SQUASH(__display)	(DISPLAY_INFO(__display)->has_cdclk_squash)
 #define HAS_CMRR(__display)		(DISPLAY_VER(__display) >= 20)
-- 
2.25.1

[PATCH 03/10] drm/i915/display: Add strength and winsize register

[Nemesa Garg]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 9694 bytes --]

The sharpness strength value is determined by user input,
while the winsize is based on the resolution.
The casf_enable flag should be set if the platform supports
sharpness adjustments and the user API strength is not zero.
Once sharpness is enabled, update the strength bit of the
register whenever the user changes the strength value,
as the enable bit and winsize bit remain constant.

v2: Introduce get_config for casf[Ankit]
v3: Replace 0 with FILTER_STRENGTH_MASK[Ankit]
v4: After updating strength add win_sz register
v5: Replace u16 with u32 for total_pixel
v6: Add the logging part here

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_casf.c     | 110 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_casf.h     |  17 +++
 .../gpu/drm/i915/display/intel_casf_regs.h    |  22 ++++
 .../drm/i915/display/intel_crtc_state_dump.c  |   5 +
 .../drm/i915/display/intel_display_types.h    |   7 ++
 drivers/gpu/drm/i915/display/skl_scaler.c     |   1 +
 drivers/gpu/drm/xe/Makefile                   |   1 +
 8 files changed, 164 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_casf_regs.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 78a45a6681df..2aeb1da455d7 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -228,6 +228,7 @@ i915-y += \
 	display/intel_bios.o \
 	display/intel_bo.o \
 	display/intel_bw.o \
+	display/intel_casf.o \
 	display/intel_cdclk.o \
 	display/intel_cmtg.o \
 	display/intel_color.o \
diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
new file mode 100644
index 000000000000..4597e576b6dc
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ *
+ */
+
+#include <drm/drm_print.h>
+
+#include "i915_reg.h"
+#include "intel_casf.h"
+#include "intel_casf_regs.h"
+#include "intel_de.h"
+#include "intel_display_regs.h"
+#include "intel_display_types.h"
+
+#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
+#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)
+
+/**
+ * DOC: Content Adaptive Sharpness Filter (CASF)
+ *
+ * Starting from LNL the display engine supports an
+ * adaptive sharpening filter, enhancing the image
+ * quality. The display hardware utilizes the second
+ * pipe scaler for implementing CASF.
+ * If sharpness is being enabled then pipe scaling
+ * cannot be used.
+ * This filter operates on a region of pixels based
+ * on the tap size. Coefficients are used to generate
+ * an alpha value which blends the sharpened image to
+ * original image.
+ */
+
+void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	int win_size;
+
+	intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), FILTER_STRENGTH_MASK,
+		     FILTER_STRENGTH(crtc_state->hw.casf_params.strength));
+
+	win_size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, 1));
+
+	intel_de_write_fw(display, SKL_PS_WIN_SZ(crtc->pipe, 1), win_size);
+}
+
+static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
+{
+	const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
+	u32 total_pixels = mode->hdisplay * mode->vdisplay;
+
+	if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3;
+	else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5;
+	else
+		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7;
+}
+
+int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!HAS_CASF(display))
+		return 0;
+
+	if (crtc_state->uapi.sharpness_strength == 0) {
+		crtc_state->hw.casf_params.casf_enable = false;
+		crtc_state->hw.casf_params.strength = 0;
+		return 0;
+	}
+
+	crtc_state->hw.casf_params.casf_enable = true;
+
+	/*
+	 * HW takes a value in form (1.0 + strength) in 4.4 fixed format.
+	 * Strength is from 0.0-14.9375 ie from 0-239.
+	 * User can give value from 0-255 but is clamped to 239.
+	 * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
+	 * 6.3125 in 4.4 format is b01100101 which is equal to 101.
+	 * Also 85 + 16 = 101.
+	 */
+	crtc_state->hw.casf_params.strength =
+		min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
+
+	intel_casf_compute_win_size(crtc_state);
+
+	return 0;
+}
+
+void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	u32 sharp;
+
+	sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));
+	if (sharp & FILTER_EN) {
+		if (drm_WARN_ON(display->drm,
+				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16))
+			crtc_state->hw.casf_params.strength = 0;
+		else
+			crtc_state->hw.casf_params.strength =
+				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp);
+		crtc_state->hw.casf_params.casf_enable = true;
+		crtc_state->hw.casf_params.win_size =
+			REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h
new file mode 100644
index 000000000000..83523fe66c48
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_CASF_H__
+#define __INTEL_CASF_H__
+
+#include <linux/types.h>
+
+struct intel_crtc_state;
+
+int intel_casf_compute_config(struct intel_crtc_state *crtc_state);
+void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state);
+void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state);
+
+#endif /* __INTEL_CASF_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h
new file mode 100644
index 000000000000..c24ba281ae37
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_CASF_REGS_H__
+#define __INTEL_CASF_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _SHARPNESS_CTL_A               0x682B0
+#define _SHARPNESS_CTL_B               0x68AB0
+#define SHARPNESS_CTL(pipe)            _MMIO_PIPE(pipe, _SHARPNESS_CTL_A, _SHARPNESS_CTL_B)
+#define   FILTER_EN                    REG_BIT(31)
+#define   FILTER_STRENGTH_MASK         REG_GENMASK(15, 8)
+#define   FILTER_STRENGTH(x)           REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x))
+#define   FILTER_SIZE_MASK             REG_GENMASK(1, 0)
+#define   SHARPNESS_FILTER_SIZE_3X3    REG_FIELD_PREP(FILTER_SIZE_MASK, 0)
+#define   SHARPNESS_FILTER_SIZE_5X5    REG_FIELD_PREP(FILTER_SIZE_MASK, 1)
+#define   SHARPNESS_FILTER_SIZE_7X7    REG_FIELD_PREP(FILTER_SIZE_MASK, 2)
+
+#endif /* __INTEL_CASF_REGS__ */
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 0c7f91046996..ae2f4a660ad5 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -373,6 +373,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 
 	intel_vdsc_state_dump(&p, 0, pipe_config);
 
+	drm_printf(&p, "sharpness strength: %d, sharpness tap size: %d, sharpness enable: %d\n",
+		   pipe_config->hw.casf_params.strength,
+		   pipe_config->hw.casf_params.win_size,
+		   pipe_config->hw.casf_params.casf_enable);
+
 dump_planes:
 	if (!state)
 		return;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 358ab922d7a7..a9642641f702 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -946,6 +946,12 @@ struct intel_csc_matrix {
 	u16 postoff[3];
 };
 
+struct intel_casf {
+	u8 strength;
+	u8 win_size;
+	bool casf_enable;
+};
+
 struct intel_crtc_state {
 	/*
 	 * uapi (drm) state. This is the software state shown to userspace.
@@ -982,6 +988,7 @@ struct intel_crtc_state {
 		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
 		struct drm_display_mode mode, pipe_mode, adjusted_mode;
 		enum drm_scaling_filter scaling_filter;
+		struct intel_casf casf_params;
 	} hw;
 
 	/* actual state of LUTs */
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index c6cccf170ff1..19aeb8d5b79c 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -6,6 +6,7 @@
 #include <drm/drm_print.h>
 
 #include "i915_utils.h"
+#include "intel_casf_regs.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_trace.h"
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index d9c6cf0f189e..90a118bc77de 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -230,6 +230,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_backlight.o \
 	i915-display/intel_bios.o \
 	i915-display/intel_bw.o \
+	i915-display/intel_casf.o \
 	i915-display/intel_cdclk.o \
 	i915-display/intel_cmtg.o \
 	i915-display/intel_color.o \
-- 
2.25.1

[PATCH 04/10] drm/i915/display: Add filter lut values

[Nemesa Garg]

Add the register bits related to filter lut values.
These values are golden values and these value has
to be loaded one time while enabling the casf.

v2: update commit message[Ankit]
v3: Make filter_load fn name same[Jani]
v4: Define the filter macros here

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_casf.c     | 47 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_casf.h     |  3 ++
 .../gpu/drm/i915/display/intel_casf_regs.h    | 11 +++++
 3 files changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
index 4597e576b6dc..45bc67377d21 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.c
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -16,6 +16,13 @@
 #define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
 #define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)
 
+#define FILTER_COEFF_0_125 125
+#define FILTER_COEFF_0_25 250
+#define FILTER_COEFF_0_5 500
+#define FILTER_COEFF_1_0 1000
+#define FILTER_COEFF_0_0 0
+#define SET_POSITIVE_SIGN(x) ((x) & (~SIGN))
+
 /**
  * DOC: Content Adaptive Sharpness Filter (CASF)
  *
@@ -31,6 +38,46 @@
  * original image.
  */
 
+/* Default LUT values to be loaded one time. */
+static const u16 sharpness_lut[] = {
+	4095, 2047, 1364, 1022, 816, 678, 579,
+	504, 444, 397, 357, 323, 293, 268, 244, 224,
+	204, 187, 170, 154, 139, 125, 111, 98, 85,
+	73, 60, 48, 36, 24, 12, 0
+};
+
+const u16 filtercoeff_1[] = {
+	FILTER_COEFF_0_0, FILTER_COEFF_0_0, FILTER_COEFF_0_5,
+	FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_0,
+	FILTER_COEFF_0_0,
+};
+
+const u16 filtercoeff_2[] = {
+	FILTER_COEFF_0_0, FILTER_COEFF_0_25, FILTER_COEFF_0_5,
+	FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25,
+	FILTER_COEFF_0_0,
+};
+
+const u16 filtercoeff_3[] = {
+	FILTER_COEFF_0_125, FILTER_COEFF_0_25, FILTER_COEFF_0_5,
+	FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25,
+	FILTER_COEFF_0_125,
+};
+
+void intel_casf_filter_lut_load(struct intel_crtc *crtc,
+				const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	int i;
+
+	intel_de_write(display, SHRPLUT_INDEX(crtc->pipe),
+		       INDEX_AUTO_INCR | INDEX_VALUE(0));
+
+	for (i = 0; i < ARRAY_SIZE(sharpness_lut); i++)
+		intel_de_write(display, SHRPLUT_DATA(crtc->pipe),
+			       sharpness_lut[i]);
+}
+
 void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h
index 83523fe66c48..3edbc3ad51cf 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.h
+++ b/drivers/gpu/drm/i915/display/intel_casf.h
@@ -9,9 +9,12 @@
 #include <linux/types.h>
 
 struct intel_crtc_state;
+struct intel_crtc;
 
 int intel_casf_compute_config(struct intel_crtc_state *crtc_state);
 void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state);
 void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state);
+void intel_casf_filter_lut_load(struct intel_crtc *crtc,
+				const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CASF_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h
index c24ba281ae37..b96950a48335 100644
--- a/drivers/gpu/drm/i915/display/intel_casf_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h
@@ -19,4 +19,15 @@
 #define   SHARPNESS_FILTER_SIZE_5X5    REG_FIELD_PREP(FILTER_SIZE_MASK, 1)
 #define   SHARPNESS_FILTER_SIZE_7X7    REG_FIELD_PREP(FILTER_SIZE_MASK, 2)
 
+#define _SHRPLUT_DATA_A                        0x682B8
+#define _SHRPLUT_DATA_B                        0x68AB8
+#define SHRPLUT_DATA(pipe)             _MMIO_PIPE(pipe, _SHRPLUT_DATA_A, _SHRPLUT_DATA_B)
+
+#define _SHRPLUT_INDEX_A               0x682B4
+#define _SHRPLUT_INDEX_B               0x68AB4
+#define SHRPLUT_INDEX(pipe)            _MMIO_PIPE(pipe, _SHRPLUT_INDEX_A, _SHRPLUT_INDEX_B)
+#define   INDEX_AUTO_INCR              REG_BIT(10)
+#define   INDEX_VALUE_MASK             REG_GENMASK(4, 0)
+#define   INDEX_VALUE(x)               REG_FIELD_PREP(INDEX_VALUE_MASK, (x))
+
 #endif /* __INTEL_CASF_REGS__ */
-- 
2.25.1

[PATCH 05/10] drm/i915/display: Compute the scaler coefficients

[Nemesa Garg]

The sharpness property requires the use of one of the scaler
so need to set the sharpness scaler coefficient values.
These values are based on experiments and vary for different
tap value/win size. These values are normalized by taking the
sum of all values and then dividing each value with a sum.

v2: Fix ifndef header naming issue reported by kernel test robot
v3: Rename file name[Arun]
    Replace array size number with macro[Arun]
v4: Correct the register format[Jani]
    Add brief comment and expalin about file[Jani]
    Remove coefficient value from crtc_state[Jani]
v5: Fix build issue
v6: Add new function for writing coefficients[Ankit]
v7: Add cooments and add a scaler id check [Ankit]
v8: Remove casf_enable from here[Ankit]
v9: Removed REG and use shift operator[Jani]
v10: Introduce the casf_enable function
     Remove filter macros from here

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_casf.c     | 102 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_casf.h     |   2 +
 .../drm/i915/display/intel_display_types.h    |   8 ++
 3 files changed, 112 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
index 45bc67377d21..63efba10d6f2 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.c
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -133,6 +133,8 @@ int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
 
 	intel_casf_compute_win_size(crtc_state);
 
+	intel_casf_scaler_compute_config(crtc_state);
+
 	return 0;
 }
 
@@ -155,3 +157,103 @@ void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
 			REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
 	}
 }
+
+static int casf_coeff_tap(int i)
+{
+	return i % SCALER_FILTER_NUM_TAPS;
+}
+
+static u32 casf_coeff(struct intel_crtc_state *crtc_state, int t)
+{
+	struct scaler_filter_coeff value;
+	u32 coeff;
+
+	value = crtc_state->hw.casf_params.coeff[t];
+	value.sign = 0;
+
+	coeff = value.sign << 15 | value.exp << 12 | value.mantissa << 3;
+	return coeff;
+}
+
+/*
+ * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
+ * To enable casf:  program scaler coefficients with the coeffients
+ * that are calculated and stored in hw.casf_params.coeff as per
+ * SCALER_COEFFICIENT_FORMAT
+ */
+static void intel_casf_write_coeff(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	int id = crtc_state->scaler_state.scaler_id;
+	int i;
+
+	if (id != 1) {
+		drm_WARN(display->drm, 0, "Second scaler not enabled\n");
+		return;
+	}
+
+	intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 0),
+			  PS_COEF_INDEX_AUTO_INC);
+
+	for (i = 0; i < 17 * SCALER_FILTER_NUM_TAPS; i += 2) {
+		u32 tmp;
+		int t;
+
+		t = casf_coeff_tap(i);
+		tmp = casf_coeff(crtc_state, t);
+
+		t = casf_coeff_tap(i + 1);
+		tmp |= casf_coeff(crtc_state, t) << 16;
+
+		intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 0),
+				  tmp);
+	}
+}
+
+static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff,
+					  u16 coefficient)
+{
+	if (coefficient < 25) {
+		coeff->mantissa = (coefficient * 2048) / 100;
+		coeff->exp = 3;
+	} else if (coefficient < 50) {
+		coeff->mantissa = (coefficient * 1024) / 100;
+		coeff->exp = 2;
+	} else if (coefficient < 100) {
+		coeff->mantissa = (coefficient * 512) / 100;
+		coeff->exp = 1;
+	} else {
+		coeff->mantissa = (coefficient * 256) / 100;
+		coeff->exp = 0;
+	}
+}
+
+void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state)
+{
+	const u16 *filtercoeff;
+	u16 filter_coeff[SCALER_FILTER_NUM_TAPS];
+	u16 sumcoeff = 0;
+	int i;
+
+	if (crtc_state->hw.casf_params.win_size == 0)
+		filtercoeff = filtercoeff_1;
+	else if (crtc_state->hw.casf_params.win_size == 1)
+		filtercoeff = filtercoeff_2;
+	else
+		filtercoeff = filtercoeff_3;
+
+	for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++)
+		sumcoeff += *(filtercoeff + i);
+
+	for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++) {
+		filter_coeff[i] = (*(filtercoeff + i) * 100 / sumcoeff);
+		convert_sharpness_coef_binary(&crtc_state->hw.casf_params.coeff[i],
+					      filter_coeff[i]);
+	}
+}
+
+void intel_casf_enable(struct intel_crtc_state *crtc_state)
+{
+	intel_casf_write_coeff(crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h
index 3edbc3ad51cf..ddd7e00ba52d 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.h
+++ b/drivers/gpu/drm/i915/display/intel_casf.h
@@ -16,5 +16,7 @@ void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state);
 void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state);
 void intel_casf_filter_lut_load(struct intel_crtc *crtc,
 				const struct intel_crtc_state *crtc_state);
+void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state);
+void intel_casf_enable(struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CASF_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a9642641f702..b03d94e6e96b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -946,7 +946,15 @@ struct intel_csc_matrix {
 	u16 postoff[3];
 };
 
+struct scaler_filter_coeff {
+	u16 sign;
+	u16 exp;
+	u16 mantissa;
+};
+
 struct intel_casf {
+#define SCALER_FILTER_NUM_TAPS 7
+	struct scaler_filter_coeff coeff[SCALER_FILTER_NUM_TAPS];
 	u8 strength;
 	u8 win_size;
 	bool casf_enable;
-- 
2.25.1

[PATCH 06/10] drm/i915/display: Add and compute scaler parameter

[Nemesa Garg]

Compute the values for second scaler for sharpness.
Fill the register bits corresponding to the scaler.

v1: Rename the title of patch [Ankit]
v2: Remove setup_casf from here[Ankit]
v3: Add skl_scaler_setup_casf in casf_enable

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_casf.c |  3 ++
 drivers/gpu/drm/i915/display/skl_scaler.c | 46 +++++++++++++++++++++++
 drivers/gpu/drm/i915/display/skl_scaler.h |  2 +
 3 files changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
index 63efba10d6f2..f1d158e02c9e 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.c
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -12,6 +12,7 @@
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
+#include "skl_scaler.h"
 
 #define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
 #define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)
@@ -256,4 +257,6 @@ void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state)
 void intel_casf_enable(struct intel_crtc_state *crtc_state)
 {
 	intel_casf_write_coeff(crtc_state);
+
+	skl_scaler_setup_casf(crtc_state);
 }
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 19aeb8d5b79c..33ad1dd16bb2 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -739,6 +739,52 @@ static void skl_scaler_setup_filter(struct intel_display *display,
 	}
 }
 
+#define CASF_SCALER_FILTER_SELECT \
+	(PS_FILTER_PROGRAMMED | \
+	PS_Y_VERT_FILTER_SELECT(0) | \
+	PS_Y_HORZ_FILTER_SELECT(0) | \
+	PS_UV_VERT_FILTER_SELECT(0) | \
+	PS_UV_HORZ_FILTER_SELECT(0))
+
+void skl_scaler_setup_casf(struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct intel_display *display = to_intel_display(crtc);
+	struct drm_display_mode *adjusted_mode =
+	&crtc_state->hw.adjusted_mode;
+	struct intel_crtc_scaler_state *scaler_state =
+		&crtc_state->scaler_state;
+	struct drm_rect src, dest;
+	int id, width, height;
+	int x = 0, y = 0;
+	enum pipe pipe = crtc->pipe;
+	u32 ps_ctrl;
+
+	width = adjusted_mode->crtc_hdisplay;
+	height = adjusted_mode->crtc_vdisplay;
+
+	drm_rect_init(&dest, x, y, width, height);
+
+	width = drm_rect_width(&dest);
+	height = drm_rect_height(&dest);
+	id = scaler_state->scaler_id;
+
+	drm_rect_init(&src, 0, 0,
+		      drm_rect_width(&crtc_state->pipe_src) << 16,
+		      drm_rect_height(&crtc_state->pipe_src) << 16);
+
+	trace_intel_pipe_scaler_update_arm(crtc, id, x, y, width, height);
+
+	ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |
+		  CASF_SCALER_FILTER_SELECT;
+
+	intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl);
+	intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id),
+			  PS_WIN_XPOS(x) | PS_WIN_YPOS(y));
+	intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id),
+			  PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height));
+}
+
 void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h
index 12a19016c5f6..f2256984a97e 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.h
+++ b/drivers/gpu/drm/i915/display/skl_scaler.h
@@ -36,6 +36,8 @@ void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
 
 void skl_scaler_get_config(struct intel_crtc_state *crtc_state);
 
+void skl_scaler_setup_casf(struct intel_crtc_state *crtc_state);
+
 enum drm_mode_status
 skl_scaler_mode_valid(struct intel_display *display,
 		      const struct drm_display_mode *mode,
-- 
2.25.1

[PATCH 07/10] drm/i915/display: Configure the second scaler

[Nemesa Garg]

Both sharpness and panel fitter use pipe scaler,
but only one can be enabled at a time. Furthermore
sharpness uses second scaler. So for CASF, check if
second scaler is available and make sure that only
either of panel fitter or sharpness is enabled at
a time.

v2: Add the panel fitting check before enabling sharpness
v3: Reframe commit message[Arun]
v4: Replace string based comparison with plane_state[Jani]
v5: Rebase
v6: Fix build issue
v7: Remove scaler id from verify_crtc_state[Ankit]
v8: Change the patch title. Add code comment.
    Move the config part in patch#6. [Ankit]
v9: Refactor the patch[Ankit]
v10: Modify the header of patch[Ankit]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_casf.c    |  8 +++++++
 drivers/gpu/drm/i915/display/intel_casf.h    |  1 +
 drivers/gpu/drm/i915/display/intel_display.c |  4 +++-
 drivers/gpu/drm/i915/display/skl_scaler.c    | 25 +++++++++++++++-----
 4 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
index f1d158e02c9e..3011a6c4b46b 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.c
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -159,6 +159,14 @@ void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
 	}
 }
 
+bool intel_casf_needs_scaler(const struct intel_crtc_state *crtc_state)
+{
+	if (crtc_state->hw.casf_params.casf_enable)
+		return true;
+
+	return false;
+}
+
 static int casf_coeff_tap(int i)
 {
 	return i % SCALER_FILTER_NUM_TAPS;
diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h
index ddd7e00ba52d..f59a8603eea4 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.h
+++ b/drivers/gpu/drm/i915/display/intel_casf.h
@@ -18,5 +18,6 @@ void intel_casf_filter_lut_load(struct intel_crtc *crtc,
 				const struct intel_crtc_state *crtc_state);
 void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state);
 void intel_casf_enable(struct intel_crtc_state *crtc_state);
+bool intel_casf_needs_scaler(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CASF_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 18b9baa96241..6c3f6207143c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -60,6 +60,7 @@
 #include "intel_audio.h"
 #include "intel_bo.h"
 #include "intel_bw.h"
+#include "intel_casf.h"
 #include "intel_cdclk.h"
 #include "intel_clock_gating.h"
 #include "intel_color.h"
@@ -4204,7 +4205,8 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 
 	if (DISPLAY_VER(display) >= 9) {
 		if (intel_crtc_needs_modeset(crtc_state) ||
-		    intel_crtc_needs_fastset(crtc_state)) {
+		    intel_crtc_needs_fastset(crtc_state) ||
+		    intel_casf_needs_scaler(crtc_state)) {
 			ret = skl_update_scaler_crtc(crtc_state);
 			if (ret)
 				return ret;
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 33ad1dd16bb2..9cab3f9dc147 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -6,6 +6,7 @@
 #include <drm/drm_print.h>
 
 #include "i915_utils.h"
+#include "intel_casf.h"
 #include "intel_casf_regs.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
@@ -283,7 +284,8 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
 				 drm_rect_width(&crtc_state->pipe_src),
 				 drm_rect_height(&crtc_state->pipe_src),
 				 width, height, NULL, 0,
-				 crtc_state->pch_pfit.enabled);
+				 crtc_state->pch_pfit.enabled ||
+				 intel_casf_needs_scaler(crtc_state));
 }
 
 /**
@@ -322,7 +324,9 @@ int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 }
 
 static int intel_allocate_scaler(struct intel_crtc_scaler_state *scaler_state,
-				 struct intel_crtc *crtc)
+				 struct intel_crtc *crtc,
+				 struct intel_plane_state *plane_state,
+				 bool casf_scaler)
 {
 	int i;
 
@@ -330,6 +334,10 @@ static int intel_allocate_scaler(struct intel_crtc_scaler_state *scaler_state,
 		if (scaler_state->scalers[i].in_use)
 			continue;
 
+		/* CASF needs second scaler */
+		if (!plane_state && casf_scaler && i != 1)
+			continue;
+
 		scaler_state->scalers[i].in_use = true;
 
 		return i;
@@ -380,7 +388,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state,
 				     int num_scalers_need, struct intel_crtc *crtc,
 				     const char *name, int idx,
 				     struct intel_plane_state *plane_state,
-				     int *scaler_id)
+				     int *scaler_id, bool casf_scaler)
 {
 	struct intel_display *display = to_intel_display(crtc);
 	struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
@@ -389,7 +397,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state,
 	int vscale = 0;
 
 	if (*scaler_id < 0)
-		*scaler_id = intel_allocate_scaler(scaler_state, crtc);
+		*scaler_id = intel_allocate_scaler(scaler_state, crtc, plane_state, casf_scaler);
 
 	if (drm_WARN(display->drm, *scaler_id < 0,
 		     "Cannot find scaler for %s:%d\n", name, idx))
@@ -521,10 +529,14 @@ static int setup_crtc_scaler(struct intel_atomic_state *state,
 	struct intel_crtc_scaler_state *scaler_state =
 		&crtc_state->scaler_state;
 
+	if (intel_casf_needs_scaler(crtc_state) && crtc_state->pch_pfit.enabled)
+		return -EINVAL;
+
 	return intel_atomic_setup_scaler(crtc_state,
 					 hweight32(scaler_state->scaler_users),
 					 crtc, "CRTC", crtc->base.base.id,
-					 NULL, &scaler_state->scaler_id);
+					 NULL, &scaler_state->scaler_id,
+					 intel_casf_needs_scaler(crtc_state));
 }
 
 static int setup_plane_scaler(struct intel_atomic_state *state,
@@ -559,7 +571,8 @@ static int setup_plane_scaler(struct intel_atomic_state *state,
 	return intel_atomic_setup_scaler(crtc_state,
 					 hweight32(scaler_state->scaler_users),
 					 crtc, "PLANE", plane->base.base.id,
-					 plane_state, &plane_state->scaler_id);
+					 plane_state, &plane_state->scaler_id,
+					 false);
 }
 
 /**
-- 
2.25.1

[PATCH 08/10] drm/i915/display: Set and get the casf config

[Nemesa Garg]

Set the configuration for CASF and capture it
in crtc_state and get the configuration by
reading back. Add the support to compare the
software and hardware state of CASF.

v2: Update subject[Ankit]
v3: Add the state compare[Ankit]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  7 +++++++
 drivers/gpu/drm/i915/display/skl_scaler.c    | 19 +++++++++++++------
 2 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6c3f6207143c..6a4d0fe4d6e5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4203,6 +4203,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 		return ret;
 	}
 
+	ret = intel_casf_compute_config(crtc_state);
+	if (ret)
+		return ret;
+
 	if (DISPLAY_VER(display) >= 9) {
 		if (intel_crtc_needs_modeset(crtc_state) ||
 		    intel_crtc_needs_fastset(crtc_state) ||
@@ -5265,6 +5269,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
 		PIPE_CONF_CHECK_I(pixel_rate);
+		PIPE_CONF_CHECK_BOOL(hw.casf_params.casf_enable);
+		PIPE_CONF_CHECK_I(hw.casf_params.win_size);
+		PIPE_CONF_CHECK_I(hw.casf_params.strength);
 
 		PIPE_CONF_CHECK_X(gamma_mode);
 		if (display->platform.cherryview)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 9cab3f9dc147..956b1f6cbaa5 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -981,16 +981,23 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
 			continue;
 
 		id = i;
-		crtc_state->pch_pfit.enabled = true;
+
+		/* Read CASF regs for second scaler */
+		if (HAS_CASF(display) && id == 1)
+			intel_casf_sharpness_get_config(crtc_state);
+
+		if (!crtc_state->hw.casf_params.casf_enable)
+			crtc_state->pch_pfit.enabled = true;
 
 		pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, i));
 		size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, i));
 
-		drm_rect_init(&crtc_state->pch_pfit.dst,
-			      REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
-			      REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
-			      REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
-			      REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));
+		if (!crtc_state->hw.casf_params.casf_enable)
+			drm_rect_init(&crtc_state->pch_pfit.dst,
+				      REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
+				      REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
+				      REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
+				      REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));
 
 		scaler_state->scalers[i].in_use = true;
 		break;
-- 
2.25.1

[PATCH 09/10] drm/i915/display: Enable/disable casf

[Nemesa Garg]

To enable or disable the sharpness check the
casf_enable flag. While enabling the sharpness
write the programmable coefficients, sharpness
register bits and also enable the scaler.
Load the filter lut value which needs to be done
one time while enabling the sharpness.

v2: Introduce casf_enable here[Ankit]
v3: Use is_disabling in casf_disabling[Ankit]
v4: Swap old_state and new_state param[Ankit]
v5: In disable fn move win_sz after sharpness_ctl.
v6: Add filter_lut_load in casf_enable

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_casf.c    | 23 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_casf.h    |  1 +
 drivers/gpu/drm/i915/display/intel_display.c | 26 ++++++++++++++++++++
 3 files changed, 50 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
index 3011a6c4b46b..5570c83f3890 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.c
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -264,7 +264,30 @@ void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state)
 
 void intel_casf_enable(struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	u32 sharpness_ctl;
+
+	intel_casf_filter_lut_load(crtc, crtc_state);
+
 	intel_casf_write_coeff(crtc_state);
 
+	sharpness_ctl = FILTER_EN | FILTER_STRENGTH(crtc_state->hw.casf_params.strength);
+
+	sharpness_ctl |= crtc_state->hw.casf_params.win_size;
+
+	intel_de_write(display, SHARPNESS_CTL(crtc->pipe), sharpness_ctl);
+
 	skl_scaler_setup_casf(crtc_state);
 }
+
+void intel_casf_disable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	intel_de_write(display, SKL_PS_CTRL(crtc->pipe, 1), 0);
+	intel_de_write(display, SKL_PS_WIN_POS(crtc->pipe, 1), 0);
+	intel_de_write(display, SHARPNESS_CTL(crtc->pipe), 0);
+	intel_de_write(display, SKL_PS_WIN_SZ(crtc->pipe, 1), 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h
index f59a8603eea4..6d820e2b5b21 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.h
+++ b/drivers/gpu/drm/i915/display/intel_casf.h
@@ -19,5 +19,6 @@ void intel_casf_filter_lut_load(struct intel_crtc *crtc,
 void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state);
 void intel_casf_enable(struct intel_crtc_state *crtc_state);
 bool intel_casf_needs_scaler(const struct intel_crtc_state *crtc_state);
+void intel_casf_disable(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CASF_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6a4d0fe4d6e5..d27366f9435c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -980,6 +980,24 @@ static bool audio_disabling(const struct intel_crtc_state *old_crtc_state,
 		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);
 }
 
+static bool intel_casf_enabling(const struct intel_crtc_state *new_crtc_state,
+				const struct intel_crtc_state *old_crtc_state)
+{
+	if (!new_crtc_state->hw.active)
+		return false;
+
+	return is_enabling(hw.casf_params.casf_enable, old_crtc_state, new_crtc_state);
+}
+
+static bool intel_casf_disabling(const struct intel_crtc_state *old_crtc_state,
+				 const struct intel_crtc_state *new_crtc_state)
+{
+	if (!new_crtc_state->hw.active)
+		return false;
+
+	return is_disabling(hw.casf_params.casf_enable, old_crtc_state, new_crtc_state);
+}
+
 #undef is_disabling
 #undef is_enabling
 
@@ -1135,6 +1153,9 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 	if (audio_disabling(old_crtc_state, new_crtc_state))
 		intel_encoders_audio_disable(state, crtc);
 
+	if (intel_casf_disabling(old_crtc_state, new_crtc_state))
+		intel_casf_disable(new_crtc_state);
+
 	intel_drrs_deactivate(old_crtc_state);
 
 	if (hsw_ips_pre_update(state, crtc))
@@ -6692,6 +6713,11 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
 			intel_vrr_set_transcoder_timings(new_crtc_state);
 	}
 
+	if (intel_casf_enabling(new_crtc_state, old_crtc_state))
+		intel_casf_enable(new_crtc_state);
+	else if (new_crtc_state->hw.casf_params.strength != old_crtc_state->hw.casf_params.strength)
+		intel_casf_update_strength(new_crtc_state);
+
 	intel_fbc_update(state, crtc);
 
 	drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF));
-- 
2.25.1

[PATCH 10/10] drm/i915/display: Expose sharpness strength property

[Nemesa Garg]

Expose the drm crtc sharpness strength property which will enable
or disable the sharpness/casf based on user input. With this user
can set/update the strength of the sharpness or casf filter.

v2: Update subject[Ankit]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index a187db6df2d3..4102087aee62 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -390,6 +390,9 @@ int intel_crtc_init(struct intel_display *display, enum pipe pipe)
 
 	drm_WARN_ON(display->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
 
+	if (HAS_CASF(display))
+		drm_crtc_create_sharpness_strength_property(&crtc->base);
+
 	return 0;
 
 fail:
-- 
2.25.1

✗ CI.checkpatch: warning for Introduce drm sharpness property

[Patchwork]

== Series Details ==

Series: Introduce drm sharpness property
URL   : https://patchwork.freedesktop.org/series/155103/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
fbd08a78c3a3bb17964db2a326514c69c1dca660
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit e836ef5f66196838b69caa44d6a2890530b13d6f
Author: Nemesa Garg <nemesa.garg@intel.com>
Date:   Fri Sep 26 17:07:28 2025 +0530

    drm/i915/display: Expose sharpness strength property
    
    Expose the drm crtc sharpness strength property which will enable
    or disable the sharpness/casf based on user input. With this user
    can set/update the strength of the sharpness or casf filter.
    
    v2: Update subject[Ankit]
    
    Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
    Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+ /mt/dim checkpatch d557b14c00c4ab027e66c1c7bf512cf479ff8c24 drm-intel
6b6fc8ef3224 drm/drm_crtc: Introduce sharpness strength property
159f7dc7c444 drm/i915/display: Introduce HAS_CASF for sharpness support
a84268a33d7d drm/i915/display: Add strength and winsize register
-:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#35: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 200 lines checked
2a8887cb8c44 drm/i915/display: Add filter lut values
4c196c436438 drm/i915/display: Compute the scaler coefficients
80810d92c644 drm/i915/display: Add and compute scaler parameter
1af159722ef2 drm/i915/display: Configure the second scaler
9d14de496152 drm/i915/display: Set and get the casf config
67d6a2523889 drm/i915/display: Enable/disable casf
e836ef5f6619 drm/i915/display: Expose sharpness strength property

✓ CI.KUnit: success for Introduce drm sharpness property

[Patchwork]

== Series Details ==

Series: Introduce drm sharpness property
URL   : https://patchwork.freedesktop.org/series/155103/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[12:57:24] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:57:28] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:57:57] Starting KUnit Kernel (1/1)...
[12:57:57] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:57:57] ================== guc_buf (11 subtests) ===================
[12:57:57] [PASSED] test_smallest
[12:57:57] [PASSED] test_largest
[12:57:57] [PASSED] test_granular
[12:57:57] [PASSED] test_unique
[12:57:57] [PASSED] test_overlap
[12:57:57] [PASSED] test_reusable
[12:57:57] [PASSED] test_too_big
[12:57:57] [PASSED] test_flush
[12:57:57] [PASSED] test_lookup
[12:57:57] [PASSED] test_data
[12:57:57] [PASSED] test_class
[12:57:57] ===================== [PASSED] guc_buf =====================
[12:57:57] =================== guc_dbm (7 subtests) ===================
[12:57:57] [PASSED] test_empty
[12:57:57] [PASSED] test_default
[12:57:57] ======================== test_size  ========================
[12:57:57] [PASSED] 4
[12:57:57] [PASSED] 8
[12:57:57] [PASSED] 32
[12:57:57] [PASSED] 256
[12:57:57] ==================== [PASSED] test_size ====================
[12:57:57] ======================= test_reuse  ========================
[12:57:57] [PASSED] 4
[12:57:57] [PASSED] 8
[12:57:57] [PASSED] 32
[12:57:57] [PASSED] 256
[12:57:57] =================== [PASSED] test_reuse ====================
[12:57:57] =================== test_range_overlap  ====================
[12:57:57] [PASSED] 4
[12:57:57] [PASSED] 8
[12:57:57] [PASSED] 32
[12:57:57] [PASSED] 256
[12:57:57] =============== [PASSED] test_range_overlap ================
[12:57:57] =================== test_range_compact  ====================
[12:57:57] [PASSED] 4
[12:57:57] [PASSED] 8
[12:57:57] [PASSED] 32
[12:57:57] [PASSED] 256
[12:57:57] =============== [PASSED] test_range_compact ================
[12:57:57] ==================== test_range_spare  =====================
[12:57:57] [PASSED] 4
[12:57:57] [PASSED] 8
[12:57:57] [PASSED] 32
[12:57:57] [PASSED] 256
[12:57:57] ================ [PASSED] test_range_spare =================
[12:57:57] ===================== [PASSED] guc_dbm =====================
[12:57:57] =================== guc_idm (6 subtests) ===================
[12:57:57] [PASSED] bad_init
[12:57:57] [PASSED] no_init
[12:57:57] [PASSED] init_fini
[12:57:57] [PASSED] check_used
[12:57:57] [PASSED] check_quota
[12:57:57] [PASSED] check_all
[12:57:57] ===================== [PASSED] guc_idm =====================
[12:57:57] ================== no_relay (3 subtests) ===================
[12:57:57] [PASSED] xe_drops_guc2pf_if_not_ready
[12:57:57] [PASSED] xe_drops_guc2vf_if_not_ready
[12:57:57] [PASSED] xe_rejects_send_if_not_ready
[12:57:57] ==================== [PASSED] no_relay =====================
[12:57:57] ================== pf_relay (14 subtests) ==================
[12:57:57] [PASSED] pf_rejects_guc2pf_too_short
[12:57:57] [PASSED] pf_rejects_guc2pf_too_long
[12:57:57] [PASSED] pf_rejects_guc2pf_no_payload
[12:57:57] [PASSED] pf_fails_no_payload
[12:57:57] [PASSED] pf_fails_bad_origin
[12:57:57] [PASSED] pf_fails_bad_type
[12:57:57] [PASSED] pf_txn_reports_error
[12:57:57] [PASSED] pf_txn_sends_pf2guc
[12:57:57] [PASSED] pf_sends_pf2guc
[12:57:57] [SKIPPED] pf_loopback_nop
[12:57:57] [SKIPPED] pf_loopback_echo
[12:57:57] [SKIPPED] pf_loopback_fail
[12:57:57] [SKIPPED] pf_loopback_busy
[12:57:57] [SKIPPED] pf_loopback_retry
[12:57:57] ==================== [PASSED] pf_relay =====================
[12:57:57] ================== vf_relay (3 subtests) ===================
[12:57:57] [PASSED] vf_rejects_guc2vf_too_short
[12:57:57] [PASSED] vf_rejects_guc2vf_too_long
[12:57:57] [PASSED] vf_rejects_guc2vf_no_payload
[12:57:57] ==================== [PASSED] vf_relay =====================
[12:57:57] ===================== lmtt (1 subtest) =====================
[12:57:57] ======================== test_ops  =========================
[12:57:57] [PASSED] 2-level
[12:57:57] [PASSED] multi-level
[12:57:57] ==================== [PASSED] test_ops =====================
[12:57:57] ====================== [PASSED] lmtt =======================
[12:57:57] ================= pf_service (11 subtests) =================
[12:57:57] [PASSED] pf_negotiate_any
[12:57:57] [PASSED] pf_negotiate_base_match
[12:57:57] [PASSED] pf_negotiate_base_newer
[12:57:57] [PASSED] pf_negotiate_base_next
[12:57:57] [SKIPPED] pf_negotiate_base_older
[12:57:57] [PASSED] pf_negotiate_base_prev
[12:57:57] [PASSED] pf_negotiate_latest_match
[12:57:57] [PASSED] pf_negotiate_latest_newer
[12:57:57] [PASSED] pf_negotiate_latest_next
[12:57:57] [SKIPPED] pf_negotiate_latest_older
[12:57:57] [SKIPPED] pf_negotiate_latest_prev
[12:57:57] =================== [PASSED] pf_service ====================
[12:57:57] ================= xe_guc_g2g (2 subtests) ==================
[12:57:57] ============== xe_live_guc_g2g_kunit_default  ==============
[12:57:57] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[12:57:57] ============== xe_live_guc_g2g_kunit_allmem  ===============
[12:57:57] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[12:57:57] =================== [SKIPPED] xe_guc_g2g ===================
[12:57:57] =================== xe_mocs (2 subtests) ===================
[12:57:57] ================ xe_live_mocs_kernel_kunit  ================
[12:57:57] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[12:57:57] ================ xe_live_mocs_reset_kunit  =================
[12:57:57] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[12:57:57] ==================== [SKIPPED] xe_mocs =====================
[12:57:57] ================= xe_migrate (2 subtests) ==================
[12:57:57] ================= xe_migrate_sanity_kunit  =================
[12:57:57] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[12:57:57] ================== xe_validate_ccs_kunit  ==================
[12:57:57] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[12:57:57] =================== [SKIPPED] xe_migrate ===================
[12:57:57] ================== xe_dma_buf (1 subtest) ==================
[12:57:57] ==================== xe_dma_buf_kunit  =====================
[12:57:57] ================ [SKIPPED] xe_dma_buf_kunit ================
[12:57:57] =================== [SKIPPED] xe_dma_buf ===================
[12:57:57] ================= xe_bo_shrink (1 subtest) =================
[12:57:57] =================== xe_bo_shrink_kunit  ====================
[12:57:57] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[12:57:57] ================== [SKIPPED] xe_bo_shrink ==================
[12:57:57] ==================== xe_bo (2 subtests) ====================
[12:57:57] ================== xe_ccs_migrate_kunit  ===================
[12:57:57] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[12:57:57] ==================== xe_bo_evict_kunit  ====================
[12:57:57] =============== [SKIPPED] xe_bo_evict_kunit ================
[12:57:57] ===================== [SKIPPED] xe_bo ======================
[12:57:57] ==================== args (11 subtests) ====================
[12:57:57] [PASSED] count_args_test
[12:57:57] [PASSED] call_args_example
[12:57:57] [PASSED] call_args_test
[12:57:57] [PASSED] drop_first_arg_example
[12:57:57] [PASSED] drop_first_arg_test
[12:57:57] [PASSED] first_arg_example
[12:57:57] [PASSED] first_arg_test
[12:57:57] [PASSED] last_arg_example
[12:57:57] [PASSED] last_arg_test
[12:57:57] [PASSED] pick_arg_example
[12:57:57] [PASSED] sep_comma_example
[12:57:57] ====================== [PASSED] args =======================
[12:57:57] =================== xe_pci (3 subtests) ====================
[12:57:57] ==================== check_graphics_ip  ====================
[12:57:57] [PASSED] 12.00 Xe_LP
[12:57:57] [PASSED] 12.10 Xe_LP+
[12:57:57] [PASSED] 12.55 Xe_HPG
[12:57:57] [PASSED] 12.60 Xe_HPC
[12:57:57] [PASSED] 12.70 Xe_LPG
[12:57:57] [PASSED] 12.71 Xe_LPG
[12:57:57] [PASSED] 12.74 Xe_LPG+
[12:57:57] [PASSED] 20.01 Xe2_HPG
[12:57:57] [PASSED] 20.02 Xe2_HPG
[12:57:57] [PASSED] 20.04 Xe2_LPG
[12:57:57] [PASSED] 30.00 Xe3_LPG
[12:57:57] [PASSED] 30.01 Xe3_LPG
[12:57:57] [PASSED] 30.03 Xe3_LPG
[12:57:57] ================ [PASSED] check_graphics_ip ================
[12:57:57] ===================== check_media_ip  ======================
[12:57:57] [PASSED] 12.00 Xe_M
[12:57:57] [PASSED] 12.55 Xe_HPM
[12:57:57] [PASSED] 13.00 Xe_LPM+
[12:57:57] [PASSED] 13.01 Xe2_HPM
[12:57:57] [PASSED] 20.00 Xe2_LPM
[12:57:57] [PASSED] 30.00 Xe3_LPM
[12:57:57] [PASSED] 30.02 Xe3_LPM
[12:57:57] ================= [PASSED] check_media_ip ==================
[12:57:57] ================= check_platform_gt_count  =================
[12:57:57] [PASSED] 0x9A60 (TIGERLAKE)
[12:57:57] [PASSED] 0x9A68 (TIGERLAKE)
[12:57:57] [PASSED] 0x9A70 (TIGERLAKE)
[12:57:57] [PASSED] 0x9A40 (TIGERLAKE)
[12:57:57] [PASSED] 0x9A49 (TIGERLAKE)
[12:57:57] [PASSED] 0x9A59 (TIGERLAKE)
[12:57:57] [PASSED] 0x9A78 (TIGERLAKE)
[12:57:57] [PASSED] 0x9AC0 (TIGERLAKE)
[12:57:57] [PASSED] 0x9AC9 (TIGERLAKE)
[12:57:57] [PASSED] 0x9AD9 (TIGERLAKE)
[12:57:57] [PASSED] 0x9AF8 (TIGERLAKE)
[12:57:57] [PASSED] 0x4C80 (ROCKETLAKE)
[12:57:57] [PASSED] 0x4C8A (ROCKETLAKE)
[12:57:57] [PASSED] 0x4C8B (ROCKETLAKE)
[12:57:57] [PASSED] 0x4C8C (ROCKETLAKE)
[12:57:57] [PASSED] 0x4C90 (ROCKETLAKE)
[12:57:57] [PASSED] 0x4C9A (ROCKETLAKE)
[12:57:57] [PASSED] 0x4680 (ALDERLAKE_S)
[12:57:57] [PASSED] 0x4682 (ALDERLAKE_S)
[12:57:57] [PASSED] 0x4688 (ALDERLAKE_S)
[12:57:57] [PASSED] 0x468A (ALDERLAKE_S)
[12:57:57] [PASSED] 0x468B (ALDERLAKE_S)
[12:57:57] [PASSED] 0x4690 (ALDERLAKE_S)
[12:57:57] [PASSED] 0x4692 (ALDERLAKE_S)
[12:57:57] [PASSED] 0x4693 (ALDERLAKE_S)
[12:57:57] [PASSED] 0x46A0 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x46A1 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x46A2 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x46A3 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x46A6 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x46A8 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x46AA (ALDERLAKE_P)
[12:57:57] [PASSED] 0x462A (ALDERLAKE_P)
[12:57:57] [PASSED] 0x4626 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x4628 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x46B0 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x46B1 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x46B2 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x46B3 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x46C0 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x46C1 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x46C2 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x46C3 (ALDERLAKE_P)
[12:57:57] [PASSED] 0x46D0 (ALDERLAKE_N)
[12:57:57] [PASSED] 0x46D1 (ALDERLAKE_N)
[12:57:57] [PASSED] 0x46D2 (ALDERLAKE_N)
[12:57:57] [PASSED] 0x46D3 (ALDERLAKE_N)
[12:57:57] [PASSED] 0x46D4 (ALDERLAKE_N)
[12:57:57] [PASSED] 0xA721 (ALDERLAKE_P)
[12:57:57] [PASSED] 0xA7A1 (ALDERLAKE_P)
[12:57:57] [PASSED] 0xA7A9 (ALDERLAKE_P)
[12:57:57] [PASSED] 0xA7AC (ALDERLAKE_P)
[12:57:57] [PASSED] 0xA7AD (ALDERLAKE_P)
[12:57:57] [PASSED] 0xA720 (ALDERLAKE_P)
[12:57:57] [PASSED] 0xA7A0 (ALDERLAKE_P)
[12:57:57] [PASSED] 0xA7A8 (ALDERLAKE_P)
[12:57:57] [PASSED] 0xA7AA (ALDERLAKE_P)
[12:57:57] [PASSED] 0xA7AB (ALDERLAKE_P)
[12:57:57] [PASSED] 0xA780 (ALDERLAKE_S)
[12:57:57] [PASSED] 0xA781 (ALDERLAKE_S)
[12:57:57] [PASSED] 0xA782 (ALDERLAKE_S)
[12:57:57] [PASSED] 0xA783 (ALDERLAKE_S)
[12:57:57] [PASSED] 0xA788 (ALDERLAKE_S)
[12:57:57] [PASSED] 0xA789 (ALDERLAKE_S)
[12:57:57] [PASSED] 0xA78A (ALDERLAKE_S)
[12:57:57] [PASSED] 0xA78B (ALDERLAKE_S)
[12:57:57] [PASSED] 0x4905 (DG1)
[12:57:57] [PASSED] 0x4906 (DG1)
[12:57:57] [PASSED] 0x4907 (DG1)
[12:57:57] [PASSED] 0x4908 (DG1)
[12:57:57] [PASSED] 0x4909 (DG1)
[12:57:57] [PASSED] 0x56C0 (DG2)
[12:57:57] [PASSED] 0x56C2 (DG2)
[12:57:57] [PASSED] 0x56C1 (DG2)
[12:57:57] [PASSED] 0x7D51 (METEORLAKE)
[12:57:57] [PASSED] 0x7DD1 (METEORLAKE)
[12:57:57] [PASSED] 0x7D41 (METEORLAKE)
[12:57:57] [PASSED] 0x7D67 (METEORLAKE)
[12:57:57] [PASSED] 0xB640 (METEORLAKE)
[12:57:57] [PASSED] 0x56A0 (DG2)
[12:57:57] [PASSED] 0x56A1 (DG2)
[12:57:57] [PASSED] 0x56A2 (DG2)
[12:57:57] [PASSED] 0x56BE (DG2)
[12:57:57] [PASSED] 0x56BF (DG2)
[12:57:57] [PASSED] 0x5690 (DG2)
[12:57:57] [PASSED] 0x5691 (DG2)
[12:57:57] [PASSED] 0x5692 (DG2)
[12:57:57] [PASSED] 0x56A5 (DG2)
[12:57:57] [PASSED] 0x56A6 (DG2)
[12:57:57] [PASSED] 0x56B0 (DG2)
[12:57:57] [PASSED] 0x56B1 (DG2)
[12:57:57] [PASSED] 0x56BA (DG2)
[12:57:57] [PASSED] 0x56BB (DG2)
[12:57:57] [PASSED] 0x56BC (DG2)
[12:57:57] [PASSED] 0x56BD (DG2)
[12:57:57] [PASSED] 0x5693 (DG2)
[12:57:57] [PASSED] 0x5694 (DG2)
[12:57:57] [PASSED] 0x5695 (DG2)
[12:57:57] [PASSED] 0x56A3 (DG2)
[12:57:57] [PASSED] 0x56A4 (DG2)
[12:57:57] [PASSED] 0x56B2 (DG2)
[12:57:57] [PASSED] 0x56B3 (DG2)
[12:57:57] [PASSED] 0x5696 (DG2)
[12:57:57] [PASSED] 0x5697 (DG2)
[12:57:57] [PASSED] 0xB69 (PVC)
[12:57:57] [PASSED] 0xB6E (PVC)
[12:57:57] [PASSED] 0xBD4 (PVC)
[12:57:57] [PASSED] 0xBD5 (PVC)
[12:57:57] [PASSED] 0xBD6 (PVC)
[12:57:57] [PASSED] 0xBD7 (PVC)
[12:57:57] [PASSED] 0xBD8 (PVC)
[12:57:57] [PASSED] 0xBD9 (PVC)
[12:57:57] [PASSED] 0xBDA (PVC)
[12:57:57] [PASSED] 0xBDB (PVC)
[12:57:57] [PASSED] 0xBE0 (PVC)
[12:57:57] [PASSED] 0xBE1 (PVC)
[12:57:57] [PASSED] 0xBE5 (PVC)
[12:57:57] [PASSED] 0x7D40 (METEORLAKE)
[12:57:57] [PASSED] 0x7D45 (METEORLAKE)
[12:57:57] [PASSED] 0x7D55 (METEORLAKE)
[12:57:57] [PASSED] 0x7D60 (METEORLAKE)
[12:57:57] [PASSED] 0x7DD5 (METEORLAKE)
[12:57:57] [PASSED] 0x6420 (LUNARLAKE)
[12:57:57] [PASSED] 0x64A0 (LUNARLAKE)
[12:57:57] [PASSED] 0x64B0 (LUNARLAKE)
[12:57:57] [PASSED] 0xE202 (BATTLEMAGE)
[12:57:57] [PASSED] 0xE209 (BATTLEMAGE)
[12:57:57] [PASSED] 0xE20B (BATTLEMAGE)
[12:57:57] [PASSED] 0xE20C (BATTLEMAGE)
[12:57:57] [PASSED] 0xE20D (BATTLEMAGE)
[12:57:57] [PASSED] 0xE210 (BATTLEMAGE)
[12:57:57] [PASSED] 0xE211 (BATTLEMAGE)
[12:57:57] [PASSED] 0xE212 (BATTLEMAGE)
[12:57:57] [PASSED] 0xE216 (BATTLEMAGE)
[12:57:57] [PASSED] 0xE220 (BATTLEMAGE)
[12:57:57] [PASSED] 0xE221 (BATTLEMAGE)
[12:57:57] [PASSED] 0xE222 (BATTLEMAGE)
[12:57:57] [PASSED] 0xE223 (BATTLEMAGE)
[12:57:57] [PASSED] 0xB080 (PANTHERLAKE)
[12:57:57] [PASSED] 0xB081 (PANTHERLAKE)
[12:57:57] [PASSED] 0xB082 (PANTHERLAKE)
[12:57:57] [PASSED] 0xB083 (PANTHERLAKE)
[12:57:57] [PASSED] 0xB084 (PANTHERLAKE)
[12:57:57] [PASSED] 0xB085 (PANTHERLAKE)
[12:57:57] [PASSED] 0xB086 (PANTHERLAKE)
[12:57:57] [PASSED] 0xB087 (PANTHERLAKE)
[12:57:57] [PASSED] 0xB08F (PANTHERLAKE)
[12:57:57] [PASSED] 0xB090 (PANTHERLAKE)
[12:57:57] [PASSED] 0xB0A0 (PANTHERLAKE)
[12:57:57] [PASSED] 0xB0B0 (PANTHERLAKE)
[12:57:57] [PASSED] 0xFD80 (PANTHERLAKE)
[12:57:57] [PASSED] 0xFD81 (PANTHERLAKE)
[12:57:57] ============= [PASSED] check_platform_gt_count =============
[12:57:57] ===================== [PASSED] xe_pci ======================
[12:57:57] =================== xe_rtp (2 subtests) ====================
[12:57:57] =============== xe_rtp_process_to_sr_tests  ================
[12:57:57] [PASSED] coalesce-same-reg
[12:57:57] [PASSED] no-match-no-add
[12:57:57] [PASSED] match-or
[12:57:57] [PASSED] match-or-xfail
[12:57:57] [PASSED] no-match-no-add-multiple-rules
[12:57:57] [PASSED] two-regs-two-entries
[12:57:57] [PASSED] clr-one-set-other
[12:57:57] [PASSED] set-field
[12:57:57] [PASSED] conflict-duplicate
[12:57:57] [PASSED] conflict-not-disjoint
[12:57:57] [PASSED] conflict-reg-type
[12:57:57] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[12:57:57] ================== xe_rtp_process_tests  ===================
[12:57:57] [PASSED] active1
[12:57:57] [PASSED] active2
[12:57:57] [PASSED] active-inactive
[12:57:57] [PASSED] inactive-active
[12:57:57] [PASSED] inactive-1st_or_active-inactive
[12:57:57] [PASSED] inactive-2nd_or_active-inactive
[12:57:57] [PASSED] inactive-last_or_active-inactive
[12:57:57] [PASSED] inactive-no_or_active-inactive
[12:57:57] ============== [PASSED] xe_rtp_process_tests ===============
[12:57:57] ===================== [PASSED] xe_rtp ======================
[12:57:57] ==================== xe_wa (1 subtest) =====================
[12:57:57] ======================== xe_wa_gt  =========================
[12:57:57] [PASSED] TIGERLAKE B0
[12:57:57] [PASSED] DG1 A0
[12:57:57] [PASSED] DG1 B0
[12:57:57] [PASSED] ALDERLAKE_S A0
[12:57:57] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[12:57:57] [PASSED] ALDERLAKE_S C0
[12:57:57] [PASSED] ALDERLAKE_S D0
[12:57:57] [PASSED] ALDERLAKE_P A0
[12:57:57] [PASSED] ALDERLAKE_P B0
[12:57:57] [PASSED] ALDERLAKE_P C0
[12:57:57] [PASSED] ALDERLAKE_S RPLS D0
[12:57:57] [PASSED] ALDERLAKE_P RPLU E0
[12:57:57] [PASSED] DG2 G10 C0
[12:57:57] [PASSED] DG2 G11 B1
[12:57:57] [PASSED] DG2 G12 A1
[12:57:57] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:57:57] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:57:57] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[12:57:57] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[12:57:57] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[12:57:57] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[12:57:57] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[12:57:57] ==================== [PASSED] xe_wa_gt =====================
[12:57:57] ====================== [PASSED] xe_wa ======================
[12:57:57] ============================================================
[12:57:57] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[12:57:57] Elapsed time: 33.574s total, 4.229s configuring, 28.979s building, 0.318s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[12:57:57] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:57:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:58:23] Starting KUnit Kernel (1/1)...
[12:58:23] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:58:23] ============ drm_test_pick_cmdline (2 subtests) ============
[12:58:23] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[12:58:23] =============== drm_test_pick_cmdline_named  ===============
[12:58:23] [PASSED] NTSC
[12:58:23] [PASSED] NTSC-J
[12:58:23] [PASSED] PAL
[12:58:23] [PASSED] PAL-M
[12:58:23] =========== [PASSED] drm_test_pick_cmdline_named ===========
[12:58:23] ============== [PASSED] drm_test_pick_cmdline ==============
[12:58:23] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[12:58:23] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[12:58:23] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[12:58:23] =========== drm_validate_clone_mode (2 subtests) ===========
[12:58:23] ============== drm_test_check_in_clone_mode  ===============
[12:58:23] [PASSED] in_clone_mode
[12:58:23] [PASSED] not_in_clone_mode
[12:58:23] ========== [PASSED] drm_test_check_in_clone_mode ===========
[12:58:23] =============== drm_test_check_valid_clones  ===============
[12:58:23] [PASSED] not_in_clone_mode
[12:58:23] [PASSED] valid_clone
[12:58:23] [PASSED] invalid_clone
[12:58:23] =========== [PASSED] drm_test_check_valid_clones ===========
[12:58:23] ============= [PASSED] drm_validate_clone_mode =============
[12:58:23] ============= drm_validate_modeset (1 subtest) =============
[12:58:23] [PASSED] drm_test_check_connector_changed_modeset
[12:58:23] ============== [PASSED] drm_validate_modeset ===============
[12:58:23] ====== drm_test_bridge_get_current_state (2 subtests) ======
[12:58:23] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[12:58:23] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[12:58:23] ======== [PASSED] drm_test_bridge_get_current_state ========
[12:58:23] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[12:58:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[12:58:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[12:58:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[12:58:23] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[12:58:23] ============== drm_bridge_alloc (2 subtests) ===============
[12:58:23] [PASSED] drm_test_drm_bridge_alloc_basic
[12:58:23] [PASSED] drm_test_drm_bridge_alloc_get_put
[12:58:23] ================ [PASSED] drm_bridge_alloc =================
[12:58:23] ================== drm_buddy (7 subtests) ==================
[12:58:23] [PASSED] drm_test_buddy_alloc_limit
[12:58:23] [PASSED] drm_test_buddy_alloc_optimistic
[12:58:23] [PASSED] drm_test_buddy_alloc_pessimistic
[12:58:23] [PASSED] drm_test_buddy_alloc_pathological
[12:58:23] [PASSED] drm_test_buddy_alloc_contiguous
[12:58:23] [PASSED] drm_test_buddy_alloc_clear
[12:58:23] [PASSED] drm_test_buddy_alloc_range_bias
[12:58:23] ==================== [PASSED] drm_buddy ====================
[12:58:23] ============= drm_cmdline_parser (40 subtests) =============
[12:58:23] [PASSED] drm_test_cmdline_force_d_only
[12:58:23] [PASSED] drm_test_cmdline_force_D_only_dvi
[12:58:23] [PASSED] drm_test_cmdline_force_D_only_hdmi
[12:58:23] [PASSED] drm_test_cmdline_force_D_only_not_digital
[12:58:23] [PASSED] drm_test_cmdline_force_e_only
[12:58:23] [PASSED] drm_test_cmdline_res
[12:58:23] [PASSED] drm_test_cmdline_res_vesa
[12:58:23] [PASSED] drm_test_cmdline_res_vesa_rblank
[12:58:23] [PASSED] drm_test_cmdline_res_rblank
[12:58:23] [PASSED] drm_test_cmdline_res_bpp
[12:58:23] [PASSED] drm_test_cmdline_res_refresh
[12:58:23] [PASSED] drm_test_cmdline_res_bpp_refresh
[12:58:23] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[12:58:23] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[12:58:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[12:58:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[12:58:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[12:58:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[12:58:23] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[12:58:23] [PASSED] drm_test_cmdline_res_margins_force_on
[12:58:23] [PASSED] drm_test_cmdline_res_vesa_margins
[12:58:23] [PASSED] drm_test_cmdline_name
[12:58:23] [PASSED] drm_test_cmdline_name_bpp
[12:58:23] [PASSED] drm_test_cmdline_name_option
[12:58:23] [PASSED] drm_test_cmdline_name_bpp_option
[12:58:23] [PASSED] drm_test_cmdline_rotate_0
[12:58:23] [PASSED] drm_test_cmdline_rotate_90
[12:58:23] [PASSED] drm_test_cmdline_rotate_180
[12:58:23] [PASSED] drm_test_cmdline_rotate_270
[12:58:23] [PASSED] drm_test_cmdline_hmirror
[12:58:23] [PASSED] drm_test_cmdline_vmirror
[12:58:23] [PASSED] drm_test_cmdline_margin_options
[12:58:23] [PASSED] drm_test_cmdline_multiple_options
[12:58:23] [PASSED] drm_test_cmdline_bpp_extra_and_option
[12:58:23] [PASSED] drm_test_cmdline_extra_and_option
[12:58:23] [PASSED] drm_test_cmdline_freestanding_options
[12:58:23] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[12:58:23] [PASSED] drm_test_cmdline_panel_orientation
[12:58:23] ================ drm_test_cmdline_invalid  =================
[12:58:23] [PASSED] margin_only
[12:58:23] [PASSED] interlace_only
[12:58:23] [PASSED] res_missing_x
[12:58:23] [PASSED] res_missing_y
[12:58:23] [PASSED] res_bad_y
[12:58:23] [PASSED] res_missing_y_bpp
[12:58:23] [PASSED] res_bad_bpp
[12:58:23] [PASSED] res_bad_refresh
[12:58:23] [PASSED] res_bpp_refresh_force_on_off
[12:58:23] [PASSED] res_invalid_mode
[12:58:23] [PASSED] res_bpp_wrong_place_mode
[12:58:23] [PASSED] name_bpp_refresh
[12:58:23] [PASSED] name_refresh
[12:58:23] [PASSED] name_refresh_wrong_mode
[12:58:23] [PASSED] name_refresh_invalid_mode
[12:58:23] [PASSED] rotate_multiple
[12:58:23] [PASSED] rotate_invalid_val
[12:58:23] [PASSED] rotate_truncated
[12:58:23] [PASSED] invalid_option
[12:58:23] [PASSED] invalid_tv_option
[12:58:23] [PASSED] truncated_tv_option
[12:58:23] ============ [PASSED] drm_test_cmdline_invalid =============
[12:58:23] =============== drm_test_cmdline_tv_options  ===============
[12:58:23] [PASSED] NTSC
[12:58:23] [PASSED] NTSC_443
[12:58:23] [PASSED] NTSC_J
[12:58:23] [PASSED] PAL
[12:58:23] [PASSED] PAL_M
[12:58:23] [PASSED] PAL_N
[12:58:23] [PASSED] SECAM
[12:58:23] [PASSED] MONO_525
[12:58:23] [PASSED] MONO_625
[12:58:23] =========== [PASSED] drm_test_cmdline_tv_options ===========
[12:58:23] =============== [PASSED] drm_cmdline_parser ================
[12:58:23] ========== drmm_connector_hdmi_init (20 subtests) ==========
[12:58:23] [PASSED] drm_test_connector_hdmi_init_valid
[12:58:23] [PASSED] drm_test_connector_hdmi_init_bpc_8
[12:58:23] [PASSED] drm_test_connector_hdmi_init_bpc_10
[12:58:23] [PASSED] drm_test_connector_hdmi_init_bpc_12
[12:58:23] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[12:58:23] [PASSED] drm_test_connector_hdmi_init_bpc_null
[12:58:23] [PASSED] drm_test_connector_hdmi_init_formats_empty
[12:58:23] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[12:58:23] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[12:58:23] [PASSED] supported_formats=0x9 yuv420_allowed=1
[12:58:23] [PASSED] supported_formats=0x9 yuv420_allowed=0
[12:58:23] [PASSED] supported_formats=0x3 yuv420_allowed=1
[12:58:23] [PASSED] supported_formats=0x3 yuv420_allowed=0
[12:58:23] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:58:23] [PASSED] drm_test_connector_hdmi_init_null_ddc
[12:58:23] [PASSED] drm_test_connector_hdmi_init_null_product
[12:58:23] [PASSED] drm_test_connector_hdmi_init_null_vendor
[12:58:23] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[12:58:23] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[12:58:23] [PASSED] drm_test_connector_hdmi_init_product_valid
[12:58:23] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[12:58:23] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[12:58:23] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[12:58:23] ========= drm_test_connector_hdmi_init_type_valid  =========
[12:58:23] [PASSED] HDMI-A
[12:58:23] [PASSED] HDMI-B
[12:58:23] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[12:58:23] ======== drm_test_connector_hdmi_init_type_invalid  ========
[12:58:23] [PASSED] Unknown
[12:58:23] [PASSED] VGA
[12:58:23] [PASSED] DVI-I
[12:58:23] [PASSED] DVI-D
[12:58:23] [PASSED] DVI-A
[12:58:23] [PASSED] Composite
[12:58:23] [PASSED] SVIDEO
[12:58:23] [PASSED] LVDS
[12:58:23] [PASSED] Component
[12:58:23] [PASSED] DIN
[12:58:23] [PASSED] DP
[12:58:23] [PASSED] TV
[12:58:23] [PASSED] eDP
[12:58:23] [PASSED] Virtual
[12:58:23] [PASSED] DSI
[12:58:23] [PASSED] DPI
[12:58:23] [PASSED] Writeback
[12:58:23] [PASSED] SPI
[12:58:23] [PASSED] USB
[12:58:23] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[12:58:23] ============ [PASSED] drmm_connector_hdmi_init =============
[12:58:23] ============= drmm_connector_init (3 subtests) =============
[12:58:23] [PASSED] drm_test_drmm_connector_init
[12:58:23] [PASSED] drm_test_drmm_connector_init_null_ddc
[12:58:23] ========= drm_test_drmm_connector_init_type_valid  =========
[12:58:23] [PASSED] Unknown
[12:58:23] [PASSED] VGA
[12:58:23] [PASSED] DVI-I
[12:58:23] [PASSED] DVI-D
[12:58:23] [PASSED] DVI-A
[12:58:23] [PASSED] Composite
[12:58:23] [PASSED] SVIDEO
[12:58:23] [PASSED] LVDS
[12:58:23] [PASSED] Component
[12:58:23] [PASSED] DIN
[12:58:23] [PASSED] DP
[12:58:23] [PASSED] HDMI-A
[12:58:23] [PASSED] HDMI-B
[12:58:23] [PASSED] TV
[12:58:23] [PASSED] eDP
[12:58:23] [PASSED] Virtual
[12:58:23] [PASSED] DSI
[12:58:23] [PASSED] DPI
[12:58:23] [PASSED] Writeback
[12:58:23] [PASSED] SPI
[12:58:23] [PASSED] USB
[12:58:23] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[12:58:23] =============== [PASSED] drmm_connector_init ===============
[12:58:23] ========= drm_connector_dynamic_init (6 subtests) ==========
[12:58:23] [PASSED] drm_test_drm_connector_dynamic_init
[12:58:23] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[12:58:23] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[12:58:23] [PASSED] drm_test_drm_connector_dynamic_init_properties
[12:58:23] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[12:58:23] [PASSED] Unknown
[12:58:23] [PASSED] VGA
[12:58:23] [PASSED] DVI-I
[12:58:23] [PASSED] DVI-D
[12:58:23] [PASSED] DVI-A
[12:58:23] [PASSED] Composite
[12:58:23] [PASSED] SVIDEO
[12:58:23] [PASSED] LVDS
[12:58:23] [PASSED] Component
[12:58:23] [PASSED] DIN
[12:58:23] [PASSED] DP
[12:58:23] [PASSED] HDMI-A
[12:58:23] [PASSED] HDMI-B
[12:58:23] [PASSED] TV
[12:58:23] [PASSED] eDP
[12:58:23] [PASSED] Virtual
[12:58:23] [PASSED] DSI
[12:58:23] [PASSED] DPI
[12:58:23] [PASSED] Writeback
[12:58:23] [PASSED] SPI
[12:58:23] [PASSED] USB
[12:58:23] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[12:58:23] ======== drm_test_drm_connector_dynamic_init_name  =========
[12:58:23] [PASSED] Unknown
[12:58:23] [PASSED] VGA
[12:58:23] [PASSED] DVI-I
[12:58:23] [PASSED] DVI-D
[12:58:23] [PASSED] DVI-A
[12:58:23] [PASSED] Composite
[12:58:23] [PASSED] SVIDEO
[12:58:23] [PASSED] LVDS
[12:58:23] [PASSED] Component
[12:58:23] [PASSED] DIN
[12:58:23] [PASSED] DP
[12:58:23] [PASSED] HDMI-A
[12:58:23] [PASSED] HDMI-B
[12:58:23] [PASSED] TV
[12:58:23] [PASSED] eDP
[12:58:23] [PASSED] Virtual
[12:58:23] [PASSED] DSI
[12:58:23] [PASSED] DPI
[12:58:23] [PASSED] Writeback
[12:58:23] [PASSED] SPI
[12:58:23] [PASSED] USB
[12:58:23] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[12:58:23] =========== [PASSED] drm_connector_dynamic_init ============
[12:58:23] ==== drm_connector_dynamic_register_early (4 subtests) =====
[12:58:23] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[12:58:23] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[12:58:23] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[12:58:23] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[12:58:23] ====== [PASSED] drm_connector_dynamic_register_early =======
[12:58:23] ======= drm_connector_dynamic_register (7 subtests) ========
[12:58:23] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[12:58:23] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[12:58:23] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[12:58:23] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[12:58:23] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[12:58:23] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[12:58:23] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[12:58:23] ========= [PASSED] drm_connector_dynamic_register ==========
[12:58:23] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[12:58:23] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[12:58:23] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[12:58:23] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[12:58:23] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[12:58:23] ========== drm_test_get_tv_mode_from_name_valid  ===========
[12:58:23] [PASSED] NTSC
[12:58:23] [PASSED] NTSC-443
[12:58:23] [PASSED] NTSC-J
[12:58:23] [PASSED] PAL
[12:58:23] [PASSED] PAL-M
[12:58:23] [PASSED] PAL-N
[12:58:23] [PASSED] SECAM
[12:58:23] [PASSED] Mono
[12:58:23] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[12:58:23] [PASSED] drm_test_get_tv_mode_from_name_truncated
[12:58:23] ============ [PASSED] drm_get_tv_mode_from_name ============
[12:58:23] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[12:58:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[12:58:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[12:58:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[12:58:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[12:58:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[12:58:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[12:58:23] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[12:58:23] [PASSED] VIC 96
[12:58:23] [PASSED] VIC 97
[12:58:23] [PASSED] VIC 101
[12:58:23] [PASSED] VIC 102
[12:58:23] [PASSED] VIC 106
[12:58:23] [PASSED] VIC 107
[12:58:23] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[12:58:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[12:58:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[12:58:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[12:58:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[12:58:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[12:58:23] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[12:58:23] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[12:58:23] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[12:58:23] [PASSED] Automatic
[12:58:23] [PASSED] Full
[12:58:23] [PASSED] Limited 16:235
[12:58:23] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[12:58:23] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[12:58:23] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[12:58:23] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[12:58:23] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[12:58:23] [PASSED] RGB
[12:58:23] [PASSED] YUV 4:2:0
[12:58:23] [PASSED] YUV 4:2:2
[12:58:23] [PASSED] YUV 4:4:4
[12:58:23] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[12:58:23] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[12:58:23] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[12:58:23] ============= drm_damage_helper (21 subtests) ==============
[12:58:23] [PASSED] drm_test_damage_iter_no_damage
[12:58:23] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[12:58:23] [PASSED] drm_test_damage_iter_no_damage_src_moved
[12:58:23] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[12:58:23] [PASSED] drm_test_damage_iter_no_damage_not_visible
[12:58:23] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[12:58:23] [PASSED] drm_test_damage_iter_no_damage_no_fb
[12:58:23] [PASSED] drm_test_damage_iter_simple_damage
[12:58:23] [PASSED] drm_test_damage_iter_single_damage
[12:58:23] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[12:58:23] [PASSED] drm_test_damage_iter_single_damage_outside_src
[12:58:23] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[12:58:23] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[12:58:23] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[12:58:23] [PASSED] drm_test_damage_iter_single_damage_src_moved
[12:58:23] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[12:58:23] [PASSED] drm_test_damage_iter_damage
[12:58:23] [PASSED] drm_test_damage_iter_damage_one_intersect
[12:58:23] [PASSED] drm_test_damage_iter_damage_one_outside
[12:58:23] [PASSED] drm_test_damage_iter_damage_src_moved
[12:58:23] [PASSED] drm_test_damage_iter_damage_not_visible
[12:58:23] ================ [PASSED] drm_damage_helper ================
[12:58:23] ============== drm_dp_mst_helper (3 subtests) ==============
[12:58:23] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[12:58:23] [PASSED] Clock 154000 BPP 30 DSC disabled
[12:58:23] [PASSED] Clock 234000 BPP 30 DSC disabled
[12:58:23] [PASSED] Clock 297000 BPP 24 DSC disabled
[12:58:23] [PASSED] Clock 332880 BPP 24 DSC enabled
[12:58:23] [PASSED] Clock 324540 BPP 24 DSC enabled
[12:58:23] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[12:58:23] ============== drm_test_dp_mst_calc_pbn_div  ===============
[12:58:23] [PASSED] Link rate 2000000 lane count 4
[12:58:23] [PASSED] Link rate 2000000 lane count 2
[12:58:23] [PASSED] Link rate 2000000 lane count 1
[12:58:23] [PASSED] Link rate 1350000 lane count 4
[12:58:23] [PASSED] Link rate 1350000 lane count 2
[12:58:23] [PASSED] Link rate 1350000 lane count 1
[12:58:23] [PASSED] Link rate 1000000 lane count 4
[12:58:23] [PASSED] Link rate 1000000 lane count 2
[12:58:23] [PASSED] Link rate 1000000 lane count 1
[12:58:23] [PASSED] Link rate 810000 lane count 4
[12:58:23] [PASSED] Link rate 810000 lane count 2
[12:58:23] [PASSED] Link rate 810000 lane count 1
[12:58:23] [PASSED] Link rate 540000 lane count 4
[12:58:23] [PASSED] Link rate 540000 lane count 2
[12:58:23] [PASSED] Link rate 540000 lane count 1
[12:58:23] [PASSED] Link rate 270000 lane count 4
[12:58:23] [PASSED] Link rate 270000 lane count 2
[12:58:23] [PASSED] Link rate 270000 lane count 1
[12:58:23] [PASSED] Link rate 162000 lane count 4
[12:58:23] [PASSED] Link rate 162000 lane count 2
[12:58:23] [PASSED] Link rate 162000 lane count 1
[12:58:23] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[12:58:23] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[12:58:23] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[12:58:23] [PASSED] DP_POWER_UP_PHY with port number
[12:58:23] [PASSED] DP_POWER_DOWN_PHY with port number
[12:58:23] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[12:58:23] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[12:58:23] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[12:58:23] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[12:58:23] [PASSED] DP_QUERY_PAYLOAD with port number
[12:58:23] [PASSED] DP_QUERY_PAYLOAD with VCPI
[12:58:23] [PASSED] DP_REMOTE_DPCD_READ with port number
[12:58:23] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[12:58:23] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[12:58:23] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[12:58:23] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[12:58:23] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[12:58:23] [PASSED] DP_REMOTE_I2C_READ with port number
[12:58:23] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[12:58:23] [PASSED] DP_REMOTE_I2C_READ with transactions array
[12:58:23] [PASSED] DP_REMOTE_I2C_WRITE with port number
[12:58:23] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[12:58:23] [PASSED] DP_REMOTE_I2C_WRITE with data array
[12:58:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[12:58:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[12:58:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[12:58:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[12:58:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[12:58:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[12:58:23] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[12:58:23] ================ [PASSED] drm_dp_mst_helper ================
[12:58:23] ================== drm_exec (7 subtests) ===================
[12:58:23] [PASSED] sanitycheck
[12:58:23] [PASSED] test_lock
[12:58:23] [PASSED] test_lock_unlock
[12:58:23] [PASSED] test_duplicates
[12:58:23] [PASSED] test_prepare
[12:58:23] [PASSED] test_prepare_array
[12:58:23] [PASSED] test_multiple_loops
[12:58:23] ==================== [PASSED] drm_exec =====================
[12:58:23] =========== drm_format_helper_test (17 subtests) ===========
[12:58:23] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[12:58:23] [PASSED] single_pixel_source_buffer
[12:58:23] [PASSED] single_pixel_clip_rectangle
[12:58:23] [PASSED] well_known_colors
[12:58:23] [PASSED] destination_pitch
[12:58:23] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[12:58:23] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[12:58:23] [PASSED] single_pixel_source_buffer
[12:58:23] [PASSED] single_pixel_clip_rectangle
[12:58:23] [PASSED] well_known_colors
[12:58:23] [PASSED] destination_pitch
[12:58:23] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[12:58:23] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[12:58:23] [PASSED] single_pixel_source_buffer
[12:58:23] [PASSED] single_pixel_clip_rectangle
[12:58:23] [PASSED] well_known_colors
[12:58:23] [PASSED] destination_pitch
[12:58:23] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[12:58:23] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[12:58:23] [PASSED] single_pixel_source_buffer
[12:58:23] [PASSED] single_pixel_clip_rectangle
[12:58:23] [PASSED] well_known_colors
[12:58:23] [PASSED] destination_pitch
[12:58:23] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[12:58:23] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[12:58:23] [PASSED] single_pixel_source_buffer
[12:58:23] [PASSED] single_pixel_clip_rectangle
[12:58:23] [PASSED] well_known_colors
[12:58:23] [PASSED] destination_pitch
[12:58:23] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[12:58:23] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[12:58:23] [PASSED] single_pixel_source_buffer
[12:58:23] [PASSED] single_pixel_clip_rectangle
[12:58:23] [PASSED] well_known_colors
[12:58:23] [PASSED] destination_pitch
[12:58:23] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[12:58:23] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[12:58:23] [PASSED] single_pixel_source_buffer
[12:58:23] [PASSED] single_pixel_clip_rectangle
[12:58:23] [PASSED] well_known_colors
[12:58:23] [PASSED] destination_pitch
[12:58:23] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[12:58:23] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[12:58:23] [PASSED] single_pixel_source_buffer
[12:58:23] [PASSED] single_pixel_clip_rectangle
[12:58:23] [PASSED] well_known_colors
[12:58:23] [PASSED] destination_pitch
[12:58:23] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[12:58:23] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[12:58:23] [PASSED] single_pixel_source_buffer
[12:58:23] [PASSED] single_pixel_clip_rectangle
[12:58:23] [PASSED] well_known_colors
[12:58:23] [PASSED] destination_pitch
[12:58:23] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[12:58:23] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[12:58:23] [PASSED] single_pixel_source_buffer
[12:58:23] [PASSED] single_pixel_clip_rectangle
[12:58:23] [PASSED] well_known_colors
[12:58:23] [PASSED] destination_pitch
[12:58:23] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[12:58:23] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[12:58:23] [PASSED] single_pixel_source_buffer
[12:58:23] [PASSED] single_pixel_clip_rectangle
[12:58:23] [PASSED] well_known_colors
[12:58:23] [PASSED] destination_pitch
[12:58:23] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[12:58:23] ============== drm_test_fb_xrgb8888_to_mono  ===============
[12:58:23] [PASSED] single_pixel_source_buffer
[12:58:23] [PASSED] single_pixel_clip_rectangle
[12:58:23] [PASSED] well_known_colors
[12:58:23] [PASSED] destination_pitch
[12:58:23] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[12:58:23] ==================== drm_test_fb_swab  =====================
[12:58:23] [PASSED] single_pixel_source_buffer
[12:58:23] [PASSED] single_pixel_clip_rectangle
[12:58:23] [PASSED] well_known_colors
[12:58:23] [PASSED] destination_pitch
[12:58:23] ================ [PASSED] drm_test_fb_swab =================
[12:58:23] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[12:58:23] [PASSED] single_pixel_source_buffer
[12:58:23] [PASSED] single_pixel_clip_rectangle
[12:58:23] [PASSED] well_known_colors
[12:58:23] [PASSED] destination_pitch
[12:58:23] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[12:58:23] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[12:58:23] [PASSED] single_pixel_source_buffer
[12:58:23] [PASSED] single_pixel_clip_rectangle
[12:58:23] [PASSED] well_known_colors
[12:58:23] [PASSED] destination_pitch
[12:58:23] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[12:58:23] ================= drm_test_fb_clip_offset  =================
[12:58:23] [PASSED] pass through
[12:58:23] [PASSED] horizontal offset
[12:58:23] [PASSED] vertical offset
[12:58:23] [PASSED] horizontal and vertical offset
[12:58:23] [PASSED] horizontal offset (custom pitch)
[12:58:23] [PASSED] vertical offset (custom pitch)
[12:58:23] [PASSED] horizontal and vertical offset (custom pitch)
[12:58:23] ============= [PASSED] drm_test_fb_clip_offset =============
[12:58:23] =================== drm_test_fb_memcpy  ====================
[12:58:23] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[12:58:23] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[12:58:23] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[12:58:23] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[12:58:23] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[12:58:23] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[12:58:23] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[12:58:23] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[12:58:23] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[12:58:23] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[12:58:23] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[12:58:23] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[12:58:23] =============== [PASSED] drm_test_fb_memcpy ================
[12:58:23] ============= [PASSED] drm_format_helper_test ==============
[12:58:23] ================= drm_format (18 subtests) =================
[12:58:23] [PASSED] drm_test_format_block_width_invalid
[12:58:23] [PASSED] drm_test_format_block_width_one_plane
[12:58:23] [PASSED] drm_test_format_block_width_two_plane
[12:58:23] [PASSED] drm_test_format_block_width_three_plane
[12:58:23] [PASSED] drm_test_format_block_width_tiled
[12:58:23] [PASSED] drm_test_format_block_height_invalid
[12:58:23] [PASSED] drm_test_format_block_height_one_plane
[12:58:23] [PASSED] drm_test_format_block_height_two_plane
[12:58:23] [PASSED] drm_test_format_block_height_three_plane
[12:58:23] [PASSED] drm_test_format_block_height_tiled
[12:58:23] [PASSED] drm_test_format_min_pitch_invalid
[12:58:23] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[12:58:23] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[12:58:23] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[12:58:23] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[12:58:23] [PASSED] drm_test_format_min_pitch_two_plane
[12:58:23] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[12:58:23] [PASSED] drm_test_format_min_pitch_tiled
[12:58:23] =================== [PASSED] drm_format ====================
[12:58:23] ============== drm_framebuffer (10 subtests) ===============
[12:58:23] ========== drm_test_framebuffer_check_src_coords  ==========
[12:58:23] [PASSED] Success: source fits into fb
[12:58:23] [PASSED] Fail: overflowing fb with x-axis coordinate
[12:58:23] [PASSED] Fail: overflowing fb with y-axis coordinate
[12:58:23] [PASSED] Fail: overflowing fb with source width
[12:58:23] [PASSED] Fail: overflowing fb with source height
[12:58:23] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[12:58:23] [PASSED] drm_test_framebuffer_cleanup
[12:58:23] =============== drm_test_framebuffer_create  ===============
[12:58:23] [PASSED] ABGR8888 normal sizes
[12:58:23] [PASSED] ABGR8888 max sizes
[12:58:23] [PASSED] ABGR8888 pitch greater than min required
[12:58:23] [PASSED] ABGR8888 pitch less than min required
[12:58:23] [PASSED] ABGR8888 Invalid width
[12:58:23] [PASSED] ABGR8888 Invalid buffer handle
[12:58:23] [PASSED] No pixel format
[12:58:23] [PASSED] ABGR8888 Width 0
[12:58:23] [PASSED] ABGR8888 Height 0
[12:58:23] [PASSED] ABGR8888 Out of bound height * pitch combination
[12:58:23] [PASSED] ABGR8888 Large buffer offset
[12:58:23] [PASSED] ABGR8888 Buffer offset for inexistent plane
[12:58:23] [PASSED] ABGR8888 Invalid flag
[12:58:23] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[12:58:23] [PASSED] ABGR8888 Valid buffer modifier
[12:58:23] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[12:58:23] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[12:58:23] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[12:58:23] [PASSED] NV12 Normal sizes
[12:58:23] [PASSED] NV12 Max sizes
[12:58:23] [PASSED] NV12 Invalid pitch
[12:58:23] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[12:58:23] [PASSED] NV12 different  modifier per-plane
[12:58:23] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[12:58:23] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[12:58:23] [PASSED] NV12 Modifier for inexistent plane
[12:58:23] [PASSED] NV12 Handle for inexistent plane
[12:58:23] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[12:58:23] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[12:58:23] [PASSED] YVU420 Normal sizes
[12:58:23] [PASSED] YVU420 Max sizes
[12:58:23] [PASSED] YVU420 Invalid pitch
[12:58:23] [PASSED] YVU420 Different pitches
[12:58:23] [PASSED] YVU420 Different buffer offsets/pitches
[12:58:23] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[12:58:23] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[12:58:23] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[12:58:23] [PASSED] YVU420 Valid modifier
[12:58:23] [PASSED] YVU420 Different modifiers per plane
[12:58:23] [PASSED] YVU420 Modifier for inexistent plane
[12:58:23] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[12:58:23] [PASSED] X0L2 Normal sizes
[12:58:23] [PASSED] X0L2 Max sizes
[12:58:23] [PASSED] X0L2 Invalid pitch
[12:58:23] [PASSED] X0L2 Pitch greater than minimum required
[12:58:23] [PASSED] X0L2 Handle for inexistent plane
[12:58:23] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[12:58:23] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[12:58:23] [PASSED] X0L2 Valid modifier
[12:58:23] [PASSED] X0L2 Modifier for inexistent plane
[12:58:23] =========== [PASSED] drm_test_framebuffer_create ===========
[12:58:23] [PASSED] drm_test_framebuffer_free
[12:58:23] [PASSED] drm_test_framebuffer_init
[12:58:23] [PASSED] drm_test_framebuffer_init_bad_format
[12:58:23] [PASSED] drm_test_framebuffer_init_dev_mismatch
[12:58:23] [PASSED] drm_test_framebuffer_lookup
[12:58:23] [PASSED] drm_test_framebuffer_lookup_inexistent
[12:58:23] [PASSED] drm_test_framebuffer_modifiers_not_supported
[12:58:23] ================= [PASSED] drm_framebuffer =================
[12:58:23] ================ drm_gem_shmem (8 subtests) ================
[12:58:23] [PASSED] drm_gem_shmem_test_obj_create
[12:58:23] [PASSED] drm_gem_shmem_test_obj_create_private
[12:58:23] [PASSED] drm_gem_shmem_test_pin_pages
[12:58:23] [PASSED] drm_gem_shmem_test_vmap
[12:58:23] [PASSED] drm_gem_shmem_test_get_pages_sgt
[12:58:23] [PASSED] drm_gem_shmem_test_get_sg_table
[12:58:23] [PASSED] drm_gem_shmem_test_madvise
[12:58:23] [PASSED] drm_gem_shmem_test_purge
[12:58:23] ================== [PASSED] drm_gem_shmem ==================
[12:58:23] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[12:58:23] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[12:58:23] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[12:58:23] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[12:58:23] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[12:58:23] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[12:58:23] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[12:58:23] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[12:58:23] [PASSED] Automatic
[12:58:23] [PASSED] Full
[12:58:23] [PASSED] Limited 16:235
[12:58:23] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[12:58:23] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[12:58:23] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[12:58:23] [PASSED] drm_test_check_disable_connector
[12:58:23] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[12:58:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[12:58:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[12:58:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[12:58:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[12:58:23] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[12:58:23] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[12:58:23] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[12:58:23] [PASSED] drm_test_check_output_bpc_dvi
[12:58:23] [PASSED] drm_test_check_output_bpc_format_vic_1
[12:58:23] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[12:58:23] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[12:58:23] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[12:58:23] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[12:58:23] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[12:58:23] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[12:58:23] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[12:58:23] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[12:58:23] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[12:58:23] [PASSED] drm_test_check_broadcast_rgb_value
[12:58:23] [PASSED] drm_test_check_bpc_8_value
[12:58:23] [PASSED] drm_test_check_bpc_10_value
[12:58:23] [PASSED] drm_test_check_bpc_12_value
[12:58:23] [PASSED] drm_test_check_format_value
[12:58:23] [PASSED] drm_test_check_tmds_char_value
[12:58:23] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[12:58:23] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[12:58:23] [PASSED] drm_test_check_mode_valid
[12:58:23] [PASSED] drm_test_check_mode_valid_reject
[12:58:23] [PASSED] drm_test_check_mode_valid_reject_rate
[12:58:23] [PASSED] drm_test_check_mode_valid_reject_max_clock
[12:58:23] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[12:58:23] ================= drm_managed (2 subtests) =================
[12:58:23] [PASSED] drm_test_managed_release_action
[12:58:23] [PASSED] drm_test_managed_run_action
[12:58:23] =================== [PASSED] drm_managed ===================
[12:58:23] =================== drm_mm (6 subtests) ====================
[12:58:23] [PASSED] drm_test_mm_init
[12:58:23] [PASSED] drm_test_mm_debug
[12:58:23] [PASSED] drm_test_mm_align32
[12:58:23] [PASSED] drm_test_mm_align64
[12:58:23] [PASSED] drm_test_mm_lowest
[12:58:23] [PASSED] drm_test_mm_highest
[12:58:23] ===================== [PASSED] drm_mm ======================
[12:58:23] ============= drm_modes_analog_tv (5 subtests) =============
[12:58:23] [PASSED] drm_test_modes_analog_tv_mono_576i
[12:58:23] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[12:58:23] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[12:58:23] [PASSED] drm_test_modes_analog_tv_pal_576i
[12:58:23] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[12:58:23] =============== [PASSED] drm_modes_analog_tv ===============
[12:58:23] ============== drm_plane_helper (2 subtests) ===============
[12:58:23] =============== drm_test_check_plane_state  ================
[12:58:23] [PASSED] clipping_simple
[12:58:23] [PASSED] clipping_rotate_reflect
[12:58:23] [PASSED] positioning_simple
[12:58:23] [PASSED] upscaling
[12:58:23] [PASSED] downscaling
[12:58:23] [PASSED] rounding1
[12:58:23] [PASSED] rounding2
[12:58:23] [PASSED] rounding3
[12:58:23] [PASSED] rounding4
[12:58:23] =========== [PASSED] drm_test_check_plane_state ============
[12:58:23] =========== drm_test_check_invalid_plane_state  ============
[12:58:23] [PASSED] positioning_invalid
[12:58:23] [PASSED] upscaling_invalid
[12:58:23] [PASSED] downscaling_invalid
[12:58:23] ======= [PASSED] drm_test_check_invalid_plane_state ========
[12:58:23] ================ [PASSED] drm_plane_helper =================
[12:58:23] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[12:58:23] ====== drm_test_connector_helper_tv_get_modes_check  =======
[12:58:23] [PASSED] None
[12:58:23] [PASSED] PAL
[12:58:23] [PASSED] NTSC
[12:58:23] [PASSED] Both, NTSC Default
[12:58:23] [PASSED] Both, PAL Default
[12:58:23] [PASSED] Both, NTSC Default, with PAL on command-line
[12:58:23] [PASSED] Both, PAL Default, with NTSC on command-line
[12:58:23] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[12:58:23] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[12:58:23] ================== drm_rect (9 subtests) ===================
[12:58:23] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[12:58:23] [PASSED] drm_test_rect_clip_scaled_not_clipped
[12:58:23] [PASSED] drm_test_rect_clip_scaled_clipped
[12:58:23] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[12:58:23] ================= drm_test_rect_intersect  =================
[12:58:23] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[12:58:23] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[12:58:23] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[12:58:23] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[12:58:23] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[12:58:23] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[12:58:23] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[12:58:23] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[12:58:23] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[12:58:23] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[12:58:23] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[12:58:23] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[12:58:23] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[12:58:23] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[12:58:23] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[12:58:23] ============= [PASSED] drm_test_rect_intersect =============
[12:58:23] ================ drm_test_rect_calc_hscale  ================
[12:58:23] [PASSED] normal use
[12:58:23] [PASSED] out of max range
[12:58:23] [PASSED] out of min range
[12:58:23] [PASSED] zero dst
[12:58:23] [PASSED] negative src
[12:58:23] [PASSED] negative dst
[12:58:23] ============ [PASSED] drm_test_rect_calc_hscale ============
[12:58:23] ================ drm_test_rect_calc_vscale  ================
[12:58:23] [PASSED] normal use
[12:58:23] [PASSED] out of max range
[12:58:23] [PASSED] out of min range
[12:58:23] [PASSED] zero dst
[12:58:23] [PASSED] negative src
stty: 'standard input': Inappropriate ioctl for device
[12:58:23] [PASSED] negative dst
[12:58:23] ============ [PASSED] drm_test_rect_calc_vscale ============
[12:58:23] ================== drm_test_rect_rotate  ===================
[12:58:23] [PASSED] reflect-x
[12:58:23] [PASSED] reflect-y
[12:58:23] [PASSED] rotate-0
[12:58:23] [PASSED] rotate-90
[12:58:23] [PASSED] rotate-180
[12:58:23] [PASSED] rotate-270
[12:58:23] ============== [PASSED] drm_test_rect_rotate ===============
[12:58:23] ================ drm_test_rect_rotate_inv  =================
[12:58:23] [PASSED] reflect-x
[12:58:23] [PASSED] reflect-y
[12:58:23] [PASSED] rotate-0
[12:58:23] [PASSED] rotate-90
[12:58:23] [PASSED] rotate-180
[12:58:23] [PASSED] rotate-270
[12:58:23] ============ [PASSED] drm_test_rect_rotate_inv =============
[12:58:23] ==================== [PASSED] drm_rect =====================
[12:58:23] ============ drm_sysfb_modeset_test (1 subtest) ============
[12:58:23] ============ drm_test_sysfb_build_fourcc_list  =============
[12:58:23] [PASSED] no native formats
[12:58:23] [PASSED] XRGB8888 as native format
[12:58:23] [PASSED] remove duplicates
[12:58:23] [PASSED] convert alpha formats
[12:58:23] [PASSED] random formats
[12:58:23] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[12:58:23] ============= [PASSED] drm_sysfb_modeset_test ==============
[12:58:23] ============================================================
[12:58:23] Testing complete. Ran 621 tests: passed: 621
[12:58:23] Elapsed time: 25.525s total, 1.738s configuring, 23.620s building, 0.151s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[12:58:23] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:58:25] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:58:34] Starting KUnit Kernel (1/1)...
[12:58:34] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:58:34] ================= ttm_device (5 subtests) ==================
[12:58:34] [PASSED] ttm_device_init_basic
[12:58:34] [PASSED] ttm_device_init_multiple
[12:58:34] [PASSED] ttm_device_fini_basic
[12:58:34] [PASSED] ttm_device_init_no_vma_man
[12:58:34] ================== ttm_device_init_pools  ==================
[12:58:34] [PASSED] No DMA allocations, no DMA32 required
[12:58:34] [PASSED] DMA allocations, DMA32 required
[12:58:34] [PASSED] No DMA allocations, DMA32 required
[12:58:34] [PASSED] DMA allocations, no DMA32 required
[12:58:34] ============== [PASSED] ttm_device_init_pools ==============
[12:58:34] =================== [PASSED] ttm_device ====================
[12:58:34] ================== ttm_pool (8 subtests) ===================
[12:58:34] ================== ttm_pool_alloc_basic  ===================
[12:58:34] [PASSED] One page
[12:58:34] [PASSED] More than one page
[12:58:34] [PASSED] Above the allocation limit
[12:58:34] [PASSED] One page, with coherent DMA mappings enabled
[12:58:34] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:58:34] ============== [PASSED] ttm_pool_alloc_basic ===============
[12:58:34] ============== ttm_pool_alloc_basic_dma_addr  ==============
[12:58:34] [PASSED] One page
[12:58:34] [PASSED] More than one page
[12:58:34] [PASSED] Above the allocation limit
[12:58:34] [PASSED] One page, with coherent DMA mappings enabled
[12:58:34] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:58:34] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[12:58:34] [PASSED] ttm_pool_alloc_order_caching_match
[12:58:34] [PASSED] ttm_pool_alloc_caching_mismatch
[12:58:34] [PASSED] ttm_pool_alloc_order_mismatch
[12:58:34] [PASSED] ttm_pool_free_dma_alloc
[12:58:34] [PASSED] ttm_pool_free_no_dma_alloc
[12:58:34] [PASSED] ttm_pool_fini_basic
[12:58:34] ==================== [PASSED] ttm_pool =====================
[12:58:34] ================ ttm_resource (8 subtests) =================
[12:58:34] ================= ttm_resource_init_basic  =================
[12:58:34] [PASSED] Init resource in TTM_PL_SYSTEM
[12:58:34] [PASSED] Init resource in TTM_PL_VRAM
[12:58:34] [PASSED] Init resource in a private placement
[12:58:34] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[12:58:34] ============= [PASSED] ttm_resource_init_basic =============
[12:58:34] [PASSED] ttm_resource_init_pinned
[12:58:34] [PASSED] ttm_resource_fini_basic
[12:58:34] [PASSED] ttm_resource_manager_init_basic
[12:58:34] [PASSED] ttm_resource_manager_usage_basic
[12:58:34] [PASSED] ttm_resource_manager_set_used_basic
[12:58:34] [PASSED] ttm_sys_man_alloc_basic
[12:58:34] [PASSED] ttm_sys_man_free_basic
[12:58:34] ================== [PASSED] ttm_resource ===================
[12:58:34] =================== ttm_tt (15 subtests) ===================
[12:58:34] ==================== ttm_tt_init_basic  ====================
[12:58:34] [PASSED] Page-aligned size
[12:58:34] [PASSED] Extra pages requested
[12:58:34] ================ [PASSED] ttm_tt_init_basic ================
[12:58:34] [PASSED] ttm_tt_init_misaligned
[12:58:34] [PASSED] ttm_tt_fini_basic
[12:58:34] [PASSED] ttm_tt_fini_sg
[12:58:34] [PASSED] ttm_tt_fini_shmem
[12:58:34] [PASSED] ttm_tt_create_basic
[12:58:34] [PASSED] ttm_tt_create_invalid_bo_type
[12:58:34] [PASSED] ttm_tt_create_ttm_exists
[12:58:34] [PASSED] ttm_tt_create_failed
[12:58:34] [PASSED] ttm_tt_destroy_basic
[12:58:34] [PASSED] ttm_tt_populate_null_ttm
[12:58:34] [PASSED] ttm_tt_populate_populated_ttm
[12:58:34] [PASSED] ttm_tt_unpopulate_basic
[12:58:34] [PASSED] ttm_tt_unpopulate_empty_ttm
[12:58:34] [PASSED] ttm_tt_swapin_basic
[12:58:34] ===================== [PASSED] ttm_tt ======================
[12:58:34] =================== ttm_bo (14 subtests) ===================
[12:58:34] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[12:58:34] [PASSED] Cannot be interrupted and sleeps
[12:58:34] [PASSED] Cannot be interrupted, locks straight away
[12:58:34] [PASSED] Can be interrupted, sleeps
[12:58:34] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[12:58:34] [PASSED] ttm_bo_reserve_locked_no_sleep
[12:58:34] [PASSED] ttm_bo_reserve_no_wait_ticket
[12:58:34] [PASSED] ttm_bo_reserve_double_resv
[12:58:34] [PASSED] ttm_bo_reserve_interrupted
[12:58:34] [PASSED] ttm_bo_reserve_deadlock
[12:58:34] [PASSED] ttm_bo_unreserve_basic
[12:58:34] [PASSED] ttm_bo_unreserve_pinned
[12:58:34] [PASSED] ttm_bo_unreserve_bulk
[12:58:34] [PASSED] ttm_bo_fini_basic
[12:58:34] [PASSED] ttm_bo_fini_shared_resv
[12:58:34] [PASSED] ttm_bo_pin_basic
[12:58:34] [PASSED] ttm_bo_pin_unpin_resource
[12:58:34] [PASSED] ttm_bo_multiple_pin_one_unpin
[12:58:34] ===================== [PASSED] ttm_bo ======================
[12:58:34] ============== ttm_bo_validate (21 subtests) ===============
[12:58:34] ============== ttm_bo_init_reserved_sys_man  ===============
[12:58:34] [PASSED] Buffer object for userspace
[12:58:34] [PASSED] Kernel buffer object
[12:58:34] [PASSED] Shared buffer object
[12:58:34] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[12:58:34] ============== ttm_bo_init_reserved_mock_man  ==============
[12:58:34] [PASSED] Buffer object for userspace
[12:58:34] [PASSED] Kernel buffer object
[12:58:34] [PASSED] Shared buffer object
[12:58:34] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[12:58:34] [PASSED] ttm_bo_init_reserved_resv
[12:58:34] ================== ttm_bo_validate_basic  ==================
[12:58:34] [PASSED] Buffer object for userspace
[12:58:34] [PASSED] Kernel buffer object
[12:58:34] [PASSED] Shared buffer object
[12:58:34] ============== [PASSED] ttm_bo_validate_basic ==============
[12:58:34] [PASSED] ttm_bo_validate_invalid_placement
[12:58:34] ============= ttm_bo_validate_same_placement  ==============
[12:58:34] [PASSED] System manager
[12:58:34] [PASSED] VRAM manager
[12:58:34] ========= [PASSED] ttm_bo_validate_same_placement ==========
[12:58:34] [PASSED] ttm_bo_validate_failed_alloc
[12:58:34] [PASSED] ttm_bo_validate_pinned
[12:58:34] [PASSED] ttm_bo_validate_busy_placement
[12:58:34] ================ ttm_bo_validate_multihop  =================
[12:58:34] [PASSED] Buffer object for userspace
[12:58:34] [PASSED] Kernel buffer object
[12:58:34] [PASSED] Shared buffer object
[12:58:34] ============ [PASSED] ttm_bo_validate_multihop =============
[12:58:34] ========== ttm_bo_validate_no_placement_signaled  ==========
[12:58:34] [PASSED] Buffer object in system domain, no page vector
[12:58:34] [PASSED] Buffer object in system domain with an existing page vector
[12:58:34] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[12:58:34] ======== ttm_bo_validate_no_placement_not_signaled  ========
[12:58:34] [PASSED] Buffer object for userspace
[12:58:34] [PASSED] Kernel buffer object
[12:58:34] [PASSED] Shared buffer object
[12:58:34] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[12:58:34] [PASSED] ttm_bo_validate_move_fence_signaled
[12:58:34] ========= ttm_bo_validate_move_fence_not_signaled  =========
[12:58:34] [PASSED] Waits for GPU
[12:58:34] [PASSED] Tries to lock straight away
[12:58:34] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[12:58:34] [PASSED] ttm_bo_validate_happy_evict
[12:58:34] [PASSED] ttm_bo_validate_all_pinned_evict
[12:58:34] [PASSED] ttm_bo_validate_allowed_only_evict
[12:58:34] [PASSED] ttm_bo_validate_deleted_evict
[12:58:34] [PASSED] ttm_bo_validate_busy_domain_evict
[12:58:34] [PASSED] ttm_bo_validate_evict_gutting
[12:58:34] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[12:58:34] ================= [PASSED] ttm_bo_validate =================
[12:58:34] ============================================================
[12:58:34] Testing complete. Ran 101 tests: passed: 101
[12:58:34] Elapsed time: 11.100s total, 1.721s configuring, 9.163s building, 0.179s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for Introduce drm sharpness property

[Patchwork]

== Series Details ==

Series: Introduce drm sharpness property
URL   : https://patchwork.freedesktop.org/series/155103/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast d557b14c00c4ab027e66c1c7bf512cf479ff8c24
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/drm_drv.c:449:6: warning: context imbalance in 'drm_dev_enter' - different lock contexts for basic block
+drivers/gpu/drm/drm_drv.c: note: in included file (through include/linux/notifier.h, arch/x86/include/asm/uprobes.h, include/linux/uprobes.h, include/linux/mm_types.h, include/linux/mmzone.h, include/linux/gfp.h, ...):
+drivers/gpu/drm/drm_plane.c:213:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_casf.c:150:21: error: too long token expansion
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2041:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2054:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2054:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2054:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+drivers/gpu/drm/i915/i915_irq.c:466:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:466:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:474:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:474:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:479:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:479:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:479:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:517:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:517:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:525:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:525:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:530:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:530:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:530:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:574:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:574:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:577:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:577:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:581:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:581:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:588:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:588:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:588:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:588:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/intel_uncore.c:1928:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1929:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1996:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1997:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2018:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2019:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock
+./include/linux/srcu.h:373:9: warning: context imbalance in 'drm_dev_exit' - unexpected unlock

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Introduce drm sharpness property

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 855 bytes --]

== Series Details ==

Series: Introduce drm sharpness property
URL   : https://patchwork.freedesktop.org/series/155103/
State : success

== Summary ==

CI Bug Log - changes from xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24_BAT -> xe-pw-155103v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24 -> xe-pw-155103v1

  IGT_8554: 8554
  xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24: d557b14c00c4ab027e66c1c7bf512cf479ff8c24
  xe-pw-155103v1: 155103v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/index.html

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✓ Xe.CI.Full: success for Introduce drm sharpness property

[Patchwork]

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== Series Details ==

Series: Introduce drm sharpness property
URL   : https://patchwork.freedesktop.org/series/155103/
State : success

== Summary ==

CI Bug Log - changes from xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24_FULL -> xe-pw-155103v1_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-155103v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][1] ([Intel XE#316]) +4 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-433/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][2] ([Intel XE#1124]) +3 other tests skip
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#1124])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-lnl-7/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][4] ([Intel XE#1124]) +7 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2314] / [Intel XE#2894])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-7/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][6] ([Intel XE#2191])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-3840x2160p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][7] ([Intel XE#367]) +2 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-436/igt@kms_bw@linear-tiling-3-displays-3840x2160p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2887]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2652] / [Intel XE#787]) +16 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-4/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#3432])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][11] ([Intel XE#3862]) +1 other test incomplete
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][12] ([Intel XE#787]) +76 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][13] ([Intel XE#2907])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#455] / [Intel XE#787]) +21 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-436/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][15] -> [INCOMPLETE][16] ([Intel XE#2705] / [Intel XE#4212])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][17] ([Intel XE#2705] / [Intel XE#4212] / [Intel XE#4345])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][18] ([Intel XE#2705] / [Intel XE#4212])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html

  * igt@kms_chamelium_color@gamma:
    - shard-dg2-set2:     NOTRUN -> [SKIP][19] ([Intel XE#306]) +3 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-464/igt@kms_chamelium_color@gamma.html

  * igt@kms_chamelium_edid@vga-edid-read:
    - shard-dg2-set2:     NOTRUN -> [SKIP][20] ([Intel XE#373]) +6 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@kms_chamelium_edid@vga-edid-read.html

  * igt@kms_chamelium_hpd@vga-hpd-fast:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2252]) +3 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-7/igt@kms_chamelium_hpd@vga-hpd-fast.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2-set2:     NOTRUN -> [FAIL][22] ([Intel XE#1178]) +1 other test fail
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-436/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2321])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2320]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_cursor_crc@cursor-onscreen-256x85.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-dg2-set2:     NOTRUN -> [SKIP][25] ([Intel XE#308]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
    - shard-bmg:          [PASS][26] -> [SKIP][27] ([Intel XE#2291]) +2 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-5/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2-set2:     NOTRUN -> [SKIP][28] ([Intel XE#323]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dp_aux_dev:
    - shard-bmg:          [PASS][29] -> [SKIP][30] ([Intel XE#3009])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-4/igt@kms_dp_aux_dev.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_dp_aux_dev.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2244]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-7/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][32] ([Intel XE#455]) +19 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-436/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#5425])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-4/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_feature_discovery@display-3x:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#2373])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_feature_discovery@display-3x.html

  * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2316])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-bmg:          [PASS][36] -> [SKIP][37] ([Intel XE#2316]) +6 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-5/igt@kms_flip@2x-nonexisting-fb.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip@dpms-off-confusion@c-hdmi-a1:
    - shard-adlp:         [PASS][38] -> [DMESG-WARN][39] ([Intel XE#4543]) +11 other tests dmesg-warn
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-9/igt@kms_flip@dpms-off-confusion@c-hdmi-a1.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-6/igt@kms_flip@dpms-off-confusion@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [PASS][40] -> [FAIL][41] ([Intel XE#301]) +1 other test fail
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-rmfb:
    - shard-adlp:         [PASS][42] -> [DMESG-WARN][43] ([Intel XE#4543] / [Intel XE#5208])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-1/igt@kms_flip@flip-vs-rmfb.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-8/igt@kms_flip@flip-vs-rmfb.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#1401] / [Intel XE#1745])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-lnl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#1401])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-lnl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#2293] / [Intel XE#2380]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2293]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#2311]) +7 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#5390]) +4 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][50] ([Intel XE#651]) +29 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
    - shard-dg2-set2:     NOTRUN -> [SKIP][51] ([Intel XE#658])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#656]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][53] ([Intel XE#653]) +30 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#2313]) +7 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#2312]) +7 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-dg2-set2:     NOTRUN -> [SKIP][56] ([Intel XE#346])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-464/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#3012])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-dg2-set2:     NOTRUN -> [SKIP][58] ([Intel XE#2925])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-dg2-set2:     NOTRUN -> [SKIP][59] ([Intel XE#356])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-1:
    - shard-adlp:         [PASS][60] -> [DMESG-WARN][61] ([Intel XE#2953] / [Intel XE#4173]) +1 other test dmesg-warn
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-8/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-1.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-4/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-1.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-dg2-set2:     NOTRUN -> [SKIP][62] ([Intel XE#5021])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_pm_backlight@fade:
    - shard-dg2-set2:     NOTRUN -> [SKIP][63] ([Intel XE#870]) +1 other test skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-464/igt@kms_pm_backlight@fade.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][64] ([Intel XE#1406] / [Intel XE#1489]) +8 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-436/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-7/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-psr2-cursor-plane-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][66] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +12 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@kms_psr@fbc-psr2-cursor-plane-onoff.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][67] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +4 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-4/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_psr@psr2-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#1406] / [Intel XE#2234])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_psr@psr2-primary-render.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-dg2-set2:     NOTRUN -> [SKIP][69] ([Intel XE#1127])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-433/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@sprite-rotation-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][70] ([Intel XE#3414])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@kms_rotation_crc@sprite-rotation-90.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-dg2-set2:     NOTRUN -> [SKIP][71] ([Intel XE#330])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-436/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vrr@cmrr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][72] ([Intel XE#2168])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-433/igt@kms_vrr@cmrr.html

  * igt@kms_vrr@flip-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#1499])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_vrr@flip-suspend.html

  * igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute:
    - shard-dg2-set2:     NOTRUN -> [SKIP][74] ([Intel XE#1280] / [Intel XE#455]) +1 other test skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-436/igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute.html

  * igt@xe_copy_basic@mem-set-linear-0x369:
    - shard-dg2-set2:     NOTRUN -> [SKIP][75] ([Intel XE#1126])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@xe_copy_basic@mem-set-linear-0x369.html

  * igt@xe_eudebug@basic-client-th:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#4837]) +4 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@xe_eudebug@basic-client-th.html

  * igt@xe_eudebug@vm-bind-clear-faultable:
    - shard-dg2-set2:     NOTRUN -> [SKIP][77] ([Intel XE#4837]) +14 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@xe_eudebug@vm-bind-clear-faultable.html

  * igt@xe_evict_ccs@evict-overcommit-simple:
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#688])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-lnl-7/igt@xe_evict_ccs@evict-overcommit-simple.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-mmap:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#2322]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-4/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html

  * igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][80] ([Intel XE#288]) +22 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-433/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-imm.html

  * igt@xe_exec_mix_modes@exec-simple-batch-store-lr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][81] ([Intel XE#2360])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-433/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html

  * igt@xe_exec_reset@parallel-gt-reset:
    - shard-adlp:         [PASS][82] -> [DMESG-WARN][83] ([Intel XE#3876])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-1/igt@xe_exec_reset@parallel-gt-reset.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-8/igt@xe_exec_reset@parallel-gt-reset.html

  * igt@xe_exec_system_allocator@threads-many-execqueues-mmap-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#4943]) +13 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-4/igt@xe_exec_system_allocator@threads-many-execqueues-mmap-huge-nomemset.html
    - shard-lnl:          NOTRUN -> [SKIP][85] ([Intel XE#4943])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-lnl-7/igt@xe_exec_system_allocator@threads-many-execqueues-mmap-huge-nomemset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-remap-eocheck:
    - shard-dg2-set2:     NOTRUN -> [SKIP][86] ([Intel XE#4915]) +225 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-remap-eocheck.html

  * igt@xe_exec_threads@threads-mixed-shared-vm-basic:
    - shard-adlp:         [PASS][87] -> [DMESG-FAIL][88] ([Intel XE#3876])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-1/igt@xe_exec_threads@threads-mixed-shared-vm-basic.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-8/igt@xe_exec_threads@threads-mixed-shared-vm-basic.html

  * igt@xe_oa@closed-fd-and-unmapped-access:
    - shard-dg2-set2:     NOTRUN -> [SKIP][89] ([Intel XE#3573]) +8 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@xe_oa@closed-fd-and-unmapped-access.html

  * igt@xe_pm@d3cold-mmap-system:
    - shard-bmg:          NOTRUN -> [SKIP][90] ([Intel XE#2284])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-7/igt@xe_pm@d3cold-mmap-system.html

  * igt@xe_pmu@engine-activity-most-load-idle:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][91] ([Intel XE#6190]) +1 other test dmesg-warn
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@xe_pmu@engine-activity-most-load-idle.html

  * igt@xe_pmu@fn-engine-activity-load:
    - shard-dg2-set2:     NOTRUN -> [SKIP][92] ([Intel XE#4650])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-436/igt@xe_pmu@fn-engine-activity-load.html

  * igt@xe_pmu@gt-frequency:
    - shard-dg2-set2:     [PASS][93] -> [FAIL][94] ([Intel XE#4819]) +1 other test fail
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-dg2-464/igt@xe_pmu@gt-frequency.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-434/igt@xe_pmu@gt-frequency.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-rpm:
    - shard-bmg:          NOTRUN -> [SKIP][95] ([Intel XE#4733])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-4/igt@xe_pxp@pxp-stale-bo-exec-post-rpm.html

  * igt@xe_pxp@pxp-termination-key-update-post-rpm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][96] ([Intel XE#4733]) +1 other test skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@xe_pxp@pxp-termination-key-update-post-rpm.html

  * igt@xe_query@multigpu-query-engines:
    - shard-bmg:          NOTRUN -> [SKIP][97] ([Intel XE#944])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@xe_query@multigpu-query-engines.html

  * igt@xe_query@multigpu-query-uc-fw-version-guc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][98] ([Intel XE#944]) +2 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-463/igt@xe_query@multigpu-query-uc-fw-version-guc.html

  
#### Possible fixes ####

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1:
    - shard-adlp:         [DMESG-WARN][99] ([Intel XE#4543]) -> [PASS][100] +13 other tests pass
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-2/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-3/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          [SKIP][101] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-1/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [INCOMPLETE][103] ([Intel XE#2705] / [Intel XE#4212] / [Intel XE#4345]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][105] ([Intel XE#2705] / [Intel XE#4212]) -> [PASS][106]
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-bmg:          [SKIP][107] ([Intel XE#2291]) -> [PASS][108] +1 other test pass
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-1/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-bmg:          [SKIP][109] ([Intel XE#1340]) -> [PASS][110]
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-bmg:          [SKIP][111] ([Intel XE#2316]) -> [PASS][112] +5 other tests pass
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@flip-vs-rmfb-interruptible:
    - shard-adlp:         [DMESG-WARN][113] ([Intel XE#5208]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-8/igt@kms_flip@flip-vs-rmfb-interruptible.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-4/igt@kms_flip@flip-vs-rmfb-interruptible.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-bmg:          [INCOMPLETE][115] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][116] +1 other test pass
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-6/igt@kms_flip@flip-vs-suspend.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-4/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-x:
    - shard-adlp:         [DMESG-FAIL][117] ([Intel XE#4543]) -> [PASS][118] +1 other test pass
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-x.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-x.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-bmg:          [SKIP][119] ([Intel XE#4596]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-4.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-c:
    - shard-adlp:         [DMESG-WARN][121] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][122] +7 other tests pass
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-8/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-c.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-4/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-c.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-adlp:         [FAIL][123] ([Intel XE#718]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-1/igt@kms_pm_dc@dc6-dpms.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-8/igt@kms_pm_dc@dc6-dpms.html

  * igt@xe_exec_reset@cm-close-fd:
    - shard-adlp:         [DMESG-WARN][125] -> [PASS][126]
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-3/igt@xe_exec_reset@cm-close-fd.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-1/igt@xe_exec_reset@cm-close-fd.html

  * {igt@xe_exec_system_allocator@many-large-execqueues-malloc-prefetch}:
    - shard-lnl:          [CRASH][127] ([Intel XE#6192]) -> [PASS][128] +11 other tests pass
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-lnl-3/igt@xe_exec_system_allocator@many-large-execqueues-malloc-prefetch.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-lnl-2/igt@xe_exec_system_allocator@many-large-execqueues-malloc-prefetch.html

  * {igt@xe_exec_system_allocator@once-malloc-prefetch-race}:
    - shard-bmg:          [CRASH][129] ([Intel XE#6192]) -> [PASS][130] +13 other tests pass
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-8/igt@xe_exec_system_allocator@once-malloc-prefetch-race.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-1/igt@xe_exec_system_allocator@once-malloc-prefetch-race.html

  * igt@xe_module_load@many-reload:
    - shard-adlp:         [DMESG-WARN][131] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#5244]) -> [PASS][132]
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-8/igt@xe_module_load@many-reload.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-4/igt@xe_module_load@many-reload.html

  * igt@xe_pm_residency@gt-c6-freeze@gt0:
    - shard-adlp:         [DMESG-WARN][133] ([Intel XE#2953] / [Intel XE#3088] / [Intel XE#4173]) -> [PASS][134] +1 other test pass
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-1/igt@xe_pm_residency@gt-c6-freeze@gt0.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-8/igt@xe_pm_residency@gt-c6-freeze@gt0.html

  
#### Warnings ####

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-adlp:         [DMESG-FAIL][135] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543]) -> [DMESG-FAIL][136] ([Intel XE#4543])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-9/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][137] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345]) -> [INCOMPLETE][138] ([Intel XE#2705] / [Intel XE#4212] / [Intel XE#4345])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          [FAIL][139] ([Intel XE#1178]) -> [SKIP][140] ([Intel XE#2341])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-5/igt@kms_content_protection@atomic.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_content_protection@atomic.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-adlp:         [DMESG-FAIL][141] ([Intel XE#4543]) -> [DMESG-WARN][142] ([Intel XE#4543])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1:
    - shard-adlp:         [FAIL][143] ([Intel XE#301]) -> [DMESG-WARN][144] ([Intel XE#4543])
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-adlp-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-adlp-9/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-blt:
    - shard-bmg:          [SKIP][145] ([Intel XE#2311]) -> [SKIP][146] ([Intel XE#2312]) +7 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-blt.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][147] ([Intel XE#2312]) -> [SKIP][148] ([Intel XE#2311]) +8 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][149] ([Intel XE#2312]) -> [SKIP][150] ([Intel XE#5390]) +5 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          [SKIP][151] ([Intel XE#5390]) -> [SKIP][152] ([Intel XE#2312]) +4 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
    - shard-bmg:          [SKIP][153] ([Intel XE#2312]) -> [SKIP][154] ([Intel XE#2313]) +10 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render:
    - shard-bmg:          [SKIP][155] ([Intel XE#2313]) -> [SKIP][156] ([Intel XE#2312]) +7 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-bmg:          [SKIP][157] ([Intel XE#5021]) -> [SKIP][158] ([Intel XE#4596])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-yf.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][159] ([Intel XE#2426]) -> [FAIL][160] ([Intel XE#1729])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][161] ([Intel XE#2509]) -> [SKIP][162] ([Intel XE#2426])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-dg2-set2:     [ABORT][163] ([Intel XE#5466]) -> [ABORT][164] ([Intel XE#4917] / [Intel XE#5466])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24/shard-dg2-463/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/shard-dg2-436/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#3088]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3088
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/356
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4819
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5191
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5244
  [Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5425]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5425
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5786]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5786
  [Intel XE#6190]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6190
  [Intel XE#6192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6192
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24 -> xe-pw-155103v1

  IGT_8554: 8554
  xe-3833-d557b14c00c4ab027e66c1c7bf512cf479ff8c24: d557b14c00c4ab027e66c1c7bf512cf479ff8c24
  xe-pw-155103v1: 155103v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155103v1/index.html

[-- Attachment #2: Type: text/html, Size: 56982 bytes --]

Re: [PATCH 03/10] drm/i915/display: Add strength and winsize register

[Nautiyal, Ankit K]

On 9/26/2025 5:07 PM, Nemesa Garg wrote:
> The sharpness strength value is determined by user input,
> while the winsize is based on the resolution.
> The casf_enable flag should be set if the platform supports
> sharpness adjustments and the user API strength is not zero.
> Once sharpness is enabled, update the strength bit of the
> register whenever the user changes the strength value,
> as the enable bit and winsize bit remain constant.

The commit message and subject are no longer matching with the changes, 
so need to update these.


>
> v2: Introduce get_config for casf[Ankit]
> v3: Replace 0 with FILTER_STRENGTH_MASK[Ankit]
> v4: After updating strength add win_sz register
> v5: Replace u16 with u32 for total_pixel
> v6: Add the logging part here
>
> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> ---
>   drivers/gpu/drm/i915/Makefile                 |   1 +
>   drivers/gpu/drm/i915/display/intel_casf.c     | 110 ++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_casf.h     |  17 +++
>   .../gpu/drm/i915/display/intel_casf_regs.h    |  22 ++++
>   .../drm/i915/display/intel_crtc_state_dump.c  |   5 +
>   .../drm/i915/display/intel_display_types.h    |   7 ++
>   drivers/gpu/drm/i915/display/skl_scaler.c     |   1 +
>   drivers/gpu/drm/xe/Makefile                   |   1 +
>   8 files changed, 164 insertions(+)
>   create mode 100644 drivers/gpu/drm/i915/display/intel_casf.c
>   create mode 100644 drivers/gpu/drm/i915/display/intel_casf.h
>   create mode 100644 drivers/gpu/drm/i915/display/intel_casf_regs.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 78a45a6681df..2aeb1da455d7 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -228,6 +228,7 @@ i915-y += \
>   	display/intel_bios.o \
>   	display/intel_bo.o \
>   	display/intel_bw.o \
> +	display/intel_casf.o \
>   	display/intel_cdclk.o \
>   	display/intel_cmtg.o \
>   	display/intel_color.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
> new file mode 100644
> index 000000000000..4597e576b6dc
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_casf.c
> @@ -0,0 +1,110 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + *
> + */
> +
> +#include <drm/drm_print.h>
> +
> +#include "i915_reg.h"
> +#include "intel_casf.h"
> +#include "intel_casf_regs.h"
> +#include "intel_de.h"
> +#include "intel_display_regs.h"
> +#include "intel_display_types.h"
> +
> +#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
> +#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)
> +
> +/**
> + * DOC: Content Adaptive Sharpness Filter (CASF)
> + *
> + * Starting from LNL the display engine supports an
> + * adaptive sharpening filter, enhancing the image
> + * quality. The display hardware utilizes the second
> + * pipe scaler for implementing CASF.
> + * If sharpness is being enabled then pipe scaling
> + * cannot be used.
> + * This filter operates on a region of pixels based
> + * on the tap size. Coefficients are used to generate
> + * an alpha value which blends the sharpened image to
> + * original image.
> + */
> +
> +void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	int win_size;
> +
> +	intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), FILTER_STRENGTH_MASK,
> +		     FILTER_STRENGTH(crtc_state->hw.casf_params.strength));
> +
> +	win_size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, 1));
> +
> +	intel_de_write_fw(display, SKL_PS_WIN_SZ(crtc->pipe, 1), win_size);
> +}
> +
> +static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
> +{
> +	const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
> +	u32 total_pixels = mode->hdisplay * mode->vdisplay;
> +
> +	if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
> +		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3;
> +	else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
> +		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5;
> +	else
> +		crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7;
> +}
> +
> +int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (!HAS_CASF(display))
> +		return 0;
> +
> +	if (crtc_state->uapi.sharpness_strength == 0) {
> +		crtc_state->hw.casf_params.casf_enable = false;
> +		crtc_state->hw.casf_params.strength = 0;
> +		return 0;
> +	}
> +
> +	crtc_state->hw.casf_params.casf_enable = true;
> +
> +	/*
> +	 * HW takes a value in form (1.0 + strength) in 4.4 fixed format.
> +	 * Strength is from 0.0-14.9375 ie from 0-239.
> +	 * User can give value from 0-255 but is clamped to 239.
> +	 * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
> +	 * 6.3125 in 4.4 format is b01100101 which is equal to 101.
> +	 * Also 85 + 16 = 101.
> +	 */
> +	crtc_state->hw.casf_params.strength =
> +		min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
> +
> +	intel_casf_compute_win_size(crtc_state);
> +
> +	return 0;
> +}
> +
> +void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	u32 sharp;
> +
> +	sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));
> +	if (sharp & FILTER_EN) {
> +		if (drm_WARN_ON(display->drm,
> +				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16))
> +			crtc_state->hw.casf_params.strength = 0;
> +		else
> +			crtc_state->hw.casf_params.strength =
> +				REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp);
> +		crtc_state->hw.casf_params.casf_enable = true;
> +		crtc_state->hw.casf_params.win_size =
> +			REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
> +	}
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h
> new file mode 100644
> index 000000000000..83523fe66c48
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_casf.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_CASF_H__
> +#define __INTEL_CASF_H__
> +
> +#include <linux/types.h>
> +
> +struct intel_crtc_state;
> +
> +int intel_casf_compute_config(struct intel_crtc_state *crtc_state);
> +void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state);
> +void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state);
After refactoring and code movement some functions doesn’t appear to be 
at right place.

IMO introduce the intel_casf_enable() and intel_casf_disable() in this 
patch and add code to write the strength and winsize in both.

Similarly in subsequent patches add register bits, functions to 
read/write and call them from the intel_casf_* functions.

Regards,

Ankit

Finally these will be called from appropriate places.


Regards,

Ankit


> +
> +#endif /* __INTEL_CASF_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h
> new file mode 100644
> index 000000000000..c24ba281ae37
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_CASF_REGS_H__
> +#define __INTEL_CASF_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define _SHARPNESS_CTL_A               0x682B0
> +#define _SHARPNESS_CTL_B               0x68AB0
> +#define SHARPNESS_CTL(pipe)            _MMIO_PIPE(pipe, _SHARPNESS_CTL_A, _SHARPNESS_CTL_B)
> +#define   FILTER_EN                    REG_BIT(31)
> +#define   FILTER_STRENGTH_MASK         REG_GENMASK(15, 8)
> +#define   FILTER_STRENGTH(x)           REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x))
> +#define   FILTER_SIZE_MASK             REG_GENMASK(1, 0)
> +#define   SHARPNESS_FILTER_SIZE_3X3    REG_FIELD_PREP(FILTER_SIZE_MASK, 0)
> +#define   SHARPNESS_FILTER_SIZE_5X5    REG_FIELD_PREP(FILTER_SIZE_MASK, 1)
> +#define   SHARPNESS_FILTER_SIZE_7X7    REG_FIELD_PREP(FILTER_SIZE_MASK, 2)
> +
> +#endif /* __INTEL_CASF_REGS__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 0c7f91046996..ae2f4a660ad5 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -373,6 +373,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>   
>   	intel_vdsc_state_dump(&p, 0, pipe_config);
>   
> +	drm_printf(&p, "sharpness strength: %d, sharpness tap size: %d, sharpness enable: %d\n",
> +		   pipe_config->hw.casf_params.strength,
> +		   pipe_config->hw.casf_params.win_size,
> +		   pipe_config->hw.casf_params.casf_enable);
> +
>   dump_planes:
>   	if (!state)
>   		return;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 358ab922d7a7..a9642641f702 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -946,6 +946,12 @@ struct intel_csc_matrix {
>   	u16 postoff[3];
>   };
>   
> +struct intel_casf {
> +	u8 strength;
> +	u8 win_size;
> +	bool casf_enable;
> +};
> +
>   struct intel_crtc_state {
>   	/*
>   	 * uapi (drm) state. This is the software state shown to userspace.
> @@ -982,6 +988,7 @@ struct intel_crtc_state {
>   		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
>   		struct drm_display_mode mode, pipe_mode, adjusted_mode;
>   		enum drm_scaling_filter scaling_filter;
> +		struct intel_casf casf_params;
>   	} hw;
>   
>   	/* actual state of LUTs */
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index c6cccf170ff1..19aeb8d5b79c 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -6,6 +6,7 @@
>   #include <drm/drm_print.h>
>   
>   #include "i915_utils.h"
> +#include "intel_casf_regs.h"
>   #include "intel_de.h"
>   #include "intel_display_regs.h"
>   #include "intel_display_trace.h"
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index d9c6cf0f189e..90a118bc77de 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -230,6 +230,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>   	i915-display/intel_backlight.o \
>   	i915-display/intel_bios.o \
>   	i915-display/intel_bw.o \
> +	i915-display/intel_casf.o \
>   	i915-display/intel_cdclk.o \
>   	i915-display/intel_cmtg.o \
>   	i915-display/intel_color.o \

Re: [PATCH 04/10] drm/i915/display: Add filter lut values

[Nautiyal, Ankit K]

On 9/26/2025 5:07 PM, Nemesa Garg wrote:
> Add the register bits related to filter lut values.
> These values are golden values and these value has
> to be loaded one time while enabling the casf.
>
> v2: update commit message[Ankit]
> v3: Make filter_load fn name same[Jani]
> v4: Define the filter macros here
>
> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_casf.c     | 47 +++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_casf.h     |  3 ++
>   .../gpu/drm/i915/display/intel_casf_regs.h    | 11 +++++
>   3 files changed, 61 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
> index 4597e576b6dc..45bc67377d21 100644
> --- a/drivers/gpu/drm/i915/display/intel_casf.c
> +++ b/drivers/gpu/drm/i915/display/intel_casf.c
> @@ -16,6 +16,13 @@
>   #define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
>   #define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)
>   
> +#define FILTER_COEFF_0_125 125
> +#define FILTER_COEFF_0_25 250
> +#define FILTER_COEFF_0_5 500
> +#define FILTER_COEFF_1_0 1000
> +#define FILTER_COEFF_0_0 0
> +#define SET_POSITIVE_SIGN(x) ((x) & (~SIGN))
> +
>   /**
>    * DOC: Content Adaptive Sharpness Filter (CASF)
>    *
> @@ -31,6 +38,46 @@
>    * original image.
>    */
>   
> +/* Default LUT values to be loaded one time. */
> +static const u16 sharpness_lut[] = {
> +	4095, 2047, 1364, 1022, 816, 678, 579,
> +	504, 444, 397, 357, 323, 293, 268, 244, 224,
> +	204, 187, 170, 154, 139, 125, 111, 98, 85,
> +	73, 60, 48, 36, 24, 12, 0
> +};
> +
> +const u16 filtercoeff_1[] = {
> +	FILTER_COEFF_0_0, FILTER_COEFF_0_0, FILTER_COEFF_0_5,
> +	FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_0,
> +	FILTER_COEFF_0_0,
> +};
> +
> +const u16 filtercoeff_2[] = {
> +	FILTER_COEFF_0_0, FILTER_COEFF_0_25, FILTER_COEFF_0_5,
> +	FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25,
> +	FILTER_COEFF_0_0,
> +};
> +
> +const u16 filtercoeff_3[] = {
> +	FILTER_COEFF_0_125, FILTER_COEFF_0_25, FILTER_COEFF_0_5,
> +	FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25,
> +	FILTER_COEFF_0_125,
> +};
> +
> +void intel_casf_filter_lut_load(struct intel_crtc *crtc,
> +				const struct intel_crtc_state *crtc_state)

This should be static and should be called from intel_casf_enable().


> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	int i;
> +
> +	intel_de_write(display, SHRPLUT_INDEX(crtc->pipe),
> +		       INDEX_AUTO_INCR | INDEX_VALUE(0));
> +
> +	for (i = 0; i < ARRAY_SIZE(sharpness_lut); i++)
> +		intel_de_write(display, SHRPLUT_DATA(crtc->pipe),
> +			       sharpness_lut[i]);
> +}
> +
>   void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h
> index 83523fe66c48..3edbc3ad51cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_casf.h
> +++ b/drivers/gpu/drm/i915/display/intel_casf.h
> @@ -9,9 +9,12 @@
>   #include <linux/types.h>
>   
>   struct intel_crtc_state;
> +struct intel_crtc;
>   
>   int intel_casf_compute_config(struct intel_crtc_state *crtc_state);
>   void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state);
>   void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state);
> +void intel_casf_filter_lut_load(struct intel_crtc *crtc,
> +				const struct intel_crtc_state *crtc_state);
>   
>   #endif /* __INTEL_CASF_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h
> index c24ba281ae37..b96950a48335 100644
> --- a/drivers/gpu/drm/i915/display/intel_casf_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h
> @@ -19,4 +19,15 @@
>   #define   SHARPNESS_FILTER_SIZE_5X5    REG_FIELD_PREP(FILTER_SIZE_MASK, 1)
>   #define   SHARPNESS_FILTER_SIZE_7X7    REG_FIELD_PREP(FILTER_SIZE_MASK, 2)
>   
> +#define _SHRPLUT_DATA_A                        0x682B8
> +#define _SHRPLUT_DATA_B                        0x68AB8
> +#define SHRPLUT_DATA(pipe)             _MMIO_PIPE(pipe, _SHRPLUT_DATA_A, _SHRPLUT_DATA_B)
> +
> +#define _SHRPLUT_INDEX_A               0x682B4
> +#define _SHRPLUT_INDEX_B               0x68AB4

It seems the macros and the registers offsets seems to be not separated 
by tab, but spaces in some places.

Can you check these once?

As per i915_reg.h : “Indent macro values from macro names using TABs"

Regards,

Ankit


> +#define SHRPLUT_INDEX(pipe)            _MMIO_PIPE(pipe, _SHRPLUT_INDEX_A, _SHRPLUT_INDEX_B)
> +#define   INDEX_AUTO_INCR              REG_BIT(10)
> +#define   INDEX_VALUE_MASK             REG_GENMASK(4, 0)
> +#define   INDEX_VALUE(x)               REG_FIELD_PREP(INDEX_VALUE_MASK, (x))
> +
>   #endif /* __INTEL_CASF_REGS__ */