[PATCH v7 00/14] Add support for Common SDP Transmission Line

[PATCH v7 00/14] Add support for Common SDP Transmission Line

[Ankit Nautiyal]

Xe3p_lpd introduces new register bits to program a common SDP
Transmission line that will be used by the Hardware to position the
SDPs. Along with this, another new register is also added to stagger
the different SDPs.

This series adds support for programming the Common SDP Transmission Line
(CMN_SDP_TL) and its stagger control registers.

Rev2:
 - Add tracking for AS SDP Transmission line first. Instead of directly
   programming it in the register, compute the state during
   compute_config_late() and write the value from crtc_state.
   Readout from the register through a vrr helper, since the register is
   defined in context of VRR and will be used for both DP and HDMI VRR
   packets.
 - Add support to track other SDP transmission lines, instead of stagger
   values.
 - Compute the transmission lines in compute_config_late path and add
   readout.
 - Always write the Common SDP Transmission line and other stagger
   values, whether the packets are sent or not.
 - Dump SDP transmission lines in crtc_state.

Rev3:
 - Introduce new files for handling the Data Island Packets (DIPs)
   programming in one place. (Ville)
 - Extract the Transmission Line programming for
   HDMI Extended Metadata Packet (EMP) and Adaptive Sync SDP (AS SDP)
   i.e. EMP_AS_SDP_TL in the new file.
 - Add programming for Common Base SDP Transmission lines and other
   stagger offsets in the new file.
 - Add a #TODO to extract other helpers that deal with Data Island Packets
   and VIDEO_DIP registers.
 - Place the HAS_* Macros related to DIP in the intel_dip.h file
   instead of intel_display_devices.h (Jani) 
 - Make function names more descriptive and avoid overuse of multiple
   acronyms. (Jani)

Note:
 - Though I have fixed the naming as suggested in most places, I
   have retained HAS_EMP_AS_SDP_TL for the following reasons:
   1) Lack of an apt name that avoids the acronym for
      'Extended Metadata Packet Adaptive Sync Secondary Packet Transmission
      Line'.
   2) Keeping this name makes it easier to find and map with the exact name
      for such a complex register name.

   However, I am open to suggestions for a better name.

Rev4:
 - Drop the patch to check for DP encoder before writing EMP_AS_SDP_TL
   register. Instead reset the register to 0 for non DP encoder case.

Rev5:
 - Rebase
 - Address review comments from Suraj:
 - Drop some redundant checks, and fix few commit messages.

Rev6:
 - Move the new struct in intel_display_types.h from intel_dip.h (Jani)
 - Check for CMN_SDP_TL restriction and Warn if not followed. (Suraj)
 - Use HAS_CMN_SDP_TL() instead of checking if cmn_sdp_tl is set or not.
   (Sashiko)
 - Make sure that the guardband is sufficient as per CMN_SDP_TL while
   optiminzing the guardband.

Rev7:
 - Account for VSC SDP's own minimum guardband requirement in
   intel_dp_sdp_min_guardband(), for completeness. (Sashiko)
 - Wrap two long line macro definitions in intel_dip_regs.h.

Ankit Nautiyal (13):
  drm/i915/dip: Add new file to handle Data Island Packet hardware
  drm/i915/vrr: Use the helper to write EMP_AS_SDP_TL register
  drm/i915/intel_dip: Add check for DP encoder
  drm/i915/dip: Add helper to get AS SDP Transmission Line
  drm/i915/display: Add crtc state for DIP transmission lines
  drm/i915/dip: Store and use AS SDP transmission line from crtc state
  drm/i915/dip: Add HAS_COMMON_SDP_TL macro
  drm/i915/dip: Store SDP transmission lines in crtc_state
  drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission
    line
  drm/i915/dip: Enable Common SDP Transmission line
  drm/i915/dp: Account VSC SDP in min guardband
  drm/i915/dp: Adjust SDP guardband requirement for CMN_SDP_TL
  drm/i915/display: Dump DIP Transmission lines

Arun R Murthy (1):
  drm/i915/dip_regs: Add register definitions for common SDP
    Transmission Line

 drivers/gpu/drm/i915/Makefile                 |   1 +
 .../drm/i915/display/intel_crtc_state_dump.c  |   9 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |   5 +
 drivers/gpu/drm/i915/display/intel_dip.c      | 215 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dip.h      |  53 +++++
 drivers/gpu/drm/i915/display/intel_dip_regs.h |  38 ++++
 drivers/gpu/drm/i915/display/intel_display.c  |   6 +
 .../drm/i915/display/intel_display_types.h    |  16 ++
 drivers/gpu/drm/i915/display/intel_dp.c       |  62 ++++-
 drivers/gpu/drm/i915/display/intel_vrr.c      |  14 +-
 drivers/gpu/drm/i915/display/intel_vrr_regs.h |   6 -
 drivers/gpu/drm/xe/Makefile                   |   1 +
 12 files changed, 407 insertions(+), 19 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dip.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_dip.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_dip_regs.h

-- 
2.50.1

[PATCH v7 01/14] drm/i915/dip: Add new file to handle Data Island Packet hardware

[Ankit Nautiyal]

Add new files intel_dip.c, intel_dip.h, and intel_dip_regs.h to handle
low level hardware programming related to Data Island Packets.

Currently only programming of the Transmission Line for HDMI 2.1
Extended Metadata Packet (EMP) and DP Adaptive-Sync Secondary Data
Packet (SDP) is added (MMIO register EMP_AS_SDP_TL).

This will serve as a common place for DIP related code, which is currently
scattered across DP and HDMI files. A TODO has been added for extracting
the remaining DIP helpers.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |  1 +
 drivers/gpu/drm/i915/display/intel_dip.c      | 39 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dip.h      | 38 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dip_regs.h | 18 +++++++++
 drivers/gpu/drm/i915/display/intel_vrr.c      |  1 +
 drivers/gpu/drm/i915/display/intel_vrr_regs.h |  6 ---
 drivers/gpu/drm/xe/Makefile                   |  1 +
 7 files changed, 98 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dip.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_dip.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_dip_regs.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a83fa8be0aba..d4e7764621e1 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -349,6 +349,7 @@ i915-y += \
 	display/intel_cx0_phy.o \
 	display/intel_ddi.o \
 	display/intel_ddi_buf_trans.o \
+	display/intel_dip.o \
 	display/intel_display_device.o \
 	display/intel_display_trace.o \
 	display/intel_dkl_phy.o \
diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
new file mode 100644
index 000000000000..2e2bdb2b199c
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dip.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ *
+ */
+
+#include "intel_de.h"
+#include "intel_dip.h"
+#include "intel_dip_regs.h"
+#include "intel_display_types.h"
+
+u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 val;
+
+	if (!HAS_EMP_AS_SDP_TL(display))
+		return 0;
+
+	val = intel_de_read(display, EMP_AS_SDP_TL(display, cpu_transcoder));
+	return REG_FIELD_GET(EMP_AS_SDP_DB_TL_MASK, val);
+}
+
+void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (!HAS_EMP_AS_SDP_TL(display))
+		return;
+	/*
+	 * Since currently we support VRR only for DP/eDP, so this is programmed
+	 * only for Adaptive Sync SDP to Vsync start.
+	 */
+	intel_de_write(display,
+		       EMP_AS_SDP_TL(display, cpu_transcoder),
+		       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dip.h b/drivers/gpu/drm/i915/display/intel_dip.h
new file mode 100644
index 000000000000..25bae4a04d6b
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dip.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef __INTEL_DIP_H__
+#define __INTEL_DIP_H__
+
+#include "intel_display_device.h"
+
+/*
+ * Video DIP (Data Island Packet) helpers.
+ *
+ * This file contains helpers for programming video DIP related hardware.
+ *
+ * TODO: Currently, this is only used for programming EMP_AS_SDP_TL i.e. to
+ * program Transmission Line for HDMI 2.1 Extended Metadata Packet (EMP) and
+ * DP Adaptive Sync (AS) Secondary Data Packet (SDP). However, all low level
+ * DIP buffer read/write and related helpers should be extracted here later.
+ */
+
+struct intel_crtc_state;
+
+/*
+ * EMP AS SDP TL: Extended Metadata Packet (EMP) Adaptive Sync (AS)
+ * Secondary Data Packet (SDP) Transmission Line (TL).
+ *
+ * Starting with BMG (display ver 14.01) and LNL+ (display ver 20+),
+ * the AS SDP transmission line is programmable via the EMP AS SDP TL
+ * register.
+ */
+#define HAS_EMP_AS_SDP_TL(__display)	(DISPLAY_VERx100(__display) == 1401 || \
+					 DISPLAY_VER(__display) >= 20)
+
+u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
+void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
+
+#endif /* __INTEL_DIP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dip_regs.h b/drivers/gpu/drm/i915/display/intel_dip_regs.h
new file mode 100644
index 000000000000..c4e1dab1ea46
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dip_regs.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef __INTEL_DIP_REGS_H__
+#define __INTEL_DIP_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+/* EMP (Extended Metadata Packet) AS (Adaptive Sync) SDP Transmission Line */
+#define _EMP_AS_SDP_TL_A			0x60204
+#define EMP_AS_SDP_TL(display, trans)		_MMIO_TRANS2((display), (trans), _EMP_AS_SDP_TL_A)
+#define   EMP_AS_SDP_DB_TL_MASK			REG_GENMASK(12, 0)
+#define   EMP_AS_SDP_DB_TL(db_transmit_line)	REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, \
+							       (db_transmit_line))
+
+#endif /* __INTEL_DIP_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index e36db1174440..fd8b6f829cfe 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -17,6 +17,7 @@
 #include "intel_cmtg.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
+#include "intel_dip_regs.h"
 #include "intel_display_limits.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 9d4d6573a149..ba8631cbc672 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -174,12 +174,6 @@
 #define   VRR_VSYNC_START_MASK			REG_GENMASK(12, 0)
 #define   VRR_VSYNC_START(vsync_start)		REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
 
-/* Common register for HDMI EMP and DP AS SDP */
-#define _EMP_AS_SDP_TL_A			0x60204
-#define EMP_AS_SDP_TL(display, trans)		_MMIO_TRANS2((display), (trans), _EMP_AS_SDP_TL_A)
-#define   EMP_AS_SDP_DB_TL_MASK			REG_GENMASK(12, 0)
-#define   EMP_AS_SDP_DB_TL(db_transmit_line)	REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line))
-
 #define _TRANS_CMRR_M_LO_A			0x604F0
 #define TRANS_CMRR_M_LO(display, trans)		_MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_LO_A)
 
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 67b8b5477639..ba4404896f2f 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -259,6 +259,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_ddi.o \
 	i915-display/intel_ddi_buf_trans.o \
 	i915-display/intel_de.o \
+	i915-display/intel_dip.o \
 	i915-display/intel_display.o \
 	i915-display/intel_display_conversion.o \
 	i915-display/intel_display_device.o \
-- 
2.50.1

[PATCH v7 02/14] drm/i915/vrr: Use the helper to write EMP_AS_SDP_TL register

[Ankit Nautiyal]

Now that intel_dip_write_emp_as_sdp_tl() exists, use it instead of
the open-coded EMP_AS_SDP_TL programming sequence in
intel_vrr_set_transcoder_timings().

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index fd8b6f829cfe..a516ba34e0d0 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -17,6 +17,7 @@
 #include "intel_cmtg.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
+#include "intel_dip.h"
 #include "intel_dip_regs.h"
 #include "intel_display_limits.h"
 #include "intel_display_regs.h"
@@ -711,17 +712,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 			       VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
 			       VRR_VSYNC_START(crtc_state->vrr.vsync_start));
 
-	/*
-	 * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
-	 * double buffering point and transmission line for VRR packets for
-	 * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
-	 * Since currently we support VRR only for DP/eDP, so this is programmed
-	 * to for Adaptive Sync SDP to Vsync start.
-	 */
-	if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
-		intel_de_write(display,
-			       EMP_AS_SDP_TL(display, cpu_transcoder),
-			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
+	intel_dip_write_emp_as_sdp_tl(crtc_state);
 }
 
 void
-- 
2.50.1

[PATCH v7 03/14] drm/i915/intel_dip: Add check for DP encoder

[Ankit Nautiyal]

At the moment, the common register for programming Transmission line for
Extended Metadata Packet and Adaptive-Sync Secondary Data Packet
(EMP_AS_SDP_TL) is only used to program Adaptive-Sync SDP (AS SDP).

Since VRR and Video Timing Extended Metadat Packet (VTEMP) are not yet
implemented for HDMI, add an explicit check to write the register only
for DP encoders (that may use AS SDP) and reset the register for non-DP
encoders.

In subsequent changes, instead of directly writing the value,
appropriate helpers will be called, that will supply the transmission line
for these packets.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dip.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
index 2e2bdb2b199c..b28352a9e23f 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.c
+++ b/drivers/gpu/drm/i915/display/intel_dip.c
@@ -26,14 +26,19 @@ void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 transmission_line = 0;
 
 	if (!HAS_EMP_AS_SDP_TL(display))
 		return;
 	/*
-	 * Since currently we support VRR only for DP/eDP, so this is programmed
-	 * only for Adaptive Sync SDP to Vsync start.
+	 * Since we currently support VRR only for DP/eDP, program the register
+	 * for Adaptive Sync SDP using vsync start. For non-DP encoders,
+	 * the register is reset to 0.
 	 */
+	if (intel_crtc_has_dp_encoder(crtc_state))
+		transmission_line = crtc_state->vrr.vsync_start;
+
 	intel_de_write(display,
 		       EMP_AS_SDP_TL(display, cpu_transcoder),
-		       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
+		       EMP_AS_SDP_DB_TL(transmission_line));
 }
-- 
2.50.1

[PATCH v7 04/14] drm/i915/dip: Add helper to get AS SDP Transmission Line

[Ankit Nautiyal]

Introduce a DIP helper to compute the Adaptive Sync SDP transmission line
and use it when programming the EMP_AS_SDP_TL register.

Currently the AS SDP transmission line is programmed to the T1 position.
This can be extended in the future to support programming the T2 position
as well.

While at it, improve the documentation: the AS SDP transmission line
corresponds to the T1 position, which maps to the start of the VSYNC
pulse.

v2:
- Move the helper into intel_dip.c and make it static, since intel_dip.c
  is its only caller.
- Drop the now unused prototype from intel_dp.h.
- Add the check HAS_EMP_AS_SDP_TL(). (Suraj)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> (#v1)
---
 drivers/gpu/drm/i915/display/intel_dip.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
index b28352a9e23f..0277b15e1c82 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.c
+++ b/drivers/gpu/drm/i915/display/intel_dip.c
@@ -9,6 +9,23 @@
 #include "intel_dip_regs.h"
 #include "intel_display_types.h"
 
+static int intel_dip_get_as_sdp_transmission_line(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!HAS_EMP_AS_SDP_TL(display))
+		return 0;
+
+	/*
+	 * EMP_AS_SDP_TL defines the T1 position as the default AS SDP
+	 * Transmission Line, which corresponds to the start of the
+	 * VSYNC pulse.
+	 *
+	 * Use the T1 position for now.
+	 */
+	return crtc_state->vrr.vsync_start;
+}
+
 u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -36,7 +53,7 @@ void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
 	 * the register is reset to 0.
 	 */
 	if (intel_crtc_has_dp_encoder(crtc_state))
-		transmission_line = crtc_state->vrr.vsync_start;
+		transmission_line = intel_dip_get_as_sdp_transmission_line(crtc_state);
 
 	intel_de_write(display,
 		       EMP_AS_SDP_TL(display, cpu_transcoder),
-- 
2.50.1

[PATCH v7 05/14] drm/i915/display: Add crtc state for DIP transmission lines

[Ankit Nautiyal]

The Adaptive Sync SDP is currently the only packet with a programmable
transmission line.

Make a structure struct intel_dip for Data Island Packets. Add a member to
track Adaptive-Sync SDP transmission line. Include the new member in the
pipe configuration comparison.

This will pave the way for supporting more packets' programmable
transmission lines, including the common base SDP transmission line
introduced with Xe3p_lpd.

v2:
 - Move struct intel_dip from intel_dip.h to intel_display_types.h (Jani)
 - Move PIPE_CONF_CHECK for emp_as_sdp_tl in !fastset block. (Sashiko)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> (#v1)
---
 drivers/gpu/drm/i915/display/intel_display.c       |  1 +
 drivers/gpu/drm/i915/display/intel_display_types.h | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9151ea6c15ab..5e8f2e48e95b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5602,6 +5602,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase);
 		PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
 		PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
+		PIPE_CONF_CHECK_I(dip.emp_as_sdp_tl);
 	}
 
 	if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a5f18ac8a7d0..334179685ea2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1007,6 +1007,14 @@ struct intel_casf {
 	bool enable;
 };
 
+struct intel_dip {
+	/*
+	 * DIP Transmission line, relative to the Vtotal.
+	 * The programmed transmit line is (Vtotal - value)
+	 */
+	u16 emp_as_sdp_tl;
+};
+
 struct intel_crtc_state {
 	/*
 	 * uapi (drm) state. This is the software state shown to userspace.
@@ -1315,6 +1323,8 @@ struct intel_crtc_state {
 		struct drm_dp_as_sdp as_sdp;
 	} infoframes;
 
+	struct intel_dip dip;
+
 	u8 eld[MAX_ELD_BYTES];
 
 	/* HDMI scrambling status */
-- 
2.50.1

[PATCH v7 06/14] drm/i915/dip: Store and use AS SDP transmission line from crtc state

[Ankit Nautiyal]

The driver currently computes the Adaptive Sync SDP transmission line
directly at programming time. Instead, compute and store the
AS SDP transmission line in the crtc state and use it when programming the
EMP_AS_SDP_TL register.

We get the clear picture about the SDPs and guardband only in
intel_dp_sdp_compute_config_late() therefore we must configure the
AS SDP transmission line at this point when AS SDP is enabled in
crtc_state.

This prepares the ground for supporting programmable transmission lines
for additional DP SDPs.

While moving the helper into intel_dip.c, drop the
intel_crtc_has_dp_encoder() check instead of relocating it. It was
needed in the old VRR write path shared by other encoderes as well, but
intel_dip_sdp_tl_compute_config_late() is only reached via DP, so HDMI
never sets crtc_state->dip.emp_as_sdp_tl and it stays 0 by default.

v2:
- Move the helper into intel_dip.c and drop the
  intel_crtc_has_dp_encoder() check.
- Drop the redundant checks. (Suraj)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  2 ++
 drivers/gpu/drm/i915/display/intel_dip.c | 20 +++++++++++---------
 drivers/gpu/drm/i915/display/intel_dip.h |  3 +++
 drivers/gpu/drm/i915/display/intel_dp.c  |  3 +++
 4 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9b3b526e5e55..dacb4b7588a0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -49,6 +49,7 @@
 #include "intel_ddi.h"
 #include "intel_ddi_buf_trans.h"
 #include "intel_de.h"
+#include "intel_dip.h"
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
@@ -4235,6 +4236,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
 	intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
 	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
 	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
+	intel_dip_sdp_transmission_line_get_config(pipe_config);
 
 	intel_audio_codec_get_config(encoder, pipe_config);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
index 0277b15e1c82..d1acc7eb5a39 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.c
+++ b/drivers/gpu/drm/i915/display/intel_dip.c
@@ -43,19 +43,21 @@ void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-	u32 transmission_line = 0;
 
 	if (!HAS_EMP_AS_SDP_TL(display))
 		return;
-	/*
-	 * Since we currently support VRR only for DP/eDP, program the register
-	 * for Adaptive Sync SDP using vsync start. For non-DP encoders,
-	 * the register is reset to 0.
-	 */
-	if (intel_crtc_has_dp_encoder(crtc_state))
-		transmission_line = intel_dip_get_as_sdp_transmission_line(crtc_state);
 
 	intel_de_write(display,
 		       EMP_AS_SDP_TL(display, cpu_transcoder),
-		       EMP_AS_SDP_DB_TL(transmission_line));
+		       EMP_AS_SDP_DB_TL(crtc_state->dip.emp_as_sdp_tl));
+}
+
+void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state)
+{
+	crtc_state->dip.emp_as_sdp_tl = intel_dip_get_as_sdp_transmission_line(crtc_state);
+}
+
+void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
+{
+	crtc_state->dip.emp_as_sdp_tl = intel_dip_read_emp_as_sdp_tl(crtc_state);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dip.h b/drivers/gpu/drm/i915/display/intel_dip.h
index 25bae4a04d6b..20f9aeb85c39 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.h
+++ b/drivers/gpu/drm/i915/display/intel_dip.h
@@ -35,4 +35,7 @@ struct intel_crtc_state;
 u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
 void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
 
+void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state);
+void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_DIP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0cd5e6b5034c..8c3a324e164e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -61,6 +61,7 @@
 #include "intel_cx0_phy.h"
 #include "intel_ddi.h"
 #include "intel_de.h"
+#include "intel_dip.h"
 #include "intel_display_driver.h"
 #include "intel_display_jiffies.h"
 #include "intel_display_utils.h"
@@ -7324,6 +7325,8 @@ int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
 		return -EINVAL;
 	}
 
+	intel_dip_sdp_tl_compute_config_late(crtc_state);
+
 	return 0;
 }
 
-- 
2.50.1

[PATCH v7 07/14] drm/i915/dip_regs: Add register definitions for common SDP Transmission Line

[Ankit Nautiyal]

From: Arun R Murthy <arun.r.murthy@intel.com>

Add registers definitions for common SDP transmission line CMN_SDP_TL
and CMN_SDP_TL_STGR_CTL.

v2: Move all registers to intel_dip_regs.h (Ankit)

Bspec: 74384
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dip_regs.h | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dip_regs.h b/drivers/gpu/drm/i915/display/intel_dip_regs.h
index c4e1dab1ea46..d7e40a613913 100644
--- a/drivers/gpu/drm/i915/display/intel_dip_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dip_regs.h
@@ -15,4 +15,24 @@
 #define   EMP_AS_SDP_DB_TL(db_transmit_line)	REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, \
 							       (db_transmit_line))
 
+/* COMMON SDP TRANSMISSION LINE */
+#define _CMN_SDP_TL_A			0x6020c
+#define CMN_SDP_TL(display, trans)	_MMIO_TRANS2(display, (trans), _CMN_SDP_TL_A)
+#define  TRANSMISSION_LINE_ENABLE	REG_BIT(31)
+#define  BASE_TRANSMISSION_LINE_MASK	REG_GENMASK(12, 0)
+#define  BASE_TRANSMISSION_LINE(x)	REG_FIELD_PREP(BASE_TRANSMISSION_LINE_MASK, x)
+
+#define _CMN_SDP_TL_STGR_CTL_A			0x60214
+#define CMN_SDP_TL_STGR_CTL(display, trans)	_MMIO_TRANS2(display, (trans), \
+							     _CMN_SDP_TL_STGR_CTL_A)
+#define  VSC_EXT_STAGGER_MASK			REG_GENMASK(11, 8)
+#define  VSC_EXT_STAGGER(x)			REG_FIELD_PREP(VSC_EXT_STAGGER_MASK, x)
+#define  VSC_EXT_STAGGER_DEFAULT		0x2
+#define  PPS_STAGGER_MASK			REG_GENMASK(7, 4)
+#define  PPS_STAGGER(x)				REG_FIELD_PREP(PPS_STAGGER_MASK, x)
+#define  PPS_STAGGER_DEFAULT			0x1
+#define  GMP_STAGGER_MASK			REG_GENMASK(3, 0)
+#define  GMP_STAGGER(x)				REG_FIELD_PREP(GMP_STAGGER_MASK, x)
+#define  GMP_STAGGER_DEFAULT			0x0
+
 #endif /* __INTEL_DIP_REGS_H__ */
-- 
2.50.1

[PATCH v7 08/14] drm/i915/dip: Add HAS_COMMON_SDP_TL macro

[Ankit Nautiyal]

Add a helper macro to detect CMN SDP TL support on platforms with display
version 35 and above.

v2: Use prefix drm/i915/dip. (Suraj)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dip.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dip.h b/drivers/gpu/drm/i915/display/intel_dip.h
index 20f9aeb85c39..8ff22eb5663b 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.h
+++ b/drivers/gpu/drm/i915/display/intel_dip.h
@@ -32,6 +32,16 @@ struct intel_crtc_state;
 #define HAS_EMP_AS_SDP_TL(__display)	(DISPLAY_VERx100(__display) == 1401 || \
 					 DISPLAY_VER(__display) >= 20)
 
+/*
+ * CMN SDP TL: Common Secondary Data Packet Transmission Line.
+ *
+ * Xe3p_lpd introduces new register CMN_SDP_TL to program a common SDP
+ * Transmission line that will be used by the Hardware to position the
+ * SDPs. Along with this, another new register CMN_SDP_TL_STGR_CTL is
+ * also added to stagger the different SDPs.
+ */
+#define HAS_COMMON_SDP_TL(__display)      (DISPLAY_VER(__display) >= 35)
+
 u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
 void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
 
-- 
2.50.1

[PATCH v7 09/14] drm/i915/dip: Store SDP transmission lines in crtc_state

[Ankit Nautiyal]

Currently the driver only programs the transmission line for the
Adaptive-Sync SDP, while the hardware controls the transmission lines for
other SDPs.

Starting with Xe3p_lpd, the hardware allows the driver to program
transmission lines for additional DP SDPs. Prepare for this by adding
fields to struct intel_crtc_state to store SDP transmission lines, and
include them in pipe config comparison.

The SDP transmission line fields track vrr.vsync_start/vtotal, which are
allowed to change during a seamless LRR fastset. Guard their pipe config
comparison under !fastset, same as vrr.vsync_start/vsync_end, so a fastset
is not unnecessarily turned into a full modeset.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c       | 5 +++++
 drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5e8f2e48e95b..e052c5ad99d9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5603,6 +5603,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
 		PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
 		PIPE_CONF_CHECK_I(dip.emp_as_sdp_tl);
+		PIPE_CONF_CHECK_I(dip.gmp_sdp_tl);
+		PIPE_CONF_CHECK_I(dip.pps_sdp_tl);
+		PIPE_CONF_CHECK_I(dip.vsc_sdp_tl);
+		PIPE_CONF_CHECK_I(dip.vsc_ext_sdp_tl);
+		PIPE_CONF_CHECK_I(dip.cmn_sdp_tl);
 	}
 
 	if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 334179685ea2..79f30660c2b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1013,6 +1013,12 @@ struct intel_dip {
 	 * The programmed transmit line is (Vtotal - value)
 	 */
 	u16 emp_as_sdp_tl;
+	u16 gmp_sdp_tl;
+	u16 pps_sdp_tl;
+	u16 vsc_sdp_tl;
+	u16 vsc_ext_sdp_tl;
+	/* Common SDP Base transmission line (Xe3p_lpd+) */
+	u16 cmn_sdp_tl;
 };
 
 struct intel_crtc_state {
-- 
2.50.1

[PATCH v7 10/14] drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission line

[Ankit Nautiyal]

Introduce helpers to program or disable CMN_SDP_TL and stagger registers
using the state stored in crtc_state.

v2:
- Use HAS_COMMON_SDP_TL(display) instead of checking
  crtc_state->dip.cmn_sdp_tl, since 0 is a valid transmission line value.
  (Sashiko)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dip.c | 56 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dip.h |  2 +
 2 files changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
index d1acc7eb5a39..f8e8577b2755 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.c
+++ b/drivers/gpu/drm/i915/display/intel_dip.c
@@ -4,6 +4,8 @@
  *
  */
 
+#include <drm/drm_print.h>
+
 #include "intel_de.h"
 #include "intel_dip.h"
 #include "intel_dip_regs.h"
@@ -61,3 +63,57 @@ void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_st
 {
 	crtc_state->dip.emp_as_sdp_tl = intel_dip_read_emp_as_sdp_tl(crtc_state);
 }
+
+static int intel_dip_sdp_tl_to_stagger(const struct intel_crtc_state *crtc_state,
+				       u16 sdp_transmission_line)
+{
+	return sdp_transmission_line - crtc_state->dip.cmn_sdp_tl;
+}
+
+void intel_dip_cmn_sdp_transmission_line_enable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	int gmp_stagger;
+	int pps_stagger;
+	int vsc_ext_stagger;
+
+	if (!HAS_COMMON_SDP_TL(display))
+		return;
+
+	gmp_stagger = intel_dip_sdp_tl_to_stagger(crtc_state,
+						  crtc_state->dip.gmp_sdp_tl);
+
+	pps_stagger = intel_dip_sdp_tl_to_stagger(crtc_state,
+						  crtc_state->dip.pps_sdp_tl);
+
+	vsc_ext_stagger = intel_dip_sdp_tl_to_stagger(crtc_state,
+						      crtc_state->dip.vsc_ext_sdp_tl);
+
+	if (drm_WARN_ON(display->drm, gmp_stagger < 0))
+		return;
+	if (drm_WARN_ON(display->drm, pps_stagger < 0))
+		return;
+	if (drm_WARN_ON(display->drm, vsc_ext_stagger < 0))
+		return;
+
+	intel_de_write(display, CMN_SDP_TL_STGR_CTL(display, cpu_transcoder),
+		       GMP_STAGGER(gmp_stagger) |
+		       PPS_STAGGER(pps_stagger) |
+		       VSC_EXT_STAGGER(vsc_ext_stagger));
+
+	intel_de_write(display, CMN_SDP_TL(display, cpu_transcoder),
+		       TRANSMISSION_LINE_ENABLE |
+		       BASE_TRANSMISSION_LINE(crtc_state->dip.cmn_sdp_tl));
+}
+
+void intel_dip_cmn_sdp_transmission_line_disable(const struct intel_crtc_state *old_crtc_state)
+{
+	struct intel_display *display = to_intel_display(old_crtc_state);
+	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+
+	if (!HAS_COMMON_SDP_TL(display))
+		return;
+
+	intel_de_write(display, CMN_SDP_TL(display, cpu_transcoder), 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dip.h b/drivers/gpu/drm/i915/display/intel_dip.h
index 8ff22eb5663b..7c64c84cb1be 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.h
+++ b/drivers/gpu/drm/i915/display/intel_dip.h
@@ -47,5 +47,7 @@ void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
 
 void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state);
 void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state);
+void intel_dip_cmn_sdp_transmission_line_enable(const struct intel_crtc_state *crtc_state);
+void intel_dip_cmn_sdp_transmission_line_disable(const struct intel_crtc_state *old_crtc_state);
 
 #endif /* __INTEL_DIP_H__ */
-- 
2.50.1

[PATCH v7 11/14] drm/i915/dip: Enable Common SDP Transmission line

[Ankit Nautiyal]

Enable programming of the common SDP transmission line on platforms that
support it. Compute and program the common base transmission line and
per-SDP stagger values from the crtc state during modeset, and disable the
feature on pipe disable.

Currently, the stagger values are set as per the default policy of the
Hardware. This can be optimized later if we come up with a specific driver
policy to sequence the SDPs better.

v2: Add WARN if the Common Transmission Line is more than Guardband +
SCL. (Suraj)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  3 +
 drivers/gpu/drm/i915/display/intel_dip.c | 96 ++++++++++++++++++++++++
 2 files changed, 99 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index dacb4b7588a0..3cdb06e81130 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2737,6 +2737,8 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	/* 6.o Configure and enable FEC if needed */
 	intel_ddi_enable_fec(encoder, crtc_state);
 
+	intel_dip_cmn_sdp_transmission_line_enable(crtc_state);
+
 	/* 7.a 128b/132b SST. */
 	if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
 		/* VCPID 1, start slot 0 for 128b/132b, tu slots */
@@ -3124,6 +3126,7 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder,
 			     DP_TP_CTL_ENABLE, 0);
 	}
 
+	intel_dip_cmn_sdp_transmission_line_disable(crtc_state);
 	intel_ddi_disable_fec(encoder, crtc_state);
 
 	if (DISPLAY_VER(display) < 14)
diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
index f8e8577b2755..f447150ff7bc 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.c
+++ b/drivers/gpu/drm/i915/display/intel_dip.c
@@ -10,6 +10,7 @@
 #include "intel_dip.h"
 #include "intel_dip_regs.h"
 #include "intel_display_types.h"
+#include "intel_hdmi.h"
 
 static int intel_dip_get_as_sdp_transmission_line(const struct intel_crtc_state *crtc_state)
 {
@@ -54,14 +55,109 @@ void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
 		       EMP_AS_SDP_DB_TL(crtc_state->dip.emp_as_sdp_tl));
 }
 
+static int intel_dip_sdp_stagger_to_tl(struct intel_crtc_state *crtc_state,
+				       int stagger)
+{
+	return crtc_state->dip.cmn_sdp_tl + stagger;
+}
+
+static
+void intel_dip_cmn_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	bool as_sdp;
+
+	if (!HAS_COMMON_SDP_TL(display))
+		return;
+
+	as_sdp = crtc_state->infoframes.enable &
+		 intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
+	/*
+	 * When AS SDP is enabled :
+	 *  - The common SDP Transmission Line matches the EMP SDP Transmission Line.
+	 *
+	 * When AS SDP is disabled:
+	 *  - Bspec mentions the positions as lines of delayed vblank.
+	 *  - Guardband = 1st line of delayed vblank
+	 *  - Common SDP Transmission line is set to 2nd line of delayed vblank.
+	 */
+
+	if (as_sdp)
+		crtc_state->dip.cmn_sdp_tl = crtc_state->dip.emp_as_sdp_tl;
+	else
+		crtc_state->dip.cmn_sdp_tl = crtc_state->vrr.guardband - 1;
+
+	if (drm_WARN_ON(display->drm,
+			crtc_state->dip.cmn_sdp_tl >=
+			crtc_state->vrr.guardband + crtc_state->set_context_latency))
+		return;
+
+	/*
+	 * Currently we are programming the default stagger values, but these
+	 * can be optimized if required, based on number of SDPs enabled.
+	 *
+	 * Default values of the Transmission lines for SDPs other than AS SDP:
+	 * VSC : CMN SDP Transmission line
+	 * GMP : CMN SDP Transmission line
+	 * PPS : CMN SDP Transmission line + 1
+	 * VSC_EXT: CMN SDP Transmission line + 2
+	 */
+	crtc_state->dip.vsc_sdp_tl = crtc_state->dip.cmn_sdp_tl;
+	crtc_state->dip.gmp_sdp_tl =
+		intel_dip_sdp_stagger_to_tl(crtc_state, GMP_STAGGER_DEFAULT);
+	crtc_state->dip.pps_sdp_tl =
+		intel_dip_sdp_stagger_to_tl(crtc_state, PPS_STAGGER_DEFAULT);
+	crtc_state->dip.vsc_ext_sdp_tl =
+		intel_dip_sdp_stagger_to_tl(crtc_state, VSC_EXT_STAGGER_DEFAULT);
+}
+
 void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state)
 {
 	crtc_state->dip.emp_as_sdp_tl = intel_dip_get_as_sdp_transmission_line(crtc_state);
+
+	intel_dip_cmn_sdp_tl_compute_config_late(crtc_state);
+}
+
+static
+void intel_dip_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u16 vsc_ext_stagger, pps_stagger, gmp_stagger;
+	u32 val;
+
+	if (!HAS_COMMON_SDP_TL(display))
+		return;
+
+	val = intel_de_read(display, CMN_SDP_TL(display, cpu_transcoder));
+
+	if (!(val & TRANSMISSION_LINE_ENABLE))
+		return;
+
+	crtc_state->dip.cmn_sdp_tl = REG_FIELD_GET(BASE_TRANSMISSION_LINE_MASK, val);
+
+	/* SDP VSC uses same transmission line as CMN base transmission line */
+	crtc_state->dip.vsc_sdp_tl = crtc_state->dip.cmn_sdp_tl;
+
+	val = intel_de_read(display, CMN_SDP_TL_STGR_CTL(display, cpu_transcoder));
+
+	vsc_ext_stagger = REG_FIELD_GET(VSC_EXT_STAGGER_MASK, val);
+	pps_stagger = REG_FIELD_GET(PPS_STAGGER_MASK, val);
+	gmp_stagger = REG_FIELD_GET(GMP_STAGGER_MASK, val);
+
+	crtc_state->dip.vsc_ext_sdp_tl =
+		intel_dip_sdp_stagger_to_tl(crtc_state, vsc_ext_stagger);
+	crtc_state->dip.pps_sdp_tl =
+		intel_dip_sdp_stagger_to_tl(crtc_state, pps_stagger);
+	crtc_state->dip.gmp_sdp_tl =
+		intel_dip_sdp_stagger_to_tl(crtc_state, gmp_stagger);
 }
 
 void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
 {
 	crtc_state->dip.emp_as_sdp_tl = intel_dip_read_emp_as_sdp_tl(crtc_state);
+
+	intel_dip_cmn_sdp_transmission_line_get_config(crtc_state);
 }
 
 static int intel_dip_sdp_tl_to_stagger(const struct intel_crtc_state *crtc_state,
-- 
2.50.1

[PATCH v7 12/14] drm/i915/dp: Account VSC SDP in min guardband

[Ankit Nautiyal]

The transmission line for VSC SDP is the same as AS SDP
(EMP_AS_SDP_TL) when AS SDP is enabled. Otherwise, it uses the
second line of delayed vblank. For VSC without AS SDP, this
requires 2 lines plus 1 setup line, so the VRR guardband must be
at least 3 lines.

When both AS SDP and VSC SDP are enabled, the guardband
requirement is already accounted for during optimized guardband
calculation and the final guardband validation in
compute_config_late(). However, when VSC SDP is enabled without
AS SDP, the VSC SDP requirement is not checked explicitly.

Even in the unlikely case where the optimized guardband is
clamped to vblank length, it cannot fall below 5 lines since such
modes are already pruned. Still, for completeness, account for
VSC SDP and ensure a minimum guardband of 3 lines.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8c3a324e164e..018dc6303dfe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7359,6 +7359,8 @@ int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 ty
 		return 8;
 	case DP_SDP_PPS:
 		return 7;
+	case DP_SDP_VSC:
+		return 3;
 	case DP_SDP_ADAPTIVE_SYNC:
 		return crtc_state->vrr.vsync_start + 1;
 	default:
@@ -7390,6 +7392,11 @@ int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 		sdp_guardband = max(sdp_guardband,
 				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_ADAPTIVE_SYNC));
 
+	if (crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
+		sdp_guardband = max(sdp_guardband,
+				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_VSC));
+
 	return sdp_guardband;
 }
 
-- 
2.50.1

[PATCH v7 13/14] drm/i915/dp: Adjust SDP guardband requirement for CMN_SDP_TL

[Ankit Nautiyal]

Once CMN_SDP_TL is enabled, GMP/PPS/VSC/VSC_EXT/AS SDPs are no longer
positioned relative to the guardband: they are anchored via
CMN_SDP_TL/CMN_SDP_TL_STGR_CTL instead. As per Bspec 68921, SDP Setup is
0 in this mode, so the old per-packet guardband sizing (based on
GMP/PPS/AS-SDP being enabled) no longer applies for GMP/PPS/VSC/VSC_EXT.

Since we are using the default stagger values for now, size the guardband
such that the max default transmission line can be supported, similar to
when CMN SDP TL is not set:

base   : 2nd line of delayed vblank
GMP    : 2 + GMP_STAGGER
VSC_EXT: 2 + VSC_EXT_STAGGER
VSC    : 2
PPS    : 2 + PPS_STAGGER

SDP Setup = 1 + MAX(GMP, VSC_EXT, VSC, PPS setup lines)

Add intel_dp_get_lines_for_cmn_sdp_tl() and route it via the existing
intel_dp_get_lines_for_sdp().

The AS SDP check in intel_dp_sdp_min_guardband() still adds
vrr.vsync_start + 1 to the guardband, since AS SDP positioning is
unaffected by CMN_SDP_TL.

v2: Add VSC min SDP guardband. (Sashiko)

Bspec: 68921
Assisted-by: Copilot:claude-sonnet-4.5
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 52 ++++++++++++++++++++++++-
 1 file changed, 50 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 018dc6303dfe..f13f17d67d5a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -62,6 +62,7 @@
 #include "intel_ddi.h"
 #include "intel_de.h"
 #include "intel_dip.h"
+#include "intel_dip_regs.h"
 #include "intel_display_driver.h"
 #include "intel_display_jiffies.h"
 #include "intel_display_utils.h"
@@ -7348,9 +7349,58 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
 	return 0;
 }
 
+static
+int intel_dp_get_lines_for_cmn_sdp_tl(u32 type)
+{
+	u32 stagger_val;
+
+	/*
+	 * Since we are using default stagger values similar to the case
+	 * where CMN SDP TL is not set, the different SDP transmission
+	 * lines are:
+	 * base : 2nd line of delayed vblank:
+	 * GMP : 2 + GMP_STAGGER
+	 * VSC_EXT: 2 + VSC_EXT_STAGGER
+	 * VSC : 2
+	 * PPS : 2 + PPS_STAGGER
+	 *
+	 * SDP Setup = 1 + MAX(GMP, VSC_EXT, VSC, PPS setup lines)
+	 *
+	 * For EMP_AS_SDP_TL guardband should be more than vrr.vsync_start.
+	 */
+
+	switch (type) {
+	case DP_SDP_VSC_EXT_VESA:
+	case DP_SDP_VSC_EXT_CEA:
+		stagger_val = VSC_EXT_STAGGER_DEFAULT;
+		break;
+	case HDMI_PACKET_TYPE_GAMUT_METADATA:
+		stagger_val = GMP_STAGGER_DEFAULT;
+		break;
+	case DP_SDP_PPS:
+		stagger_val = PPS_STAGGER_DEFAULT;
+		break;
+	case DP_SDP_VSC:
+		stagger_val = 0;
+		break;
+	default:
+		return 0;
+	}
+
+	return 1 + 2 + stagger_val;
+}
+
 static
 int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 type)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (type == DP_SDP_ADAPTIVE_SYNC)
+		return crtc_state->vrr.vsync_start + 1;
+
+	if (HAS_COMMON_SDP_TL(display))
+		return intel_dp_get_lines_for_cmn_sdp_tl(type);
+
 	switch (type) {
 	case DP_SDP_VSC_EXT_VESA:
 	case DP_SDP_VSC_EXT_CEA:
@@ -7361,8 +7411,6 @@ int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 ty
 		return 7;
 	case DP_SDP_VSC:
 		return 3;
-	case DP_SDP_ADAPTIVE_SYNC:
-		return crtc_state->vrr.vsync_start + 1;
 	default:
 		break;
 	}
-- 
2.50.1

[PATCH v7 14/14] drm/i915/display: Dump DIP Transmission lines

[Ankit Nautiyal]

Add DIP transmission lines to the CRTC state dump.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index ad4f362e0c09..92675a88b969 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -251,6 +251,15 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 			   str_enabled_disabled(pipe_config->has_panel_replay),
 			   str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));
 		drm_printf(&p, "minimum hblank: %d\n", pipe_config->min_hblank);
+
+		drm_printf(&p, "DIP Transmission Lines: EMP/AS SDP: %u\n",
+			   pipe_config->dip.emp_as_sdp_tl);
+		drm_printf(&p, "DIP Transmission Lines: Common Base SDP: %u, GMP SDP: %u, PPS SDP: %u, VSC SDP: %u, VSC_EXT SDP: %u\n",
+			   pipe_config->dip.cmn_sdp_tl,
+			   pipe_config->dip.gmp_sdp_tl,
+			   pipe_config->dip.pps_sdp_tl,
+			   pipe_config->dip.vsc_sdp_tl,
+			   pipe_config->dip.vsc_ext_sdp_tl);
 	}
 
 	drm_printf(&p, "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
-- 
2.50.1

Re: [PATCH v7 06/14] drm/i915/dip: Store and use AS SDP transmission line from crtc state

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/dip: Spurious state mismatch for EMP_AS_SDP_TL on HDMI fastsets
--

commit 33aef03ce9383e1676d66a385c5b27a724956776
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Subject: drm/i915/dip: Store and use AS SDP transmission line from crtc state

The driver computes and stores the Adaptive Sync SDP transmission line in the
crtc state and uses it when programming the EMP_AS_SDP_TL register. This
prepares the ground for supporting programmable transmission lines for
additional DP SDPs.

> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9b3b526e5e55b..dacb4b7588a02 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
[ ... ]
> @@ -4235,6 +4236,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
>  	intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
>  	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
>  	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
> +	intel_dip_sdp_transmission_line_get_config(pipe_config);

[Severity: Medium]
Will this trigger a spurious state mismatch for EMP_AS_SDP_TL on HDMI fastsets?

If a non-DP (e.g., HDMI) connection inherits a non-zero EMP_AS_SDP_TL value
from a BIOS handover or a previous DP VRR mode, the hardware state
(hw_crtc_state) will reflect this non-zero value.

This happens because intel_dip_sdp_transmission_line_get_config()
unconditionally reads the register here via intel_dip_read_emp_as_sdp_tl()
without verifying if the encoder is DP:

drivers/gpu/drm/i915/display/intel_dip.c:intel_dip_read_emp_as_sdp_tl() {
    ...
    val = intel_de_read(display, EMP_AS_SDP_TL(display, cpu_transcoder));
    return REG_FIELD_GET(EMP_AS_SDP_DB_TL_MASK, val);
}

Meanwhile, the software state (sw_crtc_state) expects 0 for HDMI since
intel_dip_sdp_tl_compute_config_late() is only called for DP.

Because the dip.emp_as_sdp_tl comparison is guarded by if (!fastset) in
intel_pipe_config_compare(), the discrepancy is ignored during the fastset
compatibility check, allowing a fastset to proceed.

The fastset skips reprogramming the VRR transcoder timings, leaving the
hardware register at its stale non-zero value.

During post-commit hardware verification in verify_crtc_state(),
intel_pipe_config_compare() is called with fastset = false, which strictly
checks the field. This causes a drm_WARN backtrace when comparing the expected
0 against the stale non-zero hardware value.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915164657.3429075-1-ankit.k.nautiyal@intel.com?part=6

Re: [PATCH v7 11/14] drm/i915/dip: Enable Common SDP Transmission line

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/dip: Missing CMN_SDP_TL programming for DP MST slave transcoders
--

commit de3a67cbeba4a6e70cc767d1dce1950454f58dfa
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/dip: Enable Common SDP Transmission line

This commit enables programming of the common SDP transmission line on
supported platforms. It computes and programs the base transmission line
and stagger values during modeset. It also disables the feature on pipe
disable.

> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index dacb4b7588a02..3cdb06e81130b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2737,6 +2737,8 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  	/* 6.o Configure and enable FEC if needed */
>  	intel_ddi_enable_fec(encoder, crtc_state);
>  
> +	intel_dip_cmn_sdp_transmission_line_enable(crtc_state);
> +

[Severity: Medium]
Will placing this transcoder-specific initialization in mtl_ddi_pre_enable_dp()
cause it to be skipped for subsequent MST streams? 

In DP MST configurations, mst_stream_pre_enable() invokes the primary encoder's
pre_enable hook (mtl_ddi_pre_enable_dp()) solely for the first active MST
stream.

Because intel_dip_cmn_sdp_transmission_line_enable() is called here, it
appears it will be skipped for all subsequent streams. This would leave the
CMN_SDP_TL registers uninitialized for slave transcoders, potentially causing
broken or mistimed SDP transmission on secondary MST monitors.

>  	/* 7.a 128b/132b SST. */
>  	if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
>  		/* VCPID 1, start slot 0 for 128b/132b, tu slots */
[ ... ]
> @@ -3124,6 +3126,7 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder,
>  			     DP_TP_CTL_ENABLE, 0);
>  	}
>  
> +	intel_dip_cmn_sdp_transmission_line_disable(crtc_state);

[Severity: Medium]
Does placing this disable routine in intel_ddi_buf_disable() prevent it from
executing for slave transcoders during MST teardown? 

Similar to the enable path, intel_ddi_buf_disable() is only called for the
last active stream during teardown, which means the CMN_SDP_TL disable routine
would be skipped for slave streams.

>  	intel_ddi_disable_fec(encoder, crtc_state);
>  
>  	if (DISPLAY_VER(display) < 14)

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915164657.3429075-1-ankit.k.nautiyal@intel.com?part=11

✗ CI.checkpatch: warning for Add support for Common SDP Transmission Line (rev7)

[Patchwork]

== Series Details ==

Series: Add support for Common SDP Transmission Line (rev7)
URL   : https://patchwork.freedesktop.org/series/162623/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
d875049d2b299159a272bd5151994970cdcd1e31
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit b91996d8ac496cca7bbe93b7f9305bf3614856cd
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Date:   Tue Sep 15 22:16:55 2026 +0530

    drm/i915/display: Dump DIP Transmission lines
    
    Add DIP transmission lines to the CRTC state dump.
    
    Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
    Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
+ /mt/dim checkpatch 0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8 drm-intel
e9e21f968703 drm/i915/dip: Add new file to handle Data Island Packet hardware
-:34: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

-:115: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__display' - possible side-effects?
#115: FILE: drivers/gpu/drm/i915/display/intel_dip.h:32:
+#define HAS_EMP_AS_SDP_TL(__display)	(DISPLAY_VERx100(__display) == 1401 || \
+					 DISPLAY_VER(__display) >= 20)

total: 0 errors, 1 warnings, 1 checks, 128 lines checked
d74f316515fa drm/i915/vrr: Use the helper to write EMP_AS_SDP_TL register
e9d5fcf6fb96 drm/i915/intel_dip: Add check for DP encoder
031f4f54c5d5 drm/i915/dip: Add helper to get AS SDP Transmission Line
5d797e1ce718 drm/i915/display: Add crtc state for DIP transmission lines
b97913e0991e drm/i915/dip: Store and use AS SDP transmission line from crtc state
9a1b18b08311 drm/i915/dip_regs: Add register definitions for common SDP Transmission Line
58c41e3f3597 drm/i915/dip: Add HAS_COMMON_SDP_TL macro
691b99257ac6 drm/i915/dip: Store SDP transmission lines in crtc_state
686cae1e3b7a drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission line
9c8cc22e6d15 drm/i915/dip: Enable Common SDP Transmission line
1de9816f582b drm/i915/dp: Account VSC SDP in min guardband
a2077e42a734 drm/i915/dp: Adjust SDP guardband requirement for CMN_SDP_TL
b91996d8ac49 drm/i915/display: Dump DIP Transmission lines

✓ CI.KUnit: success for Add support for Common SDP Transmission Line (rev7)

[Patchwork]

== Series Details ==

Series: Add support for Common SDP Transmission Line (rev7)
URL   : https://patchwork.freedesktop.org/series/162623/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[17:31:05] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:31:09] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:31:29] Starting KUnit Kernel (1/1)...
[17:31:29] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:31:29] ============= refcount_interrupt (4 subtests) ==============
[17:31:29] [PASSED] test_single_irq_change
[17:31:29] [PASSED] test_nested_irq_change
[17:31:29] [PASSED] test_multiple_irq_change
[17:31:29] [PASSED] test_irq_save
[17:31:29] =============== [PASSED] refcount_interrupt ================
[17:31:29] ================= gpu_buddy (14 subtests) ==================
[17:31:29] [PASSED] gpu_test_buddy_alloc_limit
[17:31:29] [PASSED] gpu_test_buddy_alloc_optimistic
[17:31:29] [PASSED] gpu_test_buddy_alloc_pessimistic
[17:31:29] [PASSED] gpu_test_buddy_alloc_pathological
[17:31:29] [PASSED] gpu_test_buddy_alloc_contiguous
[17:31:29] [PASSED] gpu_test_buddy_alloc_clear
[17:31:29] [PASSED] gpu_test_buddy_alloc_range
[17:31:30] [PASSED] gpu_test_buddy_alloc_range_bias
[17:31:31] [PASSED] gpu_test_buddy_fragmentation_performance
[17:31:31] [PASSED] gpu_test_buddy_dirty_tracker_performance
[17:31:31] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[17:31:31] [PASSED] gpu_test_buddy_offset_aligned_allocation
[17:31:31] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[17:31:31] [PASSED] gpu_test_buddy_addr_to_block
[17:31:31] ==================== [PASSED] gpu_buddy ====================
[17:31:31] ============================================================
[17:31:31] Testing complete. Ran 18 tests: passed: 18
[17:31:31] Elapsed time: 26.541s total, 4.329s configuring, 20.294s building, 1.874s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[17:31:31] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:31:33] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:32:07] Starting KUnit Kernel (1/1)...
[17:32:07] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:32:07] ============= refcount_interrupt (4 subtests) ==============
[17:32:07] [PASSED] test_single_irq_change
[17:32:07] [PASSED] test_nested_irq_change
[17:32:07] [PASSED] test_multiple_irq_change
[17:32:07] [PASSED] test_irq_save
[17:32:07] =============== [PASSED] refcount_interrupt ================
[17:32:07] ================== guc_buf (11 subtests) ===================
[17:32:07] [PASSED] test_smallest
[17:32:07] [PASSED] test_largest
[17:32:07] [PASSED] test_granular
[17:32:07] [PASSED] test_unique
[17:32:07] [PASSED] test_overlap
[17:32:07] [PASSED] test_reusable
[17:32:07] [PASSED] test_too_big
[17:32:07] [PASSED] test_flush
[17:32:07] [PASSED] test_lookup
[17:32:07] [PASSED] test_data
[17:32:07] [PASSED] test_class
[17:32:07] ===================== [PASSED] guc_buf =====================
[17:32:07] =================== guc_dbm (7 subtests) ===================
[17:32:07] [PASSED] test_empty
[17:32:07] [PASSED] test_default
[17:32:07] ======================== test_size  ========================
[17:32:07] [PASSED] 4
[17:32:07] [PASSED] 8
[17:32:07] [PASSED] 32
[17:32:07] [PASSED] 256
[17:32:07] ==================== [PASSED] test_size ====================
[17:32:07] ======================= test_reuse  ========================
[17:32:07] [PASSED] 4
[17:32:07] [PASSED] 8
[17:32:07] [PASSED] 32
[17:32:07] [PASSED] 256
[17:32:07] =================== [PASSED] test_reuse ====================
[17:32:07] =================== test_range_overlap  ====================
[17:32:07] [PASSED] 4
[17:32:07] [PASSED] 8
[17:32:07] [PASSED] 32
[17:32:07] [PASSED] 256
[17:32:07] =============== [PASSED] test_range_overlap ================
[17:32:07] =================== test_range_compact  ====================
[17:32:07] [PASSED] 4
[17:32:07] [PASSED] 8
[17:32:07] [PASSED] 32
[17:32:07] [PASSED] 256
[17:32:07] =============== [PASSED] test_range_compact ================
[17:32:07] ==================== test_range_spare  =====================
[17:32:07] [PASSED] 4
[17:32:07] [PASSED] 8
[17:32:07] [PASSED] 32
[17:32:07] [PASSED] 256
[17:32:07] ================ [PASSED] test_range_spare =================
[17:32:07] ===================== [PASSED] guc_dbm =====================
[17:32:07] =================== guc_idm (6 subtests) ===================
[17:32:07] [PASSED] bad_init
[17:32:07] [PASSED] no_init
[17:32:07] [PASSED] init_fini
[17:32:07] [PASSED] check_used
[17:32:07] [PASSED] check_quota
[17:32:07] [PASSED] check_all
[17:32:07] ===================== [PASSED] guc_idm =====================
[17:32:07] =============== guc_klv_helpers (9 subtests) ===============
[17:32:07] [PASSED] test_count
[17:32:07] [PASSED] test_encode_u32
[17:32:07] [PASSED] test_encode_u64
[17:32:07] [PASSED] test_encode_string
[17:32:07] [PASSED] test_encode_object_raw
[17:32:07] [PASSED] test_encode_object_klv
[17:32:07] [PASSED] test_encode_object_nested
[17:32:07] [PASSED] test_encode_object_basic
[17:32:07] [PASSED] test_print
[17:32:07] ================= [PASSED] guc_klv_helpers =================
[17:32:07] =================== xe_log (4 subtests) ====================
[17:32:07] [PASSED] demo_cper
[17:32:07] [PASSED] demo_dmesg
[17:32:07] ======================= test_dmesg  ========================
[17:32:07] [PASSED] test_fatal
[17:32:07] [PASSED] test_fatal_tile
[17:32:07] [PASSED] test_fatal_gt
[17:32:07] [PASSED] test_fatal_comp
[17:32:07] [PASSED] test_fatal_comp_tile
[17:32:07] [PASSED] test_fatal_comp_gt
[17:32:07] [PASSED] test_fatal_all
[17:32:07] [PASSED] test_recoverable
[17:32:07] [PASSED] test_recoverable_tile
[17:32:07] [PASSED] test_recoverable_gt
[17:32:07] [PASSED] test_recoverable_comp
[17:32:07] [PASSED] test_recoverable_comp_tile
[17:32:07] [PASSED] test_recoverable_comp_gt
[17:32:07] [PASSED] test_recoverable_all
[17:32:07] [PASSED] test_info
[17:32:07] [PASSED] test_info_tile
[17:32:07] [PASSED] test_info_gt
[17:32:07] [PASSED] test_info_err
[17:32:07] [PASSED] test_info_comp
[17:32:07] [PASSED] test_info_comp_tile
[17:32:07] [PASSED] test_info_comp_gt
[17:32:07] [PASSED] test_info_all
[17:32:07] [PASSED] test_hw_fatal
[17:32:07] [PASSED] test_hw_recoverable
[17:32:07] [PASSED] test_hw_corrected
[17:32:07] [PASSED] test_hw_informational
[17:32:07] =================== [PASSED] test_dmesg ====================
[17:32:07] ====================== test_invalid  =======================
[17:32:07] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[17:32:07] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[17:32:07] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[17:32:07] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[17:32:07] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[17:32:07] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[17:32:07] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[17:32:07] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[17:32:07] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[17:32:07] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[17:32:07] ================== [SKIPPED] test_invalid ==================
[17:32:07] ===================== [PASSED] xe_log ======================
[17:32:07] ================== no_relay (3 subtests) ===================
[17:32:07] [PASSED] xe_drops_guc2pf_if_not_ready
[17:32:07] [PASSED] xe_drops_guc2vf_if_not_ready
[17:32:07] [PASSED] xe_rejects_send_if_not_ready
[17:32:07] ==================== [PASSED] no_relay =====================
[17:32:07] ================== pf_relay (14 subtests) ==================
[17:32:07] [PASSED] pf_rejects_guc2pf_too_short
[17:32:07] [PASSED] pf_rejects_guc2pf_too_long
[17:32:07] [PASSED] pf_rejects_guc2pf_no_payload
[17:32:07] [PASSED] pf_fails_no_payload
[17:32:07] [PASSED] pf_fails_bad_origin
[17:32:07] [PASSED] pf_fails_bad_type
[17:32:07] [PASSED] pf_txn_reports_error
[17:32:07] [PASSED] pf_txn_sends_pf2guc
[17:32:07] [PASSED] pf_sends_pf2guc
[17:32:07] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:32:07] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:32:07] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:32:07] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:32:07] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:32:07] ==================== [PASSED] pf_relay =====================
[17:32:07] ================== vf_relay (3 subtests) ===================
[17:32:07] [PASSED] vf_rejects_guc2vf_too_short
[17:32:07] [PASSED] vf_rejects_guc2vf_too_long
[17:32:07] [PASSED] vf_rejects_guc2vf_no_payload
[17:32:07] ==================== [PASSED] vf_relay =====================
[17:32:07] ================ pf_gt_config (9 subtests) =================
[17:32:07] [PASSED] fair_contexts_1vf
[17:32:07] [PASSED] fair_doorbells_1vf
[17:32:07] [PASSED] fair_ggtt_1vf
[17:32:07] ====================== fair_vram_1vf  ======================
[17:32:07] [PASSED] 3.50 GiB
[17:32:07] [PASSED] 11.5 GiB
[17:32:07] [PASSED] 15.5 GiB
[17:32:07] [PASSED] 31.5 GiB
[17:32:07] [PASSED] 63.5 GiB
[17:32:07] [PASSED] 1.91 GiB
[17:32:07] ================== [PASSED] fair_vram_1vf ==================
[17:32:07] ================ fair_vram_1vf_admin_only  =================
[17:32:07] [PASSED] 3.50 GiB
[17:32:07] [PASSED] 11.5 GiB
[17:32:07] [PASSED] 15.5 GiB
[17:32:07] [PASSED] 31.5 GiB
[17:32:07] [PASSED] 63.5 GiB
[17:32:07] [PASSED] 1.91 GiB
[17:32:07] ============ [PASSED] fair_vram_1vf_admin_only =============
[17:32:07] ====================== fair_contexts  ======================
[17:32:07] [PASSED] 1 VF
[17:32:07] [PASSED] 2 VFs
[17:32:07] [PASSED] 3 VFs
[17:32:07] [PASSED] 4 VFs
[17:32:07] [PASSED] 5 VFs
[17:32:07] [PASSED] 6 VFs
[17:32:07] [PASSED] 7 VFs
[17:32:07] [PASSED] 8 VFs
[17:32:07] [PASSED] 9 VFs
[17:32:07] [PASSED] 10 VFs
[17:32:07] [PASSED] 11 VFs
[17:32:07] [PASSED] 12 VFs
[17:32:07] [PASSED] 13 VFs
[17:32:07] [PASSED] 14 VFs
[17:32:07] [PASSED] 15 VFs
[17:32:07] [PASSED] 16 VFs
[17:32:07] [PASSED] 17 VFs
[17:32:07] [PASSED] 18 VFs
[17:32:07] [PASSED] 19 VFs
[17:32:07] [PASSED] 20 VFs
[17:32:07] [PASSED] 21 VFs
[17:32:07] [PASSED] 22 VFs
[17:32:07] [PASSED] 23 VFs
[17:32:07] [PASSED] 24 VFs
[17:32:07] [PASSED] 25 VFs
[17:32:07] [PASSED] 26 VFs
[17:32:07] [PASSED] 27 VFs
[17:32:07] [PASSED] 28 VFs
[17:32:07] [PASSED] 29 VFs
[17:32:07] [PASSED] 30 VFs
[17:32:07] [PASSED] 31 VFs
[17:32:07] [PASSED] 32 VFs
[17:32:07] [PASSED] 33 VFs
[17:32:07] [PASSED] 34 VFs
[17:32:07] [PASSED] 35 VFs
[17:32:07] [PASSED] 36 VFs
[17:32:07] [PASSED] 37 VFs
[17:32:07] [PASSED] 38 VFs
[17:32:07] [PASSED] 39 VFs
[17:32:07] [PASSED] 40 VFs
[17:32:07] [PASSED] 41 VFs
[17:32:07] [PASSED] 42 VFs
[17:32:07] [PASSED] 43 VFs
[17:32:07] [PASSED] 44 VFs
[17:32:07] [PASSED] 45 VFs
[17:32:07] [PASSED] 46 VFs
[17:32:07] [PASSED] 47 VFs
[17:32:07] [PASSED] 48 VFs
[17:32:07] [PASSED] 49 VFs
[17:32:07] [PASSED] 50 VFs
[17:32:07] [PASSED] 51 VFs
[17:32:07] [PASSED] 52 VFs
[17:32:07] [PASSED] 53 VFs
[17:32:07] [PASSED] 54 VFs
[17:32:07] [PASSED] 55 VFs
[17:32:07] [PASSED] 56 VFs
[17:32:07] [PASSED] 57 VFs
[17:32:07] [PASSED] 58 VFs
[17:32:07] [PASSED] 59 VFs
[17:32:07] [PASSED] 60 VFs
[17:32:07] [PASSED] 61 VFs
[17:32:07] [PASSED] 62 VFs
[17:32:07] [PASSED] 63 VFs
[17:32:07] ================== [PASSED] fair_contexts ==================
[17:32:07] ===================== fair_doorbells  ======================
[17:32:07] [PASSED] 1 VF
[17:32:07] [PASSED] 2 VFs
[17:32:07] [PASSED] 3 VFs
[17:32:07] [PASSED] 4 VFs
[17:32:07] [PASSED] 5 VFs
[17:32:07] [PASSED] 6 VFs
[17:32:07] [PASSED] 7 VFs
[17:32:07] [PASSED] 8 VFs
[17:32:07] [PASSED] 9 VFs
[17:32:07] [PASSED] 10 VFs
[17:32:07] [PASSED] 11 VFs
[17:32:07] [PASSED] 12 VFs
[17:32:07] [PASSED] 13 VFs
[17:32:07] [PASSED] 14 VFs
[17:32:07] [PASSED] 15 VFs
[17:32:07] [PASSED] 16 VFs
[17:32:07] [PASSED] 17 VFs
[17:32:07] [PASSED] 18 VFs
[17:32:07] [PASSED] 19 VFs
[17:32:07] [PASSED] 20 VFs
[17:32:07] [PASSED] 21 VFs
[17:32:07] [PASSED] 22 VFs
[17:32:07] [PASSED] 23 VFs
[17:32:07] [PASSED] 24 VFs
[17:32:07] [PASSED] 25 VFs
[17:32:07] [PASSED] 26 VFs
[17:32:07] [PASSED] 27 VFs
[17:32:07] [PASSED] 28 VFs
[17:32:07] [PASSED] 29 VFs
[17:32:07] [PASSED] 30 VFs
[17:32:07] [PASSED] 31 VFs
[17:32:07] [PASSED] 32 VFs
[17:32:07] [PASSED] 33 VFs
[17:32:07] [PASSED] 34 VFs
[17:32:07] [PASSED] 35 VFs
[17:32:07] [PASSED] 36 VFs
[17:32:07] [PASSED] 37 VFs
[17:32:07] [PASSED] 38 VFs
[17:32:07] [PASSED] 39 VFs
[17:32:07] [PASSED] 40 VFs
[17:32:07] [PASSED] 41 VFs
[17:32:07] [PASSED] 42 VFs
[17:32:07] [PASSED] 43 VFs
[17:32:07] [PASSED] 44 VFs
[17:32:07] [PASSED] 45 VFs
[17:32:07] [PASSED] 46 VFs
[17:32:07] [PASSED] 47 VFs
[17:32:07] [PASSED] 48 VFs
[17:32:07] [PASSED] 49 VFs
[17:32:07] [PASSED] 50 VFs
[17:32:07] [PASSED] 51 VFs
[17:32:07] [PASSED] 52 VFs
[17:32:07] [PASSED] 53 VFs
[17:32:07] [PASSED] 54 VFs
[17:32:07] [PASSED] 55 VFs
[17:32:07] [PASSED] 56 VFs
[17:32:07] [PASSED] 57 VFs
[17:32:07] [PASSED] 58 VFs
[17:32:07] [PASSED] 59 VFs
[17:32:07] [PASSED] 60 VFs
[17:32:07] [PASSED] 61 VFs
[17:32:07] [PASSED] 62 VFs
[17:32:07] [PASSED] 63 VFs
[17:32:07] ================= [PASSED] fair_doorbells ==================
[17:32:07] ======================== fair_ggtt  ========================
[17:32:07] [PASSED] 1 VF
[17:32:07] [PASSED] 2 VFs
[17:32:07] [PASSED] 3 VFs
[17:32:07] [PASSED] 4 VFs
[17:32:07] [PASSED] 5 VFs
[17:32:07] [PASSED] 6 VFs
[17:32:07] [PASSED] 7 VFs
[17:32:07] [PASSED] 8 VFs
[17:32:07] [PASSED] 9 VFs
[17:32:07] [PASSED] 10 VFs
[17:32:07] [PASSED] 11 VFs
[17:32:07] [PASSED] 12 VFs
[17:32:07] [PASSED] 13 VFs
[17:32:07] [PASSED] 14 VFs
[17:32:07] [PASSED] 15 VFs
[17:32:07] [PASSED] 16 VFs
[17:32:07] [PASSED] 17 VFs
[17:32:07] [PASSED] 18 VFs
[17:32:07] [PASSED] 19 VFs
[17:32:07] [PASSED] 20 VFs
[17:32:07] [PASSED] 21 VFs
[17:32:07] [PASSED] 22 VFs
[17:32:07] [PASSED] 23 VFs
[17:32:07] [PASSED] 24 VFs
[17:32:07] [PASSED] 25 VFs
[17:32:07] [PASSED] 26 VFs
[17:32:07] [PASSED] 27 VFs
[17:32:07] [PASSED] 28 VFs
[17:32:07] [PASSED] 29 VFs
[17:32:07] [PASSED] 30 VFs
[17:32:07] [PASSED] 31 VFs
[17:32:07] [PASSED] 32 VFs
[17:32:07] [PASSED] 33 VFs
[17:32:07] [PASSED] 34 VFs
[17:32:07] [PASSED] 35 VFs
[17:32:07] [PASSED] 36 VFs
[17:32:07] [PASSED] 37 VFs
[17:32:07] [PASSED] 38 VFs
[17:32:07] [PASSED] 39 VFs
[17:32:07] [PASSED] 40 VFs
[17:32:07] [PASSED] 41 VFs
[17:32:07] [PASSED] 42 VFs
[17:32:07] [PASSED] 43 VFs
[17:32:07] [PASSED] 44 VFs
[17:32:07] [PASSED] 45 VFs
[17:32:07] [PASSED] 46 VFs
[17:32:07] [PASSED] 47 VFs
[17:32:07] [PASSED] 48 VFs
[17:32:07] [PASSED] 49 VFs
[17:32:07] [PASSED] 50 VFs
[17:32:07] [PASSED] 51 VFs
[17:32:07] [PASSED] 52 VFs
[17:32:07] [PASSED] 53 VFs
[17:32:07] [PASSED] 54 VFs
[17:32:07] [PASSED] 55 VFs
[17:32:07] [PASSED] 56 VFs
[17:32:07] [PASSED] 57 VFs
[17:32:07] [PASSED] 58 VFs
[17:32:07] [PASSED] 59 VFs
[17:32:07] [PASSED] 60 VFs
[17:32:07] [PASSED] 61 VFs
[17:32:07] [PASSED] 62 VFs
[17:32:07] [PASSED] 63 VFs
[17:32:07] ==================== [PASSED] fair_ggtt ====================
[17:32:07] ======================== fair_vram  ========================
[17:32:07] [PASSED] 1 VF
[17:32:07] [PASSED] 2 VFs
[17:32:07] [PASSED] 3 VFs
[17:32:07] [PASSED] 4 VFs
[17:32:07] [PASSED] 5 VFs
[17:32:07] [PASSED] 6 VFs
[17:32:07] [PASSED] 7 VFs
[17:32:07] [PASSED] 8 VFs
[17:32:07] [PASSED] 9 VFs
[17:32:07] [PASSED] 10 VFs
[17:32:07] [PASSED] 11 VFs
[17:32:07] [PASSED] 12 VFs
[17:32:07] [PASSED] 13 VFs
[17:32:07] [PASSED] 14 VFs
[17:32:07] [PASSED] 15 VFs
[17:32:07] [PASSED] 16 VFs
[17:32:07] [PASSED] 17 VFs
[17:32:07] [PASSED] 18 VFs
[17:32:07] [PASSED] 19 VFs
[17:32:07] [PASSED] 20 VFs
[17:32:07] [PASSED] 21 VFs
[17:32:07] [PASSED] 22 VFs
[17:32:07] [PASSED] 23 VFs
[17:32:07] [PASSED] 24 VFs
[17:32:07] [PASSED] 25 VFs
[17:32:07] [PASSED] 26 VFs
[17:32:07] [PASSED] 27 VFs
[17:32:07] [PASSED] 28 VFs
[17:32:07] [PASSED] 29 VFs
[17:32:07] [PASSED] 30 VFs
[17:32:07] [PASSED] 31 VFs
[17:32:07] [PASSED] 32 VFs
[17:32:07] [PASSED] 33 VFs
[17:32:07] [PASSED] 34 VFs
[17:32:07] [PASSED] 35 VFs
[17:32:07] [PASSED] 36 VFs
[17:32:07] [PASSED] 37 VFs
[17:32:07] [PASSED] 38 VFs
[17:32:07] [PASSED] 39 VFs
[17:32:07] [PASSED] 40 VFs
[17:32:07] [PASSED] 41 VFs
[17:32:07] [PASSED] 42 VFs
[17:32:07] [PASSED] 43 VFs
[17:32:07] [PASSED] 44 VFs
[17:32:07] [PASSED] 45 VFs
[17:32:07] [PASSED] 46 VFs
[17:32:07] [PASSED] 47 VFs
[17:32:07] [PASSED] 48 VFs
[17:32:07] [PASSED] 49 VFs
[17:32:07] [PASSED] 50 VFs
[17:32:07] [PASSED] 51 VFs
[17:32:07] [PASSED] 52 VFs
[17:32:07] [PASSED] 53 VFs
[17:32:07] [PASSED] 54 VFs
[17:32:07] [PASSED] 55 VFs
[17:32:07] [PASSED] 56 VFs
[17:32:07] [PASSED] 57 VFs
[17:32:07] [PASSED] 58 VFs
[17:32:07] [PASSED] 59 VFs
[17:32:07] [PASSED] 60 VFs
[17:32:07] [PASSED] 61 VFs
[17:32:07] [PASSED] 62 VFs
[17:32:07] [PASSED] 63 VFs
[17:32:07] ==================== [PASSED] fair_vram ====================
[17:32:07] ================== [PASSED] pf_gt_config ===================
[17:32:07] ===================== lmtt (1 subtest) =====================
[17:32:07] ======================== test_ops  =========================
[17:32:07] [PASSED] 2-level
[17:32:07] [PASSED] multi-level
[17:32:07] ==================== [PASSED] test_ops =====================
[17:32:07] ====================== [PASSED] lmtt =======================
[17:32:07] ================= sriov_packet (1 subtest) =================
[17:32:07] [PASSED] test_descriptor_init
[17:32:07] ================== [PASSED] sriov_packet ===================
[17:32:07] ================= pf_service (11 subtests) =================
[17:32:07] [PASSED] pf_negotiate_any
[17:32:07] [PASSED] pf_negotiate_base_match
[17:32:07] [PASSED] pf_negotiate_base_newer
[17:32:07] [PASSED] pf_negotiate_base_next
[17:32:07] [SKIPPED] pf_negotiate_base_older (no older minor)
[17:32:07] [PASSED] pf_negotiate_base_prev
[17:32:07] [PASSED] pf_negotiate_latest_match
[17:32:07] [PASSED] pf_negotiate_latest_newer
[17:32:07] [PASSED] pf_negotiate_latest_next
[17:32:07] [SKIPPED] pf_negotiate_latest_older (no older minor)
[17:32:07] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[17:32:07] =================== [PASSED] pf_service ====================
[17:32:07] ================= xe_guc_g2g (2 subtests) ==================
[17:32:07] ============== xe_live_guc_g2g_kunit_default  ==============
[17:32:07] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[17:32:07] ============== xe_live_guc_g2g_kunit_allmem  ===============
[17:32:07] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[17:32:07] =================== [SKIPPED] xe_guc_g2g ===================
[17:32:07] =================== xe_mocs (2 subtests) ===================
[17:32:07] ================ xe_live_mocs_kernel_kunit  ================
[17:32:07] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[17:32:07] ================ xe_live_mocs_reset_kunit  =================
[17:32:07] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[17:32:07] ==================== [SKIPPED] xe_mocs =====================
[17:32:07] ================= xe_migrate (2 subtests) ==================
[17:32:07] ================= xe_migrate_sanity_kunit  =================
[17:32:07] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[17:32:07] ================== xe_validate_ccs_kunit  ==================
[17:32:07] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[17:32:07] =================== [SKIPPED] xe_migrate ===================
[17:32:07] ================== xe_dma_buf (1 subtest) ==================
[17:32:07] ==================== xe_dma_buf_kunit  =====================
[17:32:07] ================ [SKIPPED] xe_dma_buf_kunit ================
[17:32:07] =================== [SKIPPED] xe_dma_buf ===================
[17:32:07] ================= xe_bo_shrink (1 subtest) =================
[17:32:07] =================== xe_bo_shrink_kunit  ====================
[17:32:07] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[17:32:07] ================== [SKIPPED] xe_bo_shrink ==================
[17:32:07] ==================== xe_bo (2 subtests) ====================
[17:32:07] ================== xe_ccs_migrate_kunit  ===================
[17:32:07] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[17:32:07] ==================== xe_bo_evict_kunit  ====================
[17:32:07] =============== [SKIPPED] xe_bo_evict_kunit ================
[17:32:07] ===================== [SKIPPED] xe_bo ======================
[17:32:07] =================== xe_any (9 subtests) ====================
[17:32:07] [PASSED] test_to_xe
[17:32:07] [PASSED] test_to_dev
[17:32:07] [PASSED] test_to_pdev
[17:32:07] [PASSED] test_to_drm
[17:32:07] [PASSED] test_if_pdev
[17:32:07] [PASSED] test_if_xe
[17:32:07] [PASSED] test_if_tile
[17:32:07] [PASSED] test_if_gt
[17:32:07] [PASSED] test_to_id
[17:32:07] ===================== [PASSED] xe_any ======================
[17:32:07] ==================== args (13 subtests) ====================
[17:32:07] [PASSED] count_args_test
[17:32:07] [PASSED] call_args_example
[17:32:07] [PASSED] call_args_test
[17:32:07] [PASSED] drop_first_arg_example
[17:32:07] [PASSED] drop_first_arg_test
[17:32:07] [PASSED] first_arg_example
[17:32:07] [PASSED] first_arg_test
[17:32:07] [PASSED] last_arg_example
[17:32:07] [PASSED] last_arg_test
[17:32:07] [PASSED] pick_arg_example
[17:32:07] [PASSED] if_args_example
[17:32:07] [PASSED] if_args_test
[17:32:07] [PASSED] sep_comma_example
[17:32:07] ====================== [PASSED] args =======================
[17:32:07] =================== xe_pci (3 subtests) ====================
[17:32:07] ==================== check_graphics_ip  ====================
[17:32:07] [PASSED] 12.00 Xe_LP
[17:32:07] [PASSED] 12.10 Xe_LP+
[17:32:07] [PASSED] 12.55 Xe_HPG
[17:32:07] [PASSED] 12.60 Xe_HPC
[17:32:07] [PASSED] 12.70 Xe_LPG
[17:32:07] [PASSED] 12.71 Xe_LPG
[17:32:07] [PASSED] 12.74 Xe_LPG+
[17:32:07] [PASSED] 20.01 Xe2_HPG
[17:32:07] [PASSED] 20.02 Xe2_HPG
[17:32:07] [PASSED] 20.04 Xe2_LPG
[17:32:07] [PASSED] 30.00 Xe3_LPG
[17:32:07] [PASSED] 30.01 Xe3_LPG
[17:32:07] [PASSED] 30.03 Xe3_LPG
[17:32:07] [PASSED] 30.04 Xe3_LPG
[17:32:07] [PASSED] 30.05 Xe3_LPG
[17:32:07] [PASSED] 35.10 Xe3p_LPG
[17:32:07] [PASSED] 35.11 Xe3p_XPC
[17:32:07] ================ [PASSED] check_graphics_ip ================
[17:32:07] ===================== check_media_ip  ======================
[17:32:07] [PASSED] 12.00 Xe_M
[17:32:07] [PASSED] 12.55 Xe_HPM
[17:32:07] [PASSED] 13.00 Xe_LPM+
[17:32:07] [PASSED] 13.01 Xe2_HPM
[17:32:07] [PASSED] 20.00 Xe2_LPM
[17:32:07] [PASSED] 30.00 Xe3_LPM
[17:32:07] [PASSED] 30.02 Xe3_LPM
[17:32:07] [PASSED] 35.00 Xe3p_LPM
[17:32:07] [PASSED] 35.03 Xe3p_HPM
[17:32:07] ================= [PASSED] check_media_ip ==================
[17:32:07] =================== check_platform_desc  ===================
[17:32:07] [PASSED] 0x9A60 (TIGERLAKE)
[17:32:07] [PASSED] 0x9A68 (TIGERLAKE)
[17:32:07] [PASSED] 0x9A70 (TIGERLAKE)
[17:32:07] [PASSED] 0x9A40 (TIGERLAKE)
[17:32:07] [PASSED] 0x9A49 (TIGERLAKE)
[17:32:07] [PASSED] 0x9A59 (TIGERLAKE)
[17:32:07] [PASSED] 0x9A78 (TIGERLAKE)
[17:32:07] [PASSED] 0x9AC0 (TIGERLAKE)
[17:32:07] [PASSED] 0x9AC9 (TIGERLAKE)
[17:32:07] [PASSED] 0x9AD9 (TIGERLAKE)
[17:32:07] [PASSED] 0x9AF8 (TIGERLAKE)
[17:32:07] [PASSED] 0x4C80 (ROCKETLAKE)
[17:32:07] [PASSED] 0x4C8A (ROCKETLAKE)
[17:32:07] [PASSED] 0x4C8B (ROCKETLAKE)
[17:32:07] [PASSED] 0x4C8C (ROCKETLAKE)
[17:32:07] [PASSED] 0x4C90 (ROCKETLAKE)
[17:32:07] [PASSED] 0x4C9A (ROCKETLAKE)
[17:32:07] [PASSED] 0x4680 (ALDERLAKE_S)
[17:32:07] [PASSED] 0x4682 (ALDERLAKE_S)
[17:32:07] [PASSED] 0x4688 (ALDERLAKE_S)
[17:32:07] [PASSED] 0x468A (ALDERLAKE_S)
[17:32:07] [PASSED] 0x468B (ALDERLAKE_S)
[17:32:07] [PASSED] 0x4690 (ALDERLAKE_S)
[17:32:07] [PASSED] 0x4692 (ALDERLAKE_S)
[17:32:07] [PASSED] 0x4693 (ALDERLAKE_S)
[17:32:07] [PASSED] 0x46A0 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x46A1 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x46A2 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x46A3 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x46A6 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x46A8 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x46AA (ALDERLAKE_P)
[17:32:07] [PASSED] 0x462A (ALDERLAKE_P)
[17:32:07] [PASSED] 0x4626 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x4628 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x46B0 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x46B1 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x46B2 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x46B3 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x46C0 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x46C1 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x46C2 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x46C3 (ALDERLAKE_P)
[17:32:07] [PASSED] 0x46D0 (ALDERLAKE_N)
[17:32:07] [PASSED] 0x46D1 (ALDERLAKE_N)
[17:32:07] [PASSED] 0x46D2 (ALDERLAKE_N)
[17:32:07] [PASSED] 0x46D3 (ALDERLAKE_N)
[17:32:07] [PASSED] 0x46D4 (ALDERLAKE_N)
[17:32:07] [PASSED] 0xA721 (ALDERLAKE_P)
[17:32:07] [PASSED] 0xA7A1 (ALDERLAKE_P)
[17:32:07] [PASSED] 0xA7A9 (ALDERLAKE_P)
[17:32:07] [PASSED] 0xA7AC (ALDERLAKE_P)
[17:32:07] [PASSED] 0xA7AD (ALDERLAKE_P)
[17:32:07] [PASSED] 0xA720 (ALDERLAKE_P)
[17:32:07] [PASSED] 0xA7A0 (ALDERLAKE_P)
[17:32:07] [PASSED] 0xA7A8 (ALDERLAKE_P)
[17:32:07] [PASSED] 0xA7AA (ALDERLAKE_P)
[17:32:07] [PASSED] 0xA7AB (ALDERLAKE_P)
[17:32:07] [PASSED] 0xA780 (ALDERLAKE_S)
[17:32:07] [PASSED] 0xA781 (ALDERLAKE_S)
[17:32:07] [PASSED] 0xA782 (ALDERLAKE_S)
[17:32:07] [PASSED] 0xA783 (ALDERLAKE_S)
[17:32:07] [PASSED] 0xA788 (ALDERLAKE_S)
[17:32:07] [PASSED] 0xA789 (ALDERLAKE_S)
[17:32:07] [PASSED] 0xA78A (ALDERLAKE_S)
[17:32:07] [PASSED] 0xA78B (ALDERLAKE_S)
[17:32:07] [PASSED] 0x4905 (DG1)
[17:32:07] [PASSED] 0x4906 (DG1)
[17:32:07] [PASSED] 0x4907 (DG1)
[17:32:07] [PASSED] 0x4908 (DG1)
[17:32:07] [PASSED] 0x4909 (DG1)
[17:32:07] [PASSED] 0x56C0 (DG2)
[17:32:07] [PASSED] 0x56C2 (DG2)
[17:32:07] [PASSED] 0x56C1 (DG2)
[17:32:07] [PASSED] 0x7D51 (METEORLAKE)
[17:32:07] [PASSED] 0x7DD1 (METEORLAKE)
[17:32:07] [PASSED] 0x7D41 (METEORLAKE)
[17:32:07] [PASSED] 0x7D67 (METEORLAKE)
[17:32:07] [PASSED] 0xB640 (METEORLAKE)
[17:32:07] [PASSED] 0x56A0 (DG2)
[17:32:07] [PASSED] 0x56A1 (DG2)
[17:32:07] [PASSED] 0x56A2 (DG2)
[17:32:07] [PASSED] 0x56BE (DG2)
[17:32:07] [PASSED] 0x56BF (DG2)
[17:32:07] [PASSED] 0x5690 (DG2)
[17:32:07] [PASSED] 0x5691 (DG2)
[17:32:07] [PASSED] 0x5692 (DG2)
[17:32:07] [PASSED] 0x56A5 (DG2)
[17:32:07] [PASSED] 0x56A6 (DG2)
[17:32:07] [PASSED] 0x56B0 (DG2)
[17:32:07] [PASSED] 0x56B1 (DG2)
[17:32:07] [PASSED] 0x56BA (DG2)
[17:32:07] [PASSED] 0x56BB (DG2)
[17:32:07] [PASSED] 0x56BC (DG2)
[17:32:07] [PASSED] 0x56BD (DG2)
[17:32:07] [PASSED] 0x5693 (DG2)
[17:32:07] [PASSED] 0x5694 (DG2)
[17:32:07] [PASSED] 0x5695 (DG2)
[17:32:07] [PASSED] 0x56A3 (DG2)
[17:32:07] [PASSED] 0x56A4 (DG2)
[17:32:07] [PASSED] 0x56B2 (DG2)
[17:32:07] [PASSED] 0x56B3 (DG2)
[17:32:07] [PASSED] 0x5696 (DG2)
[17:32:07] [PASSED] 0x5697 (DG2)
[17:32:07] [PASSED] 0xB69 (PVC)
[17:32:07] [PASSED] 0xB6E (PVC)
[17:32:07] [PASSED] 0xBD4 (PVC)
[17:32:07] [PASSED] 0xBD5 (PVC)
[17:32:07] [PASSED] 0xBD6 (PVC)
[17:32:07] [PASSED] 0xBD7 (PVC)
[17:32:07] [PASSED] 0xBD8 (PVC)
[17:32:07] [PASSED] 0xBD9 (PVC)
[17:32:07] [PASSED] 0xBDA (PVC)
[17:32:07] [PASSED] 0xBDB (PVC)
[17:32:07] [PASSED] 0xBE0 (PVC)
[17:32:07] [PASSED] 0xBE1 (PVC)
[17:32:07] [PASSED] 0xBE5 (PVC)
[17:32:07] [PASSED] 0x7D40 (METEORLAKE)
[17:32:07] [PASSED] 0x7D45 (METEORLAKE)
[17:32:07] [PASSED] 0x7D55 (METEORLAKE)
[17:32:07] [PASSED] 0x7D60 (METEORLAKE)
[17:32:07] [PASSED] 0x7DD5 (METEORLAKE)
[17:32:07] [PASSED] 0x6420 (LUNARLAKE)
[17:32:07] [PASSED] 0x64A0 (LUNARLAKE)
[17:32:07] [PASSED] 0x64B0 (LUNARLAKE)
[17:32:07] [PASSED] 0xE202 (BATTLEMAGE)
[17:32:07] [PASSED] 0xE209 (BATTLEMAGE)
[17:32:07] [PASSED] 0xE20B (BATTLEMAGE)
[17:32:07] [PASSED] 0xE20C (BATTLEMAGE)
[17:32:07] [PASSED] 0xE20D (BATTLEMAGE)
[17:32:07] [PASSED] 0xE210 (BATTLEMAGE)
[17:32:07] [PASSED] 0xE211 (BATTLEMAGE)
[17:32:07] [PASSED] 0xE212 (BATTLEMAGE)
[17:32:07] [PASSED] 0xE216 (BATTLEMAGE)
[17:32:07] [PASSED] 0xE220 (BATTLEMAGE)
[17:32:07] [PASSED] 0xE221 (BATTLEMAGE)
[17:32:07] [PASSED] 0xE222 (BATTLEMAGE)
[17:32:07] [PASSED] 0xE223 (BATTLEMAGE)
[17:32:07] [PASSED] 0xB080 (PANTHERLAKE)
[17:32:07] [PASSED] 0xB081 (PANTHERLAKE)
[17:32:07] [PASSED] 0xB082 (PANTHERLAKE)
[17:32:07] [PASSED] 0xB083 (PANTHERLAKE)
[17:32:07] [PASSED] 0xB084 (PANTHERLAKE)
[17:32:07] [PASSED] 0xB085 (PANTHERLAKE)
[17:32:07] [PASSED] 0xB086 (PANTHERLAKE)
[17:32:07] [PASSED] 0xB087 (PANTHERLAKE)
[17:32:07] [PASSED] 0xB08F (PANTHERLAKE)
[17:32:07] [PASSED] 0xB090 (PANTHERLAKE)
[17:32:07] [PASSED] 0xB0A0 (PANTHERLAKE)
[17:32:07] [PASSED] 0xB0B0 (PANTHERLAKE)
[17:32:07] [PASSED] 0xFD80 (PANTHERLAKE)
[17:32:07] [PASSED] 0xFD81 (PANTHERLAKE)
[17:32:07] [PASSED] 0xD740 (NOVALAKE_S)
[17:32:07] [PASSED] 0xD741 (NOVALAKE_S)
[17:32:07] [PASSED] 0xD742 (NOVALAKE_S)
[17:32:07] [PASSED] 0xD743 (NOVALAKE_S)
[17:32:07] [PASSED] 0xD745 (NOVALAKE_S)
[17:32:07] [PASSED] 0xD74A (NOVALAKE_S)
[17:32:07] [PASSED] 0xD74B (NOVALAKE_S)
[17:32:07] [PASSED] 0x674C (CRESCENTISLAND)
[17:32:07] [PASSED] 0x674D (CRESCENTISLAND)
[17:32:07] [PASSED] 0x674E (CRESCENTISLAND)
[17:32:07] [PASSED] 0x674F (CRESCENTISLAND)
[17:32:07] [PASSED] 0x6750 (CRESCENTISLAND)
[17:32:07] [PASSED] 0xD750 (NOVALAKE_P)
[17:32:07] [PASSED] 0xD751 (NOVALAKE_P)
[17:32:07] [PASSED] 0xD752 (NOVALAKE_P)
[17:32:07] [PASSED] 0xD753 (NOVALAKE_P)
[17:32:07] [PASSED] 0xD754 (NOVALAKE_P)
[17:32:07] [PASSED] 0xD755 (NOVALAKE_P)
[17:32:07] [PASSED] 0xD756 (NOVALAKE_P)
[17:32:07] [PASSED] 0xD757 (NOVALAKE_P)
[17:32:07] [PASSED] 0xD75F (NOVALAKE_P)
[17:32:07] =============== [PASSED] check_platform_desc ===============
[17:32:07] ===================== [PASSED] xe_pci ======================
[17:32:07] ============= xe_rtp_tables_test (5 subtests) ==============
[17:32:07] ================== xe_rtp_table_gt_test  ===================
[17:32:07] [PASSED] gt_was/14011060649
[17:32:07] [PASSED] gt_was/14011059788
[17:32:07] [PASSED] gt_was/14015795083
[17:32:07] [PASSED] gt_was/16021867713
[17:32:07] [PASSED] gt_was/14019449301
[17:32:07] [PASSED] gt_was/16028005424
[17:32:07] [PASSED] gt_was/14026578760
[17:32:07] [PASSED] gt_was/1409420604
[17:32:07] [PASSED] gt_was/1408615072
[17:32:07] [PASSED] gt_was/22010523718
[17:32:07] [PASSED] gt_was/14011006942
[17:32:07] [PASSED] gt_was/14014830051
[17:32:07] [PASSED] gt_was/18018781329
[17:32:07] [PASSED] gt_was/1509235366
[17:32:07] [PASSED] gt_was/18018781329
[17:32:07] [PASSED] gt_was/16016694945
[17:32:07] [PASSED] gt_was/14018575942
[17:32:07] [PASSED] gt_was/22016670082
[17:32:07] [PASSED] gt_was/22016670082
[17:32:07] [PASSED] gt_was/14017421178
[17:32:07] [PASSED] gt_was/16025250150
[17:32:07] [PASSED] gt_was/14021871409
[17:32:07] [PASSED] gt_was/16021865536
[17:32:07] [PASSED] gt_was/14021486841
[17:32:07] [PASSED] gt_was/14025160223
[17:32:07] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[17:32:07] [PASSED] gt_was/14025635424
[17:32:07] [PASSED] gt_was/16028005424
[17:32:07] ============== [PASSED] xe_rtp_table_gt_test ===============
[17:32:07] ================== xe_rtp_table_gt_test  ===================
[17:32:07] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[17:32:07] [PASSED] gt_tunings/Tuning: 32B Access Enable
[17:32:07] [PASSED] gt_tunings/Tuning: L3 cache
[17:32:07] [PASSED] gt_tunings/Tuning: L3 cache - media
[17:32:07] [PASSED] gt_tunings/Tuning: Compression Overfetch
[17:32:07] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[17:32:07] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[17:32:07] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[17:32:07] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[17:32:07] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[17:32:07] [PASSED] gt_tunings/Tuning: Stateless compression control
[17:32:07] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[17:32:07] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[17:32:07] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[17:32:07] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[17:32:07] ============== [PASSED] xe_rtp_table_gt_test ===============
[17:32:07] ================== xe_rtp_table_oob_test  ==================
[17:32:07] [PASSED] oob_was/1607983814
[17:32:07] [PASSED] oob_was/16010904313
[17:32:07] [PASSED] oob_was/18022495364
[17:32:07] [PASSED] oob_was/22012773006
[17:32:07] [PASSED] oob_was/14014475959
[17:32:07] [PASSED] oob_was/22011391025
[17:32:07] [PASSED] oob_was/22012727170
[17:32:07] [PASSED] oob_was/22012727685
[17:32:07] [PASSED] oob_was/22016596838
[17:32:07] [PASSED] oob_was/18020744125
[17:32:07] [PASSED] oob_was/1409600907
[17:32:07] [PASSED] oob_was/22014953428
[17:32:07] [PASSED] oob_was/16017236439
[17:32:07] [PASSED] oob_was/14019821291
[17:32:07] [PASSED] oob_was/14015076503
[17:32:07] [PASSED] oob_was/14018913170
[17:32:07] [PASSED] oob_was/14018094691
[17:32:07] [PASSED] oob_was/18024947630
[17:32:07] [PASSED] oob_was/16022287689
[17:32:07] [PASSED] oob_was/13011645652
[17:32:07] [PASSED] oob_was/14022293748
[17:32:07] [PASSED] oob_was/22019794406
[17:32:07] [PASSED] oob_was/22019338487
[17:32:07] [PASSED] oob_was/16023588340
[17:32:07] [PASSED] oob_was/14019789679
[17:32:07] [PASSED] oob_was/14022866841
[17:32:07] [PASSED] oob_was/16021333562
[17:32:07] [PASSED] oob_was/14016712196
[17:32:07] [PASSED] oob_was/14015568240
[17:32:07] [PASSED] oob_was/18013179988
[17:32:07] [PASSED] oob_was/1508761755
[17:32:07] [PASSED] oob_was/16023105232
[17:32:07] [PASSED] oob_was/16026508708
[17:32:07] [PASSED] oob_was/14020001231
[17:32:07] [PASSED] oob_was/16023683509
[17:32:07] [PASSED] oob_was/14025515070
[17:32:07] [PASSED] oob_was/15015404425_disable
[17:32:07] [PASSED] oob_was/16026007364
[17:32:07] [PASSED] oob_was/14020316580
[17:32:07] [PASSED] oob_was/14025883347
[17:32:07] [PASSED] oob_was/16029380221
[17:32:07] [PASSED] oob_was/22022079272
[17:32:07] [PASSED] oob_was/16029897822
[17:32:07] [PASSED] oob_was/14027054324
[17:32:07] ============== [PASSED] xe_rtp_table_oob_test ==============
[17:32:07] ================ xe_rtp_table_dev_oob_test  ================
[17:32:07] [PASSED] device_oob_was/22010954014
[17:32:07] [PASSED] device_oob_was/15015404425
[17:32:07] [PASSED] device_oob_was/22019338487_display
[17:32:07] [PASSED] device_oob_was/14022085890
[17:32:07] [PASSED] device_oob_was/14026539277
[17:32:07] [PASSED] device_oob_was/14026633728
[17:32:07] [PASSED] device_oob_was/14026746987
[17:32:07] [PASSED] device_oob_was/14026779378
[17:32:07] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[17:32:07] ========== xe_rtp_table_missing_upper_bound_test  ==========
[17:32:07] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[17:32:07] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[17:32:07] [PASSED] register_whitelist/1806527549
[17:32:07] [PASSED] register_whitelist/allow_read_ctx_timestamp
[17:32:07] [PASSED] register_whitelist/allow_read_queue_timestamp
[17:32:07] [PASSED] register_whitelist/16014440446
[17:32:07] [PASSED] register_whitelist/16017236439
[17:32:07] [PASSED] register_whitelist/16020183090
[17:32:07] [PASSED] register_whitelist/14024997852
[17:32:07] [PASSED] register_whitelist/14024997852
[17:32:07] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[17:32:07] =============== [PASSED] xe_rtp_tables_test ================
[17:32:07] =================== xe_rtp (3 subtests) ====================
[17:32:07] =================== xe_rtp_rules_tests  ====================
[17:32:07] [PASSED] no
[17:32:07] [PASSED] yes
[17:32:07] [PASSED] no-and-no
[17:32:07] [PASSED] no-and-yes
[17:32:07] [PASSED] yes-and-no
[17:32:07] [PASSED] yes-and-yes
[17:32:07] [PASSED] no-or-no
[17:32:07] [PASSED] no-or-yes
[17:32:07] [PASSED] yes-or-no
[17:32:07] [PASSED] yes-or-yes
[17:32:07] [PASSED] no-yes-or-yes-no
[17:32:07] [PASSED] no-yes-or-yes-yes
[17:32:07] [PASSED] yes-yes-or-no-yes
[17:32:07] [PASSED] yes-yes-or-yes-yes
[17:32:07] [PASSED] no-no-or-yes-or-no
[17:32:07] [PASSED] or
[17:32:07] [PASSED] or-yes
[17:32:07] [PASSED] or-no
[17:32:07] [PASSED] yes-or
[17:32:07] [PASSED] no-or
[17:32:07] [PASSED] no-or-or-yes
[17:32:07] [PASSED] yes-or-or-no
[17:32:07] [PASSED] no-or-or-no
[17:32:07] [PASSED] missing-context-engine-class
[17:32:07] [PASSED] missing-context-engine-class-or-yes
[17:32:07] [PASSED] missing-context-engine-class-or-or-yes
[17:32:07] =============== [PASSED] xe_rtp_rules_tests ================
[17:32:07] =============== xe_rtp_process_to_sr_tests  ================
[17:32:07] [PASSED] coalesce-same-reg
[17:32:07] [PASSED] coalesce-same-reg-literal-and-func
[17:32:07] [PASSED] no-match-no-add
[17:32:07] [PASSED] two-regs-two-entries
[17:32:07] [PASSED] clr-one-set-other
[17:32:07] [PASSED] set-field
[17:32:07] [PASSED] conflict-duplicate
[17:32:07] [PASSED] conflict-not-disjoint
[17:32:07] [PASSED] conflict-not-disjoint-literal-and-func
[17:32:07] [PASSED] conflict-reg-type
[17:32:07] [PASSED] bad-mcr-reg-forced-to-regular
[17:32:07] [PASSED] bad-regular-reg-forced-to-mcr
[17:32:07] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[17:32:07] ================== xe_rtp_process_tests  ===================
[17:32:07] [PASSED] active1
[17:32:07] [PASSED] active2
[17:32:07] [PASSED] active-inactive
[17:32:07] [PASSED] inactive-active
[17:32:07] [PASSED] inactive-active-inactive
[17:32:07] [PASSED] inactive-inactive-inactive
[17:32:07] ============== [PASSED] xe_rtp_process_tests ===============
[17:32:07] ===================== [PASSED] xe_rtp ======================
[17:32:07] ==================== xe_wa (1 subtest) =====================
[17:32:07] ======================== xe_wa_gt  =========================
[17:32:07] [PASSED] TIGERLAKE B0
[17:32:07] [PASSED] DG1 A0
[17:32:07] [PASSED] DG1 B0
[17:32:07] [PASSED] ALDERLAKE_S A0
[17:32:07] [PASSED] ALDERLAKE_S B0
[17:32:07] [PASSED] ALDERLAKE_S C0
[17:32:07] [PASSED] ALDERLAKE_S D0
[17:32:07] [PASSED] ALDERLAKE_P A0
[17:32:07] [PASSED] ALDERLAKE_P B0
[17:32:07] [PASSED] ALDERLAKE_P C0
[17:32:07] [PASSED] ALDERLAKE_S RPLS D0
[17:32:07] [PASSED] ALDERLAKE_P RPLU E0
[17:32:07] [PASSED] DG2 G10 C0
[17:32:07] [PASSED] DG2 G11 B1
[17:32:07] [PASSED] DG2 G12 A1
[17:32:07] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:32:08] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:32:08] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[17:32:08] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[17:32:08] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[17:32:08] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[17:32:08] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[17:32:08] ==================== [PASSED] xe_wa_gt =====================
[17:32:08] ====================== [PASSED] xe_wa ======================
[17:32:08] ============================================================
[17:32:08] Testing complete. Ran 793 tests: passed: 765, skipped: 28
[17:32:08] Elapsed time: 36.056s total, 1.861s configuring, 33.479s building, 0.710s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:32:08] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:32:10] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:32:34] Starting KUnit Kernel (1/1)...
[17:32:34] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:32:34] ============= refcount_interrupt (4 subtests) ==============
[17:32:34] [PASSED] test_single_irq_change
[17:32:34] [PASSED] test_nested_irq_change
[17:32:34] [PASSED] test_multiple_irq_change
[17:32:34] [PASSED] test_irq_save
[17:32:34] =============== [PASSED] refcount_interrupt ================
[17:32:34] ============ drm_test_pick_cmdline (2 subtests) ============
[17:32:34] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[17:32:34] =============== drm_test_pick_cmdline_named  ===============
[17:32:34] [PASSED] NTSC
[17:32:34] [PASSED] NTSC-J
[17:32:34] [PASSED] PAL
[17:32:34] [PASSED] PAL-M
[17:32:34] =========== [PASSED] drm_test_pick_cmdline_named ===========
[17:32:34] ============== [PASSED] drm_test_pick_cmdline ==============
[17:32:34] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[17:32:34] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[17:32:34] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[17:32:34] =========== drm_validate_clone_mode (2 subtests) ===========
[17:32:34] ============== drm_test_check_in_clone_mode  ===============
[17:32:34] [PASSED] in_clone_mode
[17:32:34] [PASSED] not_in_clone_mode
[17:32:34] ========== [PASSED] drm_test_check_in_clone_mode ===========
[17:32:34] =============== drm_test_check_valid_clones  ===============
[17:32:34] [PASSED] not_in_clone_mode
[17:32:34] [PASSED] valid_clone
[17:32:34] [PASSED] invalid_clone
[17:32:34] =========== [PASSED] drm_test_check_valid_clones ===========
[17:32:34] ============= [PASSED] drm_validate_clone_mode =============
[17:32:34] ============= drm_validate_modeset (1 subtest) =============
[17:32:34] [PASSED] drm_test_check_connector_changed_modeset
[17:32:34] ============== [PASSED] drm_validate_modeset ===============
[17:32:34] ====== drm_test_bridge_get_current_state (1 subtest) =======
[17:32:34] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[17:32:34] ======== [PASSED] drm_test_bridge_get_current_state ========
[17:32:34] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[17:32:34] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[17:32:34] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[17:32:34] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[17:32:34] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[17:32:34] ============== drm_bridge_alloc (2 subtests) ===============
[17:32:34] [PASSED] drm_test_drm_bridge_alloc_basic
[17:32:34] [PASSED] drm_test_drm_bridge_alloc_get_put
[17:32:34] ================ [PASSED] drm_bridge_alloc =================
[17:32:34] ============= drm_bridge_bus_fmt (5 subtests) ==============
[17:32:34] [PASSED] drm_test_bridge_rgb_yuv_rgb
[17:32:34] [PASSED] drm_test_bridge_must_convert_to_yuv444
[17:32:34] [PASSED] drm_test_bridge_hdmi_auto_rgb
[17:32:34] [PASSED] drm_test_bridge_auto_first
[17:32:34] [PASSED] drm_test_bridge_rgb_yuv_no_path
[17:32:34] =============== [PASSED] drm_bridge_bus_fmt ================
[17:32:34] ============= drm_cmdline_parser (40 subtests) =============
[17:32:34] [PASSED] drm_test_cmdline_force_d_only
[17:32:34] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:32:34] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:32:34] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:32:34] [PASSED] drm_test_cmdline_force_e_only
[17:32:34] [PASSED] drm_test_cmdline_res
[17:32:34] [PASSED] drm_test_cmdline_res_vesa
[17:32:34] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:32:34] [PASSED] drm_test_cmdline_res_rblank
[17:32:34] [PASSED] drm_test_cmdline_res_bpp
[17:32:34] [PASSED] drm_test_cmdline_res_refresh
[17:32:34] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:32:34] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:32:34] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:32:34] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:32:34] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:32:34] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:32:34] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:32:34] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:32:34] [PASSED] drm_test_cmdline_res_margins_force_on
[17:32:34] [PASSED] drm_test_cmdline_res_vesa_margins
[17:32:34] [PASSED] drm_test_cmdline_name
[17:32:34] [PASSED] drm_test_cmdline_name_bpp
[17:32:34] [PASSED] drm_test_cmdline_name_option
[17:32:34] [PASSED] drm_test_cmdline_name_bpp_option
[17:32:34] [PASSED] drm_test_cmdline_rotate_0
[17:32:34] [PASSED] drm_test_cmdline_rotate_90
[17:32:34] [PASSED] drm_test_cmdline_rotate_180
[17:32:34] [PASSED] drm_test_cmdline_rotate_270
[17:32:34] [PASSED] drm_test_cmdline_hmirror
[17:32:34] [PASSED] drm_test_cmdline_vmirror
[17:32:34] [PASSED] drm_test_cmdline_margin_options
[17:32:34] [PASSED] drm_test_cmdline_multiple_options
[17:32:34] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:32:34] [PASSED] drm_test_cmdline_extra_and_option
[17:32:34] [PASSED] drm_test_cmdline_freestanding_options
[17:32:34] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:32:34] [PASSED] drm_test_cmdline_panel_orientation
[17:32:34] ================ drm_test_cmdline_invalid  =================
[17:32:34] [PASSED] margin_only
[17:32:34] [PASSED] interlace_only
[17:32:34] [PASSED] res_missing_x
[17:32:34] [PASSED] res_missing_y
[17:32:34] [PASSED] res_bad_y
[17:32:34] [PASSED] res_missing_y_bpp
[17:32:34] [PASSED] res_bad_bpp
[17:32:34] [PASSED] res_bad_refresh
[17:32:34] [PASSED] res_bpp_refresh_force_on_off
[17:32:34] [PASSED] res_invalid_mode
[17:32:34] [PASSED] res_bpp_wrong_place_mode
[17:32:34] [PASSED] name_bpp_refresh
[17:32:34] [PASSED] name_refresh
[17:32:34] [PASSED] name_refresh_wrong_mode
[17:32:34] [PASSED] name_refresh_invalid_mode
[17:32:34] [PASSED] rotate_multiple
[17:32:34] [PASSED] rotate_invalid_val
[17:32:34] [PASSED] rotate_truncated
[17:32:34] [PASSED] invalid_option
[17:32:34] [PASSED] invalid_tv_option
[17:32:34] [PASSED] truncated_tv_option
[17:32:34] ============ [PASSED] drm_test_cmdline_invalid =============
[17:32:34] =============== drm_test_cmdline_tv_options  ===============
[17:32:34] [PASSED] NTSC
[17:32:34] [PASSED] NTSC_443
[17:32:34] [PASSED] NTSC_J
[17:32:34] [PASSED] PAL
[17:32:34] [PASSED] PAL_M
[17:32:34] [PASSED] PAL_N
[17:32:34] [PASSED] SECAM
[17:32:34] [PASSED] MONO_525
[17:32:34] [PASSED] MONO_625
[17:32:34] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:32:34] =============== [PASSED] drm_cmdline_parser ================
[17:32:34] ========== drmm_connector_hdmi_init (20 subtests) ==========
[17:32:34] [PASSED] drm_test_connector_hdmi_init_valid
[17:32:34] [PASSED] drm_test_connector_hdmi_init_bpc_8
[17:32:34] [PASSED] drm_test_connector_hdmi_init_bpc_10
[17:32:34] [PASSED] drm_test_connector_hdmi_init_bpc_12
[17:32:34] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[17:32:34] [PASSED] drm_test_connector_hdmi_init_bpc_null
[17:32:34] [PASSED] drm_test_connector_hdmi_init_formats_empty
[17:32:34] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[17:32:34] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[17:32:34] [PASSED] supported_formats=0x9 yuv420_allowed=1
[17:32:34] [PASSED] supported_formats=0x9 yuv420_allowed=0
[17:32:34] [PASSED] supported_formats=0x5 yuv420_allowed=1
[17:32:34] [PASSED] supported_formats=0x5 yuv420_allowed=0
[17:32:34] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:32:34] [PASSED] drm_test_connector_hdmi_init_null_ddc
[17:32:34] [PASSED] drm_test_connector_hdmi_init_null_product
[17:32:34] [PASSED] drm_test_connector_hdmi_init_null_vendor
[17:32:34] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[17:32:34] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[17:32:34] [PASSED] drm_test_connector_hdmi_init_product_valid
[17:32:34] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[17:32:34] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[17:32:34] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[17:32:34] ========= drm_test_connector_hdmi_init_type_valid  =========
[17:32:34] [PASSED] HDMI-A
[17:32:34] [PASSED] HDMI-B
[17:32:34] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[17:32:34] ======== drm_test_connector_hdmi_init_type_invalid  ========
[17:32:34] [PASSED] Unknown
[17:32:34] [PASSED] VGA
[17:32:34] [PASSED] DVI-I
[17:32:34] [PASSED] DVI-D
[17:32:34] [PASSED] DVI-A
[17:32:34] [PASSED] Composite
[17:32:34] [PASSED] SVIDEO
[17:32:34] [PASSED] LVDS
[17:32:34] [PASSED] Component
[17:32:34] [PASSED] DIN
[17:32:34] [PASSED] DP
[17:32:34] [PASSED] TV
[17:32:34] [PASSED] eDP
[17:32:34] [PASSED] Virtual
[17:32:34] [PASSED] DSI
[17:32:34] [PASSED] DPI
[17:32:34] [PASSED] Writeback
[17:32:34] [PASSED] SPI
[17:32:34] [PASSED] USB
[17:32:34] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[17:32:34] ============ [PASSED] drmm_connector_hdmi_init =============
[17:32:34] ============= drmm_connector_init (3 subtests) =============
[17:32:34] [PASSED] drm_test_drmm_connector_init
[17:32:34] [PASSED] drm_test_drmm_connector_init_null_ddc
[17:32:34] ========= drm_test_drmm_connector_init_type_valid  =========
[17:32:34] [PASSED] Unknown
[17:32:34] [PASSED] VGA
[17:32:34] [PASSED] DVI-I
[17:32:34] [PASSED] DVI-D
[17:32:34] [PASSED] DVI-A
[17:32:34] [PASSED] Composite
[17:32:34] [PASSED] SVIDEO
[17:32:34] [PASSED] LVDS
[17:32:34] [PASSED] Component
[17:32:34] [PASSED] DIN
[17:32:34] [PASSED] DP
[17:32:34] [PASSED] HDMI-A
[17:32:34] [PASSED] HDMI-B
[17:32:34] [PASSED] TV
[17:32:34] [PASSED] eDP
[17:32:34] [PASSED] Virtual
[17:32:34] [PASSED] DSI
[17:32:34] [PASSED] DPI
[17:32:34] [PASSED] Writeback
[17:32:34] [PASSED] SPI
[17:32:34] [PASSED] USB
[17:32:34] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[17:32:34] =============== [PASSED] drmm_connector_init ===============
[17:32:34] ========= drm_connector_dynamic_init (6 subtests) ==========
[17:32:34] [PASSED] drm_test_drm_connector_dynamic_init
[17:32:34] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[17:32:34] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[17:32:34] [PASSED] drm_test_drm_connector_dynamic_init_properties
[17:32:34] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[17:32:34] [PASSED] Unknown
[17:32:34] [PASSED] VGA
[17:32:34] [PASSED] DVI-I
[17:32:34] [PASSED] DVI-D
[17:32:34] [PASSED] DVI-A
[17:32:34] [PASSED] Composite
[17:32:34] [PASSED] SVIDEO
[17:32:34] [PASSED] LVDS
[17:32:34] [PASSED] Component
[17:32:34] [PASSED] DIN
[17:32:34] [PASSED] DP
[17:32:34] [PASSED] HDMI-A
[17:32:34] [PASSED] HDMI-B
[17:32:34] [PASSED] TV
[17:32:34] [PASSED] eDP
[17:32:34] [PASSED] Virtual
[17:32:34] [PASSED] DSI
[17:32:34] [PASSED] DPI
[17:32:34] [PASSED] Writeback
[17:32:34] [PASSED] SPI
[17:32:34] [PASSED] USB
[17:32:34] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[17:32:34] ======== drm_test_drm_connector_dynamic_init_name  =========
[17:32:34] [PASSED] Unknown
[17:32:34] [PASSED] VGA
[17:32:34] [PASSED] DVI-I
[17:32:34] [PASSED] DVI-D
[17:32:34] [PASSED] DVI-A
[17:32:34] [PASSED] Composite
[17:32:34] [PASSED] SVIDEO
[17:32:34] [PASSED] LVDS
[17:32:34] [PASSED] Component
[17:32:34] [PASSED] DIN
[17:32:34] [PASSED] DP
[17:32:34] [PASSED] HDMI-A
[17:32:34] [PASSED] HDMI-B
[17:32:34] [PASSED] TV
[17:32:34] [PASSED] eDP
[17:32:34] [PASSED] Virtual
[17:32:34] [PASSED] DSI
[17:32:34] [PASSED] DPI
[17:32:34] [PASSED] Writeback
[17:32:34] [PASSED] SPI
[17:32:34] [PASSED] USB
[17:32:34] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[17:32:34] =========== [PASSED] drm_connector_dynamic_init ============
[17:32:34] ==== drm_connector_dynamic_register_early (4 subtests) =====
[17:32:34] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[17:32:34] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[17:32:34] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[17:32:34] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[17:32:34] ====== [PASSED] drm_connector_dynamic_register_early =======
[17:32:34] ======= drm_connector_dynamic_register (7 subtests) ========
[17:32:34] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[17:32:34] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[17:32:34] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[17:32:34] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[17:32:34] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[17:32:34] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[17:32:34] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[17:32:34] ========= [PASSED] drm_connector_dynamic_register ==========
[17:32:34] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[17:32:34] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[17:32:34] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[17:32:34] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[17:32:34] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:32:34] ========== drm_test_get_tv_mode_from_name_valid  ===========
[17:32:34] [PASSED] NTSC
[17:32:34] [PASSED] NTSC-443
[17:32:34] [PASSED] NTSC-J
[17:32:34] [PASSED] PAL
[17:32:34] [PASSED] PAL-M
[17:32:34] [PASSED] PAL-N
[17:32:34] [PASSED] SECAM
[17:32:34] [PASSED] Mono
[17:32:34] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:32:34] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:32:34] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:32:34] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[17:32:34] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[17:32:34] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[17:32:34] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[17:32:34] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[17:32:34] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[17:32:34] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[17:32:34] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[17:32:34] [PASSED] VIC 96
[17:32:34] [PASSED] VIC 97
[17:32:34] [PASSED] VIC 101
[17:32:34] [PASSED] VIC 102
[17:32:34] [PASSED] VIC 106
[17:32:34] [PASSED] VIC 107
[17:32:34] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[17:32:34] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[17:32:34] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[17:32:34] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[17:32:34] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[17:32:34] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[17:32:34] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[17:32:34] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[17:32:34] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[17:32:34] [PASSED] Automatic
[17:32:34] [PASSED] Full
[17:32:34] [PASSED] Limited 16:235
[17:32:34] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[17:32:34] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[17:32:34] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[17:32:34] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[17:32:34] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[17:32:34] [PASSED] RGB
[17:32:34] [PASSED] YUV 4:2:0
[17:32:34] [PASSED] YUV 4:2:2
[17:32:34] [PASSED] YUV 4:4:4
[17:32:34] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[17:32:34] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[17:32:34] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[17:32:34] ============= drm_damage_helper (21 subtests) ==============
[17:32:34] [PASSED] drm_test_damage_iter_no_damage
[17:32:34] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:32:34] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:32:34] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:32:34] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:32:34] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:32:34] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:32:34] [PASSED] drm_test_damage_iter_simple_damage
[17:32:34] [PASSED] drm_test_damage_iter_single_damage
[17:32:34] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:32:34] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:32:34] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:32:34] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:32:34] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:32:34] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:32:34] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:32:34] [PASSED] drm_test_damage_iter_damage
[17:32:34] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:32:34] [PASSED] drm_test_damage_iter_damage_one_outside
[17:32:34] [PASSED] drm_test_damage_iter_damage_src_moved
[17:32:34] [PASSED] drm_test_damage_iter_damage_not_visible
[17:32:34] ================ [PASSED] drm_damage_helper ================
[17:32:34] ============== drm_dp_mst_helper (3 subtests) ==============
[17:32:34] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[17:32:34] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:32:34] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:32:34] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:32:34] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:32:34] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:32:34] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:32:34] ============== drm_test_dp_mst_calc_pbn_div  ===============
[17:32:34] [PASSED] Link rate 2000000 lane count 4
[17:32:34] [PASSED] Link rate 2000000 lane count 2
[17:32:34] [PASSED] Link rate 2000000 lane count 1
[17:32:34] [PASSED] Link rate 1350000 lane count 4
[17:32:34] [PASSED] Link rate 1350000 lane count 2
[17:32:34] [PASSED] Link rate 1350000 lane count 1
[17:32:34] [PASSED] Link rate 1000000 lane count 4
[17:32:34] [PASSED] Link rate 1000000 lane count 2
[17:32:34] [PASSED] Link rate 1000000 lane count 1
[17:32:34] [PASSED] Link rate 810000 lane count 4
[17:32:34] [PASSED] Link rate 810000 lane count 2
[17:32:34] [PASSED] Link rate 810000 lane count 1
[17:32:34] [PASSED] Link rate 540000 lane count 4
[17:32:34] [PASSED] Link rate 540000 lane count 2
[17:32:34] [PASSED] Link rate 540000 lane count 1
[17:32:34] [PASSED] Link rate 270000 lane count 4
[17:32:34] [PASSED] Link rate 270000 lane count 2
[17:32:34] [PASSED] Link rate 270000 lane count 1
[17:32:34] [PASSED] Link rate 162000 lane count 4
[17:32:34] [PASSED] Link rate 162000 lane count 2
[17:32:34] [PASSED] Link rate 162000 lane count 1
[17:32:34] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[17:32:34] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[17:32:34] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:32:34] [PASSED] DP_POWER_UP_PHY with port number
[17:32:34] [PASSED] DP_POWER_DOWN_PHY with port number
[17:32:34] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:32:34] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:32:34] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:32:34] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:32:34] [PASSED] DP_QUERY_PAYLOAD with port number
[17:32:34] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:32:34] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:32:34] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:32:34] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:32:34] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:32:34] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:32:34] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:32:34] [PASSED] DP_REMOTE_I2C_READ with port number
[17:32:34] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:32:34] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:32:34] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:32:34] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:32:34] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:32:34] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:32:34] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:32:34] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:32:34] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:32:34] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:32:34] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:32:34] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:32:34] ================ [PASSED] drm_dp_mst_helper ================
[17:32:34] ================== drm_exec (7 subtests) ===================
[17:32:34] [PASSED] sanitycheck
[17:32:34] [PASSED] test_lock
[17:32:34] [PASSED] test_lock_unlock
[17:32:34] [PASSED] test_duplicates
[17:32:34] [PASSED] test_prepare
[17:32:34] [PASSED] test_prepare_array
[17:32:34] [PASSED] test_multiple_loops
[17:32:34] ==================== [PASSED] drm_exec =====================
[17:32:34] =========== drm_format_helper_test (17 subtests) ===========
[17:32:34] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[17:32:34] [PASSED] single_pixel_source_buffer
[17:32:34] [PASSED] single_pixel_clip_rectangle
[17:32:34] [PASSED] well_known_colors
[17:32:34] [PASSED] destination_pitch
[17:32:34] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:32:34] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[17:32:34] [PASSED] single_pixel_source_buffer
[17:32:34] [PASSED] single_pixel_clip_rectangle
[17:32:34] [PASSED] well_known_colors
[17:32:34] [PASSED] destination_pitch
[17:32:34] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:32:34] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[17:32:34] [PASSED] single_pixel_source_buffer
[17:32:34] [PASSED] single_pixel_clip_rectangle
[17:32:34] [PASSED] well_known_colors
[17:32:34] [PASSED] destination_pitch
[17:32:34] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:32:34] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[17:32:34] [PASSED] single_pixel_source_buffer
[17:32:35] [PASSED] single_pixel_clip_rectangle
[17:32:35] [PASSED] well_known_colors
[17:32:35] [PASSED] destination_pitch
[17:32:35] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:32:35] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[17:32:35] [PASSED] single_pixel_source_buffer
[17:32:35] [PASSED] single_pixel_clip_rectangle
[17:32:35] [PASSED] well_known_colors
[17:32:35] [PASSED] destination_pitch
[17:32:35] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:32:35] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[17:32:35] [PASSED] single_pixel_source_buffer
[17:32:35] [PASSED] single_pixel_clip_rectangle
[17:32:35] [PASSED] well_known_colors
[17:32:35] [PASSED] destination_pitch
[17:32:35] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:32:35] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[17:32:35] [PASSED] single_pixel_source_buffer
[17:32:35] [PASSED] single_pixel_clip_rectangle
[17:32:35] [PASSED] well_known_colors
[17:32:35] [PASSED] destination_pitch
[17:32:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:32:35] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[17:32:35] [PASSED] single_pixel_source_buffer
[17:32:35] [PASSED] single_pixel_clip_rectangle
[17:32:35] [PASSED] well_known_colors
[17:32:35] [PASSED] destination_pitch
[17:32:35] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[17:32:35] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[17:32:35] [PASSED] single_pixel_source_buffer
[17:32:35] [PASSED] single_pixel_clip_rectangle
[17:32:35] [PASSED] well_known_colors
[17:32:35] [PASSED] destination_pitch
[17:32:35] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:32:35] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[17:32:35] [PASSED] single_pixel_source_buffer
[17:32:35] [PASSED] single_pixel_clip_rectangle
[17:32:35] [PASSED] well_known_colors
[17:32:35] [PASSED] destination_pitch
[17:32:35] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:32:35] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[17:32:35] [PASSED] single_pixel_source_buffer
[17:32:35] [PASSED] single_pixel_clip_rectangle
[17:32:35] [PASSED] well_known_colors
[17:32:35] [PASSED] destination_pitch
[17:32:35] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:32:35] ============== drm_test_fb_xrgb8888_to_mono  ===============
[17:32:35] [PASSED] single_pixel_source_buffer
[17:32:35] [PASSED] single_pixel_clip_rectangle
[17:32:35] [PASSED] well_known_colors
[17:32:35] [PASSED] destination_pitch
[17:32:35] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:32:35] ==================== drm_test_fb_swab  =====================
[17:32:35] [PASSED] single_pixel_source_buffer
[17:32:35] [PASSED] single_pixel_clip_rectangle
[17:32:35] [PASSED] well_known_colors
[17:32:35] [PASSED] destination_pitch
[17:32:35] ================ [PASSED] drm_test_fb_swab =================
[17:32:35] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[17:32:35] [PASSED] single_pixel_source_buffer
[17:32:35] [PASSED] single_pixel_clip_rectangle
[17:32:35] [PASSED] well_known_colors
[17:32:35] [PASSED] destination_pitch
[17:32:35] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[17:32:35] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[17:32:35] [PASSED] single_pixel_source_buffer
[17:32:35] [PASSED] single_pixel_clip_rectangle
[17:32:35] [PASSED] well_known_colors
[17:32:35] [PASSED] destination_pitch
[17:32:35] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[17:32:35] ================= drm_test_fb_clip_offset  =================
[17:32:35] [PASSED] pass through
[17:32:35] [PASSED] horizontal offset
[17:32:35] [PASSED] vertical offset
[17:32:35] [PASSED] horizontal and vertical offset
[17:32:35] [PASSED] horizontal offset (custom pitch)
[17:32:35] [PASSED] vertical offset (custom pitch)
[17:32:35] [PASSED] horizontal and vertical offset (custom pitch)
[17:32:35] ============= [PASSED] drm_test_fb_clip_offset =============
[17:32:35] =================== drm_test_fb_memcpy  ====================
[17:32:35] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[17:32:35] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[17:32:35] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[17:32:35] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[17:32:35] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[17:32:35] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[17:32:35] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[17:32:35] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[17:32:35] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[17:32:35] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[17:32:35] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[17:32:35] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[17:32:35] =============== [PASSED] drm_test_fb_memcpy ================
[17:32:35] ============= [PASSED] drm_format_helper_test ==============
[17:32:35] ================= drm_format (18 subtests) =================
[17:32:35] [PASSED] drm_test_format_block_width_invalid
[17:32:35] [PASSED] drm_test_format_block_width_one_plane
[17:32:35] [PASSED] drm_test_format_block_width_two_plane
[17:32:35] [PASSED] drm_test_format_block_width_three_plane
[17:32:35] [PASSED] drm_test_format_block_width_tiled
[17:32:35] [PASSED] drm_test_format_block_height_invalid
[17:32:35] [PASSED] drm_test_format_block_height_one_plane
[17:32:35] [PASSED] drm_test_format_block_height_two_plane
[17:32:35] [PASSED] drm_test_format_block_height_three_plane
[17:32:35] [PASSED] drm_test_format_block_height_tiled
[17:32:35] [PASSED] drm_test_format_min_pitch_invalid
[17:32:35] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:32:35] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:32:35] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:32:35] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:32:35] [PASSED] drm_test_format_min_pitch_two_plane
[17:32:35] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:32:35] [PASSED] drm_test_format_min_pitch_tiled
[17:32:35] =================== [PASSED] drm_format ====================
[17:32:35] ============== drm_framebuffer (10 subtests) ===============
[17:32:35] ========== drm_test_framebuffer_check_src_coords  ==========
[17:32:35] [PASSED] Success: source fits into fb
[17:32:35] [PASSED] Fail: overflowing fb with x-axis coordinate
[17:32:35] [PASSED] Fail: overflowing fb with y-axis coordinate
[17:32:35] [PASSED] Fail: overflowing fb with source width
[17:32:35] [PASSED] Fail: overflowing fb with source height
[17:32:35] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[17:32:35] [PASSED] drm_test_framebuffer_cleanup
[17:32:35] =============== drm_test_framebuffer_create  ===============
[17:32:35] [PASSED] ABGR8888 normal sizes
[17:32:35] [PASSED] ABGR8888 max sizes
[17:32:35] [PASSED] ABGR8888 pitch greater than min required
[17:32:35] [PASSED] ABGR8888 pitch less than min required
[17:32:35] [PASSED] ABGR8888 Invalid width
[17:32:35] [PASSED] ABGR8888 Invalid buffer handle
[17:32:35] [PASSED] No pixel format
[17:32:35] [PASSED] ABGR8888 Width 0
[17:32:35] [PASSED] ABGR8888 Height 0
[17:32:35] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:32:35] [PASSED] ABGR8888 Large buffer offset
[17:32:35] [PASSED] ABGR8888 Buffer offset for inexistent plane
[17:32:35] [PASSED] ABGR8888 Invalid flag
[17:32:35] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:32:35] [PASSED] ABGR8888 Valid buffer modifier
[17:32:35] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:32:35] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:32:35] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:32:35] [PASSED] NV12 Normal sizes
[17:32:35] [PASSED] NV12 Max sizes
[17:32:35] [PASSED] NV12 Invalid pitch
[17:32:35] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:32:35] [PASSED] NV12 different  modifier per-plane
[17:32:35] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:32:35] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:32:35] [PASSED] NV12 Modifier for inexistent plane
[17:32:35] [PASSED] NV12 Handle for inexistent plane
[17:32:35] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:32:35] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:32:35] [PASSED] YVU420 Normal sizes
[17:32:35] [PASSED] YVU420 Max sizes
[17:32:35] [PASSED] YVU420 Invalid pitch
[17:32:35] [PASSED] YVU420 Different pitches
[17:32:35] [PASSED] YVU420 Different buffer offsets/pitches
[17:32:35] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:32:35] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:32:35] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:32:35] [PASSED] YVU420 Valid modifier
[17:32:35] [PASSED] YVU420 Different modifiers per plane
[17:32:35] [PASSED] YVU420 Modifier for inexistent plane
[17:32:35] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[17:32:35] [PASSED] X0L2 Normal sizes
[17:32:35] [PASSED] X0L2 Max sizes
[17:32:35] [PASSED] X0L2 Invalid pitch
[17:32:35] [PASSED] X0L2 Pitch greater than minimum required
[17:32:35] [PASSED] X0L2 Handle for inexistent plane
[17:32:35] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:32:35] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:32:35] [PASSED] X0L2 Valid modifier
[17:32:35] [PASSED] X0L2 Modifier for inexistent plane
[17:32:35] =========== [PASSED] drm_test_framebuffer_create ===========
[17:32:35] [PASSED] drm_test_framebuffer_free
[17:32:35] [PASSED] drm_test_framebuffer_init
[17:32:35] [PASSED] drm_test_framebuffer_init_bad_format
[17:32:35] [PASSED] drm_test_framebuffer_init_dev_mismatch
[17:32:35] [PASSED] drm_test_framebuffer_lookup
[17:32:35] [PASSED] drm_test_framebuffer_lookup_inexistent
[17:32:35] [PASSED] drm_test_framebuffer_modifiers_not_supported
[17:32:35] ================= [PASSED] drm_framebuffer =================
[17:32:35] ================ drm_gem_shmem (8 subtests) ================
[17:32:35] [PASSED] drm_gem_shmem_test_obj_create
[17:32:35] [PASSED] drm_gem_shmem_test_obj_create_private
[17:32:35] [PASSED] drm_gem_shmem_test_pin_pages
[17:32:35] [PASSED] drm_gem_shmem_test_vmap
[17:32:35] [PASSED] drm_gem_shmem_test_get_sg_table
[17:32:35] [PASSED] drm_gem_shmem_test_get_pages_sgt
[17:32:35] [PASSED] drm_gem_shmem_test_madvise
[17:32:35] [PASSED] drm_gem_shmem_test_purge
[17:32:35] ================== [PASSED] drm_gem_shmem ==================
[17:32:35] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[17:32:35] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[17:32:35] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[17:32:35] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[17:32:35] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[17:32:35] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[17:32:35] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[17:32:35] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[17:32:35] [PASSED] Automatic
[17:32:35] [PASSED] Full
[17:32:35] [PASSED] Limited 16:235
[17:32:35] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[17:32:35] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[17:32:35] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[17:32:35] [PASSED] drm_test_check_disable_connector
[17:32:35] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[17:32:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[17:32:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[17:32:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[17:32:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[17:32:35] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[17:32:35] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[17:32:35] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[17:32:35] [PASSED] drm_test_check_output_bpc_dvi
[17:32:35] [PASSED] drm_test_check_output_bpc_format_vic_1
[17:32:35] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[17:32:35] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[17:32:35] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[17:32:35] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[17:32:35] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[17:32:35] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[17:32:35] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[17:32:35] ============ drm_test_check_hdmi_color_format  =============
[17:32:35] [PASSED] AUTO -> RGB
[17:32:35] [PASSED] YCBCR422 -> YUV422
[17:32:35] [PASSED] YCBCR420 -> YUV420
[17:32:35] [PASSED] YCBCR444 -> YUV444
[17:32:35] [PASSED] RGB -> RGB
[17:32:35] ======== [PASSED] drm_test_check_hdmi_color_format =========
[17:32:35] ======== drm_test_check_hdmi_color_format_420_only  ========
[17:32:35] [PASSED] RGB should fail
[17:32:35] [PASSED] YUV444 should fail
[17:32:35] [PASSED] YUV422 should fail
[17:32:35] [PASSED] YUV420 should work
[17:32:35] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[17:32:35] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[17:32:35] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[17:32:35] [PASSED] drm_test_check_broadcast_rgb_value
[17:32:35] [PASSED] drm_test_check_bpc_8_value
[17:32:35] [PASSED] drm_test_check_bpc_10_value
[17:32:35] [PASSED] drm_test_check_bpc_12_value
[17:32:35] [PASSED] drm_test_check_format_value
[17:32:35] [PASSED] drm_test_check_tmds_char_value
[17:32:35] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[17:32:35] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[17:32:35] [PASSED] drm_test_check_mode_valid
[17:32:35] [PASSED] drm_test_check_mode_valid_reject
[17:32:35] [PASSED] drm_test_check_mode_valid_reject_rate
[17:32:35] [PASSED] drm_test_check_mode_valid_reject_max_clock
[17:32:35] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[17:32:35] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[17:32:35] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[17:32:35] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[17:32:35] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[17:32:35] [PASSED] drm_test_check_infoframes
[17:32:35] [PASSED] drm_test_check_reject_avi_infoframe
[17:32:35] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[17:32:35] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[17:32:35] [PASSED] drm_test_check_reject_audio_infoframe
[17:32:35] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[17:32:35] ================= drm_managed (2 subtests) =================
[17:32:35] [PASSED] drm_test_managed_release_action
[17:32:35] [PASSED] drm_test_managed_run_action
[17:32:35] =================== [PASSED] drm_managed ===================
[17:32:35] =================== drm_mm (6 subtests) ====================
[17:32:35] [PASSED] drm_test_mm_init
[17:32:35] [PASSED] drm_test_mm_debug
[17:32:35] [PASSED] drm_test_mm_align32
[17:32:35] [PASSED] drm_test_mm_align64
[17:32:35] [PASSED] drm_test_mm_lowest
[17:32:35] [PASSED] drm_test_mm_highest
[17:32:35] ===================== [PASSED] drm_mm ======================
[17:32:35] ============= drm_modes_analog_tv (5 subtests) =============
[17:32:35] [PASSED] drm_test_modes_analog_tv_mono_576i
[17:32:35] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:32:35] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:32:35] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:32:35] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:32:35] =============== [PASSED] drm_modes_analog_tv ===============
[17:32:35] ============== drm_plane_helper (2 subtests) ===============
[17:32:35] =============== drm_test_check_plane_state  ================
[17:32:35] [PASSED] clipping_simple
[17:32:35] [PASSED] clipping_rotate_reflect
[17:32:35] [PASSED] positioning_simple
[17:32:35] [PASSED] upscaling
[17:32:35] [PASSED] downscaling
[17:32:35] [PASSED] rounding1
[17:32:35] [PASSED] rounding2
[17:32:35] [PASSED] rounding3
[17:32:35] [PASSED] rounding4
[17:32:35] =========== [PASSED] drm_test_check_plane_state ============
[17:32:35] =========== drm_test_check_invalid_plane_state  ============
[17:32:35] [PASSED] positioning_invalid
[17:32:35] [PASSED] upscaling_invalid
[17:32:35] [PASSED] downscaling_invalid
[17:32:35] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:32:35] ================ [PASSED] drm_plane_helper =================
[17:32:35] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:32:35] ====== drm_test_connector_helper_tv_get_modes_check  =======
[17:32:35] [PASSED] None
[17:32:35] [PASSED] PAL
[17:32:35] [PASSED] NTSC
[17:32:35] [PASSED] Both, NTSC Default
[17:32:35] [PASSED] Both, PAL Default
[17:32:35] [PASSED] Both, NTSC Default, with PAL on command-line
[17:32:35] [PASSED] Both, PAL Default, with NTSC on command-line
[17:32:35] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:32:35] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:32:35] ================== drm_rect (9 subtests) ===================
[17:32:35] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:32:35] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:32:35] [PASSED] drm_test_rect_clip_scaled_clipped
[17:32:35] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:32:35] ================= drm_test_rect_intersect  =================
[17:32:35] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:32:35] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:32:35] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:32:35] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:32:35] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:32:35] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:32:35] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:32:35] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:32:35] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:32:35] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:32:35] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:32:35] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:32:35] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:32:35] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:32:35] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[17:32:35] ============= [PASSED] drm_test_rect_intersect =============
[17:32:35] ================ drm_test_rect_calc_hscale  ================
[17:32:35] [PASSED] normal use
[17:32:35] [PASSED] out of max range
[17:32:35] [PASSED] out of min range
[17:32:35] [PASSED] zero dst
[17:32:35] [PASSED] negative src
[17:32:35] [PASSED] negative dst
[17:32:35] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:32:35] ================ drm_test_rect_calc_vscale  ================
[17:32:35] [PASSED] normal use
[17:32:35] [PASSED] out of max range
[17:32:35] [PASSED] out of min range
[17:32:35] [PASSED] zero dst
[17:32:35] [PASSED] negative src
[17:32:35] [PASSED] negative dst
[17:32:35] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:32:35] ================== drm_test_rect_rotate  ===================
[17:32:35] [PASSED] reflect-x
[17:32:35] [PASSED] reflect-y
[17:32:35] [PASSED] rotate-0
[17:32:35] [PASSED] rotate-90
[17:32:35] [PASSED] rotate-180
[17:32:35] [PASSED] rotate-270
[17:32:35] ============== [PASSED] drm_test_rect_rotate ===============
[17:32:35] ================ drm_test_rect_rotate_inv  =================
[17:32:35] [PASSED] reflect-x
[17:32:35] [PASSED] reflect-y
[17:32:35] [PASSED] rotate-0
[17:32:35] [PASSED] rotate-90
[17:32:35] [PASSED] rotate-180
[17:32:35] [PASSED] rotate-270
[17:32:35] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:32:35] ==================== [PASSED] drm_rect =====================
[17:32:35] ============ drm_sysfb_modeset_test (1 subtest) ============
[17:32:35] ============ drm_test_sysfb_build_fourcc_list  =============
[17:32:35] [PASSED] no native formats
[17:32:35] [PASSED] XRGB8888 as native format
[17:32:35] [PASSED] remove duplicates
[17:32:35] [PASSED] convert alpha formats
[17:32:35] [PASSED] random formats
[17:32:35] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[17:32:35] ============= [PASSED] drm_sysfb_modeset_test ==============
[17:32:35] ================== drm_fixp (2 subtests) ===================
[17:32:35] [PASSED] drm_test_int2fixp
[17:32:35] [PASSED] drm_test_sm2fixp
[17:32:35] ==================== [PASSED] drm_fixp =====================
[17:32:35] ============================================================
[17:32:35] Testing complete. Ran 641 tests: passed: 641
[17:32:35] Elapsed time: 26.915s total, 1.861s configuring, 24.888s building, 0.139s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[17:32:35] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:32:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:32:47] Starting KUnit Kernel (1/1)...
[17:32:47] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:32:47] ============= refcount_interrupt (4 subtests) ==============
[17:32:47] [PASSED] test_single_irq_change
[17:32:47] [PASSED] test_nested_irq_change
[17:32:47] [PASSED] test_multiple_irq_change
[17:32:47] [PASSED] test_irq_save
[17:32:47] =============== [PASSED] refcount_interrupt ================
[17:32:47] ================= ttm_device (5 subtests) ==================
[17:32:47] [PASSED] ttm_device_init_basic
[17:32:47] [PASSED] ttm_device_init_multiple
[17:32:47] [PASSED] ttm_device_fini_basic
[17:32:47] [PASSED] ttm_device_init_no_vma_man
[17:32:47] ================== ttm_device_init_pools  ==================
[17:32:47] [PASSED] No DMA allocations, no DMA32 required
[17:32:47] [PASSED] DMA allocations, DMA32 required
[17:32:47] [PASSED] No DMA allocations, DMA32 required
[17:32:47] [PASSED] DMA allocations, no DMA32 required
[17:32:47] ============== [PASSED] ttm_device_init_pools ==============
[17:32:47] =================== [PASSED] ttm_device ====================
[17:32:47] ================== ttm_pool (8 subtests) ===================
[17:32:47] ================== ttm_pool_alloc_basic  ===================
[17:32:47] [PASSED] One page
[17:32:47] [PASSED] More than one page
[17:32:47] [PASSED] Above the allocation limit
[17:32:47] [PASSED] One page, with coherent DMA mappings enabled
[17:32:47] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:32:47] ============== [PASSED] ttm_pool_alloc_basic ===============
[17:32:47] ============== ttm_pool_alloc_basic_dma_addr  ==============
[17:32:47] [PASSED] One page
[17:32:47] [PASSED] More than one page
[17:32:47] [PASSED] Above the allocation limit
[17:32:47] [PASSED] One page, with coherent DMA mappings enabled
[17:32:47] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:32:47] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[17:32:47] [PASSED] ttm_pool_alloc_order_caching_match
[17:32:47] [PASSED] ttm_pool_alloc_caching_mismatch
[17:32:47] [PASSED] ttm_pool_alloc_order_mismatch
[17:32:47] [PASSED] ttm_pool_free_dma_alloc
[17:32:47] [PASSED] ttm_pool_free_no_dma_alloc
[17:32:47] [PASSED] ttm_pool_fini_basic
[17:32:47] ==================== [PASSED] ttm_pool =====================
[17:32:47] ================ ttm_resource (8 subtests) =================
[17:32:47] ================= ttm_resource_init_basic  =================
[17:32:47] [PASSED] Init resource in TTM_PL_SYSTEM
[17:32:47] [PASSED] Init resource in TTM_PL_VRAM
[17:32:47] [PASSED] Init resource in a private placement
[17:32:47] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[17:32:47] ============= [PASSED] ttm_resource_init_basic =============
[17:32:47] [PASSED] ttm_resource_init_pinned
[17:32:47] [PASSED] ttm_resource_fini_basic
[17:32:47] [PASSED] ttm_resource_manager_init_basic
[17:32:47] [PASSED] ttm_resource_manager_usage_basic
[17:32:47] [PASSED] ttm_resource_manager_set_used_basic
[17:32:47] [PASSED] ttm_sys_man_alloc_basic
[17:32:47] [PASSED] ttm_sys_man_free_basic
[17:32:47] ================== [PASSED] ttm_resource ===================
[17:32:47] =================== ttm_tt (15 subtests) ===================
[17:32:47] ==================== ttm_tt_init_basic  ====================
[17:32:47] [PASSED] Page-aligned size
[17:32:47] [PASSED] Extra pages requested
[17:32:47] ================ [PASSED] ttm_tt_init_basic ================
[17:32:47] [PASSED] ttm_tt_init_misaligned
[17:32:47] [PASSED] ttm_tt_fini_basic
[17:32:47] [PASSED] ttm_tt_fini_sg
[17:32:47] [PASSED] ttm_tt_fini_shmem
[17:32:47] [PASSED] ttm_tt_create_basic
[17:32:47] [PASSED] ttm_tt_create_invalid_bo_type
[17:32:47] [PASSED] ttm_tt_create_ttm_exists
[17:32:47] [PASSED] ttm_tt_create_failed
[17:32:47] [PASSED] ttm_tt_destroy_basic
[17:32:47] [PASSED] ttm_tt_populate_null_ttm
[17:32:47] [PASSED] ttm_tt_populate_populated_ttm
[17:32:47] [PASSED] ttm_tt_unpopulate_basic
[17:32:47] [PASSED] ttm_tt_unpopulate_empty_ttm
[17:32:47] [PASSED] ttm_tt_swapin_basic
[17:32:47] ===================== [PASSED] ttm_tt ======================
[17:32:47] =================== ttm_bo (14 subtests) ===================
[17:32:47] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[17:32:47] [PASSED] Cannot be interrupted and sleeps
[17:32:47] [PASSED] Cannot be interrupted, locks straight away
[17:32:47] [PASSED] Can be interrupted, sleeps
[17:32:47] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[17:32:47] [PASSED] ttm_bo_reserve_locked_no_sleep
[17:32:47] [PASSED] ttm_bo_reserve_no_wait_ticket
[17:32:47] [PASSED] ttm_bo_reserve_double_resv
[17:32:47] [PASSED] ttm_bo_reserve_interrupted
[17:32:47] [PASSED] ttm_bo_reserve_deadlock
[17:32:47] [PASSED] ttm_bo_unreserve_basic
[17:32:47] [PASSED] ttm_bo_unreserve_pinned
[17:32:47] [PASSED] ttm_bo_unreserve_bulk
[17:32:47] [PASSED] ttm_bo_fini_basic
[17:32:47] [PASSED] ttm_bo_fini_shared_resv
[17:32:47] [PASSED] ttm_bo_pin_basic
[17:32:47] [PASSED] ttm_bo_pin_unpin_resource
[17:32:47] [PASSED] ttm_bo_multiple_pin_one_unpin
[17:32:47] ===================== [PASSED] ttm_bo ======================
[17:32:47] ============== ttm_bo_validate (22 subtests) ===============
[17:32:47] ============== ttm_bo_init_reserved_sys_man  ===============
[17:32:47] [PASSED] Buffer object for userspace
[17:32:47] [PASSED] Kernel buffer object
[17:32:47] [PASSED] Shared buffer object
[17:32:47] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[17:32:47] ============== ttm_bo_init_reserved_mock_man  ==============
[17:32:47] [PASSED] Buffer object for userspace
[17:32:47] [PASSED] Kernel buffer object
[17:32:47] [PASSED] Shared buffer object
[17:32:47] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[17:32:47] [PASSED] ttm_bo_init_reserved_resv
[17:32:47] ================== ttm_bo_validate_basic  ==================
[17:32:47] [PASSED] Buffer object for userspace
[17:32:47] [PASSED] Kernel buffer object
[17:32:47] [PASSED] Shared buffer object
[17:32:47] ============== [PASSED] ttm_bo_validate_basic ==============
[17:32:47] [PASSED] ttm_bo_validate_invalid_placement
[17:32:47] ============= ttm_bo_validate_same_placement  ==============
[17:32:47] [PASSED] System manager
[17:32:47] [PASSED] VRAM manager
[17:32:47] ========= [PASSED] ttm_bo_validate_same_placement ==========
[17:32:47] [PASSED] ttm_bo_validate_failed_alloc
[17:32:47] [PASSED] ttm_bo_validate_pinned
[17:32:47] [PASSED] ttm_bo_validate_busy_placement
[17:32:47] ================ ttm_bo_validate_multihop  =================
[17:32:47] [PASSED] Buffer object for userspace
[17:32:47] [PASSED] Kernel buffer object
[17:32:47] [PASSED] Shared buffer object
[17:32:47] ============ [PASSED] ttm_bo_validate_multihop =============
[17:32:47] ========== ttm_bo_validate_no_placement_signaled  ==========
[17:32:47] [PASSED] Buffer object in system domain, no page vector
[17:32:47] [PASSED] Buffer object in system domain with an existing page vector
[17:32:47] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[17:32:47] ======== ttm_bo_validate_no_placement_not_signaled  ========
[17:32:47] [PASSED] Buffer object for userspace
[17:32:47] [PASSED] Kernel buffer object
[17:32:47] [PASSED] Shared buffer object
[17:32:47] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[17:32:47] [PASSED] ttm_bo_validate_move_fence_signaled
[17:32:47] ========= ttm_bo_validate_move_fence_not_signaled  =========
[17:32:47] [PASSED] Waits for GPU
[17:32:47] [PASSED] Tries to lock straight away
[17:32:47] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[17:32:47] [PASSED] ttm_bo_validate_swapout
[17:32:47] [PASSED] ttm_bo_validate_happy_evict
[17:32:47] [PASSED] ttm_bo_validate_all_pinned_evict
[17:32:47] [PASSED] ttm_bo_validate_allowed_only_evict
[17:32:47] [PASSED] ttm_bo_validate_deleted_evict
[17:32:47] [PASSED] ttm_bo_validate_busy_domain_evict
[17:32:47] [PASSED] ttm_bo_validate_evict_gutting
[17:32:47] [PASSED] ttm_bo_validate_recrusive_evict
[17:32:47] ================= [PASSED] ttm_bo_validate =================
[17:32:47] ============================================================
[17:32:47] Testing complete. Ran 106 tests: passed: 106
[17:32:47] Elapsed time: 12.150s total, 1.843s configuring, 10.042s building, 0.234s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[17:32:47] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:32:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:32:58] Starting KUnit Kernel (1/1)...
[17:32:58] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:32:58] ============= refcount_interrupt (4 subtests) ==============
[17:32:58] [PASSED] test_single_irq_change
[17:32:58] [PASSED] test_nested_irq_change
[17:32:58] [PASSED] test_multiple_irq_change
[17:32:58] [PASSED] test_irq_save
[17:32:58] =============== [PASSED] refcount_interrupt ================
[17:32:58] =============== dma-buf-fence (12 subtests) ================
[17:32:58] [PASSED] test_sanitycheck
[17:32:58] [PASSED] test_signaling
[17:32:58] [PASSED] test_add_callback
[17:32:58] [PASSED] test_late_add_callback
[17:32:58] [PASSED] test_rm_callback
[17:32:58] [PASSED] test_late_rm_callback
[17:32:58] [PASSED] test_status
[17:32:58] [PASSED] test_error
[17:32:58] [PASSED] test_wait
[17:32:58] [PASSED] test_wait_timeout
[17:32:58] [PASSED] test_stub
[17:32:58] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[17:32:58] ================== [PASSED] dma-buf-fence ==================
[17:32:58] ============ dma-buf-fence-chain (11 subtests) =============
[17:32:58] [PASSED] test_sanitycheck
[17:32:58] [PASSED] test_find_seqno
[17:32:58] [PASSED] test_find_signaled
[17:32:58] [PASSED] test_find_out_of_order
[17:33:03] [PASSED] test_find_gap
[17:33:03] [PASSED] test_find_race
[17:33:03] [PASSED] test_signal_forward
[17:33:03] [PASSED] test_signal_backward
[17:33:03] [PASSED] test_wait_forward
[17:33:03] [PASSED] test_wait_backward
[17:33:03] [PASSED] test_wait_random
[17:33:03] =============== [PASSED] dma-buf-fence-chain ===============
[17:33:03] ============ dma-buf-fence-unwrap (10 subtests) ============
[17:33:03] [PASSED] test_sanitycheck
[17:33:03] [PASSED] test_unwrap_array
[17:33:03] [PASSED] test_unwrap_chain
[17:33:03] [PASSED] test_unwrap_chain_array
[17:33:03] [PASSED] test_unwrap_merge
[17:33:03] [PASSED] test_unwrap_merge_duplicate
[17:33:03] [PASSED] test_unwrap_merge_seqno
[17:33:03] [PASSED] test_unwrap_merge_order
[17:33:03] [PASSED] test_unwrap_merge_complex
[17:33:03] [PASSED] test_unwrap_merge_complex_seqno
[17:33:03] ============== [PASSED] dma-buf-fence-unwrap ===============
[17:33:03] ================ dma-buf-resv (5 subtests) =================
[17:33:03] [PASSED] test_sanitycheck
[17:33:03] ===================== test_signaling  ======================
[17:33:03] [PASSED] kernel
[17:33:03] [PASSED] write
[17:33:03] [PASSED] read
[17:33:03] [PASSED] bookkeep
[17:33:03] ================= [PASSED] test_signaling ==================
[17:33:03] ====================== test_for_each  ======================
[17:33:03] [PASSED] kernel
[17:33:03] [PASSED] write
[17:33:03] [PASSED] read
[17:33:03] [PASSED] bookkeep
[17:33:03] ================== [PASSED] test_for_each ==================
[17:33:03] ================= test_for_each_unlocked  ==================
[17:33:03] [PASSED] kernel
[17:33:03] [PASSED] write
[17:33:03] [PASSED] read
[17:33:03] [PASSED] bookkeep
[17:33:03] ============= [PASSED] test_for_each_unlocked ==============
[17:33:03] ===================== test_get_fences  =====================
[17:33:03] [PASSED] kernel
[17:33:03] [PASSED] write
[17:33:03] [PASSED] read
[17:33:03] [PASSED] bookkeep
[17:33:03] ================= [PASSED] test_get_fences =================
[17:33:03] ================== [PASSED] dma-buf-resv ===================
[17:33:03] ============================================================
[17:33:03] Testing complete. Ran 54 tests: passed: 53, skipped: 1
[17:33:03] Elapsed time: 15.951s total, 1.826s configuring, 8.754s building, 5.336s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Add support for Common SDP Transmission Line (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2386 bytes --]

== Series Details ==

Series: Add support for Common SDP Transmission Line (rev7)
URL   : https://patchwork.freedesktop.org/series/162623/
State : success

== Summary ==

CI Bug Log - changes from xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6_BAT -> xe-pw-162623v7_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (15 -> 15)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-162623v7_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@reltime:
    - bat-ptl-2:          [PASS][1] -> [FAIL][2] ([Intel XE#9115])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/bat-ptl-2/igt@xe_waitfence@reltime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/bat-ptl-2/igt@xe_waitfence@reltime.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-bmg-2:          [ABORT][3] ([Intel XE#8007]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html
    - bat-nvls-1:         [DMESG-WARN][5] ([Intel XE#8762] / [Intel XE#9069]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/bat-nvls-1/igt@core_hotunplug@unbind-rebind.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/bat-nvls-1/igt@core_hotunplug@unbind-rebind.html

  
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8762]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8762
  [Intel XE#9069]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9069
  [Intel XE#9115]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9115


Build changes
-------------

  * Linux: xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6 -> xe-pw-162623v7

  IGT_9098: 9098
  xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6: 4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6
  xe-pw-162623v7: 162623v7

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/index.html

[-- Attachment #2: Type: text/html, Size: 2967 bytes --]

✓ Xe.CI.FULL: success for Add support for Common SDP Transmission Line (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 53900 bytes --]

== Series Details ==

Series: Add support for Common SDP Transmission Line (rev7)
URL   : https://patchwork.freedesktop.org/series/162623/
State : success

== Summary ==

CI Bug Log - changes from xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6_FULL -> xe-pw-162623v7_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-162623v7_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@4-tiled-8bpp-rotate-90:
    - shard-lnl:          NOTRUN -> [ABORT][1] ([Intel XE#4760])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-1/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][2] ([Intel XE#1407])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#7059] / [Intel XE#7085])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#2327])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-1/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#1124]) +7 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][6] ([Intel XE#1124]) +2 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_bw@connected-linear-tiling-3-displays-target-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#7679])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-5/igt@kms_bw@connected-linear-tiling-3-displays-target-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-3840x2160p:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#8365])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_bw@connected-linear-tiling-4-displays-target-3840x2160p.html

  * igt@kms_bw@linear-tiling-1-displays-target-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#367])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_bw@linear-tiling-1-displays-target-3840x2160p.html

  * igt@kms_bw@linear-tiling-3-displays-target-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#367])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_bw@linear-tiling-3-displays-target-2160x1440p.html

  * igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#2887]) +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#3432]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2887]) +13 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_cdclk@mode-transition:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#9204] / [Intel XE#9205]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_cdclk@mode-transition.html

  * igt@kms_cdclk@mode-transition@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#9205]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_cdclk@mode-transition@pipe-b-edp-1.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#306] / [Intel XE#7358])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_color_pipeline@plane-ctm3x4:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#7358])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_chamelium_color_pipeline@plane-ctm3x4.html

  * igt@kms_chamelium_edid@dp-edid-change-during-hibernate:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2252]) +6 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-1/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html

  * igt@kms_chamelium_hpd@hdmi-hpd-fast:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#373]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_chamelium_hpd@hdmi-hpd-fast.html

  * igt@kms_color_pipeline@plane-lut3d-green-only@pipe-b-plane-0:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#6969]) +18 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-5/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-b-plane-0.html

  * igt@kms_color_pipeline@plane-lut3d-green-only@pipe-d-plane-4:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#6969] / [Intel XE#7006]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-5/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-d-plane-4.html

  * igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][22] ([Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-1/igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2.html

  * igt@kms_content_protection@dp-mst-lic-type-0-hdcp14:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#6974])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_content_protection@dp-mst-lic-type-0-hdcp14.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][24] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-1/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html

  * igt@kms_content_protection@uevent:
    - shard-bmg:          NOTRUN -> [FAIL][25] ([Intel XE#6707] / [Intel XE#7439]) +1 other test fail
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2321] / [Intel XE#7355])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-32x10:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2320]) +3 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-10/igt@kms_cursor_crc@cursor-onscreen-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#2321] / [Intel XE#7355])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#309] / [Intel XE#7343]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#2286] / [Intel XE#6035])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#9009])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dsc@dsc-with-bpc-bigjoiner:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#8265]) +2 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_dsc@dsc-with-bpc-bigjoiner.html

  * igt@kms_dsc@dsc-with-output-formats-bigjoiner:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#8265])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_dsc@dsc-with-output-formats-bigjoiner.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#4422] / [Intel XE#7442])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-5/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#8680])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@2x-plain-flip:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#1421]) +2 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-bmg:          [PASS][37] -> [INCOMPLETE][38] ([Intel XE#2049] / [Intel XE#2597] / [Intel XE#8155]) +3 other tests incomplete
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-bmg-2/igt@kms_flip@flip-vs-suspend-interruptible.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-6/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#7178] / [Intel XE#7349])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-rte:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#6312] / [Intel XE#651]) +4 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_frontbuffer_tracking@drrs-1p-rte.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#656] / [Intel XE#7905]) +5 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-shrfb-plflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#6312]) +3 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#4141]) +13 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#7061] / [Intel XE#7356]) +8 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#1469] / [Intel XE#7399])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-rgb565-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2311]) +51 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrshdr-rgb565-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-argb161616f-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#7061]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcpsrhdr-argb161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#7399])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y.html

  * igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#7061]) +4 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-5/igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-spr-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#2313]) +51 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-10/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-shrfb-msflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#7905]) +9 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-1/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-indfb-scaledprimary:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#7865]) +6 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_frontbuffer_tracking@psrhdr-indfb-scaledprimary.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#3374] / [Intel XE#3544])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#1503])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-10/igt@kms_hdr@invalid-hdr.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#7283])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#7283])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#2763] / [Intel XE#6886]) +9 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-10/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-2/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc3co-vpb-simulation@pr-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#8395] / [Intel XE#8396]) +3 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-5/igt@kms_pm_dc@dc3co-vpb-simulation@pr-xrgb8888.html

  * igt@kms_pm_dc@dc3co-vpb-simulation@psr2-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#8396]) +3 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-5/igt@kms_pm_dc@dc3co-vpb-simulation@psr2-xrgb8888.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#3309] / [Intel XE#7368])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#1489]) +5 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-2/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area-big-fb:
    - shard-lnl:          NOTRUN -> [SKIP][65] ([Intel XE#2893] / [Intel XE#7304]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#2387] / [Intel XE#7429])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - shard-bmg:          NOTRUN -> [SKIP][67] ([Intel XE#2234] / [Intel XE#2850]) +12 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-10/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_psr@fbc-psr2-primary-render:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#1406] / [Intel XE#7345])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_psr@fbc-psr2-primary-render.html

  * igt@kms_psr@fbc-psr2-primary-render@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#1406] / [Intel XE#4609] / [Intel XE#7345])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_psr@fbc-psr2-primary-render@edp-1.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#2330] / [Intel XE#5813])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-bmg:          NOTRUN -> [SKIP][72] ([Intel XE#3904] / [Intel XE#7342])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-10/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#1435] / [Intel XE#8695]) +1 other test skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_sharpness_filter@filter-strength:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#6503])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_sharpness_filter@filter-strength.html

  * igt@kms_vrr@lobf:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#2168] / [Intel XE#7444])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-2/igt@kms_vrr@lobf.html

  * igt@kms_vrr@lobf-dc3co:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#8397])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@kms_vrr@lobf-dc3co.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][77] ([Intel XE#1499] / [Intel XE#9271])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-10/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@xe_ccs@vm-bind-fault-mode-decompress:
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#7644])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_ccs@vm-bind-fault-mode-decompress.html

  * igt@xe_create@multigpu-create-massive-size:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#2504] / [Intel XE#7319] / [Intel XE#7350])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@xe_create@multigpu-create-massive-size.html

  * igt@xe_evict@evict-small-external-multi-queue-cm:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#8370]) +2 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-1/igt@xe_evict@evict-small-external-multi-queue-cm.html

  * igt@xe_evict@evict-threads-small-multi-vm:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#6540] / [Intel XE#688]) +3 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_evict@evict-threads-small-multi-vm.html

  * igt@xe_exec_balancer@no-exec-cm-parallel-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][82] ([Intel XE#7482]) +3 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_exec_balancer@no-exec-cm-parallel-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][83] ([Intel XE#2322] / [Intel XE#7372]) +7 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-10/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][84] ([Intel XE#1392]) +1 other test skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-invalidate-imm:
    - shard-bmg:          NOTRUN -> [SKIP][85] ([Intel XE#8374]) +9 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-1/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-invalidate-imm.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-imm:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#8374]) +3 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_exec_fault_mode@once-multi-queue-userptr-imm.html

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-priority:
    - shard-lnl:          NOTRUN -> [SKIP][87] ([Intel XE#8364]) +6 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-priority.html

  * igt@xe_exec_multi_queue@two-queues-priority:
    - shard-bmg:          NOTRUN -> [SKIP][88] ([Intel XE#8364]) +26 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@xe_exec_multi_queue@two-queues-priority.html

  * igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads:
    - shard-lnl:          [PASS][89] -> [FAIL][90] ([Intel XE#7850])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-1/igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-1/igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads.html

  * igt@xe_exec_reset@multi-queue-cancel:
    - shard-bmg:          NOTRUN -> [SKIP][91] ([Intel XE#8369]) +2 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-5/igt@xe_exec_reset@multi-queue-cancel.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-huge:
    - shard-lnl:          [PASS][92] -> [INCOMPLETE][93] ([Intel XE#2594] / [Intel XE#9191])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-7/igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-huge.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-5/igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-huge.html

  * igt@xe_exec_threads@threads-multi-queue-cm-fd-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][94] ([Intel XE#8378]) +11 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-cm-fd-rebind.html

  * igt@xe_exec_threads@threads-multi-queue-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][95] ([Intel XE#8378]) +1 other test skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_exec_threads@threads-multi-queue-userptr-invalidate-race.html

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116]) -> ([PASS][117], [PASS][118], [SKIP][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136], [PASS][137], [PASS][138]) ([Intel XE#378] / [Intel XE#7405])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-1/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-8/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-8/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-4/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-8/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-4/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-1/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-1/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-4/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-2/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-5/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-5/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-2/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-5/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-2/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-7/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-7/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-3/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-7/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-3/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-3/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-3/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-3/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-7/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-1/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-1/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-7/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-3/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-7/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-1/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-4/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-4/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-4/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-5/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-5/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-8/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-8/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-8/igt@xe_module_load@load.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-5/igt@xe_module_load@load.html

  * igt@xe_multigpu_svm@mgpu-coherency-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][139] ([Intel XE#6964])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_multigpu_svm@mgpu-coherency-prefetch.html

  * igt@xe_multigpu_svm@mgpu-latency-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][140] ([Intel XE#6964]) +1 other test skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-2/igt@xe_multigpu_svm@mgpu-latency-prefetch.html

  * igt@xe_page_reclaim@pat-index-xd:
    - shard-bmg:          NOTRUN -> [SKIP][141] ([Intel XE#7793])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@xe_page_reclaim@pat-index-xd.html

  * igt@xe_page_reclaim@pde-vs-pd:
    - shard-lnl:          NOTRUN -> [SKIP][142] ([Intel XE#7793])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_page_reclaim@pde-vs-pd.html

  * igt@xe_pat@pat-sw-hw-reset-compare:
    - shard-bmg:          NOTRUN -> [FAIL][143] ([Intel XE#7695]) +1 other test fail
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-10/igt@xe_pat@pat-sw-hw-reset-compare.html

  * igt@xe_peer2peer@read:
    - shard-bmg:          NOTRUN -> [SKIP][144] ([Intel XE#2427] / [Intel XE#6953] / [Intel XE#7326] / [Intel XE#7353])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@xe_peer2peer@read.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-bmg:          NOTRUN -> [SKIP][145] ([Intel XE#2284] / [Intel XE#7370])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@xe_pm@s2idle-d3cold-basic-exec.html

  * igt@xe_pm@s4-d3cold-basic-exec:
    - shard-lnl:          NOTRUN -> [SKIP][146] ([Intel XE#2284] / [Intel XE#366] / [Intel XE#7370])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_pm@s4-d3cold-basic-exec.html

  * igt@xe_prefetch_fault@l2-prefetch-fault-svm:
    - shard-bmg:          NOTRUN -> [SKIP][147] ([Intel XE#8815])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-2/igt@xe_prefetch_fault@l2-prefetch-fault-svm.html

  * igt@xe_pxp@display-pxp-fb:
    - shard-bmg:          NOTRUN -> [SKIP][148] ([Intel XE#4733] / [Intel XE#7417]) +2 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@xe_pxp@display-pxp-fb.html

  * igt@xe_query@multigpu-query-invalid-cs-cycles:
    - shard-bmg:          NOTRUN -> [SKIP][149] ([Intel XE#944]) +1 other test skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@xe_query@multigpu-query-invalid-cs-cycles.html

  * igt@xe_query@multigpu-query-invalid-extension:
    - shard-lnl:          NOTRUN -> [SKIP][150] ([Intel XE#944])
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_query@multigpu-query-invalid-extension.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-bmg:          NOTRUN -> [FAIL][151] ([Intel XE#6569])
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-3/igt@xe_sriov_flr@flr-vfs-parallel.html

  * igt@xe_vm@overcommit-nonfault-vram-lr-external-nodefer:
    - shard-lnl:          NOTRUN -> [SKIP][152] ([Intel XE#7892])
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-2/igt@xe_vm@overcommit-nonfault-vram-lr-external-nodefer.html

  * igt@xe_wedged@basic-wedged:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][153] ([Intel XE#8963])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-1/igt@xe_wedged@basic-wedged.html

  
#### Possible fixes ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][154] ([Intel XE#301]) -> [PASS][155]
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-lnl:          [FAIL][156] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][157]
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-valid-mode:
    - shard-bmg:          [INCOMPLETE][158] ([Intel XE#9275]) -> [PASS][159] +1 other test pass
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-bmg-3/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-valid-mode.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-valid-mode.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - shard-bmg:          [INCOMPLETE][160] ([Intel XE#2597]) -> [PASS][161] +1 other test pass
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-bmg-6/igt@kms_pipe_crc_basic@suspend-read-crc.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-1/igt@kms_pipe_crc_basic@suspend-read-crc.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][162] ([Intel XE#6321] / [Intel XE#8355]) -> [PASS][163]
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-bmg-9/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-5/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create:
    - shard-bmg:          [ABORT][164] ([Intel XE#8007]) -> [PASS][165] +1 other test pass
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-bmg-8/igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-2/igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create.html

  * igt@xe_pm@s3-vm-bind-userptr:
    - shard-bmg:          [INCOMPLETE][166] ([Intel XE#8175]) -> [PASS][167]
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-bmg-6/igt@xe_pm@s3-vm-bind-userptr.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-10/igt@xe_pm@s3-vm-bind-userptr.html

  
#### Warnings ####

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-lnl:          [SKIP][168] ([Intel XE#309] / [Intel XE#7343] / [Intel XE#7935]) -> [SKIP][169] ([Intel XE#309] / [Intel XE#7343])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][170] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][171] ([Intel XE#301])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][172] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][173] ([Intel XE#2509] / [Intel XE#7437])
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-suspend:
    - shard-bmg:          [SKIP][174] ([Intel XE#1499]) -> [SKIP][175] ([Intel XE#1499] / [Intel XE#9271]) +7 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-bmg-2/igt@kms_vrr@flip-suspend.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-6/igt@kms_vrr@flip-suspend.html

  * igt@kms_vrr@lobf@pipe-a-edp-1:
    - shard-lnl:          [SKIP][176] ([Intel XE#7638]) -> [SKIP][177] ([Intel XE#7638] / [Intel XE#9271])
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-2/igt@kms_vrr@lobf@pipe-a-edp-1.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-7/igt@kms_vrr@lobf@pipe-a-edp-1.html

  * igt@kms_vrr@negative-basic:
    - shard-lnl:          [SKIP][178] ([Intel XE#1499]) -> [SKIP][179] ([Intel XE#1499] / [Intel XE#9271]) +2 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-lnl-1/igt@kms_vrr@negative-basic.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-lnl-4/igt@kms_vrr@negative-basic.html

  * igt@xe_exec_reset@gt-reset-fault-injection:
    - shard-bmg:          [DMESG-WARN][180] ([Intel XE#9130]) -> [ABORT][181] ([Intel XE#9131] / [Intel XE#9145])
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6/shard-bmg-5/igt@xe_exec_reset@gt-reset-fault-injection.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/shard-bmg-2/igt@xe_exec_reset@gt-reset-fault-injection.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1469
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2427
  [Intel XE#2504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2504
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2594
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4760
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6953
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7006]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7006
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7319]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7319
  [Intel XE#7326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7326
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7350
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7353]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7353
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7368]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7368
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7429]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7429
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7439
  [Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
  [Intel XE#7444]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7444
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7638]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7638
  [Intel XE#7644]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7644
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7695
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7850
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7935]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7935
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8155]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8155
  [Intel XE#8175]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8175
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8365]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8365
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8370
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8395
  [Intel XE#8396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8396
  [Intel XE#8397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8397
  [Intel XE#8680]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8680
  [Intel XE#8695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8695
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#8815]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8815
  [Intel XE#8963]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8963
  [Intel XE#9009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9009
  [Intel XE#9130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9130
  [Intel XE#9131]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9131
  [Intel XE#9145]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9145
  [Intel XE#9191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9191
  [Intel XE#9204]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9204
  [Intel XE#9205]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9205
  [Intel XE#9271]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9271
  [Intel XE#9275]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9275
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6 -> xe-pw-162623v7

  IGT_9098: 9098
  xe-5754-4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6: 4fb02d7ad2f3a5c67d0b7a341c452a07b9a9eaf6
  xe-pw-162623v7: 162623v7

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v7/index.html

[-- Attachment #2: Type: text/html, Size: 61018 bytes --]

RE: [PATCH v7 12/14] drm/i915/dp: Account VSC SDP in min guardband

[Kandpal, Suraj]

> Subject: [PATCH v7 12/14] drm/i915/dp: Account VSC SDP in min guardband
> 
> The transmission line for VSC SDP is the same as AS SDP
> (EMP_AS_SDP_TL) when AS SDP is enabled. Otherwise, it uses the second line
> of delayed vblank. For VSC without AS SDP, this requires 2 lines plus 1 setup
> line, so the VRR guardband must be at least 3 lines.
> 
> When both AS SDP and VSC SDP are enabled, the guardband requirement is
> already accounted for during optimized guardband calculation and the final
> guardband validation in compute_config_late(). However, when VSC SDP is
> enabled without AS SDP, the VSC SDP requirement is not checked explicitly.
> 
> Even in the unlikely case where the optimized guardband is clamped to vblank
> length, it cannot fall below 5 lines since such modes are already pruned. Still,
> for completeness, account for VSC SDP and ensure a minimum guardband of 3
> lines.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8c3a324e164e..018dc6303dfe 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7359,6 +7359,8 @@ int intel_dp_get_lines_for_sdp(const struct
> intel_crtc_state *crtc_state, u32 ty
>  		return 8;
>  	case DP_SDP_PPS:
>  		return 7;
> +	case DP_SDP_VSC:
> +		return 3;
>  	case DP_SDP_ADAPTIVE_SYNC:
>  		return crtc_state->vrr.vsync_start + 1;
>  	default:
> @@ -7390,6 +7392,11 @@ int intel_dp_sdp_min_guardband(const struct
> intel_crtc_state *crtc_state,
>  		sdp_guardband = max(sdp_guardband,
>  				    intel_dp_get_lines_for_sdp(crtc_state,
> DP_SDP_ADAPTIVE_SYNC));
> 
> +	if (crtc_state->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
> +		sdp_guardband = max(sdp_guardband,
> +				    intel_dp_get_lines_for_sdp(crtc_state,
> DP_SDP_VSC));
> +
>  	return sdp_guardband;
>  }
> 
> --
> 2.50.1

Re: [PATCH v7 06/14] drm/i915/dip: Store and use AS SDP transmission line from crtc state

[Nautiyal, Ankit K]

On 9/15/2026 10:52 PM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] drm/i915/dip: Spurious state mismatch for EMP_AS_SDP_TL on HDMI fastsets
> --
>
> commit 33aef03ce9383e1676d66a385c5b27a724956776
> Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Subject: drm/i915/dip: Store and use AS SDP transmission line from crtc state
>
> The driver computes and stores the Adaptive Sync SDP transmission line in the
> crtc state and uses it when programming the EMP_AS_SDP_TL register. This
> prepares the ground for supporting programmable transmission lines for
> additional DP SDPs.
>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index 9b3b526e5e55b..dacb4b7588a02 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> [ ... ]
>> @@ -4235,6 +4236,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
>>   	intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
>>   	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
>>   	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
>> +	intel_dip_sdp_transmission_line_get_config(pipe_config);
> [Severity: Medium]
> Will this trigger a spurious state mismatch for EMP_AS_SDP_TL on HDMI fastsets?
>
> If a non-DP (e.g., HDMI) connection inherits a non-zero EMP_AS_SDP_TL value
> from a BIOS handover or a previous DP VRR mode, the hardware state
> (hw_crtc_state) will reflect this non-zero value.
>
> This happens because intel_dip_sdp_transmission_line_get_config()
> unconditionally reads the register here via intel_dip_read_emp_as_sdp_tl()
> without verifying if the encoder is DP:
>
> drivers/gpu/drm/i915/display/intel_dip.c:intel_dip_read_emp_as_sdp_tl() {
>      ...
>      val = intel_de_read(display, EMP_AS_SDP_TL(display, cpu_transcoder));
>      return REG_FIELD_GET(EMP_AS_SDP_DB_TL_MASK, val);
> }
>
> Meanwhile, the software state (sw_crtc_state) expects 0 for HDMI since
> intel_dip_sdp_tl_compute_config_late() is only called for DP.
>
> Because the dip.emp_as_sdp_tl comparison is guarded by if (!fastset) in
> intel_pipe_config_compare(), the discrepancy is ignored during the fastset
> compatibility check, allowing a fastset to proceed.
>
> The fastset skips reprogramming the VRR transcoder timings, leaving the
> hardware register at its stale non-zero value.


intel_vrr_set_transcoder_timings() is set from both modeset and fastset 
path and is written for all platforms that support VRR && have  
EMP_AS_SDP_TL.

intel_vrr_possible() is basically checking flipline that is always set 
for the platforms that have VRR and EMP_AS_SDP_TL, so there is no early 
return from intel_vrr_set_transcoder_timings() either.

Regards,

Ankit

>
> During post-commit hardware verification in verify_crtc_state(),
> intel_pipe_config_compare() is called with fastset = false, which strictly
> checks the field. This causes a drm_WARN backtrace when comparing the expected
> 0 against the stale non-zero hardware value.
>

Re: [PATCH v7 11/14] drm/i915/dip: Enable Common SDP Transmission line

[Nautiyal, Ankit K]

On 9/15/2026 10:58 PM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] drm/i915/dip: Missing CMN_SDP_TL programming for DP MST slave transcoders
> --
>
> commit de3a67cbeba4a6e70cc767d1dce1950454f58dfa
> Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> drm/i915/dip: Enable Common SDP Transmission line
>
> This commit enables programming of the common SDP transmission line on
> supported platforms. It computes and programs the base transmission line
> and stagger values during modeset. It also disables the feature on pipe
> disable.
>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index dacb4b7588a02..3cdb06e81130b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -2737,6 +2737,8 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>>   	/* 6.o Configure and enable FEC if needed */
>>   	intel_ddi_enable_fec(encoder, crtc_state);
>>   
>> +	intel_dip_cmn_sdp_transmission_line_enable(crtc_state);
>> +
> [Severity: Medium]
> Will placing this transcoder-specific initialization in mtl_ddi_pre_enable_dp()
> cause it to be skipped for subsequent MST streams?
>
> In DP MST configurations, mst_stream_pre_enable() invokes the primary encoder's
> pre_enable hook (mtl_ddi_pre_enable_dp()) solely for the first active MST
> stream.
>
> Because intel_dip_cmn_sdp_transmission_line_enable() is called here, it
> appears it will be skipped for all subsequent streams. This would leave the
> CMN_SDP_TL registers uninitialized for slave transcoders, potentially causing
> broken or mistimed SDP transmission on secondary MST monitors.
>
>>   	/* 7.a 128b/132b SST. */
>>   	if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
>>   		/* VCPID 1, start slot 0 for 128b/132b, tu slots */
> [ ... ]
>> @@ -3124,6 +3126,7 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder,
>>   			     DP_TP_CTL_ENABLE, 0);
>>   	}
>>   
>> +	intel_dip_cmn_sdp_transmission_line_disable(crtc_state);
> [Severity: Medium]
> Does placing this disable routine in intel_ddi_buf_disable() prevent it from
> executing for slave transcoders during MST teardown?
>
> Similar to the enable path, intel_ddi_buf_disable() is only called for the
> last active stream during teardown, which means the CMN_SDP_TL disable routine
> would be skipped for slave streams.


For both comments. MST + VRR is not yet supported.

Regards,

Ankit

>
>>   	intel_ddi_disable_fec(encoder, crtc_state);
>>   
>>   	if (DISPLAY_VER(display) < 14)

Re: [PATCH v7 00/14] Add support for Common SDP Transmission Line

[Nautiyal, Ankit K]

On 9/15/2026 10:16 PM, Ankit Nautiyal wrote:
> Xe3p_lpd introduces new register bits to program a common SDP
> Transmission line that will be used by the Hardware to position the
> SDPs. Along with this, another new register is also added to stagger
> the different SDPs.
>
> This series adds support for programming the Common SDP Transmission Line
> (CMN_SDP_TL) and its stagger control registers.
>
> Rev2:
>   - Add tracking for AS SDP Transmission line first. Instead of directly
>     programming it in the register, compute the state during
>     compute_config_late() and write the value from crtc_state.
>     Readout from the register through a vrr helper, since the register is
>     defined in context of VRR and will be used for both DP and HDMI VRR
>     packets.
>   - Add support to track other SDP transmission lines, instead of stagger
>     values.
>   - Compute the transmission lines in compute_config_late path and add
>     readout.
>   - Always write the Common SDP Transmission line and other stagger
>     values, whether the packets are sent or not.
>   - Dump SDP transmission lines in crtc_state.
>
> Rev3:
>   - Introduce new files for handling the Data Island Packets (DIPs)
>     programming in one place. (Ville)
>   - Extract the Transmission Line programming for
>     HDMI Extended Metadata Packet (EMP) and Adaptive Sync SDP (AS SDP)
>     i.e. EMP_AS_SDP_TL in the new file.
>   - Add programming for Common Base SDP Transmission lines and other
>     stagger offsets in the new file.
>   - Add a #TODO to extract other helpers that deal with Data Island Packets
>     and VIDEO_DIP registers.
>   - Place the HAS_* Macros related to DIP in the intel_dip.h file
>     instead of intel_display_devices.h (Jani)
>   - Make function names more descriptive and avoid overuse of multiple
>     acronyms. (Jani)
>
> Note:
>   - Though I have fixed the naming as suggested in most places, I
>     have retained HAS_EMP_AS_SDP_TL for the following reasons:
>     1) Lack of an apt name that avoids the acronym for
>        'Extended Metadata Packet Adaptive Sync Secondary Packet Transmission
>        Line'.
>     2) Keeping this name makes it easier to find and map with the exact name
>        for such a complex register name.
>
>     However, I am open to suggestions for a better name.
>
> Rev4:
>   - Drop the patch to check for DP encoder before writing EMP_AS_SDP_TL
>     register. Instead reset the register to 0 for non DP encoder case.
>
> Rev5:
>   - Rebase
>   - Address review comments from Suraj:
>   - Drop some redundant checks, and fix few commit messages.
>
> Rev6:
>   - Move the new struct in intel_display_types.h from intel_dip.h (Jani)
>   - Check for CMN_SDP_TL restriction and Warn if not followed. (Suraj)
>   - Use HAS_CMN_SDP_TL() instead of checking if cmn_sdp_tl is set or not.
>     (Sashiko)
>   - Make sure that the guardband is sufficient as per CMN_SDP_TL while
>     optiminzing the guardband.
>
> Rev7:
>   - Account for VSC SDP's own minimum guardband requirement in
>     intel_dp_sdp_min_guardband(), for completeness. (Sashiko)
>   - Wrap two long line macro definitions in intel_dip_regs.h.
>
> Ankit Nautiyal (13):
>    drm/i915/dip: Add new file to handle Data Island Packet hardware
>    drm/i915/vrr: Use the helper to write EMP_AS_SDP_TL register
>    drm/i915/intel_dip: Add check for DP encoder
>    drm/i915/dip: Add helper to get AS SDP Transmission Line
>    drm/i915/display: Add crtc state for DIP transmission lines
>    drm/i915/dip: Store and use AS SDP transmission line from crtc state
>    drm/i915/dip: Add HAS_COMMON_SDP_TL macro
>    drm/i915/dip: Store SDP transmission lines in crtc_state
>    drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission
>      line
>    drm/i915/dip: Enable Common SDP Transmission line
>    drm/i915/dp: Account VSC SDP in min guardband
>    drm/i915/dp: Adjust SDP guardband requirement for CMN_SDP_TL
>    drm/i915/display: Dump DIP Transmission lines
>
> Arun R Murthy (1):
>    drm/i915/dip_regs: Add register definitions for common SDP
>      Transmission Line

Thanks for the review comments, and suggestions. Pushed to drm-intel-next.

intel_dip.c was introduced here but only covers the transmission-line 
handling. Two follow-ups remain:

- Extract the remaining low-level DIP buffer/infoframe code out of 
intel_hdmi.c into intel_dip.c.
- Introduce a DIP type enum so HDMI packet types and DP SDP types aren't 
mixed in the same namespace in hsw_infoframe_enable()

I'll try to get to that next.


Thanks & Regards,

Ankit

>
>   drivers/gpu/drm/i915/Makefile                 |   1 +
>   .../drm/i915/display/intel_crtc_state_dump.c  |   9 +
>   drivers/gpu/drm/i915/display/intel_ddi.c      |   5 +
>   drivers/gpu/drm/i915/display/intel_dip.c      | 215 ++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_dip.h      |  53 +++++
>   drivers/gpu/drm/i915/display/intel_dip_regs.h |  38 ++++
>   drivers/gpu/drm/i915/display/intel_display.c  |   6 +
>   .../drm/i915/display/intel_display_types.h    |  16 ++
>   drivers/gpu/drm/i915/display/intel_dp.c       |  62 ++++-
>   drivers/gpu/drm/i915/display/intel_vrr.c      |  14 +-
>   drivers/gpu/drm/i915/display/intel_vrr_regs.h |   6 -
>   drivers/gpu/drm/xe/Makefile                   |   1 +
>   12 files changed, 407 insertions(+), 19 deletions(-)
>   create mode 100644 drivers/gpu/drm/i915/display/intel_dip.c
>   create mode 100644 drivers/gpu/drm/i915/display/intel_dip.h
>   create mode 100644 drivers/gpu/drm/i915/display/intel_dip_regs.h
>