[PATCH v2 00/13] drm/i915/display: Add DC3CO support

[PATCH v2 00/13] drm/i915/display: Add DC3CO support

[Dibin Moolakadan Subrahmanian]

This series adds initial DC3CO support for display version 35+ and adds
debugfs visibility into DC3CO count/residency.

The series also includes required PSR/ALPM updates for DC3CO enablement.

This series is based on the CMTG enablement series currently under
review:
https://patchwork.freedesktop.org/series/157664/

DC3CO is not enabled by this series since power_domains->allowed_dc_mask
is not updated to include DC3CO.

TODO:
- CMTG restore on DC6 exit
- CMTG HWGB programming for DC3CO latencies
- Enable DC3CO in power_domains->allowed_dc_mask

Changes in v2:
- Move dc3co state from intel_atomic_state to display->power
- Squash cleanup and related patches to reduce series from 19 to 13
  patches

Dibin Moolakadan Subrahmanian (13):
  drm/i915/display: Remove TGL DC3CO support
  drm/i915/display: Switch DC3Co enable from standalone bit to DC level
    encoding
  drm/i915/display: Use FIELD_PREP() for DC state enable bits
  drm/i915/display: Add DC3CO DC_STATE enable/disable support
  drm/i915/display: Add DC3CO support check and validate target DC state
  drm/i915/display: Add HAS_DC3CO() macro
  drm/i915/display: Add DC3CO eligibility computation
  drm/i915/display: Store DC3CO eligibility in PSR state
  drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO
  drm/i915/display: Enable DC3CO idle protocol in ALPM
  drm/i915/display: PSR Add delayed work to exit DC3CO
  drm/i915/display: Add helper to enable DC counter
  drm/i915/display: Add DC3CO count and residency in dmc debugfs

 drivers/gpu/drm/i915/display/intel_alpm.c     |   6 +
 drivers/gpu/drm/i915/display/intel_display.c  |  92 ++++++-
 drivers/gpu/drm/i915/display/intel_display.h  |   1 -
 .../gpu/drm/i915/display/intel_display_core.h |   3 +-
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_power.c    |  50 +++-
 .../drm/i915/display/intel_display_power.h    |  23 ++
 .../i915/display/intel_display_power_well.c   |  36 ++-
 .../i915/display/intel_display_power_well.h   |   1 +
 .../gpu/drm/i915/display/intel_display_regs.h |  14 +-
 .../drm/i915/display/intel_display_types.h    |   7 +-
 drivers/gpu/drm/i915/display/intel_dmc.c      |  15 +-
 drivers/gpu/drm/i915/display/intel_dmc_regs.h |   2 +
 drivers/gpu/drm/i915/display/intel_dmc_wl.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 230 +++++-------------
 drivers/gpu/drm/i915/display/intel_psr_regs.h |   1 +
 16 files changed, 266 insertions(+), 218 deletions(-)

-- 
2.43.0

[PATCH v2 01/13] drm/i915/display: Remove TGL DC3CO support

[Dibin Moolakadan Subrahmanian]

Remove all Tiger Lake DC3CO-related functions from intel_psr.c and
intel_display_power_well.c, as the feature is not enabled and not used.
Also remove the TGL/DG1 DC3CO count debugfs entry from intel_dmc.c,
as DC3CO is not active on those platforms. A new debugfs entry for
Xe3LP will be added in a subsequent patch.

Remove the unused dc3co_exitline field from struct intel_psr and
struct intel_crtc_state, along with the corresponding EXITLINE register
read in intel_psr_get_config().

Changes in v2:
- Squash "Remove unused PSR dc3co_exitline field" and
  "Remove unused dc3co_exitline from crtc_state" into this patch

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 .../i915/display/intel_display_power_well.c   |  25 ---
 .../drm/i915/display/intel_display_types.h    |   3 -
 drivers/gpu/drm/i915/display/intel_dmc.c      |   6 -
 drivers/gpu/drm/i915/display/intel_psr.c      | 171 ------------------
 4 files changed, 205 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 6fbfd46461b0..a7c5290edec1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -866,23 +866,6 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 	power_domains->dc_state = val & mask;
 }
 
-static void tgl_enable_dc3co(struct intel_display *display)
-{
-	drm_dbg_kms(display->drm, "Enabling DC3CO\n");
-	gen9_set_dc_state(display, DC_STATE_EN_DC3CO);
-}
-
-static void tgl_disable_dc3co(struct intel_display *display)
-{
-	drm_dbg_kms(display->drm, "Disabling DC3CO\n");
-	intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0);
-	gen9_set_dc_state(display, DC_STATE_DISABLE);
-	/*
-	 * Delay of 200us DC3CO Exit time B.Spec 49196
-	 */
-	usleep_range(200, 210);
-}
-
 static void assert_can_enable_dc5(struct intel_display *display)
 {
 	enum i915_power_well_id high_pg;
@@ -1061,11 +1044,6 @@ void gen9_disable_dc_states(struct intel_display *display)
 	struct intel_cdclk_config cdclk_config = {};
 	u32 old_state = power_domains->dc_state;
 
-	if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) {
-		tgl_disable_dc3co(display);
-		return;
-	}
-
 	if (HAS_DISPLAY(display)) {
 		intel_dmc_wl_get_noreg(display);
 		gen9_set_dc_state(display, DC_STATE_DISABLE);
@@ -1114,9 +1092,6 @@ static void gen9_dc_off_power_well_disable(struct intel_display *display,
 		return;
 
 	switch (power_domains->target_dc_state) {
-	case DC_STATE_EN_DC3CO:
-		tgl_enable_dc3co(display);
-		break;
 	case DC_STATE_EN_UPTO_DC6:
 		skl_enable_dc6(display);
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c81916761850..fc283cc429ec 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1183,7 +1183,6 @@ struct intel_crtc_state {
 	bool pkg_c_latency_used;
 	/* Only used for state verification. */
 	enum intel_panel_replay_dsc_support panel_replay_dsc_support;
-	u32 dc3co_exitline;
 	u16 su_y_granularity;
 	u8 active_non_psr_pipes;
 	u8 entry_setup_frames;
@@ -1775,9 +1774,7 @@ struct intel_psr {
 	bool source_panel_replay_support;
 	bool sink_panel_replay_support;
 	bool panel_replay_enabled;
-	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
-	struct delayed_work dc3co_work;
 	u8 entry_setup_frames;
 
 	u8 io_wake_lines;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 2104164e136e..8b5840116f64 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1647,19 +1647,13 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 		   DMC_VERSION_MINOR(dmc->version));
 
 	if (DISPLAY_VER(display) >= 12) {
-		i915_reg_t dc3co_reg;
-
 		if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {
-			dc3co_reg = DG1_DMC_DEBUG3;
 			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
 		} else {
-			dc3co_reg = TGL_DMC_DEBUG3;
 			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
 			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
 		}
 
-		seq_printf(m, "DC3CO count: %d\n",
-			   intel_de_read(display, dc3co_reg));
 	} else {
 		dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT :
 			SKL_DMC_DC3_DC5_COUNT;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 63c19958a9e3..34e4a1ad609e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -87,22 +87,6 @@
  * issues the self-refresh re-enable code is done from a work queue, which
  * must be correctly synchronized/cancelled when shutting down the pipe."
  *
- * DC3CO (DC3 clock off)
- *
- * On top of PSR2, GEN12 adds a intermediate power savings state that turns
- * clock off automatically during PSR2 idle state.
- * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep
- * entry/exit allows the HW to enter a low-power state even when page flipping
- * periodically (for instance a 30fps video playback scenario).
- *
- * Every time a flips occurs PSR2 will get out of deep sleep state(if it was),
- * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6
- * frames, if no other flip occurs and the function above is executed, DC3CO is
- * disabled and PSR2 is configured to enter deep sleep, resetting again in case
- * of another flip.
- * Front buffer modifications do not trigger DC3CO activation on purpose as it
- * would bring a lot of complexity and most of the moderns systems will only
- * use page flips.
  */
 
 /*
@@ -1207,108 +1191,6 @@ static void psr2_program_idle_frames(struct intel_dp *intel_dp,
 		     EDP_PSR2_IDLE_FRAMES(idle_frames));
 }
 
-static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-
-	psr2_program_idle_frames(intel_dp, 0);
-	intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO);
-}
-
-static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-
-	intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
-	psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
-}
-
-static void tgl_dc3co_disable_work(struct work_struct *work)
-{
-	struct intel_dp *intel_dp =
-		container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
-
-	mutex_lock(&intel_dp->psr.lock);
-	/* If delayed work is pending, it is not idle */
-	if (delayed_work_pending(&intel_dp->psr.dc3co_work))
-		goto unlock;
-
-	tgl_psr2_disable_dc3co(intel_dp);
-unlock:
-	mutex_unlock(&intel_dp->psr.lock);
-}
-
-static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
-{
-	if (!intel_dp->psr.dc3co_exitline)
-		return;
-
-	cancel_delayed_work(&intel_dp->psr.dc3co_work);
-	/* Before PSR2 exit disallow dc3co*/
-	tgl_psr2_disable_dc3co(intel_dp);
-}
-
-static bool
-dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,
-			      struct intel_crtc_state *crtc_state)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
-	enum port port = dig_port->base.port;
-
-	if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
-		return pipe <= PIPE_B && port <= PORT_B;
-	else
-		return pipe == PIPE_A && port == PORT_A;
-}
-
-static void
-tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
-				  struct intel_crtc_state *crtc_state)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-	const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
-	struct i915_power_domains *power_domains = &display->power.domains;
-	u32 exit_scanlines;
-
-	/*
-	 * FIXME: Due to the changed sequence of activating/deactivating DC3CO,
-	 * disable DC3CO until the changed dc3co activating/deactivating sequence
-	 * is applied. B.Specs:49196
-	 */
-	return;
-
-	/*
-	 * DMC's DC3CO exit mechanism has an issue with Selective Fecth
-	 * TODO: when the issue is addressed, this restriction should be removed.
-	 */
-	if (crtc_state->enable_psr2_sel_fetch)
-		return;
-
-	if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO))
-		return;
-
-	if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
-		return;
-
-	/* Wa_16011303918:adl-p */
-	if (intel_display_wa(display, INTEL_DISPLAY_WA_16011303918))
-		return;
-
-	/*
-	 * DC3CO Exit time 200us B.Spec 49196
-	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
-	 */
-	exit_scanlines =
-		intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
-
-	if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay))
-		return;
-
-	crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
-}
-
 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 					      struct intel_crtc_state *crtc_state)
 {
@@ -1651,8 +1533,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
-
 	return true;
 }
 
@@ -1967,12 +1847,6 @@ void intel_psr_get_config(struct intel_encoder *encoder,
 	}
 
 	pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled;
-
-	if (DISPLAY_VER(display) >= 12) {
-		val = intel_de_read(display,
-				    TRANS_EXITLINE(display, cpu_transcoder));
-		pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val);
-	}
 unlock:
 	mutex_unlock(&intel_dp->psr.lock);
 }
@@ -2100,16 +1974,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 
 	psr_irq_control(intel_dp);
 
-	/*
-	 * TODO: if future platforms supports DC3CO in more than one
-	 * transcoder, EXITLINE will need to be unset when disabling PSR
-	 */
-	if (intel_dp->psr.dc3co_exitline)
-		intel_de_rmw(display,
-			     TRANS_EXITLINE(display, cpu_transcoder),
-			     EXITLINE_MASK,
-			     intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE);
-
 	if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display))
 		intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
 			     intel_dp->psr.psr2_sel_fetch_enabled ?
@@ -2209,7 +2073,6 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 	/* DC5/DC6 requires at least 6 idle frames */
 	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
 	intel_dp->psr.dc3co_exit_delay = val;
-	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
 	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
 	intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et;
 	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
@@ -2288,8 +2151,6 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
 		intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),
 			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
 	} else if (intel_dp->psr.sel_update_enabled) {
-		tgl_disallow_dc3co_on_psr2_exit(intel_dp);
-
 		val = intel_de_rmw(display,
 				   EDP_PSR2_CTL(display, cpu_transcoder),
 				   EDP_PSR2_ENABLE, 0);
@@ -2431,7 +2292,6 @@ void intel_psr_disable(struct intel_dp *intel_dp,
 
 	mutex_unlock(&intel_dp->psr.lock);
 	cancel_work_sync(&intel_dp->psr.work);
-	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
 }
 
 /**
@@ -2462,7 +2322,6 @@ void intel_psr_pause(struct intel_dp *intel_dp)
 	mutex_unlock(&psr->lock);
 
 	cancel_work_sync(&psr->work);
-	cancel_delayed_work_sync(&psr->dc3co_work);
 }
 
 /**
@@ -3608,34 +3467,6 @@ void intel_psr_invalidate(struct intel_display *display,
 		mutex_unlock(&intel_dp->psr.lock);
 	}
 }
-/*
- * When we will be completely rely on PSR2 S/W tracking in future,
- * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
- * event also therefore tgl_dc3co_flush_locked() require to be changed
- * accordingly in future.
- */
-static void
-tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
-		       enum fb_op_origin origin)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-
-	if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled ||
-	    !intel_dp->psr.active)
-		return;
-
-	/*
-	 * At every frontbuffer flush flip event modified delay of delayed work,
-	 * when delayed work schedules that means display has been idle.
-	 */
-	if (!(frontbuffer_bits &
-	    INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
-		return;
-
-	tgl_psr2_enable_dc3co(intel_dp);
-	mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,
-			 intel_dp->psr.dc3co_exit_delay);
-}
 
 static void _psr_flush_handle(struct intel_dp *intel_dp)
 {
@@ -3722,7 +3553,6 @@ void intel_psr_flush(struct intel_display *display,
 		if (origin == ORIGIN_FLIP ||
 		    (origin == ORIGIN_CURSOR_UPDATE &&
 		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
-			tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);
 			goto unlock;
 		}
 
@@ -3781,7 +3611,6 @@ void intel_psr_init(struct intel_dp *intel_dp)
 		intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
 
 	INIT_WORK(&intel_dp->psr.work, intel_psr_work);
-	INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
 	mutex_init(&intel_dp->psr.lock);
 }
 
-- 
2.43.0

[PATCH v2 02/13] drm/i915/display: Switch DC3Co enable from standalone bit to DC level encoding

[Dibin Moolakadan Subrahmanian]

On platforms prior to xe3, DC3CO was controlled via a standalone enable
bit. Starting with xe3, DC3CO is encoded as part of the existing
DC_STATE_EN_UPTO_DC* field.

No functional change, as DC3CO is not enabled on platforms prior to xe3.

Changes in v2:
- Update commit header (Uma Shankar)

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c      | 6 +++---
 drivers/gpu/drm/i915/display/intel_display_power_well.c | 4 ++--
 drivers/gpu/drm/i915/display/intel_display_regs.h       | 2 +-
 drivers/gpu/drm/i915/display/intel_dmc_wl.c             | 2 +-
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 80ecf373fb19..77c32492caa1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -267,7 +267,7 @@ sanitize_target_dc_state(struct intel_display *display,
 	static const u32 states[] = {
 		DC_STATE_EN_UPTO_DC6,
 		DC_STATE_EN_UPTO_DC5,
-		DC_STATE_EN_DC3CO,
+		DC_STATE_EN_UPTO_DC3CO,
 		DC_STATE_DISABLE,
 	};
 	int i;
@@ -999,10 +999,10 @@ static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)
 
 	switch (requested_dc) {
 	case 4:
-		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
+		mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6;
 		break;
 	case 3:
-		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
+		mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC5;
 		break;
 	case 2:
 		mask |= DC_STATE_EN_UPTO_DC6;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index a7c5290edec1..b5e6437c3d8d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -772,7 +772,7 @@ static u32 gen9_dc_mask(struct intel_display *display)
 	mask = DC_STATE_EN_UPTO_DC5;
 
 	if (DISPLAY_VER(display) >= 12)
-		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+		mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6
 					  | DC_STATE_EN_DC9;
 	else if (DISPLAY_VER(display) == 11)
 		mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
@@ -1022,7 +1022,7 @@ static void bxt_verify_dpio_phy_power_wells(struct intel_display *display)
 static bool gen9_dc_off_power_well_enabled(struct intel_display *display,
 					   struct i915_power_well *power_well)
 {
-	return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+	return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC3CO) == 0 &&
 		(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index dada8dc27ea4..2ad211da9157 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3039,13 +3039,13 @@ enum skl_power_gate {
 /* GEN9 DC */
 #define DC_STATE_EN			_MMIO(0x45504)
 #define  DC_STATE_DISABLE		0
-#define  DC_STATE_EN_DC3CO		REG_BIT(30)
 #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
 #define  HOLD_PHY_CLKREQ_PG1_LATCH	REG_BIT(21)
 #define  HOLD_PHY_PG1_LATCH		REG_BIT(20)
 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
 #define  DC_STATE_EN_DC9		(1 << 3)
 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
+#define  DC_STATE_EN_UPTO_DC3CO		(3 << 0)
 #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
 
 #define  DC_STATE_DEBUG                  _MMIO(0x45520)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index ddf1a1f1ebc3..13192531cd49 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -260,7 +260,7 @@ static bool intel_dmc_wl_check_range(struct intel_display *display,
 	 * the DMC and requires a DC exit for proper access.
 	 */
 	switch (dc_state) {
-	case DC_STATE_EN_DC3CO:
+	case DC_STATE_EN_UPTO_DC3CO:
 		ranges = xe3lpd_dc3co_dmc_ranges;
 		break;
 	case DC_STATE_EN_UPTO_DC5:
-- 
2.43.0

[PATCH v2 03/13] drm/i915/display: Use FIELD_PREP() for DC state enable bits

[Dibin Moolakadan Subrahmanian]

Replace open-coded shifts with REG_GENMASK() and REG_FIELD_PREP()
for the DC state enable field.

Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_regs.h | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 2ad211da9157..fa56cc506e3f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3042,11 +3042,12 @@ enum skl_power_gate {
 #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
 #define  HOLD_PHY_CLKREQ_PG1_LATCH	REG_BIT(21)
 #define  HOLD_PHY_PG1_LATCH		REG_BIT(20)
-#define  DC_STATE_EN_UPTO_DC5		(1 << 0)
 #define  DC_STATE_EN_DC9		(1 << 3)
-#define  DC_STATE_EN_UPTO_DC6		(2 << 0)
-#define  DC_STATE_EN_UPTO_DC3CO		(3 << 0)
-#define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
+#define  DC_STATE_EN_UPTO_DC5_DC6_MASK   REG_GENMASK(1, 0)
+#define  DC_STATE_EN_DISABLE		REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 0)
+#define  DC_STATE_EN_UPTO_DC5		REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 1)
+#define  DC_STATE_EN_UPTO_DC6		REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 2)
+#define  DC_STATE_EN_UPTO_DC3CO	REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 3)
 
 #define  DC_STATE_DEBUG                  _MMIO(0x45520)
 #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
-- 
2.43.0

[PATCH v2 04/13] drm/i915/display: Add DC3CO DC_STATE enable/disable support

[Dibin Moolakadan Subrahmanian]

Add DC3CO handling to the dc_off power well sequencing and disable the
DMC wakelock when exiting DC3CO.

BSpec: 75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 .../drm/i915/display/intel_display_power_well.c  | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index b5e6437c3d8d..5e002d459e95 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -866,6 +866,13 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 	power_domains->dc_state = val & mask;
 }
 
+static void xe3lpd_enable_dc3co(struct intel_display *display)
+{
+	drm_dbg_kms(display->drm, "Enabling DC3CO\n");
+	intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC3CO);
+	gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC3CO);
+}
+
 static void assert_can_enable_dc5(struct intel_display *display)
 {
 	enum i915_power_well_id high_pg;
@@ -1054,9 +1061,13 @@ void gen9_disable_dc_states(struct intel_display *display)
 	}
 
 	if (old_state == DC_STATE_EN_UPTO_DC5 ||
-	    old_state == DC_STATE_EN_UPTO_DC6)
+	    old_state == DC_STATE_EN_UPTO_DC6 ||
+	    old_state == DC_STATE_EN_UPTO_DC3CO)
 		intel_dmc_wl_disable(display);
 
+	if (old_state == DC_STATE_EN_UPTO_DC3CO)
+		return;
+
 	intel_cdclk_get_cdclk(display, &cdclk_config);
 	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
 	drm_WARN_ON(display->drm,
@@ -1092,6 +1103,9 @@ static void gen9_dc_off_power_well_disable(struct intel_display *display,
 		return;
 
 	switch (power_domains->target_dc_state) {
+	case DC_STATE_EN_UPTO_DC3CO:
+		xe3lpd_enable_dc3co(display);
+		break;
 	case DC_STATE_EN_UPTO_DC6:
 		skl_enable_dc6(display);
 		break;
-- 
2.43.0

[PATCH v2 05/13] drm/i915/display: Add DC3CO support check and validate target DC state

[Dibin Moolakadan Subrahmanian]

Validate the requested target DC state against allowed_dc_mask in
intel_display_power_set_target_dc_state() to avoid programming
unsupported DC states.

Also add intel_display_power_dc3co_supported() helper to query DC3CO
support from allowed_dc_mask.

Changes in v2:
- Squash "Add helper to check DC3CO support" patch into this patch

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 14 ++++++++++++++
 drivers/gpu/drm/i915/display/intel_display_power.h |  1 +
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 77c32492caa1..f626803bbd88 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -302,6 +302,13 @@ void intel_display_power_set_target_dc_state(struct intel_display *display,
 	struct i915_power_domains *power_domains = &display->power.domains;
 
 	mutex_lock(&power_domains->lock);
+
+	if ((state & power_domains->allowed_dc_mask) != state) {
+		drm_dbg_kms(display->drm,
+			    "Rejecting DC state 0x%x (allowed mask 0x%x)\n",
+			     state, power_domains->allowed_dc_mask);
+		goto unlock;
+	}
 	power_well = lookup_power_well(display, SKL_DISP_DC_OFF);
 
 	if (drm_WARN_ON(display->drm, !power_well))
@@ -358,6 +365,13 @@ u32 intel_display_power_get_current_dc_state(struct intel_display *display)
 	return current_dc_state;
 }
 
+bool intel_display_power_dc3co_supported(struct intel_display *display)
+{
+	struct i915_power_domains *power_domains = &display->power.domains;
+
+	return (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) == DC_STATE_EN_UPTO_DC3CO;
+}
+
 static void __async_put_domains_mask(struct i915_power_domains *power_domains,
 				     struct intel_power_domain_mask *mask)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index d616d5d09cbe..05880e9da89f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -186,6 +186,7 @@ void intel_display_power_resume(struct intel_display *display);
 void intel_display_power_set_target_dc_state(struct intel_display *display,
 					     u32 state);
 u32 intel_display_power_get_current_dc_state(struct intel_display *display);
+bool intel_display_power_dc3co_supported(struct intel_display *display);
 
 bool intel_display_power_is_enabled(struct intel_display *display,
 				    enum intel_display_power_domain domain);
-- 
2.43.0

[PATCH v2 06/13] drm/i915/display: Add HAS_DC3CO() macro

[Dibin Moolakadan Subrahmanian]

Add HAS_DC3CO() to identify platforms supporting DC3CO.
DC3CO is supported from display version 35 onwards.

BSpec: 75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 074e3ba8fb77..7fd994d92ba9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -159,6 +159,7 @@ struct intel_display_platforms {
 #define HAS_CUR_FBC(__display)		(!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13))
 #define HAS_D12_PLANE_MINIMIZATION(__display)	((__display)->platform.rocketlake || (__display)->platform.alderlake_s)
 #define HAS_DBUF_OVERLAP_DETECTION(__display)	(DISPLAY_RUNTIME_INFO(__display)->has_dbuf_overlap_detection)
+#define HAS_DC3CO(__display)		(DISPLAY_VER(__display) >= 35)
 #define HAS_DDI(__display)		(DISPLAY_INFO(__display)->has_ddi)
 #define HAS_DISPLAY(__display)		(DISPLAY_RUNTIME_INFO(__display)->pipe_mask != 0)
 #define HAS_DMC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dmc)
-- 
2.43.0

[PATCH v2 07/13] drm/i915/display: Add DC3CO eligibility computation

[Dibin Moolakadan Subrahmanian]

Compute DC3CO eligibility during atomic_check based on
pipe/port constraints and runtime triggers and store
result in display->power.dc3co.

When DC3CO is allowed, request DC_STATE_EN_UPTO_DC3CO and
reduce the DC entry delay. Otherwise, retain the existing
delay and set default DC_STATE_EN_UPTO_DC6 .

Changes in v2:
- Move dc3co state from intel_atomic_state to display->power (Uma Shankar)
- Use #define bitmasks instead of enum for DC3CO triggers (Jani Nikula)

BSpec: 75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 92 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_display.h  |  1 -
 .../gpu/drm/i915/display/intel_display_core.h |  3 +-
 .../drm/i915/display/intel_display_power.c    | 30 ++++++
 .../drm/i915/display/intel_display_power.h    | 22 +++++
 5 files changed, 141 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 674a4ece6d0f..de493d04a622 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5870,6 +5870,69 @@ static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
 	return false;
 }
 
+static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
+					     const struct intel_crtc_state *crtc_state)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+	enum port port = dig_port->base.port;
+	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
+
+	return num_pipes == 1 && pipe <= PIPE_B && port <= PORT_B;
+}
+
+static void intel_dc3co_compute_state(struct intel_atomic_state *state)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *crtc_state;
+	struct intel_encoder *encoder;
+	struct intel_dp *intel_dp;
+	int active_pipes = 0;
+	u32 trigger = DC3CO_TRIGGER_NONE;
+
+	if (!HAS_DC3CO(display))
+		return;
+
+	for_each_intel_crtc(display->drm, crtc) {
+		trigger = DC3CO_TRIGGER_NONE;
+		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+		if (!crtc_state)
+			crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
+
+		if (!crtc_state || !crtc_state->hw.active)
+			continue;
+
+		active_pipes++;
+
+		if (active_pipes > 1)
+			goto done;
+
+		for_each_intel_encoder_mask(display->drm, encoder,
+					    crtc_state->uapi.encoder_mask) {
+			if (encoder->type != INTEL_OUTPUT_EDP)
+				goto done;
+
+			intel_dp = enc_to_intel_dp(encoder);
+
+			if (!intel_dc3co_port_pipe_compatible(intel_dp, crtc_state))
+				goto done;
+		}
+
+		if (crtc_state->has_lobf)
+			trigger |= DC3CO_TRIGGER_LOBF;
+		if (crtc_state->has_panel_replay)
+			trigger |= DC3CO_TRIGGER_PANEL_REPLAY;
+		if (crtc_state->has_sel_update)
+			trigger |= DC3CO_TRIGGER_PSR2;
+	}
+
+done:
+	intel_display_power_dc3co_update(display, !!trigger, trigger);
+	drm_dbg_kms(display->drm, "DC3CO allowed=%d trigger=0x%x\n",
+		    !!trigger, trigger);
+}
+
 static int intel_atomic_check_joiner(struct intel_atomic_state *state,
 				     struct intel_crtc *primary_crtc)
 {
@@ -6544,6 +6607,7 @@ int intel_atomic_check(struct drm_device *dev,
 	if (ret)
 		goto fail;
 
+	intel_dc3co_compute_state(state);
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
 		intel_color_assert_luts(new_crtc_state);
@@ -7415,6 +7479,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
 	struct ref_tracker *wakeref = NULL;
 	int i;
+	int power_async_delay;
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
 		intel_atomic_dsb_prepare(state, crtc);
@@ -7621,11 +7686,28 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		 */
 		intel_uncore_arm_unclaimed_mmio_detection(uncore);
 	}
-	/*
-	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
-	 * toggling overhead at and above 60 FPS.
-	 */
-	intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17);
+
+	if (intel_display_power_dc3co_allowed(display) &&
+	    intel_display_power_dc3co_supported(display)) {
+		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC3CO);
+		/*
+		 * Use minimal re-enable delay to allow DC3CO entry on
+		 * the next idle frame, unlike the 17ms guard needed to
+		 * prevent DC5/DC6 toggling overhead at 60+ FPS.
+		 */
+		power_async_delay = 1;
+	} else {
+		/*
+		 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
+		 * toggling overhead at and above 60 FPS.
+		 */
+		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
+		power_async_delay = 17;
+	}
+
+	intel_display_power_put_async_delay(display,
+					    POWER_DOMAIN_DC_OFF, wakeref, power_async_delay);
+
 	intel_display_rpm_put(display, state->wakeref);
 
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 1e76a455d7c4..2795e4b9e799 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -521,5 +521,4 @@ bool assert_port_valid(struct intel_display *display, enum port port);
 
 bool intel_scanout_needs_vtd_wa(struct intel_display *display);
 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
-
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index c5a07090cba6..13e9b986b6fc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -535,7 +535,8 @@ struct intel_display {
 
 	struct {
 		struct i915_power_domains domains;
-
+		/* DC3CO eligibility state */
+		struct intel_dc3co_state dc3co;
 		/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
 		u32 chv_phy_control;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index f626803bbd88..ff1915be59c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -372,6 +372,35 @@ bool intel_display_power_dc3co_supported(struct intel_display *display)
 	return (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) == DC_STATE_EN_UPTO_DC3CO;
 }
 
+void intel_display_power_dc3co_update(struct intel_display *display,
+				      bool allowed, u32 trigger)
+{
+	struct intel_dc3co_state *dc3co = &display->power.dc3co;
+
+	if (!HAS_DC3CO(display))
+		return;
+
+	mutex_lock(&dc3co->lock);
+	dc3co->allowed = allowed;
+	dc3co->trigger = trigger;
+	mutex_unlock(&dc3co->lock);
+}
+
+bool intel_display_power_dc3co_allowed(struct intel_display *display)
+{
+	struct intel_dc3co_state *dc3co = &display->power.dc3co;
+	bool allowed;
+
+	if (!HAS_DC3CO(display))
+		return false;
+
+	mutex_lock(&dc3co->lock);
+	allowed = dc3co->allowed;
+	mutex_unlock(&dc3co->lock);
+
+	return allowed;
+}
+
 static void __async_put_domains_mask(struct i915_power_domains *power_domains,
 				     struct intel_power_domain_mask *mask)
 {
@@ -1051,6 +1080,7 @@ int intel_power_domains_init(struct intel_display *display)
 		sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
 
 	mutex_init(&power_domains->lock);
+	mutex_init(&display->power.dc3co.lock);
 
 	INIT_DELAYED_WORK(&power_domains->async_put_work,
 			  intel_display_power_put_async_work);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 05880e9da89f..0b1a06f88ae5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -131,6 +131,25 @@ struct intel_power_domain_mask {
 	DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
 };
 
+/*
+ * DC3CO enabling triggers (bitmask).
+ * DC3CO may be enabled when at least one of these triggers is active.
+ * Additional constraints may still apply.
+ */
+#define DC3CO_TRIGGER_NONE		(0)
+#define DC3CO_TRIGGER_PSR2		BIT(0)
+#define DC3CO_TRIGGER_LOBF		BIT(1)
+#define DC3CO_TRIGGER_PANEL_REPLAY	BIT(2)
+#define DC3CO_TRIGGER_ALL		(DC3CO_TRIGGER_PSR2 | \
+					 DC3CO_TRIGGER_LOBF | \
+					 DC3CO_TRIGGER_PANEL_REPLAY)
+
+struct intel_dc3co_state {
+	struct mutex lock; /* Protects allowed and trigger fields */
+	bool allowed; /* DC3CO eligibility result */
+	u32 trigger; /* Bitmask of active DC3CO triggers */
+};
+
 struct i915_power_domains {
 	/*
 	 * Power wells needed for initialization at driver init and suspend
@@ -187,6 +206,9 @@ void intel_display_power_set_target_dc_state(struct intel_display *display,
 					     u32 state);
 u32 intel_display_power_get_current_dc_state(struct intel_display *display);
 bool intel_display_power_dc3co_supported(struct intel_display *display);
+void intel_display_power_dc3co_update(struct intel_display *display,
+				      bool allowed, u32 trigger);
+bool intel_display_power_dc3co_allowed(struct intel_display *display);
 
 bool intel_display_power_is_enabled(struct intel_display *display,
 				    enum intel_display_power_domain domain);
-- 
2.43.0

[PATCH v2 08/13] drm/i915/display: Store DC3CO eligibility in PSR state

[Dibin Moolakadan Subrahmanian]

Store DC3CO eligibility in intel_dp->psr during
intel_psr_post_plane_update() so PSR configuration
can take DC3CO into account.

This will be used to control PSR2 parameters such as idle frames.

Changes in v2:
- Use intel_display_power_dc3co_allowed(display) instead
  of intel_dc3co_allowed(state)

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++
 drivers/gpu/drm/i915/display/intel_psr.c           | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index fc283cc429ec..28ab686b702a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1769,6 +1769,8 @@ struct intel_psr {
 	ktime_t last_exit;
 	bool sink_not_reliable;
 	bool irq_aux_error;
+	/* DC3CO eligibility used to control PSR configuration */
+	bool dc3co_eligible;
 	u16 su_w_granularity;
 	u16 su_y_granularity;
 	bool source_panel_replay_support;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 34e4a1ad609e..2e0478e3d560 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2263,6 +2263,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
 	intel_dp->psr.active_non_psr_pipes = 0;
 	intel_dp->psr.pkg_c_latency_used = 0;
+	intel_dp->psr.dc3co_eligible = false;
 }
 
 /**
@@ -3095,6 +3096,9 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
 		 */
 		intel_dp->psr.busy_frontbuffer_bits = 0;
 
+		intel_dp->psr.dc3co_eligible = intel_display_power_dc3co_allowed(display) &&
+			intel_display_power_dc3co_supported(display);
+
 		mutex_unlock(&psr->lock);
 	}
 }
-- 
2.43.0

[PATCH v2 09/13] drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO

[Dibin Moolakadan Subrahmanian]

Force idle_frames to 0 when DC3CO is eligible.

Changes in v2:
- Extend existing Wa_16025596647 condition
  instead of adding a new if block (Uma Shankar)

BSpec: 75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2e0478e3d560..ff9ce7d2a5aa 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1069,10 +1069,11 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	u32 psr_val = 0;
 	u8 idle_frames;
 
-	/* Wa_16025596647 */
-	if ((DISPLAY_VER(display) == 20 ||
-	     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
-	    is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
+	/* DC3CO / Wa_16025596647 */
+	if (intel_dp->psr.dc3co_eligible ||
+	    ((DISPLAY_VER(display) == 20 ||
+	      IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
+	     is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used))
 		idle_frames = 0;
 	else
 		idle_frames = psr_compute_idle_frames(intel_dp);
-- 
2.43.0

[PATCH v2 10/13] drm/i915/display: Enable DC3CO idle protocol in ALPM

[Dibin Moolakadan Subrahmanian]

Add PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL bit definition and set it
when DC3CO is allowed.

Changes in v2:
- Squash "Define DC3CO idle protocol bit in PR_ALPM_CTL"
  into this patch (Uma Shankar)
- Use intel_display_power_dc3co_allowed(display)
  instead of intel_dc3co_allowed(state)

BSpec: 75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 6 ++++++
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index a7350ce8e716..6394d1568b54 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -389,6 +389,12 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			if (crtc_state->disable_as_sdp_when_pr_active)
 				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
 
+			if (intel_display_power_dc3co_allowed(display) &&
+			    intel_display_power_dc3co_supported(display))
+				pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
+			else
+				pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
+
 			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
 				       pr_alpm_ctl);
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 8afbf5a38335..16a9e3af198d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -268,6 +268,7 @@
 
 #define _PR_ALPM_CTL_A	0x60948
 #define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _PR_ALPM_CTL_A)
+#define  PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL			BIT(7)
 #define  PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU	BIT(6)
 #define  PR_ALPM_CTL_RFB_UPDATE_CONTROL				BIT(5)
 #define  PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE	BIT(4)
-- 
2.43.0

[PATCH v2 11/13] drm/i915/display: PSR Add delayed work to exit DC3CO

[Dibin Moolakadan Subrahmanian]

For DC3CO, idle_frames is programmed to 0, so PSR does not
enter deep sleep. Add delayed work to schedule DC3CO exit
after an idle duration derived from frame time (minimum
equivalent of 6 frames).

The work is re-armed from the PSR flush path on relevant frontbuffer
activity. Once the display remains idle, DC3CO is disabled, idle frames
are reprogrammed to their normal value, and DC6 is enabled to allow
deeper power savings.

Changes in v2:
- Squash "PSR set idle frames while exit from DC3CO"
  into this patch (Uma Shankar)
- Add cancel_delayed_work() in intel_psr_disable_locked()
  before clearing dc3co_eligible (Uma Shankar)

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  2 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 50 +++++++++++++++++++
 2 files changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 28ab686b702a..fb5c12bb5b5c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1771,6 +1771,8 @@ struct intel_psr {
 	bool irq_aux_error;
 	/* DC3CO eligibility used to control PSR configuration */
 	bool dc3co_eligible;
+	/* DC3CO disable work */
+	struct delayed_work dc3co_work;
 	u16 su_w_granularity;
 	u16 su_y_granularity;
 	bool source_panel_replay_support;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index ff9ce7d2a5aa..36180206d3ad 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1728,6 +1728,51 @@ static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp,
 		!crtc_state->has_sel_update);
 }
 
+static void psr2_dc3co_disable_locked(struct intel_dp *intel_dp)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	if (intel_dp->psr.dc3co_eligible) {
+		intel_dp->psr.dc3co_eligible = false;
+		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
+		psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
+	}
+}
+
+static void psr2_dc3co_disable_work(struct work_struct *work)
+{
+	struct intel_dp *intel_dp =
+		container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
+
+	mutex_lock(&intel_dp->psr.lock);
+	psr2_dc3co_disable_locked(intel_dp);
+	mutex_unlock(&intel_dp->psr.lock);
+}
+
+static void
+psr2_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
+			enum fb_op_origin origin)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	if (!intel_dp->psr.dc3co_eligible)
+		return;
+
+	if (!intel_dp->psr.sel_update_enabled ||
+	    !intel_dp->psr.active)
+		return;
+	/*
+	 * At every frontbuffer flush flip event modified delay of delayed work,
+	 * when delayed work schedules that means display has been idle.
+	 */
+	if (!(frontbuffer_bits &
+	    INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
+		return;
+
+	mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,
+			 intel_dp->psr.dc3co_exit_delay);
+}
+
 static
 void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp,
 				 struct intel_crtc_state *crtc_state)
@@ -2264,6 +2309,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
 	intel_dp->psr.active_non_psr_pipes = 0;
 	intel_dp->psr.pkg_c_latency_used = 0;
+	cancel_delayed_work(&intel_dp->psr.dc3co_work);
 	intel_dp->psr.dc3co_eligible = false;
 }
 
@@ -2294,6 +2340,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
 
 	mutex_unlock(&intel_dp->psr.lock);
 	cancel_work_sync(&intel_dp->psr.work);
+	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
 }
 
 /**
@@ -2324,6 +2371,7 @@ void intel_psr_pause(struct intel_dp *intel_dp)
 	mutex_unlock(&psr->lock);
 
 	cancel_work_sync(&psr->work);
+	cancel_delayed_work_sync(&psr->dc3co_work);
 }
 
 /**
@@ -3558,6 +3606,7 @@ void intel_psr_flush(struct intel_display *display,
 		if (origin == ORIGIN_FLIP ||
 		    (origin == ORIGIN_CURSOR_UPDATE &&
 		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
+			psr2_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);
 			goto unlock;
 		}
 
@@ -3616,6 +3665,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
 		intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
 
 	INIT_WORK(&intel_dp->psr.work, intel_psr_work);
+	INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, psr2_dc3co_disable_work);
 	mutex_init(&intel_dp->psr.lock);
 }
 
-- 
2.43.0

[PATCH v2 12/13] drm/i915/display: Add helper to enable DC counter

[Dibin Moolakadan Subrahmanian]

Add xe3lpd_enable_dc_count() to enable the DC_COUNT_EN register.
Also define DC_STATE_DC3CO_RESIDENCY to read DC3CO residency.
Needed to retrieve DC residency for DC3CO.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power_well.c | 5 +++++
 drivers/gpu/drm/i915/display/intel_display_power_well.h | 1 +
 drivers/gpu/drm/i915/display/intel_display_regs.h       | 5 +++++
 drivers/gpu/drm/i915/display/intel_dmc.c                | 3 +++
 4 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 5e002d459e95..16204b930adb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -866,6 +866,11 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 	power_domains->dc_state = val & mask;
 }
 
+void xe3lpd_enable_dc_count(struct intel_display *display)
+{
+	intel_de_write(display, DC_COUNT_EN, DC_COUNT_EN_COUNTER_ENABLE);
+}
+
 static void xe3lpd_enable_dc3co(struct intel_display *display)
 {
 	drm_dbg_kms(display->drm, "Enabling DC3CO\n");
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index 8f5524da2d06..0ce64b894436 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -159,6 +159,7 @@ void gen9_set_dc_state(struct intel_display *display, u32 state);
 void gen9_disable_dc_states(struct intel_display *display);
 void bxt_enable_dc9(struct intel_display *display);
 void bxt_disable_dc9(struct intel_display *display);
+void xe3lpd_enable_dc_count(struct intel_display *display);
 
 extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
 extern const struct i915_power_well_ops chv_pipe_power_well_ops;
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index fa56cc506e3f..b9d60ec09e4d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3053,6 +3053,11 @@ enum skl_power_gate {
 #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
 #define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1 << 1)
 
+#define DC_COUNT_EN			_MMIO(0x457B4)
+#define DC_COUNT_EN_COUNTER_ENABLE	REG_BIT(31)
+
+#define DC_STATE_DC3CO_RESIDENCY	_MMIO(0x457B8)
+
 #define D_COMP_BDW			_MMIO(0x138144)
 
 /* Pipe WM_LINETIME - watermark line time */
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 8b5840116f64..a85e2edcb894 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -941,6 +941,9 @@ void intel_dmc_load_program(struct intel_display *display)
 
 	gen9_set_dc_state_debugmask(display);
 
+	if (DISPLAY_VER(display) >= 35)
+		xe3lpd_enable_dc_count(display);
+
 	pipedmc_clock_gating_wa(display, false);
 }
 
-- 
2.43.0

[PATCH v2 13/13] drm/i915/display: Add DC3CO count and residency in dmc debugfs

[Dibin Moolakadan Subrahmanian]

Expose DC3CO count and residency for xe3lp platforms via debugfs.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c      | 8 +++++++-
 drivers/gpu/drm/i915/display/intel_dmc_regs.h | 2 ++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index a85e2edcb894..3cd960163d28 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1650,7 +1650,13 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 		   DMC_VERSION_MINOR(dmc->version));
 
 	if (DISPLAY_VER(display) >= 12) {
-		if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {
+		if (DISPLAY_VER(display) >= 35) {
+			seq_printf(m, "DC3CO count: %d\n",
+				   intel_de_read(display, XE3P_DMC_DC3CO_COUNT));
+
+			seq_printf(m, "DC3CO residency: %d\n",
+				   intel_de_read(display, DC_STATE_DC3CO_RESIDENCY));
+		} else if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {
 			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
 		} else {
 			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index 38e342b45af0..1998549b6318 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -531,6 +531,8 @@ enum pipedmc_event_id {
 #define TGL_DMC_DEBUG3		_MMIO(0x101090)
 #define DG1_DMC_DEBUG3		_MMIO(0x13415c)
 
+#define XE3P_DMC_DC3CO_COUNT	_MMIO(0x8f05C)
+
 #define DMC_WAKELOCK_CFG	_MMIO(0x8F1B0)
 #define  DMC_WAKELOCK_CFG_ENABLE REG_BIT(31)
 #define DMC_WAKELOCK1_CTL	_MMIO(0x8F140)
-- 
2.43.0

✓ CI.KUnit: success for drm/i915/display: Add DC3CO support (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Add DC3CO support (rev2)
URL   : https://patchwork.freedesktop.org/series/163938/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:26:05] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:26:09] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[21:26:48] Starting KUnit Kernel (1/1)...
[21:26:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:26:48] ================== guc_buf (11 subtests) ===================
[21:26:48] [PASSED] test_smallest
[21:26:48] [PASSED] test_largest
[21:26:48] [PASSED] test_granular
[21:26:48] [PASSED] test_unique
[21:26:48] [PASSED] test_overlap
[21:26:48] [PASSED] test_reusable
[21:26:48] [PASSED] test_too_big
[21:26:48] [PASSED] test_flush
[21:26:48] [PASSED] test_lookup
[21:26:48] [PASSED] test_data
[21:26:48] [PASSED] test_class
[21:26:48] ===================== [PASSED] guc_buf =====================
[21:26:48] =================== guc_dbm (7 subtests) ===================
[21:26:48] [PASSED] test_empty
[21:26:48] [PASSED] test_default
[21:26:48] ======================== test_size  ========================
[21:26:48] [PASSED] 4
[21:26:48] [PASSED] 8
[21:26:48] [PASSED] 32
[21:26:48] [PASSED] 256
[21:26:48] ==================== [PASSED] test_size ====================
[21:26:48] ======================= test_reuse  ========================
[21:26:48] [PASSED] 4
[21:26:48] [PASSED] 8
[21:26:48] [PASSED] 32
[21:26:48] [PASSED] 256
[21:26:48] =================== [PASSED] test_reuse ====================
[21:26:48] =================== test_range_overlap  ====================
[21:26:48] [PASSED] 4
[21:26:48] [PASSED] 8
[21:26:48] [PASSED] 32
[21:26:48] [PASSED] 256
[21:26:48] =============== [PASSED] test_range_overlap ================
[21:26:48] =================== test_range_compact  ====================
[21:26:48] [PASSED] 4
[21:26:48] [PASSED] 8
[21:26:48] [PASSED] 32
[21:26:48] [PASSED] 256
[21:26:48] =============== [PASSED] test_range_compact ================
[21:26:48] ==================== test_range_spare  =====================
[21:26:48] [PASSED] 4
[21:26:48] [PASSED] 8
[21:26:48] [PASSED] 32
[21:26:48] [PASSED] 256
[21:26:48] ================ [PASSED] test_range_spare =================
[21:26:48] ===================== [PASSED] guc_dbm =====================
[21:26:48] =================== guc_idm (6 subtests) ===================
[21:26:48] [PASSED] bad_init
[21:26:48] [PASSED] no_init
[21:26:48] [PASSED] init_fini
[21:26:48] [PASSED] check_used
[21:26:48] [PASSED] check_quota
[21:26:48] [PASSED] check_all
[21:26:48] ===================== [PASSED] guc_idm =====================
[21:26:48] ================== no_relay (3 subtests) ===================
[21:26:48] [PASSED] xe_drops_guc2pf_if_not_ready
[21:26:48] [PASSED] xe_drops_guc2vf_if_not_ready
[21:26:48] [PASSED] xe_rejects_send_if_not_ready
[21:26:48] ==================== [PASSED] no_relay =====================
[21:26:48] ================== pf_relay (14 subtests) ==================
[21:26:48] [PASSED] pf_rejects_guc2pf_too_short
[21:26:48] [PASSED] pf_rejects_guc2pf_too_long
[21:26:48] [PASSED] pf_rejects_guc2pf_no_payload
[21:26:48] [PASSED] pf_fails_no_payload
[21:26:48] [PASSED] pf_fails_bad_origin
[21:26:48] [PASSED] pf_fails_bad_type
[21:26:48] [PASSED] pf_txn_reports_error
[21:26:48] [PASSED] pf_txn_sends_pf2guc
[21:26:48] [PASSED] pf_sends_pf2guc
[21:26:48] [SKIPPED] pf_loopback_nop
[21:26:48] [SKIPPED] pf_loopback_echo
[21:26:48] [SKIPPED] pf_loopback_fail
[21:26:48] [SKIPPED] pf_loopback_busy
[21:26:48] [SKIPPED] pf_loopback_retry
[21:26:48] ==================== [PASSED] pf_relay =====================
[21:26:48] ================== vf_relay (3 subtests) ===================
[21:26:48] [PASSED] vf_rejects_guc2vf_too_short
[21:26:48] [PASSED] vf_rejects_guc2vf_too_long
[21:26:48] [PASSED] vf_rejects_guc2vf_no_payload
[21:26:48] ==================== [PASSED] vf_relay =====================
[21:26:48] ================ pf_gt_config (9 subtests) =================
[21:26:48] [PASSED] fair_contexts_1vf
[21:26:48] [PASSED] fair_doorbells_1vf
[21:26:48] [PASSED] fair_ggtt_1vf
[21:26:48] ====================== fair_vram_1vf  ======================
[21:26:48] [PASSED] 3.50 GiB
[21:26:48] [PASSED] 11.5 GiB
[21:26:48] [PASSED] 15.5 GiB
[21:26:48] [PASSED] 31.5 GiB
[21:26:48] [PASSED] 63.5 GiB
[21:26:48] [PASSED] 1.91 GiB
[21:26:48] ================== [PASSED] fair_vram_1vf ==================
[21:26:48] ================ fair_vram_1vf_admin_only  =================
[21:26:48] [PASSED] 3.50 GiB
[21:26:48] [PASSED] 11.5 GiB
[21:26:48] [PASSED] 15.5 GiB
[21:26:48] [PASSED] 31.5 GiB
[21:26:48] [PASSED] 63.5 GiB
[21:26:48] [PASSED] 1.91 GiB
[21:26:48] ============ [PASSED] fair_vram_1vf_admin_only =============
[21:26:48] ====================== fair_contexts  ======================
[21:26:48] [PASSED] 1 VF
[21:26:48] [PASSED] 2 VFs
[21:26:48] [PASSED] 3 VFs
[21:26:48] [PASSED] 4 VFs
[21:26:48] [PASSED] 5 VFs
[21:26:48] [PASSED] 6 VFs
[21:26:48] [PASSED] 7 VFs
[21:26:48] [PASSED] 8 VFs
[21:26:48] [PASSED] 9 VFs
[21:26:48] [PASSED] 10 VFs
[21:26:48] [PASSED] 11 VFs
[21:26:48] [PASSED] 12 VFs
[21:26:48] [PASSED] 13 VFs
[21:26:48] [PASSED] 14 VFs
[21:26:48] [PASSED] 15 VFs
[21:26:48] [PASSED] 16 VFs
[21:26:48] [PASSED] 17 VFs
[21:26:48] [PASSED] 18 VFs
[21:26:48] [PASSED] 19 VFs
[21:26:48] [PASSED] 20 VFs
[21:26:48] [PASSED] 21 VFs
[21:26:48] [PASSED] 22 VFs
[21:26:48] [PASSED] 23 VFs
[21:26:48] [PASSED] 24 VFs
[21:26:48] [PASSED] 25 VFs
[21:26:48] [PASSED] 26 VFs
[21:26:48] [PASSED] 27 VFs
[21:26:48] [PASSED] 28 VFs
[21:26:48] [PASSED] 29 VFs
[21:26:48] [PASSED] 30 VFs
[21:26:48] [PASSED] 31 VFs
[21:26:48] [PASSED] 32 VFs
[21:26:48] [PASSED] 33 VFs
[21:26:48] [PASSED] 34 VFs
[21:26:48] [PASSED] 35 VFs
[21:26:48] [PASSED] 36 VFs
[21:26:48] [PASSED] 37 VFs
[21:26:48] [PASSED] 38 VFs
[21:26:48] [PASSED] 39 VFs
[21:26:48] [PASSED] 40 VFs
[21:26:48] [PASSED] 41 VFs
[21:26:48] [PASSED] 42 VFs
[21:26:48] [PASSED] 43 VFs
[21:26:48] [PASSED] 44 VFs
[21:26:48] [PASSED] 45 VFs
[21:26:48] [PASSED] 46 VFs
[21:26:48] [PASSED] 47 VFs
[21:26:48] [PASSED] 48 VFs
[21:26:48] [PASSED] 49 VFs
[21:26:48] [PASSED] 50 VFs
[21:26:48] [PASSED] 51 VFs
[21:26:48] [PASSED] 52 VFs
[21:26:48] [PASSED] 53 VFs
[21:26:48] [PASSED] 54 VFs
[21:26:48] [PASSED] 55 VFs
[21:26:48] [PASSED] 56 VFs
[21:26:48] [PASSED] 57 VFs
[21:26:48] [PASSED] 58 VFs
[21:26:48] [PASSED] 59 VFs
[21:26:48] [PASSED] 60 VFs
[21:26:48] [PASSED] 61 VFs
[21:26:48] [PASSED] 62 VFs
[21:26:48] [PASSED] 63 VFs
[21:26:48] ================== [PASSED] fair_contexts ==================
[21:26:48] ===================== fair_doorbells  ======================
[21:26:48] [PASSED] 1 VF
[21:26:48] [PASSED] 2 VFs
[21:26:48] [PASSED] 3 VFs
[21:26:48] [PASSED] 4 VFs
[21:26:48] [PASSED] 5 VFs
[21:26:48] [PASSED] 6 VFs
[21:26:48] [PASSED] 7 VFs
[21:26:48] [PASSED] 8 VFs
[21:26:48] [PASSED] 9 VFs
[21:26:48] [PASSED] 10 VFs
[21:26:48] [PASSED] 11 VFs
[21:26:48] [PASSED] 12 VFs
[21:26:48] [PASSED] 13 VFs
[21:26:48] [PASSED] 14 VFs
[21:26:48] [PASSED] 15 VFs
[21:26:48] [PASSED] 16 VFs
[21:26:48] [PASSED] 17 VFs
[21:26:48] [PASSED] 18 VFs
[21:26:48] [PASSED] 19 VFs
[21:26:48] [PASSED] 20 VFs
[21:26:48] [PASSED] 21 VFs
[21:26:48] [PASSED] 22 VFs
[21:26:48] [PASSED] 23 VFs
[21:26:48] [PASSED] 24 VFs
[21:26:48] [PASSED] 25 VFs
[21:26:48] [PASSED] 26 VFs
[21:26:48] [PASSED] 27 VFs
[21:26:48] [PASSED] 28 VFs
[21:26:48] [PASSED] 29 VFs
[21:26:48] [PASSED] 30 VFs
[21:26:48] [PASSED] 31 VFs
[21:26:48] [PASSED] 32 VFs
[21:26:48] [PASSED] 33 VFs
[21:26:48] [PASSED] 34 VFs
[21:26:48] [PASSED] 35 VFs
[21:26:48] [PASSED] 36 VFs
[21:26:48] [PASSED] 37 VFs
[21:26:48] [PASSED] 38 VFs
[21:26:48] [PASSED] 39 VFs
[21:26:48] [PASSED] 40 VFs
[21:26:48] [PASSED] 41 VFs
[21:26:48] [PASSED] 42 VFs
[21:26:48] [PASSED] 43 VFs
[21:26:48] [PASSED] 44 VFs
[21:26:48] [PASSED] 45 VFs
[21:26:48] [PASSED] 46 VFs
[21:26:48] [PASSED] 47 VFs
[21:26:48] [PASSED] 48 VFs
[21:26:48] [PASSED] 49 VFs
[21:26:48] [PASSED] 50 VFs
[21:26:48] [PASSED] 51 VFs
[21:26:48] [PASSED] 52 VFs
[21:26:48] [PASSED] 53 VFs
[21:26:48] [PASSED] 54 VFs
[21:26:48] [PASSED] 55 VFs
[21:26:48] [PASSED] 56 VFs
[21:26:48] [PASSED] 57 VFs
[21:26:48] [PASSED] 58 VFs
[21:26:48] [PASSED] 59 VFs
[21:26:48] [PASSED] 60 VFs
[21:26:48] [PASSED] 61 VFs
[21:26:48] [PASSED] 62 VFs
[21:26:48] [PASSED] 63 VFs
[21:26:48] ================= [PASSED] fair_doorbells ==================
[21:26:48] ======================== fair_ggtt  ========================
[21:26:48] [PASSED] 1 VF
[21:26:48] [PASSED] 2 VFs
[21:26:48] [PASSED] 3 VFs
[21:26:48] [PASSED] 4 VFs
[21:26:48] [PASSED] 5 VFs
[21:26:48] [PASSED] 6 VFs
[21:26:48] [PASSED] 7 VFs
[21:26:48] [PASSED] 8 VFs
[21:26:48] [PASSED] 9 VFs
[21:26:48] [PASSED] 10 VFs
[21:26:48] [PASSED] 11 VFs
[21:26:48] [PASSED] 12 VFs
[21:26:48] [PASSED] 13 VFs
[21:26:48] [PASSED] 14 VFs
[21:26:48] [PASSED] 15 VFs
[21:26:48] [PASSED] 16 VFs
[21:26:48] [PASSED] 17 VFs
[21:26:48] [PASSED] 18 VFs
[21:26:48] [PASSED] 19 VFs
[21:26:48] [PASSED] 20 VFs
[21:26:48] [PASSED] 21 VFs
[21:26:48] [PASSED] 22 VFs
[21:26:48] [PASSED] 23 VFs
[21:26:48] [PASSED] 24 VFs
[21:26:48] [PASSED] 25 VFs
[21:26:48] [PASSED] 26 VFs
[21:26:48] [PASSED] 27 VFs
[21:26:48] [PASSED] 28 VFs
[21:26:48] [PASSED] 29 VFs
[21:26:48] [PASSED] 30 VFs
[21:26:48] [PASSED] 31 VFs
[21:26:48] [PASSED] 32 VFs
[21:26:48] [PASSED] 33 VFs
[21:26:48] [PASSED] 34 VFs
[21:26:48] [PASSED] 35 VFs
[21:26:48] [PASSED] 36 VFs
[21:26:48] [PASSED] 37 VFs
[21:26:48] [PASSED] 38 VFs
[21:26:48] [PASSED] 39 VFs
[21:26:48] [PASSED] 40 VFs
[21:26:48] [PASSED] 41 VFs
[21:26:48] [PASSED] 42 VFs
[21:26:48] [PASSED] 43 VFs
[21:26:48] [PASSED] 44 VFs
[21:26:48] [PASSED] 45 VFs
[21:26:48] [PASSED] 46 VFs
[21:26:48] [PASSED] 47 VFs
[21:26:48] [PASSED] 48 VFs
[21:26:48] [PASSED] 49 VFs
[21:26:48] [PASSED] 50 VFs
[21:26:48] [PASSED] 51 VFs
[21:26:48] [PASSED] 52 VFs
[21:26:48] [PASSED] 53 VFs
[21:26:48] [PASSED] 54 VFs
[21:26:48] [PASSED] 55 VFs
[21:26:48] [PASSED] 56 VFs
[21:26:48] [PASSED] 57 VFs
[21:26:48] [PASSED] 58 VFs
[21:26:48] [PASSED] 59 VFs
[21:26:48] [PASSED] 60 VFs
[21:26:48] [PASSED] 61 VFs
[21:26:48] [PASSED] 62 VFs
[21:26:48] [PASSED] 63 VFs
[21:26:48] ==================== [PASSED] fair_ggtt ====================
[21:26:48] ======================== fair_vram  ========================
[21:26:48] [PASSED] 1 VF
[21:26:48] [PASSED] 2 VFs
[21:26:48] [PASSED] 3 VFs
[21:26:48] [PASSED] 4 VFs
[21:26:48] [PASSED] 5 VFs
[21:26:48] [PASSED] 6 VFs
[21:26:48] [PASSED] 7 VFs
[21:26:48] [PASSED] 8 VFs
[21:26:48] [PASSED] 9 VFs
[21:26:48] [PASSED] 10 VFs
[21:26:48] [PASSED] 11 VFs
[21:26:48] [PASSED] 12 VFs
[21:26:48] [PASSED] 13 VFs
[21:26:48] [PASSED] 14 VFs
[21:26:48] [PASSED] 15 VFs
[21:26:48] [PASSED] 16 VFs
[21:26:48] [PASSED] 17 VFs
[21:26:48] [PASSED] 18 VFs
[21:26:48] [PASSED] 19 VFs
[21:26:48] [PASSED] 20 VFs
[21:26:48] [PASSED] 21 VFs
[21:26:48] [PASSED] 22 VFs
[21:26:48] [PASSED] 23 VFs
[21:26:48] [PASSED] 24 VFs
[21:26:48] [PASSED] 25 VFs
[21:26:48] [PASSED] 26 VFs
[21:26:48] [PASSED] 27 VFs
[21:26:48] [PASSED] 28 VFs
[21:26:48] [PASSED] 29 VFs
[21:26:48] [PASSED] 30 VFs
[21:26:48] [PASSED] 31 VFs
[21:26:48] [PASSED] 32 VFs
[21:26:48] [PASSED] 33 VFs
[21:26:48] [PASSED] 34 VFs
[21:26:48] [PASSED] 35 VFs
[21:26:48] [PASSED] 36 VFs
[21:26:48] [PASSED] 37 VFs
[21:26:48] [PASSED] 38 VFs
[21:26:48] [PASSED] 39 VFs
[21:26:48] [PASSED] 40 VFs
[21:26:48] [PASSED] 41 VFs
[21:26:48] [PASSED] 42 VFs
[21:26:48] [PASSED] 43 VFs
[21:26:48] [PASSED] 44 VFs
[21:26:48] [PASSED] 45 VFs
[21:26:48] [PASSED] 46 VFs
[21:26:48] [PASSED] 47 VFs
[21:26:48] [PASSED] 48 VFs
[21:26:48] [PASSED] 49 VFs
[21:26:48] [PASSED] 50 VFs
[21:26:48] [PASSED] 51 VFs
[21:26:48] [PASSED] 52 VFs
[21:26:48] [PASSED] 53 VFs
[21:26:48] [PASSED] 54 VFs
[21:26:48] [PASSED] 55 VFs
[21:26:48] [PASSED] 56 VFs
[21:26:48] [PASSED] 57 VFs
[21:26:48] [PASSED] 58 VFs
[21:26:48] [PASSED] 59 VFs
[21:26:48] [PASSED] 60 VFs
[21:26:48] [PASSED] 61 VFs
[21:26:48] [PASSED] 62 VFs
[21:26:48] [PASSED] 63 VFs
[21:26:48] ==================== [PASSED] fair_vram ====================
[21:26:48] ================== [PASSED] pf_gt_config ===================
[21:26:48] ===================== lmtt (1 subtest) =====================
[21:26:48] ======================== test_ops  =========================
[21:26:48] [PASSED] 2-level
[21:26:48] [PASSED] multi-level
[21:26:48] ==================== [PASSED] test_ops =====================
[21:26:48] ====================== [PASSED] lmtt =======================
[21:26:48] ================= pf_service (11 subtests) =================
[21:26:48] [PASSED] pf_negotiate_any
[21:26:48] [PASSED] pf_negotiate_base_match
[21:26:48] [PASSED] pf_negotiate_base_newer
[21:26:48] [PASSED] pf_negotiate_base_next
[21:26:48] [SKIPPED] pf_negotiate_base_older
[21:26:48] [PASSED] pf_negotiate_base_prev
[21:26:48] [PASSED] pf_negotiate_latest_match
[21:26:48] [PASSED] pf_negotiate_latest_newer
[21:26:48] [PASSED] pf_negotiate_latest_next
[21:26:48] [SKIPPED] pf_negotiate_latest_older
[21:26:48] [SKIPPED] pf_negotiate_latest_prev
[21:26:48] =================== [PASSED] pf_service ====================
[21:26:48] ================= xe_guc_g2g (2 subtests) ==================
[21:26:48] ============== xe_live_guc_g2g_kunit_default  ==============
[21:26:48] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[21:26:48] ============== xe_live_guc_g2g_kunit_allmem  ===============
[21:26:48] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[21:26:48] =================== [SKIPPED] xe_guc_g2g ===================
[21:26:48] =================== xe_mocs (2 subtests) ===================
[21:26:48] ================ xe_live_mocs_kernel_kunit  ================
[21:26:48] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:26:48] ================ xe_live_mocs_reset_kunit  =================
[21:26:48] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:26:48] ==================== [SKIPPED] xe_mocs =====================
[21:26:48] ================= xe_migrate (2 subtests) ==================
[21:26:48] ================= xe_migrate_sanity_kunit  =================
[21:26:48] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:26:48] ================== xe_validate_ccs_kunit  ==================
[21:26:48] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:26:48] =================== [SKIPPED] xe_migrate ===================
[21:26:48] ================== xe_dma_buf (1 subtest) ==================
[21:26:48] ==================== xe_dma_buf_kunit  =====================
[21:26:48] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:26:48] =================== [SKIPPED] xe_dma_buf ===================
[21:26:48] ================= xe_bo_shrink (1 subtest) =================
[21:26:48] =================== xe_bo_shrink_kunit  ====================
[21:26:48] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:26:48] ================== [SKIPPED] xe_bo_shrink ==================
[21:26:48] ==================== xe_bo (2 subtests) ====================
[21:26:48] ================== xe_ccs_migrate_kunit  ===================
[21:26:48] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:26:48] ==================== xe_bo_evict_kunit  ====================
[21:26:48] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:26:48] ===================== [SKIPPED] xe_bo ======================
[21:26:48] ==================== args (13 subtests) ====================
[21:26:48] [PASSED] count_args_test
[21:26:48] [PASSED] call_args_example
[21:26:48] [PASSED] call_args_test
[21:26:48] [PASSED] drop_first_arg_example
[21:26:48] [PASSED] drop_first_arg_test
[21:26:48] [PASSED] first_arg_example
[21:26:48] [PASSED] first_arg_test
[21:26:48] [PASSED] last_arg_example
[21:26:48] [PASSED] last_arg_test
[21:26:48] [PASSED] pick_arg_example
[21:26:48] [PASSED] if_args_example
[21:26:48] [PASSED] if_args_test
[21:26:48] [PASSED] sep_comma_example
[21:26:48] ====================== [PASSED] args =======================
[21:26:48] =================== xe_pci (3 subtests) ====================
[21:26:48] ==================== check_graphics_ip  ====================
[21:26:48] [PASSED] 12.00 Xe_LP
[21:26:48] [PASSED] 12.10 Xe_LP+
[21:26:48] [PASSED] 12.55 Xe_HPG
[21:26:48] [PASSED] 12.60 Xe_HPC
[21:26:48] [PASSED] 12.70 Xe_LPG
[21:26:48] [PASSED] 12.71 Xe_LPG
[21:26:48] [PASSED] 12.74 Xe_LPG+
[21:26:48] [PASSED] 20.01 Xe2_HPG
[21:26:48] [PASSED] 20.02 Xe2_HPG
[21:26:48] [PASSED] 20.04 Xe2_LPG
[21:26:48] [PASSED] 30.00 Xe3_LPG
[21:26:48] [PASSED] 30.01 Xe3_LPG
[21:26:48] [PASSED] 30.03 Xe3_LPG
[21:26:48] [PASSED] 30.04 Xe3_LPG
[21:26:48] [PASSED] 30.05 Xe3_LPG
[21:26:48] [PASSED] 35.10 Xe3p_LPG
[21:26:48] [PASSED] 35.11 Xe3p_XPC
[21:26:48] ================ [PASSED] check_graphics_ip ================
[21:26:48] ===================== check_media_ip  ======================
[21:26:48] [PASSED] 12.00 Xe_M
[21:26:48] [PASSED] 12.55 Xe_HPM
[21:26:48] [PASSED] 13.00 Xe_LPM+
[21:26:48] [PASSED] 13.01 Xe2_HPM
[21:26:48] [PASSED] 20.00 Xe2_LPM
[21:26:48] [PASSED] 30.00 Xe3_LPM
[21:26:48] [PASSED] 30.02 Xe3_LPM
[21:26:48] [PASSED] 35.00 Xe3p_LPM
[21:26:48] [PASSED] 35.03 Xe3p_HPM
[21:26:48] ================= [PASSED] check_media_ip ==================
[21:26:48] =================== check_platform_desc  ===================
[21:26:48] [PASSED] 0x9A60 (TIGERLAKE)
[21:26:48] [PASSED] 0x9A68 (TIGERLAKE)
[21:26:48] [PASSED] 0x9A70 (TIGERLAKE)
[21:26:48] [PASSED] 0x9A40 (TIGERLAKE)
[21:26:48] [PASSED] 0x9A49 (TIGERLAKE)
[21:26:48] [PASSED] 0x9A59 (TIGERLAKE)
[21:26:48] [PASSED] 0x9A78 (TIGERLAKE)
[21:26:48] [PASSED] 0x9AC0 (TIGERLAKE)
[21:26:48] [PASSED] 0x9AC9 (TIGERLAKE)
[21:26:48] [PASSED] 0x9AD9 (TIGERLAKE)
[21:26:48] [PASSED] 0x9AF8 (TIGERLAKE)
[21:26:48] [PASSED] 0x4C80 (ROCKETLAKE)
[21:26:48] [PASSED] 0x4C8A (ROCKETLAKE)
[21:26:48] [PASSED] 0x4C8B (ROCKETLAKE)
[21:26:48] [PASSED] 0x4C8C (ROCKETLAKE)
[21:26:48] [PASSED] 0x4C90 (ROCKETLAKE)
[21:26:48] [PASSED] 0x4C9A (ROCKETLAKE)
[21:26:48] [PASSED] 0x4680 (ALDERLAKE_S)
[21:26:48] [PASSED] 0x4682 (ALDERLAKE_S)
[21:26:48] [PASSED] 0x4688 (ALDERLAKE_S)
[21:26:48] [PASSED] 0x468A (ALDERLAKE_S)
[21:26:48] [PASSED] 0x468B (ALDERLAKE_S)
[21:26:48] [PASSED] 0x4690 (ALDERLAKE_S)
[21:26:48] [PASSED] 0x4692 (ALDERLAKE_S)
[21:26:48] [PASSED] 0x4693 (ALDERLAKE_S)
[21:26:48] [PASSED] 0x46A0 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x46A1 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x46A2 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x46A3 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x46A6 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x46A8 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x46AA (ALDERLAKE_P)
[21:26:48] [PASSED] 0x462A (ALDERLAKE_P)
[21:26:48] [PASSED] 0x4626 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x4628 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x46B0 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x46B1 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x46B2 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x46B3 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x46C0 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x46C1 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x46C2 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x46C3 (ALDERLAKE_P)
[21:26:48] [PASSED] 0x46D0 (ALDERLAKE_N)
[21:26:48] [PASSED] 0x46D1 (ALDERLAKE_N)
[21:26:48] [PASSED] 0x46D2 (ALDERLAKE_N)
[21:26:48] [PASSED] 0x46D3 (ALDERLAKE_N)
[21:26:48] [PASSED] 0x46D4 (ALDERLAKE_N)
[21:26:48] [PASSED] 0xA721 (ALDERLAKE_P)
[21:26:48] [PASSED] 0xA7A1 (ALDERLAKE_P)
[21:26:48] [PASSED] 0xA7A9 (ALDERLAKE_P)
[21:26:48] [PASSED] 0xA7AC (ALDERLAKE_P)
[21:26:48] [PASSED] 0xA7AD (ALDERLAKE_P)
[21:26:48] [PASSED] 0xA720 (ALDERLAKE_P)
[21:26:48] [PASSED] 0xA7A0 (ALDERLAKE_P)
[21:26:48] [PASSED] 0xA7A8 (ALDERLAKE_P)
[21:26:48] [PASSED] 0xA7AA (ALDERLAKE_P)
[21:26:48] [PASSED] 0xA7AB (ALDERLAKE_P)
[21:26:48] [PASSED] 0xA780 (ALDERLAKE_S)
[21:26:48] [PASSED] 0xA781 (ALDERLAKE_S)
[21:26:48] [PASSED] 0xA782 (ALDERLAKE_S)
[21:26:48] [PASSED] 0xA783 (ALDERLAKE_S)
[21:26:48] [PASSED] 0xA788 (ALDERLAKE_S)
[21:26:48] [PASSED] 0xA789 (ALDERLAKE_S)
[21:26:48] [PASSED] 0xA78A (ALDERLAKE_S)
[21:26:48] [PASSED] 0xA78B (ALDERLAKE_S)
[21:26:48] [PASSED] 0x4905 (DG1)
[21:26:48] [PASSED] 0x4906 (DG1)
[21:26:48] [PASSED] 0x4907 (DG1)
[21:26:48] [PASSED] 0x4908 (DG1)
[21:26:48] [PASSED] 0x4909 (DG1)
[21:26:48] [PASSED] 0x56C0 (DG2)
[21:26:48] [PASSED] 0x56C2 (DG2)
[21:26:48] [PASSED] 0x56C1 (DG2)
[21:26:48] [PASSED] 0x7D51 (METEORLAKE)
[21:26:48] [PASSED] 0x7DD1 (METEORLAKE)
[21:26:48] [PASSED] 0x7D41 (METEORLAKE)
[21:26:48] [PASSED] 0x7D67 (METEORLAKE)
[21:26:48] [PASSED] 0xB640 (METEORLAKE)
[21:26:48] [PASSED] 0x56A0 (DG2)
[21:26:48] [PASSED] 0x56A1 (DG2)
[21:26:48] [PASSED] 0x56A2 (DG2)
[21:26:48] [PASSED] 0x56BE (DG2)
[21:26:48] [PASSED] 0x56BF (DG2)
[21:26:48] [PASSED] 0x5690 (DG2)
[21:26:48] [PASSED] 0x5691 (DG2)
[21:26:48] [PASSED] 0x5692 (DG2)
[21:26:48] [PASSED] 0x56A5 (DG2)
[21:26:48] [PASSED] 0x56A6 (DG2)
[21:26:48] [PASSED] 0x56B0 (DG2)
[21:26:48] [PASSED] 0x56B1 (DG2)
[21:26:48] [PASSED] 0x56BA (DG2)
[21:26:48] [PASSED] 0x56BB (DG2)
[21:26:48] [PASSED] 0x56BC (DG2)
[21:26:48] [PASSED] 0x56BD (DG2)
[21:26:48] [PASSED] 0x5693 (DG2)
[21:26:48] [PASSED] 0x5694 (DG2)
[21:26:48] [PASSED] 0x5695 (DG2)
[21:26:48] [PASSED] 0x56A3 (DG2)
[21:26:48] [PASSED] 0x56A4 (DG2)
[21:26:48] [PASSED] 0x56B2 (DG2)
[21:26:48] [PASSED] 0x56B3 (DG2)
[21:26:48] [PASSED] 0x5696 (DG2)
[21:26:48] [PASSED] 0x5697 (DG2)
[21:26:48] [PASSED] 0xB69 (PVC)
[21:26:48] [PASSED] 0xB6E (PVC)
[21:26:48] [PASSED] 0xBD4 (PVC)
[21:26:48] [PASSED] 0xBD5 (PVC)
[21:26:48] [PASSED] 0xBD6 (PVC)
[21:26:48] [PASSED] 0xBD7 (PVC)
[21:26:48] [PASSED] 0xBD8 (PVC)
[21:26:48] [PASSED] 0xBD9 (PVC)
[21:26:48] [PASSED] 0xBDA (PVC)
[21:26:48] [PASSED] 0xBDB (PVC)
[21:26:48] [PASSED] 0xBE0 (PVC)
[21:26:48] [PASSED] 0xBE1 (PVC)
[21:26:48] [PASSED] 0xBE5 (PVC)
[21:26:48] [PASSED] 0x7D40 (METEORLAKE)
[21:26:48] [PASSED] 0x7D45 (METEORLAKE)
[21:26:48] [PASSED] 0x7D55 (METEORLAKE)
[21:26:48] [PASSED] 0x7D60 (METEORLAKE)
[21:26:48] [PASSED] 0x7DD5 (METEORLAKE)
[21:26:48] [PASSED] 0x6420 (LUNARLAKE)
[21:26:48] [PASSED] 0x64A0 (LUNARLAKE)
[21:26:48] [PASSED] 0x64B0 (LUNARLAKE)
[21:26:48] [PASSED] 0xE202 (BATTLEMAGE)
[21:26:48] [PASSED] 0xE209 (BATTLEMAGE)
[21:26:48] [PASSED] 0xE20B (BATTLEMAGE)
[21:26:48] [PASSED] 0xE20C (BATTLEMAGE)
[21:26:48] [PASSED] 0xE20D (BATTLEMAGE)
[21:26:48] [PASSED] 0xE210 (BATTLEMAGE)
[21:26:48] [PASSED] 0xE211 (BATTLEMAGE)
[21:26:48] [PASSED] 0xE212 (BATTLEMAGE)
[21:26:48] [PASSED] 0xE216 (BATTLEMAGE)
[21:26:48] [PASSED] 0xE220 (BATTLEMAGE)
[21:26:48] [PASSED] 0xE221 (BATTLEMAGE)
[21:26:48] [PASSED] 0xE222 (BATTLEMAGE)
[21:26:48] [PASSED] 0xE223 (BATTLEMAGE)
[21:26:48] [PASSED] 0xB080 (PANTHERLAKE)
[21:26:48] [PASSED] 0xB081 (PANTHERLAKE)
[21:26:48] [PASSED] 0xB082 (PANTHERLAKE)
[21:26:48] [PASSED] 0xB083 (PANTHERLAKE)
[21:26:48] [PASSED] 0xB084 (PANTHERLAKE)
[21:26:48] [PASSED] 0xB085 (PANTHERLAKE)
[21:26:48] [PASSED] 0xB086 (PANTHERLAKE)
[21:26:48] [PASSED] 0xB087 (PANTHERLAKE)
[21:26:48] [PASSED] 0xB08F (PANTHERLAKE)
[21:26:48] [PASSED] 0xB090 (PANTHERLAKE)
[21:26:48] [PASSED] 0xB0A0 (PANTHERLAKE)
[21:26:48] [PASSED] 0xB0B0 (PANTHERLAKE)
[21:26:48] [PASSED] 0xFD80 (PANTHERLAKE)
[21:26:48] [PASSED] 0xFD81 (PANTHERLAKE)
[21:26:48] [PASSED] 0xD740 (NOVALAKE_S)
[21:26:48] [PASSED] 0xD741 (NOVALAKE_S)
[21:26:48] [PASSED] 0xD742 (NOVALAKE_S)
[21:26:48] [PASSED] 0xD743 (NOVALAKE_S)
[21:26:48] [PASSED] 0xD744 (NOVALAKE_S)
[21:26:48] [PASSED] 0xD745 (NOVALAKE_S)
[21:26:48] [PASSED] 0x674C (CRESCENTISLAND)
[21:26:48] [PASSED] 0xD750 (NOVALAKE_P)
[21:26:48] [PASSED] 0xD751 (NOVALAKE_P)
[21:26:48] [PASSED] 0xD752 (NOVALAKE_P)
[21:26:48] [PASSED] 0xD753 (NOVALAKE_P)
[21:26:48] [PASSED] 0xD754 (NOVALAKE_P)
[21:26:48] [PASSED] 0xD755 (NOVALAKE_P)
[21:26:48] [PASSED] 0xD756 (NOVALAKE_P)
[21:26:48] [PASSED] 0xD757 (NOVALAKE_P)
[21:26:48] [PASSED] 0xD75F (NOVALAKE_P)
[21:26:48] =============== [PASSED] check_platform_desc ===============
[21:26:48] ===================== [PASSED] xe_pci ======================
[21:26:48] =================== xe_rtp (2 subtests) ====================
[21:26:48] =============== xe_rtp_process_to_sr_tests  ================
[21:26:48] [PASSED] coalesce-same-reg
[21:26:48] [PASSED] no-match-no-add
[21:26:48] [PASSED] match-or
[21:26:48] [PASSED] match-or-xfail
[21:26:48] [PASSED] no-match-no-add-multiple-rules
[21:26:48] [PASSED] two-regs-two-entries
[21:26:48] [PASSED] clr-one-set-other
[21:26:48] [PASSED] set-field
[21:26:48] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[21:26:48] [PASSED] conflict-not-disjoint
[21:26:48] [PASSED] conflict-reg-type
[21:26:48] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:26:48] ================== xe_rtp_process_tests  ===================
[21:26:48] [PASSED] active1
[21:26:48] [PASSED] active2
[21:26:48] [PASSED] active-inactive
[21:26:48] [PASSED] inactive-active
[21:26:48] [PASSED] inactive-1st_or_active-inactive
[21:26:48] [PASSED] inactive-2nd_or_active-inactive
[21:26:48] [PASSED] inactive-last_or_active-inactive
[21:26:48] [PASSED] inactive-no_or_active-inactive
[21:26:48] ============== [PASSED] xe_rtp_process_tests ===============
[21:26:48] ===================== [PASSED] xe_rtp ======================
[21:26:48] ==================== xe_wa (1 subtest) =====================
[21:26:48] ======================== xe_wa_gt  =========================
[21:26:48] [PASSED] TIGERLAKE B0
[21:26:48] [PASSED] DG1 A0
[21:26:48] [PASSED] DG1 B0
[21:26:48] [PASSED] ALDERLAKE_S A0
[21:26:48] [PASSED] ALDERLAKE_S B0
[21:26:48] [PASSED] ALDERLAKE_S C0
[21:26:48] [PASSED] ALDERLAKE_S D0
[21:26:48] [PASSED] ALDERLAKE_P A0
[21:26:48] [PASSED] ALDERLAKE_P B0
[21:26:48] [PASSED] ALDERLAKE_P C0
[21:26:48] [PASSED] ALDERLAKE_S RPLS D0
[21:26:48] [PASSED] ALDERLAKE_P RPLU E0
[21:26:48] [PASSED] DG2 G10 C0
[21:26:48] [PASSED] DG2 G11 B1
[21:26:48] [PASSED] DG2 G12 A1
[21:26:48] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:26:48] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:26:48] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[21:26:48] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[21:26:48] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[21:26:48] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[21:26:48] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[21:26:48] ==================== [PASSED] xe_wa_gt =====================
[21:26:48] ====================== [PASSED] xe_wa ======================
[21:26:48] ============================================================
[21:26:48] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[21:26:48] Elapsed time: 43.231s total, 4.306s configuring, 38.256s building, 0.620s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:26:48] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:26:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[21:27:19] Starting KUnit Kernel (1/1)...
[21:27:19] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:27:19] ============ drm_test_pick_cmdline (2 subtests) ============
[21:27:19] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[21:27:19] =============== drm_test_pick_cmdline_named  ===============
[21:27:19] [PASSED] NTSC
[21:27:19] [PASSED] NTSC-J
[21:27:19] [PASSED] PAL
[21:27:19] [PASSED] PAL-M
[21:27:19] =========== [PASSED] drm_test_pick_cmdline_named ===========
[21:27:19] ============== [PASSED] drm_test_pick_cmdline ==============
[21:27:19] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:27:19] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:27:19] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:27:19] =========== drm_validate_clone_mode (2 subtests) ===========
[21:27:19] ============== drm_test_check_in_clone_mode  ===============
[21:27:19] [PASSED] in_clone_mode
[21:27:19] [PASSED] not_in_clone_mode
[21:27:19] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:27:19] =============== drm_test_check_valid_clones  ===============
[21:27:19] [PASSED] not_in_clone_mode
[21:27:19] [PASSED] valid_clone
[21:27:19] [PASSED] invalid_clone
[21:27:19] =========== [PASSED] drm_test_check_valid_clones ===========
[21:27:19] ============= [PASSED] drm_validate_clone_mode =============
[21:27:19] ============= drm_validate_modeset (1 subtest) =============
[21:27:19] [PASSED] drm_test_check_connector_changed_modeset
[21:27:19] ============== [PASSED] drm_validate_modeset ===============
[21:27:19] ====== drm_test_bridge_get_current_state (2 subtests) ======
[21:27:19] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:27:19] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[21:27:19] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:27:19] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:27:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:27:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:27:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[21:27:19] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:27:19] ============== drm_bridge_alloc (2 subtests) ===============
[21:27:19] [PASSED] drm_test_drm_bridge_alloc_basic
[21:27:19] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:27:19] ================ [PASSED] drm_bridge_alloc =================
[21:27:19] ============= drm_cmdline_parser (40 subtests) =============
[21:27:19] [PASSED] drm_test_cmdline_force_d_only
[21:27:19] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:27:19] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:27:19] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:27:19] [PASSED] drm_test_cmdline_force_e_only
[21:27:19] [PASSED] drm_test_cmdline_res
[21:27:19] [PASSED] drm_test_cmdline_res_vesa
[21:27:19] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:27:19] [PASSED] drm_test_cmdline_res_rblank
[21:27:19] [PASSED] drm_test_cmdline_res_bpp
[21:27:19] [PASSED] drm_test_cmdline_res_refresh
[21:27:19] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:27:19] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:27:19] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:27:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:27:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:27:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:27:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:27:19] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:27:19] [PASSED] drm_test_cmdline_res_margins_force_on
[21:27:19] [PASSED] drm_test_cmdline_res_vesa_margins
[21:27:19] [PASSED] drm_test_cmdline_name
[21:27:19] [PASSED] drm_test_cmdline_name_bpp
[21:27:19] [PASSED] drm_test_cmdline_name_option
[21:27:19] [PASSED] drm_test_cmdline_name_bpp_option
[21:27:19] [PASSED] drm_test_cmdline_rotate_0
[21:27:19] [PASSED] drm_test_cmdline_rotate_90
[21:27:19] [PASSED] drm_test_cmdline_rotate_180
[21:27:19] [PASSED] drm_test_cmdline_rotate_270
[21:27:19] [PASSED] drm_test_cmdline_hmirror
[21:27:19] [PASSED] drm_test_cmdline_vmirror
[21:27:19] [PASSED] drm_test_cmdline_margin_options
[21:27:19] [PASSED] drm_test_cmdline_multiple_options
[21:27:19] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:27:19] [PASSED] drm_test_cmdline_extra_and_option
[21:27:19] [PASSED] drm_test_cmdline_freestanding_options
[21:27:19] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:27:19] [PASSED] drm_test_cmdline_panel_orientation
[21:27:19] ================ drm_test_cmdline_invalid  =================
[21:27:19] [PASSED] margin_only
[21:27:19] [PASSED] interlace_only
[21:27:19] [PASSED] res_missing_x
[21:27:19] [PASSED] res_missing_y
[21:27:19] [PASSED] res_bad_y
[21:27:19] [PASSED] res_missing_y_bpp
[21:27:19] [PASSED] res_bad_bpp
[21:27:19] [PASSED] res_bad_refresh
[21:27:19] [PASSED] res_bpp_refresh_force_on_off
[21:27:19] [PASSED] res_invalid_mode
[21:27:19] [PASSED] res_bpp_wrong_place_mode
[21:27:19] [PASSED] name_bpp_refresh
[21:27:19] [PASSED] name_refresh
[21:27:19] [PASSED] name_refresh_wrong_mode
[21:27:19] [PASSED] name_refresh_invalid_mode
[21:27:19] [PASSED] rotate_multiple
[21:27:19] [PASSED] rotate_invalid_val
[21:27:19] [PASSED] rotate_truncated
[21:27:19] [PASSED] invalid_option
[21:27:19] [PASSED] invalid_tv_option
[21:27:19] [PASSED] truncated_tv_option
[21:27:19] ============ [PASSED] drm_test_cmdline_invalid =============
[21:27:19] =============== drm_test_cmdline_tv_options  ===============
[21:27:19] [PASSED] NTSC
[21:27:19] [PASSED] NTSC_443
[21:27:19] [PASSED] NTSC_J
[21:27:19] [PASSED] PAL
[21:27:19] [PASSED] PAL_M
[21:27:19] [PASSED] PAL_N
[21:27:19] [PASSED] SECAM
[21:27:19] [PASSED] MONO_525
[21:27:19] [PASSED] MONO_625
[21:27:19] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:27:19] =============== [PASSED] drm_cmdline_parser ================
[21:27:19] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:27:19] [PASSED] drm_test_connector_hdmi_init_valid
[21:27:19] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:27:19] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:27:19] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:27:19] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:27:19] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:27:19] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:27:19] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:27:19] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[21:27:19] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:27:19] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:27:19] [PASSED] supported_formats=0x5 yuv420_allowed=1
[21:27:19] [PASSED] supported_formats=0x5 yuv420_allowed=0
[21:27:19] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:27:19] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:27:19] [PASSED] drm_test_connector_hdmi_init_null_product
[21:27:19] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:27:19] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:27:19] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:27:19] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:27:19] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:27:19] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:27:19] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:27:19] ========= drm_test_connector_hdmi_init_type_valid  =========
[21:27:19] [PASSED] HDMI-A
[21:27:19] [PASSED] HDMI-B
[21:27:19] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:27:19] ======== drm_test_connector_hdmi_init_type_invalid  ========
[21:27:19] [PASSED] Unknown
[21:27:19] [PASSED] VGA
[21:27:19] [PASSED] DVI-I
[21:27:19] [PASSED] DVI-D
[21:27:19] [PASSED] DVI-A
[21:27:19] [PASSED] Composite
[21:27:19] [PASSED] SVIDEO
[21:27:19] [PASSED] LVDS
[21:27:19] [PASSED] Component
[21:27:19] [PASSED] DIN
[21:27:19] [PASSED] DP
[21:27:19] [PASSED] TV
[21:27:19] [PASSED] eDP
[21:27:19] [PASSED] Virtual
[21:27:19] [PASSED] DSI
[21:27:19] [PASSED] DPI
[21:27:19] [PASSED] Writeback
[21:27:19] [PASSED] SPI
[21:27:19] [PASSED] USB
[21:27:19] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:27:19] ============ [PASSED] drmm_connector_hdmi_init =============
[21:27:19] ============= drmm_connector_init (3 subtests) =============
[21:27:19] [PASSED] drm_test_drmm_connector_init
[21:27:19] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:27:19] ========= drm_test_drmm_connector_init_type_valid  =========
[21:27:19] [PASSED] Unknown
[21:27:19] [PASSED] VGA
[21:27:19] [PASSED] DVI-I
[21:27:19] [PASSED] DVI-D
[21:27:19] [PASSED] DVI-A
[21:27:19] [PASSED] Composite
[21:27:19] [PASSED] SVIDEO
[21:27:19] [PASSED] LVDS
[21:27:19] [PASSED] Component
[21:27:19] [PASSED] DIN
[21:27:19] [PASSED] DP
[21:27:19] [PASSED] HDMI-A
[21:27:19] [PASSED] HDMI-B
[21:27:19] [PASSED] TV
[21:27:19] [PASSED] eDP
[21:27:19] [PASSED] Virtual
[21:27:19] [PASSED] DSI
[21:27:19] [PASSED] DPI
[21:27:19] [PASSED] Writeback
[21:27:19] [PASSED] SPI
[21:27:19] [PASSED] USB
[21:27:19] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:27:19] =============== [PASSED] drmm_connector_init ===============
[21:27:19] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:27:19] [PASSED] drm_test_drm_connector_dynamic_init
[21:27:19] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:27:19] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:27:19] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:27:19] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[21:27:19] [PASSED] Unknown
[21:27:19] [PASSED] VGA
[21:27:19] [PASSED] DVI-I
[21:27:19] [PASSED] DVI-D
[21:27:19] [PASSED] DVI-A
[21:27:19] [PASSED] Composite
[21:27:19] [PASSED] SVIDEO
[21:27:19] [PASSED] LVDS
[21:27:19] [PASSED] Component
[21:27:19] [PASSED] DIN
[21:27:19] [PASSED] DP
[21:27:19] [PASSED] HDMI-A
[21:27:19] [PASSED] HDMI-B
[21:27:19] [PASSED] TV
[21:27:19] [PASSED] eDP
[21:27:19] [PASSED] Virtual
[21:27:19] [PASSED] DSI
[21:27:19] [PASSED] DPI
[21:27:19] [PASSED] Writeback
[21:27:19] [PASSED] SPI
[21:27:19] [PASSED] USB
[21:27:19] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:27:19] ======== drm_test_drm_connector_dynamic_init_name  =========
[21:27:19] [PASSED] Unknown
[21:27:19] [PASSED] VGA
[21:27:19] [PASSED] DVI-I
[21:27:19] [PASSED] DVI-D
[21:27:19] [PASSED] DVI-A
[21:27:19] [PASSED] Composite
[21:27:19] [PASSED] SVIDEO
[21:27:19] [PASSED] LVDS
[21:27:19] [PASSED] Component
[21:27:19] [PASSED] DIN
[21:27:19] [PASSED] DP
[21:27:19] [PASSED] HDMI-A
[21:27:19] [PASSED] HDMI-B
[21:27:19] [PASSED] TV
[21:27:19] [PASSED] eDP
[21:27:19] [PASSED] Virtual
[21:27:19] [PASSED] DSI
[21:27:19] [PASSED] DPI
[21:27:19] [PASSED] Writeback
[21:27:19] [PASSED] SPI
[21:27:19] [PASSED] USB
[21:27:19] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:27:19] =========== [PASSED] drm_connector_dynamic_init ============
[21:27:19] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:27:19] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:27:19] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:27:19] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:27:19] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:27:19] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:27:19] ======= drm_connector_dynamic_register (7 subtests) ========
[21:27:19] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:27:19] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:27:19] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:27:19] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:27:19] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:27:19] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:27:19] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:27:19] ========= [PASSED] drm_connector_dynamic_register ==========
[21:27:19] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:27:19] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:27:19] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:27:19] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:27:19] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:27:19] ========== drm_test_get_tv_mode_from_name_valid  ===========
[21:27:19] [PASSED] NTSC
[21:27:19] [PASSED] NTSC-443
[21:27:19] [PASSED] NTSC-J
[21:27:19] [PASSED] PAL
[21:27:19] [PASSED] PAL-M
[21:27:19] [PASSED] PAL-N
[21:27:19] [PASSED] SECAM
[21:27:19] [PASSED] Mono
[21:27:19] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:27:19] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:27:19] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:27:19] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:27:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:27:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:27:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:27:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:27:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:27:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:27:19] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[21:27:19] [PASSED] VIC 96
[21:27:19] [PASSED] VIC 97
[21:27:19] [PASSED] VIC 101
[21:27:19] [PASSED] VIC 102
[21:27:19] [PASSED] VIC 106
[21:27:19] [PASSED] VIC 107
[21:27:19] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:27:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:27:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:27:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:27:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:27:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:27:19] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:27:19] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:27:19] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[21:27:19] [PASSED] Automatic
[21:27:19] [PASSED] Full
[21:27:19] [PASSED] Limited 16:235
[21:27:19] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:27:19] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:27:19] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:27:19] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:27:19] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[21:27:19] [PASSED] RGB
[21:27:19] [PASSED] YUV 4:2:0
[21:27:19] [PASSED] YUV 4:2:2
[21:27:19] [PASSED] YUV 4:4:4
[21:27:19] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:27:19] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:27:19] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:27:19] ============= drm_damage_helper (21 subtests) ==============
[21:27:19] [PASSED] drm_test_damage_iter_no_damage
[21:27:19] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:27:19] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:27:19] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:27:19] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:27:19] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:27:19] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:27:19] [PASSED] drm_test_damage_iter_simple_damage
[21:27:19] [PASSED] drm_test_damage_iter_single_damage
[21:27:19] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:27:19] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:27:19] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:27:19] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:27:19] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:27:19] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:27:19] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:27:19] [PASSED] drm_test_damage_iter_damage
[21:27:19] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:27:19] [PASSED] drm_test_damage_iter_damage_one_outside
[21:27:19] [PASSED] drm_test_damage_iter_damage_src_moved
[21:27:19] [PASSED] drm_test_damage_iter_damage_not_visible
[21:27:19] ================ [PASSED] drm_damage_helper ================
[21:27:19] ============== drm_dp_mst_helper (3 subtests) ==============
[21:27:19] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[21:27:19] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:27:19] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:27:19] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:27:19] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:27:19] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:27:19] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:27:19] ============== drm_test_dp_mst_calc_pbn_div  ===============
[21:27:19] [PASSED] Link rate 2000000 lane count 4
[21:27:19] [PASSED] Link rate 2000000 lane count 2
[21:27:19] [PASSED] Link rate 2000000 lane count 1
[21:27:19] [PASSED] Link rate 1350000 lane count 4
[21:27:19] [PASSED] Link rate 1350000 lane count 2
[21:27:19] [PASSED] Link rate 1350000 lane count 1
[21:27:19] [PASSED] Link rate 1000000 lane count 4
[21:27:19] [PASSED] Link rate 1000000 lane count 2
[21:27:19] [PASSED] Link rate 1000000 lane count 1
[21:27:19] [PASSED] Link rate 810000 lane count 4
[21:27:19] [PASSED] Link rate 810000 lane count 2
[21:27:19] [PASSED] Link rate 810000 lane count 1
[21:27:19] [PASSED] Link rate 540000 lane count 4
[21:27:19] [PASSED] Link rate 540000 lane count 2
[21:27:19] [PASSED] Link rate 540000 lane count 1
[21:27:19] [PASSED] Link rate 270000 lane count 4
[21:27:19] [PASSED] Link rate 270000 lane count 2
[21:27:19] [PASSED] Link rate 270000 lane count 1
[21:27:19] [PASSED] Link rate 162000 lane count 4
[21:27:19] [PASSED] Link rate 162000 lane count 2
[21:27:19] [PASSED] Link rate 162000 lane count 1
[21:27:19] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:27:19] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[21:27:19] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:27:19] [PASSED] DP_POWER_UP_PHY with port number
[21:27:19] [PASSED] DP_POWER_DOWN_PHY with port number
[21:27:19] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:27:19] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:27:19] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:27:19] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:27:19] [PASSED] DP_QUERY_PAYLOAD with port number
[21:27:19] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:27:19] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:27:19] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:27:19] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:27:19] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:27:19] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:27:19] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:27:19] [PASSED] DP_REMOTE_I2C_READ with port number
[21:27:19] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:27:19] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:27:19] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:27:19] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:27:19] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:27:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:27:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:27:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:27:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:27:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:27:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:27:19] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:27:19] ================ [PASSED] drm_dp_mst_helper ================
[21:27:19] ================== drm_exec (7 subtests) ===================
[21:27:19] [PASSED] sanitycheck
[21:27:19] [PASSED] test_lock
[21:27:19] [PASSED] test_lock_unlock
[21:27:19] [PASSED] test_duplicates
[21:27:19] [PASSED] test_prepare
[21:27:19] [PASSED] test_prepare_array
[21:27:19] [PASSED] test_multiple_loops
[21:27:19] ==================== [PASSED] drm_exec =====================
[21:27:19] =========== drm_format_helper_test (17 subtests) ===========
[21:27:19] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[21:27:19] [PASSED] single_pixel_source_buffer
[21:27:19] [PASSED] single_pixel_clip_rectangle
[21:27:19] [PASSED] well_known_colors
[21:27:19] [PASSED] destination_pitch
[21:27:19] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:27:19] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[21:27:19] [PASSED] single_pixel_source_buffer
[21:27:19] [PASSED] single_pixel_clip_rectangle
[21:27:19] [PASSED] well_known_colors
[21:27:19] [PASSED] destination_pitch
[21:27:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:27:19] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[21:27:19] [PASSED] single_pixel_source_buffer
[21:27:19] [PASSED] single_pixel_clip_rectangle
[21:27:19] [PASSED] well_known_colors
[21:27:19] [PASSED] destination_pitch
[21:27:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:27:19] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[21:27:19] [PASSED] single_pixel_source_buffer
[21:27:19] [PASSED] single_pixel_clip_rectangle
[21:27:19] [PASSED] well_known_colors
[21:27:19] [PASSED] destination_pitch
[21:27:19] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:27:19] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[21:27:19] [PASSED] single_pixel_source_buffer
[21:27:19] [PASSED] single_pixel_clip_rectangle
[21:27:19] [PASSED] well_known_colors
[21:27:19] [PASSED] destination_pitch
[21:27:19] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:27:19] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[21:27:19] [PASSED] single_pixel_source_buffer
[21:27:19] [PASSED] single_pixel_clip_rectangle
[21:27:19] [PASSED] well_known_colors
[21:27:19] [PASSED] destination_pitch
[21:27:19] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:27:19] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[21:27:19] [PASSED] single_pixel_source_buffer
[21:27:19] [PASSED] single_pixel_clip_rectangle
[21:27:19] [PASSED] well_known_colors
[21:27:19] [PASSED] destination_pitch
[21:27:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:27:19] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[21:27:19] [PASSED] single_pixel_source_buffer
[21:27:19] [PASSED] single_pixel_clip_rectangle
[21:27:19] [PASSED] well_known_colors
[21:27:19] [PASSED] destination_pitch
[21:27:19] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:27:19] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[21:27:19] [PASSED] single_pixel_source_buffer
[21:27:19] [PASSED] single_pixel_clip_rectangle
[21:27:19] [PASSED] well_known_colors
[21:27:19] [PASSED] destination_pitch
[21:27:19] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:27:19] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[21:27:19] [PASSED] single_pixel_source_buffer
[21:27:19] [PASSED] single_pixel_clip_rectangle
[21:27:19] [PASSED] well_known_colors
[21:27:19] [PASSED] destination_pitch
[21:27:19] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:27:19] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[21:27:19] [PASSED] single_pixel_source_buffer
[21:27:19] [PASSED] single_pixel_clip_rectangle
[21:27:19] [PASSED] well_known_colors
[21:27:19] [PASSED] destination_pitch
[21:27:19] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:27:19] ============== drm_test_fb_xrgb8888_to_mono  ===============
[21:27:19] [PASSED] single_pixel_source_buffer
[21:27:19] [PASSED] single_pixel_clip_rectangle
[21:27:19] [PASSED] well_known_colors
[21:27:19] [PASSED] destination_pitch
[21:27:19] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:27:19] ==================== drm_test_fb_swab  =====================
[21:27:19] [PASSED] single_pixel_source_buffer
[21:27:19] [PASSED] single_pixel_clip_rectangle
[21:27:19] [PASSED] well_known_colors
[21:27:19] [PASSED] destination_pitch
[21:27:19] ================ [PASSED] drm_test_fb_swab =================
[21:27:19] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[21:27:19] [PASSED] single_pixel_source_buffer
[21:27:19] [PASSED] single_pixel_clip_rectangle
[21:27:19] [PASSED] well_known_colors
[21:27:19] [PASSED] destination_pitch
[21:27:19] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:27:19] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[21:27:19] [PASSED] single_pixel_source_buffer
[21:27:19] [PASSED] single_pixel_clip_rectangle
[21:27:19] [PASSED] well_known_colors
[21:27:19] [PASSED] destination_pitch
[21:27:19] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:27:19] ================= drm_test_fb_clip_offset  =================
[21:27:19] [PASSED] pass through
[21:27:19] [PASSED] horizontal offset
[21:27:19] [PASSED] vertical offset
[21:27:19] [PASSED] horizontal and vertical offset
[21:27:19] [PASSED] horizontal offset (custom pitch)
[21:27:19] [PASSED] vertical offset (custom pitch)
[21:27:19] [PASSED] horizontal and vertical offset (custom pitch)
[21:27:19] ============= [PASSED] drm_test_fb_clip_offset =============
[21:27:19] =================== drm_test_fb_memcpy  ====================
[21:27:19] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:27:19] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:27:19] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:27:19] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:27:19] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:27:19] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:27:19] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:27:19] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:27:19] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:27:19] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:27:19] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:27:19] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:27:19] =============== [PASSED] drm_test_fb_memcpy ================
[21:27:19] ============= [PASSED] drm_format_helper_test ==============
[21:27:19] ================= drm_format (18 subtests) =================
[21:27:19] [PASSED] drm_test_format_block_width_invalid
[21:27:19] [PASSED] drm_test_format_block_width_one_plane
[21:27:19] [PASSED] drm_test_format_block_width_two_plane
[21:27:19] [PASSED] drm_test_format_block_width_three_plane
[21:27:19] [PASSED] drm_test_format_block_width_tiled
[21:27:19] [PASSED] drm_test_format_block_height_invalid
[21:27:19] [PASSED] drm_test_format_block_height_one_plane
[21:27:19] [PASSED] drm_test_format_block_height_two_plane
[21:27:19] [PASSED] drm_test_format_block_height_three_plane
[21:27:19] [PASSED] drm_test_format_block_height_tiled
[21:27:19] [PASSED] drm_test_format_min_pitch_invalid
[21:27:19] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:27:19] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:27:19] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:27:19] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:27:19] [PASSED] drm_test_format_min_pitch_two_plane
[21:27:19] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:27:19] [PASSED] drm_test_format_min_pitch_tiled
[21:27:19] =================== [PASSED] drm_format ====================
[21:27:19] ============== drm_framebuffer (10 subtests) ===============
[21:27:19] ========== drm_test_framebuffer_check_src_coords  ==========
[21:27:19] [PASSED] Success: source fits into fb
[21:27:19] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:27:19] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:27:19] [PASSED] Fail: overflowing fb with source width
[21:27:19] [PASSED] Fail: overflowing fb with source height
[21:27:19] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:27:19] [PASSED] drm_test_framebuffer_cleanup
[21:27:19] =============== drm_test_framebuffer_create  ===============
[21:27:19] [PASSED] ABGR8888 normal sizes
[21:27:19] [PASSED] ABGR8888 max sizes
[21:27:19] [PASSED] ABGR8888 pitch greater than min required
[21:27:19] [PASSED] ABGR8888 pitch less than min required
[21:27:19] [PASSED] ABGR8888 Invalid width
[21:27:19] [PASSED] ABGR8888 Invalid buffer handle
[21:27:19] [PASSED] No pixel format
[21:27:19] [PASSED] ABGR8888 Width 0
[21:27:19] [PASSED] ABGR8888 Height 0
[21:27:19] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:27:19] [PASSED] ABGR8888 Large buffer offset
[21:27:19] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:27:19] [PASSED] ABGR8888 Invalid flag
[21:27:19] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:27:19] [PASSED] ABGR8888 Valid buffer modifier
[21:27:19] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:27:19] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:27:19] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:27:19] [PASSED] NV12 Normal sizes
[21:27:19] [PASSED] NV12 Max sizes
[21:27:19] [PASSED] NV12 Invalid pitch
[21:27:19] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:27:19] [PASSED] NV12 different  modifier per-plane
[21:27:19] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:27:19] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:27:19] [PASSED] NV12 Modifier for inexistent plane
[21:27:19] [PASSED] NV12 Handle for inexistent plane
[21:27:19] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:27:19] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:27:19] [PASSED] YVU420 Normal sizes
[21:27:19] [PASSED] YVU420 Max sizes
[21:27:19] [PASSED] YVU420 Invalid pitch
[21:27:19] [PASSED] YVU420 Different pitches
[21:27:19] [PASSED] YVU420 Different buffer offsets/pitches
[21:27:19] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:27:19] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:27:19] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:27:19] [PASSED] YVU420 Valid modifier
[21:27:19] [PASSED] YVU420 Different modifiers per plane
[21:27:19] [PASSED] YVU420 Modifier for inexistent plane
[21:27:19] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:27:19] [PASSED] X0L2 Normal sizes
[21:27:19] [PASSED] X0L2 Max sizes
[21:27:19] [PASSED] X0L2 Invalid pitch
[21:27:19] [PASSED] X0L2 Pitch greater than minimum required
[21:27:19] [PASSED] X0L2 Handle for inexistent plane
[21:27:19] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:27:19] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:27:19] [PASSED] X0L2 Valid modifier
[21:27:19] [PASSED] X0L2 Modifier for inexistent plane
[21:27:19] =========== [PASSED] drm_test_framebuffer_create ===========
[21:27:19] [PASSED] drm_test_framebuffer_free
[21:27:19] [PASSED] drm_test_framebuffer_init
[21:27:19] [PASSED] drm_test_framebuffer_init_bad_format
[21:27:19] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:27:19] [PASSED] drm_test_framebuffer_lookup
[21:27:19] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:27:19] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:27:19] ================= [PASSED] drm_framebuffer =================
[21:27:19] ================ drm_gem_shmem (8 subtests) ================
[21:27:19] [PASSED] drm_gem_shmem_test_obj_create
[21:27:19] [PASSED] drm_gem_shmem_test_obj_create_private
[21:27:19] [PASSED] drm_gem_shmem_test_pin_pages
[21:27:19] [PASSED] drm_gem_shmem_test_vmap
[21:27:19] [PASSED] drm_gem_shmem_test_get_sg_table
[21:27:19] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:27:19] [PASSED] drm_gem_shmem_test_madvise
[21:27:19] [PASSED] drm_gem_shmem_test_purge
[21:27:19] ================== [PASSED] drm_gem_shmem ==================
[21:27:19] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[21:27:19] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:27:19] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:27:19] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:27:19] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:27:19] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:27:19] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:27:19] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[21:27:19] [PASSED] Automatic
[21:27:19] [PASSED] Full
[21:27:19] [PASSED] Limited 16:235
[21:27:19] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:27:19] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:27:19] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:27:19] [PASSED] drm_test_check_disable_connector
[21:27:19] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:27:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:27:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:27:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:27:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:27:19] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:27:19] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:27:19] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:27:19] [PASSED] drm_test_check_output_bpc_dvi
[21:27:19] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:27:19] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:27:19] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:27:19] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:27:19] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:27:19] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:27:19] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:27:19] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:27:19] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:27:19] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:27:19] [PASSED] drm_test_check_broadcast_rgb_value
[21:27:19] [PASSED] drm_test_check_bpc_8_value
[21:27:19] [PASSED] drm_test_check_bpc_10_value
[21:27:19] [PASSED] drm_test_check_bpc_12_value
[21:27:19] [PASSED] drm_test_check_format_value
[21:27:19] [PASSED] drm_test_check_tmds_char_value
[21:27:19] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:27:19] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[21:27:19] [PASSED] drm_test_check_mode_valid
[21:27:19] [PASSED] drm_test_check_mode_valid_reject
[21:27:19] [PASSED] drm_test_check_mode_valid_reject_rate
[21:27:19] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:27:19] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:27:19] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[21:27:19] [PASSED] drm_test_check_infoframes
[21:27:19] [PASSED] drm_test_check_reject_avi_infoframe
[21:27:19] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[21:27:19] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[21:27:19] [PASSED] drm_test_check_reject_audio_infoframe
[21:27:19] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[21:27:19] ================= drm_managed (2 subtests) =================
[21:27:19] [PASSED] drm_test_managed_release_action
[21:27:19] [PASSED] drm_test_managed_run_action
[21:27:19] =================== [PASSED] drm_managed ===================
[21:27:19] =================== drm_mm (6 subtests) ====================
[21:27:19] [PASSED] drm_test_mm_init
[21:27:19] [PASSED] drm_test_mm_debug
[21:27:19] [PASSED] drm_test_mm_align32
[21:27:19] [PASSED] drm_test_mm_align64
[21:27:19] [PASSED] drm_test_mm_lowest
[21:27:19] [PASSED] drm_test_mm_highest
[21:27:19] ===================== [PASSED] drm_mm ======================
[21:27:19] ============= drm_modes_analog_tv (5 subtests) =============
[21:27:19] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:27:19] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:27:19] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:27:19] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:27:19] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:27:19] =============== [PASSED] drm_modes_analog_tv ===============
[21:27:19] ============== drm_plane_helper (2 subtests) ===============
[21:27:19] =============== drm_test_check_plane_state  ================
[21:27:19] [PASSED] clipping_simple
[21:27:19] [PASSED] clipping_rotate_reflect
[21:27:19] [PASSED] positioning_simple
[21:27:19] [PASSED] upscaling
[21:27:19] [PASSED] downscaling
[21:27:19] [PASSED] rounding1
[21:27:19] [PASSED] rounding2
[21:27:19] [PASSED] rounding3
[21:27:19] [PASSED] rounding4
[21:27:19] =========== [PASSED] drm_test_check_plane_state ============
[21:27:19] =========== drm_test_check_invalid_plane_state  ============
[21:27:19] [PASSED] positioning_invalid
[21:27:19] [PASSED] upscaling_invalid
[21:27:19] [PASSED] downscaling_invalid
[21:27:19] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:27:19] ================ [PASSED] drm_plane_helper =================
[21:27:19] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:27:19] ====== drm_test_connector_helper_tv_get_modes_check  =======
[21:27:19] [PASSED] None
[21:27:19] [PASSED] PAL
[21:27:19] [PASSED] NTSC
[21:27:19] [PASSED] Both, NTSC Default
[21:27:19] [PASSED] Both, PAL Default
[21:27:19] [PASSED] Both, NTSC Default, with PAL on command-line
[21:27:19] [PASSED] Both, PAL Default, with NTSC on command-line
[21:27:19] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:27:19] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:27:19] ================== drm_rect (9 subtests) ===================
[21:27:19] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:27:19] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:27:19] [PASSED] drm_test_rect_clip_scaled_clipped
[21:27:19] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:27:19] ================= drm_test_rect_intersect  =================
[21:27:19] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:27:19] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:27:19] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:27:19] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:27:19] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:27:19] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:27:19] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:27:19] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:27:19] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:27:19] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:27:19] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:27:19] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:27:19] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:27:19] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:27:19] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[21:27:19] ============= [PASSED] drm_test_rect_intersect =============
[21:27:19] ================ drm_test_rect_calc_hscale  ================
[21:27:19] [PASSED] normal use
[21:27:19] [PASSED] out of max range
[21:27:19] [PASSED] out of min range
[21:27:19] [PASSED] zero dst
[21:27:19] [PASSED] negative src
[21:27:19] [PASSED] negative dst
[21:27:19] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:27:19] ================ drm_test_rect_calc_vscale  ================
[21:27:19] [PASSED] normal use
[21:27:19] [PASSED] out of max range
[21:27:19] [PASSED] out of min range
[21:27:19] [PASSED] zero dst
[21:27:19] [PASSED] negative src
[21:27:19] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[21:27:19] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:27:19] ================== drm_test_rect_rotate  ===================
[21:27:19] [PASSED] reflect-x
[21:27:19] [PASSED] reflect-y
[21:27:19] [PASSED] rotate-0
[21:27:19] [PASSED] rotate-90
[21:27:19] [PASSED] rotate-180
[21:27:19] [PASSED] rotate-270
[21:27:19] ============== [PASSED] drm_test_rect_rotate ===============
[21:27:19] ================ drm_test_rect_rotate_inv  =================
[21:27:19] [PASSED] reflect-x
[21:27:19] [PASSED] reflect-y
[21:27:19] [PASSED] rotate-0
[21:27:19] [PASSED] rotate-90
[21:27:19] [PASSED] rotate-180
[21:27:19] [PASSED] rotate-270
[21:27:19] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:27:19] ==================== [PASSED] drm_rect =====================
[21:27:19] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:27:19] ============ drm_test_sysfb_build_fourcc_list  =============
[21:27:19] [PASSED] no native formats
[21:27:19] [PASSED] XRGB8888 as native format
[21:27:19] [PASSED] remove duplicates
[21:27:19] [PASSED] convert alpha formats
[21:27:19] [PASSED] random formats
[21:27:19] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:27:19] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:27:19] ================== drm_fixp (2 subtests) ===================
[21:27:19] [PASSED] drm_test_int2fixp
[21:27:19] [PASSED] drm_test_sm2fixp
[21:27:19] ==================== [PASSED] drm_fixp =====================
[21:27:19] ============================================================
[21:27:19] Testing complete. Ran 621 tests: passed: 621
[21:27:19] Elapsed time: 30.931s total, 1.653s configuring, 29.062s building, 0.179s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:27:19] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:27:21] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[21:27:30] Starting KUnit Kernel (1/1)...
[21:27:30] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:27:30] ================= ttm_device (5 subtests) ==================
[21:27:30] [PASSED] ttm_device_init_basic
[21:27:30] [PASSED] ttm_device_init_multiple
[21:27:30] [PASSED] ttm_device_fini_basic
[21:27:30] [PASSED] ttm_device_init_no_vma_man
[21:27:30] ================== ttm_device_init_pools  ==================
[21:27:30] [PASSED] No DMA allocations, no DMA32 required
[21:27:30] [PASSED] DMA allocations, DMA32 required
[21:27:30] [PASSED] No DMA allocations, DMA32 required
[21:27:30] [PASSED] DMA allocations, no DMA32 required
[21:27:30] ============== [PASSED] ttm_device_init_pools ==============
[21:27:30] =================== [PASSED] ttm_device ====================
[21:27:30] ================== ttm_pool (8 subtests) ===================
[21:27:30] ================== ttm_pool_alloc_basic  ===================
[21:27:30] [PASSED] One page
[21:27:30] [PASSED] More than one page
[21:27:30] [PASSED] Above the allocation limit
[21:27:30] [PASSED] One page, with coherent DMA mappings enabled
[21:27:30] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:27:30] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:27:30] ============== ttm_pool_alloc_basic_dma_addr  ==============
[21:27:30] [PASSED] One page
[21:27:30] [PASSED] More than one page
[21:27:30] [PASSED] Above the allocation limit
[21:27:30] [PASSED] One page, with coherent DMA mappings enabled
[21:27:30] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:27:30] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:27:30] [PASSED] ttm_pool_alloc_order_caching_match
[21:27:30] [PASSED] ttm_pool_alloc_caching_mismatch
[21:27:30] [PASSED] ttm_pool_alloc_order_mismatch
[21:27:30] [PASSED] ttm_pool_free_dma_alloc
[21:27:30] [PASSED] ttm_pool_free_no_dma_alloc
[21:27:30] [PASSED] ttm_pool_fini_basic
[21:27:30] ==================== [PASSED] ttm_pool =====================
[21:27:30] ================ ttm_resource (8 subtests) =================
[21:27:30] ================= ttm_resource_init_basic  =================
[21:27:30] [PASSED] Init resource in TTM_PL_SYSTEM
[21:27:30] [PASSED] Init resource in TTM_PL_VRAM
[21:27:30] [PASSED] Init resource in a private placement
[21:27:30] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:27:30] ============= [PASSED] ttm_resource_init_basic =============
[21:27:30] [PASSED] ttm_resource_init_pinned
[21:27:30] [PASSED] ttm_resource_fini_basic
[21:27:30] [PASSED] ttm_resource_manager_init_basic
[21:27:30] [PASSED] ttm_resource_manager_usage_basic
[21:27:30] [PASSED] ttm_resource_manager_set_used_basic
[21:27:30] [PASSED] ttm_sys_man_alloc_basic
[21:27:30] [PASSED] ttm_sys_man_free_basic
[21:27:30] ================== [PASSED] ttm_resource ===================
[21:27:30] =================== ttm_tt (15 subtests) ===================
[21:27:30] ==================== ttm_tt_init_basic  ====================
[21:27:30] [PASSED] Page-aligned size
[21:27:30] [PASSED] Extra pages requested
[21:27:30] ================ [PASSED] ttm_tt_init_basic ================
[21:27:30] [PASSED] ttm_tt_init_misaligned
[21:27:30] [PASSED] ttm_tt_fini_basic
[21:27:30] [PASSED] ttm_tt_fini_sg
[21:27:30] [PASSED] ttm_tt_fini_shmem
[21:27:30] [PASSED] ttm_tt_create_basic
[21:27:30] [PASSED] ttm_tt_create_invalid_bo_type
[21:27:30] [PASSED] ttm_tt_create_ttm_exists
[21:27:30] [PASSED] ttm_tt_create_failed
[21:27:30] [PASSED] ttm_tt_destroy_basic
[21:27:30] [PASSED] ttm_tt_populate_null_ttm
[21:27:30] [PASSED] ttm_tt_populate_populated_ttm
[21:27:30] [PASSED] ttm_tt_unpopulate_basic
[21:27:30] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:27:30] [PASSED] ttm_tt_swapin_basic
[21:27:30] ===================== [PASSED] ttm_tt ======================
[21:27:30] =================== ttm_bo (14 subtests) ===================
[21:27:30] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[21:27:30] [PASSED] Cannot be interrupted and sleeps
[21:27:30] [PASSED] Cannot be interrupted, locks straight away
[21:27:30] [PASSED] Can be interrupted, sleeps
[21:27:30] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:27:30] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:27:30] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:27:30] [PASSED] ttm_bo_reserve_double_resv
[21:27:30] [PASSED] ttm_bo_reserve_interrupted
[21:27:30] [PASSED] ttm_bo_reserve_deadlock
[21:27:30] [PASSED] ttm_bo_unreserve_basic
[21:27:30] [PASSED] ttm_bo_unreserve_pinned
[21:27:30] [PASSED] ttm_bo_unreserve_bulk
[21:27:30] [PASSED] ttm_bo_fini_basic
[21:27:30] [PASSED] ttm_bo_fini_shared_resv
[21:27:30] [PASSED] ttm_bo_pin_basic
[21:27:30] [PASSED] ttm_bo_pin_unpin_resource
[21:27:30] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:27:30] ===================== [PASSED] ttm_bo ======================
[21:27:30] ============== ttm_bo_validate (22 subtests) ===============
[21:27:30] ============== ttm_bo_init_reserved_sys_man  ===============
[21:27:30] [PASSED] Buffer object for userspace
[21:27:30] [PASSED] Kernel buffer object
[21:27:30] [PASSED] Shared buffer object
[21:27:30] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:27:30] ============== ttm_bo_init_reserved_mock_man  ==============
[21:27:30] [PASSED] Buffer object for userspace
[21:27:30] [PASSED] Kernel buffer object
[21:27:30] [PASSED] Shared buffer object
[21:27:30] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:27:30] [PASSED] ttm_bo_init_reserved_resv
[21:27:30] ================== ttm_bo_validate_basic  ==================
[21:27:30] [PASSED] Buffer object for userspace
[21:27:30] [PASSED] Kernel buffer object
[21:27:30] [PASSED] Shared buffer object
[21:27:30] ============== [PASSED] ttm_bo_validate_basic ==============
[21:27:30] [PASSED] ttm_bo_validate_invalid_placement
[21:27:30] ============= ttm_bo_validate_same_placement  ==============
[21:27:30] [PASSED] System manager
[21:27:30] [PASSED] VRAM manager
[21:27:30] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:27:30] [PASSED] ttm_bo_validate_failed_alloc
[21:27:30] [PASSED] ttm_bo_validate_pinned
[21:27:30] [PASSED] ttm_bo_validate_busy_placement
[21:27:30] ================ ttm_bo_validate_multihop  =================
[21:27:30] [PASSED] Buffer object for userspace
[21:27:30] [PASSED] Kernel buffer object
[21:27:30] [PASSED] Shared buffer object
[21:27:30] ============ [PASSED] ttm_bo_validate_multihop =============
[21:27:30] ========== ttm_bo_validate_no_placement_signaled  ==========
[21:27:30] [PASSED] Buffer object in system domain, no page vector
[21:27:30] [PASSED] Buffer object in system domain with an existing page vector
[21:27:30] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:27:30] ======== ttm_bo_validate_no_placement_not_signaled  ========
[21:27:30] [PASSED] Buffer object for userspace
[21:27:30] [PASSED] Kernel buffer object
[21:27:30] [PASSED] Shared buffer object
[21:27:30] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:27:30] [PASSED] ttm_bo_validate_move_fence_signaled
[21:27:31] ========= ttm_bo_validate_move_fence_not_signaled  =========
[21:27:31] [PASSED] Waits for GPU
[21:27:31] [PASSED] Tries to lock straight away
[21:27:31] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:27:31] [PASSED] ttm_bo_validate_swapout
[21:27:31] [PASSED] ttm_bo_validate_happy_evict
[21:27:31] [PASSED] ttm_bo_validate_all_pinned_evict
[21:27:31] [PASSED] ttm_bo_validate_allowed_only_evict
[21:27:31] [PASSED] ttm_bo_validate_deleted_evict
[21:27:31] [PASSED] ttm_bo_validate_busy_domain_evict
[21:27:31] [PASSED] ttm_bo_validate_evict_gutting
[21:27:31] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[21:27:31] ================= [PASSED] ttm_bo_validate =================
[21:27:31] ============================================================
[21:27:31] Testing complete. Ran 102 tests: passed: 102
[21:27:31] Elapsed time: 11.183s total, 1.660s configuring, 9.257s building, 0.232s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/display: Add DC3CO support (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1094 bytes --]

== Series Details ==

Series: drm/i915/display: Add DC3CO support (rev2)
URL   : https://patchwork.freedesktop.org/series/163938/
State : success

== Summary ==

CI Bug Log - changes from xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd_BAT -> xe-pw-163938v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_8869 -> IGT_8870
  * Linux: xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd -> xe-pw-163938v2

  IGT_8869: 4963e78e038806cc75f885d7d5713bb0d12c01d1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8870: 1aba4b364b6dbdf7926cc78501e7281d5176b029 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd: 489e26ada57ce96a2ee3e5853cfe74981ef85bbd
  xe-pw-163938v2: 163938v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/index.html

[-- Attachment #2: Type: text/html, Size: 1656 bytes --]

✗ Xe.CI.FULL: failure for drm/i915/display: Add DC3CO support (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 50911 bytes --]

== Series Details ==

Series: drm/i915/display: Add DC3CO support (rev2)
URL   : https://patchwork.freedesktop.org/series/163938/
State : failure

== Summary ==

CI Bug Log - changes from xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd_FULL -> xe-pw-163938v2_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-163938v2_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-163938v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-163938v2_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_sharpness_filter@invalid-plane-with-filter@pipe-a-edp-1-invalid-plane-with-filter:
    - shard-lnl:          [PASS][1] -> [DMESG-WARN][2] +1 other test dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-lnl-6/igt@kms_sharpness_filter@invalid-plane-with-filter@pipe-a-edp-1-invalid-plane-with-filter.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-lnl-4/igt@kms_sharpness_filter@invalid-plane-with-filter@pipe-a-edp-1-invalid-plane-with-filter.html

  * igt@xe_exec_system_allocator@eu-fault-2m-range-device-host:
    - shard-bmg:          [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-2/igt@xe_exec_system_allocator@eu-fault-2m-range-device-host.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-1/igt@xe_exec_system_allocator@eu-fault-2m-range-device-host.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma:
    - shard-lnl:          [PASS][5] -> [FAIL][6] +1 other test fail
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-lnl-4/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-lnl-5/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_uc_fw_init:
    - shard-bmg:          [PASS][7] -> [ABORT][8]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-8/igt@xe_fault_injection@inject-fault-probe-function-xe_uc_fw_init.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-3/igt@xe_fault_injection@inject-fault-probe-function-xe_uc_fw_init.html

  * igt@xe_pat@pt-caching:
    - shard-bmg:          NOTRUN -> [ABORT][9]
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@xe_pat@pt-caching.html

  
#### Warnings ####

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-lnl:          [SKIP][10] ([Intel XE#7339]) -> [SKIP][11]
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-lnl-7/igt@kms_pm_dc@dc3co-vpb-simulation.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-lnl-3/igt@kms_pm_dc@dc3co-vpb-simulation.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_bw@linear-tiling-2-displays-target-1920x1080p}:
    - shard-bmg:          NOTRUN -> [SKIP][12]
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@kms_bw@linear-tiling-2-displays-target-1920x1080p.html

  * {igt@kms_bw@linear-tiling-3-displays-target-3840x2160p}:
    - shard-bmg:          [SKIP][13] ([Intel XE#6703]) -> [SKIP][14]
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_bw@linear-tiling-3-displays-target-3840x2160p.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-1/igt@kms_bw@linear-tiling-3-displays-target-3840x2160p.html

  
Known issues
------------

  Here are the changes found in xe-pw-163938v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2327]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#1124]) +4 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2887]) +4 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-2/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#3432])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html

  * igt@kms_chamelium_frames@hdmi-aspect-ratio:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2252]) +2 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-2/igt@kms_chamelium_frames@hdmi-aspect-ratio.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          NOTRUN -> [FAIL][20] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@uevent@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][21] ([Intel XE#6707] / [Intel XE#7439])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@kms_content_protection@uevent@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-offscreen-128x42:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2320]) +2 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-9/igt@kms_cursor_crc@cursor-offscreen-128x42.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][23] -> [DMESG-WARN][24] ([Intel XE#5354]) +1 other test dmesg-warn
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][25] -> [FAIL][26] ([Intel XE#7571])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#4331] / [Intel XE#7227])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-1/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [PASS][28] -> [FAIL][29] ([Intel XE#301]) +1 other test fail
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#7178] / [Intel XE#7349])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#7178] / [Intel XE#7351])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#2311]) +7 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#4141]) +6 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2313]) +9 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#6911] / [Intel XE#7378])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#2486])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-3/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#6912] / [Intel XE#7375])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#7283]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-2/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#7794])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_psr2_sf@pr-cursor-plane-update-sf:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#1489]) +1 other test skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@kms_psr2_sf@pr-cursor-plane-update-sf.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2387] / [Intel XE#7429])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-psr-sprite-render:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-2/igt@kms_psr@fbc-psr-sprite-render.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [PASS][44] -> [FAIL][45] ([Intel XE#2142]) +1 other test fail
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-lnl-1/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-lnl-2/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_compute@eu-busy-10s:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#6599])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@xe_compute@eu-busy-10s.html

  * igt@xe_eudebug_online@single-step-one:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#7636]) +2 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-2/igt@xe_eudebug_online@single-step-one.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-imm:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#7136]) +2 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-imm.html

  * igt@xe_exec_multi_queue@two-queues-priority:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#6874]) +10 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-3/igt@xe_exec_multi_queue@two-queues-priority.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#7138]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@xe_exec_threads@threads-multi-queue-mixed-userptr.html

  * igt@xe_multigpu_svm@mgpu-latency-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#6964]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-2/igt@xe_multigpu_svm@mgpu-latency-prefetch.html

  * igt@xe_page_reclaim@random:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#7793])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-7/igt@xe_page_reclaim@random.html

  * igt@xe_query@multigpu-query-config:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#944])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-7/igt@xe_query@multigpu-query-config.html

  * igt@xe_sriov_flr@flr-each-isolation:
    - shard-bmg:          [PASS][55] -> [FAIL][56] ([Intel XE#6569])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-5/igt@xe_sriov_flr@flr-each-isolation.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-7/igt@xe_sriov_flr@flr-each-isolation.html

  
#### Possible fixes ####

  * igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size:
    - shard-bmg:          [DMESG-FAIL][57] -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-bmg:          [ABORT][59] ([Intel XE#6652]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-2/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@cd-dp2-hdmi-a3:
    - shard-bmg:          [ABORT][61] ([Intel XE#5545] / [Intel XE#6652]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-2/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@cd-dp2-hdmi-a3.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@cd-dp2-hdmi-a3.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-bmg:          [SKIP][63] ([Intel XE#7308]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_hdmi_inject@inject-audio.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-9/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          [FAIL][65] ([Intel XE#7340] / [Intel XE#7504]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-lnl-4/igt@kms_pm_dc@dc5-dpms.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-lnl-3/igt@kms_pm_dc@dc5-dpms.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-lnl:          [FAIL][67] ([Intel XE#7340]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-lnl-4/igt@kms_pm_dc@dc6-psr.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-lnl-4/igt@kms_pm_dc@dc6-psr.html

  * igt@xe_configfs@gt-types-allowed:
    - shard-bmg:          [DMESG-WARN][69] ([Intel XE#7725]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-6/igt@xe_configfs@gt-types-allowed.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@xe_configfs@gt-types-allowed.html

  * igt@xe_create@invalid-pad:
    - shard-bmg:          [SKIP][71] ([Intel XE#6557] / [Intel XE#6703]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_create@invalid-pad.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-6/igt@xe_create@invalid-pad.html

  * igt@xe_exec_system_allocator@many-execqueues-new-busy-nomemset:
    - shard-bmg:          [INCOMPLETE][73] ([Intel XE#6652]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-5/igt@xe_exec_system_allocator@many-execqueues-new-busy-nomemset.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-1/igt@xe_exec_system_allocator@many-execqueues-new-busy-nomemset.html

  * igt@xe_exec_system_allocator@process-many-malloc-nomemset:
    - shard-bmg:          [SKIP][75] ([Intel XE#6703]) -> [PASS][76] +119 other tests pass
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_exec_system_allocator@process-many-malloc-nomemset.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@xe_exec_system_allocator@process-many-malloc-nomemset.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_hw_engine_group_add_exec_queue:
    - shard-bmg:          [ABORT][77] ([Intel XE#7578]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-1/igt@xe_fault_injection@exec-queue-create-fail-xe_hw_engine_group_add_exec_queue.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@xe_fault_injection@exec-queue-create-fail-xe_hw_engine_group_add_exec_queue.html

  * igt@xe_live_ktest@xe_bo:
    - shard-bmg:          [FAIL][79] -> [PASS][80] +1 other test pass
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_live_ktest@xe_bo.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@xe_live_ktest@xe_bo.html

  * igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit:
    - shard-bmg:          [FAIL][81] ([Intel XE#7736]) -> [PASS][82] +2 other tests pass
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-bmg:          [FAIL][83] ([Intel XE#6569]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-6/igt@xe_sriov_flr@flr-vfs-parallel.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-7/igt@xe_sriov_flr@flr-vfs-parallel.html

  * igt@xe_survivability@runtime-survivability:
    - shard-bmg:          [DMESG-WARN][85] ([Intel XE#6627] / [Intel XE#7419]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-1/igt@xe_survivability@runtime-survivability.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@xe_survivability@runtime-survivability.html

  
#### Warnings ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-bmg:          [SKIP][87] ([Intel XE#6703]) -> [SKIP][88] ([Intel XE#2370])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-bmg:          [SKIP][89] ([Intel XE#6703]) -> [SKIP][90] ([Intel XE#2327])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_big_fb@linear-16bpp-rotate-90.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-bmg:          [SKIP][91] ([Intel XE#6703]) -> [SKIP][92] ([Intel XE#607] / [Intel XE#7361])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-7/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
    - shard-bmg:          [SKIP][93] ([Intel XE#6703]) -> [SKIP][94] ([Intel XE#1124])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-1/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs:
    - shard-bmg:          [SKIP][95] ([Intel XE#6703]) -> [SKIP][96] ([Intel XE#2887]) +3 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs.html

  * igt@kms_chamelium_hpd@hdmi-hpd-after-suspend:
    - shard-bmg:          [SKIP][97] ([Intel XE#6703]) -> [SKIP][98] ([Intel XE#2252]) +1 other test skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_chamelium_hpd@hdmi-hpd-after-suspend.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@kms_chamelium_hpd@hdmi-hpd-after-suspend.html

  * igt@kms_content_protection@uevent:
    - shard-bmg:          [SKIP][99] ([Intel XE#6703]) -> [FAIL][100] ([Intel XE#6707] / [Intel XE#7439])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_content_protection@uevent.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-bmg:          [SKIP][101] ([Intel XE#6703]) -> [SKIP][102] ([Intel XE#2321] / [Intel XE#7355])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_cursor_crc@cursor-random-512x512.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-1/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-max-size:
    - shard-bmg:          [SKIP][103] ([Intel XE#6703]) -> [SKIP][104] ([Intel XE#2320])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_cursor_crc@cursor-sliding-max-size.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-3/igt@kms_cursor_crc@cursor-sliding-max-size.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yuv-linear-to-32bpp-yuv-linear-reflect-x:
    - shard-bmg:          [SKIP][105] ([Intel XE#6703]) -> [SKIP][106] ([Intel XE#7179])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-yuv-linear-to-32bpp-yuv-linear-reflect-x.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-yuv-linear-to-32bpp-yuv-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][107] ([Intel XE#6703]) -> [SKIP][108] ([Intel XE#4141]) +4 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-render:
    - shard-bmg:          [SKIP][109] ([Intel XE#6703]) -> [SKIP][110] ([Intel XE#2311]) +3 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-render.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-suspend:
    - shard-bmg:          [SKIP][111] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][112] ([Intel XE#2311])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-suspend.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt:
    - shard-bmg:          [SKIP][113] ([Intel XE#6703]) -> [SKIP][114] ([Intel XE#2313]) +3 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-argb161616f-draw-mmap-wc:
    - shard-bmg:          [SKIP][115] ([Intel XE#6703]) -> [SKIP][116] ([Intel XE#7061] / [Intel XE#7356])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-argb161616f-draw-mmap-wc.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-argb161616f-draw-mmap-wc.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][117] ([Intel XE#3544]) -> [SKIP][118] ([Intel XE#3374] / [Intel XE#3544])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-9/igt@kms_hdr@brightness-with-hdr.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-7/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping:
    - shard-bmg:          [SKIP][119] ([Intel XE#6703]) -> [SKIP][120] ([Intel XE#7283]) +1 other test skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-bmg:          [SKIP][121] ([Intel XE#6703]) -> [SKIP][122] ([Intel XE#7376] / [Intel XE#870])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_pm_backlight@basic-brightness.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
    - shard-bmg:          [SKIP][123] ([Intel XE#6703]) -> [SKIP][124] ([Intel XE#1489]) +2 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr@psr2-sprite-render:
    - shard-bmg:          [SKIP][125] ([Intel XE#6703]) -> [SKIP][126] ([Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_psr@psr2-sprite-render.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-2/igt@kms_psr@psr2-sprite-render.html

  * igt@kms_sharpness_filter@filter-scaler-upscale:
    - shard-bmg:          [SKIP][127] ([Intel XE#6703]) -> [SKIP][128] ([Intel XE#6503])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_sharpness_filter@filter-scaler-upscale.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@kms_sharpness_filter@filter-scaler-upscale.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][129] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][130] ([Intel XE#2509] / [Intel XE#7437])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@cmrr:
    - shard-bmg:          [SKIP][131] ([Intel XE#6703]) -> [SKIP][132] ([Intel XE#2168] / [Intel XE#7444])
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@kms_vrr@cmrr.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-1/igt@kms_vrr@cmrr.html

  * igt@xe_eudebug@discovery-empty:
    - shard-bmg:          [SKIP][133] ([Intel XE#6703]) -> [SKIP][134] ([Intel XE#7636]) +2 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_eudebug@discovery-empty.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-7/igt@xe_eudebug@discovery-empty.html

  * igt@xe_evict@evict-mixed-threads-small-multi-queue:
    - shard-bmg:          [SKIP][135] ([Intel XE#6703]) -> [SKIP][136] ([Intel XE#7140])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_evict@evict-mixed-threads-small-multi-queue.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-2/igt@xe_evict@evict-mixed-threads-small-multi-queue.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind:
    - shard-bmg:          [SKIP][137] ([Intel XE#6703]) -> [SKIP][138] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr:
    - shard-bmg:          [SKIP][139] ([Intel XE#6703]) -> [SKIP][140] ([Intel XE#7136]) +1 other test skip
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_exec_fault_mode@twice-multi-queue-userptr.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@xe_exec_fault_mode@twice-multi-queue-userptr.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-close-fd:
    - shard-bmg:          [SKIP][141] ([Intel XE#6703]) -> [SKIP][142] ([Intel XE#6874]) +4 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-close-fd.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-9/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-close-fd.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-rebind:
    - shard-bmg:          [SKIP][143] ([Intel XE#6703]) -> [SKIP][144] ([Intel XE#7138]) +1 other test skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_exec_threads@threads-multi-queue-mixed-rebind.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@xe_exec_threads@threads-multi-queue-mixed-rebind.html

  * igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
    - shard-bmg:          [FAIL][145] -> [SKIP][146] ([Intel XE#2229])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][147], [PASS][148], [SKIP][149], [PASS][150], [PASS][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156], [PASS][157], [PASS][158], [PASS][159], [PASS][160], [PASS][161], [PASS][162], [PASS][163], [PASS][164], [PASS][165], [PASS][166], [PASS][167], [PASS][168], [PASS][169], [PASS][170], [PASS][171], [PASS][172]) ([Intel XE#2457] / [Intel XE#7405]) -> ([PASS][173], [PASS][174], [PASS][175], [PASS][176], [PASS][177], [PASS][178], [PASS][179], [PASS][180], [PASS][181], [PASS][182], [PASS][183], [PASS][184], [PASS][185], [PASS][186], [PASS][187], [PASS][188], [PASS][189], [PASS][190], [PASS][191], [PASS][192], [PASS][193], [PASS][194], [DMESG-WARN][195], [DMESG-WARN][196], [PASS][197]) ([Intel XE#7725])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-9/igt@xe_module_load@load.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-6/igt@xe_module_load@load.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-9/igt@xe_module_load@load.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-8/igt@xe_module_load@load.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-8/igt@xe_module_load@load.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-7/igt@xe_module_load@load.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-7/igt@xe_module_load@load.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-5/igt@xe_module_load@load.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-1/igt@xe_module_load@load.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_module_load@load.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-6/igt@xe_module_load@load.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-2/igt@xe_module_load@load.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-6/igt@xe_module_load@load.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-10/igt@xe_module_load@load.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-9/igt@xe_module_load@load.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-7/igt@xe_module_load@load.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-2/igt@xe_module_load@load.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-9/igt@xe_module_load@load.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-10/igt@xe_module_load@load.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-10/igt@xe_module_load@load.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-2/igt@xe_module_load@load.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-1/igt@xe_module_load@load.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-8/igt@xe_module_load@load.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_module_load@load.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_module_load@load.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-5/igt@xe_module_load@load.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@xe_module_load@load.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-7/igt@xe_module_load@load.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-3/igt@xe_module_load@load.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-2/igt@xe_module_load@load.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-3/igt@xe_module_load@load.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@xe_module_load@load.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@xe_module_load@load.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-2/igt@xe_module_load@load.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@xe_module_load@load.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-6/igt@xe_module_load@load.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-7/igt@xe_module_load@load.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-2/igt@xe_module_load@load.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-9/igt@xe_module_load@load.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-1/igt@xe_module_load@load.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-9/igt@xe_module_load@load.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-9/igt@xe_module_load@load.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-7/igt@xe_module_load@load.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@xe_module_load@load.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-1/igt@xe_module_load@load.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@xe_module_load@load.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@xe_module_load@load.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-10/igt@xe_module_load@load.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-6/igt@xe_module_load@load.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-6/igt@xe_module_load@load.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-6/igt@xe_module_load@load.html

  * igt@xe_page_reclaim@binds-large-split:
    - shard-bmg:          [SKIP][198] ([Intel XE#6703]) -> [SKIP][199] ([Intel XE#7793])
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_page_reclaim@binds-large-split.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-8/igt@xe_page_reclaim@binds-large-split.html

  * igt@xe_pm@d3hot-i2c:
    - shard-bmg:          [SKIP][200] ([Intel XE#6703]) -> [SKIP][201] ([Intel XE#5742] / [Intel XE#7328] / [Intel XE#7400])
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_pm@d3hot-i2c.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-5/igt@xe_pm@d3hot-i2c.html

  * igt@xe_query@multigpu-query-hwconfig:
    - shard-bmg:          [SKIP][202] ([Intel XE#6703]) -> [SKIP][203] ([Intel XE#944])
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd/shard-bmg-3/igt@xe_query@multigpu-query-hwconfig.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/shard-bmg-6/igt@xe_query@multigpu-query-hwconfig.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#6599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6599
  [Intel XE#6627]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6627
  [Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7227
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7308
  [Intel XE#7328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7328
  [Intel XE#7339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7339
  [Intel XE#7340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7340
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7361
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7375
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7378
  [Intel XE#7400]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7400
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7419]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7419
  [Intel XE#7429]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7429
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7439
  [Intel XE#7444]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7444
  [Intel XE#7504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7504
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#7578]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7578
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#7725]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7725
  [Intel XE#7736]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7736
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7794
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_8869 -> IGT_8870
  * Linux: xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd -> xe-pw-163938v2

  IGT_8869: 4963e78e038806cc75f885d7d5713bb0d12c01d1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8870: 1aba4b364b6dbdf7926cc78501e7281d5176b029 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4926-489e26ada57ce96a2ee3e5853cfe74981ef85bbd: 489e26ada57ce96a2ee3e5853cfe74981ef85bbd
  xe-pw-163938v2: 163938v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163938v2/index.html

[-- Attachment #2: Type: text/html, Size: 58483 bytes --]

RE: [PATCH v2 06/13] drm/i915/display: Add HAS_DC3CO() macro

[Shankar, Uma]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Wednesday, April 22, 2026 9:56 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kurmi, Suresh Kumar
> <suresh.kumar.kurmi@intel.com>
> Subject: [PATCH v2 06/13] drm/i915/display: Add HAS_DC3CO() macro
> 
> Add HAS_DC3CO() to identify platforms supporting DC3CO.
> DC3CO is supported from display version 35 onwards.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> BSpec: 75253
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 074e3ba8fb77..7fd994d92ba9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -159,6 +159,7 @@ struct intel_display_platforms {
>  #define HAS_CUR_FBC(__display)		(!HAS_GMCH(__display) &&
> IS_DISPLAY_VER(__display, 7, 13))
>  #define HAS_D12_PLANE_MINIMIZATION(__display)	((__display)-
> >platform.rocketlake || (__display)->platform.alderlake_s)
>  #define HAS_DBUF_OVERLAP_DETECTION(__display)
> 	(DISPLAY_RUNTIME_INFO(__display)->has_dbuf_overlap_detection)
> +#define HAS_DC3CO(__display)		(DISPLAY_VER(__display) >= 35)
>  #define HAS_DDI(__display)		(DISPLAY_INFO(__display)->has_ddi)
>  #define HAS_DISPLAY(__display)
> 	(DISPLAY_RUNTIME_INFO(__display)->pipe_mask != 0)
>  #define HAS_DMC(__display)		(DISPLAY_RUNTIME_INFO(__display)-
> >has_dmc)
> --
> 2.43.0

RE: [PATCH v2 07/13] drm/i915/display: Add DC3CO eligibility computation

[Shankar, Uma]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Wednesday, April 22, 2026 9:56 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kurmi, Suresh Kumar
> <suresh.kumar.kurmi@intel.com>
> Subject: [PATCH v2 07/13] drm/i915/display: Add DC3CO eligibility computation
> 
> Compute DC3CO eligibility during atomic_check based on pipe/port constraints
> and runtime triggers and store result in display->power.dc3co.
> 
> When DC3CO is allowed, request DC_STATE_EN_UPTO_DC3CO and reduce the
> DC entry delay. Otherwise, retain the existing delay and set default
> DC_STATE_EN_UPTO_DC6 .
> 
> Changes in v2:
> - Move dc3co state from intel_atomic_state to display->power (Uma Shankar)
> - Use #define bitmasks instead of enum for DC3CO triggers (Jani Nikula)
> 
> BSpec: 75253
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 92 ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_display.h  |  1 -
> .../gpu/drm/i915/display/intel_display_core.h |  3 +-
>  .../drm/i915/display/intel_display_power.c    | 30 ++++++
>  .../drm/i915/display/intel_display_power.h    | 22 +++++
>  5 files changed, 141 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 674a4ece6d0f..de493d04a622 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5870,6 +5870,69 @@ static bool intel_pipes_need_modeset(struct
> intel_atomic_state *state,
>  	return false;
>  }
> 
> +static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
> +					     const struct intel_crtc_state
> *crtc_state) {
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> +	enum port port = dig_port->base.port;
> +	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
> +
> +	return num_pipes == 1 && pipe <= PIPE_B && port <= PORT_B; }
> +
> +static void intel_dc3co_compute_state(struct intel_atomic_state *state)
> +{
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_crtc *crtc;
> +	struct intel_crtc_state *crtc_state;
> +	struct intel_encoder *encoder;
> +	struct intel_dp *intel_dp;
> +	int active_pipes = 0;
> +	u32 trigger = DC3CO_TRIGGER_NONE;
> +
> +	if (!HAS_DC3CO(display))
> +		return;
> +
> +	for_each_intel_crtc(display->drm, crtc) {
> +		trigger = DC3CO_TRIGGER_NONE;
> +		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> +		if (!crtc_state)
> +			crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
> +
> +		if (!crtc_state || !crtc_state->hw.active)
> +			continue;
> +
> +		active_pipes++;
> +
> +		if (active_pipes > 1)
> +			goto done;
> +
> +		for_each_intel_encoder_mask(display->drm, encoder,
> +					    crtc_state->uapi.encoder_mask) {
> +			if (encoder->type != INTEL_OUTPUT_EDP)
> +				goto done;
> +
> +			intel_dp = enc_to_intel_dp(encoder);
> +
> +			if (!intel_dc3co_port_pipe_compatible(intel_dp,
> crtc_state))
> +				goto done;
> +		}
> +
> +		if (crtc_state->has_lobf)
> +			trigger |= DC3CO_TRIGGER_LOBF;
> +		if (crtc_state->has_panel_replay)
> +			trigger |= DC3CO_TRIGGER_PANEL_REPLAY;
> +		if (crtc_state->has_sel_update)
> +			trigger |= DC3CO_TRIGGER_PSR2;

These values will get updated even if active pipe count is 2. Please check once.

With this fixed,
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

Note: Would be good to get feedback from Imre as well.

> +	}
> +
> +done:
> +	intel_display_power_dc3co_update(display, !!trigger, trigger);
> +	drm_dbg_kms(display->drm, "DC3CO allowed=%d trigger=0x%x\n",
> +		    !!trigger, trigger);
> +}
> +
>  static int intel_atomic_check_joiner(struct intel_atomic_state *state,
>  				     struct intel_crtc *primary_crtc)  { @@ -6544,6
> +6607,7 @@ int intel_atomic_check(struct drm_device *dev,
>  	if (ret)
>  		goto fail;
> 
> +	intel_dc3co_compute_state(state);
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>  					    new_crtc_state, i) {
>  		intel_color_assert_luts(new_crtc_state);
> @@ -7415,6 +7479,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
>  	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
>  	struct ref_tracker *wakeref = NULL;
>  	int i;
> +	int power_async_delay;
> 
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
>  		intel_atomic_dsb_prepare(state, crtc); @@ -7621,11 +7686,28
> @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		 */
>  		intel_uncore_arm_unclaimed_mmio_detection(uncore);
>  	}
> -	/*
> -	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
> -	 * toggling overhead at and above 60 FPS.
> -	 */
> -	intel_display_power_put_async_delay(display,
> POWER_DOMAIN_DC_OFF, wakeref, 17);
> +
> +	if (intel_display_power_dc3co_allowed(display) &&
> +	    intel_display_power_dc3co_supported(display)) {
> +		intel_display_power_set_target_dc_state(display,
> DC_STATE_EN_UPTO_DC3CO);
> +		/*
> +		 * Use minimal re-enable delay to allow DC3CO entry on
> +		 * the next idle frame, unlike the 17ms guard needed to
> +		 * prevent DC5/DC6 toggling overhead at 60+ FPS.
> +		 */
> +		power_async_delay = 1;
> +	} else {
> +		/*
> +		 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
> +		 * toggling overhead at and above 60 FPS.
> +		 */
> +		intel_display_power_set_target_dc_state(display,
> DC_STATE_EN_UPTO_DC6);
> +		power_async_delay = 17;
> +	}
> +
> +	intel_display_power_put_async_delay(display,
> +					    POWER_DOMAIN_DC_OFF, wakeref,
> power_async_delay);
> +
>  	intel_display_rpm_put(display, state->wakeref);
> 
>  	/*
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 1e76a455d7c4..2795e4b9e799 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -521,5 +521,4 @@ bool assert_port_valid(struct intel_display *display, enum
> port port);
> 
>  bool intel_scanout_needs_vtd_wa(struct intel_display *display);  int
> intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
> -
>  #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index c5a07090cba6..13e9b986b6fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -535,7 +535,8 @@ struct intel_display {
> 
>  	struct {
>  		struct i915_power_domains domains;
> -
> +		/* DC3CO eligibility state */
> +		struct intel_dc3co_state dc3co;
>  		/* Shadow for DISPLAY_PHY_CONTROL which can't be safely
> read */
>  		u32 chv_phy_control;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index f626803bbd88..ff1915be59c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -372,6 +372,35 @@ bool intel_display_power_dc3co_supported(struct
> intel_display *display)
>  	return (power_domains->allowed_dc_mask &
> DC_STATE_EN_UPTO_DC3CO) == DC_STATE_EN_UPTO_DC3CO;  }
> 
> +void intel_display_power_dc3co_update(struct intel_display *display,
> +				      bool allowed, u32 trigger)
> +{
> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
> +
> +	if (!HAS_DC3CO(display))
> +		return;
> +
> +	mutex_lock(&dc3co->lock);
> +	dc3co->allowed = allowed;
> +	dc3co->trigger = trigger;
> +	mutex_unlock(&dc3co->lock);
> +}
> +
> +bool intel_display_power_dc3co_allowed(struct intel_display *display) {
> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
> +	bool allowed;
> +
> +	if (!HAS_DC3CO(display))
> +		return false;
> +
> +	mutex_lock(&dc3co->lock);
> +	allowed = dc3co->allowed;
> +	mutex_unlock(&dc3co->lock);
> +
> +	return allowed;
> +}
> +
>  static void __async_put_domains_mask(struct i915_power_domains
> *power_domains,
>  				     struct intel_power_domain_mask *mask)  {
> @@ -1051,6 +1080,7 @@ int intel_power_domains_init(struct intel_display
> *display)
>  		sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
> 
>  	mutex_init(&power_domains->lock);
> +	mutex_init(&display->power.dc3co.lock);
> 
>  	INIT_DELAYED_WORK(&power_domains->async_put_work,
>  			  intel_display_power_put_async_work);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 05880e9da89f..0b1a06f88ae5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -131,6 +131,25 @@ struct intel_power_domain_mask {
>  	DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);  };
> 
> +/*
> + * DC3CO enabling triggers (bitmask).
> + * DC3CO may be enabled when at least one of these triggers is active.
> + * Additional constraints may still apply.
> + */
> +#define DC3CO_TRIGGER_NONE		(0)
> +#define DC3CO_TRIGGER_PSR2		BIT(0)
> +#define DC3CO_TRIGGER_LOBF		BIT(1)
> +#define DC3CO_TRIGGER_PANEL_REPLAY	BIT(2)
> +#define DC3CO_TRIGGER_ALL		(DC3CO_TRIGGER_PSR2 | \
> +					 DC3CO_TRIGGER_LOBF | \
> +					 DC3CO_TRIGGER_PANEL_REPLAY)
> +
> +struct intel_dc3co_state {
> +	struct mutex lock; /* Protects allowed and trigger fields */
> +	bool allowed; /* DC3CO eligibility result */
> +	u32 trigger; /* Bitmask of active DC3CO triggers */ };
> +
>  struct i915_power_domains {
>  	/*
>  	 * Power wells needed for initialization at driver init and suspend @@ -
> 187,6 +206,9 @@ void intel_display_power_set_target_dc_state(struct
> intel_display *display,
>  					     u32 state);
>  u32 intel_display_power_get_current_dc_state(struct intel_display *display);  bool
> intel_display_power_dc3co_supported(struct intel_display *display);
> +void intel_display_power_dc3co_update(struct intel_display *display,
> +				      bool allowed, u32 trigger);
> +bool intel_display_power_dc3co_allowed(struct intel_display *display);
> 
>  bool intel_display_power_is_enabled(struct intel_display *display,
>  				    enum intel_display_power_domain domain);
> --
> 2.43.0

RE: [PATCH v2 08/13] drm/i915/display: Store DC3CO eligibility in PSR state

[Shankar, Uma]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Wednesday, April 22, 2026 9:56 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kurmi, Suresh Kumar
> <suresh.kumar.kurmi@intel.com>
> Subject: [PATCH v2 08/13] drm/i915/display: Store DC3CO eligibility in PSR state
> 
> Store DC3CO eligibility in intel_dp->psr during
> intel_psr_post_plane_update() so PSR configuration can take DC3CO into
> account.
> 
> This will be used to control PSR2 parameters such as idle frames.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Changes in v2:
> - Use intel_display_power_dc3co_allowed(display) instead
>   of intel_dc3co_allowed(state)
> 
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++
>  drivers/gpu/drm/i915/display/intel_psr.c           | 4 ++++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index fc283cc429ec..28ab686b702a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1769,6 +1769,8 @@ struct intel_psr {
>  	ktime_t last_exit;
>  	bool sink_not_reliable;
>  	bool irq_aux_error;
> +	/* DC3CO eligibility used to control PSR configuration */
> +	bool dc3co_eligible;
>  	u16 su_w_granularity;
>  	u16 su_y_granularity;
>  	bool source_panel_replay_support;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 34e4a1ad609e..2e0478e3d560 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2263,6 +2263,7 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
>  	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
>  	intel_dp->psr.active_non_psr_pipes = 0;
>  	intel_dp->psr.pkg_c_latency_used = 0;
> +	intel_dp->psr.dc3co_eligible = false;
>  }
> 
>  /**
> @@ -3095,6 +3096,9 @@ void intel_psr_post_plane_update(struct
> intel_atomic_state *state,
>  		 */
>  		intel_dp->psr.busy_frontbuffer_bits = 0;
> 
> +		intel_dp->psr.dc3co_eligible =
> intel_display_power_dc3co_allowed(display) &&
> +			intel_display_power_dc3co_supported(display);
> +
>  		mutex_unlock(&psr->lock);
>  	}
>  }
> --
> 2.43.0

RE: [PATCH v2 09/13] drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO

[Shankar, Uma]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Wednesday, April 22, 2026 9:56 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kurmi, Suresh Kumar
> <suresh.kumar.kurmi@intel.com>
> Subject: [PATCH v2 09/13] drm/i915/display: PSR2: Set idle_frames to 0 for
> DC3CO
> 
> Force idle_frames to 0 when DC3CO is eligible.
> 
> Changes in v2:
> - Extend existing Wa_16025596647 condition
>   instead of adding a new if block (Uma Shankar)

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> BSpec: 75253
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2e0478e3d560..ff9ce7d2a5aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1069,10 +1069,11 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
>  	u32 psr_val = 0;
>  	u8 idle_frames;
> 
> -	/* Wa_16025596647 */
> -	if ((DISPLAY_VER(display) == 20 ||
> -	     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
> &&
> -	    is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
> +	/* DC3CO / Wa_16025596647 */
> +	if (intel_dp->psr.dc3co_eligible ||
> +	    ((DISPLAY_VER(display) == 20 ||
> +	      IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
> &&
> +	     is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used))
>  		idle_frames = 0;
>  	else
>  		idle_frames = psr_compute_idle_frames(intel_dp);
> --
> 2.43.0

RE: [PATCH v2 10/13] drm/i915/display: Enable DC3CO idle protocol in ALPM

[Shankar, Uma]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Wednesday, April 22, 2026 9:56 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kurmi, Suresh Kumar
> <suresh.kumar.kurmi@intel.com>
> Subject: [PATCH v2 10/13] drm/i915/display: Enable DC3CO idle protocol in ALPM
> 
> Add PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL bit definition and set it
> when DC3CO is allowed.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Changes in v2:
> - Squash "Define DC3CO idle protocol bit in PR_ALPM_CTL"
>   into this patch (Uma Shankar)
> - Use intel_display_power_dc3co_allowed(display)
>   instead of intel_dc3co_allowed(state)
> 
> BSpec: 75253
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c     | 6 ++++++
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 1 +
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index a7350ce8e716..6394d1568b54 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -389,6 +389,12 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  			if (crtc_state->disable_as_sdp_when_pr_active)
>  				pr_alpm_ctl |=
> PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> 
> +			if (intel_display_power_dc3co_allowed(display) &&
> +			    intel_display_power_dc3co_supported(display))
> +				pr_alpm_ctl |=
> PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> +			else
> +				pr_alpm_ctl &=
> ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> +
>  			intel_de_write(display, PR_ALPM_CTL(display,
> cpu_transcoder),
>  				       pr_alpm_ctl);
>  		}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 8afbf5a38335..16a9e3af198d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -268,6 +268,7 @@
> 
>  #define _PR_ALPM_CTL_A	0x60948
>  #define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran,
> _PR_ALPM_CTL_A)
> +#define  PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL
> 	BIT(7)
>  #define  PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU
> 	BIT(6)
>  #define  PR_ALPM_CTL_RFB_UPDATE_CONTROL
> 	BIT(5)
>  #define  PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE
> 	BIT(4)
> --
> 2.43.0

RE: [PATCH v2 11/13] drm/i915/display: PSR Add delayed work to exit DC3CO

[Shankar, Uma]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Wednesday, April 22, 2026 9:56 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kurmi, Suresh Kumar
> <suresh.kumar.kurmi@intel.com>
> Subject: [PATCH v2 11/13] drm/i915/display: PSR Add delayed work to exit
> DC3CO
> 
> For DC3CO, idle_frames is programmed to 0, so PSR does not enter deep sleep.
> Add delayed work to schedule DC3CO exit after an idle duration derived from
> frame time (minimum equivalent of 6 frames).
> 
> The work is re-armed from the PSR flush path on relevant frontbuffer activity.
> Once the display remains idle, DC3CO is disabled, idle frames are reprogrammed
> to their normal value, and DC6 is enabled to allow deeper power savings.
> 
> Changes in v2:
> - Squash "PSR set idle frames while exit from DC3CO"
>   into this patch (Uma Shankar)
> - Add cancel_delayed_work() in intel_psr_disable_locked()
>   before clearing dc3co_eligible (Uma Shankar)

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  2 +
>  drivers/gpu/drm/i915/display/intel_psr.c      | 50 +++++++++++++++++++
>  2 files changed, 52 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 28ab686b702a..fb5c12bb5b5c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1771,6 +1771,8 @@ struct intel_psr {
>  	bool irq_aux_error;
>  	/* DC3CO eligibility used to control PSR configuration */
>  	bool dc3co_eligible;
> +	/* DC3CO disable work */
> +	struct delayed_work dc3co_work;
>  	u16 su_w_granularity;
>  	u16 su_y_granularity;
>  	bool source_panel_replay_support;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index ff9ce7d2a5aa..36180206d3ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1728,6 +1728,51 @@ static bool intel_psr_needs_wa_18037818876(struct
> intel_dp *intel_dp,
>  		!crtc_state->has_sel_update);
>  }
> 
> +static void psr2_dc3co_disable_locked(struct intel_dp *intel_dp) {
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	if (intel_dp->psr.dc3co_eligible) {
> +		intel_dp->psr.dc3co_eligible = false;
> +		intel_display_power_set_target_dc_state(display,
> DC_STATE_EN_UPTO_DC6);
> +		psr2_program_idle_frames(intel_dp,
> psr_compute_idle_frames(intel_dp));
> +	}
> +}
> +
> +static void psr2_dc3co_disable_work(struct work_struct *work) {
> +	struct intel_dp *intel_dp =
> +		container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
> +
> +	mutex_lock(&intel_dp->psr.lock);
> +	psr2_dc3co_disable_locked(intel_dp);
> +	mutex_unlock(&intel_dp->psr.lock);
> +}
> +
> +static void
> +psr2_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
> +			enum fb_op_origin origin)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	if (!intel_dp->psr.dc3co_eligible)
> +		return;
> +
> +	if (!intel_dp->psr.sel_update_enabled ||
> +	    !intel_dp->psr.active)
> +		return;
> +	/*
> +	 * At every frontbuffer flush flip event modified delay of delayed work,
> +	 * when delayed work schedules that means display has been idle.
> +	 */
> +	if (!(frontbuffer_bits &
> +	    INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
> +		return;
> +
> +	mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,
> +			 intel_dp->psr.dc3co_exit_delay);
> +}
> +
>  static
>  void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp,
>  				 struct intel_crtc_state *crtc_state) @@ -2264,6
> +2309,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
>  	intel_dp->psr.active_non_psr_pipes = 0;
>  	intel_dp->psr.pkg_c_latency_used = 0;
> +	cancel_delayed_work(&intel_dp->psr.dc3co_work);
>  	intel_dp->psr.dc3co_eligible = false;
>  }
> 
> @@ -2294,6 +2340,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
> 
>  	mutex_unlock(&intel_dp->psr.lock);
>  	cancel_work_sync(&intel_dp->psr.work);
> +	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
>  }
> 
>  /**
> @@ -2324,6 +2371,7 @@ void intel_psr_pause(struct intel_dp *intel_dp)
>  	mutex_unlock(&psr->lock);
> 
>  	cancel_work_sync(&psr->work);
> +	cancel_delayed_work_sync(&psr->dc3co_work);
>  }
> 
>  /**
> @@ -3558,6 +3606,7 @@ void intel_psr_flush(struct intel_display *display,
>  		if (origin == ORIGIN_FLIP ||
>  		    (origin == ORIGIN_CURSOR_UPDATE &&
>  		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
> +			psr2_dc3co_flush_locked(intel_dp, frontbuffer_bits,
> origin);
>  			goto unlock;
>  		}
> 
> @@ -3616,6 +3665,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
>  		intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
> 
>  	INIT_WORK(&intel_dp->psr.work, intel_psr_work);
> +	INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work,
> psr2_dc3co_disable_work);
>  	mutex_init(&intel_dp->psr.lock);
>  }
> 
> --
> 2.43.0

Re: [PATCH v2 07/13] drm/i915/display: Add DC3CO eligibility computation

[Dibin Moolakadan Subrahmanian]

On 27-04-2026 08:40, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Sent: Wednesday, April 22, 2026 9:56 PM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>; Kurmi, Suresh Kumar
>> <suresh.kumar.kurmi@intel.com>
>> Subject: [PATCH v2 07/13] drm/i915/display: Add DC3CO eligibility computation
>>
>> Compute DC3CO eligibility during atomic_check based on pipe/port constraints
>> and runtime triggers and store result in display->power.dc3co.
>>
>> When DC3CO is allowed, request DC_STATE_EN_UPTO_DC3CO and reduce the
>> DC entry delay. Otherwise, retain the existing delay and set default
>> DC_STATE_EN_UPTO_DC6 .
>>
>> Changes in v2:
>> - Move dc3co state from intel_atomic_state to display->power (Uma Shankar)
>> - Use #define bitmasks instead of enum for DC3CO triggers (Jani Nikula)
>>
>> BSpec: 75253
>> Signed-off-by: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c  | 92 ++++++++++++++++++-
>> drivers/gpu/drm/i915/display/intel_display.h  |  1 -
>> .../gpu/drm/i915/display/intel_display_core.h |  3 +-
>>   .../drm/i915/display/intel_display_power.c    | 30 ++++++
>>   .../drm/i915/display/intel_display_power.h    | 22 +++++
>>   5 files changed, 141 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index 674a4ece6d0f..de493d04a622 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -5870,6 +5870,69 @@ static bool intel_pipes_need_modeset(struct
>> intel_atomic_state *state,
>>   	return false;
>>   }
>>
>> +static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
>> +					     const struct intel_crtc_state
>> *crtc_state) {
>> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> +	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
>> +	enum port port = dig_port->base.port;
>> +	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
>> +
>> +	return num_pipes == 1 && pipe <= PIPE_B && port <= PORT_B; }
>> +
>> +static void intel_dc3co_compute_state(struct intel_atomic_state *state)
>> +{
>> +	struct intel_display *display = to_intel_display(state);
>> +	struct intel_crtc *crtc;
>> +	struct intel_crtc_state *crtc_state;
>> +	struct intel_encoder *encoder;
>> +	struct intel_dp *intel_dp;
>> +	int active_pipes = 0;
>> +	u32 trigger = DC3CO_TRIGGER_NONE;
>> +
>> +	if (!HAS_DC3CO(display))
>> +		return;
>> +
>> +	for_each_intel_crtc(display->drm, crtc) {
>> +		trigger = DC3CO_TRIGGER_NONE;
>> +		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
>> +		if (!crtc_state)
>> +			crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
>> +
>> +		if (!crtc_state || !crtc_state->hw.active)
>> +			continue;
>> +
>> +		active_pipes++;
>> +
>> +		if (active_pipes > 1)
>> +			goto done;
>> +
>> +		for_each_intel_encoder_mask(display->drm, encoder,
>> +					    crtc_state->uapi.encoder_mask) {
>> +			if (encoder->type != INTEL_OUTPUT_EDP)
>> +				goto done;
>> +
>> +			intel_dp = enc_to_intel_dp(encoder);
>> +
>> +			if (!intel_dc3co_port_pipe_compatible(intel_dp,
>> crtc_state))
>> +				goto done;
>> +		}
>> +
>> +		if (crtc_state->has_lobf)
>> +			trigger |= DC3CO_TRIGGER_LOBF;
>> +		if (crtc_state->has_panel_replay)
>> +			trigger |= DC3CO_TRIGGER_PANEL_REPLAY;
>> +		if (crtc_state->has_sel_update)
>> +			trigger |= DC3CO_TRIGGER_PSR2;
> These values will get updated even if active pipe count is 2. Please check once.

trigger is initialized with DC3CO_TRIGGER_NONE at the beginning for loop.
For the second active pipe, trigger will be set to DC3CO_TRIGGER_NONE
and the loop will break before trigger update here.

>
> With this fixed,
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>
> Note: Would be good to get feedback from Imre as well.

ok.

>
>> +	}
>> +
>> +done:
>> +	intel_display_power_dc3co_update(display, !!trigger, trigger);
>> +	drm_dbg_kms(display->drm, "DC3CO allowed=%d trigger=0x%x\n",
>> +		    !!trigger, trigger);
>> +}
>> +
>>   static int intel_atomic_check_joiner(struct intel_atomic_state *state,
>>   				     struct intel_crtc *primary_crtc)  { @@ -6544,6
>> +6607,7 @@ int intel_atomic_check(struct drm_device *dev,
>>   	if (ret)
>>   		goto fail;
>>
>> +	intel_dc3co_compute_state(state);
>>   	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>>   					    new_crtc_state, i) {
>>   		intel_color_assert_luts(new_crtc_state);
>> @@ -7415,6 +7479,7 @@ static void intel_atomic_commit_tail(struct
>> intel_atomic_state *state)
>>   	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
>>   	struct ref_tracker *wakeref = NULL;
>>   	int i;
>> +	int power_async_delay;
>>
>>   	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
>>   		intel_atomic_dsb_prepare(state, crtc); @@ -7621,11 +7686,28
>> @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>   		 */
>>   		intel_uncore_arm_unclaimed_mmio_detection(uncore);
>>   	}
>> -	/*
>> -	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
>> -	 * toggling overhead at and above 60 FPS.
>> -	 */
>> -	intel_display_power_put_async_delay(display,
>> POWER_DOMAIN_DC_OFF, wakeref, 17);
>> +
>> +	if (intel_display_power_dc3co_allowed(display) &&
>> +	    intel_display_power_dc3co_supported(display)) {
>> +		intel_display_power_set_target_dc_state(display,
>> DC_STATE_EN_UPTO_DC3CO);
>> +		/*
>> +		 * Use minimal re-enable delay to allow DC3CO entry on
>> +		 * the next idle frame, unlike the 17ms guard needed to
>> +		 * prevent DC5/DC6 toggling overhead at 60+ FPS.
>> +		 */
>> +		power_async_delay = 1;
>> +	} else {
>> +		/*
>> +		 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
>> +		 * toggling overhead at and above 60 FPS.
>> +		 */
>> +		intel_display_power_set_target_dc_state(display,
>> DC_STATE_EN_UPTO_DC6);
>> +		power_async_delay = 17;
>> +	}
>> +
>> +	intel_display_power_put_async_delay(display,
>> +					    POWER_DOMAIN_DC_OFF, wakeref,
>> power_async_delay);
>> +
>>   	intel_display_rpm_put(display, state->wakeref);
>>
>>   	/*
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
>> b/drivers/gpu/drm/i915/display/intel_display.h
>> index 1e76a455d7c4..2795e4b9e799 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display.h
>> @@ -521,5 +521,4 @@ bool assert_port_valid(struct intel_display *display, enum
>> port port);
>>
>>   bool intel_scanout_needs_vtd_wa(struct intel_display *display);  int
>> intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
>> -
>>   #endif
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index c5a07090cba6..13e9b986b6fc 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -535,7 +535,8 @@ struct intel_display {
>>
>>   	struct {
>>   		struct i915_power_domains domains;
>> -
>> +		/* DC3CO eligibility state */
>> +		struct intel_dc3co_state dc3co;
>>   		/* Shadow for DISPLAY_PHY_CONTROL which can't be safely
>> read */
>>   		u32 chv_phy_control;
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>> b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index f626803bbd88..ff1915be59c9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -372,6 +372,35 @@ bool intel_display_power_dc3co_supported(struct
>> intel_display *display)
>>   	return (power_domains->allowed_dc_mask &
>> DC_STATE_EN_UPTO_DC3CO) == DC_STATE_EN_UPTO_DC3CO;  }
>>
>> +void intel_display_power_dc3co_update(struct intel_display *display,
>> +				      bool allowed, u32 trigger)
>> +{
>> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
>> +
>> +	if (!HAS_DC3CO(display))
>> +		return;
>> +
>> +	mutex_lock(&dc3co->lock);
>> +	dc3co->allowed = allowed;
>> +	dc3co->trigger = trigger;
>> +	mutex_unlock(&dc3co->lock);
>> +}
>> +
>> +bool intel_display_power_dc3co_allowed(struct intel_display *display) {
>> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
>> +	bool allowed;
>> +
>> +	if (!HAS_DC3CO(display))
>> +		return false;
>> +
>> +	mutex_lock(&dc3co->lock);
>> +	allowed = dc3co->allowed;
>> +	mutex_unlock(&dc3co->lock);
>> +
>> +	return allowed;
>> +}
>> +
>>   static void __async_put_domains_mask(struct i915_power_domains
>> *power_domains,
>>   				     struct intel_power_domain_mask *mask)  {
>> @@ -1051,6 +1080,7 @@ int intel_power_domains_init(struct intel_display
>> *display)
>>   		sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
>>
>>   	mutex_init(&power_domains->lock);
>> +	mutex_init(&display->power.dc3co.lock);
>>
>>   	INIT_DELAYED_WORK(&power_domains->async_put_work,
>>   			  intel_display_power_put_async_work);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
>> b/drivers/gpu/drm/i915/display/intel_display_power.h
>> index 05880e9da89f..0b1a06f88ae5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> @@ -131,6 +131,25 @@ struct intel_power_domain_mask {
>>   	DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);  };
>>
>> +/*
>> + * DC3CO enabling triggers (bitmask).
>> + * DC3CO may be enabled when at least one of these triggers is active.
>> + * Additional constraints may still apply.
>> + */
>> +#define DC3CO_TRIGGER_NONE		(0)
>> +#define DC3CO_TRIGGER_PSR2		BIT(0)
>> +#define DC3CO_TRIGGER_LOBF		BIT(1)
>> +#define DC3CO_TRIGGER_PANEL_REPLAY	BIT(2)
>> +#define DC3CO_TRIGGER_ALL		(DC3CO_TRIGGER_PSR2 | \
>> +					 DC3CO_TRIGGER_LOBF | \
>> +					 DC3CO_TRIGGER_PANEL_REPLAY)
>> +
>> +struct intel_dc3co_state {
>> +	struct mutex lock; /* Protects allowed and trigger fields */
>> +	bool allowed; /* DC3CO eligibility result */
>> +	u32 trigger; /* Bitmask of active DC3CO triggers */ };
>> +
>>   struct i915_power_domains {
>>   	/*
>>   	 * Power wells needed for initialization at driver init and suspend @@ -
>> 187,6 +206,9 @@ void intel_display_power_set_target_dc_state(struct
>> intel_display *display,
>>   					     u32 state);
>>   u32 intel_display_power_get_current_dc_state(struct intel_display *display);  bool
>> intel_display_power_dc3co_supported(struct intel_display *display);
>> +void intel_display_power_dc3co_update(struct intel_display *display,
>> +				      bool allowed, u32 trigger);
>> +bool intel_display_power_dc3co_allowed(struct intel_display *display);
>>
>>   bool intel_display_power_is_enabled(struct intel_display *display,
>>   				    enum intel_display_power_domain domain);
>> --
>> 2.43.0

RE: [PATCH v2 05/13] drm/i915/display: Add DC3CO support check and validate target DC state

[Manna, Animesh]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Wednesday, April 22, 2026 9:56 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kurmi, Suresh Kumar
> <suresh.kumar.kurmi@intel.com>
> Subject: [PATCH v2 05/13] drm/i915/display: Add DC3CO support check and
> validate target DC state
> 
> Validate the requested target DC state against allowed_dc_mask in
> intel_display_power_set_target_dc_state() to avoid programming
> unsupported DC states.
> 
> Also add intel_display_power_dc3co_supported() helper to query DC3CO
> support from allowed_dc_mask.
> 
> Changes in v2:
> - Squash "Add helper to check DC3CO support" patch into this patch
> 
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 14 ++++++++++++++
> drivers/gpu/drm/i915/display/intel_display_power.h |  1 +
>  2 files changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 77c32492caa1..f626803bbd88 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -302,6 +302,13 @@ void
> intel_display_power_set_target_dc_state(struct intel_display *display,
>  	struct i915_power_domains *power_domains = &display-
> >power.domains;
> 
>  	mutex_lock(&power_domains->lock);
> +
> +	if ((state & power_domains->allowed_dc_mask) != state) {
> +		drm_dbg_kms(display->drm,
> +			    "Rejecting DC state 0x%x (allowed mask 0x%x)\n",
> +			     state, power_domains->allowed_dc_mask);
> +		goto unlock;
> +	}
>  	power_well = lookup_power_well(display, SKL_DISP_DC_OFF);
> 
>  	if (drm_WARN_ON(display->drm, !power_well)) @@ -358,6 +365,13
> @@ u32 intel_display_power_get_current_dc_state(struct intel_display
> *display)
>  	return current_dc_state;
>  }
> 
> +bool intel_display_power_dc3co_supported(struct intel_display *display)
> +{
> +	struct i915_power_domains *power_domains = &display-
> >power.domains;
> +
> +	return (power_domains->allowed_dc_mask &
> DC_STATE_EN_UPTO_DC3CO) ==
> +DC_STATE_EN_UPTO_DC3CO; }
> +

allowed_dc_mask is not set in this patch series, which I presume will be based on HAS_DC3CO() check.
Could not differentiate between intel_display_power_dc3co_supported() and HAS_DC3CO() and both are dependent only on DISPLAY_VER() like if platform is supporting or not.

Regards,
Animesh

>  static void __async_put_domains_mask(struct i915_power_domains
> *power_domains,
>  				     struct intel_power_domain_mask *mask)
> { diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index d616d5d09cbe..05880e9da89f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -186,6 +186,7 @@ void intel_display_power_resume(struct intel_display
> *display);  void intel_display_power_set_target_dc_state(struct intel_display
> *display,
>  					     u32 state);
>  u32 intel_display_power_get_current_dc_state(struct intel_display
> *display);
> +bool intel_display_power_dc3co_supported(struct intel_display
> +*display);
> 
>  bool intel_display_power_is_enabled(struct intel_display *display,
>  				    enum intel_display_power_domain
> domain);
> --
> 2.43.0

RE: [PATCH v2 07/13] drm/i915/display: Add DC3CO eligibility computation

[Manna, Animesh]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Wednesday, April 22, 2026 9:56 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kurmi, Suresh Kumar
> <suresh.kumar.kurmi@intel.com>
> Subject: [PATCH v2 07/13] drm/i915/display: Add DC3CO eligibility
> computation
> 
> Compute DC3CO eligibility during atomic_check based on pipe/port
> constraints and runtime triggers and store result in display->power.dc3co.
> 
> When DC3CO is allowed, request DC_STATE_EN_UPTO_DC3CO and reduce
> the DC entry delay. Otherwise, retain the existing delay and set default
> DC_STATE_EN_UPTO_DC6 .
> 
> Changes in v2:
> - Move dc3co state from intel_atomic_state to display->power (Uma
> Shankar)
> - Use #define bitmasks instead of enum for DC3CO triggers (Jani Nikula)
> 
> BSpec: 75253
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 92 ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_display.h  |  1 -
> .../gpu/drm/i915/display/intel_display_core.h |  3 +-
>  .../drm/i915/display/intel_display_power.c    | 30 ++++++
>  .../drm/i915/display/intel_display_power.h    | 22 +++++
>  5 files changed, 141 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 674a4ece6d0f..de493d04a622 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5870,6 +5870,69 @@ static bool intel_pipes_need_modeset(struct
> intel_atomic_state *state,
>  	return false;
>  }
> 
> +static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
> +					     const struct intel_crtc_state
> *crtc_state) {
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> +	enum port port = dig_port->base.port;
> +	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
> +
> +	return num_pipes == 1 && pipe <= PIPE_B && port <= PORT_B; }
> +
> +static void intel_dc3co_compute_state(struct intel_atomic_state *state)
> +{
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_crtc *crtc;
> +	struct intel_crtc_state *crtc_state;
> +	struct intel_encoder *encoder;
> +	struct intel_dp *intel_dp;
> +	int active_pipes = 0;
> +	u32 trigger = DC3CO_TRIGGER_NONE;
> +
> +	if (!HAS_DC3CO(display))
> +		return;
> +
> +	for_each_intel_crtc(display->drm, crtc) {
> +		trigger = DC3CO_TRIGGER_NONE;
> +		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> +		if (!crtc_state)
> +			crtc_state = intel_atomic_get_old_crtc_state(state,
> crtc);

New crtc_state is overwritten with old_crtc_state and used below. Not clear about the need of new_crtc_state.
Maybe good to explain with a code comment how new_crtc_state and old_crtc_state used in this function.
Better to keep separate variable new_crtc_state/old_crtc_sate  and use as per need.
  
> +
> +		if (!crtc_state || !crtc_state->hw.active)
> +			continue;
> +
> +		active_pipes++;
> +
> +		if (active_pipes > 1)
> +			goto done;
> +
> +		for_each_intel_encoder_mask(display->drm, encoder,
> +					    crtc_state->uapi.encoder_mask) {
> +			if (encoder->type != INTEL_OUTPUT_EDP)
> +				goto done;

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) can be used which will use crtc_state and the above looping can be avoided.

> +
> +			intel_dp = enc_to_intel_dp(encoder);
> +
> +			if (!intel_dc3co_port_pipe_compatible(intel_dp,
> crtc_state))
> +				goto done;
> +		}
> +
> +		if (crtc_state->has_lobf)
> +			trigger |= DC3CO_TRIGGER_LOBF;
> +		if (crtc_state->has_panel_replay)
> +			trigger |= DC3CO_TRIGGER_PANEL_REPLAY;
> +		if (crtc_state->has_sel_update)
> +			trigger |= DC3CO_TRIGGER_PSR2;
> +	}
> +
> +done:
> +	intel_display_power_dc3co_update(display, !!trigger, trigger);

Not sure the usage of !!trigger, maybe just pass the trigger and if it is not zero then set the allowed inside intel_display_power_dc3co_update().

Regards,
Animesh
 
> +	drm_dbg_kms(display->drm, "DC3CO allowed=%d trigger=0x%x\n",
> +		    !!trigger, trigger);
> +}
> +
>  static int intel_atomic_check_joiner(struct intel_atomic_state *state,
>  				     struct intel_crtc *primary_crtc)  { @@ -
> 6544,6 +6607,7 @@ int intel_atomic_check(struct drm_device *dev,
>  	if (ret)
>  		goto fail;
> 
> +	intel_dc3co_compute_state(state);
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>  					    new_crtc_state, i) {
>  		intel_color_assert_luts(new_crtc_state);
> @@ -7415,6 +7479,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
>  	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] =
> {};
>  	struct ref_tracker *wakeref = NULL;
>  	int i;
> +	int power_async_delay;
> 
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
>  		intel_atomic_dsb_prepare(state, crtc); @@ -7621,11
> +7686,28 @@ static void intel_atomic_commit_tail(struct intel_atomic_state
> *state)
>  		 */
>  		intel_uncore_arm_unclaimed_mmio_detection(uncore);
>  	}
> -	/*
> -	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
> -	 * toggling overhead at and above 60 FPS.
> -	 */
> -	intel_display_power_put_async_delay(display,
> POWER_DOMAIN_DC_OFF, wakeref, 17);
> +
> +	if (intel_display_power_dc3co_allowed(display) &&
> +	    intel_display_power_dc3co_supported(display)) {
> +		intel_display_power_set_target_dc_state(display,
> DC_STATE_EN_UPTO_DC3CO);
> +		/*
> +		 * Use minimal re-enable delay to allow DC3CO entry on
> +		 * the next idle frame, unlike the 17ms guard needed to
> +		 * prevent DC5/DC6 toggling overhead at 60+ FPS.
> +		 */
> +		power_async_delay = 1;
> +	} else {
> +		/*
> +		 * Delay re-enabling DC states by 17 ms to avoid the off->on-
> >off
> +		 * toggling overhead at and above 60 FPS.
> +		 */
> +		intel_display_power_set_target_dc_state(display,
> DC_STATE_EN_UPTO_DC6);
> +		power_async_delay = 17;
> +	}
> +
> +	intel_display_power_put_async_delay(display,
> +					    POWER_DOMAIN_DC_OFF,
> wakeref, power_async_delay);
> +
>  	intel_display_rpm_put(display, state->wakeref);
> 
>  	/*
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 1e76a455d7c4..2795e4b9e799 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -521,5 +521,4 @@ bool assert_port_valid(struct intel_display *display,
> enum port port);
> 
>  bool intel_scanout_needs_vtd_wa(struct intel_display *display);  int
> intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
> -
>  #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index c5a07090cba6..13e9b986b6fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -535,7 +535,8 @@ struct intel_display {
> 
>  	struct {
>  		struct i915_power_domains domains;
> -
> +		/* DC3CO eligibility state */
> +		struct intel_dc3co_state dc3co;
>  		/* Shadow for DISPLAY_PHY_CONTROL which can't be safely
> read */
>  		u32 chv_phy_control;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index f626803bbd88..ff1915be59c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -372,6 +372,35 @@ bool intel_display_power_dc3co_supported(struct
> intel_display *display)
>  	return (power_domains->allowed_dc_mask &
> DC_STATE_EN_UPTO_DC3CO) == DC_STATE_EN_UPTO_DC3CO;  }
> 
> +void intel_display_power_dc3co_update(struct intel_display *display,
> +				      bool allowed, u32 trigger)
> +{
> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
> +
> +	if (!HAS_DC3CO(display))
> +		return;
> +
> +	mutex_lock(&dc3co->lock);
> +	dc3co->allowed = allowed;
> +	dc3co->trigger = trigger;
> +	mutex_unlock(&dc3co->lock);
> +}
> +
> +bool intel_display_power_dc3co_allowed(struct intel_display *display) {
> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
> +	bool allowed;
> +
> +	if (!HAS_DC3CO(display))
> +		return false;
> +
> +	mutex_lock(&dc3co->lock);
> +	allowed = dc3co->allowed;
> +	mutex_unlock(&dc3co->lock);
> +
> +	return allowed;
> +}
> +
>  static void __async_put_domains_mask(struct i915_power_domains
> *power_domains,
>  				     struct intel_power_domain_mask *mask)
> { @@ -1051,6 +1080,7 @@ int intel_power_domains_init(struct intel_display
> *display)
>  		sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
> 
>  	mutex_init(&power_domains->lock);
> +	mutex_init(&display->power.dc3co.lock);
> 
>  	INIT_DELAYED_WORK(&power_domains->async_put_work,
>  			  intel_display_power_put_async_work);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 05880e9da89f..0b1a06f88ae5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -131,6 +131,25 @@ struct intel_power_domain_mask {
>  	DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);  };
> 
> +/*
> + * DC3CO enabling triggers (bitmask).
> + * DC3CO may be enabled when at least one of these triggers is active.
> + * Additional constraints may still apply.
> + */
> +#define DC3CO_TRIGGER_NONE		(0)
> +#define DC3CO_TRIGGER_PSR2		BIT(0)
> +#define DC3CO_TRIGGER_LOBF		BIT(1)
> +#define DC3CO_TRIGGER_PANEL_REPLAY	BIT(2)
> +#define DC3CO_TRIGGER_ALL		(DC3CO_TRIGGER_PSR2 | \
> +					 DC3CO_TRIGGER_LOBF | \
> +					 DC3CO_TRIGGER_PANEL_REPLAY)
> +
> +struct intel_dc3co_state {
> +	struct mutex lock; /* Protects allowed and trigger fields */
> +	bool allowed; /* DC3CO eligibility result */
> +	u32 trigger; /* Bitmask of active DC3CO triggers */ };
> +
>  struct i915_power_domains {
>  	/*
>  	 * Power wells needed for initialization at driver init and suspend
> @@ -187,6 +206,9 @@ void intel_display_power_set_target_dc_state(struct
> intel_display *display,
>  					     u32 state);
>  u32 intel_display_power_get_current_dc_state(struct intel_display
> *display);  bool intel_display_power_dc3co_supported(struct intel_display
> *display);
> +void intel_display_power_dc3co_update(struct intel_display *display,
> +				      bool allowed, u32 trigger);
> +bool intel_display_power_dc3co_allowed(struct intel_display *display);
> 
>  bool intel_display_power_is_enabled(struct intel_display *display,
>  				    enum intel_display_power_domain
> domain);
> --
> 2.43.0

Re: [PATCH v2 07/13] drm/i915/display: Add DC3CO eligibility computation

[Dibin Moolakadan Subrahmanian]

On 29-04-2026 11:12, Manna, Animesh wrote:
>
>> -----Original Message-----
>> From: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Sent: Wednesday, April 22, 2026 9:56 PM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>; Kurmi, Suresh Kumar
>> <suresh.kumar.kurmi@intel.com>
>> Subject: [PATCH v2 07/13] drm/i915/display: Add DC3CO eligibility
>> computation
>>
>> Compute DC3CO eligibility during atomic_check based on pipe/port
>> constraints and runtime triggers and store result in display->power.dc3co.
>>
>> When DC3CO is allowed, request DC_STATE_EN_UPTO_DC3CO and reduce
>> the DC entry delay. Otherwise, retain the existing delay and set default
>> DC_STATE_EN_UPTO_DC6 .
>>
>> Changes in v2:
>> - Move dc3co state from intel_atomic_state to display->power (Uma
>> Shankar)
>> - Use #define bitmasks instead of enum for DC3CO triggers (Jani Nikula)
>>
>> BSpec: 75253
>> Signed-off-by: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c  | 92 ++++++++++++++++++-
>> drivers/gpu/drm/i915/display/intel_display.h  |  1 -
>> .../gpu/drm/i915/display/intel_display_core.h |  3 +-
>>   .../drm/i915/display/intel_display_power.c    | 30 ++++++
>>   .../drm/i915/display/intel_display_power.h    | 22 +++++
>>   5 files changed, 141 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index 674a4ece6d0f..de493d04a622 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -5870,6 +5870,69 @@ static bool intel_pipes_need_modeset(struct
>> intel_atomic_state *state,
>>   	return false;
>>   }
>>
>> +static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
>> +					     const struct intel_crtc_state
>> *crtc_state) {
>> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> +	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
>> +	enum port port = dig_port->base.port;
>> +	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
>> +
>> +	return num_pipes == 1 && pipe <= PIPE_B && port <= PORT_B; }
>> +
>> +static void intel_dc3co_compute_state(struct intel_atomic_state *state)
>> +{
>> +	struct intel_display *display = to_intel_display(state);
>> +	struct intel_crtc *crtc;
>> +	struct intel_crtc_state *crtc_state;
>> +	struct intel_encoder *encoder;
>> +	struct intel_dp *intel_dp;
>> +	int active_pipes = 0;
>> +	u32 trigger = DC3CO_TRIGGER_NONE;
>> +
>> +	if (!HAS_DC3CO(display))
>> +		return;
>> +
>> +	for_each_intel_crtc(display->drm, crtc) {
>> +		trigger = DC3CO_TRIGGER_NONE;
>> +		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
>> +		if (!crtc_state)
>> +			crtc_state = intel_atomic_get_old_crtc_state(state,
>> crtc);
> New crtc_state is overwritten with old_crtc_state and used below. Not clear about the need of new_crtc_state.
> Maybe good to explain with a code comment how new_crtc_state and old_crtc_state used in this function.
> Better to keep separate variable new_crtc_state/old_crtc_sate  and use as per need.
>    

The assignment from old_crtc_state occurs only if intel_atomic_get_new_crtc_state() returns NULL.
For the DC3CO 'allow' decision must consider 'untouched' pipes as well.
This design maintains a single variable to simplify the unified evaluation logic.
I can add comment if needed.

>> +
>> +		if (!crtc_state || !crtc_state->hw.active)
>> +			continue;
>> +
>> +		active_pipes++;
>> +
>> +		if (active_pipes > 1)
>> +			goto done;
>> +
>> +		for_each_intel_encoder_mask(display->drm, encoder,
>> +					    crtc_state->uapi.encoder_mask) {
>> +			if (encoder->type != INTEL_OUTPUT_EDP)
>> +				goto done;
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) can be used which will use crtc_state and the above looping can be avoided.
>
>> +
>> +			intel_dp = enc_to_intel_dp(encoder);
>> +
>> +			if (!intel_dc3co_port_pipe_compatible(intel_dp,
>> crtc_state))
>> +				goto done;
>> +		}
>> +
>> +		if (crtc_state->has_lobf)
>> +			trigger |= DC3CO_TRIGGER_LOBF;
>> +		if (crtc_state->has_panel_replay)
>> +			trigger |= DC3CO_TRIGGER_PANEL_REPLAY;
>> +		if (crtc_state->has_sel_update)
>> +			trigger |= DC3CO_TRIGGER_PSR2;
>> +	}
>> +
>> +done:
>> +	intel_display_power_dc3co_update(display, !!trigger, trigger);
> Not sure the usage of !!trigger, maybe just pass the trigger and if it is not zero then set the allowed inside intel_display_power_dc3co_update().

The use of !!trigger is intentional.
It's commonly used in the kernel to normalize a bitmask to a boolean.

>
> Regards,
> Animesh
>   
>> +	drm_dbg_kms(display->drm, "DC3CO allowed=%d trigger=0x%x\n",
>> +		    !!trigger, trigger);
>> +}
>> +
>>   static int intel_atomic_check_joiner(struct intel_atomic_state *state,
>>   				     struct intel_crtc *primary_crtc)  { @@ -
>> 6544,6 +6607,7 @@ int intel_atomic_check(struct drm_device *dev,
>>   	if (ret)
>>   		goto fail;
>>
>> +	intel_dc3co_compute_state(state);
>>   	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>>   					    new_crtc_state, i) {
>>   		intel_color_assert_luts(new_crtc_state);
>> @@ -7415,6 +7479,7 @@ static void intel_atomic_commit_tail(struct
>> intel_atomic_state *state)
>>   	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] =
>> {};
>>   	struct ref_tracker *wakeref = NULL;
>>   	int i;
>> +	int power_async_delay;
>>
>>   	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
>>   		intel_atomic_dsb_prepare(state, crtc); @@ -7621,11
>> +7686,28 @@ static void intel_atomic_commit_tail(struct intel_atomic_state
>> *state)
>>   		 */
>>   		intel_uncore_arm_unclaimed_mmio_detection(uncore);
>>   	}
>> -	/*
>> -	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
>> -	 * toggling overhead at and above 60 FPS.
>> -	 */
>> -	intel_display_power_put_async_delay(display,
>> POWER_DOMAIN_DC_OFF, wakeref, 17);
>> +
>> +	if (intel_display_power_dc3co_allowed(display) &&
>> +	    intel_display_power_dc3co_supported(display)) {
>> +		intel_display_power_set_target_dc_state(display,
>> DC_STATE_EN_UPTO_DC3CO);
>> +		/*
>> +		 * Use minimal re-enable delay to allow DC3CO entry on
>> +		 * the next idle frame, unlike the 17ms guard needed to
>> +		 * prevent DC5/DC6 toggling overhead at 60+ FPS.
>> +		 */
>> +		power_async_delay = 1;
>> +	} else {
>> +		/*
>> +		 * Delay re-enabling DC states by 17 ms to avoid the off->on-
>>> off
>> +		 * toggling overhead at and above 60 FPS.
>> +		 */
>> +		intel_display_power_set_target_dc_state(display,
>> DC_STATE_EN_UPTO_DC6);
>> +		power_async_delay = 17;
>> +	}
>> +
>> +	intel_display_power_put_async_delay(display,
>> +					    POWER_DOMAIN_DC_OFF,
>> wakeref, power_async_delay);
>> +
>>   	intel_display_rpm_put(display, state->wakeref);
>>
>>   	/*
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
>> b/drivers/gpu/drm/i915/display/intel_display.h
>> index 1e76a455d7c4..2795e4b9e799 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display.h
>> @@ -521,5 +521,4 @@ bool assert_port_valid(struct intel_display *display,
>> enum port port);
>>
>>   bool intel_scanout_needs_vtd_wa(struct intel_display *display);  int
>> intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
>> -
>>   #endif
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index c5a07090cba6..13e9b986b6fc 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -535,7 +535,8 @@ struct intel_display {
>>
>>   	struct {
>>   		struct i915_power_domains domains;
>> -
>> +		/* DC3CO eligibility state */
>> +		struct intel_dc3co_state dc3co;
>>   		/* Shadow for DISPLAY_PHY_CONTROL which can't be safely
>> read */
>>   		u32 chv_phy_control;
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>> b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index f626803bbd88..ff1915be59c9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -372,6 +372,35 @@ bool intel_display_power_dc3co_supported(struct
>> intel_display *display)
>>   	return (power_domains->allowed_dc_mask &
>> DC_STATE_EN_UPTO_DC3CO) == DC_STATE_EN_UPTO_DC3CO;  }
>>
>> +void intel_display_power_dc3co_update(struct intel_display *display,
>> +				      bool allowed, u32 trigger)
>> +{
>> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
>> +
>> +	if (!HAS_DC3CO(display))
>> +		return;
>> +
>> +	mutex_lock(&dc3co->lock);
>> +	dc3co->allowed = allowed;
>> +	dc3co->trigger = trigger;
>> +	mutex_unlock(&dc3co->lock);
>> +}
>> +
>> +bool intel_display_power_dc3co_allowed(struct intel_display *display) {
>> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
>> +	bool allowed;
>> +
>> +	if (!HAS_DC3CO(display))
>> +		return false;
>> +
>> +	mutex_lock(&dc3co->lock);
>> +	allowed = dc3co->allowed;
>> +	mutex_unlock(&dc3co->lock);
>> +
>> +	return allowed;
>> +}
>> +
>>   static void __async_put_domains_mask(struct i915_power_domains
>> *power_domains,
>>   				     struct intel_power_domain_mask *mask)
>> { @@ -1051,6 +1080,7 @@ int intel_power_domains_init(struct intel_display
>> *display)
>>   		sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
>>
>>   	mutex_init(&power_domains->lock);
>> +	mutex_init(&display->power.dc3co.lock);
>>
>>   	INIT_DELAYED_WORK(&power_domains->async_put_work,
>>   			  intel_display_power_put_async_work);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
>> b/drivers/gpu/drm/i915/display/intel_display_power.h
>> index 05880e9da89f..0b1a06f88ae5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> @@ -131,6 +131,25 @@ struct intel_power_domain_mask {
>>   	DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);  };
>>
>> +/*
>> + * DC3CO enabling triggers (bitmask).
>> + * DC3CO may be enabled when at least one of these triggers is active.
>> + * Additional constraints may still apply.
>> + */
>> +#define DC3CO_TRIGGER_NONE		(0)
>> +#define DC3CO_TRIGGER_PSR2		BIT(0)
>> +#define DC3CO_TRIGGER_LOBF		BIT(1)
>> +#define DC3CO_TRIGGER_PANEL_REPLAY	BIT(2)
>> +#define DC3CO_TRIGGER_ALL		(DC3CO_TRIGGER_PSR2 | \
>> +					 DC3CO_TRIGGER_LOBF | \
>> +					 DC3CO_TRIGGER_PANEL_REPLAY)
>> +
>> +struct intel_dc3co_state {
>> +	struct mutex lock; /* Protects allowed and trigger fields */
>> +	bool allowed; /* DC3CO eligibility result */
>> +	u32 trigger; /* Bitmask of active DC3CO triggers */ };
>> +
>>   struct i915_power_domains {
>>   	/*
>>   	 * Power wells needed for initialization at driver init and suspend
>> @@ -187,6 +206,9 @@ void intel_display_power_set_target_dc_state(struct
>> intel_display *display,
>>   					     u32 state);
>>   u32 intel_display_power_get_current_dc_state(struct intel_display
>> *display);  bool intel_display_power_dc3co_supported(struct intel_display
>> *display);
>> +void intel_display_power_dc3co_update(struct intel_display *display,
>> +				      bool allowed, u32 trigger);
>> +bool intel_display_power_dc3co_allowed(struct intel_display *display);
>>
>>   bool intel_display_power_is_enabled(struct intel_display *display,
>>   				    enum intel_display_power_domain
>> domain);
>> --
>> 2.43.0

Re: [PATCH v2 05/13] drm/i915/display: Add DC3CO support check and validate target DC state

[Dibin Moolakadan Subrahmanian]

On 29-04-2026 10:43, Manna, Animesh wrote:
>
>> -----Original Message-----
>> From: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Sent: Wednesday, April 22, 2026 9:56 PM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>; Kurmi, Suresh Kumar
>> <suresh.kumar.kurmi@intel.com>
>> Subject: [PATCH v2 05/13] drm/i915/display: Add DC3CO support check and
>> validate target DC state
>>
>> Validate the requested target DC state against allowed_dc_mask in
>> intel_display_power_set_target_dc_state() to avoid programming
>> unsupported DC states.
>>
>> Also add intel_display_power_dc3co_supported() helper to query DC3CO
>> support from allowed_dc_mask.
>>
>> Changes in v2:
>> - Squash "Add helper to check DC3CO support" patch into this patch
>>
>> Signed-off-by: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display_power.c | 14 ++++++++++++++
>> drivers/gpu/drm/i915/display/intel_display_power.h |  1 +
>>   2 files changed, 15 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>> b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 77c32492caa1..f626803bbd88 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -302,6 +302,13 @@ void
>> intel_display_power_set_target_dc_state(struct intel_display *display,
>>   	struct i915_power_domains *power_domains = &display-
>>> power.domains;
>>   	mutex_lock(&power_domains->lock);
>> +
>> +	if ((state & power_domains->allowed_dc_mask) != state) {
>> +		drm_dbg_kms(display->drm,
>> +			    "Rejecting DC state 0x%x (allowed mask 0x%x)\n",
>> +			     state, power_domains->allowed_dc_mask);
>> +		goto unlock;
>> +	}
>>   	power_well = lookup_power_well(display, SKL_DISP_DC_OFF);
>>
>>   	if (drm_WARN_ON(display->drm, !power_well)) @@ -358,6 +365,13
>> @@ u32 intel_display_power_get_current_dc_state(struct intel_display
>> *display)
>>   	return current_dc_state;
>>   }
>>
>> +bool intel_display_power_dc3co_supported(struct intel_display *display)
>> +{
>> +	struct i915_power_domains *power_domains = &display-
>>> power.domains;
>> +
>> +	return (power_domains->allowed_dc_mask &
>> DC_STATE_EN_UPTO_DC3CO) ==
>> +DC_STATE_EN_UPTO_DC3CO; }
>> +
> allowed_dc_mask is not set in this patch series, which I presume will be based on HAS_DC3CO() check.
> Could not differentiate between intel_display_power_dc3co_supported() and HAS_DC3CO() and both are dependent only on DISPLAY_VER() like if platform is supporting or not.

HAS_DC3CO() checks for the HW capablity.
intel_display_power_dc3co_supported() checks if dc3co is supported at runtime.
it check DC3CO against power_domains->allowed_dc_mask which is assigned at in intel_power_domains_init()
based on params.enable_dc , allowing the feature to be controlled via module parameters.

> Regards,
> Animesh
>
>>   static void __async_put_domains_mask(struct i915_power_domains
>> *power_domains,
>>   				     struct intel_power_domain_mask *mask)
>> { diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
>> b/drivers/gpu/drm/i915/display/intel_display_power.h
>> index d616d5d09cbe..05880e9da89f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> @@ -186,6 +186,7 @@ void intel_display_power_resume(struct intel_display
>> *display);  void intel_display_power_set_target_dc_state(struct intel_display
>> *display,
>>   					     u32 state);
>>   u32 intel_display_power_get_current_dc_state(struct intel_display
>> *display);
>> +bool intel_display_power_dc3co_supported(struct intel_display
>> +*display);
>>
>>   bool intel_display_power_is_enabled(struct intel_display *display,
>>   				    enum intel_display_power_domain
>> domain);
>> --
>> 2.43.0