Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: "Laguna, Lukasz" <lukasz.laguna@intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>,
	Matthew Brost <matthew.brost@intel.com>
Cc: <intel-xe@lists.freedesktop.org>
Subject: Re: [PATCH 11/12] drm/xe/pf: Add TLB invalidation support for MERT
Date: Tue, 28 Oct 2025 10:33:05 +0100	[thread overview]
Message-ID: <33aff812-d941-43e1-910c-afe33e168e9d@intel.com> (raw)
In-Reply-To: <a3mxo7dyi4lg4hj6looiw6ig7dto75ryjspwfcyonint6kfvcz@mvrk6ypi5vdc>


On 10/23/2025 17:11, Lucas De Marchi wrote:
> On Wed, Oct 22, 2025 at 11:28:19AM -0700, Matthew Brost wrote:
>> On Tue, Oct 21, 2025 at 10:17:43PM -0700, Lucas De Marchi wrote:
>>> From: Lukasz Laguna <lukasz.laguna@intel.com>
>>>
>>> Trigger MERT's TLB invalidation after LMTT updates ensuring memory
>>> translations remain coherent.
>>>
>>> Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com>
>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>> ---
>>>  drivers/gpu/drm/xe/regs/xe_mert_regs.h     |  3 +++
>>>  drivers/gpu/drm/xe/xe_device_types.h       |  6 ++++++
>>>  drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c | 19 +++++++++++++++++++
>>>  drivers/gpu/drm/xe/xe_irq.c                |  8 ++++++++
>>>  drivers/gpu/drm/xe/xe_sriov_pf.c           |  3 +++
>>>  5 files changed, 39 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/xe/regs/xe_mert_regs.h 
>>> b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
>>> index 5b7c15e08747e..aef66c04901d2 100644
>>> --- a/drivers/gpu/drm/xe/regs/xe_mert_regs.h
>>> +++ b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
>>> @@ -10,4 +10,7 @@
>>>
>>>  #define MERT_LMEM_CFG                XE_REG(0x1448b0)
>>>
>>> +#define MERT_TLB_INV_DESC_A            XE_REG(0x14cf7c)
>>> +#define   MERT_TLB_INV_DESC_A_VALID        REG_BIT(0)
>>> +
>>>  #endif /* _XE_MERT_REGS_H_ */
>>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h 
>>> b/drivers/gpu/drm/xe/xe_device_types.h
>>> index fb401809fae5a..6fcd35bee73b5 100644
>>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>>> @@ -219,6 +219,12 @@ struct xe_tile {
>>>
>>>      /** @debugfs: debugfs directory associated with this tile */
>>>      struct dentry *debugfs;
>>> +
>>> +    /** @mert: MERT-related data */
>>> +    struct {
>>> +        /** @mert.tlb_inv_done: completion of TLB invalidation */
>>> +        struct completion tlb_inv_done;
>>> +    } mert;
>>>  };
>>>
>>>  /**
>>> diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c 
>>> b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
>>> index c0c0215c07036..ebe81cb21f5ab 100644
>>> --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
>>> +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
>>> @@ -10,6 +10,7 @@
>>>  #include "abi/guc_klvs_abi.h"
>>>
>>>  #include "regs/xe_guc_regs.h"
>>> +#include "regs/xe_mert_regs.h"
>>>
>>>  #include "xe_bo.h"
>>>  #include "xe_device.h"
>>> @@ -31,6 +32,7 @@
>>>  #include "xe_lmtt.h"
>>>  #include "xe_map.h"
>>>  #include "xe_migrate.h"
>>> +#include "xe_mmio.h"
>>>  #include "xe_sriov.h"
>>>  #include "xe_ttm_vram_mgr.h"
>>>  #include "xe_vram_types.h"
>>> @@ -1346,6 +1348,20 @@ static int pf_distribute_config_lmem(struct 
>>> xe_gt *gt, unsigned int vfid, u64 si
>>>      return 0;
>>>  }
>>>
>>> +static void invalidate_mert_lmtt(struct xe_device *xe)
>>> +{
>>> +    const long timeout = HZ / 4;
>>> +    struct xe_tile *tile = xe_device_get_root_tile(xe);
>>> +
>>> +    xe_assert(xe, xe_device_has_mert(xe));
>>> +
>>
>> It is not obvious how upper layers which call this function get
>> exclusive access to what appears to be a per device resource.
>
> this is a static function that will only be called by the function
> below... I think the lockdep should rather be added in that entrypoint?
>
>>
>> Is xe_sriov_pf_master_mutex held here? If so, I'd add a lockdep assert
>> so this is self documenting on how exclusion is achieved and to prevent
>> misuse. If not, you probably need a lock here.
>

xe_sriov_pf_master_mutex is held here, but there can still be a race 
between reinit_completion() and complete(). I'll prepare a new locking 
approach.

Thanks,
Lukasz

> yep, but another question below for Lukasz or you...
>
>>
>> Matt
>>
>>> + reinit_completion(&tile->mert.tlb_inv_done);
>
> is that the right thing here? Is xe_sriov_pf_master_mutex preventing 2
> waiters?
>
> Lucas De Marchi
>
>>> +    xe_mmio_write32(&tile->mmio, MERT_TLB_INV_DESC_A, 
>>> MERT_TLB_INV_DESC_A_VALID);
>>> +
>>> +    if (!wait_for_completion_timeout(&tile->mert.tlb_inv_done, 
>>> timeout))
>>> +        drm_err(&xe->drm, "MERT TLB invalidation timeout\n");
>>> +}
>>> +
>>>  static void pf_force_lmtt_invalidate(struct xe_device *xe)
>>>  {
>>>      struct xe_lmtt *lmtt;
>>> @@ -1359,6 +1375,9 @@ static void pf_force_lmtt_invalidate(struct 
>>> xe_device *xe)
>>>          lmtt = &tile->sriov.pf.lmtt;
>>>          xe_lmtt_invalidate_hw(lmtt);
>>>      }
>>> +
>>> +    if (xe_device_has_mert(xe))
>>> +        invalidate_mert_lmtt(xe);
>>>  }
>>>
>>>  static void pf_reset_vf_lmtt(struct xe_device *xe, unsigned int vfid)
>>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>>> index 011b5eb66102f..82bf0d3995dfe 100644
>>> --- a/drivers/gpu/drm/xe/xe_irq.c
>>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>>> @@ -12,6 +12,7 @@
>>>  #include "display/xe_display.h"
>>>  #include "regs/xe_guc_regs.h"
>>>  #include "regs/xe_irq_regs.h"
>>> +#include "regs/xe_mert_regs.h"
>>>  #include "xe_device.h"
>>>  #include "xe_drv.h"
>>>  #include "xe_gsc_proxy.h"
>>> @@ -468,8 +469,15 @@ static void dg1_intr_enable(struct xe_device 
>>> *xe, bool stall)
>>>
>>>  static void mert_irq_handler(struct xe_device *xe, u32 master_ctl)
>>>  {
>>> +    struct xe_tile *tile = xe_device_get_root_tile(xe);
>>> +    u32 reg_val;
>>> +
>>>      if (!(master_ctl & SOC_H2DMEMINT_IRQ))
>>>          return;
>>> +
>>> +    reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_INV_DESC_A);
>>> +    if (!(reg_val & MERT_TLB_INV_DESC_A_VALID))
>>> +        complete(&tile->mert.tlb_inv_done);
>>>  }
>>>
>>>  /*
>>> diff --git a/drivers/gpu/drm/xe/xe_sriov_pf.c 
>>> b/drivers/gpu/drm/xe/xe_sriov_pf.c
>>> index bc1ab9ee31d92..b40701d75dacb 100644
>>> --- a/drivers/gpu/drm/xe/xe_sriov_pf.c
>>> +++ b/drivers/gpu/drm/xe/xe_sriov_pf.c
>>> @@ -88,6 +88,7 @@ bool xe_sriov_pf_readiness(struct xe_device *xe)
>>>   */
>>>  int xe_sriov_pf_init_early(struct xe_device *xe)
>>>  {
>>> +    struct xe_tile *root_tile = xe_device_get_root_tile(xe);
>>>      int err;
>>>
>>>      xe_assert(xe, IS_SRIOV_PF(xe));
>>> @@ -103,6 +104,8 @@ int xe_sriov_pf_init_early(struct xe_device *xe)
>>>
>>>      xe_sriov_pf_service_init(xe);
>>>
>>> +    init_completion(&root_tile->mert.tlb_inv_done);
>>> +
>>>      return 0;
>>>  }
>>>
>>>
>>> -- 
>>> 2.51.0
>>>

  reply	other threads:[~2025-10-28  9:33 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-22  5:17 [PATCH 00/12] drm/xe: Add support for Crescent Island Lucas De Marchi
2025-10-22  5:17 ` [PATCH 01/12] drm/xe/cri: Add CRI platform definition Lucas De Marchi
2025-10-22 14:58   ` Shekhar Chauhan
2025-10-22 19:45     ` Lucas De Marchi
2025-10-23 10:57       ` Lucas De Marchi
2025-10-23 11:13         ` Lucas De Marchi
2025-10-22  5:17 ` [PATCH 02/12] topic/for-xe-CI: drm/xe/cri: Define GuC firmware for CRI Lucas De Marchi
2025-10-23 10:33   ` Lucas De Marchi
2025-10-22  5:17 ` [PATCH 03/12] drm/xe/cri: Setup MOCS table Lucas De Marchi
2025-10-22  8:06   ` Vivekanandan, Balasubramani
2025-10-22  5:17 ` [PATCH 04/12] drm/xe/cri: Add new performance limit reasons bits Lucas De Marchi
2025-10-22  6:31   ` [PATCH 4/12] " Raag Jadav
2025-10-22 21:22     ` Lucas De Marchi
2025-10-22  5:17 ` [PATCH 05/12] drm/xe/cri: Add check to verify if CSC is a PCIe endpoint Lucas De Marchi
2025-10-22  5:17 ` [PATCH 06/12] drm/xe/pm: Enable D3cold WAKE# support Lucas De Marchi
2025-10-22  6:35   ` [PATCH 6/12] " Raag Jadav
2025-10-22 19:53     ` Lucas De Marchi
2025-10-22  5:17 ` [PATCH 07/12] drm/xe: Add device flag to indicate standalone MERT Lucas De Marchi
2025-10-28 21:53   ` Dixit, Ashutosh
2025-10-22  5:17 ` [PATCH 08/12] drm/xe/oa/uapi: Expose MERT OA unit Lucas De Marchi
2025-10-22 23:09   ` Umesh Nerlige Ramappa
2025-11-24 21:34     ` Dixit, Ashutosh
2025-10-22  5:17 ` [PATCH 09/12] drm/xe/pf: Configure LMTT in MERT Lucas De Marchi
2025-10-22  5:17 ` [PATCH 10/12] drm/xe: Handle MERT interrupts Lucas De Marchi
2025-10-22 23:19   ` Matt Roper
2025-10-23 14:42     ` Lucas De Marchi
2025-10-28  9:30       ` Laguna, Lukasz
2025-10-22  5:17 ` [PATCH 11/12] drm/xe/pf: Add TLB invalidation support for MERT Lucas De Marchi
2025-10-22 18:28   ` Matthew Brost
2025-10-23 15:11     ` Lucas De Marchi
2025-10-28  9:33       ` Laguna, Lukasz [this message]
2025-10-22  5:17 ` [PATCH 12/12] drm/xe/pf: Handle MERT catastrophic errors Lucas De Marchi
2025-10-22  5:40 ` ✗ CI.checkpatch: warning for drm/xe: Add support for Crescent Island Patchwork
2025-10-22  5:41 ` ✓ CI.KUnit: success " Patchwork
2025-10-22  6:29 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-22  7:56 ` ✗ Xe.CI.Full: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=33aff812-d941-43e1-910c-afe33e168e9d@intel.com \
    --to=lukasz.laguna@intel.com \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=lucas.demarchi@intel.com \
    --cc=matthew.brost@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox