From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 10/19] drm/i915/de: Simplify intel_de_read8()
Date: Tue, 09 Dec 2025 12:47:44 +0200 [thread overview]
Message-ID: <377ea121db5a593af09af8199ce318b945ba5859@intel.com> (raw)
In-Reply-To: <20251208182637.334-11-ville.syrjala@linux.intel.com>
On Mon, 08 Dec 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_de_read8() is only needed for VGA register MMIO access
> by the CRT code on gen2/3. Remove the redundant wakelock stuff,
> and add a platform check to make sure this won't get used on
> any platform where MMIO VGA register accesses don't work.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Not a fan of adding the extra dep on drm_print.h as I've tried hard to
remove it from headers all over the place to uncover the implicit
dependencies.
Oh well, maybe this will be addressed in the upcoming mmio series?
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_de.h | 13 +++++--------
> 1 file changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
> index a7ce3b875e06..5c1b37d30045 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -6,6 +6,8 @@
> #ifndef __INTEL_DE_H__
> #define __INTEL_DE_H__
>
> +#include <drm/drm_print.h>
> +
> #include "intel_display_core.h"
> #include "intel_dmc_wl.h"
> #include "intel_dsb.h"
> @@ -34,15 +36,10 @@ intel_de_read(struct intel_display *display, i915_reg_t reg)
> static inline u8
> intel_de_read8(struct intel_display *display, i915_reg_t reg)
> {
> - u8 val;
> + /* this is only used on VGA registers (possible on pre-g4x) */
> + drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x);
>
> - intel_dmc_wl_get(display, reg);
> -
> - val = intel_uncore_read8(__to_uncore(display), reg);
> -
> - intel_dmc_wl_put(display, reg);
> -
> - return val;
> + return intel_uncore_read8(__to_uncore(display), reg);
> }
>
> static inline u64
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-12-09 10:47 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-08 18:26 [PATCH 00/19] drm/i915/vga: Try to sort out the VGA decode mess Ville Syrjala
2025-12-08 18:26 ` [PATCH 01/19] drm/i915/vga: Register vgaarb client later Ville Syrjala
2025-12-09 10:23 ` Jani Nikula
2025-12-08 18:26 ` [PATCH 02/19] drm/i915/vga: Get rid of intel_vga_reset_io_mem() Ville Syrjala
2025-12-09 10:26 ` Jani Nikula
2025-12-08 18:26 ` [PATCH 03/19] drm/i915/power: Remove i915_power_well_desc::has_vga Ville Syrjala
2025-12-09 10:27 ` Jani Nikula
2025-12-08 18:26 ` [PATCH 04/19] drm/i915/vga: Extract intel_gmch_ctrl_reg() Ville Syrjala
2025-12-09 10:28 ` Jani Nikula
2025-12-08 18:26 ` [PATCH 05/19] drm/i915/vga: Don't touch VGA registers if VGA decode is fully disabled Ville Syrjala
2025-12-09 10:29 ` Jani Nikula
2025-12-08 18:26 ` [PATCH 06/19] drm/i915/vga: Clean up VGA registers even if VGA plane is disabled Ville Syrjala
2025-12-09 10:32 ` Jani Nikula
2025-12-08 18:26 ` [PATCH 07/19] drm/i915/vga: Avoid VGA arbiter during intel_vga_disable() for iGPUs Ville Syrjala
2025-12-09 10:35 ` Jani Nikula
2025-12-09 12:17 ` Ville Syrjälä
2025-12-08 18:26 ` [PATCH 08/19] drm/i915/vga: Stop trying to use GMCH_CTRL for VGA decode control Ville Syrjala
2025-12-09 10:39 ` Jani Nikula
2025-12-08 18:26 ` [PATCH 09/19] drm/i915/vga: Assert that VGA register accesses are going to the right GPU Ville Syrjala
2025-12-09 10:40 ` Jani Nikula
2025-12-08 18:26 ` [PATCH 10/19] drm/i915/de: Simplify intel_de_read8() Ville Syrjala
2025-12-09 10:47 ` Jani Nikula [this message]
2025-12-08 18:26 ` [PATCH 11/19] drm/i915/de: Add intel_de_write8() Ville Syrjala
2025-12-09 10:49 ` Jani Nikula
2025-12-08 18:26 ` [PATCH 12/19] drm/i915/vga: Introduce intel_vga_{read,write}() Ville Syrjala
2025-12-09 10:52 ` Jani Nikula
2025-12-08 18:26 ` [PATCH 13/19] drm/i915/vga: Use MMIO for VGA registers on pre-g4x Ville Syrjala
2025-12-09 10:53 ` Jani Nikula
2025-12-08 18:26 ` [PATCH 14/19] video/vga: Add VGA_IS0_R Ville Syrjala
2025-12-08 21:07 ` kernel test robot
2025-12-08 21:18 ` kernel test robot
2025-12-08 22:22 ` kernel test robot
2025-12-09 7:55 ` [PATCH v2 " Ville Syrjala
2025-12-09 10:55 ` Jani Nikula
2025-12-18 16:56 ` Ville Syrjälä
2025-12-10 14:13 ` [PATCH " kernel test robot
2025-12-10 14:24 ` kernel test robot
2025-12-08 18:26 ` [PATCH 15/19] drm/i915/crt: Use IS0_R instead of VGA_MIS_W Ville Syrjala
2025-12-09 10:56 ` Jani Nikula
2025-12-08 18:26 ` [PATCH 16/19] drm/i915/crt: Extract intel_crt_sense_above_threshold() Ville Syrjala
2025-12-09 10:57 ` Jani Nikula
2025-12-08 18:26 ` [PATCH 17/19] drm/i915: Get rid of the INTEL_GMCH_CTRL alias Ville Syrjala
2025-12-09 10:58 ` Jani Nikula
2025-12-08 18:26 ` [PATCH 18/19] drm/i915: Clean up PCI config space reg defines Ville Syrjala
2025-12-09 11:00 ` Jani Nikula
2025-12-09 11:01 ` Jani Nikula
2025-12-08 18:26 ` [PATCH 19/19] drm/i915: Document the GMCH_CTRL register a bit Ville Syrjala
2025-12-09 11:03 ` Jani Nikula
2025-12-08 20:19 ` ✗ CI.KUnit: failure for drm/i915/vga: Try to sort out the VGA decode mess Patchwork
2025-12-09 8:52 ` ✓ CI.KUnit: success for drm/i915/vga: Try to sort out the VGA decode mess (rev2) Patchwork
2025-12-09 9:07 ` ✗ CI.checksparse: warning " Patchwork
2025-12-09 9:35 ` ✓ Xe.CI.BAT: success " Patchwork
2025-12-09 15:57 ` ✗ Xe.CI.Full: failure " Patchwork
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