Re: [PATCH 11/19] drm/i915/de: Add intel_de_write8()

[Jani Nikula <jani.nikula@linux.intel.com>]

On Mon, 08 Dec 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add a write counterpart to intel_de_read8(). Will be used for
> MMIO access to VGA registers on pre-g4x.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_de.h               | 8 ++++++++
>  drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h | 8 ++++++++
>  drivers/gpu/drm/xe/xe_mmio.c                          | 9 +++++++++
>  drivers/gpu/drm/xe/xe_mmio.h                          | 1 +
>  4 files changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
> index 5c1b37d30045..f30f3f8ebee1 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -42,6 +42,14 @@ intel_de_read8(struct intel_display *display, i915_reg_t reg)
>  	return intel_uncore_read8(__to_uncore(display), reg);
>  }
>  
> +static inline void
> +intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val)
> +{
> +	drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x);
> +
> +	intel_uncore_write8(__to_uncore(display), reg, val);
> +}
> +
>  static inline u64
>  intel_de_read64_2x32(struct intel_display *display,
>  		     i915_reg_t lower_reg, i915_reg_t upper_reg)
> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> index d93ddacdf743..02b096bd7a4c 100644
> --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> +++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> @@ -40,6 +40,14 @@ static inline u8 intel_uncore_read8(struct intel_uncore *uncore,
>  	return xe_mmio_read8(__compat_uncore_to_mmio(uncore), reg);
>  }
>  
> +static inline void intel_uncore_write8(struct intel_uncore *uncore,
> +				       i915_reg_t i915_reg, u8 val)
> +{
> +	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> +	xe_mmio_write8(__compat_uncore_to_mmio(uncore), reg, val);
> +}
> +
>  static inline u16 intel_uncore_read16(struct intel_uncore *uncore,
>  				      i915_reg_t i915_reg)
>  {
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index 350dca1f0925..6bdaedc1da73 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -158,6 +158,15 @@ u8 xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg)
>  	return val;
>  }
>  
> +void xe_mmio_write8(struct xe_mmio *mmio, struct xe_reg reg, u8 val)
> +{
> +	u32 addr = xe_mmio_adjusted_addr(mmio, reg.addr);
> +
> +	trace_xe_reg_rw(mmio, true, addr, val, sizeof(val));
> +
> +	writeb(val, mmio->regs + addr);
> +}
> +
>  u16 xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg)
>  {
>  	u32 addr = xe_mmio_adjusted_addr(mmio, reg.addr);
> diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
> index 15362789ab99..cd355a43af3d 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.h
> +++ b/drivers/gpu/drm/xe/xe_mmio.h
> @@ -17,6 +17,7 @@ int xe_mmio_probe_tiles(struct xe_device *xe);
>  void xe_mmio_init(struct xe_mmio *mmio, struct xe_tile *tile, void __iomem *ptr, u32 size);
>  
>  u8 xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg);
> +void xe_mmio_write8(struct xe_mmio *mmio, struct xe_reg reg, u8 val);
>  u16 xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg);
>  void xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val);
>  u32 xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg);

-- 
Jani Nikula, Intel