* [PATCH 0/2] drm/i915/vrr: Hide even more ICL/TGL weirdness
@ 2025-09-18 23:22 Ville Syrjala
2025-09-18 23:22 ` [PATCH 1/2] drm/i915/vrr: Hide the ICL/TGL intel_vrr_flipline_offset() mangling better Ville Syrjala
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Ville Syrjala @ 2025-09-18 23:22 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Previosuly we took care to hide most of the ICL/TGL vs. ADL+
differences. But the flipline>=vmin+1 stuff still remains.
Try to hide that as well.
Ville Syrjälä (2):
drm/i915/vrr: Hide the ICL/TGL intel_vrr_flipline_offset() mangling
better
drm/i915/vrr:
s/intel_vrr_flipline_offset/intel_vrr_vmin_flipline_offset/
drivers/gpu/drm/i915/display/intel_vrr.c | 34 +++++++++++++-----------
1 file changed, 19 insertions(+), 15 deletions(-)
--
2.49.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] drm/i915/vrr: Hide the ICL/TGL intel_vrr_flipline_offset() mangling better
2025-09-18 23:22 [PATCH 0/2] drm/i915/vrr: Hide even more ICL/TGL weirdness Ville Syrjala
@ 2025-09-18 23:22 ` Ville Syrjala
2025-09-19 10:49 ` Nautiyal, Ankit K
2025-09-18 23:22 ` [PATCH 2/2] drm/i915/vrr: s/intel_vrr_flipline_offset/intel_vrr_vmin_flipline_offset/ Ville Syrjala
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Ville Syrjala @ 2025-09-18 23:22 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
ICL/TGL VRR hardware won't allow us to program flipline==vmin. If we do
that the actual effect will be the same as if we had programmed
flipline=vmin+1, which would make the minimum vtotal one scanline taller
than expected.
To compensate for this we reduce vmin by one, and then program
flipline=vmin+1. So we end up with a flipline value that matches
the expected minimum vtotal. Currently this adjustment happens
in intel_vrr_compute_config() which means that crtc_state->vrr.vmin
will no longer be directly usable for the remainder of the high
level VRR code. That is annoying at best, fragile at worst.
Hide the adjustment in low level code instead. This will allow most
of the higher level VRR code to remain blissfully ignorant about this
fact. Afterwards crtc_state->vrr.{vmin,flipline} will be equal
and match the minimum vtotal, exactly how things already work
on ADL+.
The only slight downside is that the actual register value will no
longer match crtc_state->vrr.vmin on ICL/TGL, but that may already
be the case on TGL because the register value will also have been
adjusted by the SCL.
Note that we must change the guardband calculation to account
for intel_vrr_extra_vblank_delay() explicitly. Previously that
was accidentally handled by the earlier vmin reduction by
intel_vrr_flipline_offset().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 30 ++++++++++++++----------
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 71a985d00604..e725b4581e81 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -108,15 +108,20 @@ int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state)
static int intel_vrr_flipline_offset(struct intel_display *display)
{
- /* ICL/TGL hardware imposes flipline>=vmin+1 */
+ /*
+ * ICL/TGL hardware imposes flipline>=vmin+1
+ *
+ * We reduce the vmin value to compensate when programming the
+ * hardware. This approach allows flipline to remain set at the
+ * original value, and thus the frame will have the desired
+ * minimum vtotal.
+ */
return DISPLAY_VER(display) < 13 ? 1 : 0;
}
static int intel_vrr_vmin_flipline(const struct intel_crtc_state *crtc_state)
{
- struct intel_display *display = to_intel_display(crtc_state);
-
- return crtc_state->vrr.vmin + intel_vrr_flipline_offset(display);
+ return crtc_state->vrr.vmin;
}
static int intel_vrr_guardband_to_pipeline_full(const struct intel_crtc_state *crtc_state,
@@ -400,13 +405,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
else
intel_vrr_compute_fixed_rr_timings(crtc_state);
- /*
- * flipline determines the min vblank length the hardware will
- * generate, and on ICL/TGL flipline>=vmin+1, hence we reduce
- * vmin by one to make sure we can get the actual min vblank length.
- */
- crtc_state->vrr.vmin -= intel_vrr_flipline_offset(display);
-
if (HAS_AS_SDP(display)) {
crtc_state->vrr.vsync_start =
(crtc_state->hw.adjusted_mode.crtc_vtotal -
@@ -426,7 +424,8 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
return;
crtc_state->vrr.guardband =
- crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
+ crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
+ intel_vrr_extra_vblank_delay(display);
if (DISPLAY_VER(display) < 13) {
/* FIXME handle the limit in a proper way */
@@ -597,7 +596,10 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
{
- return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmin);
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmin) -
+ intel_vrr_flipline_offset(display);
}
static int intel_vrr_hw_vmax(const struct intel_crtc_state *crtc_state)
@@ -762,6 +764,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
crtc_state->vrr.flipline += intel_vrr_real_vblank_delay(crtc_state);
crtc_state->vrr.vmax += intel_vrr_real_vblank_delay(crtc_state);
crtc_state->vrr.vmin += intel_vrr_real_vblank_delay(crtc_state);
+
+ crtc_state->vrr.vmin += intel_vrr_flipline_offset(display);
}
/*
--
2.49.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/i915/vrr: s/intel_vrr_flipline_offset/intel_vrr_vmin_flipline_offset/
2025-09-18 23:22 [PATCH 0/2] drm/i915/vrr: Hide even more ICL/TGL weirdness Ville Syrjala
2025-09-18 23:22 ` [PATCH 1/2] drm/i915/vrr: Hide the ICL/TGL intel_vrr_flipline_offset() mangling better Ville Syrjala
@ 2025-09-18 23:22 ` Ville Syrjala
2025-09-19 10:49 ` Nautiyal, Ankit K
2025-09-18 23:29 ` ✓ CI.KUnit: success for drm/i915/vrr: Hide even more ICL/TGL weirdness Patchwork
2025-09-19 0:03 ` ✓ Xe.CI.BAT: " Patchwork
3 siblings, 1 reply; 7+ messages in thread
From: Ville Syrjala @ 2025-09-18 23:22 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename intel_vrr_flipline_offset() to intel_vrr_vmin_flipline_offset()
to better reflect the fact that it gives us the minimum offset allowed
between vmin and flipline.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index e725b4581e81..9e007aab1452 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -106,7 +106,7 @@ int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state)
intel_vrr_extra_vblank_delay(display);
}
-static int intel_vrr_flipline_offset(struct intel_display *display)
+static int intel_vrr_vmin_flipline_offset(struct intel_display *display)
{
/*
* ICL/TGL hardware imposes flipline>=vmin+1
@@ -288,7 +288,7 @@ int intel_vrr_fixed_rr_hw_vmin(const struct intel_crtc_state *crtc_state)
struct intel_display *display = to_intel_display(crtc_state);
return intel_vrr_fixed_rr_hw_vtotal(crtc_state) -
- intel_vrr_flipline_offset(display);
+ intel_vrr_vmin_flipline_offset(display);
}
static
@@ -599,7 +599,7 @@ static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
struct intel_display *display = to_intel_display(crtc_state);
return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmin) -
- intel_vrr_flipline_offset(display);
+ intel_vrr_vmin_flipline_offset(display);
}
static int intel_vrr_hw_vmax(const struct intel_crtc_state *crtc_state)
@@ -765,7 +765,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
crtc_state->vrr.vmax += intel_vrr_real_vblank_delay(crtc_state);
crtc_state->vrr.vmin += intel_vrr_real_vblank_delay(crtc_state);
- crtc_state->vrr.vmin += intel_vrr_flipline_offset(display);
+ crtc_state->vrr.vmin += intel_vrr_vmin_flipline_offset(display);
}
/*
--
2.49.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✓ CI.KUnit: success for drm/i915/vrr: Hide even more ICL/TGL weirdness
2025-09-18 23:22 [PATCH 0/2] drm/i915/vrr: Hide even more ICL/TGL weirdness Ville Syrjala
2025-09-18 23:22 ` [PATCH 1/2] drm/i915/vrr: Hide the ICL/TGL intel_vrr_flipline_offset() mangling better Ville Syrjala
2025-09-18 23:22 ` [PATCH 2/2] drm/i915/vrr: s/intel_vrr_flipline_offset/intel_vrr_vmin_flipline_offset/ Ville Syrjala
@ 2025-09-18 23:29 ` Patchwork
2025-09-19 0:03 ` ✓ Xe.CI.BAT: " Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2025-09-18 23:29 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-xe
== Series Details ==
Series: drm/i915/vrr: Hide even more ICL/TGL weirdness
URL : https://patchwork.freedesktop.org/series/154745/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[23:27:51] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:27:55] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:28:24] Starting KUnit Kernel (1/1)...
[23:28:24] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:28:24] ================== guc_buf (11 subtests) ===================
[23:28:24] [PASSED] test_smallest
[23:28:24] [PASSED] test_largest
[23:28:24] [PASSED] test_granular
[23:28:24] [PASSED] test_unique
[23:28:24] [PASSED] test_overlap
[23:28:24] [PASSED] test_reusable
[23:28:24] [PASSED] test_too_big
[23:28:24] [PASSED] test_flush
[23:28:24] [PASSED] test_lookup
[23:28:24] [PASSED] test_data
[23:28:24] [PASSED] test_class
[23:28:24] ===================== [PASSED] guc_buf =====================
[23:28:24] =================== guc_dbm (7 subtests) ===================
[23:28:24] [PASSED] test_empty
[23:28:24] [PASSED] test_default
[23:28:24] ======================== test_size ========================
[23:28:24] [PASSED] 4
[23:28:24] [PASSED] 8
[23:28:24] [PASSED] 32
[23:28:24] [PASSED] 256
[23:28:24] ==================== [PASSED] test_size ====================
[23:28:24] ======================= test_reuse ========================
[23:28:24] [PASSED] 4
[23:28:24] [PASSED] 8
[23:28:24] [PASSED] 32
[23:28:24] [PASSED] 256
[23:28:24] =================== [PASSED] test_reuse ====================
[23:28:24] =================== test_range_overlap ====================
[23:28:24] [PASSED] 4
[23:28:24] [PASSED] 8
[23:28:24] [PASSED] 32
[23:28:24] [PASSED] 256
[23:28:24] =============== [PASSED] test_range_overlap ================
[23:28:24] =================== test_range_compact ====================
[23:28:24] [PASSED] 4
[23:28:24] [PASSED] 8
[23:28:24] [PASSED] 32
[23:28:24] [PASSED] 256
[23:28:24] =============== [PASSED] test_range_compact ================
[23:28:24] ==================== test_range_spare =====================
[23:28:24] [PASSED] 4
[23:28:24] [PASSED] 8
[23:28:24] [PASSED] 32
[23:28:24] [PASSED] 256
[23:28:24] ================ [PASSED] test_range_spare =================
[23:28:24] ===================== [PASSED] guc_dbm =====================
[23:28:24] =================== guc_idm (6 subtests) ===================
[23:28:24] [PASSED] bad_init
[23:28:24] [PASSED] no_init
[23:28:24] [PASSED] init_fini
[23:28:24] [PASSED] check_used
[23:28:24] [PASSED] check_quota
[23:28:24] [PASSED] check_all
[23:28:24] ===================== [PASSED] guc_idm =====================
[23:28:24] ================== no_relay (3 subtests) ===================
[23:28:24] [PASSED] xe_drops_guc2pf_if_not_ready
[23:28:24] [PASSED] xe_drops_guc2vf_if_not_ready
[23:28:24] [PASSED] xe_rejects_send_if_not_ready
[23:28:24] ==================== [PASSED] no_relay =====================
[23:28:24] ================== pf_relay (14 subtests) ==================
[23:28:24] [PASSED] pf_rejects_guc2pf_too_short
[23:28:24] [PASSED] pf_rejects_guc2pf_too_long
[23:28:24] [PASSED] pf_rejects_guc2pf_no_payload
[23:28:24] [PASSED] pf_fails_no_payload
[23:28:24] [PASSED] pf_fails_bad_origin
[23:28:24] [PASSED] pf_fails_bad_type
[23:28:24] [PASSED] pf_txn_reports_error
[23:28:24] [PASSED] pf_txn_sends_pf2guc
[23:28:24] [PASSED] pf_sends_pf2guc
[23:28:24] [SKIPPED] pf_loopback_nop
[23:28:24] [SKIPPED] pf_loopback_echo
[23:28:24] [SKIPPED] pf_loopback_fail
[23:28:24] [SKIPPED] pf_loopback_busy
[23:28:24] [SKIPPED] pf_loopback_retry
[23:28:24] ==================== [PASSED] pf_relay =====================
[23:28:24] ================== vf_relay (3 subtests) ===================
[23:28:24] [PASSED] vf_rejects_guc2vf_too_short
[23:28:24] [PASSED] vf_rejects_guc2vf_too_long
[23:28:24] [PASSED] vf_rejects_guc2vf_no_payload
[23:28:24] ==================== [PASSED] vf_relay =====================
[23:28:24] ===================== lmtt (1 subtest) =====================
[23:28:24] ======================== test_ops =========================
[23:28:24] [PASSED] 2-level
[23:28:24] [PASSED] multi-level
[23:28:24] ==================== [PASSED] test_ops =====================
[23:28:24] ====================== [PASSED] lmtt =======================
[23:28:24] ================= pf_service (11 subtests) =================
[23:28:24] [PASSED] pf_negotiate_any
[23:28:24] [PASSED] pf_negotiate_base_match
[23:28:24] [PASSED] pf_negotiate_base_newer
[23:28:24] [PASSED] pf_negotiate_base_next
[23:28:24] [SKIPPED] pf_negotiate_base_older
[23:28:24] [PASSED] pf_negotiate_base_prev
[23:28:24] [PASSED] pf_negotiate_latest_match
[23:28:24] [PASSED] pf_negotiate_latest_newer
[23:28:24] [PASSED] pf_negotiate_latest_next
[23:28:24] [SKIPPED] pf_negotiate_latest_older
[23:28:24] [SKIPPED] pf_negotiate_latest_prev
[23:28:24] =================== [PASSED] pf_service ====================
[23:28:24] ================= xe_guc_g2g (2 subtests) ==================
[23:28:24] ============== xe_live_guc_g2g_kunit_default ==============
[23:28:24] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[23:28:24] ============== xe_live_guc_g2g_kunit_allmem ===============
[23:28:24] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[23:28:24] =================== [SKIPPED] xe_guc_g2g ===================
[23:28:24] =================== xe_mocs (2 subtests) ===================
[23:28:24] ================ xe_live_mocs_kernel_kunit ================
[23:28:24] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[23:28:24] ================ xe_live_mocs_reset_kunit =================
[23:28:24] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[23:28:24] ==================== [SKIPPED] xe_mocs =====================
[23:28:24] ================= xe_migrate (2 subtests) ==================
[23:28:24] ================= xe_migrate_sanity_kunit =================
[23:28:24] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[23:28:24] ================== xe_validate_ccs_kunit ==================
[23:28:24] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[23:28:24] =================== [SKIPPED] xe_migrate ===================
[23:28:24] ================== xe_dma_buf (1 subtest) ==================
[23:28:24] ==================== xe_dma_buf_kunit =====================
[23:28:24] ================ [SKIPPED] xe_dma_buf_kunit ================
[23:28:24] =================== [SKIPPED] xe_dma_buf ===================
[23:28:24] ================= xe_bo_shrink (1 subtest) =================
[23:28:24] =================== xe_bo_shrink_kunit ====================
[23:28:24] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[23:28:24] ================== [SKIPPED] xe_bo_shrink ==================
[23:28:24] ==================== xe_bo (2 subtests) ====================
[23:28:24] ================== xe_ccs_migrate_kunit ===================
[23:28:24] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[23:28:24] ==================== xe_bo_evict_kunit ====================
[23:28:24] =============== [SKIPPED] xe_bo_evict_kunit ================
[23:28:24] ===================== [SKIPPED] xe_bo ======================
[23:28:24] ==================== args (11 subtests) ====================
[23:28:24] [PASSED] count_args_test
[23:28:24] [PASSED] call_args_example
[23:28:24] [PASSED] call_args_test
[23:28:24] [PASSED] drop_first_arg_example
[23:28:24] [PASSED] drop_first_arg_test
[23:28:24] [PASSED] first_arg_example
[23:28:24] [PASSED] first_arg_test
[23:28:24] [PASSED] last_arg_example
[23:28:24] [PASSED] last_arg_test
[23:28:24] [PASSED] pick_arg_example
[23:28:24] [PASSED] sep_comma_example
[23:28:24] ====================== [PASSED] args =======================
[23:28:24] =================== xe_pci (3 subtests) ====================
[23:28:24] ==================== check_graphics_ip ====================
[23:28:24] [PASSED] 12.00 Xe_LP
[23:28:24] [PASSED] 12.10 Xe_LP+
[23:28:24] [PASSED] 12.55 Xe_HPG
[23:28:24] [PASSED] 12.60 Xe_HPC
[23:28:24] [PASSED] 12.70 Xe_LPG
[23:28:24] [PASSED] 12.71 Xe_LPG
[23:28:24] [PASSED] 12.74 Xe_LPG+
[23:28:24] [PASSED] 20.01 Xe2_HPG
[23:28:24] [PASSED] 20.02 Xe2_HPG
[23:28:24] [PASSED] 20.04 Xe2_LPG
[23:28:24] [PASSED] 30.00 Xe3_LPG
[23:28:24] [PASSED] 30.01 Xe3_LPG
[23:28:24] [PASSED] 30.03 Xe3_LPG
[23:28:24] ================ [PASSED] check_graphics_ip ================
[23:28:24] ===================== check_media_ip ======================
[23:28:24] [PASSED] 12.00 Xe_M
[23:28:24] [PASSED] 12.55 Xe_HPM
[23:28:24] [PASSED] 13.00 Xe_LPM+
[23:28:24] [PASSED] 13.01 Xe2_HPM
[23:28:24] [PASSED] 20.00 Xe2_LPM
[23:28:24] [PASSED] 30.00 Xe3_LPM
[23:28:24] [PASSED] 30.02 Xe3_LPM
[23:28:24] ================= [PASSED] check_media_ip ==================
[23:28:24] ================= check_platform_gt_count =================
[23:28:24] [PASSED] 0x9A60 (TIGERLAKE)
[23:28:24] [PASSED] 0x9A68 (TIGERLAKE)
[23:28:24] [PASSED] 0x9A70 (TIGERLAKE)
[23:28:24] [PASSED] 0x9A40 (TIGERLAKE)
[23:28:24] [PASSED] 0x9A49 (TIGERLAKE)
[23:28:24] [PASSED] 0x9A59 (TIGERLAKE)
[23:28:24] [PASSED] 0x9A78 (TIGERLAKE)
[23:28:24] [PASSED] 0x9AC0 (TIGERLAKE)
[23:28:24] [PASSED] 0x9AC9 (TIGERLAKE)
[23:28:24] [PASSED] 0x9AD9 (TIGERLAKE)
[23:28:24] [PASSED] 0x9AF8 (TIGERLAKE)
[23:28:24] [PASSED] 0x4C80 (ROCKETLAKE)
[23:28:24] [PASSED] 0x4C8A (ROCKETLAKE)
[23:28:24] [PASSED] 0x4C8B (ROCKETLAKE)
[23:28:24] [PASSED] 0x4C8C (ROCKETLAKE)
[23:28:24] [PASSED] 0x4C90 (ROCKETLAKE)
[23:28:24] [PASSED] 0x4C9A (ROCKETLAKE)
[23:28:24] [PASSED] 0x4680 (ALDERLAKE_S)
[23:28:24] [PASSED] 0x4682 (ALDERLAKE_S)
[23:28:24] [PASSED] 0x4688 (ALDERLAKE_S)
[23:28:24] [PASSED] 0x468A (ALDERLAKE_S)
[23:28:24] [PASSED] 0x468B (ALDERLAKE_S)
[23:28:24] [PASSED] 0x4690 (ALDERLAKE_S)
[23:28:24] [PASSED] 0x4692 (ALDERLAKE_S)
[23:28:24] [PASSED] 0x4693 (ALDERLAKE_S)
[23:28:24] [PASSED] 0x46A0 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x46A1 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x46A2 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x46A3 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x46A6 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x46A8 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x46AA (ALDERLAKE_P)
[23:28:24] [PASSED] 0x462A (ALDERLAKE_P)
[23:28:24] [PASSED] 0x4626 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x4628 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x46B0 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x46B1 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x46B2 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x46B3 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x46C0 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x46C1 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x46C2 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x46C3 (ALDERLAKE_P)
[23:28:24] [PASSED] 0x46D0 (ALDERLAKE_N)
[23:28:24] [PASSED] 0x46D1 (ALDERLAKE_N)
[23:28:24] [PASSED] 0x46D2 (ALDERLAKE_N)
[23:28:24] [PASSED] 0x46D3 (ALDERLAKE_N)
[23:28:24] [PASSED] 0x46D4 (ALDERLAKE_N)
[23:28:24] [PASSED] 0xA721 (ALDERLAKE_P)
[23:28:24] [PASSED] 0xA7A1 (ALDERLAKE_P)
[23:28:24] [PASSED] 0xA7A9 (ALDERLAKE_P)
[23:28:24] [PASSED] 0xA7AC (ALDERLAKE_P)
[23:28:24] [PASSED] 0xA7AD (ALDERLAKE_P)
[23:28:24] [PASSED] 0xA720 (ALDERLAKE_P)
[23:28:24] [PASSED] 0xA7A0 (ALDERLAKE_P)
[23:28:24] [PASSED] 0xA7A8 (ALDERLAKE_P)
[23:28:24] [PASSED] 0xA7AA (ALDERLAKE_P)
[23:28:24] [PASSED] 0xA7AB (ALDERLAKE_P)
[23:28:24] [PASSED] 0xA780 (ALDERLAKE_S)
[23:28:24] [PASSED] 0xA781 (ALDERLAKE_S)
[23:28:24] [PASSED] 0xA782 (ALDERLAKE_S)
[23:28:24] [PASSED] 0xA783 (ALDERLAKE_S)
[23:28:24] [PASSED] 0xA788 (ALDERLAKE_S)
[23:28:24] [PASSED] 0xA789 (ALDERLAKE_S)
[23:28:24] [PASSED] 0xA78A (ALDERLAKE_S)
[23:28:24] [PASSED] 0xA78B (ALDERLAKE_S)
[23:28:24] [PASSED] 0x4905 (DG1)
[23:28:24] [PASSED] 0x4906 (DG1)
[23:28:24] [PASSED] 0x4907 (DG1)
[23:28:24] [PASSED] 0x4908 (DG1)
[23:28:24] [PASSED] 0x4909 (DG1)
[23:28:24] [PASSED] 0x56C0 (DG2)
[23:28:24] [PASSED] 0x56C2 (DG2)
[23:28:24] [PASSED] 0x56C1 (DG2)
[23:28:24] [PASSED] 0x7D51 (METEORLAKE)
[23:28:24] [PASSED] 0x7DD1 (METEORLAKE)
[23:28:24] [PASSED] 0x7D41 (METEORLAKE)
[23:28:24] [PASSED] 0x7D67 (METEORLAKE)
[23:28:24] [PASSED] 0xB640 (METEORLAKE)
[23:28:24] [PASSED] 0x56A0 (DG2)
[23:28:24] [PASSED] 0x56A1 (DG2)
[23:28:24] [PASSED] 0x56A2 (DG2)
[23:28:24] [PASSED] 0x56BE (DG2)
[23:28:24] [PASSED] 0x56BF (DG2)
[23:28:24] [PASSED] 0x5690 (DG2)
[23:28:24] [PASSED] 0x5691 (DG2)
[23:28:24] [PASSED] 0x5692 (DG2)
[23:28:24] [PASSED] 0x56A5 (DG2)
[23:28:24] [PASSED] 0x56A6 (DG2)
[23:28:24] [PASSED] 0x56B0 (DG2)
[23:28:24] [PASSED] 0x56B1 (DG2)
[23:28:24] [PASSED] 0x56BA (DG2)
[23:28:24] [PASSED] 0x56BB (DG2)
[23:28:24] [PASSED] 0x56BC (DG2)
[23:28:24] [PASSED] 0x56BD (DG2)
[23:28:24] [PASSED] 0x5693 (DG2)
[23:28:24] [PASSED] 0x5694 (DG2)
[23:28:24] [PASSED] 0x5695 (DG2)
[23:28:24] [PASSED] 0x56A3 (DG2)
[23:28:24] [PASSED] 0x56A4 (DG2)
[23:28:24] [PASSED] 0x56B2 (DG2)
[23:28:24] [PASSED] 0x56B3 (DG2)
[23:28:24] [PASSED] 0x5696 (DG2)
[23:28:24] [PASSED] 0x5697 (DG2)
[23:28:24] [PASSED] 0xB69 (PVC)
[23:28:24] [PASSED] 0xB6E (PVC)
[23:28:24] [PASSED] 0xBD4 (PVC)
[23:28:24] [PASSED] 0xBD5 (PVC)
[23:28:24] [PASSED] 0xBD6 (PVC)
[23:28:24] [PASSED] 0xBD7 (PVC)
[23:28:24] [PASSED] 0xBD8 (PVC)
[23:28:24] [PASSED] 0xBD9 (PVC)
[23:28:24] [PASSED] 0xBDA (PVC)
[23:28:24] [PASSED] 0xBDB (PVC)
[23:28:24] [PASSED] 0xBE0 (PVC)
[23:28:24] [PASSED] 0xBE1 (PVC)
[23:28:24] [PASSED] 0xBE5 (PVC)
[23:28:24] [PASSED] 0x7D40 (METEORLAKE)
[23:28:24] [PASSED] 0x7D45 (METEORLAKE)
[23:28:24] [PASSED] 0x7D55 (METEORLAKE)
[23:28:24] [PASSED] 0x7D60 (METEORLAKE)
[23:28:24] [PASSED] 0x7DD5 (METEORLAKE)
[23:28:24] [PASSED] 0x6420 (LUNARLAKE)
[23:28:24] [PASSED] 0x64A0 (LUNARLAKE)
[23:28:24] [PASSED] 0x64B0 (LUNARLAKE)
[23:28:24] [PASSED] 0xE202 (BATTLEMAGE)
[23:28:24] [PASSED] 0xE209 (BATTLEMAGE)
[23:28:24] [PASSED] 0xE20B (BATTLEMAGE)
[23:28:24] [PASSED] 0xE20C (BATTLEMAGE)
[23:28:24] [PASSED] 0xE20D (BATTLEMAGE)
[23:28:24] [PASSED] 0xE210 (BATTLEMAGE)
[23:28:24] [PASSED] 0xE211 (BATTLEMAGE)
[23:28:24] [PASSED] 0xE212 (BATTLEMAGE)
[23:28:24] [PASSED] 0xE216 (BATTLEMAGE)
[23:28:24] [PASSED] 0xE220 (BATTLEMAGE)
[23:28:24] [PASSED] 0xE221 (BATTLEMAGE)
[23:28:24] [PASSED] 0xE222 (BATTLEMAGE)
[23:28:24] [PASSED] 0xE223 (BATTLEMAGE)
[23:28:24] [PASSED] 0xB080 (PANTHERLAKE)
[23:28:24] [PASSED] 0xB081 (PANTHERLAKE)
[23:28:24] [PASSED] 0xB082 (PANTHERLAKE)
[23:28:24] [PASSED] 0xB083 (PANTHERLAKE)
[23:28:24] [PASSED] 0xB084 (PANTHERLAKE)
[23:28:24] [PASSED] 0xB085 (PANTHERLAKE)
[23:28:24] [PASSED] 0xB086 (PANTHERLAKE)
[23:28:24] [PASSED] 0xB087 (PANTHERLAKE)
[23:28:24] [PASSED] 0xB08F (PANTHERLAKE)
[23:28:24] [PASSED] 0xB090 (PANTHERLAKE)
[23:28:24] [PASSED] 0xB0A0 (PANTHERLAKE)
[23:28:24] [PASSED] 0xB0B0 (PANTHERLAKE)
[23:28:24] [PASSED] 0xFD80 (PANTHERLAKE)
[23:28:24] [PASSED] 0xFD81 (PANTHERLAKE)
[23:28:24] ============= [PASSED] check_platform_gt_count =============
[23:28:24] ===================== [PASSED] xe_pci ======================
[23:28:24] =================== xe_rtp (2 subtests) ====================
[23:28:24] =============== xe_rtp_process_to_sr_tests ================
[23:28:24] [PASSED] coalesce-same-reg
[23:28:24] [PASSED] no-match-no-add
[23:28:24] [PASSED] match-or
[23:28:24] [PASSED] match-or-xfail
[23:28:24] [PASSED] no-match-no-add-multiple-rules
[23:28:24] [PASSED] two-regs-two-entries
[23:28:24] [PASSED] clr-one-set-other
[23:28:24] [PASSED] set-field
[23:28:24] [PASSED] conflict-duplicate
[23:28:24] [PASSED] conflict-not-disjoint
[23:28:24] [PASSED] conflict-reg-type
[23:28:24] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[23:28:24] ================== xe_rtp_process_tests ===================
[23:28:24] [PASSED] active1
[23:28:24] [PASSED] active2
[23:28:24] [PASSED] active-inactive
[23:28:24] [PASSED] inactive-active
[23:28:24] [PASSED] inactive-1st_or_active-inactive
[23:28:24] [PASSED] inactive-2nd_or_active-inactive
[23:28:24] [PASSED] inactive-last_or_active-inactive
[23:28:24] [PASSED] inactive-no_or_active-inactive
[23:28:24] ============== [PASSED] xe_rtp_process_tests ===============
[23:28:24] ===================== [PASSED] xe_rtp ======================
[23:28:24] ==================== xe_wa (1 subtest) =====================
[23:28:24] ======================== xe_wa_gt =========================
[23:28:24] [PASSED] TIGERLAKE B0
[23:28:24] [PASSED] DG1 A0
[23:28:24] [PASSED] DG1 B0
[23:28:24] [PASSED] ALDERLAKE_S A0
[23:28:24] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[23:28:24] [PASSED] ALDERLAKE_S C0
[23:28:24] [PASSED] ALDERLAKE_S D0
[23:28:24] [PASSED] ALDERLAKE_P A0
[23:28:24] [PASSED] ALDERLAKE_P B0
[23:28:24] [PASSED] ALDERLAKE_P C0
[23:28:24] [PASSED] ALDERLAKE_S RPLS D0
[23:28:24] [PASSED] ALDERLAKE_P RPLU E0
[23:28:24] [PASSED] DG2 G10 C0
[23:28:24] [PASSED] DG2 G11 B1
[23:28:24] [PASSED] DG2 G12 A1
[23:28:24] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:28:24] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:28:24] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[23:28:24] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[23:28:24] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[23:28:24] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[23:28:24] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[23:28:24] ==================== [PASSED] xe_wa_gt =====================
[23:28:24] ====================== [PASSED] xe_wa ======================
[23:28:24] ============================================================
[23:28:24] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[23:28:24] Elapsed time: 33.661s total, 4.275s configuring, 29.019s building, 0.326s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[23:28:24] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:28:26] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:28:50] Starting KUnit Kernel (1/1)...
[23:28:50] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:28:50] ============ drm_test_pick_cmdline (2 subtests) ============
[23:28:50] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[23:28:50] =============== drm_test_pick_cmdline_named ===============
[23:28:50] [PASSED] NTSC
[23:28:50] [PASSED] NTSC-J
[23:28:50] [PASSED] PAL
[23:28:50] [PASSED] PAL-M
[23:28:50] =========== [PASSED] drm_test_pick_cmdline_named ===========
[23:28:50] ============== [PASSED] drm_test_pick_cmdline ==============
[23:28:50] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[23:28:50] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[23:28:50] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[23:28:50] =========== drm_validate_clone_mode (2 subtests) ===========
[23:28:50] ============== drm_test_check_in_clone_mode ===============
[23:28:50] [PASSED] in_clone_mode
[23:28:50] [PASSED] not_in_clone_mode
[23:28:50] ========== [PASSED] drm_test_check_in_clone_mode ===========
[23:28:50] =============== drm_test_check_valid_clones ===============
[23:28:50] [PASSED] not_in_clone_mode
[23:28:50] [PASSED] valid_clone
[23:28:50] [PASSED] invalid_clone
[23:28:50] =========== [PASSED] drm_test_check_valid_clones ===========
[23:28:50] ============= [PASSED] drm_validate_clone_mode =============
[23:28:50] ============= drm_validate_modeset (1 subtest) =============
[23:28:50] [PASSED] drm_test_check_connector_changed_modeset
[23:28:50] ============== [PASSED] drm_validate_modeset ===============
[23:28:50] ====== drm_test_bridge_get_current_state (2 subtests) ======
[23:28:50] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[23:28:50] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[23:28:50] ======== [PASSED] drm_test_bridge_get_current_state ========
[23:28:50] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[23:28:50] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[23:28:50] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[23:28:50] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[23:28:50] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[23:28:50] ============== drm_bridge_alloc (2 subtests) ===============
[23:28:50] [PASSED] drm_test_drm_bridge_alloc_basic
[23:28:50] [PASSED] drm_test_drm_bridge_alloc_get_put
[23:28:50] ================ [PASSED] drm_bridge_alloc =================
[23:28:50] ================== drm_buddy (7 subtests) ==================
[23:28:50] [PASSED] drm_test_buddy_alloc_limit
[23:28:50] [PASSED] drm_test_buddy_alloc_optimistic
[23:28:50] [PASSED] drm_test_buddy_alloc_pessimistic
[23:28:50] [PASSED] drm_test_buddy_alloc_pathological
[23:28:50] [PASSED] drm_test_buddy_alloc_contiguous
[23:28:50] [PASSED] drm_test_buddy_alloc_clear
[23:28:50] [PASSED] drm_test_buddy_alloc_range_bias
[23:28:50] ==================== [PASSED] drm_buddy ====================
[23:28:50] ============= drm_cmdline_parser (40 subtests) =============
[23:28:50] [PASSED] drm_test_cmdline_force_d_only
[23:28:50] [PASSED] drm_test_cmdline_force_D_only_dvi
[23:28:50] [PASSED] drm_test_cmdline_force_D_only_hdmi
[23:28:50] [PASSED] drm_test_cmdline_force_D_only_not_digital
[23:28:50] [PASSED] drm_test_cmdline_force_e_only
[23:28:50] [PASSED] drm_test_cmdline_res
[23:28:50] [PASSED] drm_test_cmdline_res_vesa
[23:28:50] [PASSED] drm_test_cmdline_res_vesa_rblank
[23:28:50] [PASSED] drm_test_cmdline_res_rblank
[23:28:50] [PASSED] drm_test_cmdline_res_bpp
[23:28:50] [PASSED] drm_test_cmdline_res_refresh
[23:28:50] [PASSED] drm_test_cmdline_res_bpp_refresh
[23:28:50] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[23:28:50] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[23:28:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[23:28:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[23:28:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[23:28:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[23:28:50] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[23:28:50] [PASSED] drm_test_cmdline_res_margins_force_on
[23:28:50] [PASSED] drm_test_cmdline_res_vesa_margins
[23:28:50] [PASSED] drm_test_cmdline_name
[23:28:50] [PASSED] drm_test_cmdline_name_bpp
[23:28:50] [PASSED] drm_test_cmdline_name_option
[23:28:50] [PASSED] drm_test_cmdline_name_bpp_option
[23:28:50] [PASSED] drm_test_cmdline_rotate_0
[23:28:50] [PASSED] drm_test_cmdline_rotate_90
[23:28:50] [PASSED] drm_test_cmdline_rotate_180
[23:28:50] [PASSED] drm_test_cmdline_rotate_270
[23:28:50] [PASSED] drm_test_cmdline_hmirror
[23:28:50] [PASSED] drm_test_cmdline_vmirror
[23:28:50] [PASSED] drm_test_cmdline_margin_options
[23:28:50] [PASSED] drm_test_cmdline_multiple_options
[23:28:50] [PASSED] drm_test_cmdline_bpp_extra_and_option
[23:28:50] [PASSED] drm_test_cmdline_extra_and_option
[23:28:50] [PASSED] drm_test_cmdline_freestanding_options
[23:28:50] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[23:28:50] [PASSED] drm_test_cmdline_panel_orientation
[23:28:50] ================ drm_test_cmdline_invalid =================
[23:28:50] [PASSED] margin_only
[23:28:50] [PASSED] interlace_only
[23:28:50] [PASSED] res_missing_x
[23:28:50] [PASSED] res_missing_y
[23:28:50] [PASSED] res_bad_y
[23:28:50] [PASSED] res_missing_y_bpp
[23:28:50] [PASSED] res_bad_bpp
[23:28:50] [PASSED] res_bad_refresh
[23:28:50] [PASSED] res_bpp_refresh_force_on_off
[23:28:50] [PASSED] res_invalid_mode
[23:28:50] [PASSED] res_bpp_wrong_place_mode
[23:28:50] [PASSED] name_bpp_refresh
[23:28:50] [PASSED] name_refresh
[23:28:50] [PASSED] name_refresh_wrong_mode
[23:28:50] [PASSED] name_refresh_invalid_mode
[23:28:50] [PASSED] rotate_multiple
[23:28:50] [PASSED] rotate_invalid_val
[23:28:50] [PASSED] rotate_truncated
[23:28:50] [PASSED] invalid_option
[23:28:50] [PASSED] invalid_tv_option
[23:28:50] [PASSED] truncated_tv_option
[23:28:50] ============ [PASSED] drm_test_cmdline_invalid =============
[23:28:50] =============== drm_test_cmdline_tv_options ===============
[23:28:50] [PASSED] NTSC
[23:28:50] [PASSED] NTSC_443
[23:28:50] [PASSED] NTSC_J
[23:28:50] [PASSED] PAL
[23:28:50] [PASSED] PAL_M
[23:28:50] [PASSED] PAL_N
[23:28:50] [PASSED] SECAM
[23:28:50] [PASSED] MONO_525
[23:28:50] [PASSED] MONO_625
[23:28:50] =========== [PASSED] drm_test_cmdline_tv_options ===========
[23:28:50] =============== [PASSED] drm_cmdline_parser ================
[23:28:50] ========== drmm_connector_hdmi_init (20 subtests) ==========
[23:28:50] [PASSED] drm_test_connector_hdmi_init_valid
[23:28:50] [PASSED] drm_test_connector_hdmi_init_bpc_8
[23:28:50] [PASSED] drm_test_connector_hdmi_init_bpc_10
[23:28:50] [PASSED] drm_test_connector_hdmi_init_bpc_12
[23:28:50] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[23:28:50] [PASSED] drm_test_connector_hdmi_init_bpc_null
[23:28:50] [PASSED] drm_test_connector_hdmi_init_formats_empty
[23:28:50] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[23:28:50] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[23:28:50] [PASSED] supported_formats=0x9 yuv420_allowed=1
[23:28:50] [PASSED] supported_formats=0x9 yuv420_allowed=0
[23:28:50] [PASSED] supported_formats=0x3 yuv420_allowed=1
[23:28:50] [PASSED] supported_formats=0x3 yuv420_allowed=0
[23:28:50] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[23:28:50] [PASSED] drm_test_connector_hdmi_init_null_ddc
[23:28:50] [PASSED] drm_test_connector_hdmi_init_null_product
[23:28:50] [PASSED] drm_test_connector_hdmi_init_null_vendor
[23:28:50] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[23:28:50] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[23:28:50] [PASSED] drm_test_connector_hdmi_init_product_valid
[23:28:50] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[23:28:50] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[23:28:50] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[23:28:50] ========= drm_test_connector_hdmi_init_type_valid =========
[23:28:50] [PASSED] HDMI-A
[23:28:50] [PASSED] HDMI-B
[23:28:50] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[23:28:50] ======== drm_test_connector_hdmi_init_type_invalid ========
[23:28:50] [PASSED] Unknown
[23:28:50] [PASSED] VGA
[23:28:50] [PASSED] DVI-I
[23:28:50] [PASSED] DVI-D
[23:28:50] [PASSED] DVI-A
[23:28:50] [PASSED] Composite
[23:28:50] [PASSED] SVIDEO
[23:28:50] [PASSED] LVDS
[23:28:50] [PASSED] Component
[23:28:50] [PASSED] DIN
[23:28:50] [PASSED] DP
[23:28:50] [PASSED] TV
[23:28:50] [PASSED] eDP
[23:28:50] [PASSED] Virtual
[23:28:50] [PASSED] DSI
[23:28:50] [PASSED] DPI
[23:28:50] [PASSED] Writeback
[23:28:50] [PASSED] SPI
[23:28:50] [PASSED] USB
[23:28:50] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[23:28:50] ============ [PASSED] drmm_connector_hdmi_init =============
[23:28:50] ============= drmm_connector_init (3 subtests) =============
[23:28:50] [PASSED] drm_test_drmm_connector_init
[23:28:50] [PASSED] drm_test_drmm_connector_init_null_ddc
[23:28:50] ========= drm_test_drmm_connector_init_type_valid =========
[23:28:50] [PASSED] Unknown
[23:28:50] [PASSED] VGA
[23:28:50] [PASSED] DVI-I
[23:28:50] [PASSED] DVI-D
[23:28:50] [PASSED] DVI-A
[23:28:50] [PASSED] Composite
[23:28:50] [PASSED] SVIDEO
[23:28:50] [PASSED] LVDS
[23:28:50] [PASSED] Component
[23:28:50] [PASSED] DIN
[23:28:50] [PASSED] DP
[23:28:50] [PASSED] HDMI-A
[23:28:50] [PASSED] HDMI-B
[23:28:50] [PASSED] TV
[23:28:50] [PASSED] eDP
[23:28:50] [PASSED] Virtual
[23:28:50] [PASSED] DSI
[23:28:50] [PASSED] DPI
[23:28:50] [PASSED] Writeback
[23:28:50] [PASSED] SPI
[23:28:50] [PASSED] USB
[23:28:50] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[23:28:50] =============== [PASSED] drmm_connector_init ===============
[23:28:50] ========= drm_connector_dynamic_init (6 subtests) ==========
[23:28:50] [PASSED] drm_test_drm_connector_dynamic_init
[23:28:50] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[23:28:50] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[23:28:50] [PASSED] drm_test_drm_connector_dynamic_init_properties
[23:28:50] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[23:28:50] [PASSED] Unknown
[23:28:50] [PASSED] VGA
[23:28:50] [PASSED] DVI-I
[23:28:50] [PASSED] DVI-D
[23:28:50] [PASSED] DVI-A
[23:28:50] [PASSED] Composite
[23:28:50] [PASSED] SVIDEO
[23:28:50] [PASSED] LVDS
[23:28:50] [PASSED] Component
[23:28:50] [PASSED] DIN
[23:28:50] [PASSED] DP
[23:28:50] [PASSED] HDMI-A
[23:28:50] [PASSED] HDMI-B
[23:28:50] [PASSED] TV
[23:28:50] [PASSED] eDP
[23:28:50] [PASSED] Virtual
[23:28:50] [PASSED] DSI
[23:28:50] [PASSED] DPI
[23:28:50] [PASSED] Writeback
[23:28:50] [PASSED] SPI
[23:28:50] [PASSED] USB
[23:28:50] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[23:28:50] ======== drm_test_drm_connector_dynamic_init_name =========
[23:28:50] [PASSED] Unknown
[23:28:50] [PASSED] VGA
[23:28:50] [PASSED] DVI-I
[23:28:50] [PASSED] DVI-D
[23:28:50] [PASSED] DVI-A
[23:28:50] [PASSED] Composite
[23:28:50] [PASSED] SVIDEO
[23:28:50] [PASSED] LVDS
[23:28:50] [PASSED] Component
[23:28:50] [PASSED] DIN
[23:28:50] [PASSED] DP
[23:28:50] [PASSED] HDMI-A
[23:28:50] [PASSED] HDMI-B
[23:28:50] [PASSED] TV
[23:28:50] [PASSED] eDP
[23:28:50] [PASSED] Virtual
[23:28:50] [PASSED] DSI
[23:28:50] [PASSED] DPI
[23:28:50] [PASSED] Writeback
[23:28:50] [PASSED] SPI
[23:28:50] [PASSED] USB
[23:28:50] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[23:28:50] =========== [PASSED] drm_connector_dynamic_init ============
[23:28:50] ==== drm_connector_dynamic_register_early (4 subtests) =====
[23:28:50] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[23:28:50] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[23:28:50] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[23:28:50] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[23:28:50] ====== [PASSED] drm_connector_dynamic_register_early =======
[23:28:50] ======= drm_connector_dynamic_register (7 subtests) ========
[23:28:50] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[23:28:50] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[23:28:50] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[23:28:50] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[23:28:50] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[23:28:50] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[23:28:50] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[23:28:50] ========= [PASSED] drm_connector_dynamic_register ==========
[23:28:50] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[23:28:50] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[23:28:50] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[23:28:50] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[23:28:50] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[23:28:50] ========== drm_test_get_tv_mode_from_name_valid ===========
[23:28:50] [PASSED] NTSC
[23:28:50] [PASSED] NTSC-443
[23:28:50] [PASSED] NTSC-J
[23:28:50] [PASSED] PAL
[23:28:50] [PASSED] PAL-M
[23:28:50] [PASSED] PAL-N
[23:28:50] [PASSED] SECAM
[23:28:50] [PASSED] Mono
[23:28:50] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[23:28:50] [PASSED] drm_test_get_tv_mode_from_name_truncated
[23:28:50] ============ [PASSED] drm_get_tv_mode_from_name ============
[23:28:50] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[23:28:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[23:28:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[23:28:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[23:28:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[23:28:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[23:28:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[23:28:50] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[23:28:50] [PASSED] VIC 96
[23:28:50] [PASSED] VIC 97
[23:28:50] [PASSED] VIC 101
[23:28:50] [PASSED] VIC 102
[23:28:50] [PASSED] VIC 106
[23:28:50] [PASSED] VIC 107
[23:28:50] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[23:28:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[23:28:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[23:28:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[23:28:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[23:28:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[23:28:50] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[23:28:50] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[23:28:50] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[23:28:50] [PASSED] Automatic
[23:28:50] [PASSED] Full
[23:28:50] [PASSED] Limited 16:235
[23:28:50] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[23:28:50] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[23:28:50] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[23:28:50] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[23:28:50] === drm_test_drm_hdmi_connector_get_output_format_name ====
[23:28:50] [PASSED] RGB
[23:28:50] [PASSED] YUV 4:2:0
[23:28:50] [PASSED] YUV 4:2:2
[23:28:50] [PASSED] YUV 4:4:4
[23:28:50] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[23:28:50] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[23:28:50] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[23:28:50] ============= drm_damage_helper (21 subtests) ==============
[23:28:50] [PASSED] drm_test_damage_iter_no_damage
[23:28:50] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[23:28:50] [PASSED] drm_test_damage_iter_no_damage_src_moved
[23:28:50] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[23:28:50] [PASSED] drm_test_damage_iter_no_damage_not_visible
[23:28:50] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[23:28:50] [PASSED] drm_test_damage_iter_no_damage_no_fb
[23:28:50] [PASSED] drm_test_damage_iter_simple_damage
[23:28:50] [PASSED] drm_test_damage_iter_single_damage
[23:28:50] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[23:28:50] [PASSED] drm_test_damage_iter_single_damage_outside_src
[23:28:50] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[23:28:50] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[23:28:50] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[23:28:50] [PASSED] drm_test_damage_iter_single_damage_src_moved
[23:28:50] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[23:28:50] [PASSED] drm_test_damage_iter_damage
[23:28:50] [PASSED] drm_test_damage_iter_damage_one_intersect
[23:28:50] [PASSED] drm_test_damage_iter_damage_one_outside
[23:28:50] [PASSED] drm_test_damage_iter_damage_src_moved
[23:28:50] [PASSED] drm_test_damage_iter_damage_not_visible
[23:28:50] ================ [PASSED] drm_damage_helper ================
[23:28:50] ============== drm_dp_mst_helper (3 subtests) ==============
[23:28:50] ============== drm_test_dp_mst_calc_pbn_mode ==============
[23:28:50] [PASSED] Clock 154000 BPP 30 DSC disabled
[23:28:50] [PASSED] Clock 234000 BPP 30 DSC disabled
[23:28:50] [PASSED] Clock 297000 BPP 24 DSC disabled
[23:28:50] [PASSED] Clock 332880 BPP 24 DSC enabled
[23:28:50] [PASSED] Clock 324540 BPP 24 DSC enabled
[23:28:50] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[23:28:50] ============== drm_test_dp_mst_calc_pbn_div ===============
[23:28:50] [PASSED] Link rate 2000000 lane count 4
[23:28:50] [PASSED] Link rate 2000000 lane count 2
[23:28:50] [PASSED] Link rate 2000000 lane count 1
[23:28:50] [PASSED] Link rate 1350000 lane count 4
[23:28:50] [PASSED] Link rate 1350000 lane count 2
[23:28:50] [PASSED] Link rate 1350000 lane count 1
[23:28:50] [PASSED] Link rate 1000000 lane count 4
[23:28:50] [PASSED] Link rate 1000000 lane count 2
[23:28:50] [PASSED] Link rate 1000000 lane count 1
[23:28:50] [PASSED] Link rate 810000 lane count 4
[23:28:50] [PASSED] Link rate 810000 lane count 2
[23:28:50] [PASSED] Link rate 810000 lane count 1
[23:28:50] [PASSED] Link rate 540000 lane count 4
[23:28:50] [PASSED] Link rate 540000 lane count 2
[23:28:50] [PASSED] Link rate 540000 lane count 1
[23:28:50] [PASSED] Link rate 270000 lane count 4
[23:28:50] [PASSED] Link rate 270000 lane count 2
[23:28:50] [PASSED] Link rate 270000 lane count 1
[23:28:50] [PASSED] Link rate 162000 lane count 4
[23:28:50] [PASSED] Link rate 162000 lane count 2
[23:28:50] [PASSED] Link rate 162000 lane count 1
[23:28:50] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[23:28:50] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[23:28:50] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[23:28:50] [PASSED] DP_POWER_UP_PHY with port number
[23:28:50] [PASSED] DP_POWER_DOWN_PHY with port number
[23:28:50] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[23:28:50] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[23:28:50] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[23:28:50] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[23:28:50] [PASSED] DP_QUERY_PAYLOAD with port number
[23:28:50] [PASSED] DP_QUERY_PAYLOAD with VCPI
[23:28:50] [PASSED] DP_REMOTE_DPCD_READ with port number
[23:28:50] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[23:28:50] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[23:28:50] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[23:28:50] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[23:28:50] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[23:28:50] [PASSED] DP_REMOTE_I2C_READ with port number
[23:28:50] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[23:28:50] [PASSED] DP_REMOTE_I2C_READ with transactions array
[23:28:50] [PASSED] DP_REMOTE_I2C_WRITE with port number
[23:28:50] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[23:28:50] [PASSED] DP_REMOTE_I2C_WRITE with data array
[23:28:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[23:28:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[23:28:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[23:28:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[23:28:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[23:28:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[23:28:50] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[23:28:50] ================ [PASSED] drm_dp_mst_helper ================
[23:28:50] ================== drm_exec (7 subtests) ===================
[23:28:50] [PASSED] sanitycheck
[23:28:50] [PASSED] test_lock
[23:28:50] [PASSED] test_lock_unlock
[23:28:50] [PASSED] test_duplicates
[23:28:50] [PASSED] test_prepare
[23:28:50] [PASSED] test_prepare_array
[23:28:50] [PASSED] test_multiple_loops
[23:28:50] ==================== [PASSED] drm_exec =====================
[23:28:50] =========== drm_format_helper_test (17 subtests) ===========
[23:28:50] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[23:28:50] [PASSED] single_pixel_source_buffer
[23:28:50] [PASSED] single_pixel_clip_rectangle
[23:28:50] [PASSED] well_known_colors
[23:28:50] [PASSED] destination_pitch
[23:28:50] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[23:28:50] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[23:28:50] [PASSED] single_pixel_source_buffer
[23:28:50] [PASSED] single_pixel_clip_rectangle
[23:28:50] [PASSED] well_known_colors
[23:28:50] [PASSED] destination_pitch
[23:28:50] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[23:28:50] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[23:28:50] [PASSED] single_pixel_source_buffer
[23:28:50] [PASSED] single_pixel_clip_rectangle
[23:28:50] [PASSED] well_known_colors
[23:28:50] [PASSED] destination_pitch
[23:28:50] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[23:28:50] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[23:28:50] [PASSED] single_pixel_source_buffer
[23:28:50] [PASSED] single_pixel_clip_rectangle
[23:28:50] [PASSED] well_known_colors
[23:28:50] [PASSED] destination_pitch
[23:28:50] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[23:28:50] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[23:28:50] [PASSED] single_pixel_source_buffer
[23:28:50] [PASSED] single_pixel_clip_rectangle
[23:28:50] [PASSED] well_known_colors
[23:28:50] [PASSED] destination_pitch
[23:28:50] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[23:28:50] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[23:28:50] [PASSED] single_pixel_source_buffer
[23:28:50] [PASSED] single_pixel_clip_rectangle
[23:28:50] [PASSED] well_known_colors
[23:28:50] [PASSED] destination_pitch
[23:28:50] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[23:28:50] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[23:28:50] [PASSED] single_pixel_source_buffer
[23:28:50] [PASSED] single_pixel_clip_rectangle
[23:28:50] [PASSED] well_known_colors
[23:28:50] [PASSED] destination_pitch
[23:28:50] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[23:28:50] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[23:28:50] [PASSED] single_pixel_source_buffer
[23:28:50] [PASSED] single_pixel_clip_rectangle
[23:28:50] [PASSED] well_known_colors
[23:28:50] [PASSED] destination_pitch
[23:28:50] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[23:28:50] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[23:28:50] [PASSED] single_pixel_source_buffer
[23:28:50] [PASSED] single_pixel_clip_rectangle
[23:28:50] [PASSED] well_known_colors
[23:28:50] [PASSED] destination_pitch
[23:28:50] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[23:28:50] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[23:28:50] [PASSED] single_pixel_source_buffer
[23:28:50] [PASSED] single_pixel_clip_rectangle
[23:28:50] [PASSED] well_known_colors
[23:28:50] [PASSED] destination_pitch
[23:28:50] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[23:28:50] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[23:28:50] [PASSED] single_pixel_source_buffer
[23:28:50] [PASSED] single_pixel_clip_rectangle
[23:28:50] [PASSED] well_known_colors
[23:28:50] [PASSED] destination_pitch
[23:28:50] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[23:28:50] ============== drm_test_fb_xrgb8888_to_mono ===============
[23:28:50] [PASSED] single_pixel_source_buffer
[23:28:50] [PASSED] single_pixel_clip_rectangle
[23:28:50] [PASSED] well_known_colors
[23:28:50] [PASSED] destination_pitch
[23:28:50] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[23:28:50] ==================== drm_test_fb_swab =====================
[23:28:50] [PASSED] single_pixel_source_buffer
[23:28:50] [PASSED] single_pixel_clip_rectangle
[23:28:50] [PASSED] well_known_colors
[23:28:50] [PASSED] destination_pitch
[23:28:50] ================ [PASSED] drm_test_fb_swab =================
[23:28:50] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[23:28:50] [PASSED] single_pixel_source_buffer
[23:28:50] [PASSED] single_pixel_clip_rectangle
[23:28:50] [PASSED] well_known_colors
[23:28:50] [PASSED] destination_pitch
[23:28:50] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[23:28:50] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[23:28:50] [PASSED] single_pixel_source_buffer
[23:28:50] [PASSED] single_pixel_clip_rectangle
[23:28:50] [PASSED] well_known_colors
[23:28:50] [PASSED] destination_pitch
[23:28:50] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[23:28:50] ================= drm_test_fb_clip_offset =================
[23:28:50] [PASSED] pass through
[23:28:50] [PASSED] horizontal offset
[23:28:50] [PASSED] vertical offset
[23:28:50] [PASSED] horizontal and vertical offset
[23:28:50] [PASSED] horizontal offset (custom pitch)
[23:28:50] [PASSED] vertical offset (custom pitch)
[23:28:50] [PASSED] horizontal and vertical offset (custom pitch)
[23:28:50] ============= [PASSED] drm_test_fb_clip_offset =============
[23:28:50] =================== drm_test_fb_memcpy ====================
[23:28:50] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[23:28:50] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[23:28:50] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[23:28:50] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[23:28:50] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[23:28:50] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[23:28:50] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[23:28:50] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[23:28:50] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[23:28:50] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[23:28:50] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[23:28:50] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[23:28:50] =============== [PASSED] drm_test_fb_memcpy ================
[23:28:50] ============= [PASSED] drm_format_helper_test ==============
[23:28:50] ================= drm_format (18 subtests) =================
[23:28:50] [PASSED] drm_test_format_block_width_invalid
[23:28:50] [PASSED] drm_test_format_block_width_one_plane
[23:28:50] [PASSED] drm_test_format_block_width_two_plane
[23:28:50] [PASSED] drm_test_format_block_width_three_plane
[23:28:50] [PASSED] drm_test_format_block_width_tiled
[23:28:50] [PASSED] drm_test_format_block_height_invalid
[23:28:50] [PASSED] drm_test_format_block_height_one_plane
[23:28:50] [PASSED] drm_test_format_block_height_two_plane
[23:28:50] [PASSED] drm_test_format_block_height_three_plane
[23:28:50] [PASSED] drm_test_format_block_height_tiled
[23:28:50] [PASSED] drm_test_format_min_pitch_invalid
[23:28:50] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[23:28:50] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[23:28:50] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[23:28:50] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[23:28:50] [PASSED] drm_test_format_min_pitch_two_plane
[23:28:50] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[23:28:50] [PASSED] drm_test_format_min_pitch_tiled
[23:28:50] =================== [PASSED] drm_format ====================
[23:28:50] ============== drm_framebuffer (10 subtests) ===============
[23:28:50] ========== drm_test_framebuffer_check_src_coords ==========
[23:28:50] [PASSED] Success: source fits into fb
[23:28:50] [PASSED] Fail: overflowing fb with x-axis coordinate
[23:28:50] [PASSED] Fail: overflowing fb with y-axis coordinate
[23:28:50] [PASSED] Fail: overflowing fb with source width
[23:28:50] [PASSED] Fail: overflowing fb with source height
[23:28:50] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[23:28:50] [PASSED] drm_test_framebuffer_cleanup
[23:28:50] =============== drm_test_framebuffer_create ===============
[23:28:50] [PASSED] ABGR8888 normal sizes
[23:28:50] [PASSED] ABGR8888 max sizes
[23:28:50] [PASSED] ABGR8888 pitch greater than min required
[23:28:50] [PASSED] ABGR8888 pitch less than min required
[23:28:50] [PASSED] ABGR8888 Invalid width
[23:28:50] [PASSED] ABGR8888 Invalid buffer handle
[23:28:50] [PASSED] No pixel format
[23:28:50] [PASSED] ABGR8888 Width 0
[23:28:50] [PASSED] ABGR8888 Height 0
[23:28:50] [PASSED] ABGR8888 Out of bound height * pitch combination
[23:28:50] [PASSED] ABGR8888 Large buffer offset
[23:28:50] [PASSED] ABGR8888 Buffer offset for inexistent plane
[23:28:50] [PASSED] ABGR8888 Invalid flag
[23:28:50] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[23:28:50] [PASSED] ABGR8888 Valid buffer modifier
[23:28:50] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[23:28:50] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[23:28:50] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[23:28:50] [PASSED] NV12 Normal sizes
[23:28:50] [PASSED] NV12 Max sizes
[23:28:50] [PASSED] NV12 Invalid pitch
[23:28:50] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[23:28:50] [PASSED] NV12 different modifier per-plane
[23:28:50] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[23:28:50] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[23:28:50] [PASSED] NV12 Modifier for inexistent plane
[23:28:50] [PASSED] NV12 Handle for inexistent plane
[23:28:50] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[23:28:50] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[23:28:50] [PASSED] YVU420 Normal sizes
[23:28:50] [PASSED] YVU420 Max sizes
[23:28:50] [PASSED] YVU420 Invalid pitch
[23:28:50] [PASSED] YVU420 Different pitches
[23:28:50] [PASSED] YVU420 Different buffer offsets/pitches
[23:28:50] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[23:28:50] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[23:28:50] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[23:28:50] [PASSED] YVU420 Valid modifier
[23:28:50] [PASSED] YVU420 Different modifiers per plane
[23:28:50] [PASSED] YVU420 Modifier for inexistent plane
[23:28:50] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[23:28:50] [PASSED] X0L2 Normal sizes
[23:28:50] [PASSED] X0L2 Max sizes
[23:28:50] [PASSED] X0L2 Invalid pitch
[23:28:50] [PASSED] X0L2 Pitch greater than minimum required
[23:28:50] [PASSED] X0L2 Handle for inexistent plane
[23:28:50] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[23:28:50] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[23:28:50] [PASSED] X0L2 Valid modifier
[23:28:50] [PASSED] X0L2 Modifier for inexistent plane
[23:28:50] =========== [PASSED] drm_test_framebuffer_create ===========
[23:28:50] [PASSED] drm_test_framebuffer_free
[23:28:50] [PASSED] drm_test_framebuffer_init
[23:28:50] [PASSED] drm_test_framebuffer_init_bad_format
[23:28:50] [PASSED] drm_test_framebuffer_init_dev_mismatch
[23:28:50] [PASSED] drm_test_framebuffer_lookup
[23:28:50] [PASSED] drm_test_framebuffer_lookup_inexistent
[23:28:50] [PASSED] drm_test_framebuffer_modifiers_not_supported
[23:28:50] ================= [PASSED] drm_framebuffer =================
[23:28:50] ================ drm_gem_shmem (8 subtests) ================
[23:28:50] [PASSED] drm_gem_shmem_test_obj_create
[23:28:50] [PASSED] drm_gem_shmem_test_obj_create_private
[23:28:50] [PASSED] drm_gem_shmem_test_pin_pages
[23:28:50] [PASSED] drm_gem_shmem_test_vmap
[23:28:50] [PASSED] drm_gem_shmem_test_get_pages_sgt
[23:28:50] [PASSED] drm_gem_shmem_test_get_sg_table
[23:28:50] [PASSED] drm_gem_shmem_test_madvise
[23:28:50] [PASSED] drm_gem_shmem_test_purge
[23:28:50] ================== [PASSED] drm_gem_shmem ==================
[23:28:50] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[23:28:50] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[23:28:50] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[23:28:50] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[23:28:50] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[23:28:50] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[23:28:50] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[23:28:50] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[23:28:50] [PASSED] Automatic
[23:28:50] [PASSED] Full
[23:28:50] [PASSED] Limited 16:235
[23:28:50] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[23:28:50] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[23:28:50] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[23:28:50] [PASSED] drm_test_check_disable_connector
[23:28:50] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[23:28:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[23:28:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[23:28:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[23:28:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[23:28:50] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[23:28:50] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[23:28:50] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[23:28:50] [PASSED] drm_test_check_output_bpc_dvi
[23:28:50] [PASSED] drm_test_check_output_bpc_format_vic_1
[23:28:50] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[23:28:50] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[23:28:50] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[23:28:50] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[23:28:50] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[23:28:50] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[23:28:50] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[23:28:50] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[23:28:50] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[23:28:50] [PASSED] drm_test_check_broadcast_rgb_value
[23:28:50] [PASSED] drm_test_check_bpc_8_value
[23:28:50] [PASSED] drm_test_check_bpc_10_value
[23:28:50] [PASSED] drm_test_check_bpc_12_value
[23:28:50] [PASSED] drm_test_check_format_value
[23:28:50] [PASSED] drm_test_check_tmds_char_value
[23:28:50] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[23:28:50] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[23:28:50] [PASSED] drm_test_check_mode_valid
[23:28:50] [PASSED] drm_test_check_mode_valid_reject
[23:28:50] [PASSED] drm_test_check_mode_valid_reject_rate
[23:28:50] [PASSED] drm_test_check_mode_valid_reject_max_clock
[23:28:50] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[23:28:50] ================= drm_managed (2 subtests) =================
[23:28:50] [PASSED] drm_test_managed_release_action
[23:28:50] [PASSED] drm_test_managed_run_action
[23:28:50] =================== [PASSED] drm_managed ===================
[23:28:50] =================== drm_mm (6 subtests) ====================
[23:28:50] [PASSED] drm_test_mm_init
[23:28:50] [PASSED] drm_test_mm_debug
[23:28:50] [PASSED] drm_test_mm_align32
[23:28:50] [PASSED] drm_test_mm_align64
[23:28:50] [PASSED] drm_test_mm_lowest
[23:28:50] [PASSED] drm_test_mm_highest
[23:28:50] ===================== [PASSED] drm_mm ======================
[23:28:50] ============= drm_modes_analog_tv (5 subtests) =============
[23:28:50] [PASSED] drm_test_modes_analog_tv_mono_576i
[23:28:50] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[23:28:50] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[23:28:50] [PASSED] drm_test_modes_analog_tv_pal_576i
[23:28:50] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[23:28:50] =============== [PASSED] drm_modes_analog_tv ===============
[23:28:50] ============== drm_plane_helper (2 subtests) ===============
[23:28:50] =============== drm_test_check_plane_state ================
[23:28:50] [PASSED] clipping_simple
[23:28:50] [PASSED] clipping_rotate_reflect
[23:28:50] [PASSED] positioning_simple
[23:28:50] [PASSED] upscaling
[23:28:50] [PASSED] downscaling
[23:28:50] [PASSED] rounding1
[23:28:50] [PASSED] rounding2
[23:28:50] [PASSED] rounding3
[23:28:50] [PASSED] rounding4
[23:28:50] =========== [PASSED] drm_test_check_plane_state ============
[23:28:50] =========== drm_test_check_invalid_plane_state ============
[23:28:50] [PASSED] positioning_invalid
[23:28:50] [PASSED] upscaling_invalid
[23:28:50] [PASSED] downscaling_invalid
[23:28:50] ======= [PASSED] drm_test_check_invalid_plane_state ========
[23:28:50] ================ [PASSED] drm_plane_helper =================
[23:28:50] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[23:28:50] ====== drm_test_connector_helper_tv_get_modes_check =======
[23:28:50] [PASSED] None
[23:28:50] [PASSED] PAL
[23:28:50] [PASSED] NTSC
[23:28:50] [PASSED] Both, NTSC Default
[23:28:50] [PASSED] Both, PAL Default
[23:28:50] [PASSED] Both, NTSC Default, with PAL on command-line
[23:28:50] [PASSED] Both, PAL Default, with NTSC on command-line
[23:28:50] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[23:28:50] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[23:28:50] ================== drm_rect (9 subtests) ===================
[23:28:50] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[23:28:50] [PASSED] drm_test_rect_clip_scaled_not_clipped
[23:28:50] [PASSED] drm_test_rect_clip_scaled_clipped
[23:28:50] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[23:28:50] ================= drm_test_rect_intersect =================
[23:28:50] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[23:28:50] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[23:28:50] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[23:28:50] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[23:28:50] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[23:28:50] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[23:28:50] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[23:28:50] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[23:28:50] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[23:28:50] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[23:28:50] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[23:28:50] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[23:28:50] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[23:28:50] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[23:28:50] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[23:28:50] ============= [PASSED] drm_test_rect_intersect =============
[23:28:50] ================ drm_test_rect_calc_hscale ================
[23:28:50] [PASSED] normal use
[23:28:50] [PASSED] out of max range
[23:28:50] [PASSED] out of min range
[23:28:50] [PASSED] zero dst
[23:28:50] [PASSED] negative src
[23:28:50] [PASSED] negative dst
[23:28:50] ============ [PASSED] drm_test_rect_calc_hscale ============
[23:28:50] ================ drm_test_rect_calc_vscale ================
[23:28:50] [PASSED] normal use
[23:28:50] [PASSED] out of max range
[23:28:50] [PASSED] out of min range
[23:28:50] [PASSED] zero dst
[23:28:50] [PASSED] negative src
stty: 'standard input': Inappropriate ioctl for device
[23:28:50] [PASSED] negative dst
[23:28:50] ============ [PASSED] drm_test_rect_calc_vscale ============
[23:28:50] ================== drm_test_rect_rotate ===================
[23:28:50] [PASSED] reflect-x
[23:28:50] [PASSED] reflect-y
[23:28:50] [PASSED] rotate-0
[23:28:50] [PASSED] rotate-90
[23:28:50] [PASSED] rotate-180
[23:28:50] [PASSED] rotate-270
[23:28:50] ============== [PASSED] drm_test_rect_rotate ===============
[23:28:50] ================ drm_test_rect_rotate_inv =================
[23:28:50] [PASSED] reflect-x
[23:28:50] [PASSED] reflect-y
[23:28:50] [PASSED] rotate-0
[23:28:50] [PASSED] rotate-90
[23:28:50] [PASSED] rotate-180
[23:28:50] [PASSED] rotate-270
[23:28:50] ============ [PASSED] drm_test_rect_rotate_inv =============
[23:28:50] ==================== [PASSED] drm_rect =====================
[23:28:50] ============ drm_sysfb_modeset_test (1 subtest) ============
[23:28:50] ============ drm_test_sysfb_build_fourcc_list =============
[23:28:50] [PASSED] no native formats
[23:28:50] [PASSED] XRGB8888 as native format
[23:28:50] [PASSED] remove duplicates
[23:28:50] [PASSED] convert alpha formats
[23:28:50] [PASSED] random formats
[23:28:50] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[23:28:50] ============= [PASSED] drm_sysfb_modeset_test ==============
[23:28:50] ============================================================
[23:28:50] Testing complete. Ran 621 tests: passed: 621
[23:28:50] Elapsed time: 25.603s total, 1.770s configuring, 23.613s building, 0.205s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[23:28:50] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:28:52] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:29:01] Starting KUnit Kernel (1/1)...
[23:29:01] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:29:01] ================= ttm_device (5 subtests) ==================
[23:29:01] [PASSED] ttm_device_init_basic
[23:29:01] [PASSED] ttm_device_init_multiple
[23:29:01] [PASSED] ttm_device_fini_basic
[23:29:01] [PASSED] ttm_device_init_no_vma_man
[23:29:01] ================== ttm_device_init_pools ==================
[23:29:01] [PASSED] No DMA allocations, no DMA32 required
[23:29:01] [PASSED] DMA allocations, DMA32 required
[23:29:01] [PASSED] No DMA allocations, DMA32 required
[23:29:01] [PASSED] DMA allocations, no DMA32 required
[23:29:01] ============== [PASSED] ttm_device_init_pools ==============
[23:29:01] =================== [PASSED] ttm_device ====================
[23:29:01] ================== ttm_pool (8 subtests) ===================
[23:29:01] ================== ttm_pool_alloc_basic ===================
[23:29:01] [PASSED] One page
[23:29:01] [PASSED] More than one page
[23:29:01] [PASSED] Above the allocation limit
[23:29:01] [PASSED] One page, with coherent DMA mappings enabled
[23:29:01] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:29:01] ============== [PASSED] ttm_pool_alloc_basic ===============
[23:29:01] ============== ttm_pool_alloc_basic_dma_addr ==============
[23:29:01] [PASSED] One page
[23:29:01] [PASSED] More than one page
[23:29:01] [PASSED] Above the allocation limit
[23:29:01] [PASSED] One page, with coherent DMA mappings enabled
[23:29:01] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:29:01] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[23:29:01] [PASSED] ttm_pool_alloc_order_caching_match
[23:29:01] [PASSED] ttm_pool_alloc_caching_mismatch
[23:29:01] [PASSED] ttm_pool_alloc_order_mismatch
[23:29:01] [PASSED] ttm_pool_free_dma_alloc
[23:29:01] [PASSED] ttm_pool_free_no_dma_alloc
[23:29:01] [PASSED] ttm_pool_fini_basic
[23:29:01] ==================== [PASSED] ttm_pool =====================
[23:29:01] ================ ttm_resource (8 subtests) =================
[23:29:01] ================= ttm_resource_init_basic =================
[23:29:01] [PASSED] Init resource in TTM_PL_SYSTEM
[23:29:01] [PASSED] Init resource in TTM_PL_VRAM
[23:29:01] [PASSED] Init resource in a private placement
[23:29:01] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[23:29:01] ============= [PASSED] ttm_resource_init_basic =============
[23:29:01] [PASSED] ttm_resource_init_pinned
[23:29:01] [PASSED] ttm_resource_fini_basic
[23:29:01] [PASSED] ttm_resource_manager_init_basic
[23:29:01] [PASSED] ttm_resource_manager_usage_basic
[23:29:01] [PASSED] ttm_resource_manager_set_used_basic
[23:29:01] [PASSED] ttm_sys_man_alloc_basic
[23:29:01] [PASSED] ttm_sys_man_free_basic
[23:29:01] ================== [PASSED] ttm_resource ===================
[23:29:01] =================== ttm_tt (15 subtests) ===================
[23:29:01] ==================== ttm_tt_init_basic ====================
[23:29:01] [PASSED] Page-aligned size
[23:29:01] [PASSED] Extra pages requested
[23:29:01] ================ [PASSED] ttm_tt_init_basic ================
[23:29:01] [PASSED] ttm_tt_init_misaligned
[23:29:01] [PASSED] ttm_tt_fini_basic
[23:29:01] [PASSED] ttm_tt_fini_sg
[23:29:01] [PASSED] ttm_tt_fini_shmem
[23:29:01] [PASSED] ttm_tt_create_basic
[23:29:01] [PASSED] ttm_tt_create_invalid_bo_type
[23:29:01] [PASSED] ttm_tt_create_ttm_exists
[23:29:01] [PASSED] ttm_tt_create_failed
[23:29:01] [PASSED] ttm_tt_destroy_basic
[23:29:01] [PASSED] ttm_tt_populate_null_ttm
[23:29:01] [PASSED] ttm_tt_populate_populated_ttm
[23:29:01] [PASSED] ttm_tt_unpopulate_basic
[23:29:01] [PASSED] ttm_tt_unpopulate_empty_ttm
[23:29:01] [PASSED] ttm_tt_swapin_basic
[23:29:01] ===================== [PASSED] ttm_tt ======================
[23:29:01] =================== ttm_bo (14 subtests) ===================
[23:29:01] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[23:29:01] [PASSED] Cannot be interrupted and sleeps
[23:29:01] [PASSED] Cannot be interrupted, locks straight away
[23:29:01] [PASSED] Can be interrupted, sleeps
[23:29:01] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[23:29:01] [PASSED] ttm_bo_reserve_locked_no_sleep
[23:29:01] [PASSED] ttm_bo_reserve_no_wait_ticket
[23:29:01] [PASSED] ttm_bo_reserve_double_resv
[23:29:01] [PASSED] ttm_bo_reserve_interrupted
[23:29:01] [PASSED] ttm_bo_reserve_deadlock
[23:29:01] [PASSED] ttm_bo_unreserve_basic
[23:29:01] [PASSED] ttm_bo_unreserve_pinned
[23:29:01] [PASSED] ttm_bo_unreserve_bulk
[23:29:01] [PASSED] ttm_bo_fini_basic
[23:29:01] [PASSED] ttm_bo_fini_shared_resv
[23:29:01] [PASSED] ttm_bo_pin_basic
[23:29:01] [PASSED] ttm_bo_pin_unpin_resource
[23:29:01] [PASSED] ttm_bo_multiple_pin_one_unpin
[23:29:01] ===================== [PASSED] ttm_bo ======================
[23:29:01] ============== ttm_bo_validate (21 subtests) ===============
[23:29:01] ============== ttm_bo_init_reserved_sys_man ===============
[23:29:01] [PASSED] Buffer object for userspace
[23:29:01] [PASSED] Kernel buffer object
[23:29:01] [PASSED] Shared buffer object
[23:29:01] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[23:29:01] ============== ttm_bo_init_reserved_mock_man ==============
[23:29:01] [PASSED] Buffer object for userspace
[23:29:01] [PASSED] Kernel buffer object
[23:29:01] [PASSED] Shared buffer object
[23:29:01] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[23:29:01] [PASSED] ttm_bo_init_reserved_resv
[23:29:01] ================== ttm_bo_validate_basic ==================
[23:29:01] [PASSED] Buffer object for userspace
[23:29:01] [PASSED] Kernel buffer object
[23:29:01] [PASSED] Shared buffer object
[23:29:01] ============== [PASSED] ttm_bo_validate_basic ==============
[23:29:01] [PASSED] ttm_bo_validate_invalid_placement
[23:29:01] ============= ttm_bo_validate_same_placement ==============
[23:29:01] [PASSED] System manager
[23:29:01] [PASSED] VRAM manager
[23:29:01] ========= [PASSED] ttm_bo_validate_same_placement ==========
[23:29:01] [PASSED] ttm_bo_validate_failed_alloc
[23:29:01] [PASSED] ttm_bo_validate_pinned
[23:29:01] [PASSED] ttm_bo_validate_busy_placement
[23:29:01] ================ ttm_bo_validate_multihop =================
[23:29:01] [PASSED] Buffer object for userspace
[23:29:01] [PASSED] Kernel buffer object
[23:29:01] [PASSED] Shared buffer object
[23:29:01] ============ [PASSED] ttm_bo_validate_multihop =============
[23:29:01] ========== ttm_bo_validate_no_placement_signaled ==========
[23:29:01] [PASSED] Buffer object in system domain, no page vector
[23:29:01] [PASSED] Buffer object in system domain with an existing page vector
[23:29:01] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[23:29:01] ======== ttm_bo_validate_no_placement_not_signaled ========
[23:29:01] [PASSED] Buffer object for userspace
[23:29:01] [PASSED] Kernel buffer object
[23:29:01] [PASSED] Shared buffer object
[23:29:01] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[23:29:01] [PASSED] ttm_bo_validate_move_fence_signaled
[23:29:01] ========= ttm_bo_validate_move_fence_not_signaled =========
[23:29:01] [PASSED] Waits for GPU
[23:29:01] [PASSED] Tries to lock straight away
[23:29:01] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[23:29:01] [PASSED] ttm_bo_validate_happy_evict
[23:29:01] [PASSED] ttm_bo_validate_all_pinned_evict
[23:29:01] [PASSED] ttm_bo_validate_allowed_only_evict
[23:29:01] [PASSED] ttm_bo_validate_deleted_evict
[23:29:01] [PASSED] ttm_bo_validate_busy_domain_evict
[23:29:01] [PASSED] ttm_bo_validate_evict_gutting
[23:29:01] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[23:29:01] ================= [PASSED] ttm_bo_validate =================
[23:29:01] ============================================================
[23:29:01] Testing complete. Ran 101 tests: passed: 101
[23:29:01] Elapsed time: 11.100s total, 1.724s configuring, 9.110s building, 0.238s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915/vrr: Hide even more ICL/TGL weirdness
2025-09-18 23:22 [PATCH 0/2] drm/i915/vrr: Hide even more ICL/TGL weirdness Ville Syrjala
` (2 preceding siblings ...)
2025-09-18 23:29 ` ✓ CI.KUnit: success for drm/i915/vrr: Hide even more ICL/TGL weirdness Patchwork
@ 2025-09-19 0:03 ` Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2025-09-19 0:03 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 869 bytes --]
== Series Details ==
Series: drm/i915/vrr: Hide even more ICL/TGL weirdness
URL : https://patchwork.freedesktop.org/series/154745/
State : success
== Summary ==
CI Bug Log - changes from xe-3794-d96edc0e90a16032294fb5c32aa8139fbc052a1e_BAT -> xe-pw-154745v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-3794-d96edc0e90a16032294fb5c32aa8139fbc052a1e -> xe-pw-154745v1
IGT_8543: 8543
xe-3794-d96edc0e90a16032294fb5c32aa8139fbc052a1e: d96edc0e90a16032294fb5c32aa8139fbc052a1e
xe-pw-154745v1: 154745v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154745v1/index.html
[-- Attachment #2: Type: text/html, Size: 1417 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915/vrr: Hide the ICL/TGL intel_vrr_flipline_offset() mangling better
2025-09-18 23:22 ` [PATCH 1/2] drm/i915/vrr: Hide the ICL/TGL intel_vrr_flipline_offset() mangling better Ville Syrjala
@ 2025-09-19 10:49 ` Nautiyal, Ankit K
0 siblings, 0 replies; 7+ messages in thread
From: Nautiyal, Ankit K @ 2025-09-19 10:49 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On 9/19/2025 4:52 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> ICL/TGL VRR hardware won't allow us to program flipline==vmin. If we do
> that the actual effect will be the same as if we had programmed
> flipline=vmin+1, which would make the minimum vtotal one scanline taller
> than expected.
>
> To compensate for this we reduce vmin by one, and then program
> flipline=vmin+1. So we end up with a flipline value that matches
> the expected minimum vtotal. Currently this adjustment happens
> in intel_vrr_compute_config() which means that crtc_state->vrr.vmin
> will no longer be directly usable for the remainder of the high
> level VRR code. That is annoying at best, fragile at worst.
>
> Hide the adjustment in low level code instead. This will allow most
> of the higher level VRR code to remain blissfully ignorant about this
> fact. Afterwards crtc_state->vrr.{vmin,flipline} will be equal
> and match the minimum vtotal, exactly how things already work
> on ADL+.
>
> The only slight downside is that the actual register value will no
> longer match crtc_state->vrr.vmin on ICL/TGL, but that may already
> be the case on TGL because the register value will also have been
> adjusted by the SCL.
>
> Note that we must change the guardband calculation to account
> for intel_vrr_extra_vblank_delay() explicitly. Previously that
> was accidentally handled by the earlier vmin reduction by
> intel_vrr_flipline_offset().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 30 ++++++++++++++----------
> 1 file changed, 17 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 71a985d00604..e725b4581e81 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -108,15 +108,20 @@ int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state)
>
> static int intel_vrr_flipline_offset(struct intel_display *display)
> {
> - /* ICL/TGL hardware imposes flipline>=vmin+1 */
> + /*
> + * ICL/TGL hardware imposes flipline>=vmin+1
> + *
> + * We reduce the vmin value to compensate when programming the
> + * hardware. This approach allows flipline to remain set at the
> + * original value, and thus the frame will have the desired
> + * minimum vtotal.
> + */
> return DISPLAY_VER(display) < 13 ? 1 : 0;
> }
>
> static int intel_vrr_vmin_flipline(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_display *display = to_intel_display(crtc_state);
> -
> - return crtc_state->vrr.vmin + intel_vrr_flipline_offset(display);
> + return crtc_state->vrr.vmin;
> }
>
> static int intel_vrr_guardband_to_pipeline_full(const struct intel_crtc_state *crtc_state,
> @@ -400,13 +405,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> else
> intel_vrr_compute_fixed_rr_timings(crtc_state);
>
> - /*
> - * flipline determines the min vblank length the hardware will
> - * generate, and on ICL/TGL flipline>=vmin+1, hence we reduce
> - * vmin by one to make sure we can get the actual min vblank length.
> - */
> - crtc_state->vrr.vmin -= intel_vrr_flipline_offset(display);
> -
> if (HAS_AS_SDP(display)) {
> crtc_state->vrr.vsync_start =
> (crtc_state->hw.adjusted_mode.crtc_vtotal -
> @@ -426,7 +424,8 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
> return;
>
> crtc_state->vrr.guardband =
> - crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
> + crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
> + intel_vrr_extra_vblank_delay(display);
>
> if (DISPLAY_VER(display) < 13) {
> /* FIXME handle the limit in a proper way */
> @@ -597,7 +596,10 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
>
> static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
> {
> - return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmin);
> + struct intel_display *display = to_intel_display(crtc_state);
> +
> + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmin) -
> + intel_vrr_flipline_offset(display);
> }
>
> static int intel_vrr_hw_vmax(const struct intel_crtc_state *crtc_state)
> @@ -762,6 +764,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> crtc_state->vrr.flipline += intel_vrr_real_vblank_delay(crtc_state);
> crtc_state->vrr.vmax += intel_vrr_real_vblank_delay(crtc_state);
> crtc_state->vrr.vmin += intel_vrr_real_vblank_delay(crtc_state);
> +
> + crtc_state->vrr.vmin += intel_vrr_flipline_offset(display);
> }
>
> /*
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915/vrr: s/intel_vrr_flipline_offset/intel_vrr_vmin_flipline_offset/
2025-09-18 23:22 ` [PATCH 2/2] drm/i915/vrr: s/intel_vrr_flipline_offset/intel_vrr_vmin_flipline_offset/ Ville Syrjala
@ 2025-09-19 10:49 ` Nautiyal, Ankit K
0 siblings, 0 replies; 7+ messages in thread
From: Nautiyal, Ankit K @ 2025-09-19 10:49 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On 9/19/2025 4:52 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename intel_vrr_flipline_offset() to intel_vrr_vmin_flipline_offset()
> to better reflect the fact that it gives us the minimum offset allowed
> between vmin and flipline.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index e725b4581e81..9e007aab1452 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -106,7 +106,7 @@ int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state)
> intel_vrr_extra_vblank_delay(display);
> }
>
> -static int intel_vrr_flipline_offset(struct intel_display *display)
> +static int intel_vrr_vmin_flipline_offset(struct intel_display *display)
> {
> /*
> * ICL/TGL hardware imposes flipline>=vmin+1
> @@ -288,7 +288,7 @@ int intel_vrr_fixed_rr_hw_vmin(const struct intel_crtc_state *crtc_state)
> struct intel_display *display = to_intel_display(crtc_state);
>
> return intel_vrr_fixed_rr_hw_vtotal(crtc_state) -
> - intel_vrr_flipline_offset(display);
> + intel_vrr_vmin_flipline_offset(display);
> }
>
> static
> @@ -599,7 +599,7 @@ static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
> struct intel_display *display = to_intel_display(crtc_state);
>
> return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmin) -
> - intel_vrr_flipline_offset(display);
> + intel_vrr_vmin_flipline_offset(display);
> }
>
> static int intel_vrr_hw_vmax(const struct intel_crtc_state *crtc_state)
> @@ -765,7 +765,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> crtc_state->vrr.vmax += intel_vrr_real_vblank_delay(crtc_state);
> crtc_state->vrr.vmin += intel_vrr_real_vblank_delay(crtc_state);
>
> - crtc_state->vrr.vmin += intel_vrr_flipline_offset(display);
> + crtc_state->vrr.vmin += intel_vrr_vmin_flipline_offset(display);
> }
>
> /*
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-09-19 10:49 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2025-09-18 23:22 [PATCH 0/2] drm/i915/vrr: Hide even more ICL/TGL weirdness Ville Syrjala
2025-09-18 23:22 ` [PATCH 1/2] drm/i915/vrr: Hide the ICL/TGL intel_vrr_flipline_offset() mangling better Ville Syrjala
2025-09-19 10:49 ` Nautiyal, Ankit K
2025-09-18 23:22 ` [PATCH 2/2] drm/i915/vrr: s/intel_vrr_flipline_offset/intel_vrr_vmin_flipline_offset/ Ville Syrjala
2025-09-19 10:49 ` Nautiyal, Ankit K
2025-09-18 23:29 ` ✓ CI.KUnit: success for drm/i915/vrr: Hide even more ICL/TGL weirdness Patchwork
2025-09-19 0:03 ` ✓ Xe.CI.BAT: " Patchwork
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