* [PATCH v9 0/4] drm/xe/guc: Add GuC based register capture for error capture
@ 2024-06-07 0:07 Zhanjun Dong
2024-06-07 0:07 ` [PATCH v9 1/4] drm/xe/guc: Prepare GuC register list and update ADS size " Zhanjun Dong
` (11 more replies)
0 siblings, 12 replies; 24+ messages in thread
From: Zhanjun Dong @ 2024-06-07 0:07 UTC (permalink / raw)
To: intel-xe; +Cc: Zhanjun Dong, Alan Previn
Port GuC based register capture for error capture from i915 to Xe.
There are 3 parts inside:
. Prepare for capture registers
There is a bo create at guc ads init time, that is very early
and engi ne map is not ready, make it hard to calculate the
capture buffer size, new function created for worst case size
caluation. Other than that, this part basically follows the i915
design.
. Process capture notification message
Basically follows i915 design
. Sysfs command process.
Xe switched to devcoredump, adopted command line process with
captured node list.
Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com>
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Changes from prior revs:
v9:- Merged snapshot register list into capture register lists
Optimized devcoredump timing to take snapshot after guc reset
Add global and engine class registers into capture list
Fixed bug of incorrect matching guc class id with guc capture class id
v8:- Reorgnize the order of patches
Change the capture size check from worst min size to worst size
Replace the kernel alloc with drm managed alloc
Replace the memcpy with xe_map_memcpy_from
Free GuC capture outlist as part of xe_devcoredump_free
v7:- Kconfig CONFIG_DRM_XE_CAPTURE_ERROR removed
v6:- Change hardcoded register snapshot fill to follow mapping tables
When capture is empty, take snapshot from engine
v5:- Split dss helper code out as an standalone patch
Remove old platform registers definition.
Split register map table to 32 and 64bit each
v4:- Move register map table to xe_hw_engine.c
v3:- Remove condition compilation in code
v2:- Split into multiple chunks
Zhanjun Dong (4):
drm/xe/guc: Prepare GuC register list and update ADS size for error
capture
drm/xe/guc: Add XE_LP steered register lists
drm/xe/guc: Add capture size check in GuC log buffer
drm/xe/guc: Extract GuC capture lists to register snapshot
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/abi/guc_actions_abi.h | 7 +
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
drivers/gpu/drm/xe/xe_devcoredump.c | 4 +
drivers/gpu/drm/xe/xe_devcoredump_types.h | 2 +
drivers/gpu/drm/xe/xe_gt_printk.h | 3 +
drivers/gpu/drm/xe/xe_guc.c | 5 +
drivers/gpu/drm/xe/xe_guc.h | 28 +
drivers/gpu/drm/xe/xe_guc_ads.c | 213 +++-
drivers/gpu/drm/xe/xe_guc_ads.h | 3 +
drivers/gpu/drm/xe/xe_guc_ads_types.h | 2 +
drivers/gpu/drm/xe/xe_guc_capture.c | 1412 +++++++++++++++++++++
drivers/gpu/drm/xe/xe_guc_capture.h | 53 +
drivers/gpu/drm/xe/xe_guc_capture_fwif.h | 198 +++
drivers/gpu/drm/xe/xe_guc_ct.c | 2 +
drivers/gpu/drm/xe/xe_guc_fwif.h | 76 ++
drivers/gpu/drm/xe/xe_guc_log.c | 179 +++
drivers/gpu/drm/xe/xe_guc_log.h | 17 +-
drivers/gpu/drm/xe/xe_guc_log_types.h | 24 +
drivers/gpu/drm/xe/xe_guc_submit.c | 63 +-
drivers/gpu/drm/xe/xe_guc_submit.h | 2 +
drivers/gpu/drm/xe/xe_guc_types.h | 2 +
drivers/gpu/drm/xe/xe_hw_engine.c | 218 ++--
drivers/gpu/drm/xe/xe_hw_engine_types.h | 159 ++-
drivers/gpu/drm/xe/xe_lrc.h | 1 +
25 files changed, 2510 insertions(+), 166 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_guc_capture.c
create mode 100644 drivers/gpu/drm/xe/xe_guc_capture.h
create mode 100644 drivers/gpu/drm/xe/xe_guc_capture_fwif.h
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH v9 1/4] drm/xe/guc: Prepare GuC register list and update ADS size for error capture 2024-06-07 0:07 [PATCH v9 0/4] drm/xe/guc: Add GuC based register capture for error capture Zhanjun Dong @ 2024-06-07 0:07 ` Zhanjun Dong 2024-06-14 11:50 ` Michal Wajdeczko 2024-06-07 0:07 ` [PATCH v9 2/4] drm/xe/guc: Add XE_LP steered register lists Zhanjun Dong ` (10 subsequent siblings) 11 siblings, 1 reply; 24+ messages in thread From: Zhanjun Dong @ 2024-06-07 0:07 UTC (permalink / raw) To: intel-xe; +Cc: Zhanjun Dong Add referenced registers defines and list of registers. Update GuC ADS size allocation to include space for the lists of error state capture register descriptors. Then, populate GuC ADS with the lists of registers we want GuC to report back to host on engine reset events. This list should include global, engine-class and engine-instance registers for every engine-class type on the current hardware. Ensure we allocate a persistent store for the register lists that are populated into ADS so that we don't need to allocate memory during GT resets when GuC is reloaded and ADS population happens again. Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> --- drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/xe_guc.c | 5 + drivers/gpu/drm/xe/xe_guc.h | 5 + drivers/gpu/drm/xe/xe_guc_ads.c | 213 +++++++++++++- drivers/gpu/drm/xe/xe_guc_ads.h | 3 + drivers/gpu/drm/xe/xe_guc_ads_types.h | 2 + drivers/gpu/drm/xe/xe_guc_capture.c | 352 +++++++++++++++++++++++ drivers/gpu/drm/xe/xe_guc_capture.h | 43 +++ drivers/gpu/drm/xe/xe_guc_capture_fwif.h | 145 ++++++++++ drivers/gpu/drm/xe/xe_guc_fwif.h | 22 ++ drivers/gpu/drm/xe/xe_guc_types.h | 2 + 11 files changed, 781 insertions(+), 12 deletions(-) create mode 100644 drivers/gpu/drm/xe/xe_guc_capture.c create mode 100644 drivers/gpu/drm/xe/xe_guc_capture.h create mode 100644 drivers/gpu/drm/xe/xe_guc_capture_fwif.h diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 0c3e3adabb27..2454443fc6a3 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -71,6 +71,7 @@ xe-y += xe_bb.o \ xe_gt_topology.o \ xe_guc.o \ xe_guc_ads.o \ + xe_guc_capture.o \ xe_guc_ct.o \ xe_guc_db_mgr.o \ xe_guc_debugfs.o \ diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c index 0bf6e01b8910..6860c92f3547 100644 --- a/drivers/gpu/drm/xe/xe_guc.c +++ b/drivers/gpu/drm/xe/xe_guc.c @@ -22,6 +22,7 @@ #include "xe_gt_sriov_vf.h" #include "xe_gt_throttle.h" #include "xe_guc_ads.h" +#include "xe_guc_capture.h" #include "xe_guc_ct.h" #include "xe_guc_db_mgr.h" #include "xe_guc_hwconfig.h" @@ -338,6 +339,10 @@ int xe_guc_init(struct xe_guc *guc) if (ret) goto out; + ret = xe_guc_capture_init(guc); + if (ret) + goto out; + ret = xe_guc_ads_init(&guc->ads); if (ret) goto out; diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h index af59c9545753..ddfa855458ab 100644 --- a/drivers/gpu/drm/xe/xe_guc.h +++ b/drivers/gpu/drm/xe/xe_guc.h @@ -69,4 +69,9 @@ static inline struct xe_device *guc_to_xe(struct xe_guc *guc) return gt_to_xe(guc_to_gt(guc)); } +static inline struct drm_device *guc_to_drm(struct xe_guc *guc) +{ + return &guc_to_xe(guc)->drm; +} + #endif diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c index 1c60b685dbc6..7c4ca986db68 100644 --- a/drivers/gpu/drm/xe/xe_guc_ads.c +++ b/drivers/gpu/drm/xe/xe_guc_ads.c @@ -18,6 +18,8 @@ #include "xe_gt_ccs_mode.h" #include "xe_gt_printk.h" #include "xe_guc.h" +#include "xe_guc_capture.h" +#include "xe_guc_capture_fwif.h" #include "xe_guc_ct.h" #include "xe_hw_engine.h" #include "xe_lrc.h" @@ -127,6 +129,8 @@ struct __guc_ads_blob { #define info_map_read(xe_, map_, field_) \ xe_map_rd_field(xe_, map_, 0, struct guc_gt_system_info, field_) +static int guc_capture_prep_lists(struct xe_guc_ads *ads); + static size_t guc_ads_regset_size(struct xe_guc_ads *ads) { struct xe_device *xe = ads_to_xe(ads); @@ -148,8 +152,7 @@ static u32 guc_ads_waklv_size(struct xe_guc_ads *ads) static size_t guc_ads_capture_size(struct xe_guc_ads *ads) { - /* FIXME: Allocate a proper capture list */ - return PAGE_ALIGN(PAGE_SIZE); + return PAGE_ALIGN(ads->capture_size); } static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads) @@ -388,6 +391,48 @@ static int calculate_waklv_size(struct xe_guc_ads *ads) return SZ_4K; } +/** + * xe_guc_capture_ads_input_worst_size - Calculate the worst size for GuC register capture + * @guc: point to xe_guc structure + * + * Calculate the worst size for GuC register capture by including all possible engines classes. + * + * Returns: Calculated size + */ +int xe_guc_capture_ads_input_worst_size(struct xe_guc *guc) +{ + size_t total_size, class_size, instance_size, global_size; + int i, j; + + /* This function calculates the worst case register lists size by + * including all possible engines classes. It is called during the + * first of a two-phase GuC (and ADS-population) initialization + * sequence, that is, during the pre-hwconfig phase before we have + * the exact engine fusing info. + */ + total_size = PAGE_SIZE; /* Pad a page in front for empty lists */ + for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) { + for (j = 0; j < GUC_CAPTURE_LIST_CLASS_MAX; j++) { + if (xe_guc_capture_getlistsize(guc, i, + GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, + j, &class_size) < 0) + class_size = 0; + if (xe_guc_capture_getlistsize(guc, i, + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, + j, &instance_size) < 0) + instance_size = 0; + total_size += class_size + instance_size; + } + if (xe_guc_capture_getlistsize(guc, i, + GUC_CAPTURE_LIST_TYPE_GLOBAL, + 0, &global_size) < 0) + global_size = 0; + total_size += global_size; + } + + return PAGE_ALIGN(total_size); +} + #define MAX_GOLDEN_LRC_SIZE (SZ_4K * 64) int xe_guc_ads_init(struct xe_guc_ads *ads) @@ -398,6 +443,10 @@ int xe_guc_ads_init(struct xe_guc_ads *ads) struct xe_bo *bo; ads->golden_lrc_size = calculate_golden_lrc_size(ads); + /* At time of ads init, hwconfig was not loaded, engine info like engine mask is not ready. + * Capture size is using the worst size calculation. + */ + ads->capture_size = xe_guc_capture_ads_input_worst_size(ads_to_guc(ads)); ads->regset_size = calculate_regset_size(gt); ads->ads_waklv_size = calculate_waklv_size(ads); @@ -431,10 +480,11 @@ int xe_guc_ads_init_post_hwconfig(struct xe_guc_ads *ads) xe_gt_assert(gt, ads->bo); ads->golden_lrc_size = calculate_golden_lrc_size(ads); + /* Calculate Capture size with worst size */ + ads->capture_size = xe_guc_capture_ads_input_worst_size(ads_to_guc(ads)); ads->regset_size = calculate_regset_size(gt); - xe_gt_assert(gt, ads->golden_lrc_size + - (ads->regset_size - prev_regset_size) <= + xe_gt_assert(gt, ads->golden_lrc_size + (ads->regset_size - prev_regset_size) <= MAX_GOLDEN_LRC_SIZE); return 0; @@ -530,20 +580,159 @@ static void guc_mapping_table_init(struct xe_gt *gt, } } -static void guc_capture_list_init(struct xe_guc_ads *ads) +static u32 guc_get_capture_engine_mask(struct xe_gt *gt, struct iosys_map *info_map, + u32 capture_class) { + struct xe_device *xe = gt_to_xe(gt); + u32 mask; + + switch (capture_class) { + case GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE: + mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_RENDER_CLASS]); + mask |= info_map_read(xe, info_map, engine_enabled_masks[GUC_COMPUTE_CLASS]); + break; + case GUC_CAPTURE_LIST_CLASS_VIDEO: + mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_VIDEO_CLASS]); + break; + case GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE: + mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS]); + break; + case GUC_CAPTURE_LIST_CLASS_BLITTER: + mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_BLITTER_CLASS]); + break; + case GUC_CAPTURE_LIST_CLASS_GSC_OTHER: + mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS]); + break; + default: + mask = 0; + } + + return mask; +} + +static int guc_capture_prep_lists(struct xe_guc_ads *ads) +{ + struct xe_guc *guc = ads_to_guc(ads); + struct xe_gt *gt = ads_to_gt(ads); + u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0; + struct iosys_map info_map; + size_t size = 0; + void *ptr; int i, j; - u32 addr = xe_bo_ggtt_addr(ads->bo) + guc_ads_capture_offset(ads); - /* FIXME: Populate a proper capture list */ + capture_offset = guc_ads_capture_offset(ads); + ads_ggtt = xe_bo_ggtt_addr(ads->bo); + info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), + offsetof(struct __guc_ads_blob, system_info)); + + /* first, set aside the first page for a capture_list with zero descriptors */ + total_size = PAGE_SIZE; + if (!xe_guc_capture_getnullheader(guc, &ptr, &size)) + xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, ptr, size); + + null_ggtt = ads_ggtt + capture_offset; + capture_offset += PAGE_SIZE; + + /* Populate capture list : at this point adps is already allocated and mapped to worst case + * size + */ for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) { - for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) { - ads_blob_write(ads, ads.capture_instance[i][j], addr); - ads_blob_write(ads, ads.capture_class[i][j], addr); + bool write_empty_list; + + for (j = 0; j < GUC_CAPTURE_LIST_CLASS_MAX; j++) { + u32 engine_mask = guc_get_capture_engine_mask(gt, &info_map, j); + /* null list if we dont have said engine or list */ + if (!engine_mask) { + ads_blob_write(ads, ads.capture_class[i][j], null_ggtt); + ads_blob_write(ads, ads.capture_instance[i][j], null_ggtt); + continue; + } + /********************************************************/ + /*** engine exists: start with engine-class registers ***/ + /********************************************************/ + write_empty_list = true; /* starting assumption is an empty list */ + size = 0; + if (!xe_guc_capture_getlistsize(guc, i, + GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, + j, &size)) { + if (total_size + size > ads->capture_size) + xe_gt_dbg(gt, "Capture size overflow :%zu vs %d\n", + total_size + size, ads->capture_size); + else if (!xe_guc_capture_getlist(guc, i, + GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, + j, &ptr)) + /* everything checked out, populate! */ + write_empty_list = false; + } + if (!write_empty_list) { + ads_blob_write(ads, ads.capture_class[i][j], + ads_ggtt + capture_offset); + xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, + ptr, size); + total_size += size; + capture_offset += size; + } else { + ads_blob_write(ads, ads.capture_class[i][j], null_ggtt); + } + + /********************************************************/ + /*** engine exists: next, engine-instance registers ***/ + /********************************************************/ + write_empty_list = true; /* starting assumption is an empty list */ + size = 0; + if (!xe_guc_capture_getlistsize(guc, i, + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, + j, &size)) { + if (total_size + size > ads->capture_size) + xe_gt_dbg(gt, "Capture size overflow :%zu vs %d\n", + total_size + size, ads->capture_size); + else if (!xe_guc_capture_getlist(guc, i, + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, + j, &ptr)) + /* everything checked out, populate! */ + write_empty_list = false; + } + + if (!write_empty_list) { + ads_blob_write(ads, ads.capture_instance[i][j], + ads_ggtt + capture_offset); + xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, + ptr, size); + total_size += size; + capture_offset += size; + } else { + ads_blob_write(ads, ads.capture_instance[i][j], null_ggtt); + } } - ads_blob_write(ads, ads.capture_global[i], addr); + /********************************************************/ + /*** global registers is last in our PF/VF loops ***/ + /********************************************************/ + write_empty_list = true; /* starting assumption is an empty list */ + size = 0; + if (!xe_guc_capture_getlistsize(guc, i, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &size)) { + if (total_size + size > ads->capture_size) + xe_gt_dbg(gt, "Capture size overflow :%zu vs %d\n", + total_size + size, ads->capture_size); + else if (!xe_guc_capture_getlist(guc, i, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, + &ptr)) + write_empty_list = false; /* everything checked out, populate! */ + } + if (!write_empty_list) { + ads_blob_write(ads, ads.capture_global[i], ads_ggtt + capture_offset); + xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, ptr, + size); + total_size += size; + capture_offset += size; + } else { + ads_blob_write(ads, ads.capture_global[i], null_ggtt); + } } + + if (ads->capture_size != PAGE_ALIGN(total_size)) + xe_gt_info(gt, "ADS capture alloc size changed from %d to %d\n", + ads->capture_size, PAGE_ALIGN(total_size)); + return PAGE_ALIGN(total_size); } static void guc_mmio_regset_write_one(struct xe_guc_ads *ads, @@ -732,7 +921,7 @@ void xe_guc_ads_populate(struct xe_guc_ads *ads) guc_mmio_reg_state_init(ads); guc_prep_golden_lrc_null(ads); guc_mapping_table_init(gt, &info_map); - guc_capture_list_init(ads); + guc_capture_prep_lists(ads); guc_doorbell_init(ads); guc_waklv_init(ads); diff --git a/drivers/gpu/drm/xe/xe_guc_ads.h b/drivers/gpu/drm/xe/xe_guc_ads.h index 2e6674c760ff..11b6e3ea3d9f 100644 --- a/drivers/gpu/drm/xe/xe_guc_ads.h +++ b/drivers/gpu/drm/xe/xe_guc_ads.h @@ -8,11 +8,14 @@ struct xe_guc_ads; +struct xe_guc; + int xe_guc_ads_init(struct xe_guc_ads *ads); int xe_guc_ads_init_post_hwconfig(struct xe_guc_ads *ads); void xe_guc_ads_populate(struct xe_guc_ads *ads); void xe_guc_ads_populate_minimal(struct xe_guc_ads *ads); void xe_guc_ads_populate_post_load(struct xe_guc_ads *ads); int xe_guc_ads_scheduler_policy_toggle_reset(struct xe_guc_ads *ads); +int xe_guc_capture_ads_input_worst_size(struct xe_guc *guc); #endif diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h index 2de5decfe0fd..70c132458ac3 100644 --- a/drivers/gpu/drm/xe/xe_guc_ads_types.h +++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h @@ -22,6 +22,8 @@ struct xe_guc_ads { u32 regset_size; /** @ads_waklv_size: total waklv size supported by platform */ u32 ads_waklv_size; + /** @capture_size: size of register set passed to GuC for capture */ + u32 capture_size; }; #endif diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c new file mode 100644 index 000000000000..19bd79285061 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_guc_capture.c @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2021-2022 Intel Corporation + */ + +#include <linux/types.h> + +#include <drm/drm_managed.h> +#include <drm/drm_print.h> + +#include "abi/guc_actions_abi.h" +#include "regs/xe_engine_regs.h" +#include "regs/xe_gt_regs.h" +#include "regs/xe_guc_regs.h" +#include "regs/xe_regs.h" + +#include "xe_bo.h" +#include "xe_device.h" +#include "xe_exec_queue_types.h" +#include "xe_gt.h" +#include "xe_gt_mcr.h" +#include "xe_gt_printk.h" +#include "xe_guc.h" +#include "xe_guc_capture.h" +#include "xe_guc_capture_fwif.h" +#include "xe_guc_ct.h" +#include "xe_guc_log.h" +#include "xe_guc_submit.h" +#include "xe_hw_engine_types.h" +#include "xe_macros.h" +#include "xe_map.h" + +/* + * Define all device tables of GuC error capture register lists + * NOTE: For engine-registers, GuC only needs the register offsets + * from the engine-mmio-base + */ +#define COMMON_XELP_BASE_GLOBAL \ + { FORCEWAKE_GT, 0, 0} + +#define COMMON_BASE_ENGINE_INSTANCE \ + { RING_ESR(0), 0, 0}, \ + { RING_EMR(0), 0, 0}, \ + { RING_EIR(0), 0, 0}, \ + { RING_EXECLIST_STATUS_HI(0), 0, 0}, \ + { RING_EXECLIST_STATUS_LO(0), 0, 0}, \ + { RING_DMA_FADD(0), 0, 0}, \ + { RING_DMA_FADD_UDW(0), 0, 0}, \ + { RING_IPEHR(0), 0, 0}, \ + { RING_BBADDR(0), 0, 0}, \ + { RING_BBADDR_UDW(0), 0, 0}, \ + { RING_ACTHD(0), 0, 0}, \ + { RING_ACTHD_UDW(0), 0, 0}, \ + { RING_START(0), 0, 0}, \ + { RING_HEAD(0), 0, 0}, \ + { RING_TAIL(0), 0, 0}, \ + { RING_CTL(0), 0, 0}, \ + { RING_MI_MODE(0), 0, 0}, \ + { RING_HWS_PGA(0), 0, 0}, \ + { RING_MODE(0), 0, 0} + +/* XE_LP Global */ +static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = { + COMMON_XELP_BASE_GLOBAL, +}; + +/* Render / Compute Per-Engine-Instance */ +static const struct __guc_mmio_reg_descr xe_rc_inst_regs[] = { + COMMON_BASE_ENGINE_INSTANCE, +}; + +/* Media Decode/Encode Per-Engine-Instance */ +static const struct __guc_mmio_reg_descr xe_vd_inst_regs[] = { + COMMON_BASE_ENGINE_INSTANCE, +}; + +/* Video Enhancement Per-Engine-Instance */ +static const struct __guc_mmio_reg_descr xe_vec_inst_regs[] = { + COMMON_BASE_ENGINE_INSTANCE, +}; + +/* Blitter Per-Engine-Instance */ +static const struct __guc_mmio_reg_descr xe_blt_inst_regs[] = { + COMMON_BASE_ENGINE_INSTANCE, +}; + +/* XE_LP - GSC Per-Engine-Instance */ +static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = { + COMMON_BASE_ENGINE_INSTANCE, +}; + +/* + * Empty list to prevent warnings about unknown class/instance types + * as not all class/instanace types have entries on all platforms. + */ +static const struct __guc_mmio_reg_descr empty_regs_list[] = { +}; + +#define TO_GCAP_DEF_OWNER(x) (GUC_CAPTURE_LIST_INDEX_##x) +#define TO_GCAP_DEF_TYPE(x) (GUC_CAPTURE_LIST_TYPE_##x) +#define MAKE_REGLIST(regslist, regsowner, regstype, class) \ + { \ + regslist, \ + ARRAY_SIZE(regslist), \ + TO_GCAP_DEF_OWNER(regsowner), \ + TO_GCAP_DEF_TYPE(regstype), \ + class, \ + } + +/* List of lists */ +static const struct __guc_mmio_reg_descr_group xe_lp_lists[] = { + MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0), + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE), + MAKE_REGLIST(xe_rc_inst_regs, PF, ENGINE_INSTANCE, + GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE), + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO), + MAKE_REGLIST(xe_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO), + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE), + MAKE_REGLIST(xe_vec_inst_regs, PF, ENGINE_INSTANCE, + GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE), + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER), + MAKE_REGLIST(xe_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER), + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER), + MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER), + {} +}; + +static const char * const capture_list_type_names[] = { + "Global", + "Class", + "Instance", + "unknown", /* Default name, if out of bound */ +}; + +static const char * const capture_engine_class_names[] = { + "Render/Compute", + "Video", + "VideoEnhance", + "Blitter", + "GSC-Other", + "unknown", /* Default name, if out of bound */ +}; + +/* Get item from array by index. + * The last item is the default value, referenced for index out of bound condition. + */ +#define get_item_with_default(ar, index) (ar[(index) >= ARRAY_SIZE(ar) ? ARRAY_SIZE(ar) - 1 : \ + (index)]) + +static const struct __guc_mmio_reg_descr_group * +guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists, + u32 owner, u32 type, u32 id) +{ + int i; + + if (!reglists) + return NULL; + + for (i = 0; reglists[i].list; ++i) { + if (reglists[i].owner == owner && reglists[i].type == type && + (reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL)) + return ®lists[i]; + } + + return NULL; +} + +static const struct __guc_mmio_reg_descr_group * +guc_capture_get_device_reglist(struct xe_guc *guc) +{ + return xe_lp_lists; +} + +static int +guc_capture_list_init(struct xe_guc *guc, u32 owner, u32 type, u32 classid, + struct guc_mmio_reg *ptr, u16 num_entries) +{ + u32 i = 0; + const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists; + const struct __guc_mmio_reg_descr_group *match; + + if (!reglists) + return -ENODEV; + + match = guc_capture_get_one_list(reglists, owner, type, classid); + if (!match) + return -ENODATA; + + for (i = 0; i < num_entries && i < match->num_regs; ++i) { + ptr[i].offset = match->list[i].reg.addr; + ptr[i].value = 0xDEADF00D; + ptr[i].flags = match->list[i].flags; + ptr[i].mask = match->list[i].mask; + } + + if (i < num_entries) + xe_gt_dbg(guc_to_gt(guc), "Got short capture reglist init: %d out %d.\n", i, + num_entries); + + return 0; +} + +static int +guc_cap_list_num_regs(struct xe_guc_state_capture *gc, u32 owner, u32 type, u32 classid) +{ + const struct __guc_mmio_reg_descr_group *match; + + match = guc_capture_get_one_list(gc->reglists, owner, type, classid); + if (!match) + return 0; + + return match->num_regs; +} + +static int +guc_capture_getlistsize(struct xe_guc *guc, u32 owner, u32 type, u32 classid, + size_t *size, bool is_purpose_est) +{ + struct xe_guc_state_capture *gc = guc->capture; + struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid]; + int num_regs; + + if (!gc->reglists) { + xe_gt_warn(guc_to_gt(guc), "No capture reglist for this device\n"); + return -ENODEV; + } + + if (cache->is_valid) { + *size = cache->size; + return cache->status; + } + + if (!is_purpose_est && owner == GUC_CAPTURE_LIST_INDEX_PF && + !guc_capture_get_one_list(gc->reglists, owner, type, classid)) { + if (type == GUC_CAPTURE_LIST_TYPE_GLOBAL) + xe_gt_warn(guc_to_gt(guc), "Missing capture reglist: global!\n"); + else + xe_gt_warn(guc_to_gt(guc), "Missing capture reglist: %s(%u):%s(%u)!\n", + get_item_with_default(capture_list_type_names, type), type, + get_item_with_default(capture_engine_class_names, classid), + classid); + return -ENODEV; + } + + num_regs = guc_cap_list_num_regs(gc, owner, type, classid); + /* intentional empty lists can exist depending on hw config */ + if (!num_regs) + return -ENODATA; + + if (size) + *size = PAGE_ALIGN((sizeof(struct guc_debug_capture_list)) + + (num_regs * sizeof(struct guc_mmio_reg))); + + return 0; +} + +int +xe_guc_capture_getlistsize(struct xe_guc *guc, u32 owner, u32 type, u32 classid, size_t *size) +{ + return guc_capture_getlistsize(guc, owner, type, classid, size, false); +} + +int +xe_guc_capture_getlist(struct xe_guc *guc, u32 owner, u32 type, u32 classid, void **outptr) +{ + struct xe_guc_state_capture *gc = guc->capture; + struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid]; + struct guc_debug_capture_list *listnode; + int ret, num_regs; + u8 *caplist, *tmp; + size_t size = 0; + + if (!gc->reglists) + return -ENODEV; + + if (cache->is_valid) { + *outptr = cache->ptr; + return cache->status; + } + + ret = xe_guc_capture_getlistsize(guc, owner, type, classid, &size); + if (ret) { + cache->is_valid = true; + cache->ptr = NULL; + cache->size = 0; + cache->status = ret; + return ret; + } + + caplist = drmm_kzalloc(guc_to_drm(guc), size, GFP_KERNEL); + if (!caplist) { + xe_gt_dbg(guc_to_gt(guc), "Failed to alloc cached register capture list"); + return -ENOMEM; + } + + /* populate capture list header */ + tmp = caplist; + num_regs = guc_cap_list_num_regs(guc->capture, owner, type, classid); + listnode = (struct guc_debug_capture_list *)tmp; + listnode->header.info = FIELD_PREP(GUC_CAPTURELISTHDR_NUMDESCR, (u32)num_regs); + + /* populate list of register descriptor */ + tmp += sizeof(struct guc_debug_capture_list); + guc_capture_list_init(guc, owner, type, classid, (struct guc_mmio_reg *)tmp, num_regs); + + /* cache this list */ + cache->is_valid = true; + cache->ptr = caplist; + cache->size = size; + cache->status = 0; + + *outptr = caplist; + + return 0; +} + +int +xe_guc_capture_getnullheader(struct xe_guc *guc, void **outptr, size_t *size) +{ + struct xe_guc_state_capture *gc = guc->capture; + int tmp = sizeof(u32) * 4; + void *null_header; + + if (gc->ads_null_cache) { + *outptr = gc->ads_null_cache; + *size = tmp; + return 0; + } + + null_header = drmm_kzalloc(guc_to_drm(guc), tmp, GFP_KERNEL); + if (!null_header) { + xe_gt_dbg(guc_to_gt(guc), "Failed to alloc cached register capture null list"); + return -ENOMEM; + } + + gc->ads_null_cache = null_header; + *outptr = null_header; + *size = tmp; + + return 0; +} + +int xe_guc_capture_init(struct xe_guc *guc) +{ + guc->capture = drmm_kzalloc(guc_to_drm(guc), sizeof(*guc->capture), GFP_KERNEL); + if (!guc->capture) + return -ENOMEM; + + guc->capture->reglists = guc_capture_get_device_reglist(guc); + + return 0; +} diff --git a/drivers/gpu/drm/xe/xe_guc_capture.h b/drivers/gpu/drm/xe/xe_guc_capture.h new file mode 100644 index 000000000000..ba3e0aabee01 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_guc_capture.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2021-2021 Intel Corporation + */ + +#ifndef _XE_GUC_CAPTURE_H +#define _XE_GUC_CAPTURE_H + +#include <linux/types.h> +#include "regs/xe_reg_defs.h" + +struct xe_guc; + +/* + * struct __guc_mmio_reg_descr / struct __guc_mmio_reg_descr_group + * + * xe_guc_capture module uses these structures to maintain static + * tables (per unique platform) that consists of lists of registers + * (offsets, names, flags,...) that are used at the ADS regisration + * time as well as during runtime processing and reporting of error- + * capture states generated by GuC just prior to engine reset events. + */ +struct __guc_mmio_reg_descr { + struct xe_reg reg; + u32 flags; + u32 mask; + const char *regname; +}; + +struct __guc_mmio_reg_descr_group { + const struct __guc_mmio_reg_descr *list; + u32 num_regs; + u32 owner; /* see enum guc_capture_owner */ + u32 type; /* see enum guc_capture_type */ + u32 engine; /* as per MAX_ENGINE_CLASS */ +}; + +int xe_guc_capture_getlist(struct xe_guc *guc, u32 owner, u32 type, u32 classid, void **outptr); +int xe_guc_capture_getlistsize(struct xe_guc *guc, u32 owner, u32 type, u32 classid, size_t *size); +int xe_guc_capture_getnullheader(struct xe_guc *guc, void **outptr, size_t *size); +int xe_guc_capture_init(struct xe_guc *guc); + +#endif /* _XE_GUC_CAPTURE_H */ diff --git a/drivers/gpu/drm/xe/xe_guc_capture_fwif.h b/drivers/gpu/drm/xe/xe_guc_capture_fwif.h new file mode 100644 index 000000000000..1b08388b0b94 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_guc_capture_fwif.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2021-2022 Intel Corporation + */ + +#ifndef _XE_GUC_CAPTURE_FWIF_H +#define _XE_GUC_CAPTURE_FWIF_H + +#include <linux/types.h> + +#include "xe_guc_fwif.h" + +/* + * struct guc_debug_capture_list_header / struct guc_debug_capture_list + * + * As part of ADS registration, these header structures (followed by + * an array of 'struct guc_mmio_reg' entries) are used to register with + * GuC microkernel the list of registers we want it to dump out prior + * to a engine reset. + */ +struct guc_debug_capture_list_header { + u32 info; +#define GUC_CAPTURELISTHDR_NUMDESCR GENMASK(15, 0) +} __packed; + +struct guc_debug_capture_list { + struct guc_debug_capture_list_header header; + struct guc_mmio_reg regs[]; +} __packed; + +/* + * struct guc_state_capture_header_t / struct guc_state_capture_t / + * guc_state_capture_group_header_t / guc_state_capture_group_t + * + * Prior to resetting engines that have hung or faulted, GuC microkernel + * reports the engine error-state (register values that was read) by + * logging them into the shared GuC log buffer using these hierarchy + * of structures. + */ +struct guc_state_capture_header_t { + u32 owner; +#define CAP_HDR_CAPTURE_VFID GENMASK(7, 0) + u32 info; +#define CAP_HDR_CAPTURE_TYPE GENMASK(3, 0) /* see enum guc_capture_type */ +#define CAP_HDR_ENGINE_CLASS GENMASK(7, 4) /* see GUC_MAX_ENGINE_CLASSES */ +#define CAP_HDR_ENGINE_INSTANCE GENMASK(11, 8) + u32 lrca; /* if type-instance, LRCA (address) that hung, else set to ~0 */ + u32 guc_id; /* if type-instance, context index of hung context, else set to ~0 */ + u32 num_mmios; +#define CAP_HDR_NUM_MMIOS GENMASK(9, 0) +} __packed; + +struct guc_state_capture_t { + struct guc_state_capture_header_t header; + struct guc_mmio_reg mmio_entries[]; +} __packed; + +enum guc_capture_group_types { + GUC_STATE_CAPTURE_GROUP_TYPE_FULL, + GUC_STATE_CAPTURE_GROUP_TYPE_PARTIAL, + GUC_STATE_CAPTURE_GROUP_TYPE_MAX, +}; + +struct guc_state_capture_group_header_t { + u32 owner; +#define CAP_GRP_HDR_CAPTURE_VFID GENMASK(7, 0) + u32 info; +#define CAP_GRP_HDR_NUM_CAPTURES GENMASK(7, 0) +#define CAP_GRP_HDR_CAPTURE_TYPE GENMASK(15, 8) /* guc_capture_group_types */ +} __packed; + +/* this is the top level structure where an error-capture dump starts */ +struct guc_state_capture_group_t { + struct guc_state_capture_group_header_t grp_header; + struct guc_state_capture_t capture_entries[]; +} __packed; + +/* + * struct __guc_capture_ads_cache + * + * A structure to cache register lists that were populated and registered + * with GuC at startup during ADS registration. This allows much quicker + * GuC resets without re-parsing all the tables for the given gt. + */ +struct __guc_capture_ads_cache { + bool is_valid; + void *ptr; + size_t size; + int status; +}; + +/** + * struct xe_guc_state_capture + * + * Internal context of the xe_guc_capture module. + */ +struct xe_guc_state_capture { + /** + * @reglists: static table of register lists used for error-capture state. + */ + const struct __guc_mmio_reg_descr_group *reglists; + + /** + * @ads_cache: cached register lists that is ADS format ready + */ + struct __guc_capture_ads_cache ads_cache[GUC_CAPTURE_LIST_INDEX_MAX] + [GUC_CAPTURE_LIST_TYPE_MAX] + [GUC_MAX_ENGINE_CLASSES]; + + /** + * @ads_null_cache: ADS null cache. + */ + void *ads_null_cache; + + /** + * @cachelist: Pool of pre-allocated nodes for error capture output + * + * We need this pool of pre-allocated nodes because we cannot + * dynamically allocate new nodes when receiving the G2H notification + * because the event handlers for all G2H event-processing is called + * by the ct processing worker queue and when that queue is being + * processed, there is no absoluate guarantee that we are not in the + * midst of a GT reset operation (which doesn't allow allocations). + */ + struct list_head cachelist; +#define PREALLOC_NODES_MAX_COUNT (3 * GUC_MAX_ENGINE_CLASSES * GUC_MAX_INSTANCES_PER_CLASS) +#define PREALLOC_NODES_DEFAULT_NUMREGS 64 + + /** + * @max_mmio_per_node: Max MMIO per node. + */ + int max_mmio_per_node; + + /** + * @outlist: Pool of pre-allocated nodes for error capture output + * + * A linked list of parsed GuC error-capture output data before + * reporting with formatting via xe_devcoredump. Each node in this linked list shall + * contain a single engine-capture including global, engine-class and + * engine-instance register dumps as per guc_capture_parsed_output_node + */ + struct list_head outlist; +}; + +#endif /* _XE_GUC_CAPTURE_FWIF_H */ diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h index 19ee71aeaf17..04b03c398191 100644 --- a/drivers/gpu/drm/xe/xe_guc_fwif.h +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h @@ -9,6 +9,7 @@ #include <linux/bits.h> #include "abi/guc_klvs_abi.h" +#include "xe_hw_engine_types.h" #define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 4 #define G2H_LEN_DW_DEREGISTER_CONTEXT 3 @@ -164,8 +165,11 @@ struct guc_mmio_reg { u32 flags; u32 mask; #define GUC_REGSET_MASKED BIT(0) +#define GUC_REGSET_STEERING_NEEDED BIT(1) #define GUC_REGSET_MASKED_WITH_VALUE BIT(2) #define GUC_REGSET_RESTORE_ONLY BIT(3) +#define GUC_REGSET_STEERING_GROUP GENMASK(16, 12) +#define GUC_REGSET_STEERING_INSTANCE GENMASK(23, 20) } __packed; /* GuC register sets */ @@ -194,6 +198,24 @@ enum { GUC_CAPTURE_LIST_INDEX_MAX = 2, }; +/*Register-types of GuC capture register lists */ +enum guc_capture_type { + GUC_CAPTURE_LIST_TYPE_GLOBAL = 0, + GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, + GUC_CAPTURE_LIST_TYPE_MAX, +}; + +/* Class indecies for capture_class and capture_instance arrays */ +enum { + GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE = 0, + GUC_CAPTURE_LIST_CLASS_VIDEO = 1, + GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE = 2, + GUC_CAPTURE_LIST_CLASS_BLITTER = 3, + GUC_CAPTURE_LIST_CLASS_GSC_OTHER = 4, + GUC_CAPTURE_LIST_CLASS_MAX = 5 +}; + /* GuC Additional Data Struct */ struct guc_ads { struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h index 546ac6350a31..6d7d0976b7af 100644 --- a/drivers/gpu/drm/xe/xe_guc_types.h +++ b/drivers/gpu/drm/xe/xe_guc_types.h @@ -58,6 +58,8 @@ struct xe_guc { struct xe_guc_ads ads; /** @ct: GuC ct */ struct xe_guc_ct ct; + /** @capture: the error-state-capture module's data and objects */ + struct xe_guc_state_capture *capture; /** @pc: GuC Power Conservation */ struct xe_guc_pc pc; /** @dbm: GuC Doorbell Manager */ -- 2.34.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v9 1/4] drm/xe/guc: Prepare GuC register list and update ADS size for error capture 2024-06-07 0:07 ` [PATCH v9 1/4] drm/xe/guc: Prepare GuC register list and update ADS size " Zhanjun Dong @ 2024-06-14 11:50 ` Michal Wajdeczko 2024-06-19 19:36 ` Dong, Zhanjun 0 siblings, 1 reply; 24+ messages in thread From: Michal Wajdeczko @ 2024-06-14 11:50 UTC (permalink / raw) To: Zhanjun Dong, intel-xe Hi Zhanjun, please find few late comments below On 07.06.2024 02:07, Zhanjun Dong wrote: > Add referenced registers defines and list of registers. > Update GuC ADS size allocation to include space for > the lists of error state capture register descriptors. > > Then, populate GuC ADS with the lists of registers we want > GuC to report back to host on engine reset events. This list > should include global, engine-class and engine-instance > registers for every engine-class type on the current hardware. > > Ensure we allocate a persistent store for the register lists > that are populated into ADS so that we don't need to allocate > memory during GT resets when GuC is reloaded and ADS population > happens again. > > Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> > --- > drivers/gpu/drm/xe/Makefile | 1 + > drivers/gpu/drm/xe/xe_guc.c | 5 + > drivers/gpu/drm/xe/xe_guc.h | 5 + > drivers/gpu/drm/xe/xe_guc_ads.c | 213 +++++++++++++- > drivers/gpu/drm/xe/xe_guc_ads.h | 3 + > drivers/gpu/drm/xe/xe_guc_ads_types.h | 2 + > drivers/gpu/drm/xe/xe_guc_capture.c | 352 +++++++++++++++++++++++ > drivers/gpu/drm/xe/xe_guc_capture.h | 43 +++ > drivers/gpu/drm/xe/xe_guc_capture_fwif.h | 145 ++++++++++ > drivers/gpu/drm/xe/xe_guc_fwif.h | 22 ++ > drivers/gpu/drm/xe/xe_guc_types.h | 2 + > 11 files changed, 781 insertions(+), 12 deletions(-) > create mode 100644 drivers/gpu/drm/xe/xe_guc_capture.c > create mode 100644 drivers/gpu/drm/xe/xe_guc_capture.h > create mode 100644 drivers/gpu/drm/xe/xe_guc_capture_fwif.h > > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile > index 0c3e3adabb27..2454443fc6a3 100644 > --- a/drivers/gpu/drm/xe/Makefile > +++ b/drivers/gpu/drm/xe/Makefile > @@ -71,6 +71,7 @@ xe-y += xe_bb.o \ > xe_gt_topology.o \ > xe_guc.o \ > xe_guc_ads.o \ > + xe_guc_capture.o \ > xe_guc_ct.o \ > xe_guc_db_mgr.o \ > xe_guc_debugfs.o \ > diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c > index 0bf6e01b8910..6860c92f3547 100644 > --- a/drivers/gpu/drm/xe/xe_guc.c > +++ b/drivers/gpu/drm/xe/xe_guc.c > @@ -22,6 +22,7 @@ > #include "xe_gt_sriov_vf.h" > #include "xe_gt_throttle.h" > #include "xe_guc_ads.h" > +#include "xe_guc_capture.h" > #include "xe_guc_ct.h" > #include "xe_guc_db_mgr.h" > #include "xe_guc_hwconfig.h" > @@ -338,6 +339,10 @@ int xe_guc_init(struct xe_guc *guc) > if (ret) > goto out; > > + ret = xe_guc_capture_init(guc); > + if (ret) > + goto out; > + > ret = xe_guc_ads_init(&guc->ads); > if (ret) > goto out; > diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h > index af59c9545753..ddfa855458ab 100644 > --- a/drivers/gpu/drm/xe/xe_guc.h > +++ b/drivers/gpu/drm/xe/xe_guc.h > @@ -69,4 +69,9 @@ static inline struct xe_device *guc_to_xe(struct xe_guc *guc) > return gt_to_xe(guc_to_gt(guc)); > } > > +static inline struct drm_device *guc_to_drm(struct xe_guc *guc) > +{ > + return &guc_to_xe(guc)->drm; > +} > + > #endif > diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c > index 1c60b685dbc6..7c4ca986db68 100644 > --- a/drivers/gpu/drm/xe/xe_guc_ads.c > +++ b/drivers/gpu/drm/xe/xe_guc_ads.c > @@ -18,6 +18,8 @@ > #include "xe_gt_ccs_mode.h" > #include "xe_gt_printk.h" > #include "xe_guc.h" > +#include "xe_guc_capture.h" > +#include "xe_guc_capture_fwif.h" > #include "xe_guc_ct.h" > #include "xe_hw_engine.h" > #include "xe_lrc.h" > @@ -127,6 +129,8 @@ struct __guc_ads_blob { > #define info_map_read(xe_, map_, field_) \ > xe_map_rd_field(xe_, map_, 0, struct guc_gt_system_info, field_) > > +static int guc_capture_prep_lists(struct xe_guc_ads *ads); > + > static size_t guc_ads_regset_size(struct xe_guc_ads *ads) > { > struct xe_device *xe = ads_to_xe(ads); > @@ -148,8 +152,7 @@ static u32 guc_ads_waklv_size(struct xe_guc_ads *ads) > > static size_t guc_ads_capture_size(struct xe_guc_ads *ads) > { > - /* FIXME: Allocate a proper capture list */ > - return PAGE_ALIGN(PAGE_SIZE); > + return PAGE_ALIGN(ads->capture_size); > } > > static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads) > @@ -388,6 +391,48 @@ static int calculate_waklv_size(struct xe_guc_ads *ads) > return SZ_4K; > } > > +/** > + * xe_guc_capture_ads_input_worst_size - Calculate the worst size for GuC register capture > + * @guc: point to xe_guc structure > + * > + * Calculate the worst size for GuC register capture by including all possible engines classes. > + * > + * Returns: Calculated size > + */ > +int xe_guc_capture_ads_input_worst_size(struct xe_guc *guc) shouldn't this function be located in xe_guc_capture.c ? seems to better fit than xe_guc_ads.c also, since it's returning "size" the maybe it should be of type "size_t" like the local var total_size ? > +{ > + size_t total_size, class_size, instance_size, global_size; > + int i, j; > + > + /* This function calculates the worst case register lists size by > + * including all possible engines classes. It is called during the > + * first of a two-phase GuC (and ADS-population) initialization > + * sequence, that is, during the pre-hwconfig phase before we have > + * the exact engine fusing info. > + */ for multi-line comments there is little different format of the first line: /* * This function calculates the worst case register lists size by * including all possible engines classes. It is called during the ... > + total_size = PAGE_SIZE; /* Pad a page in front for empty lists */ > + for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) { > + for (j = 0; j < GUC_CAPTURE_LIST_CLASS_MAX; j++) { > + if (xe_guc_capture_getlistsize(guc, i, > + GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, > + j, &class_size) < 0) > + class_size = 0; > + if (xe_guc_capture_getlistsize(guc, i, > + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, > + j, &instance_size) < 0) > + instance_size = 0; > + total_size += class_size + instance_size; > + } > + if (xe_guc_capture_getlistsize(guc, i, > + GUC_CAPTURE_LIST_TYPE_GLOBAL, > + 0, &global_size) < 0) > + global_size = 0; > + total_size += global_size; > + } > + > + return PAGE_ALIGN(total_size); > +} > + > #define MAX_GOLDEN_LRC_SIZE (SZ_4K * 64) > > int xe_guc_ads_init(struct xe_guc_ads *ads) > @@ -398,6 +443,10 @@ int xe_guc_ads_init(struct xe_guc_ads *ads) > struct xe_bo *bo; > > ads->golden_lrc_size = calculate_golden_lrc_size(ads); > + /* At time of ads init, hwconfig was not loaded, engine info like engine mask is not ready. > + * Capture size is using the worst size calculation. > + */ comments are usually wrapped at column 80 (just code is allowed to 100) and make it in proper style > + ads->capture_size = xe_guc_capture_ads_input_worst_size(ads_to_guc(ads)); > ads->regset_size = calculate_regset_size(gt); > ads->ads_waklv_size = calculate_waklv_size(ads); > > @@ -431,10 +480,11 @@ int xe_guc_ads_init_post_hwconfig(struct xe_guc_ads *ads) > xe_gt_assert(gt, ads->bo); > > ads->golden_lrc_size = calculate_golden_lrc_size(ads); > + /* Calculate Capture size with worst size */ > + ads->capture_size = xe_guc_capture_ads_input_worst_size(ads_to_guc(ads)); > ads->regset_size = calculate_regset_size(gt); > > - xe_gt_assert(gt, ads->golden_lrc_size + > - (ads->regset_size - prev_regset_size) <= > + xe_gt_assert(gt, ads->golden_lrc_size + (ads->regset_size - prev_regset_size) <= > MAX_GOLDEN_LRC_SIZE); > > return 0; > @@ -530,20 +580,159 @@ static void guc_mapping_table_init(struct xe_gt *gt, > } > } > > -static void guc_capture_list_init(struct xe_guc_ads *ads) > +static u32 guc_get_capture_engine_mask(struct xe_gt *gt, struct iosys_map *info_map, > + u32 capture_class) > { > + struct xe_device *xe = gt_to_xe(gt); > + u32 mask; > + > + switch (capture_class) { > + case GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE: > + mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_RENDER_CLASS]); > + mask |= info_map_read(xe, info_map, engine_enabled_masks[GUC_COMPUTE_CLASS]); > + break; > + case GUC_CAPTURE_LIST_CLASS_VIDEO: > + mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_VIDEO_CLASS]); > + break; > + case GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE: > + mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS]); > + break; > + case GUC_CAPTURE_LIST_CLASS_BLITTER: > + mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_BLITTER_CLASS]); > + break; > + case GUC_CAPTURE_LIST_CLASS_GSC_OTHER: > + mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS]); > + break; > + default: > + mask = 0; > + } > + > + return mask; > +} > + > +static int guc_capture_prep_lists(struct xe_guc_ads *ads) > +{ > + struct xe_guc *guc = ads_to_guc(ads); > + struct xe_gt *gt = ads_to_gt(ads); > + u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0; > + struct iosys_map info_map; > + size_t size = 0; > + void *ptr; > int i, j; > - u32 addr = xe_bo_ggtt_addr(ads->bo) + guc_ads_capture_offset(ads); > > - /* FIXME: Populate a proper capture list */ > + capture_offset = guc_ads_capture_offset(ads); > + ads_ggtt = xe_bo_ggtt_addr(ads->bo); > + info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), > + offsetof(struct __guc_ads_blob, system_info)); > + > + /* first, set aside the first page for a capture_list with zero descriptors */ > + total_size = PAGE_SIZE; > + if (!xe_guc_capture_getnullheader(guc, &ptr, &size)) > + xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, ptr, size); > + > + null_ggtt = ads_ggtt + capture_offset; > + capture_offset += PAGE_SIZE; > + > + /* Populate capture list : at this point adps is already allocated and mapped to worst case > + * size > + */ > for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) { > - for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) { > - ads_blob_write(ads, ads.capture_instance[i][j], addr); > - ads_blob_write(ads, ads.capture_class[i][j], addr); > + bool write_empty_list; > + > + for (j = 0; j < GUC_CAPTURE_LIST_CLASS_MAX; j++) { > + u32 engine_mask = guc_get_capture_engine_mask(gt, &info_map, j); > + /* null list if we dont have said engine or list */ > + if (!engine_mask) { > + ads_blob_write(ads, ads.capture_class[i][j], null_ggtt); > + ads_blob_write(ads, ads.capture_instance[i][j], null_ggtt); > + continue; > + } > + /********************************************************/ > + /*** engine exists: start with engine-class registers ***/ > + /********************************************************/ we usually don't use extensive code decorations like this if function is too long (and in this case it is) then rather try to split it smaller ones > + write_empty_list = true; /* starting assumption is an empty list */ > + size = 0; > + if (!xe_guc_capture_getlistsize(guc, i, > + GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, > + j, &size)) { > + if (total_size + size > ads->capture_size) > + xe_gt_dbg(gt, "Capture size overflow :%zu vs %d\n", > + total_size + size, ads->capture_size); > + else if (!xe_guc_capture_getlist(guc, i, > + GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, > + j, &ptr)) > + /* everything checked out, populate! */ > + write_empty_list = false; > + } > + if (!write_empty_list) { > + ads_blob_write(ads, ads.capture_class[i][j], > + ads_ggtt + capture_offset); > + xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, > + ptr, size); > + total_size += size; > + capture_offset += size; > + } else { > + ads_blob_write(ads, ads.capture_class[i][j], null_ggtt); > + } > + > + /********************************************************/ > + /*** engine exists: next, engine-instance registers ***/ > + /********************************************************/ > + write_empty_list = true; /* starting assumption is an empty list */ > + size = 0; > + if (!xe_guc_capture_getlistsize(guc, i, > + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, > + j, &size)) { > + if (total_size + size > ads->capture_size) > + xe_gt_dbg(gt, "Capture size overflow :%zu vs %d\n", > + total_size + size, ads->capture_size); > + else if (!xe_guc_capture_getlist(guc, i, > + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, > + j, &ptr)) > + /* everything checked out, populate! */ > + write_empty_list = false; > + } > + > + if (!write_empty_list) { > + ads_blob_write(ads, ads.capture_instance[i][j], > + ads_ggtt + capture_offset); > + xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, > + ptr, size); > + total_size += size; > + capture_offset += size; > + } else { > + ads_blob_write(ads, ads.capture_instance[i][j], null_ggtt); > + } > } > > - ads_blob_write(ads, ads.capture_global[i], addr); > + /********************************************************/ > + /*** global registers is last in our PF/VF loops ***/ > + /********************************************************/ > + write_empty_list = true; /* starting assumption is an empty list */ > + size = 0; > + if (!xe_guc_capture_getlistsize(guc, i, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &size)) { > + if (total_size + size > ads->capture_size) > + xe_gt_dbg(gt, "Capture size overflow :%zu vs %d\n", > + total_size + size, ads->capture_size); > + else if (!xe_guc_capture_getlist(guc, i, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, > + &ptr)) > + write_empty_list = false; /* everything checked out, populate! */ > + } > + if (!write_empty_list) { > + ads_blob_write(ads, ads.capture_global[i], ads_ggtt + capture_offset); > + xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, ptr, > + size); > + total_size += size; > + capture_offset += size; > + } else { > + ads_blob_write(ads, ads.capture_global[i], null_ggtt); > + } > } > + > + if (ads->capture_size != PAGE_ALIGN(total_size)) > + xe_gt_info(gt, "ADS capture alloc size changed from %d to %d\n", maybe xe_gt_dbg as it doesn't seem important for an ordinary user > + ads->capture_size, PAGE_ALIGN(total_size)); > + return PAGE_ALIGN(total_size); > } > > static void guc_mmio_regset_write_one(struct xe_guc_ads *ads, > @@ -732,7 +921,7 @@ void xe_guc_ads_populate(struct xe_guc_ads *ads) > guc_mmio_reg_state_init(ads); > guc_prep_golden_lrc_null(ads); > guc_mapping_table_init(gt, &info_map); > - guc_capture_list_init(ads); > + guc_capture_prep_lists(ads); > guc_doorbell_init(ads); > guc_waklv_init(ads); > > diff --git a/drivers/gpu/drm/xe/xe_guc_ads.h b/drivers/gpu/drm/xe/xe_guc_ads.h > index 2e6674c760ff..11b6e3ea3d9f 100644 > --- a/drivers/gpu/drm/xe/xe_guc_ads.h > +++ b/drivers/gpu/drm/xe/xe_guc_ads.h > @@ -8,11 +8,14 @@ > > struct xe_guc_ads; > please keep forward decls together, but > +struct xe_guc; > + > int xe_guc_ads_init(struct xe_guc_ads *ads); > int xe_guc_ads_init_post_hwconfig(struct xe_guc_ads *ads); > void xe_guc_ads_populate(struct xe_guc_ads *ads); > void xe_guc_ads_populate_minimal(struct xe_guc_ads *ads); > void xe_guc_ads_populate_post_load(struct xe_guc_ads *ads); > int xe_guc_ads_scheduler_policy_toggle_reset(struct xe_guc_ads *ads); > +int xe_guc_capture_ads_input_worst_size(struct xe_guc *guc); likely this function should be defined elsewhere (as clearly it does not fit here) > > #endif > diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h > index 2de5decfe0fd..70c132458ac3 100644 > --- a/drivers/gpu/drm/xe/xe_guc_ads_types.h > +++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h > @@ -22,6 +22,8 @@ struct xe_guc_ads { > u32 regset_size; > /** @ads_waklv_size: total waklv size supported by platform */ > u32 ads_waklv_size; > + /** @capture_size: size of register set passed to GuC for capture */ > + u32 capture_size; > }; > > #endif > diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c > new file mode 100644 > index 000000000000..19bd79285061 > --- /dev/null > +++ b/drivers/gpu/drm/xe/xe_guc_capture.c > @@ -0,0 +1,352 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright © 2021-2022 Intel Corporation 2024 ? > + */ > + > +#include <linux/types.h> > + > +#include <drm/drm_managed.h> > +#include <drm/drm_print.h> > + > +#include "abi/guc_actions_abi.h" > +#include "regs/xe_engine_regs.h" > +#include "regs/xe_gt_regs.h" > +#include "regs/xe_guc_regs.h" > +#include "regs/xe_regs.h" > + > +#include "xe_bo.h" > +#include "xe_device.h" > +#include "xe_exec_queue_types.h" > +#include "xe_gt.h" > +#include "xe_gt_mcr.h" > +#include "xe_gt_printk.h" > +#include "xe_guc.h" > +#include "xe_guc_capture.h" > +#include "xe_guc_capture_fwif.h" > +#include "xe_guc_ct.h" > +#include "xe_guc_log.h" > +#include "xe_guc_submit.h" > +#include "xe_hw_engine_types.h" > +#include "xe_macros.h" > +#include "xe_map.h" > + > +/* > + * Define all device tables of GuC error capture register lists > + * NOTE: For engine-registers, GuC only needs the register offsets > + * from the engine-mmio-base > + */ > +#define COMMON_XELP_BASE_GLOBAL \ > + { FORCEWAKE_GT, 0, 0} > + > +#define COMMON_BASE_ENGINE_INSTANCE \ > + { RING_ESR(0), 0, 0}, \ > + { RING_EMR(0), 0, 0}, \ > + { RING_EIR(0), 0, 0}, \ > + { RING_EXECLIST_STATUS_HI(0), 0, 0}, \ > + { RING_EXECLIST_STATUS_LO(0), 0, 0}, \ > + { RING_DMA_FADD(0), 0, 0}, \ > + { RING_DMA_FADD_UDW(0), 0, 0}, \ > + { RING_IPEHR(0), 0, 0}, \ > + { RING_BBADDR(0), 0, 0}, \ > + { RING_BBADDR_UDW(0), 0, 0}, \ > + { RING_ACTHD(0), 0, 0}, \ > + { RING_ACTHD_UDW(0), 0, 0}, \ > + { RING_START(0), 0, 0}, \ > + { RING_HEAD(0), 0, 0}, \ > + { RING_TAIL(0), 0, 0}, \ > + { RING_CTL(0), 0, 0}, \ > + { RING_MI_MODE(0), 0, 0}, \ > + { RING_HWS_PGA(0), 0, 0}, \ > + { RING_MODE(0), 0, 0} > + > +/* XE_LP Global */ > +static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = { > + COMMON_XELP_BASE_GLOBAL, > +}; > + > +/* Render / Compute Per-Engine-Instance */ > +static const struct __guc_mmio_reg_descr xe_rc_inst_regs[] = { > + COMMON_BASE_ENGINE_INSTANCE, > +}; > + > +/* Media Decode/Encode Per-Engine-Instance */ > +static const struct __guc_mmio_reg_descr xe_vd_inst_regs[] = { > + COMMON_BASE_ENGINE_INSTANCE, > +}; > + > +/* Video Enhancement Per-Engine-Instance */ > +static const struct __guc_mmio_reg_descr xe_vec_inst_regs[] = { > + COMMON_BASE_ENGINE_INSTANCE, > +}; > + > +/* Blitter Per-Engine-Instance */ > +static const struct __guc_mmio_reg_descr xe_blt_inst_regs[] = { > + COMMON_BASE_ENGINE_INSTANCE, > +}; > + > +/* XE_LP - GSC Per-Engine-Instance */ > +static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = { > + COMMON_BASE_ENGINE_INSTANCE, > +}; > + > +/* > + * Empty list to prevent warnings about unknown class/instance types > + * as not all class/instanace types have entries on all platforms. > + */ > +static const struct __guc_mmio_reg_descr empty_regs_list[] = { > +}; > + > +#define TO_GCAP_DEF_OWNER(x) (GUC_CAPTURE_LIST_INDEX_##x) > +#define TO_GCAP_DEF_TYPE(x) (GUC_CAPTURE_LIST_TYPE_##x) > +#define MAKE_REGLIST(regslist, regsowner, regstype, class) \ > + { \ > + regslist, \ > + ARRAY_SIZE(regslist), \ > + TO_GCAP_DEF_OWNER(regsowner), \ > + TO_GCAP_DEF_TYPE(regstype), \ > + class, \ GUC_CAPTURE_LIST_CLASS_##class ? > + } > + > +/* List of lists */ > +static const struct __guc_mmio_reg_descr_group xe_lp_lists[] = { > + MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0), > + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE), > + MAKE_REGLIST(xe_rc_inst_regs, PF, ENGINE_INSTANCE, > + GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE), > + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO), > + MAKE_REGLIST(xe_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO), > + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE), > + MAKE_REGLIST(xe_vec_inst_regs, PF, ENGINE_INSTANCE, > + GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE), > + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER), > + MAKE_REGLIST(xe_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER), > + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER), > + MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER), > + {} > +}; > + > +static const char * const capture_list_type_names[] = { > + "Global", > + "Class", > + "Instance", > + "unknown", /* Default name, if out of bound */ do we really need this last item ? maybe just add xe_assert() in the code to make sure it's correct? > +}; > + > +static const char * const capture_engine_class_names[] = { > + "Render/Compute", > + "Video", > + "VideoEnhance", > + "Blitter", > + "GSC-Other", > + "unknown", /* Default name, if out of bound */ ditto > +}; > + > +/* Get item from array by index. > + * The last item is the default value, referenced for index out of bound condition. > + */ > +#define get_item_with_default(ar, index) (ar[(index) >= ARRAY_SIZE(ar) ? ARRAY_SIZE(ar) - 1 : \ > + (index)]) > + > +static const struct __guc_mmio_reg_descr_group * > +guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists, > + u32 owner, u32 type, u32 id) > +{ > + int i; > + > + if (!reglists) > + return NULL; > + > + for (i = 0; reglists[i].list; ++i) { > + if (reglists[i].owner == owner && reglists[i].type == type && > + (reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL)) > + return ®lists[i]; > + } > + > + return NULL; > +} > + > +static const struct __guc_mmio_reg_descr_group * > +guc_capture_get_device_reglist(struct xe_guc *guc) > +{ > + return xe_lp_lists; > +} > + > +static int > +guc_capture_list_init(struct xe_guc *guc, u32 owner, u32 type, u32 classid, > + struct guc_mmio_reg *ptr, u16 num_entries) > +{ > + u32 i = 0; > + const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists; > + const struct __guc_mmio_reg_descr_group *match; > + > + if (!reglists) > + return -ENODEV; > + > + match = guc_capture_get_one_list(reglists, owner, type, classid); > + if (!match) > + return -ENODATA; > + > + for (i = 0; i < num_entries && i < match->num_regs; ++i) { > + ptr[i].offset = match->list[i].reg.addr; > + ptr[i].value = 0xDEADF00D; > + ptr[i].flags = match->list[i].flags; > + ptr[i].mask = match->list[i].mask; > + } > + > + if (i < num_entries) > + xe_gt_dbg(guc_to_gt(guc), "Got short capture reglist init: %d out %d.\n", i, > + num_entries); > + > + return 0; > +} > + > +static int > +guc_cap_list_num_regs(struct xe_guc_state_capture *gc, u32 owner, u32 type, u32 classid) > +{ > + const struct __guc_mmio_reg_descr_group *match; > + > + match = guc_capture_get_one_list(gc->reglists, owner, type, classid); > + if (!match) > + return 0; > + > + return match->num_regs; > +} > + > +static int > +guc_capture_getlistsize(struct xe_guc *guc, u32 owner, u32 type, u32 classid, > + size_t *size, bool is_purpose_est) > +{ > + struct xe_guc_state_capture *gc = guc->capture; > + struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid]; > + int num_regs; > + > + if (!gc->reglists) { > + xe_gt_warn(guc_to_gt(guc), "No capture reglist for this device\n"); > + return -ENODEV; > + } > + > + if (cache->is_valid) { > + *size = cache->size; > + return cache->status; > + } > + > + if (!is_purpose_est && owner == GUC_CAPTURE_LIST_INDEX_PF && > + !guc_capture_get_one_list(gc->reglists, owner, type, classid)) { > + if (type == GUC_CAPTURE_LIST_TYPE_GLOBAL) > + xe_gt_warn(guc_to_gt(guc), "Missing capture reglist: global!\n"); > + else > + xe_gt_warn(guc_to_gt(guc), "Missing capture reglist: %s(%u):%s(%u)!\n", > + get_item_with_default(capture_list_type_names, type), type, > + get_item_with_default(capture_engine_class_names, classid), > + classid); > + return -ENODEV; > + } > + > + num_regs = guc_cap_list_num_regs(gc, owner, type, classid); > + /* intentional empty lists can exist depending on hw config */ > + if (!num_regs) > + return -ENODATA; > + > + if (size) > + *size = PAGE_ALIGN((sizeof(struct guc_debug_capture_list)) + > + (num_regs * sizeof(struct guc_mmio_reg))); > + > + return 0; > +} > + > +int > +xe_guc_capture_getlistsize(struct xe_guc *guc, u32 owner, u32 type, u32 classid, size_t *size) add kernel-doc for all public functions > +{ > + return guc_capture_getlistsize(guc, owner, type, classid, size, false); > +} > + > +int > +xe_guc_capture_getlist(struct xe_guc *guc, u32 owner, u32 type, u32 classid, void **outptr) ditto > +{ > + struct xe_guc_state_capture *gc = guc->capture; > + struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid]; > + struct guc_debug_capture_list *listnode; > + int ret, num_regs; > + u8 *caplist, *tmp; > + size_t size = 0; > + > + if (!gc->reglists) > + return -ENODEV; > + > + if (cache->is_valid) { > + *outptr = cache->ptr; > + return cache->status; > + } > + > + ret = xe_guc_capture_getlistsize(guc, owner, type, classid, &size); > + if (ret) { > + cache->is_valid = true; > + cache->ptr = NULL; > + cache->size = 0; > + cache->status = ret; > + return ret; > + } > + > + caplist = drmm_kzalloc(guc_to_drm(guc), size, GFP_KERNEL); > + if (!caplist) { > + xe_gt_dbg(guc_to_gt(guc), "Failed to alloc cached register capture list"); we usually don't add extra messages for OOM condition as it will be already reported > + return -ENOMEM; > + } > + > + /* populate capture list header */ > + tmp = caplist; > + num_regs = guc_cap_list_num_regs(guc->capture, owner, type, classid); > + listnode = (struct guc_debug_capture_list *)tmp; > + listnode->header.info = FIELD_PREP(GUC_CAPTURELISTHDR_NUMDESCR, (u32)num_regs); > + > + /* populate list of register descriptor */ > + tmp += sizeof(struct guc_debug_capture_list); > + guc_capture_list_init(guc, owner, type, classid, (struct guc_mmio_reg *)tmp, num_regs); > + > + /* cache this list */ > + cache->is_valid = true; > + cache->ptr = caplist; > + cache->size = size; > + cache->status = 0; > + > + *outptr = caplist; > + > + return 0; > +} > + > +int > +xe_guc_capture_getnullheader(struct xe_guc *guc, void **outptr, size_t *size) > +{ > + struct xe_guc_state_capture *gc = guc->capture; > + int tmp = sizeof(u32) * 4; > + void *null_header; > + > + if (gc->ads_null_cache) { > + *outptr = gc->ads_null_cache; > + *size = tmp; > + return 0; > + } > + > + null_header = drmm_kzalloc(guc_to_drm(guc), tmp, GFP_KERNEL); > + if (!null_header) { > + xe_gt_dbg(guc_to_gt(guc), "Failed to alloc cached register capture null list"); > + return -ENOMEM; > + } > + > + gc->ads_null_cache = null_header; > + *outptr = null_header; > + *size = tmp; > + > + return 0; > +} > + > +int xe_guc_capture_init(struct xe_guc *guc) > +{ > + guc->capture = drmm_kzalloc(guc_to_drm(guc), sizeof(*guc->capture), GFP_KERNEL); > + if (!guc->capture) > + return -ENOMEM; > + > + guc->capture->reglists = guc_capture_get_device_reglist(guc); > + > + return 0; > +} > diff --git a/drivers/gpu/drm/xe/xe_guc_capture.h b/drivers/gpu/drm/xe/xe_guc_capture.h > new file mode 100644 > index 000000000000..ba3e0aabee01 > --- /dev/null > +++ b/drivers/gpu/drm/xe/xe_guc_capture.h > @@ -0,0 +1,43 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2021-2021 Intel Corporation 2024 > + */ > + > +#ifndef _XE_GUC_CAPTURE_H > +#define _XE_GUC_CAPTURE_H > + > +#include <linux/types.h> > +#include "regs/xe_reg_defs.h" > + > +struct xe_guc; > + > +/* > + * struct __guc_mmio_reg_descr / struct __guc_mmio_reg_descr_group > + * > + * xe_guc_capture module uses these structures to maintain static > + * tables (per unique platform) that consists of lists of registers > + * (offsets, names, flags,...) that are used at the ADS regisration > + * time as well as during runtime processing and reporting of error- > + * capture states generated by GuC just prior to engine reset events. > + */ > +struct __guc_mmio_reg_descr { > + struct xe_reg reg; > + u32 flags; > + u32 mask; > + const char *regname; > +}; > + > +struct __guc_mmio_reg_descr_group { > + const struct __guc_mmio_reg_descr *list; > + u32 num_regs; > + u32 owner; /* see enum guc_capture_owner */ > + u32 type; /* see enum guc_capture_type */ > + u32 engine; /* as per MAX_ENGINE_CLASS */ > +}; > + > +int xe_guc_capture_getlist(struct xe_guc *guc, u32 owner, u32 type, u32 classid, void **outptr); > +int xe_guc_capture_getlistsize(struct xe_guc *guc, u32 owner, u32 type, u32 classid, size_t *size); > +int xe_guc_capture_getnullheader(struct xe_guc *guc, void **outptr, size_t *size); > +int xe_guc_capture_init(struct xe_guc *guc); > + > +#endif /* _XE_GUC_CAPTURE_H */ > diff --git a/drivers/gpu/drm/xe/xe_guc_capture_fwif.h b/drivers/gpu/drm/xe/xe_guc_capture_fwif.h > new file mode 100644 > index 000000000000..1b08388b0b94 > --- /dev/null > +++ b/drivers/gpu/drm/xe/xe_guc_capture_fwif.h > @@ -0,0 +1,145 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2021-2022 Intel Corporation 2024 > + */ > + > +#ifndef _XE_GUC_CAPTURE_FWIF_H > +#define _XE_GUC_CAPTURE_FWIF_H > + > +#include <linux/types.h> > + > +#include "xe_guc_fwif.h" > + > +/* > + * struct guc_debug_capture_list_header / struct guc_debug_capture_list > + * > + * As part of ADS registration, these header structures (followed by > + * an array of 'struct guc_mmio_reg' entries) are used to register with > + * GuC microkernel the list of registers we want it to dump out prior > + * to a engine reset. > + */ > +struct guc_debug_capture_list_header { > + u32 info; > +#define GUC_CAPTURELISTHDR_NUMDESCR GENMASK(15, 0) > +} __packed; > + > +struct guc_debug_capture_list { > + struct guc_debug_capture_list_header header; > + struct guc_mmio_reg regs[]; > +} __packed; > + > +/* > + * struct guc_state_capture_header_t / struct guc_state_capture_t / > + * guc_state_capture_group_header_t / guc_state_capture_group_t > + * > + * Prior to resetting engines that have hung or faulted, GuC microkernel > + * reports the engine error-state (register values that was read) by > + * logging them into the shared GuC log buffer using these hierarchy > + * of structures. > + */ > +struct guc_state_capture_header_t { > + u32 owner; > +#define CAP_HDR_CAPTURE_VFID GENMASK(7, 0) > + u32 info; > +#define CAP_HDR_CAPTURE_TYPE GENMASK(3, 0) /* see enum guc_capture_type */ > +#define CAP_HDR_ENGINE_CLASS GENMASK(7, 4) /* see GUC_MAX_ENGINE_CLASSES */ > +#define CAP_HDR_ENGINE_INSTANCE GENMASK(11, 8) > + u32 lrca; /* if type-instance, LRCA (address) that hung, else set to ~0 */ > + u32 guc_id; /* if type-instance, context index of hung context, else set to ~0 */ > + u32 num_mmios; > +#define CAP_HDR_NUM_MMIOS GENMASK(9, 0) > +} __packed; > + > +struct guc_state_capture_t { > + struct guc_state_capture_header_t header; > + struct guc_mmio_reg mmio_entries[]; > +} __packed; > + > +enum guc_capture_group_types { > + GUC_STATE_CAPTURE_GROUP_TYPE_FULL, > + GUC_STATE_CAPTURE_GROUP_TYPE_PARTIAL, > + GUC_STATE_CAPTURE_GROUP_TYPE_MAX, > +}; > + > +struct guc_state_capture_group_header_t { > + u32 owner; > +#define CAP_GRP_HDR_CAPTURE_VFID GENMASK(7, 0) > + u32 info; > +#define CAP_GRP_HDR_NUM_CAPTURES GENMASK(7, 0) > +#define CAP_GRP_HDR_CAPTURE_TYPE GENMASK(15, 8) /* guc_capture_group_types */ > +} __packed; > + > +/* this is the top level structure where an error-capture dump starts */ > +struct guc_state_capture_group_t { > + struct guc_state_capture_group_header_t grp_header; > + struct guc_state_capture_t capture_entries[]; > +} __packed; all above definitions looks like pure GuC ABI and for that we have dedicated folder xe/abi where we keep such defs ------- and all below definitions looks like Xe driver specific related to xe_guc_capture so by convention they should be placed in xe_guc_capture_types.h file > + > +/* > + * struct __guc_capture_ads_cache > + * > + * A structure to cache register lists that were populated and registered > + * with GuC at startup during ADS registration. This allows much quicker > + * GuC resets without re-parsing all the tables for the given gt. > + */ > +struct __guc_capture_ads_cache { > + bool is_valid; > + void *ptr; > + size_t size; > + int status; > +}; > + > +/** > + * struct xe_guc_state_capture > + * > + * Internal context of the xe_guc_capture module. > + */ > +struct xe_guc_state_capture { > + /** > + * @reglists: static table of register lists used for error-capture state. > + */ > + const struct __guc_mmio_reg_descr_group *reglists; > + > + /** > + * @ads_cache: cached register lists that is ADS format ready > + */ > + struct __guc_capture_ads_cache ads_cache[GUC_CAPTURE_LIST_INDEX_MAX] > + [GUC_CAPTURE_LIST_TYPE_MAX] > + [GUC_MAX_ENGINE_CLASSES]; > + > + /** > + * @ads_null_cache: ADS null cache. > + */ > + void *ads_null_cache; > + > + /** > + * @cachelist: Pool of pre-allocated nodes for error capture output > + * > + * We need this pool of pre-allocated nodes because we cannot > + * dynamically allocate new nodes when receiving the G2H notification > + * because the event handlers for all G2H event-processing is called > + * by the ct processing worker queue and when that queue is being > + * processed, there is no absoluate guarantee that we are not in the > + * midst of a GT reset operation (which doesn't allow allocations). > + */ > + struct list_head cachelist; > +#define PREALLOC_NODES_MAX_COUNT (3 * GUC_MAX_ENGINE_CLASSES * GUC_MAX_INSTANCES_PER_CLASS) > +#define PREALLOC_NODES_DEFAULT_NUMREGS 64 > + > + /** > + * @max_mmio_per_node: Max MMIO per node. > + */ > + int max_mmio_per_node; > + > + /** > + * @outlist: Pool of pre-allocated nodes for error capture output > + * > + * A linked list of parsed GuC error-capture output data before > + * reporting with formatting via xe_devcoredump. Each node in this linked list shall > + * contain a single engine-capture including global, engine-class and > + * engine-instance register dumps as per guc_capture_parsed_output_node > + */ > + struct list_head outlist; > +}; > + > +#endif /* _XE_GUC_CAPTURE_FWIF_H */ > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h > index 19ee71aeaf17..04b03c398191 100644 > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h > @@ -9,6 +9,7 @@ > #include <linux/bits.h> > > #include "abi/guc_klvs_abi.h" > +#include "xe_hw_engine_types.h" > > #define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 4 > #define G2H_LEN_DW_DEREGISTER_CONTEXT 3 > @@ -164,8 +165,11 @@ struct guc_mmio_reg { > u32 flags; > u32 mask; > #define GUC_REGSET_MASKED BIT(0) > +#define GUC_REGSET_STEERING_NEEDED BIT(1) > #define GUC_REGSET_MASKED_WITH_VALUE BIT(2) > #define GUC_REGSET_RESTORE_ONLY BIT(3) > +#define GUC_REGSET_STEERING_GROUP GENMASK(16, 12) > +#define GUC_REGSET_STEERING_INSTANCE GENMASK(23, 20) > } __packed; > > /* GuC register sets */ > @@ -194,6 +198,24 @@ enum { > GUC_CAPTURE_LIST_INDEX_MAX = 2, > }; > > +/*Register-types of GuC capture register lists */ > +enum guc_capture_type { > + GUC_CAPTURE_LIST_TYPE_GLOBAL = 0, > + GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, > + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, > + GUC_CAPTURE_LIST_TYPE_MAX, > +}; > + > +/* Class indecies for capture_class and capture_instance arrays */ > +enum { > + GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE = 0, > + GUC_CAPTURE_LIST_CLASS_VIDEO = 1, > + GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE = 2, > + GUC_CAPTURE_LIST_CLASS_BLITTER = 3, > + GUC_CAPTURE_LIST_CLASS_GSC_OTHER = 4, > + GUC_CAPTURE_LIST_CLASS_MAX = 5 > +}; > + > /* GuC Additional Data Struct */ > struct guc_ads { > struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; > diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h > index 546ac6350a31..6d7d0976b7af 100644 > --- a/drivers/gpu/drm/xe/xe_guc_types.h > +++ b/drivers/gpu/drm/xe/xe_guc_types.h > @@ -58,6 +58,8 @@ struct xe_guc { > struct xe_guc_ads ads; > /** @ct: GuC ct */ > struct xe_guc_ct ct; > + /** @capture: the error-state-capture module's data and objects */ > + struct xe_guc_state_capture *capture; > /** @pc: GuC Power Conservation */ > struct xe_guc_pc pc; > /** @dbm: GuC Doorbell Manager */ ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v9 1/4] drm/xe/guc: Prepare GuC register list and update ADS size for error capture 2024-06-14 11:50 ` Michal Wajdeczko @ 2024-06-19 19:36 ` Dong, Zhanjun 0 siblings, 0 replies; 24+ messages in thread From: Dong, Zhanjun @ 2024-06-19 19:36 UTC (permalink / raw) To: Michal Wajdeczko, intel-xe Please see my comments inline below. Zhanjun On 2024-06-14 7:50 a.m., Michal Wajdeczko wrote: ... >> @@ -388,6 +391,48 @@ static int calculate_waklv_size(struct xe_guc_ads *ads) >> return SZ_4K; >> } >> >> +/** >> + * xe_guc_capture_ads_input_worst_size - Calculate the worst size for GuC register capture >> + * @guc: point to xe_guc structure >> + * >> + * Calculate the worst size for GuC register capture by including all possible engines classes. >> + * >> + * Returns: Calculated size >> + */ >> +int xe_guc_capture_ads_input_worst_size(struct xe_guc *guc) > > shouldn't this function be located in xe_guc_capture.c ? > seems to better fit than xe_guc_ads.c > > also, since it's returning "size" the maybe it should be of type > "size_t" like the local var total_size ? > Will be changed as advised >> +{ >> + size_t total_size, class_size, instance_size, global_size; >> + int i, j; >> + >> + /* This function calculates the worst case register lists size by >> + * including all possible engines classes. It is called during the >> + * first of a two-phase GuC (and ADS-population) initialization >> + * sequence, that is, during the pre-hwconfig phase before we have >> + * the exact engine fusing info. >> + */ > > for multi-line comments there is little different format of the first line: > > /* > * This function calculates the worst case register lists size by > * including all possible engines classes. It is called during the > ... > >> + total_size = PAGE_SIZE; /* Pad a page in front for empty lists */ >> + for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) { >> + for (j = 0; j < GUC_CAPTURE_LIST_CLASS_MAX; j++) { >> + if (xe_guc_capture_getlistsize(guc, i, >> + GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, >> + j, &class_size) < 0) >> + class_size = 0; >> + if (xe_guc_capture_getlistsize(guc, i, >> + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, >> + j, &instance_size) < 0) >> + instance_size = 0; >> + total_size += class_size + instance_size; >> + } >> + if (xe_guc_capture_getlistsize(guc, i, >> + GUC_CAPTURE_LIST_TYPE_GLOBAL, >> + 0, &global_size) < 0) >> + global_size = 0; >> + total_size += global_size; >> + } >> + >> + return PAGE_ALIGN(total_size); >> +} >> + >> #define MAX_GOLDEN_LRC_SIZE (SZ_4K * 64) >> >> int xe_guc_ads_init(struct xe_guc_ads *ads) >> @@ -398,6 +443,10 @@ int xe_guc_ads_init(struct xe_guc_ads *ads) >> struct xe_bo *bo; >> >> ads->golden_lrc_size = calculate_golden_lrc_size(ads); >> + /* At time of ads init, hwconfig was not loaded, engine info like engine mask is not ready. >> + * Capture size is using the worst size calculation. >> + */ > > comments are usually wrapped at column 80 (just code is allowed to 100) > and make it in proper style > >> + ads->capture_size = xe_guc_capture_ads_input_worst_size(ads_to_guc(ads)); >> ads->regset_size = calculate_regset_size(gt); >> ads->ads_waklv_size = calculate_waklv_size(ads); >> >> @@ -431,10 +480,11 @@ int xe_guc_ads_init_post_hwconfig(struct xe_guc_ads *ads) >> xe_gt_assert(gt, ads->bo); >> >> ads->golden_lrc_size = calculate_golden_lrc_size(ads); >> + /* Calculate Capture size with worst size */ >> + ads->capture_size = xe_guc_capture_ads_input_worst_size(ads_to_guc(ads)); >> ads->regset_size = calculate_regset_size(gt); >> >> - xe_gt_assert(gt, ads->golden_lrc_size + >> - (ads->regset_size - prev_regset_size) <= >> + xe_gt_assert(gt, ads->golden_lrc_size + (ads->regset_size - prev_regset_size) <= >> MAX_GOLDEN_LRC_SIZE); >> >> return 0; >> @@ -530,20 +580,159 @@ static void guc_mapping_table_init(struct xe_gt *gt, >> } >> } >> >> -static void guc_capture_list_init(struct xe_guc_ads *ads) >> +static u32 guc_get_capture_engine_mask(struct xe_gt *gt, struct iosys_map *info_map, >> + u32 capture_class) >> { >> + struct xe_device *xe = gt_to_xe(gt); >> + u32 mask; >> + >> + switch (capture_class) { >> + case GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE: >> + mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_RENDER_CLASS]); >> + mask |= info_map_read(xe, info_map, engine_enabled_masks[GUC_COMPUTE_CLASS]); >> + break; >> + case GUC_CAPTURE_LIST_CLASS_VIDEO: >> + mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_VIDEO_CLASS]); >> + break; >> + case GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE: >> + mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS]); >> + break; >> + case GUC_CAPTURE_LIST_CLASS_BLITTER: >> + mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_BLITTER_CLASS]); >> + break; >> + case GUC_CAPTURE_LIST_CLASS_GSC_OTHER: >> + mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS]); >> + break; >> + default: >> + mask = 0; >> + } >> + >> + return mask; >> +} >> + >> +static int guc_capture_prep_lists(struct xe_guc_ads *ads) >> +{ >> + struct xe_guc *guc = ads_to_guc(ads); >> + struct xe_gt *gt = ads_to_gt(ads); >> + u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0; >> + struct iosys_map info_map; >> + size_t size = 0; >> + void *ptr; >> int i, j; >> - u32 addr = xe_bo_ggtt_addr(ads->bo) + guc_ads_capture_offset(ads); >> >> - /* FIXME: Populate a proper capture list */ >> + capture_offset = guc_ads_capture_offset(ads); >> + ads_ggtt = xe_bo_ggtt_addr(ads->bo); >> + info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), >> + offsetof(struct __guc_ads_blob, system_info)); >> + >> + /* first, set aside the first page for a capture_list with zero descriptors */ >> + total_size = PAGE_SIZE; >> + if (!xe_guc_capture_getnullheader(guc, &ptr, &size)) >> + xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, ptr, size); >> + >> + null_ggtt = ads_ggtt + capture_offset; >> + capture_offset += PAGE_SIZE; >> + >> + /* Populate capture list : at this point adps is already allocated and mapped to worst case >> + * size >> + */ >> for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) { >> - for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) { >> - ads_blob_write(ads, ads.capture_instance[i][j], addr); >> - ads_blob_write(ads, ads.capture_class[i][j], addr); >> + bool write_empty_list; >> + >> + for (j = 0; j < GUC_CAPTURE_LIST_CLASS_MAX; j++) { >> + u32 engine_mask = guc_get_capture_engine_mask(gt, &info_map, j); >> + /* null list if we dont have said engine or list */ >> + if (!engine_mask) { >> + ads_blob_write(ads, ads.capture_class[i][j], null_ggtt); >> + ads_blob_write(ads, ads.capture_instance[i][j], null_ggtt); >> + continue; >> + } >> + /********************************************************/ >> + /*** engine exists: start with engine-class registers ***/ >> + /********************************************************/ > > we usually don't use extensive code decorations like this > > if function is too long (and in this case it is) then rather try to > split it smaller ones will split it > >> + write_empty_list = true; /* starting assumption is an empty list */ >> + size = 0; >> + if (!xe_guc_capture_getlistsize(guc, i, >> + GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, >> + j, &size)) { >> + if (total_size + size > ads->capture_size) >> + xe_gt_dbg(gt, "Capture size overflow :%zu vs %d\n", >> + total_size + size, ads->capture_size); >> + else if (!xe_guc_capture_getlist(guc, i, >> + GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, >> + j, &ptr)) >> + /* everything checked out, populate! */ >> + write_empty_list = false; >> + } >> + if (!write_empty_list) { >> + ads_blob_write(ads, ads.capture_class[i][j], >> + ads_ggtt + capture_offset); >> + xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, >> + ptr, size); >> + total_size += size; >> + capture_offset += size; >> + } else { >> + ads_blob_write(ads, ads.capture_class[i][j], null_ggtt); >> + } >> + >> + /********************************************************/ >> + /*** engine exists: next, engine-instance registers ***/ >> + /********************************************************/ >> + write_empty_list = true; /* starting assumption is an empty list */ >> + size = 0; >> + if (!xe_guc_capture_getlistsize(guc, i, >> + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, >> + j, &size)) { >> + if (total_size + size > ads->capture_size) >> + xe_gt_dbg(gt, "Capture size overflow :%zu vs %d\n", >> + total_size + size, ads->capture_size); >> + else if (!xe_guc_capture_getlist(guc, i, >> + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, >> + j, &ptr)) >> + /* everything checked out, populate! */ >> + write_empty_list = false; >> + } >> + >> + if (!write_empty_list) { >> + ads_blob_write(ads, ads.capture_instance[i][j], >> + ads_ggtt + capture_offset); >> + xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, >> + ptr, size); >> + total_size += size; >> + capture_offset += size; >> + } else { >> + ads_blob_write(ads, ads.capture_instance[i][j], null_ggtt); >> + } >> } >> >> - ads_blob_write(ads, ads.capture_global[i], addr); >> + /********************************************************/ >> + /*** global registers is last in our PF/VF loops ***/ >> + /********************************************************/ >> + write_empty_list = true; /* starting assumption is an empty list */ >> + size = 0; >> + if (!xe_guc_capture_getlistsize(guc, i, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &size)) { >> + if (total_size + size > ads->capture_size) >> + xe_gt_dbg(gt, "Capture size overflow :%zu vs %d\n", >> + total_size + size, ads->capture_size); >> + else if (!xe_guc_capture_getlist(guc, i, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, >> + &ptr)) >> + write_empty_list = false; /* everything checked out, populate! */ >> + } >> + if (!write_empty_list) { >> + ads_blob_write(ads, ads.capture_global[i], ads_ggtt + capture_offset); >> + xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, ptr, >> + size); >> + total_size += size; >> + capture_offset += size; >> + } else { >> + ads_blob_write(ads, ads.capture_global[i], null_ggtt); >> + } >> } >> + >> + if (ads->capture_size != PAGE_ALIGN(total_size)) >> + xe_gt_info(gt, "ADS capture alloc size changed from %d to %d\n", > > maybe xe_gt_dbg as it doesn't seem important for an ordinary user Will do that way > >> + ads->capture_size, PAGE_ALIGN(total_size)); >> + return PAGE_ALIGN(total_size); >> } >> >> static void guc_mmio_regset_write_one(struct xe_guc_ads *ads, >> @@ -732,7 +921,7 @@ void xe_guc_ads_populate(struct xe_guc_ads *ads) >> guc_mmio_reg_state_init(ads); >> guc_prep_golden_lrc_null(ads); >> guc_mapping_table_init(gt, &info_map); >> - guc_capture_list_init(ads); >> + guc_capture_prep_lists(ads); >> guc_doorbell_init(ads); >> guc_waklv_init(ads); >> >> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.h b/drivers/gpu/drm/xe/xe_guc_ads.h >> index 2e6674c760ff..11b6e3ea3d9f 100644 >> --- a/drivers/gpu/drm/xe/xe_guc_ads.h >> +++ b/drivers/gpu/drm/xe/xe_guc_ads.h >> @@ -8,11 +8,14 @@ >> >> struct xe_guc_ads; >> > > please keep forward decls together, but > >> +struct xe_guc; >> + >> int xe_guc_ads_init(struct xe_guc_ads *ads); >> int xe_guc_ads_init_post_hwconfig(struct xe_guc_ads *ads); >> void xe_guc_ads_populate(struct xe_guc_ads *ads); >> void xe_guc_ads_populate_minimal(struct xe_guc_ads *ads); >> void xe_guc_ads_populate_post_load(struct xe_guc_ads *ads); >> int xe_guc_ads_scheduler_policy_toggle_reset(struct xe_guc_ads *ads); >> +int xe_guc_capture_ads_input_worst_size(struct xe_guc *guc); > > likely this function should be defined elsewhere (as clearly it does not > fit here) Sure, will do > >> >> #endif >> diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h >> index 2de5decfe0fd..70c132458ac3 100644 >> --- a/drivers/gpu/drm/xe/xe_guc_ads_types.h >> +++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h >> @@ -22,6 +22,8 @@ struct xe_guc_ads { >> u32 regset_size; >> /** @ads_waklv_size: total waklv size supported by platform */ >> u32 ads_waklv_size; >> + /** @capture_size: size of register set passed to GuC for capture */ >> + u32 capture_size; >> }; >> >> #endif >> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c >> new file mode 100644 >> index 000000000000..19bd79285061 >> --- /dev/null >> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c >> @@ -0,0 +1,352 @@ >> +// SPDX-License-Identifier: MIT >> +/* >> + * Copyright © 2021-2022 Intel Corporation > > 2024 ? > >> + */ >> + >> +#include <linux/types.h> >> + >> +#include <drm/drm_managed.h> >> +#include <drm/drm_print.h> >> + >> +#include "abi/guc_actions_abi.h" >> +#include "regs/xe_engine_regs.h" >> +#include "regs/xe_gt_regs.h" >> +#include "regs/xe_guc_regs.h" >> +#include "regs/xe_regs.h" >> + >> +#include "xe_bo.h" >> +#include "xe_device.h" >> +#include "xe_exec_queue_types.h" >> +#include "xe_gt.h" >> +#include "xe_gt_mcr.h" >> +#include "xe_gt_printk.h" >> +#include "xe_guc.h" >> +#include "xe_guc_capture.h" >> +#include "xe_guc_capture_fwif.h" >> +#include "xe_guc_ct.h" >> +#include "xe_guc_log.h" >> +#include "xe_guc_submit.h" >> +#include "xe_hw_engine_types.h" >> +#include "xe_macros.h" >> +#include "xe_map.h" >> + >> +/* >> + * Define all device tables of GuC error capture register lists >> + * NOTE: For engine-registers, GuC only needs the register offsets >> + * from the engine-mmio-base >> + */ >> +#define COMMON_XELP_BASE_GLOBAL \ >> + { FORCEWAKE_GT, 0, 0} >> + >> +#define COMMON_BASE_ENGINE_INSTANCE \ >> + { RING_ESR(0), 0, 0}, \ >> + { RING_EMR(0), 0, 0}, \ >> + { RING_EIR(0), 0, 0}, \ >> + { RING_EXECLIST_STATUS_HI(0), 0, 0}, \ >> + { RING_EXECLIST_STATUS_LO(0), 0, 0}, \ >> + { RING_DMA_FADD(0), 0, 0}, \ >> + { RING_DMA_FADD_UDW(0), 0, 0}, \ >> + { RING_IPEHR(0), 0, 0}, \ >> + { RING_BBADDR(0), 0, 0}, \ >> + { RING_BBADDR_UDW(0), 0, 0}, \ >> + { RING_ACTHD(0), 0, 0}, \ >> + { RING_ACTHD_UDW(0), 0, 0}, \ >> + { RING_START(0), 0, 0}, \ >> + { RING_HEAD(0), 0, 0}, \ >> + { RING_TAIL(0), 0, 0}, \ >> + { RING_CTL(0), 0, 0}, \ >> + { RING_MI_MODE(0), 0, 0}, \ >> + { RING_HWS_PGA(0), 0, 0}, \ >> + { RING_MODE(0), 0, 0} >> + >> +/* XE_LP Global */ >> +static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = { >> + COMMON_XELP_BASE_GLOBAL, >> +}; >> + >> +/* Render / Compute Per-Engine-Instance */ >> +static const struct __guc_mmio_reg_descr xe_rc_inst_regs[] = { >> + COMMON_BASE_ENGINE_INSTANCE, >> +}; >> + >> +/* Media Decode/Encode Per-Engine-Instance */ >> +static const struct __guc_mmio_reg_descr xe_vd_inst_regs[] = { >> + COMMON_BASE_ENGINE_INSTANCE, >> +}; >> + >> +/* Video Enhancement Per-Engine-Instance */ >> +static const struct __guc_mmio_reg_descr xe_vec_inst_regs[] = { >> + COMMON_BASE_ENGINE_INSTANCE, >> +}; >> + >> +/* Blitter Per-Engine-Instance */ >> +static const struct __guc_mmio_reg_descr xe_blt_inst_regs[] = { >> + COMMON_BASE_ENGINE_INSTANCE, >> +}; >> + >> +/* XE_LP - GSC Per-Engine-Instance */ >> +static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = { >> + COMMON_BASE_ENGINE_INSTANCE, >> +}; >> + >> +/* >> + * Empty list to prevent warnings about unknown class/instance types >> + * as not all class/instanace types have entries on all platforms. >> + */ >> +static const struct __guc_mmio_reg_descr empty_regs_list[] = { >> +}; >> + >> +#define TO_GCAP_DEF_OWNER(x) (GUC_CAPTURE_LIST_INDEX_##x) >> +#define TO_GCAP_DEF_TYPE(x) (GUC_CAPTURE_LIST_TYPE_##x) >> +#define MAKE_REGLIST(regslist, regsowner, regstype, class) \ >> + { \ >> + regslist, \ >> + ARRAY_SIZE(regslist), \ >> + TO_GCAP_DEF_OWNER(regsowner), \ >> + TO_GCAP_DEF_TYPE(regstype), \ >> + class, \ > > GUC_CAPTURE_LIST_CLASS_##class ? The class here is for GUC_CAPTURE_LIST_CLASS_xxx. The MAKE_REGLIST macro was used for all of list types, the above list class is for engine class/instance type, but for glbal type, as it has no associated engine class, so helper macro is not used here like other 2 (TO_GCAP_DEF_TYPE/TO_GCAP_DEF_OWNER). This is by purpose. > >> + } >> + >> +/* List of lists */ >> +static const struct __guc_mmio_reg_descr_group xe_lp_lists[] = { >> + MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0), >> + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE), >> + MAKE_REGLIST(xe_rc_inst_regs, PF, ENGINE_INSTANCE, >> + GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE), >> + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO), >> + MAKE_REGLIST(xe_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO), >> + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE), >> + MAKE_REGLIST(xe_vec_inst_regs, PF, ENGINE_INSTANCE, >> + GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE), >> + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER), >> + MAKE_REGLIST(xe_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER), >> + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER), >> + MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER), >> + {} >> +}; >> + >> +static const char * const capture_list_type_names[] = { >> + "Global", >> + "Class", >> + "Instance", >> + "unknown", /* Default name, if out of bound */ > > do we really need this last item ? > maybe just add xe_assert() in the code to make sure it's correct? > >> +}; >> + >> +static const char * const capture_engine_class_names[] = { >> + "Render/Compute", >> + "Video", >> + "VideoEnhance", >> + "Blitter", >> + "GSC-Other", >> + "unknown", /* Default name, if out of bound */ > > ditto > >> +}; >> + >> +/* Get item from array by index. >> + * The last item is the default value, referenced for index out of bound condition. >> + */ >> +#define get_item_with_default(ar, index) (ar[(index) >= ARRAY_SIZE(ar) ? ARRAY_SIZE(ar) - 1 : \ >> + (index)]) Emm, with the xe_assert in code, the above "Default name" could be removed, and this macro is no longer needed as well. >> + >> +static const struct __guc_mmio_reg_descr_group * >> +guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists, >> + u32 owner, u32 type, u32 id) >> +{ >> + int i; >> + >> + if (!reglists) >> + return NULL; >> + >> + for (i = 0; reglists[i].list; ++i) { >> + if (reglists[i].owner == owner && reglists[i].type == type && >> + (reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL)) >> + return ®lists[i]; >> + } >> + >> + return NULL; >> +} >> + >> +static const struct __guc_mmio_reg_descr_group * >> +guc_capture_get_device_reglist(struct xe_guc *guc) >> +{ >> + return xe_lp_lists; >> +} >> + >> +static int >> +guc_capture_list_init(struct xe_guc *guc, u32 owner, u32 type, u32 classid, >> + struct guc_mmio_reg *ptr, u16 num_entries) >> +{ >> + u32 i = 0; >> + const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists; >> + const struct __guc_mmio_reg_descr_group *match; >> + >> + if (!reglists) >> + return -ENODEV; >> + >> + match = guc_capture_get_one_list(reglists, owner, type, classid); >> + if (!match) >> + return -ENODATA; >> + >> + for (i = 0; i < num_entries && i < match->num_regs; ++i) { >> + ptr[i].offset = match->list[i].reg.addr; >> + ptr[i].value = 0xDEADF00D; >> + ptr[i].flags = match->list[i].flags; >> + ptr[i].mask = match->list[i].mask; >> + } >> + >> + if (i < num_entries) >> + xe_gt_dbg(guc_to_gt(guc), "Got short capture reglist init: %d out %d.\n", i, >> + num_entries); >> + >> + return 0; >> +} >> + >> +static int >> +guc_cap_list_num_regs(struct xe_guc_state_capture *gc, u32 owner, u32 type, u32 classid) >> +{ >> + const struct __guc_mmio_reg_descr_group *match; >> + >> + match = guc_capture_get_one_list(gc->reglists, owner, type, classid); >> + if (!match) >> + return 0; >> + >> + return match->num_regs; >> +} >> + >> +static int >> +guc_capture_getlistsize(struct xe_guc *guc, u32 owner, u32 type, u32 classid, >> + size_t *size, bool is_purpose_est) >> +{ >> + struct xe_guc_state_capture *gc = guc->capture; >> + struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid]; >> + int num_regs; >> + >> + if (!gc->reglists) { >> + xe_gt_warn(guc_to_gt(guc), "No capture reglist for this device\n"); >> + return -ENODEV; >> + } >> + >> + if (cache->is_valid) { >> + *size = cache->size; >> + return cache->status; >> + } >> + >> + if (!is_purpose_est && owner == GUC_CAPTURE_LIST_INDEX_PF && >> + !guc_capture_get_one_list(gc->reglists, owner, type, classid)) { >> + if (type == GUC_CAPTURE_LIST_TYPE_GLOBAL) >> + xe_gt_warn(guc_to_gt(guc), "Missing capture reglist: global!\n"); >> + else >> + xe_gt_warn(guc_to_gt(guc), "Missing capture reglist: %s(%u):%s(%u)!\n", >> + get_item_with_default(capture_list_type_names, type), type, >> + get_item_with_default(capture_engine_class_names, classid), >> + classid); >> + return -ENODEV; >> + } >> + >> + num_regs = guc_cap_list_num_regs(gc, owner, type, classid); >> + /* intentional empty lists can exist depending on hw config */ >> + if (!num_regs) >> + return -ENODATA; >> + >> + if (size) >> + *size = PAGE_ALIGN((sizeof(struct guc_debug_capture_list)) + >> + (num_regs * sizeof(struct guc_mmio_reg))); >> + >> + return 0; >> +} >> + >> +int >> +xe_guc_capture_getlistsize(struct xe_guc *guc, u32 owner, u32 type, u32 classid, size_t *size) > > add kernel-doc for all public functions Will add > >> +{ >> + return guc_capture_getlistsize(guc, owner, type, classid, size, false); >> +} >> + >> +int >> +xe_guc_capture_getlist(struct xe_guc *guc, u32 owner, u32 type, u32 classid, void **outptr) > > ditto > >> +{ >> + struct xe_guc_state_capture *gc = guc->capture; >> + struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid]; >> + struct guc_debug_capture_list *listnode; >> + int ret, num_regs; >> + u8 *caplist, *tmp; >> + size_t size = 0; >> + >> + if (!gc->reglists) >> + return -ENODEV; >> + >> + if (cache->is_valid) { >> + *outptr = cache->ptr; >> + return cache->status; >> + } >> + >> + ret = xe_guc_capture_getlistsize(guc, owner, type, classid, &size); >> + if (ret) { >> + cache->is_valid = true; >> + cache->ptr = NULL; >> + cache->size = 0; >> + cache->status = ret; >> + return ret; >> + } >> + >> + caplist = drmm_kzalloc(guc_to_drm(guc), size, GFP_KERNEL); >> + if (!caplist) { >> + xe_gt_dbg(guc_to_gt(guc), "Failed to alloc cached register capture list"); > > we usually don't add extra messages for OOM condition as it will be > already reported Will be removed. > >> + return -ENOMEM; >> + } >> + >> + /* populate capture list header */ >> + tmp = caplist; >> + num_regs = guc_cap_list_num_regs(guc->capture, owner, type, classid); >> + listnode = (struct guc_debug_capture_list *)tmp; >> + listnode->header.info = FIELD_PREP(GUC_CAPTURELISTHDR_NUMDESCR, (u32)num_regs); >> + >> + /* populate list of register descriptor */ >> + tmp += sizeof(struct guc_debug_capture_list); >> + guc_capture_list_init(guc, owner, type, classid, (struct guc_mmio_reg *)tmp, num_regs); >> + >> + /* cache this list */ >> + cache->is_valid = true; >> + cache->ptr = caplist; >> + cache->size = size; >> + cache->status = 0; >> + >> + *outptr = caplist; >> + >> + return 0; >> +} >> + >> +int >> +xe_guc_capture_getnullheader(struct xe_guc *guc, void **outptr, size_t *size) >> +{ >> + struct xe_guc_state_capture *gc = guc->capture; >> + int tmp = sizeof(u32) * 4; >> + void *null_header; >> + >> + if (gc->ads_null_cache) { >> + *outptr = gc->ads_null_cache; >> + *size = tmp; >> + return 0; >> + } >> + >> + null_header = drmm_kzalloc(guc_to_drm(guc), tmp, GFP_KERNEL); >> + if (!null_header) { >> + xe_gt_dbg(guc_to_gt(guc), "Failed to alloc cached register capture null list"); >> + return -ENOMEM; >> + } >> + >> + gc->ads_null_cache = null_header; >> + *outptr = null_header; >> + *size = tmp; >> + >> + return 0; >> +} >> + >> +int xe_guc_capture_init(struct xe_guc *guc) >> +{ >> + guc->capture = drmm_kzalloc(guc_to_drm(guc), sizeof(*guc->capture), GFP_KERNEL); >> + if (!guc->capture) >> + return -ENOMEM; >> + >> + guc->capture->reglists = guc_capture_get_device_reglist(guc); >> + >> + return 0; >> +} >> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.h b/drivers/gpu/drm/xe/xe_guc_capture.h >> new file mode 100644 >> index 000000000000..ba3e0aabee01 >> --- /dev/null >> +++ b/drivers/gpu/drm/xe/xe_guc_capture.h >> @@ -0,0 +1,43 @@ >> +/* SPDX-License-Identifier: MIT */ >> +/* >> + * Copyright © 2021-2021 Intel Corporation > > 2024 > >> + */ >> + >> +#ifndef _XE_GUC_CAPTURE_H >> +#define _XE_GUC_CAPTURE_H >> + >> +#include <linux/types.h> >> +#include "regs/xe_reg_defs.h" >> + >> +struct xe_guc; >> + >> +/* >> + * struct __guc_mmio_reg_descr / struct __guc_mmio_reg_descr_group >> + * >> + * xe_guc_capture module uses these structures to maintain static >> + * tables (per unique platform) that consists of lists of registers >> + * (offsets, names, flags,...) that are used at the ADS regisration >> + * time as well as during runtime processing and reporting of error- >> + * capture states generated by GuC just prior to engine reset events. >> + */ >> +struct __guc_mmio_reg_descr { >> + struct xe_reg reg; >> + u32 flags; >> + u32 mask; >> + const char *regname; >> +}; >> + >> +struct __guc_mmio_reg_descr_group { >> + const struct __guc_mmio_reg_descr *list; >> + u32 num_regs; >> + u32 owner; /* see enum guc_capture_owner */ >> + u32 type; /* see enum guc_capture_type */ >> + u32 engine; /* as per MAX_ENGINE_CLASS */ >> +}; >> + >> +int xe_guc_capture_getlist(struct xe_guc *guc, u32 owner, u32 type, u32 classid, void **outptr); >> +int xe_guc_capture_getlistsize(struct xe_guc *guc, u32 owner, u32 type, u32 classid, size_t *size); >> +int xe_guc_capture_getnullheader(struct xe_guc *guc, void **outptr, size_t *size); >> +int xe_guc_capture_init(struct xe_guc *guc); >> + >> +#endif /* _XE_GUC_CAPTURE_H */ >> diff --git a/drivers/gpu/drm/xe/xe_guc_capture_fwif.h b/drivers/gpu/drm/xe/xe_guc_capture_fwif.h >> new file mode 100644 >> index 000000000000..1b08388b0b94 >> --- /dev/null >> +++ b/drivers/gpu/drm/xe/xe_guc_capture_fwif.h >> @@ -0,0 +1,145 @@ >> +/* SPDX-License-Identifier: MIT */ >> +/* >> + * Copyright © 2021-2022 Intel Corporation > > 2024 > >> + */ >> + >> +#ifndef _XE_GUC_CAPTURE_FWIF_H >> +#define _XE_GUC_CAPTURE_FWIF_H >> + >> +#include <linux/types.h> >> + >> +#include "xe_guc_fwif.h" >> + >> +/* >> + * struct guc_debug_capture_list_header / struct guc_debug_capture_list >> + * >> + * As part of ADS registration, these header structures (followed by >> + * an array of 'struct guc_mmio_reg' entries) are used to register with >> + * GuC microkernel the list of registers we want it to dump out prior >> + * to a engine reset. >> + */ >> +struct guc_debug_capture_list_header { >> + u32 info; >> +#define GUC_CAPTURELISTHDR_NUMDESCR GENMASK(15, 0) >> +} __packed; >> + >> +struct guc_debug_capture_list { >> + struct guc_debug_capture_list_header header; >> + struct guc_mmio_reg regs[]; >> +} __packed; >> + >> +/* >> + * struct guc_state_capture_header_t / struct guc_state_capture_t / >> + * guc_state_capture_group_header_t / guc_state_capture_group_t >> + * >> + * Prior to resetting engines that have hung or faulted, GuC microkernel >> + * reports the engine error-state (register values that was read) by >> + * logging them into the shared GuC log buffer using these hierarchy >> + * of structures. >> + */ >> +struct guc_state_capture_header_t { >> + u32 owner; >> +#define CAP_HDR_CAPTURE_VFID GENMASK(7, 0) >> + u32 info; >> +#define CAP_HDR_CAPTURE_TYPE GENMASK(3, 0) /* see enum guc_capture_type */ >> +#define CAP_HDR_ENGINE_CLASS GENMASK(7, 4) /* see GUC_MAX_ENGINE_CLASSES */ >> +#define CAP_HDR_ENGINE_INSTANCE GENMASK(11, 8) >> + u32 lrca; /* if type-instance, LRCA (address) that hung, else set to ~0 */ >> + u32 guc_id; /* if type-instance, context index of hung context, else set to ~0 */ >> + u32 num_mmios; >> +#define CAP_HDR_NUM_MMIOS GENMASK(9, 0) >> +} __packed; >> + >> +struct guc_state_capture_t { >> + struct guc_state_capture_header_t header; >> + struct guc_mmio_reg mmio_entries[]; >> +} __packed; >> + >> +enum guc_capture_group_types { >> + GUC_STATE_CAPTURE_GROUP_TYPE_FULL, >> + GUC_STATE_CAPTURE_GROUP_TYPE_PARTIAL, >> + GUC_STATE_CAPTURE_GROUP_TYPE_MAX, >> +}; >> + >> +struct guc_state_capture_group_header_t { >> + u32 owner; >> +#define CAP_GRP_HDR_CAPTURE_VFID GENMASK(7, 0) >> + u32 info; >> +#define CAP_GRP_HDR_NUM_CAPTURES GENMASK(7, 0) >> +#define CAP_GRP_HDR_CAPTURE_TYPE GENMASK(15, 8) /* guc_capture_group_types */ >> +} __packed; >> + >> +/* this is the top level structure where an error-capture dump starts */ >> +struct guc_state_capture_group_t { >> + struct guc_state_capture_group_header_t grp_header; >> + struct guc_state_capture_t capture_entries[]; >> +} __packed; > > all above definitions looks like pure GuC ABI and for that we have > dedicated folder xe/abi where we keep such defs > > ------- > > and all below definitions looks like Xe driver specific related to > xe_guc_capture so by convention they should be placed in > xe_guc_capture_types.h file will do > >> + >> +/* >> + * struct __guc_capture_ads_cache >> + * >> + * A structure to cache register lists that were populated and registered >> + * with GuC at startup during ADS registration. This allows much quicker >> + * GuC resets without re-parsing all the tables for the given gt. >> + */ >> +struct __guc_capture_ads_cache { >> + bool is_valid; >> + void *ptr; >> + size_t size; >> + int status; >> +}; >> + >> +/** >> + * struct xe_guc_state_capture >> + * >> + * Internal context of the xe_guc_capture module. >> + */ >> +struct xe_guc_state_capture { >> + /** >> + * @reglists: static table of register lists used for error-capture state. >> + */ >> + const struct __guc_mmio_reg_descr_group *reglists; >> + >> + /** >> + * @ads_cache: cached register lists that is ADS format ready >> + */ >> + struct __guc_capture_ads_cache ads_cache[GUC_CAPTURE_LIST_INDEX_MAX] >> + [GUC_CAPTURE_LIST_TYPE_MAX] >> + [GUC_MAX_ENGINE_CLASSES]; >> + >> + /** >> + * @ads_null_cache: ADS null cache. >> + */ >> + void *ads_null_cache; >> + >> + /** >> + * @cachelist: Pool of pre-allocated nodes for error capture output >> + * >> + * We need this pool of pre-allocated nodes because we cannot >> + * dynamically allocate new nodes when receiving the G2H notification >> + * because the event handlers for all G2H event-processing is called >> + * by the ct processing worker queue and when that queue is being >> + * processed, there is no absoluate guarantee that we are not in the >> + * midst of a GT reset operation (which doesn't allow allocations). >> + */ >> + struct list_head cachelist; >> +#define PREALLOC_NODES_MAX_COUNT (3 * GUC_MAX_ENGINE_CLASSES * GUC_MAX_INSTANCES_PER_CLASS) >> +#define PREALLOC_NODES_DEFAULT_NUMREGS 64 >> + >> + /** >> + * @max_mmio_per_node: Max MMIO per node. >> + */ >> + int max_mmio_per_node; >> + >> + /** >> + * @outlist: Pool of pre-allocated nodes for error capture output >> + * >> + * A linked list of parsed GuC error-capture output data before >> + * reporting with formatting via xe_devcoredump. Each node in this linked list shall >> + * contain a single engine-capture including global, engine-class and >> + * engine-instance register dumps as per guc_capture_parsed_output_node >> + */ >> + struct list_head outlist; >> +}; >> + >> +#endif /* _XE_GUC_CAPTURE_FWIF_H */ >> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h >> index 19ee71aeaf17..04b03c398191 100644 >> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h >> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h >> @@ -9,6 +9,7 @@ >> #include <linux/bits.h> >> >> #include "abi/guc_klvs_abi.h" >> +#include "xe_hw_engine_types.h" >> >> #define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 4 >> #define G2H_LEN_DW_DEREGISTER_CONTEXT 3 >> @@ -164,8 +165,11 @@ struct guc_mmio_reg { >> u32 flags; >> u32 mask; >> #define GUC_REGSET_MASKED BIT(0) >> +#define GUC_REGSET_STEERING_NEEDED BIT(1) >> #define GUC_REGSET_MASKED_WITH_VALUE BIT(2) >> #define GUC_REGSET_RESTORE_ONLY BIT(3) >> +#define GUC_REGSET_STEERING_GROUP GENMASK(16, 12) >> +#define GUC_REGSET_STEERING_INSTANCE GENMASK(23, 20) >> } __packed; >> >> /* GuC register sets */ >> @@ -194,6 +198,24 @@ enum { >> GUC_CAPTURE_LIST_INDEX_MAX = 2, >> }; >> >> +/*Register-types of GuC capture register lists */ >> +enum guc_capture_type { >> + GUC_CAPTURE_LIST_TYPE_GLOBAL = 0, >> + GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, >> + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, >> + GUC_CAPTURE_LIST_TYPE_MAX, >> +}; >> + >> +/* Class indecies for capture_class and capture_instance arrays */ >> +enum { >> + GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE = 0, >> + GUC_CAPTURE_LIST_CLASS_VIDEO = 1, >> + GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE = 2, >> + GUC_CAPTURE_LIST_CLASS_BLITTER = 3, >> + GUC_CAPTURE_LIST_CLASS_GSC_OTHER = 4, >> + GUC_CAPTURE_LIST_CLASS_MAX = 5 >> +}; >> + >> /* GuC Additional Data Struct */ >> struct guc_ads { >> struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; >> diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h >> index 546ac6350a31..6d7d0976b7af 100644 >> --- a/drivers/gpu/drm/xe/xe_guc_types.h >> +++ b/drivers/gpu/drm/xe/xe_guc_types.h >> @@ -58,6 +58,8 @@ struct xe_guc { >> struct xe_guc_ads ads; >> /** @ct: GuC ct */ >> struct xe_guc_ct ct; >> + /** @capture: the error-state-capture module's data and objects */ >> + struct xe_guc_state_capture *capture; >> /** @pc: GuC Power Conservation */ >> struct xe_guc_pc pc; >> /** @dbm: GuC Doorbell Manager */ ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v9 2/4] drm/xe/guc: Add XE_LP steered register lists 2024-06-07 0:07 [PATCH v9 0/4] drm/xe/guc: Add GuC based register capture for error capture Zhanjun Dong 2024-06-07 0:07 ` [PATCH v9 1/4] drm/xe/guc: Prepare GuC register list and update ADS size " Zhanjun Dong @ 2024-06-07 0:07 ` Zhanjun Dong 2024-06-13 19:02 ` Teres Alexis, Alan Previn 2024-06-07 0:07 ` [PATCH v9 3/4] drm/xe/guc: Add capture size check in GuC log buffer Zhanjun Dong ` (9 subsequent siblings) 11 siblings, 1 reply; 24+ messages in thread From: Zhanjun Dong @ 2024-06-07 0:07 UTC (permalink / raw) To: intel-xe; +Cc: Zhanjun Dong Add the ability for runtime allocation and freeing of steered register list extentions that depend on the detected HW config fuses. Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> --- drivers/gpu/drm/xe/xe_guc_capture.c | 155 ++++++++++++++++++++++- drivers/gpu/drm/xe/xe_guc_capture.h | 1 + drivers/gpu/drm/xe/xe_guc_capture_fwif.h | 8 ++ 3 files changed, 162 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c index 19bd79285061..951408846c97 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture.c +++ b/drivers/gpu/drm/xe/xe_guc_capture.c @@ -105,6 +105,7 @@ static const struct __guc_mmio_reg_descr empty_regs_list[] = { TO_GCAP_DEF_OWNER(regsowner), \ TO_GCAP_DEF_TYPE(regstype), \ class, \ + NULL, \ } /* List of lists */ @@ -165,9 +166,138 @@ guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists, return NULL; } +static struct __guc_mmio_reg_descr_group * +guc_capture_get_one_ext_list(struct __guc_mmio_reg_descr_group *reglists, + u32 owner, u32 type, u32 id) +{ + int i; + + if (!reglists) + return NULL; + + for (i = 0; reglists[i].extlist; ++i) { + if (reglists[i].owner == owner && reglists[i].type == type && + (reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL)) + return ®lists[i]; + } + + return NULL; +} + +struct __ext_steer_reg { + const char *name; + struct xe_reg_mcr reg; +}; + +static const struct __ext_steer_reg xe_extregs[] = { + {"SAMPLER_INSTDONE", SAMPLER_INSTDONE}, + {"ROW_INSTDONE", ROW_INSTDONE} +}; + +static const struct __ext_steer_reg xehpg_extregs[] = { + {"XEHPG_INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT} +}; + +static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext, + const struct __ext_steer_reg *extlist, + int slice_id, int subslice_id) +{ + ext->reg = XE_REG(extlist->reg.__reg.addr); + ext->flags = FIELD_PREP(GUC_REGSET_STEERING_GROUP, slice_id); + ext->flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, subslice_id); + ext->regname = extlist->name; +} + +static int +__alloc_ext_regs(struct drm_device *drm, struct __guc_mmio_reg_descr_group *newlist, + const struct __guc_mmio_reg_descr_group *rootlist, int num_regs) +{ + struct __guc_mmio_reg_descr *list; + + list = drmm_kzalloc(drm, num_regs * sizeof(struct __guc_mmio_reg_descr), GFP_KERNEL); + if (!list) + return -ENOMEM; + + newlist->extlist = list; + newlist->num_regs = num_regs; + newlist->owner = rootlist->owner; + newlist->engine = rootlist->engine; + newlist->type = rootlist->type; + + return 0; +} + +static void +guc_capture_alloc_steered_lists(struct xe_guc *guc, const struct __guc_mmio_reg_descr_group *lists) +{ + struct xe_gt *gt = guc_to_gt(guc); + u16 slice, subslice; + int iter, i, num_steer_regs, num_tot_regs = 0; + const struct __guc_mmio_reg_descr_group *list; + struct __guc_mmio_reg_descr_group *extlists; + struct __guc_mmio_reg_descr *extarray; + bool has_xehpg_extregs; + struct drm_device *drm = >_to_xe(gt)->drm; + + /* steered registers currently only exist for the render-class */ + list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF, + GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, + GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE); + /* skip if extlists was previously allocated */ + if (!list || guc->capture->extlists) + return; + + has_xehpg_extregs = GRAPHICS_VERx100(gt_to_xe(gt)) >= 1255; + + num_steer_regs = ARRAY_SIZE(xe_extregs); + if (has_xehpg_extregs) + num_steer_regs += ARRAY_SIZE(xehpg_extregs); + + num_tot_regs = num_steer_regs * bitmap_weight(gt->fuse_topo.g_dss_mask, + sizeof(gt->fuse_topo.g_dss_mask) * 8); + if (!num_tot_regs) + return; + + /* allocate an extra for an end marker */ + extlists = drmm_kzalloc(drm, 2 * sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL); + if (!extlists) + return; + + if (__alloc_ext_regs(drm, &extlists[0], list, num_tot_regs)) { + drmm_kfree(drm, extlists); + return; + } + + extarray = extlists[0].extlist; + for_each_dss_steering(iter, gt, slice, subslice) { + for (i = 0; i < ARRAY_SIZE(xe_extregs); ++i) { + __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice); + ++extarray; + } + + if (has_xehpg_extregs) { + for (i = 0; i < ARRAY_SIZE(xehpg_extregs); ++i) { + __fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice); + ++extarray; + } + } + } + + xe_gt_dbg(guc_to_gt(guc), "capture found %d ext-regs.\n", num_tot_regs); + guc->capture->extlists = extlists; +} + static const struct __guc_mmio_reg_descr_group * guc_capture_get_device_reglist(struct xe_guc *guc) { + /* + * For certain engine classes, there are slice and subslice + * level registers requiring steering. We allocate and populate + * these at init time based on hw config add it as an extension + * list at the end of the pre-populated render list. + */ + guc_capture_alloc_steered_lists(guc, xe_lp_lists); + return xe_lp_lists; } @@ -175,9 +305,11 @@ static int guc_capture_list_init(struct xe_guc *guc, u32 owner, u32 type, u32 classid, struct guc_mmio_reg *ptr, u16 num_entries) { - u32 i = 0; + u32 i = 0, j = 0; const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists; + struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists; const struct __guc_mmio_reg_descr_group *match; + struct __guc_mmio_reg_descr_group *matchext; if (!reglists) return -ENODEV; @@ -193,6 +325,17 @@ guc_capture_list_init(struct xe_guc *guc, u32 owner, u32 type, u32 classid, ptr[i].mask = match->list[i].mask; } + matchext = guc_capture_get_one_ext_list(extlists, owner, type, classid); + if (matchext) { + for (i = match->num_regs, j = 0; i < num_entries && + i < (match->num_regs + matchext->num_regs) && + j < matchext->num_regs; ++i, ++j) { + ptr[i].offset = matchext->extlist[j].reg.addr; + ptr[i].value = 0xDEADF00D; + ptr[i].flags = matchext->extlist[j].flags; + ptr[i].mask = matchext->extlist[j].mask; + } + } if (i < num_entries) xe_gt_dbg(guc_to_gt(guc), "Got short capture reglist init: %d out %d.\n", i, num_entries); @@ -204,12 +347,20 @@ static int guc_cap_list_num_regs(struct xe_guc_state_capture *gc, u32 owner, u32 type, u32 classid) { const struct __guc_mmio_reg_descr_group *match; + struct __guc_mmio_reg_descr_group *matchext; + int num_regs; match = guc_capture_get_one_list(gc->reglists, owner, type, classid); if (!match) return 0; - return match->num_regs; + num_regs = match->num_regs; + + matchext = guc_capture_get_one_ext_list(gc->extlists, owner, type, classid); + if (matchext) + num_regs += matchext->num_regs; + + return num_regs; } static int diff --git a/drivers/gpu/drm/xe/xe_guc_capture.h b/drivers/gpu/drm/xe/xe_guc_capture.h index ba3e0aabee01..a62b1dbd47a6 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture.h +++ b/drivers/gpu/drm/xe/xe_guc_capture.h @@ -33,6 +33,7 @@ struct __guc_mmio_reg_descr_group { u32 owner; /* see enum guc_capture_owner */ u32 type; /* see enum guc_capture_type */ u32 engine; /* as per MAX_ENGINE_CLASS */ + struct __guc_mmio_reg_descr *extlist; /* only used for steered registers */ }; int xe_guc_capture_getlist(struct xe_guc *guc, u32 owner, u32 type, u32 classid, void **outptr); diff --git a/drivers/gpu/drm/xe/xe_guc_capture_fwif.h b/drivers/gpu/drm/xe/xe_guc_capture_fwif.h index 1b08388b0b94..199e3c0108a4 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture_fwif.h +++ b/drivers/gpu/drm/xe/xe_guc_capture_fwif.h @@ -100,6 +100,14 @@ struct xe_guc_state_capture { */ const struct __guc_mmio_reg_descr_group *reglists; + /** + * @extlists: allocated table of steered register lists used for error-capture state. + * + * NOTE: steered registers have multiple instances depending on the HW configuration + * (slices or dual-sub-slices) and thus depends on HW fuses discovered at startup + */ + struct __guc_mmio_reg_descr_group *extlists; + /** * @ads_cache: cached register lists that is ADS format ready */ -- 2.34.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v9 2/4] drm/xe/guc: Add XE_LP steered register lists 2024-06-07 0:07 ` [PATCH v9 2/4] drm/xe/guc: Add XE_LP steered register lists Zhanjun Dong @ 2024-06-13 19:02 ` Teres Alexis, Alan Previn 0 siblings, 0 replies; 24+ messages in thread From: Teres Alexis, Alan Previn @ 2024-06-13 19:02 UTC (permalink / raw) To: Dong, Zhanjun, intel-xe@lists.freedesktop.org I think u missed the RB from rev8 for this patch - i see the only difference in rev9 was a trivial nit you fixed that was not blocking rev8's RB. That said, repeating RB: Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> On Thu, 2024-06-06 at 17:07 -0700, Zhanjun Dong wrote: > Add the ability for runtime allocation and freeing of > steered register list extentions that depend on the > detected HW config fuses. > > Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> > --- > drivers/gpu/drm/xe/xe_guc_capture.c | 155 alan:snip ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v9 3/4] drm/xe/guc: Add capture size check in GuC log buffer 2024-06-07 0:07 [PATCH v9 0/4] drm/xe/guc: Add GuC based register capture for error capture Zhanjun Dong 2024-06-07 0:07 ` [PATCH v9 1/4] drm/xe/guc: Prepare GuC register list and update ADS size " Zhanjun Dong 2024-06-07 0:07 ` [PATCH v9 2/4] drm/xe/guc: Add XE_LP steered register lists Zhanjun Dong @ 2024-06-07 0:07 ` Zhanjun Dong 2024-06-14 12:13 ` Michal Wajdeczko 2024-06-07 0:07 ` [PATCH v9 4/4] drm/xe/guc: Extract GuC capture lists to register snapshot Zhanjun Dong ` (8 subsequent siblings) 11 siblings, 1 reply; 24+ messages in thread From: Zhanjun Dong @ 2024-06-07 0:07 UTC (permalink / raw) To: intel-xe; +Cc: Zhanjun Dong The capture-nodes is included in GuC log buffer, add the size check for capture region in the whole GuC log buffer. Add capture output size check before allocating the shared buffer. Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> --- drivers/gpu/drm/xe/xe_gt_printk.h | 3 + drivers/gpu/drm/xe/xe_guc_capture.c | 77 +++++++++++ drivers/gpu/drm/xe/xe_guc_fwif.h | 48 +++++++ drivers/gpu/drm/xe/xe_guc_log.c | 179 ++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_guc_log.h | 17 ++- drivers/gpu/drm/xe/xe_guc_log_types.h | 24 ++++ 6 files changed, 347 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h index c2b004d3f48e..107360edfcd6 100644 --- a/drivers/gpu/drm/xe/xe_gt_printk.h +++ b/drivers/gpu/drm/xe/xe_gt_printk.h @@ -22,6 +22,9 @@ #define xe_gt_notice(_gt, _fmt, ...) \ xe_gt_printk((_gt), notice, _fmt, ##__VA_ARGS__) +#define xe_gt_notice_ratelimited(_gt, _fmt, ...) \ + xe_gt_printk((_gt), err_ratelimited, _fmt, ##__VA_ARGS__) + #define xe_gt_info(_gt, _fmt, ...) \ xe_gt_printk((_gt), info, _fmt, ##__VA_ARGS__) diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c index 951408846c97..0c90def290de 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture.c +++ b/drivers/gpu/drm/xe/xe_guc_capture.c @@ -21,6 +21,7 @@ #include "xe_gt_mcr.h" #include "xe_gt_printk.h" #include "xe_guc.h" +#include "xe_guc_ads.h" #include "xe_guc_capture.h" #include "xe_guc_capture_fwif.h" #include "xe_guc_ct.h" @@ -491,6 +492,81 @@ xe_guc_capture_getnullheader(struct xe_guc *guc, void **outptr, size_t *size) return 0; } +static int +guc_capture_output_size_est(struct xe_guc *guc) +{ + struct xe_gt *gt = guc_to_gt(guc); + struct xe_hw_engine *hwe; + enum xe_hw_engine_id id; + + int capture_size = 0; + size_t tmp = 0; + + if (!guc->capture) + return -ENODEV; + + /* + * If every single engine-instance suffered a failure in quick succession but + * were all unrelated, then a burst of multiple error-capture events would dump + * registers for every one engine instance, one at a time. In this case, GuC + * would even dump the global-registers repeatedly. + * + * For each engine instance, there would be 1 x guc_state_capture_group_t output + * followed by 3 x guc_state_capture_t lists. The latter is how the register + * dumps are split across different register types (where the '3' are global vs class + * vs instance). + */ + for_each_hw_engine(hwe, gt, id) { + capture_size += sizeof(struct guc_state_capture_group_header_t) + + (3 * sizeof(struct guc_state_capture_header_t)); + + if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &tmp, true)) + capture_size += tmp; + + if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, + hwe->class, &tmp, true)) { + capture_size += tmp; + } + if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, + hwe->class, &tmp, true)) { + capture_size += tmp; + } + } + + return capture_size; +} + +/* + * Add on a 3x multiplier to allow for multiple back-to-back captures occurring + * before the Xe can read the data out and process it + */ +#define GUC_CAPTURE_OVERBUFFER_MULTIPLIER 3 + +static void check_guc_capture_size(struct xe_guc *guc) +{ + int capture_size = guc_capture_output_size_est(guc); + int spare_size = capture_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER; + u32 buffer_size = xe_guc_log_section_size_capture(&guc->log); + + /* + * NOTE: capture_size is much smaller than the capture region allocation (DG2: <80K vs 1MB) + * Additionally, its based on space needed to fit all engines getting reset at once + * within the same G2H handler task slot. This is very unlikely. However, if GuC really + * does run out of space for whatever reason, we will see an separate warning message + * when processing the G2H event capture-notification, search for: + * xe_guc_STATE_CAPTURE_EVENT_STATUS_NOSPACE. + */ + if (capture_size < 0) + xe_gt_warn(guc_to_gt(guc), "Failed to calculate error state capture buffer minimum size: %d!\n", + capture_size); + if (capture_size > buffer_size) + xe_gt_warn(guc_to_gt(guc), "Error state capture buffer maybe small: %d < %d\n", + buffer_size, capture_size); + else if (spare_size > buffer_size) + xe_gt_dbg(guc_to_gt(guc), "Error state capture buffer lacks spare size: %d < %d (min = %d)\n", + buffer_size, spare_size, capture_size); +} + int xe_guc_capture_init(struct xe_guc *guc) { guc->capture = drmm_kzalloc(guc_to_drm(guc), sizeof(*guc->capture), GFP_KERNEL); @@ -499,5 +575,6 @@ int xe_guc_capture_init(struct xe_guc *guc) guc->capture->reglists = guc_capture_get_device_reglist(guc); + check_guc_capture_size(guc); return 0; } diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h index 04b03c398191..908298791c93 100644 --- a/drivers/gpu/drm/xe/xe_guc_fwif.h +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h @@ -250,6 +250,54 @@ struct guc_engine_usage { struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; } __packed; +/* GuC logging structures */ + +enum guc_log_buffer_type { + GUC_DEBUG_LOG_BUFFER, + GUC_CRASH_DUMP_LOG_BUFFER, + GUC_CAPTURE_LOG_BUFFER, + GUC_MAX_LOG_BUFFER +}; + +/* + * struct guc_log_buffer_state - GuC log buffer state + * + * Below state structure is used for coordination of retrieval of GuC firmware + * logs. Separate state is maintained for each log buffer type. + * read_ptr points to the location where Xe read last in log buffer and + * is read only for GuC firmware. write_ptr is incremented by GuC with number + * of bytes written for each log entry and is read only for Xe. + * When any type of log buffer becomes half full, GuC sends a flush interrupt. + * GuC firmware expects that while it is writing to 2nd half of the buffer, + * first half would get consumed by Host and then get a flush completed + * acknowledgment from Host, so that it does not end up doing any overwrite + * causing loss of logs. So when buffer gets half filled & Xe has requested + * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr + * to the value of write_ptr and raise the interrupt. + * On receiving the interrupt Xe should read the buffer, clear flush_to_file + * field and also update read_ptr with the value of sample_write_ptr, before + * sending an acknowledgment to GuC. marker & version fields are for internal + * usage of GuC and opaque to Xe. buffer_full_cnt field is incremented every + * time GuC detects the log buffer overflow. + */ +struct guc_log_buffer_state { + u32 marker[2]; + u32 read_ptr; + u32 write_ptr; + u32 size; + u32 sampled_write_ptr; + u32 wrap_offset; + union { + struct { + u32 flush_to_file:1; + u32 buffer_full_cnt:4; + u32 reserved:27; + }; + u32 flags; + }; + u32 version; +} __packed; + /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ enum xe_guc_recv_message { XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), diff --git a/drivers/gpu/drm/xe/xe_guc_log.c b/drivers/gpu/drm/xe/xe_guc_log.c index a37ee3419428..c97fc4d57168 100644 --- a/drivers/gpu/drm/xe/xe_guc_log.c +++ b/drivers/gpu/drm/xe/xe_guc_log.c @@ -9,9 +9,30 @@ #include "xe_bo.h" #include "xe_gt.h" +#include "xe_gt_printk.h" #include "xe_map.h" #include "xe_module.h" +#define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \ + __stringify(x), (long)(x)) + +#define GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE CRASH_BUFFER_SIZE +#define GUC_LOG_DEFAULT_DEBUG_BUFFER_SIZE DEBUG_BUFFER_SIZE +#define GUC_LOG_DEFAULT_CAPTURE_BUFFER_SIZE CAPTURE_BUFFER_SIZE + +struct guc_log_section { + u32 max; + u32 flag; + u32 default_val; + const char *name; +}; + +static struct xe_gt * +guc_to_gt(struct xe_guc *guc) +{ + return container_of(guc, struct xe_gt, uc.guc); +} + static struct xe_gt * log_to_gt(struct xe_guc_log *log) { @@ -96,3 +117,161 @@ int xe_guc_log_init(struct xe_guc_log *log) return 0; } + +static void _guc_log_init_sizes(struct xe_guc_log *log) +{ + struct xe_guc *guc = log_to_guc(log); + static const struct guc_log_section sections[GUC_LOG_SECTIONS_LIMIT] = { + { + GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT, + GUC_LOG_LOG_ALLOC_UNITS, + GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE, + "crash dump" + }, + { + GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT, + GUC_LOG_LOG_ALLOC_UNITS, + GUC_LOG_DEFAULT_DEBUG_BUFFER_SIZE, + "debug", + }, + { + GUC_LOG_CAPTURE_MASK >> GUC_LOG_CAPTURE_SHIFT, + GUC_LOG_CAPTURE_ALLOC_UNITS, + GUC_LOG_DEFAULT_CAPTURE_BUFFER_SIZE, + "capture", + } + }; + int i; + + for (i = 0; i < GUC_LOG_SECTIONS_LIMIT; i++) + log->sizes[i].bytes = sections[i].default_val; + + /* If debug size > 1MB then bump default crash size to keep the same units */ + if (log->sizes[GUC_LOG_SECTIONS_DEBUG].bytes >= SZ_1M && + GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE < SZ_1M) + log->sizes[GUC_LOG_SECTIONS_CRASH].bytes = SZ_1M; + + /* Prepare the GuC API structure fields: */ + for (i = 0; i < GUC_LOG_SECTIONS_LIMIT; i++) { + /* Convert to correct units */ + if ((log->sizes[i].bytes % SZ_1M) == 0) { + log->sizes[i].units = SZ_1M; + log->sizes[i].flag = sections[i].flag; + } else { + log->sizes[i].units = SZ_4K; + log->sizes[i].flag = 0; + } + + if (!IS_ALIGNED(log->sizes[i].bytes, log->sizes[i].units)) + xe_gt_err(guc_to_gt(guc), "Mis-aligned log %s size: 0x%X vs 0x%X!\n", + sections[i].name, log->sizes[i].bytes, log->sizes[i].units); + log->sizes[i].count = log->sizes[i].bytes / log->sizes[i].units; + + if (!log->sizes[i].count) { + xe_gt_err(guc_to_gt(guc), "Zero log %s size!\n", sections[i].name); + } else { + /* Size is +1 unit */ + log->sizes[i].count--; + } + + /* Clip to field size */ + if (log->sizes[i].count > sections[i].max) { + xe_gt_err(guc_to_gt(guc), "log %s size too large: %d vs %d!\n", + sections[i].name, log->sizes[i].count + 1, sections[i].max + 1); + log->sizes[i].count = sections[i].max; + } + } + + if (log->sizes[GUC_LOG_SECTIONS_CRASH].units != log->sizes[GUC_LOG_SECTIONS_DEBUG].units) { + xe_gt_err(guc_to_gt(guc), "Unit mismatch for crash and debug sections: %d vs %d!\n", + log->sizes[GUC_LOG_SECTIONS_CRASH].units, + log->sizes[GUC_LOG_SECTIONS_DEBUG].units); + log->sizes[GUC_LOG_SECTIONS_CRASH].units = log->sizes[GUC_LOG_SECTIONS_DEBUG].units; + log->sizes[GUC_LOG_SECTIONS_CRASH].count = 0; + } + + log->sizes_initialised = true; +} + +static void guc_log_init_sizes(struct xe_guc_log *log) +{ + if (log->sizes_initialised) + return; + + _guc_log_init_sizes(log); +} + +static u32 xe_guc_log_section_size_crash(struct xe_guc_log *log) +{ + guc_log_init_sizes(log); + + return log->sizes[GUC_LOG_SECTIONS_CRASH].bytes; +} + +static u32 xe_guc_log_section_size_debug(struct xe_guc_log *log) +{ + guc_log_init_sizes(log); + + return log->sizes[GUC_LOG_SECTIONS_DEBUG].bytes; +} + +u32 xe_guc_log_section_size_capture(struct xe_guc_log *log) +{ + guc_log_init_sizes(log); + + return log->sizes[GUC_LOG_SECTIONS_CAPTURE].bytes; +} + +bool xe_guc_check_log_buf_overflow(struct xe_guc_log *log, enum guc_log_buffer_type type, + unsigned int full_cnt) +{ + unsigned int prev_full_cnt = log->stats[type].sampled_overflow; + bool overflow = false; + + if (full_cnt != prev_full_cnt) { + overflow = true; + + log->stats[type].overflow = full_cnt; + log->stats[type].sampled_overflow += full_cnt - prev_full_cnt; + + if (full_cnt < prev_full_cnt) { + /* buffer_full_cnt is a 4 bit counter */ + log->stats[type].sampled_overflow += 16; + } + xe_gt_notice_ratelimited(log_to_gt(log), "log buffer overflow\n"); + } + + return overflow; +} + +unsigned int xe_guc_get_log_buffer_size(struct xe_guc_log *log, + enum guc_log_buffer_type type) +{ + switch (type) { + case GUC_DEBUG_LOG_BUFFER: + return xe_guc_log_section_size_debug(log); + case GUC_CRASH_DUMP_LOG_BUFFER: + return xe_guc_log_section_size_crash(log); + case GUC_CAPTURE_LOG_BUFFER: + return xe_guc_log_section_size_capture(log); + default: + MISSING_CASE(type); + } + + return 0; +} + +size_t xe_guc_get_log_buffer_offset(struct xe_guc_log *log, + enum guc_log_buffer_type type) +{ + enum guc_log_buffer_type i; + size_t offset = PAGE_SIZE;/* for the log_buffer_states */ + + for (i = GUC_DEBUG_LOG_BUFFER; i < GUC_MAX_LOG_BUFFER; ++i) { + if (i == type) + break; + offset += xe_guc_get_log_buffer_size(log, i); + } + + return offset; +} diff --git a/drivers/gpu/drm/xe/xe_guc_log.h b/drivers/gpu/drm/xe/xe_guc_log.h index 2d25ab28b4b3..de55de4052ca 100644 --- a/drivers/gpu/drm/xe/xe_guc_log.h +++ b/drivers/gpu/drm/xe/xe_guc_log.h @@ -7,6 +7,7 @@ #define _XE_GUC_LOG_H_ #include "xe_guc_log_types.h" +#include "xe_guc_types.h" struct drm_printer; @@ -17,7 +18,7 @@ struct drm_printer; #else #define CRASH_BUFFER_SIZE SZ_8K #define DEBUG_BUFFER_SIZE SZ_64K -#define CAPTURE_BUFFER_SIZE SZ_16K +#define CAPTURE_BUFFER_SIZE SZ_1M #endif /* * While we're using plain log level in i915, GuC controls are much more... @@ -36,6 +37,11 @@ struct drm_printer; #define GUC_VERBOSITY_TO_LOG_LEVEL(x) ((x) + 2) #define GUC_LOG_LEVEL_MAX GUC_VERBOSITY_TO_LOG_LEVEL(GUC_LOG_VERBOSITY_MAX) +static inline struct xe_guc *log_to_guc(struct xe_guc_log *log) +{ + return container_of(log, struct xe_guc, log); +} + int xe_guc_log_init(struct xe_guc_log *log); void xe_guc_log_print(struct xe_guc_log *log, struct drm_printer *p); @@ -45,4 +51,13 @@ xe_guc_log_get_level(struct xe_guc_log *log) return log->level; } +u32 xe_guc_log_section_size_capture(struct xe_guc_log *log); + +bool xe_guc_check_log_buf_overflow(struct xe_guc_log *log, + enum guc_log_buffer_type type, + unsigned int full_cnt); +unsigned int xe_guc_get_log_buffer_size(struct xe_guc_log *log, + enum guc_log_buffer_type type); +size_t xe_guc_get_log_buffer_offset(struct xe_guc_log *log, + enum guc_log_buffer_type type); #endif diff --git a/drivers/gpu/drm/xe/xe_guc_log_types.h b/drivers/gpu/drm/xe/xe_guc_log_types.h index 125080d138a7..3d4bf2a73102 100644 --- a/drivers/gpu/drm/xe/xe_guc_log_types.h +++ b/drivers/gpu/drm/xe/xe_guc_log_types.h @@ -7,6 +7,14 @@ #define _XE_GUC_LOG_TYPES_H_ #include <linux/types.h> +#include "xe_guc_fwif.h" + +enum { + GUC_LOG_SECTIONS_CRASH, + GUC_LOG_SECTIONS_DEBUG, + GUC_LOG_SECTIONS_CAPTURE, + GUC_LOG_SECTIONS_LIMIT +}; struct xe_bo; @@ -18,6 +26,22 @@ struct xe_guc_log { u32 level; /** @bo: XE BO for GuC log */ struct xe_bo *bo; + + /* Allocation settings */ + struct { + s32 bytes; /* Size in bytes */ + s32 units; /* GuC API units - 1MB or 4KB */ + s32 count; /* Number of API units */ + u32 flag; /* GuC API units flag */ + } sizes[GUC_LOG_SECTIONS_LIMIT]; + bool sizes_initialised; + + /* logging related stats */ + struct { + u32 sampled_overflow; + u32 overflow; + u32 flush; + } stats[GUC_MAX_LOG_BUFFER]; }; #endif -- 2.34.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v9 3/4] drm/xe/guc: Add capture size check in GuC log buffer 2024-06-07 0:07 ` [PATCH v9 3/4] drm/xe/guc: Add capture size check in GuC log buffer Zhanjun Dong @ 2024-06-14 12:13 ` Michal Wajdeczko 2024-06-19 19:44 ` Dong, Zhanjun 0 siblings, 1 reply; 24+ messages in thread From: Michal Wajdeczko @ 2024-06-14 12:13 UTC (permalink / raw) To: Zhanjun Dong, intel-xe, John Harrison On 07.06.2024 02:07, Zhanjun Dong wrote: > The capture-nodes is included in GuC log buffer, add the size check > for capture region in the whole GuC log buffer. > Add capture output size check before allocating the shared buffer. > > Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> > --- > drivers/gpu/drm/xe/xe_gt_printk.h | 3 + > drivers/gpu/drm/xe/xe_guc_capture.c | 77 +++++++++++ > drivers/gpu/drm/xe/xe_guc_fwif.h | 48 +++++++ > drivers/gpu/drm/xe/xe_guc_log.c | 179 ++++++++++++++++++++++++++ > drivers/gpu/drm/xe/xe_guc_log.h | 17 ++- > drivers/gpu/drm/xe/xe_guc_log_types.h | 24 ++++ > 6 files changed, 347 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h > index c2b004d3f48e..107360edfcd6 100644 > --- a/drivers/gpu/drm/xe/xe_gt_printk.h > +++ b/drivers/gpu/drm/xe/xe_gt_printk.h > @@ -22,6 +22,9 @@ > #define xe_gt_notice(_gt, _fmt, ...) \ > xe_gt_printk((_gt), notice, _fmt, ##__VA_ARGS__) > > +#define xe_gt_notice_ratelimited(_gt, _fmt, ...) \ > + xe_gt_printk((_gt), err_ratelimited, _fmt, ##__VA_ARGS__) you are mixing here 'notice' with 'err' > + > #define xe_gt_info(_gt, _fmt, ...) \ > xe_gt_printk((_gt), info, _fmt, ##__VA_ARGS__) > > diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c > index 951408846c97..0c90def290de 100644 > --- a/drivers/gpu/drm/xe/xe_guc_capture.c > +++ b/drivers/gpu/drm/xe/xe_guc_capture.c > @@ -21,6 +21,7 @@ > #include "xe_gt_mcr.h" > #include "xe_gt_printk.h" > #include "xe_guc.h" > +#include "xe_guc_ads.h" > #include "xe_guc_capture.h" > #include "xe_guc_capture_fwif.h" > #include "xe_guc_ct.h" > @@ -491,6 +492,81 @@ xe_guc_capture_getnullheader(struct xe_guc *guc, void **outptr, size_t *size) > return 0; > } > > +static int > +guc_capture_output_size_est(struct xe_guc *guc) > +{ > + struct xe_gt *gt = guc_to_gt(guc); > + struct xe_hw_engine *hwe; > + enum xe_hw_engine_id id; > + > + int capture_size = 0; > + size_t tmp = 0; > + > + if (!guc->capture) > + return -ENODEV; > + > + /* > + * If every single engine-instance suffered a failure in quick succession but > + * were all unrelated, then a burst of multiple error-capture events would dump > + * registers for every one engine instance, one at a time. In this case, GuC > + * would even dump the global-registers repeatedly. > + * > + * For each engine instance, there would be 1 x guc_state_capture_group_t output > + * followed by 3 x guc_state_capture_t lists. The latter is how the register > + * dumps are split across different register types (where the '3' are global vs class > + * vs instance). > + */ > + for_each_hw_engine(hwe, gt, id) { > + capture_size += sizeof(struct guc_state_capture_group_header_t) + > + (3 * sizeof(struct guc_state_capture_header_t)); > + > + if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &tmp, true)) > + capture_size += tmp; > + > + if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, > + hwe->class, &tmp, true)) { > + capture_size += tmp; > + } > + if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, > + hwe->class, &tmp, true)) { > + capture_size += tmp; > + } > + } > + > + return capture_size; > +} > + > +/* > + * Add on a 3x multiplier to allow for multiple back-to-back captures occurring > + * before the Xe can read the data out and process it > + */ > +#define GUC_CAPTURE_OVERBUFFER_MULTIPLIER 3 > + > +static void check_guc_capture_size(struct xe_guc *guc) > +{ > + int capture_size = guc_capture_output_size_est(guc); > + int spare_size = capture_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER; > + u32 buffer_size = xe_guc_log_section_size_capture(&guc->log); > + > + /* > + * NOTE: capture_size is much smaller than the capture region allocation (DG2: <80K vs 1MB) > + * Additionally, its based on space needed to fit all engines getting reset at once > + * within the same G2H handler task slot. This is very unlikely. However, if GuC really > + * does run out of space for whatever reason, we will see an separate warning message > + * when processing the G2H event capture-notification, search for: > + * xe_guc_STATE_CAPTURE_EVENT_STATUS_NOSPACE. > + */ please try to wrap comments at 80 (it's already multi line) > + if (capture_size < 0) > + xe_gt_warn(guc_to_gt(guc), "Failed to calculate error state capture buffer minimum size: %d!\n", > + capture_size);> + if (capture_size > buffer_size) > + xe_gt_warn(guc_to_gt(guc), "Error state capture buffer maybe small: %d < %d\n", > + buffer_size, capture_size); do we really need those both messages at warn level ? > + else if (spare_size > buffer_size) > + xe_gt_dbg(guc_to_gt(guc), "Error state capture buffer lacks spare size: %d < %d (min = %d)\n", > + buffer_size, spare_size, capture_size); > +} > + > int xe_guc_capture_init(struct xe_guc *guc) > { > guc->capture = drmm_kzalloc(guc_to_drm(guc), sizeof(*guc->capture), GFP_KERNEL); > @@ -499,5 +575,6 @@ int xe_guc_capture_init(struct xe_guc *guc) > > guc->capture->reglists = guc_capture_get_device_reglist(guc); > > + check_guc_capture_size(guc); > return 0; > } > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h > index 04b03c398191..908298791c93 100644 > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h > @@ -250,6 +250,54 @@ struct guc_engine_usage { > struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; > } __packed; > > +/* GuC logging structures */ > + > +enum guc_log_buffer_type { > + GUC_DEBUG_LOG_BUFFER, > + GUC_CRASH_DUMP_LOG_BUFFER, > + GUC_CAPTURE_LOG_BUFFER, > + GUC_MAX_LOG_BUFFER this last enumerator is not real buffer type, so better at least name it in a different way (at least add __ prefix? or best, since it looks like ABI definitions, just move it out of the enum to benefit from compiler checks that John prefers: enum guc_log_buffer_type { GUC_LOG_BUFFER_DEBUG = 0, GUC_LOG_BUFFER_CRASH_DUMP = 1, GUC_LOG_BUFFER_CAPTURE_LOG = 2, }; #define NUM_GUC_LOG_BUFFER_TYPES 3 > +}; > + > +/* > + * struct guc_log_buffer_state - GuC log buffer state this is not a kernel-doc format, intentional or typo ? > + * > + * Below state structure is used for coordination of retrieval of GuC firmware > + * logs. Separate state is maintained for each log buffer type. > + * read_ptr points to the location where Xe read last in log buffer and > + * is read only for GuC firmware. write_ptr is incremented by GuC with number > + * of bytes written for each log entry and is read only for Xe. > + * When any type of log buffer becomes half full, GuC sends a flush interrupt. > + * GuC firmware expects that while it is writing to 2nd half of the buffer, > + * first half would get consumed by Host and then get a flush completed > + * acknowledgment from Host, so that it does not end up doing any overwrite > + * causing loss of logs. So when buffer gets half filled & Xe has requested > + * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr > + * to the value of write_ptr and raise the interrupt. > + * On receiving the interrupt Xe should read the buffer, clear flush_to_file > + * field and also update read_ptr with the value of sample_write_ptr, before > + * sending an acknowledgment to GuC. marker & version fields are for internal > + * usage of GuC and opaque to Xe. buffer_full_cnt field is incremented every > + * time GuC detects the log buffer overflow. > + */ > +struct guc_log_buffer_state { > + u32 marker[2]; > + u32 read_ptr; > + u32 write_ptr; > + u32 size; > + u32 sampled_write_ptr; > + u32 wrap_offset; > + union { > + struct { > + u32 flush_to_file:1; > + u32 buffer_full_cnt:4; > + u32 reserved:27; > + }; > + u32 flags; > + }; > + u32 version; > +} __packed; this looks like a pure GuC ABI definition, maybe it deserves to be placed in separate xe/abi/guc_log_abi.h file ? > + > /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ > enum xe_guc_recv_message { > XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), > diff --git a/drivers/gpu/drm/xe/xe_guc_log.c b/drivers/gpu/drm/xe/xe_guc_log.c > index a37ee3419428..c97fc4d57168 100644 > --- a/drivers/gpu/drm/xe/xe_guc_log.c > +++ b/drivers/gpu/drm/xe/xe_guc_log.c > @@ -9,9 +9,30 @@ > > #include "xe_bo.h" > #include "xe_gt.h" > +#include "xe_gt_printk.h" > #include "xe_map.h" > #include "xe_module.h" > > +#define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \ > + __stringify(x), (long)(x)) i915'ish is forbidden in Xe you should be able to use xe_[gt_]assert() instead > + > +#define GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE CRASH_BUFFER_SIZE > +#define GUC_LOG_DEFAULT_DEBUG_BUFFER_SIZE DEBUG_BUFFER_SIZE > +#define GUC_LOG_DEFAULT_CAPTURE_BUFFER_SIZE CAPTURE_BUFFER_SIZE > + > +struct guc_log_section { > + u32 max; > + u32 flag; > + u32 default_val; > + const char *name; > +}; > + > +static struct xe_gt * > +guc_to_gt(struct xe_guc *guc) don't duplicate the code, this is already defined in xe_guc.h > +{ > + return container_of(guc, struct xe_gt, uc.guc); > +} > + > static struct xe_gt * > log_to_gt(struct xe_guc_log *log) > { > @@ -96,3 +117,161 @@ int xe_guc_log_init(struct xe_guc_log *log) > > return 0; > } > + > +static void _guc_log_init_sizes(struct xe_guc_log *log) > +{ > + struct xe_guc *guc = log_to_guc(log); > + static const struct guc_log_section sections[GUC_LOG_SECTIONS_LIMIT] = { > + { > + GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT, > + GUC_LOG_LOG_ALLOC_UNITS, > + GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE, > + "crash dump" > + }, > + { > + GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT, > + GUC_LOG_LOG_ALLOC_UNITS, > + GUC_LOG_DEFAULT_DEBUG_BUFFER_SIZE, > + "debug", > + }, > + { > + GUC_LOG_CAPTURE_MASK >> GUC_LOG_CAPTURE_SHIFT, > + GUC_LOG_CAPTURE_ALLOC_UNITS, > + GUC_LOG_DEFAULT_CAPTURE_BUFFER_SIZE, > + "capture", > + } > + }; > + int i; > + > + for (i = 0; i < GUC_LOG_SECTIONS_LIMIT; i++) > + log->sizes[i].bytes = sections[i].default_val; > + > + /* If debug size > 1MB then bump default crash size to keep the same units */ > + if (log->sizes[GUC_LOG_SECTIONS_DEBUG].bytes >= SZ_1M && > + GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE < SZ_1M) > + log->sizes[GUC_LOG_SECTIONS_CRASH].bytes = SZ_1M; > + > + /* Prepare the GuC API structure fields: */ > + for (i = 0; i < GUC_LOG_SECTIONS_LIMIT; i++) { > + /* Convert to correct units */ > + if ((log->sizes[i].bytes % SZ_1M) == 0) { > + log->sizes[i].units = SZ_1M; > + log->sizes[i].flag = sections[i].flag; > + } else { > + log->sizes[i].units = SZ_4K; > + log->sizes[i].flag = 0; > + } > + > + if (!IS_ALIGNED(log->sizes[i].bytes, log->sizes[i].units)) > + xe_gt_err(guc_to_gt(guc), "Mis-aligned log %s size: 0x%X vs 0x%X!\n", > + sections[i].name, log->sizes[i].bytes, log->sizes[i].units); this 'mis-alignment' issue seems to be due to our coding fault so we should use xe_gt_assert() to catch that > + log->sizes[i].count = log->sizes[i].bytes / log->sizes[i].units; > + > + if (!log->sizes[i].count) { > + xe_gt_err(guc_to_gt(guc), "Zero log %s size!\n", sections[i].name); > + } else { > + /* Size is +1 unit */ > + log->sizes[i].count--; > + } > + > + /* Clip to field size */ > + if (log->sizes[i].count > sections[i].max) { > + xe_gt_err(guc_to_gt(guc), "log %s size too large: %d vs %d!\n", > + sections[i].name, log->sizes[i].count + 1, sections[i].max + 1); > + log->sizes[i].count = sections[i].max; > + } > + } > + > + if (log->sizes[GUC_LOG_SECTIONS_CRASH].units != log->sizes[GUC_LOG_SECTIONS_DEBUG].units) { > + xe_gt_err(guc_to_gt(guc), "Unit mismatch for crash and debug sections: %d vs %d!\n", > + log->sizes[GUC_LOG_SECTIONS_CRASH].units, > + log->sizes[GUC_LOG_SECTIONS_DEBUG].units); > + log->sizes[GUC_LOG_SECTIONS_CRASH].units = log->sizes[GUC_LOG_SECTIONS_DEBUG].units; > + log->sizes[GUC_LOG_SECTIONS_CRASH].count = 0; > + } > + > + log->sizes_initialised = true; > +} > + > +static void guc_log_init_sizes(struct xe_guc_log *log) > +{ > + if (log->sizes_initialised) > + return; > + > + _guc_log_init_sizes(log); > +} > + > +static u32 xe_guc_log_section_size_crash(struct xe_guc_log *log) > +{ > + guc_log_init_sizes(log); > + > + return log->sizes[GUC_LOG_SECTIONS_CRASH].bytes; > +} > + > +static u32 xe_guc_log_section_size_debug(struct xe_guc_log *log) > +{ > + guc_log_init_sizes(log); > + > + return log->sizes[GUC_LOG_SECTIONS_DEBUG].bytes; > +} > + add kernel-doc for public functions > +u32 xe_guc_log_section_size_capture(struct xe_guc_log *log) > +{ > + guc_log_init_sizes(log); > + > + return log->sizes[GUC_LOG_SECTIONS_CAPTURE].bytes; > +} > + > +bool xe_guc_check_log_buf_overflow(struct xe_guc_log *log, enum guc_log_buffer_type type, > + unsigned int full_cnt) > +{ > + unsigned int prev_full_cnt = log->stats[type].sampled_overflow; > + bool overflow = false; > + > + if (full_cnt != prev_full_cnt) { > + overflow = true; > + > + log->stats[type].overflow = full_cnt; > + log->stats[type].sampled_overflow += full_cnt - prev_full_cnt; > + > + if (full_cnt < prev_full_cnt) { > + /* buffer_full_cnt is a 4 bit counter */ > + log->stats[type].sampled_overflow += 16; > + } > + xe_gt_notice_ratelimited(log_to_gt(log), "log buffer overflow\n"); > + } > + > + return overflow; > +} > + > +unsigned int xe_guc_get_log_buffer_size(struct xe_guc_log *log, > + enum guc_log_buffer_type type) > +{ > + switch (type) { > + case GUC_DEBUG_LOG_BUFFER: > + return xe_guc_log_section_size_debug(log); > + case GUC_CRASH_DUMP_LOG_BUFFER: > + return xe_guc_log_section_size_crash(log); > + case GUC_CAPTURE_LOG_BUFFER: > + return xe_guc_log_section_size_capture(log); > + default: > + MISSING_CASE(type); there should be no need for 'default' case if you properly define your enum type > + } > + > + return 0; > +} > + > +size_t xe_guc_get_log_buffer_offset(struct xe_guc_log *log, > + enum guc_log_buffer_type type) > +{ > + enum guc_log_buffer_type i; > + size_t offset = PAGE_SIZE;/* for the log_buffer_states */ > + > + for (i = GUC_DEBUG_LOG_BUFFER; i < GUC_MAX_LOG_BUFFER; ++i) { > + if (i == type) > + break; > + offset += xe_guc_get_log_buffer_size(log, i); > + } > + > + return offset; > +} > diff --git a/drivers/gpu/drm/xe/xe_guc_log.h b/drivers/gpu/drm/xe/xe_guc_log.h > index 2d25ab28b4b3..de55de4052ca 100644 > --- a/drivers/gpu/drm/xe/xe_guc_log.h > +++ b/drivers/gpu/drm/xe/xe_guc_log.h > @@ -7,6 +7,7 @@ > #define _XE_GUC_LOG_H_ > > #include "xe_guc_log_types.h" > +#include "xe_guc_types.h" > > struct drm_printer; > > @@ -17,7 +18,7 @@ struct drm_printer; > #else > #define CRASH_BUFFER_SIZE SZ_8K > #define DEBUG_BUFFER_SIZE SZ_64K > -#define CAPTURE_BUFFER_SIZE SZ_16K > +#define CAPTURE_BUFFER_SIZE SZ_1M > #endif > /* > * While we're using plain log level in i915, GuC controls are much more... > @@ -36,6 +37,11 @@ struct drm_printer; > #define GUC_VERBOSITY_TO_LOG_LEVEL(x) ((x) + 2) > #define GUC_LOG_LEVEL_MAX GUC_VERBOSITY_TO_LOG_LEVEL(GUC_LOG_VERBOSITY_MAX) > > +static inline struct xe_guc *log_to_guc(struct xe_guc_log *log) > +{ > + return container_of(log, struct xe_guc, log); > +} > + > int xe_guc_log_init(struct xe_guc_log *log); > void xe_guc_log_print(struct xe_guc_log *log, struct drm_printer *p); > > @@ -45,4 +51,13 @@ xe_guc_log_get_level(struct xe_guc_log *log) > return log->level; > } > > +u32 xe_guc_log_section_size_capture(struct xe_guc_log *log); > + > +bool xe_guc_check_log_buf_overflow(struct xe_guc_log *log, > + enum guc_log_buffer_type type, > + unsigned int full_cnt); > +unsigned int xe_guc_get_log_buffer_size(struct xe_guc_log *log, > + enum guc_log_buffer_type type); > +size_t xe_guc_get_log_buffer_offset(struct xe_guc_log *log, > + enum guc_log_buffer_type type); missing space ? > #endif > diff --git a/drivers/gpu/drm/xe/xe_guc_log_types.h b/drivers/gpu/drm/xe/xe_guc_log_types.h > index 125080d138a7..3d4bf2a73102 100644 > --- a/drivers/gpu/drm/xe/xe_guc_log_types.h > +++ b/drivers/gpu/drm/xe/xe_guc_log_types.h > @@ -7,6 +7,14 @@ > #define _XE_GUC_LOG_TYPES_H_ > > #include <linux/types.h> > +#include "xe_guc_fwif.h" > + > +enum { > + GUC_LOG_SECTIONS_CRASH, > + GUC_LOG_SECTIONS_DEBUG, > + GUC_LOG_SECTIONS_CAPTURE, > + GUC_LOG_SECTIONS_LIMIT > +}; what's the relation with enum guc_log_buffer_type ? seems to be identical > > struct xe_bo; > > @@ -18,6 +26,22 @@ struct xe_guc_log { > u32 level; > /** @bo: XE BO for GuC log */ > struct xe_bo *bo; > + > + /* Allocation settings */ > + struct { > + s32 bytes; /* Size in bytes */ > + s32 units; /* GuC API units - 1MB or 4KB */ > + s32 count; /* Number of API units */ why signed ? > + u32 flag; /* GuC API units flag */ > + } sizes[GUC_LOG_SECTIONS_LIMIT]; > + bool sizes_initialised; > + > + /* logging related stats */ > + struct { > + u32 sampled_overflow; > + u32 overflow; > + u32 flush; > + } stats[GUC_MAX_LOG_BUFFER]; > }; > > #endif ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v9 3/4] drm/xe/guc: Add capture size check in GuC log buffer 2024-06-14 12:13 ` Michal Wajdeczko @ 2024-06-19 19:44 ` Dong, Zhanjun 2024-06-19 22:28 ` Michal Wajdeczko 0 siblings, 1 reply; 24+ messages in thread From: Dong, Zhanjun @ 2024-06-19 19:44 UTC (permalink / raw) To: Michal Wajdeczko, intel-xe, John Harrison Please see my comments inline below. Zhanjun On 2024-06-14 8:13 a.m., Michal Wajdeczko wrote: > > > On 07.06.2024 02:07, Zhanjun Dong wrote: >> The capture-nodes is included in GuC log buffer, add the size check >> for capture region in the whole GuC log buffer. >> Add capture output size check before allocating the shared buffer. >> >> Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> >> --- >> drivers/gpu/drm/xe/xe_gt_printk.h | 3 + >> drivers/gpu/drm/xe/xe_guc_capture.c | 77 +++++++++++ >> drivers/gpu/drm/xe/xe_guc_fwif.h | 48 +++++++ >> drivers/gpu/drm/xe/xe_guc_log.c | 179 ++++++++++++++++++++++++++ >> drivers/gpu/drm/xe/xe_guc_log.h | 17 ++- >> drivers/gpu/drm/xe/xe_guc_log_types.h | 24 ++++ >> 6 files changed, 347 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h >> index c2b004d3f48e..107360edfcd6 100644 >> --- a/drivers/gpu/drm/xe/xe_gt_printk.h >> +++ b/drivers/gpu/drm/xe/xe_gt_printk.h >> @@ -22,6 +22,9 @@ >> #define xe_gt_notice(_gt, _fmt, ...) \ >> xe_gt_printk((_gt), notice, _fmt, ##__VA_ARGS__) >> >> +#define xe_gt_notice_ratelimited(_gt, _fmt, ...) \ >> + xe_gt_printk((_gt), err_ratelimited, _fmt, ##__VA_ARGS__) > > you are mixing here 'notice' with 'err' Thanks for point out > >> + >> #define xe_gt_info(_gt, _fmt, ...) \ >> xe_gt_printk((_gt), info, _fmt, ##__VA_ARGS__) >> >> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c >> index 951408846c97..0c90def290de 100644 >> --- a/drivers/gpu/drm/xe/xe_guc_capture.c >> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c >> @@ -21,6 +21,7 @@ >> #include "xe_gt_mcr.h" >> #include "xe_gt_printk.h" >> #include "xe_guc.h" >> +#include "xe_guc_ads.h" >> #include "xe_guc_capture.h" >> #include "xe_guc_capture_fwif.h" >> #include "xe_guc_ct.h" >> @@ -491,6 +492,81 @@ xe_guc_capture_getnullheader(struct xe_guc *guc, void **outptr, size_t *size) >> return 0; >> } >> >> +static int >> +guc_capture_output_size_est(struct xe_guc *guc) >> +{ >> + struct xe_gt *gt = guc_to_gt(guc); >> + struct xe_hw_engine *hwe; >> + enum xe_hw_engine_id id; >> + >> + int capture_size = 0; >> + size_t tmp = 0; >> + >> + if (!guc->capture) >> + return -ENODEV; >> + >> + /* >> + * If every single engine-instance suffered a failure in quick succession but >> + * were all unrelated, then a burst of multiple error-capture events would dump >> + * registers for every one engine instance, one at a time. In this case, GuC >> + * would even dump the global-registers repeatedly. >> + * >> + * For each engine instance, there would be 1 x guc_state_capture_group_t output >> + * followed by 3 x guc_state_capture_t lists. The latter is how the register >> + * dumps are split across different register types (where the '3' are global vs class >> + * vs instance). >> + */ >> + for_each_hw_engine(hwe, gt, id) { >> + capture_size += sizeof(struct guc_state_capture_group_header_t) + >> + (3 * sizeof(struct guc_state_capture_header_t)); >> + >> + if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &tmp, true)) >> + capture_size += tmp; >> + >> + if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, >> + hwe->class, &tmp, true)) { >> + capture_size += tmp; >> + } >> + if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, >> + hwe->class, &tmp, true)) { >> + capture_size += tmp; >> + } >> + } >> + >> + return capture_size; >> +} >> + >> +/* >> + * Add on a 3x multiplier to allow for multiple back-to-back captures occurring >> + * before the Xe can read the data out and process it >> + */ >> +#define GUC_CAPTURE_OVERBUFFER_MULTIPLIER 3 >> + >> +static void check_guc_capture_size(struct xe_guc *guc) >> +{ >> + int capture_size = guc_capture_output_size_est(guc); >> + int spare_size = capture_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER; >> + u32 buffer_size = xe_guc_log_section_size_capture(&guc->log); >> + >> + /* >> + * NOTE: capture_size is much smaller than the capture region allocation (DG2: <80K vs 1MB) >> + * Additionally, its based on space needed to fit all engines getting reset at once >> + * within the same G2H handler task slot. This is very unlikely. However, if GuC really >> + * does run out of space for whatever reason, we will see an separate warning message >> + * when processing the G2H event capture-notification, search for: >> + * xe_guc_STATE_CAPTURE_EVENT_STATUS_NOSPACE. >> + */ > > please try to wrap comments at 80 (it's already multi line) > >> + if (capture_size < 0) >> + xe_gt_warn(guc_to_gt(guc), "Failed to calculate error state capture buffer minimum size: %d!\n", >> + capture_size);> + if (capture_size > buffer_size) >> + xe_gt_warn(guc_to_gt(guc), "Error state capture buffer maybe small: %d < %d\n", >> + buffer_size, capture_size); > > do we really need those both messages at warn level ? Will be changed to dbg level > >> + else if (spare_size > buffer_size) >> + xe_gt_dbg(guc_to_gt(guc), "Error state capture buffer lacks spare size: %d < %d (min = %d)\n", >> + buffer_size, spare_size, capture_size); >> +} >> + >> int xe_guc_capture_init(struct xe_guc *guc) >> { >> guc->capture = drmm_kzalloc(guc_to_drm(guc), sizeof(*guc->capture), GFP_KERNEL); >> @@ -499,5 +575,6 @@ int xe_guc_capture_init(struct xe_guc *guc) >> >> guc->capture->reglists = guc_capture_get_device_reglist(guc); >> >> + check_guc_capture_size(guc); >> return 0; >> } >> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h >> index 04b03c398191..908298791c93 100644 >> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h >> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h >> @@ -250,6 +250,54 @@ struct guc_engine_usage { >> struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; >> } __packed; >> >> +/* GuC logging structures */ >> + >> +enum guc_log_buffer_type { >> + GUC_DEBUG_LOG_BUFFER, >> + GUC_CRASH_DUMP_LOG_BUFFER, >> + GUC_CAPTURE_LOG_BUFFER, >> + GUC_MAX_LOG_BUFFER > > this last enumerator is not real buffer type, so better at least name it > in a different way (at least add __ prefix? > > or best, since it looks like ABI definitions, just move it out of the > enum to benefit from compiler checks that John prefers: > > enum guc_log_buffer_type { > GUC_LOG_BUFFER_DEBUG = 0, > GUC_LOG_BUFFER_CRASH_DUMP = 1, > GUC_LOG_BUFFER_CAPTURE_LOG = 2, > }; > #define NUM_GUC_LOG_BUFFER_TYPES 3 > Will changed to: /* GuC logging structures */ enum guc_log_buffer_type { GUC_DEBUG_LOG_BUFFER, GUC_CRASH_DUMP_LOG_BUFFER, GUC_CAPTURE_LOG_BUFFER, GUC_LOG_BUFFER_TYPE_MAX }; The empty line speprate real type vs MAX I would prefer to stay within the enum, which make add new type easier, the MAX will be updated by compiler automatically, no need to manually add 1 to NUM_xxx macro. >> +}; >> + >> +/* >> + * struct guc_log_buffer_state - GuC log buffer state > > this is not a kernel-doc format, intentional or typo ? > >> + * >> + * Below state structure is used for coordination of retrieval of GuC firmware >> + * logs. Separate state is maintained for each log buffer type. >> + * read_ptr points to the location where Xe read last in log buffer and >> + * is read only for GuC firmware. write_ptr is incremented by GuC with number >> + * of bytes written for each log entry and is read only for Xe. >> + * When any type of log buffer becomes half full, GuC sends a flush interrupt. >> + * GuC firmware expects that while it is writing to 2nd half of the buffer, >> + * first half would get consumed by Host and then get a flush completed >> + * acknowledgment from Host, so that it does not end up doing any overwrite >> + * causing loss of logs. So when buffer gets half filled & Xe has requested >> + * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr >> + * to the value of write_ptr and raise the interrupt. >> + * On receiving the interrupt Xe should read the buffer, clear flush_to_file >> + * field and also update read_ptr with the value of sample_write_ptr, before >> + * sending an acknowledgment to GuC. marker & version fields are for internal >> + * usage of GuC and opaque to Xe. buffer_full_cnt field is incremented every >> + * time GuC detects the log buffer overflow. >> + */ >> +struct guc_log_buffer_state { >> + u32 marker[2]; >> + u32 read_ptr; >> + u32 write_ptr; >> + u32 size; >> + u32 sampled_write_ptr; >> + u32 wrap_offset; >> + union { >> + struct { >> + u32 flush_to_file:1; >> + u32 buffer_full_cnt:4; >> + u32 reserved:27; >> + }; >> + u32 flags; >> + }; >> + u32 version; >> +} __packed; > > this looks like a pure GuC ABI definition, maybe it deserves to be > placed in separate xe/abi/guc_log_abi.h file ? ok, to be moved to _abi > >> + >> /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ >> enum xe_guc_recv_message { >> XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), >> diff --git a/drivers/gpu/drm/xe/xe_guc_log.c b/drivers/gpu/drm/xe/xe_guc_log.c >> index a37ee3419428..c97fc4d57168 100644 >> --- a/drivers/gpu/drm/xe/xe_guc_log.c >> +++ b/drivers/gpu/drm/xe/xe_guc_log.c >> @@ -9,9 +9,30 @@ >> >> #include "xe_bo.h" >> #include "xe_gt.h" >> +#include "xe_gt_printk.h" >> #include "xe_map.h" >> #include "xe_module.h" >> >> +#define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \ >> + __stringify(x), (long)(x)) > > i915'ish is forbidden in Xe > > you should be able to use xe_[gt_]assert() instead will do > >> + >> +#define GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE CRASH_BUFFER_SIZE >> +#define GUC_LOG_DEFAULT_DEBUG_BUFFER_SIZE DEBUG_BUFFER_SIZE >> +#define GUC_LOG_DEFAULT_CAPTURE_BUFFER_SIZE CAPTURE_BUFFER_SIZE >> + >> +struct guc_log_section { >> + u32 max; >> + u32 flag; >> + u32 default_val; >> + const char *name; >> +}; >> + >> +static struct xe_gt * >> +guc_to_gt(struct xe_guc *guc) > > don't duplicate the code, this is already defined in xe_guc.h > >> +{ >> + return container_of(guc, struct xe_gt, uc.guc); >> +} >> + >> static struct xe_gt * >> log_to_gt(struct xe_guc_log *log) >> { >> @@ -96,3 +117,161 @@ int xe_guc_log_init(struct xe_guc_log *log) >> >> return 0; >> } >> + >> +static void _guc_log_init_sizes(struct xe_guc_log *log) >> +{ >> + struct xe_guc *guc = log_to_guc(log); >> + static const struct guc_log_section sections[GUC_LOG_SECTIONS_LIMIT] = { >> + { >> + GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT, >> + GUC_LOG_LOG_ALLOC_UNITS, >> + GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE, >> + "crash dump" >> + }, >> + { >> + GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT, >> + GUC_LOG_LOG_ALLOC_UNITS, >> + GUC_LOG_DEFAULT_DEBUG_BUFFER_SIZE, >> + "debug", >> + }, >> + { >> + GUC_LOG_CAPTURE_MASK >> GUC_LOG_CAPTURE_SHIFT, >> + GUC_LOG_CAPTURE_ALLOC_UNITS, >> + GUC_LOG_DEFAULT_CAPTURE_BUFFER_SIZE, >> + "capture", >> + } >> + }; >> + int i; >> + >> + for (i = 0; i < GUC_LOG_SECTIONS_LIMIT; i++) >> + log->sizes[i].bytes = sections[i].default_val; >> + >> + /* If debug size > 1MB then bump default crash size to keep the same units */ >> + if (log->sizes[GUC_LOG_SECTIONS_DEBUG].bytes >= SZ_1M && >> + GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE < SZ_1M) >> + log->sizes[GUC_LOG_SECTIONS_CRASH].bytes = SZ_1M; >> + >> + /* Prepare the GuC API structure fields: */ >> + for (i = 0; i < GUC_LOG_SECTIONS_LIMIT; i++) { >> + /* Convert to correct units */ >> + if ((log->sizes[i].bytes % SZ_1M) == 0) { >> + log->sizes[i].units = SZ_1M; >> + log->sizes[i].flag = sections[i].flag; >> + } else { >> + log->sizes[i].units = SZ_4K; >> + log->sizes[i].flag = 0; >> + } >> + >> + if (!IS_ALIGNED(log->sizes[i].bytes, log->sizes[i].units)) >> + xe_gt_err(guc_to_gt(guc), "Mis-aligned log %s size: 0x%X vs 0x%X!\n", >> + sections[i].name, log->sizes[i].bytes, log->sizes[i].units); > > this 'mis-alignment' issue seems to be due to our coding fault so we > should use xe_gt_assert() to catch that good idea, will do xe_gt_assert_msg to have more info > >> + log->sizes[i].count = log->sizes[i].bytes / log->sizes[i].units; >> + >> + if (!log->sizes[i].count) { >> + xe_gt_err(guc_to_gt(guc), "Zero log %s size!\n", sections[i].name); >> + } else { >> + /* Size is +1 unit */ >> + log->sizes[i].count--; >> + } >> + >> + /* Clip to field size */ >> + if (log->sizes[i].count > sections[i].max) { >> + xe_gt_err(guc_to_gt(guc), "log %s size too large: %d vs %d!\n", >> + sections[i].name, log->sizes[i].count + 1, sections[i].max + 1); >> + log->sizes[i].count = sections[i].max; >> + } >> + } >> + >> + if (log->sizes[GUC_LOG_SECTIONS_CRASH].units != log->sizes[GUC_LOG_SECTIONS_DEBUG].units) { >> + xe_gt_err(guc_to_gt(guc), "Unit mismatch for crash and debug sections: %d vs %d!\n", >> + log->sizes[GUC_LOG_SECTIONS_CRASH].units, >> + log->sizes[GUC_LOG_SECTIONS_DEBUG].units); >> + log->sizes[GUC_LOG_SECTIONS_CRASH].units = log->sizes[GUC_LOG_SECTIONS_DEBUG].units; >> + log->sizes[GUC_LOG_SECTIONS_CRASH].count = 0; >> + } >> + >> + log->sizes_initialised = true; >> +} >> + >> +static void guc_log_init_sizes(struct xe_guc_log *log) >> +{ >> + if (log->sizes_initialised) >> + return; >> + >> + _guc_log_init_sizes(log); >> +} >> + >> +static u32 xe_guc_log_section_size_crash(struct xe_guc_log *log) >> +{ >> + guc_log_init_sizes(log); >> + >> + return log->sizes[GUC_LOG_SECTIONS_CRASH].bytes; >> +} >> + >> +static u32 xe_guc_log_section_size_debug(struct xe_guc_log *log) >> +{ >> + guc_log_init_sizes(log); >> + >> + return log->sizes[GUC_LOG_SECTIONS_DEBUG].bytes; >> +} >> + > > add kernel-doc for public functions > >> +u32 xe_guc_log_section_size_capture(struct xe_guc_log *log) >> +{ >> + guc_log_init_sizes(log); >> + >> + return log->sizes[GUC_LOG_SECTIONS_CAPTURE].bytes; >> +} >> + >> +bool xe_guc_check_log_buf_overflow(struct xe_guc_log *log, enum guc_log_buffer_type type, >> + unsigned int full_cnt) >> +{ >> + unsigned int prev_full_cnt = log->stats[type].sampled_overflow; >> + bool overflow = false; >> + >> + if (full_cnt != prev_full_cnt) { >> + overflow = true; >> + >> + log->stats[type].overflow = full_cnt; >> + log->stats[type].sampled_overflow += full_cnt - prev_full_cnt; >> + >> + if (full_cnt < prev_full_cnt) { >> + /* buffer_full_cnt is a 4 bit counter */ >> + log->stats[type].sampled_overflow += 16; >> + } >> + xe_gt_notice_ratelimited(log_to_gt(log), "log buffer overflow\n"); >> + } >> + >> + return overflow; >> +} >> + >> +unsigned int xe_guc_get_log_buffer_size(struct xe_guc_log *log, >> + enum guc_log_buffer_type type) >> +{ >> + switch (type) { >> + case GUC_DEBUG_LOG_BUFFER: >> + return xe_guc_log_section_size_debug(log); >> + case GUC_CRASH_DUMP_LOG_BUFFER: >> + return xe_guc_log_section_size_crash(log); >> + case GUC_CAPTURE_LOG_BUFFER: >> + return xe_guc_log_section_size_capture(log); >> + default: >> + MISSING_CASE(type); > > there should be no need for 'default' case if you properly define your > enum type Compiler could check static error, while 'default' here can cover run-time errors. I would prefer to have it for public funcitons. > >> + } >> + >> + return 0; >> +} >> + >> +size_t xe_guc_get_log_buffer_offset(struct xe_guc_log *log, >> + enum guc_log_buffer_type type) >> +{ >> + enum guc_log_buffer_type i; >> + size_t offset = PAGE_SIZE;/* for the log_buffer_states */ >> + >> + for (i = GUC_DEBUG_LOG_BUFFER; i < GUC_MAX_LOG_BUFFER; ++i) { >> + if (i == type) >> + break; >> + offset += xe_guc_get_log_buffer_size(log, i); >> + } >> + >> + return offset; >> +} >> diff --git a/drivers/gpu/drm/xe/xe_guc_log.h b/drivers/gpu/drm/xe/xe_guc_log.h >> index 2d25ab28b4b3..de55de4052ca 100644 >> --- a/drivers/gpu/drm/xe/xe_guc_log.h >> +++ b/drivers/gpu/drm/xe/xe_guc_log.h >> @@ -7,6 +7,7 @@ >> #define _XE_GUC_LOG_H_ >> >> #include "xe_guc_log_types.h" >> +#include "xe_guc_types.h" >> >> struct drm_printer; >> >> @@ -17,7 +18,7 @@ struct drm_printer; >> #else >> #define CRASH_BUFFER_SIZE SZ_8K >> #define DEBUG_BUFFER_SIZE SZ_64K >> -#define CAPTURE_BUFFER_SIZE SZ_16K >> +#define CAPTURE_BUFFER_SIZE SZ_1M >> #endif >> /* >> * While we're using plain log level in i915, GuC controls are much more... >> @@ -36,6 +37,11 @@ struct drm_printer; >> #define GUC_VERBOSITY_TO_LOG_LEVEL(x) ((x) + 2) >> #define GUC_LOG_LEVEL_MAX GUC_VERBOSITY_TO_LOG_LEVEL(GUC_LOG_VERBOSITY_MAX) >> >> +static inline struct xe_guc *log_to_guc(struct xe_guc_log *log) >> +{ >> + return container_of(log, struct xe_guc, log); >> +} >> + >> int xe_guc_log_init(struct xe_guc_log *log); >> void xe_guc_log_print(struct xe_guc_log *log, struct drm_printer *p); >> >> @@ -45,4 +51,13 @@ xe_guc_log_get_level(struct xe_guc_log *log) >> return log->level; >> } >> >> +u32 xe_guc_log_section_size_capture(struct xe_guc_log *log); >> + >> +bool xe_guc_check_log_buf_overflow(struct xe_guc_log *log, >> + enum guc_log_buffer_type type, >> + unsigned int full_cnt); >> +unsigned int xe_guc_get_log_buffer_size(struct xe_guc_log *log, >> + enum guc_log_buffer_type type); >> +size_t xe_guc_get_log_buffer_offset(struct xe_guc_log *log, >> + enum guc_log_buffer_type type); > > missing space ? > >> #endif >> diff --git a/drivers/gpu/drm/xe/xe_guc_log_types.h b/drivers/gpu/drm/xe/xe_guc_log_types.h >> index 125080d138a7..3d4bf2a73102 100644 >> --- a/drivers/gpu/drm/xe/xe_guc_log_types.h >> +++ b/drivers/gpu/drm/xe/xe_guc_log_types.h >> @@ -7,6 +7,14 @@ >> #define _XE_GUC_LOG_TYPES_H_ >> >> #include <linux/types.h> >> +#include "xe_guc_fwif.h" >> + >> +enum { >> + GUC_LOG_SECTIONS_CRASH, >> + GUC_LOG_SECTIONS_DEBUG, >> + GUC_LOG_SECTIONS_CAPTURE, >> + GUC_LOG_SECTIONS_LIMIT >> +}; > > what's the relation with enum guc_log_buffer_type ? > seems to be identical Right, also crash/debug is reversed to enum guc_log_buffer_type, but it is identical, will be removed. > >> >> struct xe_bo; >> >> @@ -18,6 +26,22 @@ struct xe_guc_log { >> u32 level; >> /** @bo: XE BO for GuC log */ >> struct xe_bo *bo; >> + >> + /* Allocation settings */ >> + struct { >> + s32 bytes; /* Size in bytes */ >> + s32 units; /* GuC API units - 1MB or 4KB */ >> + s32 count; /* Number of API units */ > > why signed ? Oh, all s32 here could be u32 > >> + u32 flag; /* GuC API units flag */ >> + } sizes[GUC_LOG_SECTIONS_LIMIT]; >> + bool sizes_initialised; >> + >> + /* logging related stats */ >> + struct { >> + u32 sampled_overflow; >> + u32 overflow; >> + u32 flush; >> + } stats[GUC_MAX_LOG_BUFFER]; >> }; >> >> #endif ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v9 3/4] drm/xe/guc: Add capture size check in GuC log buffer 2024-06-19 19:44 ` Dong, Zhanjun @ 2024-06-19 22:28 ` Michal Wajdeczko 2024-06-19 22:56 ` Dong, Zhanjun 0 siblings, 1 reply; 24+ messages in thread From: Michal Wajdeczko @ 2024-06-19 22:28 UTC (permalink / raw) To: Dong, Zhanjun, intel-xe, John Harrison On 19.06.2024 21:44, Dong, Zhanjun wrote: > Please see my comments inline below. > > Zhanjun > > On 2024-06-14 8:13 a.m., Michal Wajdeczko wrote: >> >> >> On 07.06.2024 02:07, Zhanjun Dong wrote: >>> The capture-nodes is included in GuC log buffer, add the size check >>> for capture region in the whole GuC log buffer. >>> Add capture output size check before allocating the shared buffer. >>> >>> Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> >>> --- >>> drivers/gpu/drm/xe/xe_gt_printk.h | 3 + >>> drivers/gpu/drm/xe/xe_guc_capture.c | 77 +++++++++++ >>> drivers/gpu/drm/xe/xe_guc_fwif.h | 48 +++++++ >>> drivers/gpu/drm/xe/xe_guc_log.c | 179 ++++++++++++++++++++++++++ >>> drivers/gpu/drm/xe/xe_guc_log.h | 17 ++- >>> drivers/gpu/drm/xe/xe_guc_log_types.h | 24 ++++ >>> 6 files changed, 347 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h >>> b/drivers/gpu/drm/xe/xe_gt_printk.h >>> index c2b004d3f48e..107360edfcd6 100644 >>> --- a/drivers/gpu/drm/xe/xe_gt_printk.h >>> +++ b/drivers/gpu/drm/xe/xe_gt_printk.h >>> @@ -22,6 +22,9 @@ >>> #define xe_gt_notice(_gt, _fmt, ...) \ >>> xe_gt_printk((_gt), notice, _fmt, ##__VA_ARGS__) >>> +#define xe_gt_notice_ratelimited(_gt, _fmt, ...) \ >>> + xe_gt_printk((_gt), err_ratelimited, _fmt, ##__VA_ARGS__) >> >> you are mixing here 'notice' with 'err' > Thanks for point out > >> >>> + >>> #define xe_gt_info(_gt, _fmt, ...) \ >>> xe_gt_printk((_gt), info, _fmt, ##__VA_ARGS__) >>> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c >>> b/drivers/gpu/drm/xe/xe_guc_capture.c >>> index 951408846c97..0c90def290de 100644 >>> --- a/drivers/gpu/drm/xe/xe_guc_capture.c >>> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c >>> @@ -21,6 +21,7 @@ >>> #include "xe_gt_mcr.h" >>> #include "xe_gt_printk.h" >>> #include "xe_guc.h" >>> +#include "xe_guc_ads.h" >>> #include "xe_guc_capture.h" >>> #include "xe_guc_capture_fwif.h" >>> #include "xe_guc_ct.h" >>> @@ -491,6 +492,81 @@ xe_guc_capture_getnullheader(struct xe_guc *guc, >>> void **outptr, size_t *size) >>> return 0; >>> } >>> +static int >>> +guc_capture_output_size_est(struct xe_guc *guc) >>> +{ >>> + struct xe_gt *gt = guc_to_gt(guc); >>> + struct xe_hw_engine *hwe; >>> + enum xe_hw_engine_id id; >>> + >>> + int capture_size = 0; >>> + size_t tmp = 0; >>> + >>> + if (!guc->capture) >>> + return -ENODEV; >>> + >>> + /* >>> + * If every single engine-instance suffered a failure in quick >>> succession but >>> + * were all unrelated, then a burst of multiple error-capture >>> events would dump >>> + * registers for every one engine instance, one at a time. In >>> this case, GuC >>> + * would even dump the global-registers repeatedly. >>> + * >>> + * For each engine instance, there would be 1 x >>> guc_state_capture_group_t output >>> + * followed by 3 x guc_state_capture_t lists. The latter is how >>> the register >>> + * dumps are split across different register types (where the >>> '3' are global vs class >>> + * vs instance). >>> + */ >>> + for_each_hw_engine(hwe, gt, id) { >>> + capture_size += sizeof(struct >>> guc_state_capture_group_header_t) + >>> + (3 * sizeof(struct guc_state_capture_header_t)); >>> + >>> + if (!guc_capture_getlistsize(guc, 0, >>> GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &tmp, true)) >>> + capture_size += tmp; >>> + >>> + if (!guc_capture_getlistsize(guc, 0, >>> GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, >>> + hwe->class, &tmp, true)) { >>> + capture_size += tmp; >>> + } >>> + if (!guc_capture_getlistsize(guc, 0, >>> GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, >>> + hwe->class, &tmp, true)) { >>> + capture_size += tmp; >>> + } >>> + } >>> + >>> + return capture_size; >>> +} >>> + >>> +/* >>> + * Add on a 3x multiplier to allow for multiple back-to-back >>> captures occurring >>> + * before the Xe can read the data out and process it >>> + */ >>> +#define GUC_CAPTURE_OVERBUFFER_MULTIPLIER 3 >>> + >>> +static void check_guc_capture_size(struct xe_guc *guc) >>> +{ >>> + int capture_size = guc_capture_output_size_est(guc); >>> + int spare_size = capture_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER; >>> + u32 buffer_size = xe_guc_log_section_size_capture(&guc->log); >>> + >>> + /* >>> + * NOTE: capture_size is much smaller than the capture region >>> allocation (DG2: <80K vs 1MB) >>> + * Additionally, its based on space needed to fit all engines >>> getting reset at once >>> + * within the same G2H handler task slot. This is very unlikely. >>> However, if GuC really >>> + * does run out of space for whatever reason, we will see an >>> separate warning message >>> + * when processing the G2H event capture-notification, search for: >>> + * xe_guc_STATE_CAPTURE_EVENT_STATUS_NOSPACE. >>> + */ >> >> please try to wrap comments at 80 (it's already multi line) >> >>> + if (capture_size < 0) >>> + xe_gt_warn(guc_to_gt(guc), "Failed to calculate error state >>> capture buffer minimum size: %d!\n", >>> + capture_size);> + if (capture_size > buffer_size) >>> + xe_gt_warn(guc_to_gt(guc), "Error state capture buffer maybe >>> small: %d < %d\n", >>> + buffer_size, capture_size); >> >> do we really need those both messages at warn level ? > Will be changed to dbg level > >> >>> + else if (spare_size > buffer_size) >>> + xe_gt_dbg(guc_to_gt(guc), "Error state capture buffer lacks >>> spare size: %d < %d (min = %d)\n", >>> + buffer_size, spare_size, capture_size); >>> +} >>> + >>> int xe_guc_capture_init(struct xe_guc *guc) >>> { >>> guc->capture = drmm_kzalloc(guc_to_drm(guc), >>> sizeof(*guc->capture), GFP_KERNEL); >>> @@ -499,5 +575,6 @@ int xe_guc_capture_init(struct xe_guc *guc) >>> guc->capture->reglists = guc_capture_get_device_reglist(guc); >>> + check_guc_capture_size(guc); >>> return 0; >>> } >>> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h >>> b/drivers/gpu/drm/xe/xe_guc_fwif.h >>> index 04b03c398191..908298791c93 100644 >>> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h >>> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h >>> @@ -250,6 +250,54 @@ struct guc_engine_usage { >>> struct guc_engine_usage_record >>> engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; >>> } __packed; >>> +/* GuC logging structures */ >>> + >>> +enum guc_log_buffer_type { >>> + GUC_DEBUG_LOG_BUFFER, >>> + GUC_CRASH_DUMP_LOG_BUFFER, >>> + GUC_CAPTURE_LOG_BUFFER, >>> + GUC_MAX_LOG_BUFFER >> >> this last enumerator is not real buffer type, so better at least name it >> in a different way (at least add __ prefix? >> >> or best, since it looks like ABI definitions, just move it out of the >> enum to benefit from compiler checks that John prefers: >> >> enum guc_log_buffer_type { >> GUC_LOG_BUFFER_DEBUG = 0, >> GUC_LOG_BUFFER_CRASH_DUMP = 1, >> GUC_LOG_BUFFER_CAPTURE_LOG = 2, >> }; >> #define NUM_GUC_LOG_BUFFER_TYPES 3 >> > Will changed to: > /* GuC logging structures */ > enum guc_log_buffer_type { > GUC_DEBUG_LOG_BUFFER, > GUC_CRASH_DUMP_LOG_BUFFER, > GUC_CAPTURE_LOG_BUFFER, > > GUC_LOG_BUFFER_TYPE_MAX > }; > The empty line speprate real type vs MAX empty line is not enough to let the compiler see the difference between real _type_ and _max_ definition > I would prefer to stay within the enum, which make add new type easier, > the MAX will be updated by compiler automatically, no need to manually > add 1 to NUM_xxx macro. but this is (or should be) a stable ABI so we shouldn't rely on the compiler to automatically making any changes to any of these defs. and as of today we have exactly 3 types defined as: GUC_LOG_BUFFER_DEBUG = 0, GUC_LOG_BUFFER_CRASH_DUMP = 1, GUC_LOG_BUFFER_CAPTURE_LOG = 2, so if you want to use enum to get some help from the compiler, like to check that in your implementation you are not using bad types, then there should be no other enumerators in this enum, as otherwise you kill that feature also note that your approach will not work if for some reason the new type will be defined as something different than 3, like: GUC_LOG_BUFFER_FUTURE = 345 so while will have 4 TYPES, your automatic MAX will be 346, making it almost useless > >>> +}; >>> + >>> +/* >>> + * struct guc_log_buffer_state - GuC log buffer state >> >> this is not a kernel-doc format, intentional or typo ? >> >>> + * >>> + * Below state structure is used for coordination of retrieval of >>> GuC firmware >>> + * logs. Separate state is maintained for each log buffer type. >>> + * read_ptr points to the location where Xe read last in log buffer and >>> + * is read only for GuC firmware. write_ptr is incremented by GuC >>> with number >>> + * of bytes written for each log entry and is read only for Xe. >>> + * When any type of log buffer becomes half full, GuC sends a flush >>> interrupt. >>> + * GuC firmware expects that while it is writing to 2nd half of the >>> buffer, >>> + * first half would get consumed by Host and then get a flush completed >>> + * acknowledgment from Host, so that it does not end up doing any >>> overwrite >>> + * causing loss of logs. So when buffer gets half filled & Xe has >>> requested >>> + * for interrupt, GuC will set flush_to_file field, set the >>> sampled_write_ptr >>> + * to the value of write_ptr and raise the interrupt. >>> + * On receiving the interrupt Xe should read the buffer, clear >>> flush_to_file >>> + * field and also update read_ptr with the value of >>> sample_write_ptr, before >>> + * sending an acknowledgment to GuC. marker & version fields are for >>> internal >>> + * usage of GuC and opaque to Xe. buffer_full_cnt field is >>> incremented every >>> + * time GuC detects the log buffer overflow. >>> + */ >>> +struct guc_log_buffer_state { >>> + u32 marker[2]; >>> + u32 read_ptr; >>> + u32 write_ptr; >>> + u32 size; >>> + u32 sampled_write_ptr; >>> + u32 wrap_offset; >>> + union { >>> + struct { >>> + u32 flush_to_file:1; >>> + u32 buffer_full_cnt:4; >>> + u32 reserved:27; >>> + }; >>> + u32 flags; >>> + }; >>> + u32 version; >>> +} __packed; >> >> this looks like a pure GuC ABI definition, maybe it deserves to be >> placed in separate xe/abi/guc_log_abi.h file ? > ok, to be moved to _abi > >> >>> + >>> /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ >>> enum xe_guc_recv_message { >>> XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), >>> diff --git a/drivers/gpu/drm/xe/xe_guc_log.c >>> b/drivers/gpu/drm/xe/xe_guc_log.c >>> index a37ee3419428..c97fc4d57168 100644 >>> --- a/drivers/gpu/drm/xe/xe_guc_log.c >>> +++ b/drivers/gpu/drm/xe/xe_guc_log.c >>> @@ -9,9 +9,30 @@ >>> #include "xe_bo.h" >>> #include "xe_gt.h" >>> +#include "xe_gt_printk.h" >>> #include "xe_map.h" >>> #include "xe_module.h" >>> +#define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \ >>> + __stringify(x), (long)(x)) >> >> i915'ish is forbidden in Xe >> >> you should be able to use xe_[gt_]assert() instead > will do > >> >>> + >>> +#define GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE CRASH_BUFFER_SIZE >>> +#define GUC_LOG_DEFAULT_DEBUG_BUFFER_SIZE DEBUG_BUFFER_SIZE >>> +#define GUC_LOG_DEFAULT_CAPTURE_BUFFER_SIZE CAPTURE_BUFFER_SIZE >>> + >>> +struct guc_log_section { >>> + u32 max; >>> + u32 flag; >>> + u32 default_val; >>> + const char *name; >>> +}; >>> + >>> +static struct xe_gt * >>> +guc_to_gt(struct xe_guc *guc) >> >> don't duplicate the code, this is already defined in xe_guc.h >> >>> +{ >>> + return container_of(guc, struct xe_gt, uc.guc); >>> +} >>> + >>> static struct xe_gt * >>> log_to_gt(struct xe_guc_log *log) >>> { >>> @@ -96,3 +117,161 @@ int xe_guc_log_init(struct xe_guc_log *log) >>> return 0; >>> } >>> + >>> +static void _guc_log_init_sizes(struct xe_guc_log *log) >>> +{ >>> + struct xe_guc *guc = log_to_guc(log); >>> + static const struct guc_log_section >>> sections[GUC_LOG_SECTIONS_LIMIT] = { >>> + { >>> + GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT, >>> + GUC_LOG_LOG_ALLOC_UNITS, >>> + GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE, >>> + "crash dump" >>> + }, >>> + { >>> + GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT, >>> + GUC_LOG_LOG_ALLOC_UNITS, >>> + GUC_LOG_DEFAULT_DEBUG_BUFFER_SIZE, >>> + "debug", >>> + }, >>> + { >>> + GUC_LOG_CAPTURE_MASK >> GUC_LOG_CAPTURE_SHIFT, >>> + GUC_LOG_CAPTURE_ALLOC_UNITS, >>> + GUC_LOG_DEFAULT_CAPTURE_BUFFER_SIZE, >>> + "capture", >>> + } >>> + }; >>> + int i; >>> + >>> + for (i = 0; i < GUC_LOG_SECTIONS_LIMIT; i++) >>> + log->sizes[i].bytes = sections[i].default_val; >>> + >>> + /* If debug size > 1MB then bump default crash size to keep the >>> same units */ >>> + if (log->sizes[GUC_LOG_SECTIONS_DEBUG].bytes >= SZ_1M && >>> + GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE < SZ_1M) >>> + log->sizes[GUC_LOG_SECTIONS_CRASH].bytes = SZ_1M; >>> + >>> + /* Prepare the GuC API structure fields: */ >>> + for (i = 0; i < GUC_LOG_SECTIONS_LIMIT; i++) { >>> + /* Convert to correct units */ >>> + if ((log->sizes[i].bytes % SZ_1M) == 0) { >>> + log->sizes[i].units = SZ_1M; >>> + log->sizes[i].flag = sections[i].flag; >>> + } else { >>> + log->sizes[i].units = SZ_4K; >>> + log->sizes[i].flag = 0; >>> + } >>> + >>> + if (!IS_ALIGNED(log->sizes[i].bytes, log->sizes[i].units)) >>> + xe_gt_err(guc_to_gt(guc), "Mis-aligned log %s size: 0x%X >>> vs 0x%X!\n", >>> + sections[i].name, log->sizes[i].bytes, >>> log->sizes[i].units); >> >> this 'mis-alignment' issue seems to be due to our coding fault so we >> should use xe_gt_assert() to catch that > good idea, will do xe_gt_assert_msg to have more info > >> >>> + log->sizes[i].count = log->sizes[i].bytes / >>> log->sizes[i].units; >>> + >>> + if (!log->sizes[i].count) { >>> + xe_gt_err(guc_to_gt(guc), "Zero log %s size!\n", >>> sections[i].name); >>> + } else { >>> + /* Size is +1 unit */ >>> + log->sizes[i].count--; >>> + } >>> + >>> + /* Clip to field size */ >>> + if (log->sizes[i].count > sections[i].max) { >>> + xe_gt_err(guc_to_gt(guc), "log %s size too large: %d vs >>> %d!\n", >>> + sections[i].name, log->sizes[i].count + 1, >>> sections[i].max + 1); >>> + log->sizes[i].count = sections[i].max; >>> + } >>> + } >>> + >>> + if (log->sizes[GUC_LOG_SECTIONS_CRASH].units != >>> log->sizes[GUC_LOG_SECTIONS_DEBUG].units) { >>> + xe_gt_err(guc_to_gt(guc), "Unit mismatch for crash and debug >>> sections: %d vs %d!\n", >>> + log->sizes[GUC_LOG_SECTIONS_CRASH].units, >>> + log->sizes[GUC_LOG_SECTIONS_DEBUG].units); >>> + log->sizes[GUC_LOG_SECTIONS_CRASH].units = >>> log->sizes[GUC_LOG_SECTIONS_DEBUG].units; >>> + log->sizes[GUC_LOG_SECTIONS_CRASH].count = 0; >>> + } >>> + >>> + log->sizes_initialised = true; >>> +} >>> + >>> +static void guc_log_init_sizes(struct xe_guc_log *log) >>> +{ >>> + if (log->sizes_initialised) >>> + return; >>> + >>> + _guc_log_init_sizes(log); >>> +} >>> + >>> +static u32 xe_guc_log_section_size_crash(struct xe_guc_log *log) >>> +{ >>> + guc_log_init_sizes(log); >>> + >>> + return log->sizes[GUC_LOG_SECTIONS_CRASH].bytes; >>> +} >>> + >>> +static u32 xe_guc_log_section_size_debug(struct xe_guc_log *log) >>> +{ >>> + guc_log_init_sizes(log); >>> + >>> + return log->sizes[GUC_LOG_SECTIONS_DEBUG].bytes; >>> +} >>> + >> >> add kernel-doc for public functions >> >>> +u32 xe_guc_log_section_size_capture(struct xe_guc_log *log) >>> +{ >>> + guc_log_init_sizes(log); >>> + >>> + return log->sizes[GUC_LOG_SECTIONS_CAPTURE].bytes; >>> +} >>> + >>> +bool xe_guc_check_log_buf_overflow(struct xe_guc_log *log, enum >>> guc_log_buffer_type type, >>> + unsigned int full_cnt) >>> +{ >>> + unsigned int prev_full_cnt = log->stats[type].sampled_overflow; >>> + bool overflow = false; >>> + >>> + if (full_cnt != prev_full_cnt) { >>> + overflow = true; >>> + >>> + log->stats[type].overflow = full_cnt; >>> + log->stats[type].sampled_overflow += full_cnt - prev_full_cnt; >>> + >>> + if (full_cnt < prev_full_cnt) { >>> + /* buffer_full_cnt is a 4 bit counter */ >>> + log->stats[type].sampled_overflow += 16; >>> + } >>> + xe_gt_notice_ratelimited(log_to_gt(log), "log buffer >>> overflow\n"); >>> + } >>> + >>> + return overflow; >>> +} >>> + >>> +unsigned int xe_guc_get_log_buffer_size(struct xe_guc_log *log, >>> + enum guc_log_buffer_type type) >>> +{ >>> + switch (type) { >>> + case GUC_DEBUG_LOG_BUFFER: >>> + return xe_guc_log_section_size_debug(log); >>> + case GUC_CRASH_DUMP_LOG_BUFFER: >>> + return xe_guc_log_section_size_crash(log); >>> + case GUC_CAPTURE_LOG_BUFFER: >>> + return xe_guc_log_section_size_capture(log); >>> + default: >>> + MISSING_CASE(type); >> >> there should be no need for 'default' case if you properly define your >> enum type > Compiler could check static error, while 'default' here can cover > run-time errors. I would prefer to have it for public funcitons. but this is still driver only function, called only from your code, where you should be using only valid enumerators, so no need for any random runtime protection (unless you already abuse this function by using random integers as params) >> >>> + } >>> + >>> + return 0; >>> +} >>> + >>> +size_t xe_guc_get_log_buffer_offset(struct xe_guc_log *log, >>> + enum guc_log_buffer_type type) >>> +{ >>> + enum guc_log_buffer_type i; >>> + size_t offset = PAGE_SIZE;/* for the log_buffer_states */ >>> + >>> + for (i = GUC_DEBUG_LOG_BUFFER; i < GUC_MAX_LOG_BUFFER; ++i) { >>> + if (i == type) >>> + break; >>> + offset += xe_guc_get_log_buffer_size(log, i); >>> + } >>> + >>> + return offset; >>> +} >>> diff --git a/drivers/gpu/drm/xe/xe_guc_log.h >>> b/drivers/gpu/drm/xe/xe_guc_log.h >>> index 2d25ab28b4b3..de55de4052ca 100644 >>> --- a/drivers/gpu/drm/xe/xe_guc_log.h >>> +++ b/drivers/gpu/drm/xe/xe_guc_log.h >>> @@ -7,6 +7,7 @@ >>> #define _XE_GUC_LOG_H_ >>> #include "xe_guc_log_types.h" >>> +#include "xe_guc_types.h" >>> struct drm_printer; >>> @@ -17,7 +18,7 @@ struct drm_printer; >>> #else >>> #define CRASH_BUFFER_SIZE SZ_8K >>> #define DEBUG_BUFFER_SIZE SZ_64K >>> -#define CAPTURE_BUFFER_SIZE SZ_16K >>> +#define CAPTURE_BUFFER_SIZE SZ_1M >>> #endif >>> /* >>> * While we're using plain log level in i915, GuC controls are much >>> more... >>> @@ -36,6 +37,11 @@ struct drm_printer; >>> #define GUC_VERBOSITY_TO_LOG_LEVEL(x) ((x) + 2) >>> #define GUC_LOG_LEVEL_MAX >>> GUC_VERBOSITY_TO_LOG_LEVEL(GUC_LOG_VERBOSITY_MAX) >>> +static inline struct xe_guc *log_to_guc(struct xe_guc_log *log) >>> +{ >>> + return container_of(log, struct xe_guc, log); >>> +} >>> + >>> int xe_guc_log_init(struct xe_guc_log *log); >>> void xe_guc_log_print(struct xe_guc_log *log, struct drm_printer *p); >>> @@ -45,4 +51,13 @@ xe_guc_log_get_level(struct xe_guc_log *log) >>> return log->level; >>> } >>> +u32 xe_guc_log_section_size_capture(struct xe_guc_log *log); >>> + >>> +bool xe_guc_check_log_buf_overflow(struct xe_guc_log *log, >>> + enum guc_log_buffer_type type, >>> + unsigned int full_cnt); >>> +unsigned int xe_guc_get_log_buffer_size(struct xe_guc_log *log, >>> + enum guc_log_buffer_type type); >>> +size_t xe_guc_get_log_buffer_offset(struct xe_guc_log *log, >>> + enum guc_log_buffer_type type); >> >> missing space ? >> >>> #endif >>> diff --git a/drivers/gpu/drm/xe/xe_guc_log_types.h >>> b/drivers/gpu/drm/xe/xe_guc_log_types.h >>> index 125080d138a7..3d4bf2a73102 100644 >>> --- a/drivers/gpu/drm/xe/xe_guc_log_types.h >>> +++ b/drivers/gpu/drm/xe/xe_guc_log_types.h >>> @@ -7,6 +7,14 @@ >>> #define _XE_GUC_LOG_TYPES_H_ >>> #include <linux/types.h> >>> +#include "xe_guc_fwif.h" >>> + >>> +enum { >>> + GUC_LOG_SECTIONS_CRASH, >>> + GUC_LOG_SECTIONS_DEBUG, >>> + GUC_LOG_SECTIONS_CAPTURE, >>> + GUC_LOG_SECTIONS_LIMIT >>> +}; >> >> what's the relation with enum guc_log_buffer_type ? >> seems to be identical > Right, also crash/debug is reversed to enum guc_log_buffer_type, but it > is identical, will be removed. > >> >>> struct xe_bo; >>> @@ -18,6 +26,22 @@ struct xe_guc_log { >>> u32 level; >>> /** @bo: XE BO for GuC log */ >>> struct xe_bo *bo; >>> + >>> + /* Allocation settings */ >>> + struct { >>> + s32 bytes; /* Size in bytes */ >>> + s32 units; /* GuC API units - 1MB or 4KB */ >>> + s32 count; /* Number of API units */ >> >> why signed ? > Oh, all s32 here could be u32 > >> >>> + u32 flag; /* GuC API units flag */ >>> + } sizes[GUC_LOG_SECTIONS_LIMIT]; >>> + bool sizes_initialised; >>> + >>> + /* logging related stats */ >>> + struct { >>> + u32 sampled_overflow; >>> + u32 overflow; >>> + u32 flush; >>> + } stats[GUC_MAX_LOG_BUFFER]; >>> }; >>> #endif ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v9 3/4] drm/xe/guc: Add capture size check in GuC log buffer 2024-06-19 22:28 ` Michal Wajdeczko @ 2024-06-19 22:56 ` Dong, Zhanjun 0 siblings, 0 replies; 24+ messages in thread From: Dong, Zhanjun @ 2024-06-19 22:56 UTC (permalink / raw) To: Michal Wajdeczko, intel-xe, John Harrison On 2024-06-19 6:28 p.m., Michal Wajdeczko wrote: > > > On 19.06.2024 21:44, Dong, Zhanjun wrote: >> Please see my comments inline below. >> >> Zhanjun >> >> On 2024-06-14 8:13 a.m., Michal Wajdeczko wrote: >>> >>> >>> On 07.06.2024 02:07, Zhanjun Dong wrote: >>>> The capture-nodes is included in GuC log buffer, add the size check >>>> for capture region in the whole GuC log buffer. >>>> Add capture output size check before allocating the shared buffer. >>>> >>>> Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> >>>> --- >>>> drivers/gpu/drm/xe/xe_gt_printk.h | 3 + ... >>>> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h >>>> b/drivers/gpu/drm/xe/xe_guc_fwif.h >>>> index 04b03c398191..908298791c93 100644 >>>> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h >>>> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h >>>> @@ -250,6 +250,54 @@ struct guc_engine_usage { >>>> struct guc_engine_usage_record >>>> engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; >>>> } __packed; >>>> +/* GuC logging structures */ >>>> + >>>> +enum guc_log_buffer_type { >>>> + GUC_DEBUG_LOG_BUFFER, >>>> + GUC_CRASH_DUMP_LOG_BUFFER, >>>> + GUC_CAPTURE_LOG_BUFFER, >>>> + GUC_MAX_LOG_BUFFER >>> >>> this last enumerator is not real buffer type, so better at least name it >>> in a different way (at least add __ prefix? >>> >>> or best, since it looks like ABI definitions, just move it out of the >>> enum to benefit from compiler checks that John prefers: >>> >>> enum guc_log_buffer_type { >>> GUC_LOG_BUFFER_DEBUG = 0, >>> GUC_LOG_BUFFER_CRASH_DUMP = 1, >>> GUC_LOG_BUFFER_CAPTURE_LOG = 2, >>> }; >>> #define NUM_GUC_LOG_BUFFER_TYPES 3 >>> >> Will changed to: >> /* GuC logging structures */ >> enum guc_log_buffer_type { >> GUC_DEBUG_LOG_BUFFER, >> GUC_CRASH_DUMP_LOG_BUFFER, >> GUC_CAPTURE_LOG_BUFFER, >> >> GUC_LOG_BUFFER_TYPE_MAX >> }; >> The empty line speprate real type vs MAX > > empty line is not enough to let the compiler see the difference between > real _type_ and _max_ definition > >> I would prefer to stay within the enum, which make add new type easier, >> the MAX will be updated by compiler automatically, no need to manually >> add 1 to NUM_xxx macro. > > but this is (or should be) a stable ABI so we shouldn't rely on the > compiler to automatically making any changes to any of these defs. > > and as of today we have exactly 3 types defined as: > > GUC_LOG_BUFFER_DEBUG = 0, > GUC_LOG_BUFFER_CRASH_DUMP = 1, > GUC_LOG_BUFFER_CAPTURE_LOG = 2, > > so if you want to use enum to get some help from the compiler, like to > check that in your implementation you are not using bad types, then > there should be no other enumerators in this enum, as otherwise you kill > that feature > > also note that your approach will not work if for some reason the new > type will be defined as something different than 3, like: > > GUC_LOG_BUFFER_FUTURE = 345 > > so while will have 4 TYPES, your automatic MAX will be 346, making it > almost useless That's true, it is a stable ABI. Will be changed to John style. > >> >>>> +}; >>>> + >>>> +/* >>>> + * struct guc_log_buffer_state - GuC log buffer state >>> >>> this is not a kernel-doc format, intentional or typo ? >>> >>>> + * >>>> + * Below state structure is used for coordination of retrieval of >>>> GuC firmware >>>> + * logs. Separate state is maintained for each log buffer type. >>>> + * read_ptr points to the location where Xe read last in log buffer and >>>> + * is read only for GuC firmware. write_ptr is incremented by GuC >>>> with number >>>> + * of bytes written for each log entry and is read only for Xe. >>>> + * When any type of log buffer becomes half full, GuC sends a flush >>>> interrupt. >>>> + * GuC firmware expects that while it is writing to 2nd half of the >>>> buffer, >>>> + * first half would get consumed by Host and then get a flush completed >>>> + * acknowledgment from Host, so that it does not end up doing any > ... >>>> + } >>>> + >>>> + return overflow; >>>> +} >>>> + >>>> +unsigned int xe_guc_get_log_buffer_size(struct xe_guc_log *log, >>>> + enum guc_log_buffer_type type) >>>> +{ >>>> + switch (type) { >>>> + case GUC_DEBUG_LOG_BUFFER: >>>> + return xe_guc_log_section_size_debug(log); >>>> + case GUC_CRASH_DUMP_LOG_BUFFER: >>>> + return xe_guc_log_section_size_crash(log); >>>> + case GUC_CAPTURE_LOG_BUFFER: >>>> + return xe_guc_log_section_size_capture(log); >>>> + default: >>>> + MISSING_CASE(type); >>> >>> there should be no need for 'default' case if you properly define your >>> enum type >> Compiler could check static error, while 'default' here can cover >> run-time errors. I would prefer to have it for public funcitons. > > but this is still driver only function, called only from your code, > where you should be using only valid enumerators, so no need for any > random runtime protection (unless you already abuse this function by > using random integers as params) > By switch to John style, this default case could be removed. > >>> >>>> + } >>>> + >>>> + return 0; >>>> +} >>>> + >>>> +size_t xe_guc_get_log_buffer_offset(struct xe_guc_log *log, >>>> + enum guc_log_buffer_type type) >>>> +{ >>>> + enum guc_log_buffer_type i; >>>> + size_t offset = PAGE_SIZE;/* for the log_buffer_states */ >>>> + >>>> + for (i = GUC_DEBUG_LOG_BUFFER; i < GUC_MAX_LOG_BUFFER; ++i) { >>>> + if (i == type) >>>> + break; ... ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v9 4/4] drm/xe/guc: Extract GuC capture lists to register snapshot 2024-06-07 0:07 [PATCH v9 0/4] drm/xe/guc: Add GuC based register capture for error capture Zhanjun Dong ` (2 preceding siblings ...) 2024-06-07 0:07 ` [PATCH v9 3/4] drm/xe/guc: Add capture size check in GuC log buffer Zhanjun Dong @ 2024-06-07 0:07 ` Zhanjun Dong 2024-06-13 23:26 ` Teres Alexis, Alan Previn 2024-06-14 12:31 ` Michal Wajdeczko 2024-06-07 0:12 ` ✓ CI.Patch_applied: success for drm/xe/guc: Add GuC based register capture for error capture (rev9) Patchwork ` (7 subsequent siblings) 11 siblings, 2 replies; 24+ messages in thread From: Zhanjun Dong @ 2024-06-07 0:07 UTC (permalink / raw) To: intel-xe; +Cc: Zhanjun Dong Upon the G2H Notify-Err-Capture event, parse through the GuC Log Buffer (error-capture-subregion) and generate one or more capture-nodes. A single node represents a single "engine- instance-capture-dump" and contains at least 3 register lists: global, engine-class and engine-instance. An internal link list is maintained to store one or more nodes. Because the link-list node generation happen before the call to devcoredump, duplicate global and engine-class register lists for each engine-instance register dump if we find dependent-engine resets in a engine-capture-group. When xe_devcoredump calls into snapshot_from_capture_engine, we detach the matching node (guc-id, LRCA, etc) from the link list above and attach it to snapshot_regs structure when have matching LRCA/guc-id/engine-instance. To avoid dynamically allocate the output nodes during gt reset, pre-allocate a fixed number of empty nodes up front (at the time of ADS registration) that we can consume from or return to an internal cached list of nodes. Add guc capture data structure definition. Add xe_hw_engine_snapshot_from_capture to take snapshot from capture node list. Move snapshot register struct out of engine snapshot struct. Add offset in snapshot register to register definition list at xe_guc_capture.c. Snapshot could be split into global, engine class, engine instance and steering register zone, few macros defined to separate zones. Support combines 2 32bit registers as a 64bit register in snapshot, perform endian convert if needed. Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> --- drivers/gpu/drm/xe/abi/guc_actions_abi.h | 7 + drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 + drivers/gpu/drm/xe/xe_devcoredump.c | 4 + drivers/gpu/drm/xe/xe_devcoredump_types.h | 2 + drivers/gpu/drm/xe/xe_guc.h | 23 + drivers/gpu/drm/xe/xe_guc_capture.c | 876 +++++++++++++++++++++- drivers/gpu/drm/xe/xe_guc_capture.h | 9 + drivers/gpu/drm/xe/xe_guc_capture_fwif.h | 45 ++ drivers/gpu/drm/xe/xe_guc_ct.c | 2 + drivers/gpu/drm/xe/xe_guc_fwif.h | 6 + drivers/gpu/drm/xe/xe_guc_submit.c | 63 +- drivers/gpu/drm/xe/xe_guc_submit.h | 2 + drivers/gpu/drm/xe/xe_hw_engine.c | 218 ++++-- drivers/gpu/drm/xe/xe_hw_engine_types.h | 159 ++-- drivers/gpu/drm/xe/xe_lrc.h | 1 + 15 files changed, 1244 insertions(+), 175 deletions(-) diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h index 79ba98a169f9..ed1eeea34e8e 100644 --- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h +++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h @@ -182,6 +182,13 @@ enum xe_guc_sleep_state_status { #define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT) #define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8) +enum intel_guc_state_capture_event_status { + XE_GUC_STATE_CAPTURE_EVENT_STATUS_SUCCESS = 0x0, + XE_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE = 0x1, +}; + +#define XE_GUC_STATE_CAPTURE_EVENT_STATUS_MASK 0x000000FF + #define XE_GUC_TLB_INVAL_TYPE_SHIFT 0 #define XE_GUC_TLB_INVAL_MODE_SHIFT 8 /* Flush PPC or SMRO caches along with TLB invalidation request */ diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index d09b2473259f..c6bd50738e2b 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -574,4 +574,6 @@ #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) #define GT_RENDER_USER_INTERRUPT REG_BIT(0) +#define SFC_DONE(n) XE_REG(0x1cc000 + (n) * 0x1000) + #endif diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c index d7f2d19a77c1..5e80710d3cc8 100644 --- a/drivers/gpu/drm/xe/xe_devcoredump.c +++ b/drivers/gpu/drm/xe/xe_devcoredump.c @@ -16,6 +16,7 @@ #include "xe_force_wake.h" #include "xe_gt.h" #include "xe_gt_printk.h" +#include "xe_guc_capture.h" #include "xe_guc_ct.h" #include "xe_guc_submit.h" #include "xe_hw_engine.h" @@ -149,10 +150,12 @@ static void xe_devcoredump_free(void *data) if (coredump->snapshot.hwe[i]) xe_hw_engine_snapshot_free(coredump->snapshot.hwe[i]); xe_vm_snapshot_free(coredump->snapshot.vm); + xe_guc_capture_free(&coredump->snapshot.gt->uc.guc); /* To prevent stale data on next snapshot, clear everything */ memset(&coredump->snapshot, 0, sizeof(coredump->snapshot)); coredump->captured = false; + coredump->job = NULL; drm_info(&coredump_to_xe(coredump)->drm, "Xe device coredump has been deleted.\n"); } @@ -186,6 +189,7 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump, put_task_struct(task); ss->gt = q->gt; + coredump->job = job; INIT_WORK(&ss->work, xe_devcoredump_deferred_snap_work); cookie = dma_fence_begin_signalling(); diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h index 923cdf72a816..c39ab73a9f6a 100644 --- a/drivers/gpu/drm/xe/xe_devcoredump_types.h +++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h @@ -61,6 +61,8 @@ struct xe_devcoredump { bool captured; /** @snapshot: Snapshot is captured at time of the first crash */ struct xe_devcoredump_snapshot snapshot; + /** @job: Point to the issue job */ + struct xe_sched_job *job; }; #endif diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h index ddfa855458ab..e1afda9070f4 100644 --- a/drivers/gpu/drm/xe/xe_guc.h +++ b/drivers/gpu/drm/xe/xe_guc.h @@ -59,6 +59,29 @@ static inline u16 xe_engine_class_to_guc_class(enum xe_engine_class class) } } +static inline u16 xe_guc_class_to_capture_class(uint class) +{ + switch (class) { + case GUC_RENDER_CLASS: + case GUC_COMPUTE_CLASS: + return GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE; + case GUC_GSC_OTHER_CLASS: + return GUC_CAPTURE_LIST_CLASS_GSC_OTHER; + case GUC_VIDEO_CLASS: + case GUC_VIDEOENHANCE_CLASS: + case GUC_BLITTER_CLASS: + return class; + default: + XE_WARN_ON(class); + return -1; + } +} + +static inline u16 xe_engine_class_to_guc_capture_class(enum xe_engine_class class) +{ + return xe_guc_class_to_capture_class(xe_guc_class_to_capture_class(class)); +} + static inline struct xe_gt *guc_to_gt(struct xe_guc *guc) { return container_of(guc, struct xe_gt, uc.guc); diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c index 0c90def290de..f18933503672 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture.c +++ b/drivers/gpu/drm/xe/xe_guc_capture.c @@ -26,10 +26,13 @@ #include "xe_guc_capture_fwif.h" #include "xe_guc_ct.h" #include "xe_guc_log.h" +#include "xe_guc_submit_types.h" #include "xe_guc_submit.h" #include "xe_hw_engine_types.h" +#include "xe_lrc.h" #include "xe_macros.h" #include "xe_map.h" +#include "xe_sched_job.h" /* * Define all device tables of GuC error capture register lists @@ -37,28 +40,81 @@ * from the engine-mmio-base */ #define COMMON_XELP_BASE_GLOBAL \ - { FORCEWAKE_GT, 0, 0} + { FORCEWAKE_GT, 0, 0, "FORCEWAKE_GT",\ + offsetof(struct snapshot_regs, forcewake_gt) } #define COMMON_BASE_ENGINE_INSTANCE \ - { RING_ESR(0), 0, 0}, \ - { RING_EMR(0), 0, 0}, \ - { RING_EIR(0), 0, 0}, \ - { RING_EXECLIST_STATUS_HI(0), 0, 0}, \ - { RING_EXECLIST_STATUS_LO(0), 0, 0}, \ - { RING_DMA_FADD(0), 0, 0}, \ - { RING_DMA_FADD_UDW(0), 0, 0}, \ - { RING_IPEHR(0), 0, 0}, \ - { RING_BBADDR(0), 0, 0}, \ - { RING_BBADDR_UDW(0), 0, 0}, \ - { RING_ACTHD(0), 0, 0}, \ - { RING_ACTHD_UDW(0), 0, 0}, \ - { RING_START(0), 0, 0}, \ - { RING_HEAD(0), 0, 0}, \ - { RING_TAIL(0), 0, 0}, \ - { RING_CTL(0), 0, 0}, \ - { RING_MI_MODE(0), 0, 0}, \ - { RING_HWS_PGA(0), 0, 0}, \ - { RING_MODE(0), 0, 0} + { RING_HWSTAM(0), 0, 0, "HWSTAM",\ + offsetof(struct snapshot_regs, ring_hwstam) }, \ + { RING_HWS_PGA(0), 0, 0, "RING_HWS_PGA",\ + offsetof(struct snapshot_regs, ring_hws_pga) }, \ + { RING_HEAD(0), 0, 0, "RING_HEAD",\ + offsetof(struct snapshot_regs, ring_head) }, \ + { RING_TAIL(0), 0, 0, "RING_TAIL",\ + offsetof(struct snapshot_regs, ring_tail) }, \ + { RING_CTL(0), 0, 0, "RING_CTL",\ + offsetof(struct snapshot_regs, ring_ctl) }, \ + { RING_MI_MODE(0), 0, 0, "RING_MI_MODE",\ + offsetof(struct snapshot_regs, ring_mi_mode) }, \ + { RING_MODE(0), 0, 0, "RING_MODE",\ + offsetof(struct snapshot_regs, ring_mode) }, \ + { RING_ESR(0), 0, 0, "RING_ESR",\ + offsetof(struct snapshot_regs, ring_esr) }, \ + { RING_EMR(0), 0, 0, "RING_EMR",\ + offsetof(struct snapshot_regs, ring_emr) }, \ + { RING_EIR(0), 0, 0, "RING_EIR",\ + offsetof(struct snapshot_regs, ring_eir) }, \ + { RING_IMR(0), 0, 0, "RING_IMR",\ + offsetof(struct snapshot_regs, ring_imr) }, \ + { RING_IPEHR(0), 0, 0, "IPEHR",\ + offsetof(struct snapshot_regs, ipehr) }, \ + /* 64 bit register - Start */ \ + /* defined XE_GUC_SNAPSHOT_REGS_U64_START_REG_ADDR to the address of 1st register below */ \ + /* into xe_hw_engine_types.h */ \ + { RING_ACTHD(0), 0, 0, "ACTHD",\ + offsetof(struct snapshot_regs, ring_acthd) }, \ + { RING_ACTHD_UDW(0), 0, 0, NULL,\ + offsetof(struct snapshot_regs, ring_acthd) + 4}, \ + { RING_BBADDR(0), 0, 0, "RING_BBADDR",\ + offsetof(struct snapshot_regs, ring_bbaddr) }, \ + { RING_BBADDR_UDW(0), 0, 0, NULL,\ + offsetof(struct snapshot_regs, ring_bbaddr) + 4}, \ + { RING_START(0), 0, 0, "RING_START",\ + offsetof(struct snapshot_regs, ring_start) }, \ + { RING_START_UDW(0), 0, 0, NULL,\ + offsetof(struct snapshot_regs, ring_start) + 4}, \ + { RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD",\ + offsetof(struct snapshot_regs, ring_dma_fadd) }, \ + { RING_DMA_FADD_UDW(0), 0, 0, NULL,\ + offsetof(struct snapshot_regs, ring_dma_fadd) + 4}, \ + { RING_EXECLIST_STATUS_LO(0), 0, 0, "RING_EXECLIST_STATUS",\ + offsetof(struct snapshot_regs, ring_execlist_status)}, \ + { RING_EXECLIST_STATUS_HI(0), 0, 0, NULL,\ + offsetof(struct snapshot_regs, ring_execlist_status) + 4}, \ + { RING_EXECLIST_SQ_CONTENTS_LO(0), 0, 0, "RING_EXECLIST_SQ_CONTENTS",\ + offsetof(struct snapshot_regs, ring_execlist_sq_contents)}, \ + { RING_EXECLIST_SQ_CONTENTS_HI(0), 0, 0, NULL,\ + offsetof(struct snapshot_regs, ring_execlist_sq_contents) + 4}, \ + /* 64 bit register - End */ \ + /* Extra handling registers */ \ + /* define XE_GUC_SNAPSHOT_EXTRA_OPERATION_REGS_START_REG_ADDR to the address of 1st */ \ + /* register below into xe_hw_engine_types.h */ \ + { INDIRECT_RING_STATE(0), 0, 0, "INDIRECT_RING_STATE",\ + offsetof(struct snapshot_regs, indirect_ring_state)} + +#define COMMON_XELP_RC_CLASS \ + { RCU_MODE, 0, 0, "RCU_MODE",\ + offsetof(struct snapshot_regs, rcu_mode) } + +#define XELP_DIRECT_READ_VEC_CLASS \ + { SFC_DONE(0), 0, 0, "SFC_DONE[0]", \ + offsetof(struct snapshot_regs, sfc_done_0) }, \ + { SFC_DONE(1), 0, 0, "SFC_DONE[1]", \ + offsetof(struct snapshot_regs, sfc_done_1) }, \ + { SFC_DONE(2), 0, 0, "SFC_DONE[2]", \ + offsetof(struct snapshot_regs, sfc_done_2) }, \ + { SFC_DONE(3), 0, 0, "SFC_DONE[3]", \ + offsetof(struct snapshot_regs, sfc_done_3) } /* XE_LP Global */ static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = { @@ -70,6 +126,11 @@ static const struct __guc_mmio_reg_descr xe_rc_inst_regs[] = { COMMON_BASE_ENGINE_INSTANCE, }; +/* Render / Compute Per-Engine-Instance */ +static const struct __guc_mmio_reg_descr xe_rc_class_regs[] = { + COMMON_XELP_RC_CLASS, +}; + /* Media Decode/Encode Per-Engine-Instance */ static const struct __guc_mmio_reg_descr xe_vd_inst_regs[] = { COMMON_BASE_ENGINE_INSTANCE, @@ -80,6 +141,11 @@ static const struct __guc_mmio_reg_descr xe_vec_inst_regs[] = { COMMON_BASE_ENGINE_INSTANCE, }; +/* Video Enhancement Per-Engine-Class */ +static const struct __guc_mmio_reg_descr xe_vec_direct_read_regs[] = { + XELP_DIRECT_READ_VEC_CLASS, +}; + /* Blitter Per-Engine-Instance */ static const struct __guc_mmio_reg_descr xe_blt_inst_regs[] = { COMMON_BASE_ENGINE_INSTANCE, @@ -112,12 +178,13 @@ static const struct __guc_mmio_reg_descr empty_regs_list[] = { /* List of lists */ static const struct __guc_mmio_reg_descr_group xe_lp_lists[] = { MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0), - MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE), + MAKE_REGLIST(xe_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE), MAKE_REGLIST(xe_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE), MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO), MAKE_REGLIST(xe_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO), MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE), + MAKE_REGLIST(xe_vec_direct_read_regs, PF, DIRECT_READ, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE), MAKE_REGLIST(xe_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE), MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER), @@ -148,6 +215,7 @@ static const char * const capture_engine_class_names[] = { */ #define get_item_with_default(ar, index) (ar[(index) >= ARRAY_SIZE(ar) ? ARRAY_SIZE(ar) - 1 : \ (index)]) +static void guc_capture_create_prealloc_nodes(struct xe_guc *guc); static const struct __guc_mmio_reg_descr_group * guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists, @@ -167,6 +235,12 @@ guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists, return NULL; } +const struct __guc_mmio_reg_descr_group * +xe_guc_capture_get_reg_desc_list(u32 owner, u32 type, u32 engine_classid) +{ + return guc_capture_get_one_list(xe_lp_lists, owner, type, engine_classid); +} + static struct __guc_mmio_reg_descr_group * guc_capture_get_one_ext_list(struct __guc_mmio_reg_descr_group *reglists, u32 owner, u32 type, u32 id) @@ -430,6 +504,12 @@ xe_guc_capture_getlist(struct xe_guc *guc, u32 owner, u32 type, u32 classid, voi return cache->status; } + /* + * ADS population of input registers is a good + * time to pre-allocate cachelist output nodes + */ + guc_capture_create_prealloc_nodes(guc); + ret = xe_guc_capture_getlistsize(guc, owner, type, classid, &size); if (ret) { cache->is_valid = true; @@ -567,6 +647,756 @@ static void check_guc_capture_size(struct xe_guc *guc) buffer_size, spare_size, capture_size); } +static void +guc_capture_add_node_to_list(struct __guc_capture_parsed_output *node, + struct list_head *list) +{ + list_add_tail(&node->link, list); +} + +static void +guc_capture_add_node_to_outlist(struct xe_guc_state_capture *guc, + struct __guc_capture_parsed_output *node) +{ + guc_capture_add_node_to_list(node, &guc->outlist); +} + +static void +guc_capture_add_node_to_cachelist(struct xe_guc_state_capture *guc, + struct __guc_capture_parsed_output *node) +{ + guc_capture_add_node_to_list(node, &guc->cachelist); +} + +static void +guc_capture_init_node(struct xe_guc *guc, struct __guc_capture_parsed_output *node) +{ + struct guc_mmio_reg *tmp[GUC_CAPTURE_LIST_TYPE_MAX]; + int i; + + for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { + tmp[i] = node->reginfo[i].regs; + memset(tmp[i], 0, sizeof(struct guc_mmio_reg) * + guc->capture->max_mmio_per_node); + } + memset(node, 0, sizeof(*node)); + for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) + node->reginfo[i].regs = tmp[i]; + + INIT_LIST_HEAD(&node->link); +} + +/* + * KMD Init time flows: + * -------------------- + * --> alloc A: GuC input capture regs lists (registered to GuC via ADS). + * xe_guc_ads acquires the register lists by calling + * xe_guc_capture_list_size and xe_guc_capture_list_get 'n' times, + * where n = 1 for global-reg-list + + * num_engine_classes for class-reg-list + + * num_engine_classes for instance-reg-list + * (since all instances of the same engine-class type + * have an identical engine-instance register-list). + * ADS module also calls separately for PF vs VF. + * + * --> alloc B: GuC output capture buf (registered via guc_init_params(log_param)) + * Size = #define CAPTURE_BUFFER_SIZE (warns if on too-small) + * Note2: 'x 3' to hold multiple capture groups + * + * GUC Runtime notify capture: + * -------------------------- + * --> G2H STATE_CAPTURE_NOTIFICATION + * L--> xe_guc_capture_process + * L--> Loop through B (head..tail) and for each engine instance's + * err-state-captured register-list we find, we alloc 'C': + * --> alloc C: A capture-output-node structure that includes misc capture info along + * with 3 register list dumps (global, engine-class and engine-instance) + * This node is created from a pre-allocated list of blank nodes in + * guc->capture->cachelist and populated with the error-capture + * data from GuC and then it's added into guc->capture->outlist linked + * list. This list is used for matchup and printout by xe_devcoredump_read + * and xe_hw_engine_snapshot_print, (when user invokes the devcoredump sysfs). + * + * GUC --> notify context reset: + * ----------------------------- + * --> guc_exec_queue_timedout_job + * L--> xe_devcoredump + * L--> devcoredump_snapshot(..IS_GUC_CAPTURE) + * --> xe_hw_engine_snapshot_capture(..IS_GUC_CAPTURE) + * L--> xe_hw_engine_find_and_copy_guc_capture_snapshot is where + * detach C from internal linked list and add it into + * xe_hw_engine_snapshot struct (if the context and + * engine of the event notification matches a node + * in the link list). + * + * User Sysfs / Debugfs + * -------------------- + * --> xe_devcoredump_read-> + * L--> xxx_snapshot_print + * L--> xe_hw_engine_snapshot_print + * register lists values of the xe_hw_engine_snapshot + * saved from the error-engine-dump. + * + */ + +static int guc_capture_buf_cnt(struct __guc_capture_bufstate *buf) +{ + if (buf->wr >= buf->rd) + return (buf->wr - buf->rd); + return (buf->size - buf->rd) + buf->wr; +} + +static int guc_capture_buf_cnt_to_end(struct __guc_capture_bufstate *buf) +{ + if (buf->rd > buf->wr) + return (buf->size - buf->rd); + return (buf->wr - buf->rd); +} + +/* + * GuC's error-capture output is a ring buffer populated in a byte-stream fashion: + * + * The GuC Log buffer region for error-capture is managed like a ring buffer. + * The GuC firmware dumps error capture logs into this ring in a byte-stream flow. + * Additionally, as per the current and foreseeable future, all packed error- + * capture output structures are dword aligned. + * + * That said, if the GuC firmware is in the midst of writing a structure that is larger + * than one dword but the tail end of the err-capture buffer-region has lesser space left, + * we would need to extract that structure one dword at a time straddled across the end, + * onto the start of the ring. + * + * Below function, guc_capture_log_remove_dw is a helper for that. All callers of this + * function would typically do a straight-up memcpy from the ring contents and will only + * call this helper if their structure-extraction is straddling across the end of the + * ring. GuC firmware does not add any padding. The reason for the no-padding is to ease + * scalability for future expansion of output data types without requiring a redesign + * of the flow controls. + */ +static int +guc_capture_log_remove_dw(struct xe_guc *guc, struct __guc_capture_bufstate *buf, + u32 *dw) +{ + int tries = 2; + int avail = 0; + + if (!guc_capture_buf_cnt(buf)) + return 0; + + while (tries--) { + avail = guc_capture_buf_cnt_to_end(buf); + if (avail >= sizeof(u32)) { + *dw = xe_map_rd(guc_to_xe(guc), &guc->log.bo->vmap, + buf->data_offset + buf->rd, u32); + buf->rd += 4; + return 4; + } + if (avail) + xe_gt_dbg(guc_to_gt(guc), "Register capture log not dword aligned, skipping.\n"); + buf->rd = 0; + } + + return 0; +} + +static bool +guc_capture_data_extracted(struct xe_guc *guc, struct __guc_capture_bufstate *b, + int size, void *dest) +{ + if (guc_capture_buf_cnt_to_end(b) >= size) { + xe_map_memcpy_from(guc_to_xe(guc), dest, &guc->log.bo->vmap, + b->data_offset + b->rd, size); + b->rd += size; + return true; + } + return false; +} + +static int +guc_capture_log_get_group_hdr(struct xe_guc *guc, struct __guc_capture_bufstate *buf, + struct guc_state_capture_group_header_t *ghdr) +{ + int read = 0; + int fullsize = sizeof(struct guc_state_capture_group_header_t); + + if (fullsize > guc_capture_buf_cnt(buf)) + return -1; + + if (guc_capture_data_extracted(guc, buf, fullsize, (void *)ghdr)) + return 0; + + read += guc_capture_log_remove_dw(guc, buf, &ghdr->owner); + read += guc_capture_log_remove_dw(guc, buf, &ghdr->info); + if (read != fullsize) + return -1; + + return 0; +} + +static int +guc_capture_log_get_data_hdr(struct xe_guc *guc, struct __guc_capture_bufstate *buf, + struct guc_state_capture_header_t *hdr) +{ + int read = 0; + int fullsize = sizeof(struct guc_state_capture_header_t); + + if (fullsize > guc_capture_buf_cnt(buf)) + return -1; + + if (guc_capture_data_extracted(guc, buf, fullsize, (void *)hdr)) + return 0; + + read += guc_capture_log_remove_dw(guc, buf, &hdr->owner); + read += guc_capture_log_remove_dw(guc, buf, &hdr->info); + read += guc_capture_log_remove_dw(guc, buf, &hdr->lrca); + read += guc_capture_log_remove_dw(guc, buf, &hdr->guc_id); + read += guc_capture_log_remove_dw(guc, buf, &hdr->num_mmios); + if (read != fullsize) + return -1; + + return 0; +} + +static int +guc_capture_log_get_register(struct xe_guc *guc, struct __guc_capture_bufstate *buf, + struct guc_mmio_reg *reg) +{ + int read = 0; + int fullsize = sizeof(struct guc_mmio_reg); + + if (fullsize > guc_capture_buf_cnt(buf)) + return -1; + + if (guc_capture_data_extracted(guc, buf, fullsize, (void *)reg)) + return 0; + + read += guc_capture_log_remove_dw(guc, buf, ®->offset); + read += guc_capture_log_remove_dw(guc, buf, ®->value); + read += guc_capture_log_remove_dw(guc, buf, ®->flags); + read += guc_capture_log_remove_dw(guc, buf, ®->mask); + if (read != fullsize) + return -1; + + return 0; +} + +static struct __guc_capture_parsed_output * +guc_capture_get_prealloc_node(struct xe_guc *guc) +{ + struct __guc_capture_parsed_output *found = NULL; + + if (!list_empty(&guc->capture->cachelist)) { + struct __guc_capture_parsed_output *n, *ntmp; + + /* get first avail node from the cache list */ + list_for_each_entry_safe(n, ntmp, &guc->capture->cachelist, link) { + found = n; + break; + } + } else { + struct __guc_capture_parsed_output *n, *ntmp; + + /* traverse down and steal back the oldest node already allocated */ + list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) { + found = n; + } + } + if (found) { + list_del(&found->link); + guc_capture_init_node(guc, found); + } + + return found; +} + +static struct __guc_capture_parsed_output * +guc_capture_clone_node(struct xe_guc *guc, struct __guc_capture_parsed_output *original, + u32 keep_reglist_mask) +{ + struct __guc_capture_parsed_output *new; + int i; + + new = guc_capture_get_prealloc_node(guc); + if (!new) + return NULL; + if (!original) + return new; + + new->is_partial = original->is_partial; + + /* copy reg-lists that we want to clone */ + for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { + if (keep_reglist_mask & BIT(i)) { + XE_WARN_ON(original->reginfo[i].num_regs > + guc->capture->max_mmio_per_node); + + memcpy(new->reginfo[i].regs, original->reginfo[i].regs, + original->reginfo[i].num_regs * sizeof(struct guc_mmio_reg)); + + new->reginfo[i].num_regs = original->reginfo[i].num_regs; + new->reginfo[i].vfid = original->reginfo[i].vfid; + + if (i == GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS) { + new->eng_class = original->eng_class; + } else if (i == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) { + new->eng_inst = original->eng_inst; + new->guc_id = original->guc_id; + new->lrca = original->lrca; + } + } + } + + return new; +} + +static int +guc_capture_extract_reglists(struct xe_guc *guc, struct __guc_capture_bufstate *buf) +{ + struct xe_gt *gt = guc_to_gt(guc); + struct guc_state_capture_group_header_t ghdr = {0}; + struct guc_state_capture_header_t hdr = {0}; + struct __guc_capture_parsed_output *node = NULL; + struct guc_mmio_reg *regs = NULL; + int i, numlists, numregs, ret = 0; + enum guc_capture_type datatype; + struct guc_mmio_reg tmp; + bool is_partial = false; + + i = guc_capture_buf_cnt(buf); + if (!i) + return -ENODATA; + + if (i % sizeof(u32)) { + xe_gt_warn(gt, "Got mis-aligned register capture entries\n"); + ret = -EIO; + goto bailout; + } + + /* first get the capture group header */ + if (guc_capture_log_get_group_hdr(guc, buf, &ghdr)) { + ret = -EIO; + goto bailout; + } + /* + * we would typically expect a layout as below where n would be expected to be + * anywhere between 3 to n where n > 3 if we are seeing multiple dependent engine + * instances being reset together. + * ____________________________________________ + * | Capture Group | + * | ________________________________________ | + * | | Capture Group Header: | | + * | | - num_captures = 5 | | + * | |______________________________________| | + * | ________________________________________ | + * | | Capture1: | | + * | | Hdr: GLOBAL, numregs=a | | + * | | ____________________________________ | | + * | | | Reglist | | | + * | | | - reg1, reg2, ... rega | | | + * | | |__________________________________| | | + * | |______________________________________| | + * | ________________________________________ | + * | | Capture2: | | + * | | Hdr: CLASS=RENDER/COMPUTE, numregs=b| | + * | | ____________________________________ | | + * | | | Reglist | | | + * | | | - reg1, reg2, ... regb | | | + * | | |__________________________________| | | + * | |______________________________________| | + * | ________________________________________ | + * | | Capture3: | | + * | | Hdr: INSTANCE=RCS, numregs=c | | + * | | ____________________________________ | | + * | | | Reglist | | | + * | | | - reg1, reg2, ... regc | | | + * | | |__________________________________| | | + * | |______________________________________| | + * | ________________________________________ | + * | | Capture4: | | + * | | Hdr: CLASS=RENDER/COMPUTE, numregs=d| | + * | | ____________________________________ | | + * | | | Reglist | | | + * | | | - reg1, reg2, ... regd | | | + * | | |__________________________________| | | + * | |______________________________________| | + * | ________________________________________ | + * | | Capture5: | | + * | | Hdr: INSTANCE=CCS0, numregs=e | | + * | | ____________________________________ | | + * | | | Reglist | | | + * | | | - reg1, reg2, ... rege | | | + * | | |__________________________________| | | + * | |______________________________________| | + * |__________________________________________| + */ + is_partial = FIELD_GET(CAP_GRP_HDR_CAPTURE_TYPE, ghdr.info); + numlists = FIELD_GET(CAP_GRP_HDR_NUM_CAPTURES, ghdr.info); + + while (numlists--) { + if (guc_capture_log_get_data_hdr(guc, buf, &hdr)) { + ret = -EIO; + break; + } + + datatype = FIELD_GET(CAP_HDR_CAPTURE_TYPE, hdr.info); + if (datatype > GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) { + /* unknown capture type - skip over to next capture set */ + numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios); + while (numregs--) { + if (guc_capture_log_get_register(guc, buf, &tmp)) { + ret = -EIO; + break; + } + } + continue; + } else if (node) { + /* + * Based on the current capture type and what we have so far, + * decide if we should add the current node into the internal + * linked list for match-up when xe_devcoredump calls later + * (and alloc a blank node for the next set of reglists) + * or continue with the same node or clone the current node + * but only retain the global or class registers (such as the + * case of dependent engine resets). + */ + if (datatype == GUC_CAPTURE_LIST_TYPE_GLOBAL) { + guc_capture_add_node_to_outlist(guc->capture, node); + node = NULL; + } else if (datatype == GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS && + node->reginfo[GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS].num_regs) { + /* Add to list, clone node and duplicate global list */ + guc_capture_add_node_to_outlist(guc->capture, node); + node = guc_capture_clone_node(guc, node, + GCAP_PARSED_REGLIST_INDEX_GLOBAL); + } else if (datatype == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE && + node->reginfo[GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE].num_regs) { + /* Add to list, clone node and duplicate global + class lists */ + guc_capture_add_node_to_outlist(guc->capture, node); + node = guc_capture_clone_node(guc, node, + (GCAP_PARSED_REGLIST_INDEX_GLOBAL | + GCAP_PARSED_REGLIST_INDEX_ENGCLASS)); + } + } + + if (!node) { + node = guc_capture_get_prealloc_node(guc); + if (!node) { + ret = -ENOMEM; + break; + } + if (datatype != GUC_CAPTURE_LIST_TYPE_GLOBAL) + xe_gt_dbg(gt, "Register capture missing global dump: %08x!\n", + datatype); + } + node->is_partial = is_partial; + node->reginfo[datatype].vfid = FIELD_GET(CAP_HDR_CAPTURE_VFID, hdr.owner); + + switch (datatype) { + case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE: + node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info); + node->eng_inst = FIELD_GET(CAP_HDR_ENGINE_INSTANCE, hdr.info); + node->lrca = hdr.lrca; + node->guc_id = hdr.guc_id; + break; + case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS: + node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info); + break; + default: + break; + } + + numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios); + if (numregs > guc->capture->max_mmio_per_node) { + xe_gt_dbg(gt, "Register capture list extraction clipped by prealloc!\n"); + numregs = guc->capture->max_mmio_per_node; + } + node->reginfo[datatype].num_regs = numregs; + regs = node->reginfo[datatype].regs; + i = 0; + while (numregs--) { + if (guc_capture_log_get_register(guc, buf, ®s[i++])) { + ret = -EIO; + break; + } + } + } + +bailout: + if (node) { + /* If we have data, add to linked list for match-up when xe_devcoredump calls */ + for (i = GUC_CAPTURE_LIST_TYPE_GLOBAL; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { + if (node->reginfo[i].regs) { + guc_capture_add_node_to_outlist(guc->capture, node); + node = NULL; + break; + } + } + if (node) /* else return it back to cache list */ + guc_capture_add_node_to_cachelist(guc->capture, node); + } + return ret; +} + +static int __guc_capture_flushlog_complete(struct xe_guc *guc) +{ + u32 action[] = { + XE_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE, + GUC_CAPTURE_LOG_BUFFER + }; + + return xe_guc_ct_send_g2h_handler(&guc->ct, action, ARRAY_SIZE(action)); +} + +static void __guc_capture_process_output(struct xe_guc *guc) +{ + unsigned int buffer_size, read_offset, write_offset, full_count; + struct xe_uc *uc = container_of(guc, typeof(*uc), guc); + struct guc_log_buffer_state log_buf_state_local; + struct __guc_capture_bufstate buf; + bool new_overflow; + int ret; + u32 log_buf_state_offset; + u32 src_data_offset; + + log_buf_state_offset = sizeof(struct guc_log_buffer_state) * GUC_CAPTURE_LOG_BUFFER; + src_data_offset = xe_guc_get_log_buffer_offset(&guc->log, GUC_CAPTURE_LOG_BUFFER); + + /* + * Make a copy of the state structure, inside GuC log buffer + * (which is uncached mapped), on the stack to avoid reading + * from it multiple times. + */ + xe_map_memcpy_from(guc_to_xe(guc), &log_buf_state_local, &guc->log.bo->vmap, + log_buf_state_offset, sizeof(struct guc_log_buffer_state)); + + buffer_size = xe_guc_get_log_buffer_size(&guc->log, GUC_CAPTURE_LOG_BUFFER); + read_offset = log_buf_state_local.read_ptr; + write_offset = log_buf_state_local.sampled_write_ptr; + full_count = log_buf_state_local.buffer_full_cnt; + + /* Bookkeeping stuff */ + guc->log.stats[GUC_CAPTURE_LOG_BUFFER].flush += log_buf_state_local.flush_to_file; + new_overflow = xe_guc_check_log_buf_overflow(&guc->log, GUC_CAPTURE_LOG_BUFFER, + full_count); + + /* Now copy the actual logs. */ + if (unlikely(new_overflow)) { + /* copy the whole buffer in case of overflow */ + read_offset = 0; + write_offset = buffer_size; + } else if (unlikely((read_offset > buffer_size) || + (write_offset > buffer_size))) { + xe_gt_err(guc_to_gt(guc), + "Register capture buffer in invalid state: read = 0x%X, size = 0x%X!\n", + read_offset, buffer_size); + /* copy whole buffer as offsets are unreliable */ + read_offset = 0; + write_offset = buffer_size; + } + + buf.size = buffer_size; + buf.rd = read_offset; + buf.wr = write_offset; + buf.data_offset = src_data_offset; + + if (!xe_guc_read_stopped(guc)) { + do { + ret = guc_capture_extract_reglists(guc, &buf); + } while (ret >= 0); + } + + /* Update the state of log buffer err-cap state */ + xe_map_wr(guc_to_xe(guc), &guc->log.bo->vmap, + log_buf_state_offset + offsetof(struct guc_log_buffer_state, read_ptr), u32, + write_offset); + /* Clear the flush_to_file from local first, the local was loaded by above + * xe_map_memcpy_from. + */ + log_buf_state_local.flush_to_file = 0; + /* Then write out the "updated local" through xe_map_wr() */ + xe_map_wr(guc_to_xe(guc), &guc->log.bo->vmap, + log_buf_state_offset + offsetof(struct guc_log_buffer_state, flags), u32, + log_buf_state_local.flags); + __guc_capture_flushlog_complete(guc); +} + +void xe_guc_capture_process(struct xe_guc *guc) +{ + if (guc->capture) + __guc_capture_process_output(guc); +} + +static struct __guc_capture_parsed_output * +guc_capture_alloc_one_node(struct xe_guc *guc) +{ + struct drm_device *drm = guc_to_drm(guc); + struct __guc_capture_parsed_output *new; + int i; + + new = drmm_kzalloc(drm, sizeof(*new), GFP_KERNEL); + if (!new) + return NULL; + + for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { + new->reginfo[i].regs = drmm_kzalloc(drm, guc->capture->max_mmio_per_node * + sizeof(struct guc_mmio_reg), GFP_KERNEL); + if (!new->reginfo[i].regs) { + while (i) + drmm_kfree(drm, new->reginfo[--i].regs); + drmm_kfree(drm, new); + return NULL; + } + } + guc_capture_init_node(guc, new); + + return new; +} + +static void +__guc_capture_create_prealloc_nodes(struct xe_guc *guc) +{ + struct __guc_capture_parsed_output *node = NULL; + int i; + + for (i = 0; i < PREALLOC_NODES_MAX_COUNT; ++i) { + node = guc_capture_alloc_one_node(guc); + if (!node) { + xe_gt_warn(guc_to_gt(guc), "Register capture pre-alloc-cache failure\n"); + /* dont free the priors, use what we got and cleanup at shutdown */ + return; + } + guc_capture_add_node_to_cachelist(guc->capture, node); + } +} + +static int +guc_get_max_reglist_count(struct xe_guc *guc) +{ + int i, j, k, tmp, maxregcount = 0; + + for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; ++i) { + for (j = 0; j < GUC_CAPTURE_LIST_TYPE_MAX; ++j) { + for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) { + if (j == GUC_CAPTURE_LIST_TYPE_GLOBAL && k > 0) + continue; + + tmp = guc_cap_list_num_regs(guc->capture, i, j, k); + if (tmp > maxregcount) + maxregcount = tmp; + } + } + } + if (!maxregcount) + maxregcount = PREALLOC_NODES_DEFAULT_NUMREGS; + + return maxregcount; +} + +static void +guc_capture_create_prealloc_nodes(struct xe_guc *guc) +{ + /* skip if we've already done the pre-alloc */ + if (guc->capture->max_mmio_per_node) + return; + + guc->capture->max_mmio_per_node = guc_get_max_reglist_count(guc); + __guc_capture_create_prealloc_nodes(guc); +} + +static void cp_reg_to_snapshot(int type, u16 hwe_guc_class, u32 offset, u32 value, + struct snapshot_regs *regs) +{ + int i; + const struct __guc_mmio_reg_descr_group *list; + + /* Get register list for the type/class */ + list = xe_guc_capture_get_reg_desc_list(GUC_CAPTURE_LIST_INDEX_PF, type, + xe_guc_class_to_capture_class(hwe_guc_class)); + if (!list) + return; + + for (i = 0; i < list->num_regs; i++) + if (offset == list->list[i].reg.addr) { + u32 *field = (u32 *)((uintptr_t)regs + list->list[i].position_in_snapshot); + *field = value; + return; + } +} + +static void guc_capture_parse_reglist(struct __guc_capture_parsed_output *node, + struct xe_hw_engine_snapshot *snapshot, u16 hwe_guc_class) +{ + int i, type; + + if (!node) + return; + + for (type = GUC_CAPTURE_LIST_TYPE_GLOBAL; type < GUC_CAPTURE_LIST_TYPE_MAX; type++) { + struct gcap_reg_list_info *reginfo = &node->reginfo[type]; + struct guc_mmio_reg *regs = reginfo->regs; + + for (i = 0; i < reginfo->num_regs; i++) + cp_reg_to_snapshot(type, hwe_guc_class, regs[i].offset, regs[i].value, + &snapshot->reg); + } +} + +/** + * xe_hw_engine_find_and_copy_guc_capture_snapshot - Take a engine snapshot from GuC capture. + * @hwe: Xe HW Engine. + * @snapshot: Xe HW Engine snapshot object to save data, copied from error capture + * + * This can be printed out in a later stage like during dev_coredump + * analysis. + * + * Returns: None + */ +void +xe_hw_engine_find_and_copy_guc_capture_snapshot(struct xe_hw_engine *hwe, + struct xe_hw_engine_snapshot *snapshot) +{ + struct xe_gt *gt = hwe->gt; + struct xe_device *xe = gt_to_xe(gt); + struct xe_guc *guc = >->uc.guc; + struct __guc_capture_parsed_output *n, *ntmp; + struct xe_devcoredump *devcoredump = &xe->devcoredump; + struct list_head *list = &guc->capture->outlist; + struct xe_sched_job *job = devcoredump->job; + struct xe_guc_submit_exec_queue_snapshot *ge = devcoredump->snapshot.ge; + u16 guc_id = ge->guc.id; + u32 lrca; + u16 hwe_guc_class = xe_engine_class_to_guc_class(hwe->class); + + lrca = xe_lrc_ggtt_addr(job->q->lrc[0]) & LRC_GTT_ADDRESS_MASK; + + /* + * Look for a matching GuC reported error capture node from + * the internal output link-list based on engine class and instance. + */ + list_for_each_entry_safe(n, ntmp, list, link) { + if (n->eng_class == hwe_guc_class && n->eng_inst == hwe->instance && + n->guc_id == guc_id && (n->lrca & LRC_GTT_ADDRESS_MASK) == lrca) { + guc_capture_parse_reglist(n, snapshot, hwe_guc_class); + list_del(&n->link); + return; + } + } +} + +void xe_guc_capture_free(struct xe_guc *guc) +{ + if (guc->capture && !list_empty(&guc->capture->outlist)) { + struct __guc_capture_parsed_output *n, *ntmp; + + list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) { + list_del(&n->link); + /* put node back to cache list */ + /* No need to init here, guc_capture_get_prealloc_node init it later */ + guc_capture_add_node_to_cachelist(guc->capture, n); + } + } +} + int xe_guc_capture_init(struct xe_guc *guc) { guc->capture = drmm_kzalloc(guc_to_drm(guc), sizeof(*guc->capture), GFP_KERNEL); @@ -574,7 +1404,9 @@ int xe_guc_capture_init(struct xe_guc *guc) return -ENOMEM; guc->capture->reglists = guc_capture_get_device_reglist(guc); - check_guc_capture_size(guc); + INIT_LIST_HEAD(&guc->capture->outlist); + INIT_LIST_HEAD(&guc->capture->cachelist); + return 0; } diff --git a/drivers/gpu/drm/xe/xe_guc_capture.h b/drivers/gpu/drm/xe/xe_guc_capture.h index a62b1dbd47a6..c0bada99c9ec 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture.h +++ b/drivers/gpu/drm/xe/xe_guc_capture.h @@ -10,6 +10,8 @@ #include "regs/xe_reg_defs.h" struct xe_guc; +struct xe_hw_engine; +struct xe_hw_engine_snapshot; /* * struct __guc_mmio_reg_descr / struct __guc_mmio_reg_descr_group @@ -25,6 +27,7 @@ struct __guc_mmio_reg_descr { u32 flags; u32 mask; const char *regname; + u32 position_in_snapshot; }; struct __guc_mmio_reg_descr_group { @@ -36,9 +39,15 @@ struct __guc_mmio_reg_descr_group { struct __guc_mmio_reg_descr *extlist; /* only used for steered registers */ }; +void xe_guc_capture_process(struct xe_guc *guc); int xe_guc_capture_getlist(struct xe_guc *guc, u32 owner, u32 type, u32 classid, void **outptr); int xe_guc_capture_getlistsize(struct xe_guc *guc, u32 owner, u32 type, u32 classid, size_t *size); int xe_guc_capture_getnullheader(struct xe_guc *guc, void **outptr, size_t *size); +const struct __guc_mmio_reg_descr_group * +xe_guc_capture_get_reg_desc_list(u32 owner, u32 type, u32 engine_classid); +void xe_hw_engine_find_and_copy_guc_capture_snapshot(struct xe_hw_engine *hwe, + struct xe_hw_engine_snapshot *snapshot); +void xe_guc_capture_free(struct xe_guc *guc); int xe_guc_capture_init(struct xe_guc *guc); #endif /* _XE_GUC_CAPTURE_H */ diff --git a/drivers/gpu/drm/xe/xe_guc_capture_fwif.h b/drivers/gpu/drm/xe/xe_guc_capture_fwif.h index 199e3c0108a4..5ef8c20fe9bc 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture_fwif.h +++ b/drivers/gpu/drm/xe/xe_guc_capture_fwif.h @@ -10,6 +10,51 @@ #include "xe_guc_fwif.h" +/* + * struct __guc_capture_bufstate + * + * Book-keeping structure used to track read and write pointers + * as we extract error capture data from the GuC-log-buffer's + * error-capture region as a stream of dwords. + */ +struct __guc_capture_bufstate { + u32 size; + u32 data_offset; + u32 rd; + u32 wr; +}; + +/* + * struct __guc_capture_parsed_output - extracted error capture node + * + * A single unit of extracted error-capture output data grouped together + * at an engine-instance level. We keep these nodes in a linked list. + * See cachelist and outlist below. + */ +struct __guc_capture_parsed_output { + /* + * A single set of 3 capture lists: a global-list + * an engine-class-list and an engine-instance list. + * outlist in __guc_capture_parsed_output will keep + * a linked list of these nodes that will eventually + * be detached from outlist and attached into to + * xe_codedump in response to a context reset + */ + struct list_head link; + bool is_partial; + u32 eng_class; + u32 eng_inst; + u32 guc_id; + u32 lrca; + struct gcap_reg_list_info { + u32 vfid; + u32 num_regs; + struct guc_mmio_reg *regs; + } reginfo[GUC_CAPTURE_LIST_TYPE_MAX]; +#define GCAP_PARSED_REGLIST_INDEX_GLOBAL BIT(GUC_CAPTURE_LIST_TYPE_GLOBAL) +#define GCAP_PARSED_REGLIST_INDEX_ENGCLASS BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS) +}; + /* * struct guc_debug_capture_list_header / struct guc_debug_capture_list * diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c index c1f258348f5c..865b58bb4fd9 100644 --- a/drivers/gpu/drm/xe/xe_guc_ct.c +++ b/drivers/gpu/drm/xe/xe_guc_ct.c @@ -1045,6 +1045,8 @@ static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len) /* Selftest only at the moment */ break; case XE_GUC_ACTION_STATE_CAPTURE_NOTIFICATION: + ret = xe_guc_error_capture_handler(guc, payload, adj_len); + break; case XE_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE: /* FIXME: Handle this */ break; diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h index 908298791c93..f8f9c76eb7ac 100644 --- a/drivers/gpu/drm/xe/xe_guc_fwif.h +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h @@ -206,6 +206,12 @@ enum guc_capture_type { GUC_CAPTURE_LIST_TYPE_MAX, }; +/* GuC support limited registers range to be captured for debug purpose, + * for unsupported registers, direct read is the only way to save the data. + * GuC capture handling will ignore all lists with this type: GUC_CAPTURE_LIST_TYPE_DIRECT_READ + */ +#define GUC_CAPTURE_LIST_TYPE_DIRECT_READ GUC_CAPTURE_LIST_TYPE_MAX + /* Class indecies for capture_class and capture_instance arrays */ enum { GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE = 0, diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c index 47aab04cf34f..f02f4c0c9568 100644 --- a/drivers/gpu/drm/xe/xe_guc_submit.c +++ b/drivers/gpu/drm/xe/xe_guc_submit.c @@ -25,6 +25,7 @@ #include "xe_gt.h" #include "xe_gt_printk.h" #include "xe_guc.h" +#include "xe_guc_capture.h" #include "xe_guc_ct.h" #include "xe_guc_exec_queue_types.h" #include "xe_guc_id_mgr.h" @@ -769,7 +770,7 @@ static void guc_exec_queue_free_job(struct drm_sched_job *drm_job) xe_sched_job_put(job); } -static int guc_read_stopped(struct xe_guc *guc) +int xe_guc_read_stopped(struct xe_guc *guc) { return atomic_read(&guc->submission_state.stopped); } @@ -791,7 +792,7 @@ static void disable_scheduling_deregister(struct xe_guc *guc, set_min_preemption_timeout(guc, q); smp_rmb(); ret = wait_event_timeout(guc->ct.wq, !exec_queue_pending_enable(q) || - guc_read_stopped(guc), HZ * 5); + xe_guc_read_stopped(guc), HZ * 5); if (!ret) { struct xe_gpu_scheduler *sched = &q->guc->sched; @@ -906,7 +907,7 @@ static void xe_guc_exec_queue_lr_cleanup(struct work_struct *w) */ ret = wait_event_timeout(guc->ct.wq, !exec_queue_pending_disable(q) || - guc_read_stopped(guc), HZ * 5); + xe_guc_read_stopped(guc), HZ * 5); if (!ret) { drm_warn(&xe->drm, "Schedule disable failed to respond"); xe_sched_submission_start(sched); @@ -929,6 +930,8 @@ guc_exec_queue_timedout_job(struct drm_sched_job *drm_job) int err = -ETIME; int i = 0; bool wedged; + bool reset_status = exec_queue_reset(q); + bool guc_en = xe_device_uc_enabled(xe); /* * TDR has fired before free job worker. Common if exec queue @@ -948,7 +951,15 @@ guc_exec_queue_timedout_job(struct drm_sched_job *drm_job) xe_gt_WARN(q->gt, q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q), "VM job timed out on non-killed execqueue\n"); - if (!exec_queue_killed(q)) + /* take devcoredump on: + * 1. GuC not enabled + * 2. GuC enabled with GuC reset status == 1 + * When GuC enabled, register value is captured by GuC, GuC will notify host + * with capture notification message, which is right before reset. + * GuC reset status 1 also means capture ready. + * If not ready, will take snapshot after wait event within this function. + */ + if (!exec_queue_killed(q) && (!guc_en || (guc_en && reset_status))) xe_devcoredump(job); trace_xe_sched_job_timedout(job); @@ -996,8 +1007,8 @@ guc_exec_queue_timedout_job(struct drm_sched_job *drm_job) smp_rmb(); ret = wait_event_timeout(guc->ct.wq, !exec_queue_pending_disable(q) || - guc_read_stopped(guc), HZ * 5); - if (!ret || guc_read_stopped(guc)) { + xe_guc_read_stopped(guc), HZ * 5); + if (!ret || xe_guc_read_stopped(guc)) { drm_warn(&xe->drm, "Schedule disable failed to respond"); xe_sched_add_pending_job(sched, job); xe_sched_submission_start(sched); @@ -1007,6 +1018,10 @@ guc_exec_queue_timedout_job(struct drm_sched_job *drm_job) } } + /* When entring this function, if capture/reset not ready, now is time to take snapshot */ + if (!exec_queue_killed(q) && guc_en && !reset_status) + xe_devcoredump(job); + /* Stop fence signaling */ xe_hw_fence_irq_stop(q->fence_irq); @@ -1112,7 +1127,7 @@ static void suspend_fence_signal(struct xe_exec_queue *q) struct xe_device *xe = guc_to_xe(guc); xe_assert(xe, exec_queue_suspended(q) || exec_queue_killed(q) || - guc_read_stopped(guc)); + xe_guc_read_stopped(guc)); xe_assert(xe, q->guc->suspend_pending); q->guc->suspend_pending = false; @@ -1128,9 +1143,9 @@ static void __guc_exec_queue_process_msg_suspend(struct xe_sched_msg *msg) if (guc_exec_queue_allowed_to_change_state(q) && !exec_queue_suspended(q) && exec_queue_enabled(q)) { wait_event(guc->ct.wq, q->guc->resume_time != RESUME_PENDING || - guc_read_stopped(guc)); + xe_guc_read_stopped(guc)); - if (!guc_read_stopped(guc)) { + if (!xe_guc_read_stopped(guc)) { MAKE_SCHED_CONTEXT_ACTION(q, DISABLE); s64 since_resume_ms = ktime_ms_delta(ktime_get(), @@ -1258,7 +1273,7 @@ static int guc_exec_queue_init(struct xe_exec_queue *q) q->entity = &ge->entity; - if (guc_read_stopped(guc)) + if (xe_guc_read_stopped(guc)) xe_sched_stop(sched); mutex_unlock(&guc->submission_state.lock); @@ -1385,7 +1400,7 @@ static void guc_exec_queue_suspend_wait(struct xe_exec_queue *q) struct xe_guc *guc = exec_queue_to_guc(q); wait_event(q->guc->suspend_wait, !q->guc->suspend_pending || - guc_read_stopped(guc)); + xe_guc_read_stopped(guc)); } static void guc_exec_queue_resume(struct xe_exec_queue *q) @@ -1495,7 +1510,7 @@ int xe_guc_submit_reset_prepare(struct xe_guc *guc) void xe_guc_submit_reset_wait(struct xe_guc *guc) { - wait_event(guc->ct.wq, !guc_read_stopped(guc)); + wait_event(guc->ct.wq, !xe_guc_read_stopped(guc)); } void xe_guc_submit_stop(struct xe_guc *guc) @@ -1504,7 +1519,7 @@ void xe_guc_submit_stop(struct xe_guc *guc) unsigned long index; struct xe_device *xe = guc_to_xe(guc); - xe_assert(xe, guc_read_stopped(guc) == 1); + xe_assert(xe, xe_guc_read_stopped(guc) == 1); mutex_lock(&guc->submission_state.lock); @@ -1542,7 +1557,7 @@ int xe_guc_submit_start(struct xe_guc *guc) unsigned long index; struct xe_device *xe = guc_to_xe(guc); - xe_assert(xe, guc_read_stopped(guc) == 1); + xe_assert(xe, xe_guc_read_stopped(guc) == 1); mutex_lock(&guc->submission_state.lock); atomic_dec(&guc->submission_state.stopped); @@ -1698,8 +1713,6 @@ int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) xe_gt_info(gt, "Engine reset: engine_class=%s, logical_mask: 0x%x, guc_id=%d", xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id); - /* FIXME: Do error capture, most likely async */ - trace_xe_exec_queue_reset(q); /* @@ -1715,6 +1728,24 @@ int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) return 0; } +int xe_guc_error_capture_handler(struct xe_guc *guc, u32 *msg, u32 len) +{ + u32 status; + + if (unlikely(len != 1)) { + xe_gt_dbg(guc_to_gt(guc), "Invalid length %u", len); + return -EPROTO; + } + + status = msg[0] & XE_GUC_STATE_CAPTURE_EVENT_STATUS_MASK; + if (status == XE_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE) + xe_gt_warn(guc_to_gt(guc), "G2H-Error capture no space"); + + xe_guc_capture_process(guc); + + return 0; +} + int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, u32 len) { diff --git a/drivers/gpu/drm/xe/xe_guc_submit.h b/drivers/gpu/drm/xe/xe_guc_submit.h index 4ad5f4c1b084..d92256de473e 100644 --- a/drivers/gpu/drm/xe/xe_guc_submit.h +++ b/drivers/gpu/drm/xe/xe_guc_submit.h @@ -19,12 +19,14 @@ void xe_guc_submit_reset_wait(struct xe_guc *guc); void xe_guc_submit_stop(struct xe_guc *guc); int xe_guc_submit_start(struct xe_guc *guc); +int xe_guc_read_stopped(struct xe_guc *guc); int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len); int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len); int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len); int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, u32 len); int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len); +int xe_guc_error_capture_handler(struct xe_guc *guc, u32 *msg, u32 len); struct xe_guc_submit_exec_queue_snapshot * xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q); diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c index 0a83506e1ad8..3bc88fbad952 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.c +++ b/drivers/gpu/drm/xe/xe_hw_engine.c @@ -20,6 +20,9 @@ #include "xe_gt_printk.h" #include "xe_gt_mcr.h" #include "xe_gt_topology.h" +#include "xe_guc.h" +#include "xe_guc_capture.h" +#include "xe_guc_capture_fwif.h" #include "xe_hw_fence.h" #include "xe_irq.h" #include "xe_lrc.h" @@ -287,6 +290,7 @@ static void hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg, static u32 hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg) { xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base)); + xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain); reg.addr += hwe->mmio_base; @@ -825,6 +829,62 @@ xe_hw_engine_snapshot_instdone_capture(struct xe_hw_engine *hwe, } } +static void +xe_hw_engine_snapshot_from_hw_by_type(struct xe_hw_engine *hwe, + struct xe_hw_engine_snapshot *snapshot, int type) +{ + const struct __guc_mmio_reg_descr_group *list; + u16 capture_class = xe_engine_class_to_guc_capture_class(hwe->class); + int i; + + list = xe_guc_capture_get_reg_desc_list(GUC_CAPTURE_LIST_INDEX_PF, type, capture_class); + if (!list) + return; + + for (i = 0; i < list->num_regs; i++) { + u32 *field; + + /* loop until extra operation registers zone */ + if (list->list[i].reg.addr == XE_GUC_SNAPSHOT_EXTRA_OPERATION_REGS_START_REG_ADDR) + break; + + field = (u32 *)((uintptr_t)&snapshot->reg + + list->list[i].position_in_snapshot); + if (type == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) + *field = hw_engine_mmio_read32(hwe, list->list[i].reg); + else + *field = xe_mmio_read32(hwe->gt, list->list[i].reg); + } +} + +/** + * xe_hw_engine_snapshot_from_hw - Take a quick engine snapshot from HW. + * @hwe: Xe HW Engine. + * @snapshot: Point to the Xe HW Engine snapshot object to save data. + * + * This can be printed out in a later stage like during dev_coredump + * analysis. + * + * Returns: None + */ +static void +xe_hw_engine_snapshot_from_hw(struct xe_hw_engine *hwe, struct xe_hw_engine_snapshot *snapshot) +{ + int type; + + for (type = GUC_CAPTURE_LIST_TYPE_GLOBAL; type < GUC_CAPTURE_LIST_TYPE_MAX; type++) + xe_hw_engine_snapshot_from_hw_by_type(hwe, snapshot, type); + + /* Extra operation required registers zone - start */ + if (xe_gt_has_indirect_ring_state(hwe->gt)) + snapshot->reg.indirect_ring_state = + hw_engine_mmio_read32(hwe, INDIRECT_RING_STATE(0)); + /* Extra operation required registers zone - End */ + + /* Capture steering registers */ + xe_hw_engine_snapshot_instdone_capture(hwe, snapshot); +} + /** * xe_hw_engine_snapshot_capture - Take a quick snapshot of the HW Engine. * @hwe: Xe HW Engine. @@ -839,8 +899,12 @@ struct xe_hw_engine_snapshot * xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe) { struct xe_hw_engine_snapshot *snapshot; + struct xe_gt *gt = hwe->gt; + struct xe_device *xe = gt_to_xe(gt); + struct xe_guc *guc = >->uc.guc; size_t len; - u64 val; + u32 i; + bool endian_convert_required; if (!xe_hw_engine_is_valid(hwe)) return NULL; @@ -850,6 +914,9 @@ xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe) if (!snapshot) return NULL; + i = 0x01020304; + endian_convert_required = (i != le32_to_cpu(i)); + /* Because XE_MAX_DSS_FUSE_BITS is defined in xe_gt_types.h and it * includes xe_hw_engine_types.h the length of this 3 registers can't be * set in struct xe_hw_engine_snapshot, so here doing additional @@ -881,62 +948,35 @@ xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe) snapshot->mmio_base = hwe->mmio_base; /* no more VF accessible data below this point */ - if (IS_SRIOV_VF(gt_to_xe(hwe->gt))) + if (IS_SRIOV_VF(xe)) return snapshot; - snapshot->reg.ring_execlist_status = - hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0)); - val = hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0)); - snapshot->reg.ring_execlist_status |= val << 32; - - snapshot->reg.ring_execlist_sq_contents = - hw_engine_mmio_read32(hwe, RING_EXECLIST_SQ_CONTENTS_LO(0)); - val = hw_engine_mmio_read32(hwe, RING_EXECLIST_SQ_CONTENTS_HI(0)); - snapshot->reg.ring_execlist_sq_contents |= val << 32; - - snapshot->reg.ring_acthd = hw_engine_mmio_read32(hwe, RING_ACTHD(0)); - val = hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0)); - snapshot->reg.ring_acthd |= val << 32; - - snapshot->reg.ring_bbaddr = hw_engine_mmio_read32(hwe, RING_BBADDR(0)); - val = hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0)); - snapshot->reg.ring_bbaddr |= val << 32; - - snapshot->reg.ring_dma_fadd = - hw_engine_mmio_read32(hwe, RING_DMA_FADD(0)); - val = hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0)); - snapshot->reg.ring_dma_fadd |= val << 32; - - snapshot->reg.ring_hwstam = hw_engine_mmio_read32(hwe, RING_HWSTAM(0)); - snapshot->reg.ring_hws_pga = hw_engine_mmio_read32(hwe, RING_HWS_PGA(0)); - snapshot->reg.ring_start = hw_engine_mmio_read32(hwe, RING_START(0)); - if (GRAPHICS_VERx100(hwe->gt->tile->xe) >= 2000) { - val = hw_engine_mmio_read32(hwe, RING_START_UDW(0)); - snapshot->reg.ring_start |= val << 32; - } - if (xe_gt_has_indirect_ring_state(hwe->gt)) { - snapshot->reg.indirect_ring_state = - hw_engine_mmio_read32(hwe, INDIRECT_RING_STATE(0)); + /* Check GuC settings, job is set and capture outlist not empty, + * otherwise take it from engine + */ + if (xe_device_uc_enabled(xe) && xe->wedged.mode >= 1 && + !list_empty(&guc->capture->outlist) && xe->devcoredump.job) + xe_hw_engine_find_and_copy_guc_capture_snapshot(hwe, snapshot); + else + xe_hw_engine_snapshot_from_hw(hwe, snapshot); + + /* Read registers defined in "Direct read" list */ + xe_hw_engine_snapshot_from_hw_by_type(hwe, snapshot, GUC_CAPTURE_LIST_TYPE_DIRECT_READ); + + /* appy mask for ring head and tail */ + snapshot->reg.ring_head &= HEAD_ADDR; + snapshot->reg.ring_tail &= TAIL_ADDR; + + /* adjust u64 endine in snapshot if needed */ + if (endian_convert_required) { + for (i = 0; i < XE_GUC_SNAPSHOT_REGS_U32_START_OFFSET; i += sizeof(u64)) { + u64 *pdata = (u64 *)((ulong)&snapshot->reg + i); + u32 *pl = (u32 *)pdata; + u32 *ph = (u32 *)((ulong)pdata + 4); + *pdata = ((u64)*ph) << 32 | *pl; + } } - snapshot->reg.ring_head = - hw_engine_mmio_read32(hwe, RING_HEAD(0)) & HEAD_ADDR; - snapshot->reg.ring_tail = - hw_engine_mmio_read32(hwe, RING_TAIL(0)) & TAIL_ADDR; - snapshot->reg.ring_ctl = hw_engine_mmio_read32(hwe, RING_CTL(0)); - snapshot->reg.ring_mi_mode = - hw_engine_mmio_read32(hwe, RING_MI_MODE(0)); - snapshot->reg.ring_mode = hw_engine_mmio_read32(hwe, RING_MODE(0)); - snapshot->reg.ring_imr = hw_engine_mmio_read32(hwe, RING_IMR(0)); - snapshot->reg.ring_esr = hw_engine_mmio_read32(hwe, RING_ESR(0)); - snapshot->reg.ring_emr = hw_engine_mmio_read32(hwe, RING_EMR(0)); - snapshot->reg.ring_eir = hw_engine_mmio_read32(hwe, RING_EIR(0)); - snapshot->reg.ipehr = hw_engine_mmio_read32(hwe, RING_IPEHR(0)); - xe_hw_engine_snapshot_instdone_capture(hwe, snapshot); - - if (snapshot->hwe->class == XE_ENGINE_CLASS_COMPUTE) - snapshot->reg.rcu_mode = xe_mmio_read32(hwe->gt, RCU_MODE); - return snapshot; } @@ -993,6 +1033,8 @@ xe_hw_engine_snapshot_instdone_print(struct xe_hw_engine_snapshot *snapshot, str void xe_hw_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot, struct drm_printer *p) { + int i, type; + if (!snapshot) return; @@ -1001,34 +1043,52 @@ void xe_hw_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot, snapshot->logical_instance); drm_printf(p, "\tForcewake: domain 0x%x, ref %d\n", snapshot->forcewake.domain, snapshot->forcewake.ref); - drm_printf(p, "\tHWSTAM: 0x%08x\n", snapshot->reg.ring_hwstam); - drm_printf(p, "\tRING_HWS_PGA: 0x%08x\n", snapshot->reg.ring_hws_pga); - drm_printf(p, "\tRING_EXECLIST_STATUS: 0x%016llx\n", - snapshot->reg.ring_execlist_status); - drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS: 0x%016llx\n", - snapshot->reg.ring_execlist_sq_contents); - drm_printf(p, "\tRING_START: 0x%016llx\n", snapshot->reg.ring_start); - drm_printf(p, "\tRING_HEAD: 0x%08x\n", snapshot->reg.ring_head); - drm_printf(p, "\tRING_TAIL: 0x%08x\n", snapshot->reg.ring_tail); - drm_printf(p, "\tRING_CTL: 0x%08x\n", snapshot->reg.ring_ctl); - drm_printf(p, "\tRING_MI_MODE: 0x%08x\n", snapshot->reg.ring_mi_mode); - drm_printf(p, "\tRING_MODE: 0x%08x\n", - snapshot->reg.ring_mode); - drm_printf(p, "\tRING_IMR: 0x%08x\n", snapshot->reg.ring_imr); - drm_printf(p, "\tRING_ESR: 0x%08x\n", snapshot->reg.ring_esr); - drm_printf(p, "\tRING_EMR: 0x%08x\n", snapshot->reg.ring_emr); - drm_printf(p, "\tRING_EIR: 0x%08x\n", snapshot->reg.ring_eir); - drm_printf(p, "\tACTHD: 0x%016llx\n", snapshot->reg.ring_acthd); - drm_printf(p, "\tBBADDR: 0x%016llx\n", snapshot->reg.ring_bbaddr); - drm_printf(p, "\tDMA_FADDR: 0x%016llx\n", snapshot->reg.ring_dma_fadd); - drm_printf(p, "\tINDIRECT_RING_STATE: 0x%08x\n", - snapshot->reg.indirect_ring_state); - drm_printf(p, "\tIPEHR: 0x%08x\n", snapshot->reg.ipehr); + + /* Print will include direct read list in this main loop */ + for (type = GUC_CAPTURE_LIST_TYPE_GLOBAL; type <= GUC_CAPTURE_LIST_TYPE_DIRECT_READ; + type++) { + const struct __guc_mmio_reg_descr_group *list; + u16 capture_class = xe_engine_class_to_guc_capture_class(snapshot->hwe->class); + + /* Capture engine registers */ + list = xe_guc_capture_get_reg_desc_list(GUC_CAPTURE_LIST_INDEX_PF, type, + capture_class); + if (!list) + continue; + + /* loop 32bit registers until 64 bit registers */ + for (i = 0; i < list->num_regs; i++) { + u32 *field; + + if (list->list[i].reg.addr == XE_GUC_SNAPSHOT_REGS_U64_START_REG_ADDR) + break; + field = (u32 *)((uintptr_t)&snapshot->reg + + list->list[i].position_in_snapshot); + drm_printf(p, "\t%s: 0x%08x\n", list->list[i].regname, *field); + } + + if (type != GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) + continue; /* 64bit and special registers is for engine instance only */ + + /* loop 64 bit registers until special registers */ + for (; i < list->num_regs; i += 2) { + u64 *field; + + if (list->list[i].reg.addr == + XE_GUC_SNAPSHOT_EXTRA_OPERATION_REGS_START_REG_ADDR) + break; + field = (u64 *)((uintptr_t)&snapshot->reg + + list->list[i].position_in_snapshot); + drm_printf(p, "\t%s: 0x%016llx\n", list->list[i].regname, *field); + } + + /* Handling special registers - Start */ + drm_printf(p, "\tINDIRECT_RING_STATE: 0x%08x\n", snapshot->reg.indirect_ring_state); + /* Handling special registers - End */ + } + xe_hw_engine_snapshot_instdone_print(snapshot, p); - if (snapshot->hwe->class == XE_ENGINE_CLASS_COMPUTE) - drm_printf(p, "\tRCU_MODE: 0x%08x\n", - snapshot->reg.rcu_mode); drm_puts(p, "\n"); } diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h index 580bbd7e83b2..617101dca272 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine_types.h +++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h @@ -150,6 +150,106 @@ struct xe_hw_engine { struct xe_hw_engine_class_intf *eclass; }; +/** + * struct xe_hw_engine_snapshot - Hardware engine snapshot + * + * Contains the snapshot of useful hardware engine info and registers. + */ +struct snapshot_regs { + /* Engine instance type - start */ + /* 64 bit registers zone - start */ + /* + * u64 data captured by 2 u32s from GuC or by hw read. + * Save data into this u64 zone will always write in format of: + * offset + 0000: [low 32] + * offset + 0004: [high 32] + * Once all data captured, data will be converted to CPU endian order if needed at the + * end of xe_hw_engine_snapshot_capture + */ + #define XE_GUC_SNAPSHOT_REGS_U64_START_REG_ADDR RING_ACTHD(0).addr + /** @ring_acthd: RING_ACTHD */ + u64 ring_acthd; + /** @ring_bbaddr: RING_BBADDR */ + u64 ring_bbaddr; + /** @ring_start: RING_START */ + u64 ring_start; + /** @ring_dma_fadd: RING_DMA_FADD */ + u64 ring_dma_fadd; + /** @ring_execlist_status: RING_EXECLIST_STATUS */ + u64 ring_execlist_status; + /** @ring_execlist_sq_contents: RING_EXECLIST_SQ_CONTENTS */ + u64 ring_execlist_sq_contents; + /* 64 bit registers zone - end */ + + /* 32 bit registers zone - start */ + /** @reg.ring_hwstam: RING_HWSTAM */ + u32 ring_hwstam; + #define XE_GUC_SNAPSHOT_REGS_U32_START_OFFSET offsetof(struct snapshot_regs, ring_hwstam) + + /** @reg.ring_hws_pga: RING_HWS_PGA */ + u32 ring_hws_pga; + u32 ring_head; + /** @reg.ring_tail: RING_TAIL */ + u32 ring_tail; + /** @reg.ring_ctl: RING_CTL */ + u32 ring_ctl; + /** @reg.ring_mi_mode: RING_MI_MODE */ + u32 ring_mi_mode; + /** @reg.ring_mode: RING_MODE */ + u32 ring_mode; + /** @reg.ring_imr: RING_IMR */ + u32 ring_imr; + /** @reg.ring_esr: RING_ESR */ + u32 ring_esr; + /** @reg.ring_emr: RING_EMR */ + u32 ring_emr; + /** @reg.ring_eir: RING_EIR */ + u32 ring_eir; + /** @reg.ipehr: IPEHR */ + u32 ipehr; + /* Engine instance type - end */ + + /* Engine class type - start */ + /** @reg.rcu_mode: RCU_MODE */ + u32 rcu_mode; + /** @reg.sfc_done_[0-3]: SFC_DONE[0-3] */ + u32 sfc_done_0; + u32 sfc_done_1; + u32 sfc_done_2; + u32 sfc_done_3; + /* Engine class type - end */ + + /* Global type - start */ + /** @reg.forcewake_gt: FORCEWAKE_GT */ + u32 forcewake_gt; + /* Global type - end */ + + /* Extra operation Registers zone - start */ + /* registers requires extra code to handling */ + #define XE_GUC_SNAPSHOT_EXTRA_OPERATION_REGS_START_REG_ADDR INDIRECT_RING_STATE(0).addr + /** @reg.indirect_ring_state: INDIRECT_RING_STATE */ + u32 indirect_ring_state; + /* Special registers zone - end */ + + /* Steering registers */ + struct { + /** @reg.instdone.ring: RING_INSTDONE */ + u32 ring; + /** @reg.instdone.slice_common: SC_INSTDONE */ + u32 *slice_common; + /** @reg.instdone.slice_common_extra: SC_INSTDONE_EXTRA */ + u32 *slice_common_extra; + /** @reg.instdone.slice_common_extra2: SC_INSTDONE_EXTRA2 */ + u32 *slice_common_extra2; + /** @reg.instdone.sampler: SAMPLER_INSTDONE */ + u32 *sampler; + /** @reg.instdone.row: ROW_INSTDONE */ + u32 *row; + /** @reg.instdone.geom_svg: INSTDONE_GEOM_SVGUNIT */ + u32 *geom_svg; + } instdone; +}; + /** * struct xe_hw_engine_snapshot - Hardware engine snapshot * @@ -172,64 +272,7 @@ struct xe_hw_engine_snapshot { /** @mmio_base: MMIO base address of this hw engine*/ u32 mmio_base; /** @reg: Useful MMIO register snapshot */ - struct { - /** @reg.ring_execlist_status: RING_EXECLIST_STATUS */ - u64 ring_execlist_status; - /** @reg.ring_execlist_sq_contents: RING_EXECLIST_SQ_CONTENTS */ - u64 ring_execlist_sq_contents; - /** @reg.ring_acthd: RING_ACTHD */ - u64 ring_acthd; - /** @reg.ring_bbaddr: RING_BBADDR */ - u64 ring_bbaddr; - /** @reg.ring_dma_fadd: RING_DMA_FADD */ - u64 ring_dma_fadd; - /** @reg.ring_hwstam: RING_HWSTAM */ - u32 ring_hwstam; - /** @reg.ring_hws_pga: RING_HWS_PGA */ - u32 ring_hws_pga; - /** @reg.ring_start: RING_START */ - u64 ring_start; - /** @reg.ring_head: RING_HEAD */ - u32 ring_head; - /** @reg.ring_tail: RING_TAIL */ - u32 ring_tail; - /** @reg.ring_ctl: RING_CTL */ - u32 ring_ctl; - /** @reg.ring_mi_mode: RING_MI_MODE */ - u32 ring_mi_mode; - /** @reg.ring_mode: RING_MODE */ - u32 ring_mode; - /** @reg.ring_imr: RING_IMR */ - u32 ring_imr; - /** @reg.ring_esr: RING_ESR */ - u32 ring_esr; - /** @reg.ring_emr: RING_EMR */ - u32 ring_emr; - /** @reg.ring_eir: RING_EIR */ - u32 ring_eir; - /** @reg.indirect_ring_state: INDIRECT_RING_STATE */ - u32 indirect_ring_state; - /** @reg.ipehr: IPEHR */ - u32 ipehr; - /** @reg.rcu_mode: RCU_MODE */ - u32 rcu_mode; - struct { - /** @reg.instdone.ring: RING_INSTDONE */ - u32 ring; - /** @reg.instdone.slice_common: SC_INSTDONE */ - u32 *slice_common; - /** @reg.instdone.slice_common_extra: SC_INSTDONE_EXTRA */ - u32 *slice_common_extra; - /** @reg.instdone.slice_common_extra2: SC_INSTDONE_EXTRA2 */ - u32 *slice_common_extra2; - /** @reg.instdone.sampler: SAMPLER_INSTDONE */ - u32 *sampler; - /** @reg.instdone.row: ROW_INSTDONE */ - u32 *row; - /** @reg.instdone.geom_svg: INSTDONE_GEOM_SVGUNIT */ - u32 *geom_svg; - } instdone; - } reg; + struct snapshot_regs reg; }; #endif diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h index 882c3437ba5c..8c83601fc695 100644 --- a/drivers/gpu/drm/xe/xe_lrc.h +++ b/drivers/gpu/drm/xe/xe_lrc.h @@ -21,6 +21,7 @@ struct xe_lrc_snapshot; struct xe_vm; #define LRC_PPHWSP_SCRATCH_ADDR (0x34 * 4) +#define LRC_GTT_ADDRESS_MASK GENMASK(31, 12) struct xe_lrc *xe_lrc_create(struct xe_hw_engine *hwe, struct xe_vm *vm, u32 ring_size); -- 2.34.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v9 4/4] drm/xe/guc: Extract GuC capture lists to register snapshot 2024-06-07 0:07 ` [PATCH v9 4/4] drm/xe/guc: Extract GuC capture lists to register snapshot Zhanjun Dong @ 2024-06-13 23:26 ` Teres Alexis, Alan Previn 2024-06-19 20:17 ` Dong, Zhanjun 2024-06-14 12:31 ` Michal Wajdeczko 1 sibling, 1 reply; 24+ messages in thread From: Teres Alexis, Alan Previn @ 2024-06-13 23:26 UTC (permalink / raw) To: Dong, Zhanjun, intel-xe@lists.freedesktop.org alan: Hi there Zhanjun, as per offline conversation, i was surprised to see you squash the "Guc-error-capture-extraction" together with the "Plumb GuC-capture into dev coredump" patch but now realize i made a regrettable typo in my rev8 review comments - when i mentioned about posisbly squashing pre-allocate-nodes with node-extraction i said "patch 4 and patch 6" but what i meant was "patch 4 and patch 5". I'm terribly sorry about this mistake. Since we know that you have to redo this patch anyways based on offline conversation to resolve race between drm-tdr vs guc-context-reset, thanks for agreeing to keep extraction separate again. And ofc we don't need pre-allocating of nodes now. On Thu, 2024-06-06 at 17:07 -0700, Zhanjun Dong wrote: > Upon the G2H Notify-Err-Capture event, parse through the > GuC Log Buffer (error-capture-subregion) and generate one or > more capture-nodes. A single node represents a single "engine- > instance-capture-dump" and contains at least 3 register lists: > global, engine-class and engine-instance. An internal link > list is maintained to store one or more nodes. > Because the link-list node generation happen before the call > to devcoredump, duplicate global and engine-class register > lists for each engine-instance register dump if we find > dependent-engine resets in a engine-capture-group. > When xe_devcoredump calls into snapshot_from_capture_engine, > we detach the matching node (guc-id, LRCA, etc) from the link list > above and attach it to snapshot_regs structure when have > matching LRCA/guc-id/engine-instance. > > To avoid dynamically allocate the output nodes during gt reset, > pre-allocate a fixed number of empty nodes up front (at the > time of ADS registration) that we can consume from or return to > an internal cached list of nodes. > Add guc capture data structure definition. > > Add xe_hw_engine_snapshot_from_capture to take snapshot from capture > node list. > Move snapshot register struct out of engine snapshot struct. > Add offset in snapshot register to register definition list at > xe_guc_capture.c. > Snapshot could be split into global, engine class, engine instance > and steering register zone, few macros defined to separate zones. > Support combines 2 32bit registers as a 64bit register in snapshot, > perform endian convert if needed. > > Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> > --- > drivers/gpu/drm/xe/abi/guc_actions_abi.h | 7 + > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 + > drivers/gpu/drm/xe/xe_devcoredump.c | 4 + > drivers/gpu/drm/xe/xe_devcoredump_types.h | 2 + > drivers/gpu/drm/xe/xe_guc.h | 23 + > drivers/gpu/drm/xe/xe_guc_capture.c | 876 > +++++++++++++++++++++- > drivers/gpu/drm/xe/xe_guc_capture.h | 9 + > drivers/gpu/drm/xe/xe_guc_capture_fwif.h | 45 ++ > drivers/gpu/drm/xe/xe_guc_ct.c | 2 + > drivers/gpu/drm/xe/xe_guc_fwif.h | 6 + > drivers/gpu/drm/xe/xe_guc_submit.c | 63 +- > drivers/gpu/drm/xe/xe_guc_submit.h | 2 + > drivers/gpu/drm/xe/xe_hw_engine.c | 218 ++++-- > drivers/gpu/drm/xe/xe_hw_engine_types.h | 159 ++-- > drivers/gpu/drm/xe/xe_lrc.h | 1 + > 15 files changed, 1244 insertions(+), 175 deletions(-) > > diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h > b/drivers/gpu/drm/xe/abi/guc_actions_abi.h > index 79ba98a169f9..ed1eeea34e8e 100644 > --- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h > +++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h > @@ -182,6 +182,13 @@ enum xe_guc_sleep_state_status { > #define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << > GUC_LOG_CONTROL_VERBOSITY_SHIFT) > #define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8) > > +enum intel_guc_state_capture_event_status { > + XE_GUC_STATE_CAPTURE_EVENT_STATUS_SUCCESS = 0x0, > + XE_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE = 0x1, > +}; > + > +#define XE_GUC_STATE_CAPTURE_EVENT_STATUS_MASK 0x000000FF > + > #define XE_GUC_TLB_INVAL_TYPE_SHIFT 0 > #define XE_GUC_TLB_INVAL_MODE_SHIFT 8 > /* Flush PPC or SMRO caches along with TLB invalidation request */ > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h > b/drivers/gpu/drm/xe/regs/xe_gt_regs.h > index d09b2473259f..c6bd50738e2b 100644 > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h > @@ -574,4 +574,6 @@ > #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) > #define GT_RENDER_USER_INTERRUPT REG_BIT(0) > > +#define SFC_DONE(n) XE_REG(0x1cc000 + (n) > * 0x1000) > + > #endif > diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c > b/drivers/gpu/drm/xe/xe_devcoredump.c > index d7f2d19a77c1..5e80710d3cc8 100644 > --- a/drivers/gpu/drm/xe/xe_devcoredump.c > +++ b/drivers/gpu/drm/xe/xe_devcoredump.c > @@ -16,6 +16,7 @@ > #include "xe_force_wake.h" > #include "xe_gt.h" > #include "xe_gt_printk.h" > +#include "xe_guc_capture.h" > #include "xe_guc_ct.h" > #include "xe_guc_submit.h" > #include "xe_hw_engine.h" > @@ -149,10 +150,12 @@ static void xe_devcoredump_free(void *data) > if (coredump->snapshot.hwe[i]) > xe_hw_engine_snapshot_free(coredump- > >snapshot.hwe[i]); > xe_vm_snapshot_free(coredump->snapshot.vm); > + xe_guc_capture_free(&coredump->snapshot.gt->uc.guc); > > /* To prevent stale data on next snapshot, clear everything > */ > memset(&coredump->snapshot, 0, sizeof(coredump->snapshot)); > coredump->captured = false; > + coredump->job = NULL; > drm_info(&coredump_to_xe(coredump)->drm, > "Xe device coredump has been deleted.\n"); > } > @@ -186,6 +189,7 @@ static void devcoredump_snapshot(struct > xe_devcoredump *coredump, > put_task_struct(task); > > ss->gt = q->gt; > + coredump->job = job; > INIT_WORK(&ss->work, xe_devcoredump_deferred_snap_work); > > cookie = dma_fence_begin_signalling(); > diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h > b/drivers/gpu/drm/xe/xe_devcoredump_types.h > index 923cdf72a816..c39ab73a9f6a 100644 > --- a/drivers/gpu/drm/xe/xe_devcoredump_types.h > +++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h > @@ -61,6 +61,8 @@ struct xe_devcoredump { > bool captured; > /** @snapshot: Snapshot is captured at time of the first > crash */ > struct xe_devcoredump_snapshot snapshot; > + /** @job: Point to the issue job */ > + struct xe_sched_job *job; > }; > > #endif > diff --git a/drivers/gpu/drm/xe/xe_guc.h > b/drivers/gpu/drm/xe/xe_guc.h > index ddfa855458ab..e1afda9070f4 100644 > --- a/drivers/gpu/drm/xe/xe_guc.h > +++ b/drivers/gpu/drm/xe/xe_guc.h > @@ -59,6 +59,29 @@ static inline u16 > xe_engine_class_to_guc_class(enum xe_engine_class class) > } > } > > +static inline u16 xe_guc_class_to_capture_class(uint class) > +{ > + switch (class) { > + case GUC_RENDER_CLASS: > + case GUC_COMPUTE_CLASS: > + return GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE; > + case GUC_GSC_OTHER_CLASS: > + return GUC_CAPTURE_LIST_CLASS_GSC_OTHER; > + case GUC_VIDEO_CLASS: > + case GUC_VIDEOENHANCE_CLASS: > + case GUC_BLITTER_CLASS: > + return class; > + default: > + XE_WARN_ON(class); > + return -1; > + } > +} > + > +static inline u16 xe_engine_class_to_guc_capture_class(enum > xe_engine_class class) > +{ > + return > xe_guc_class_to_capture_class(xe_guc_class_to_capture_class(class)); > +} > + > static inline struct xe_gt *guc_to_gt(struct xe_guc *guc) > { > return container_of(guc, struct xe_gt, uc.guc); > alan:snip. > +static void > +__guc_capture_create_prealloc_nodes(struct xe_guc *guc) > +{ > + struct __guc_capture_parsed_output *node = NULL; > + int i; > + > + for (i = 0; i < PREALLOC_NODES_MAX_COUNT; ++i) { > + node = guc_capture_alloc_one_node(guc); > + if (!node) { > + xe_gt_warn(guc_to_gt(guc), "Register capture > pre-alloc-cache failure\n"); > + /* dont free the priors, use what we got and > cleanup at shutdown */ > + return; > + } > + guc_capture_add_node_to_cachelist(guc->capture, > node); > + } > +} > + btw, why are we still using this pre-allocated-nodes framework and functions? i thought we decided we didn't need it for the case of Xe? (since we'll serialize the extraction-flow vs any reset-flow vs the devcoredump-printing by putting them on the same workqueue). In that case we can remove the prealocated nodes' cachelist extraction code requiring new ndes can dynamically by calling guc_capture_alloc_one_node directly alan:snip. same comment above for below hnk. > +static void > +guc_capture_create_prealloc_nodes(struct xe_guc *guc) > +{ > + /* skip if we've already done the pre-alloc */ > + if (guc->capture->max_mmio_per_node) > + return; > + > + guc->capture->max_mmio_per_node = > guc_get_max_reglist_count(guc); > + __guc_capture_create_prealloc_nodes(guc); > +} > + > +static void cp_reg_to_snapshot(int type, u16 hwe_guc_class, u32 > offset, u32 value, > + struct snapshot_regs *regs) > +{ > + int i; > + const struct __guc_mmio_reg_descr_group *list; > + > + /* Get register list for the type/class */ > + list = > xe_guc_capture_get_reg_desc_list(GUC_CAPTURE_LIST_INDEX_PF, type, > + xe_guc_class_to_captu > re_class(hwe_guc_class)); > + if (!list) > + return; > + > + for (i = 0; i < list->num_regs; i++) > + if (offset == list->list[i].reg.addr) { > + u32 *field = (u32 *)((uintptr_t)regs + list- > >list[i].position_in_snapshot); > + *field = value; > + return; > + } > +} > + > +static void guc_capture_parse_reglist(struct > __guc_capture_parsed_output *node, > + struct xe_hw_engine_snapshot > *snapshot, u16 hwe_guc_class) > +{ > + int i, type; > + > + if (!node) > + return; > + > + for (type = GUC_CAPTURE_LIST_TYPE_GLOBAL; type < > GUC_CAPTURE_LIST_TYPE_MAX; type++) { > + struct gcap_reg_list_info *reginfo = &node- > >reginfo[type]; > + struct guc_mmio_reg *regs = reginfo->regs; > + > + for (i = 0; i < reginfo->num_regs; i++) > + cp_reg_to_snapshot(type, hwe_guc_class, > regs[i].offset, regs[i].value, > + &snapshot->reg); > + } > +} > + > +/** > + * xe_hw_engine_find_and_copy_guc_capture_snapshot - Take a engine > snapshot from GuC capture. > + * @hwe: Xe HW Engine. > + * @snapshot: Xe HW Engine snapshot object to save data, copied from > error capture > + * > + * This can be printed out in a later stage like during dev_coredump > + * analysis. > + * > + * Returns: None > + */ > +void > +xe_hw_engine_find_and_copy_guc_capture_snapshot(struct xe_hw_engine > *hwe, > + struct > xe_hw_engine_snapshot *snapshot) > +{ > + struct xe_gt *gt = hwe->gt; > + struct xe_device *xe = gt_to_xe(gt); > + struct xe_guc *guc = >->uc.guc; > + struct __guc_capture_parsed_output *n, *ntmp; > + struct xe_devcoredump *devcoredump = &xe->devcoredump; > + struct list_head *list = &guc->capture->outlist; > + struct xe_sched_job *job = devcoredump->job; > + struct xe_guc_submit_exec_queue_snapshot *ge = devcoredump- > >snapshot.ge; > + u16 guc_id = ge->guc.id; > + u32 lrca; > + u16 hwe_guc_class = xe_engine_class_to_guc_class(hwe->class); > + > + lrca = xe_lrc_ggtt_addr(job->q->lrc[0]) & > LRC_GTT_ADDRESS_MASK; > + > + /* > + * Look for a matching GuC reported error capture node from > + * the internal output link-list based on engine class and > instance. > + */ > + list_for_each_entry_safe(n, ntmp, list, link) { > + if (n->eng_class == hwe_guc_class && n->eng_inst == > hwe->instance && > + n->guc_id == guc_id && (n->lrca & > LRC_GTT_ADDRESS_MASK) == lrca) { > + guc_capture_parse_reglist(n, snapshot, > hwe_guc_class); > + list_del(&n->link); > + return; > + } > + } > +} > + > +void xe_guc_capture_free(struct xe_guc *guc) > +{ > + if (guc->capture && !list_empty(&guc->capture->outlist)) { > + struct __guc_capture_parsed_output *n, *ntmp; > + > + list_for_each_entry_safe(n, ntmp, &guc->capture- > >outlist, link) { > + list_del(&n->link); > + /* put node back to cache list */ > + /* No need to init here, > guc_capture_get_prealloc_node init it later */ > + guc_capture_add_node_to_cachelist(guc- > >capture, n); > + } > + } > +} > + > int xe_guc_capture_init(struct xe_guc *guc) > { > guc->capture = drmm_kzalloc(guc_to_drm(guc), sizeof(*guc- > >capture), GFP_KERNEL); > @@ -574,7 +1404,9 @@ int xe_guc_capture_init(struct xe_guc *guc) > return -ENOMEM; > > guc->capture->reglists = guc_capture_get_device_reglist(guc); > - > check_guc_capture_size(guc); > + INIT_LIST_HEAD(&guc->capture->outlist); > + INIT_LIST_HEAD(&guc->capture->cachelist); > + > return 0; > } > diff --git a/drivers/gpu/drm/xe/xe_guc_capture.h > b/drivers/gpu/drm/xe/xe_guc_capture.h > index a62b1dbd47a6..c0bada99c9ec 100644 > --- a/drivers/gpu/drm/xe/xe_guc_capture.h > +++ b/drivers/gpu/drm/xe/xe_guc_capture.h > @@ -10,6 +10,8 @@ > #include "regs/xe_reg_defs.h" > > struct xe_guc; > +struct xe_hw_engine; > +struct xe_hw_engine_snapshot; > > /* > * struct __guc_mmio_reg_descr / struct __guc_mmio_reg_descr_group > @@ -25,6 +27,7 @@ struct __guc_mmio_reg_descr { > u32 flags; > u32 mask; > const char *regname; > + u32 position_in_snapshot; > }; > > struct __guc_mmio_reg_descr_group { > @@ -36,9 +39,15 @@ struct __guc_mmio_reg_descr_group { > struct __guc_mmio_reg_descr *extlist; /* only used for > steered registers */ > }; > > +void xe_guc_capture_process(struct xe_guc *guc); > int xe_guc_capture_getlist(struct xe_guc *guc, u32 owner, u32 type, > u32 classid, void **outptr); > int xe_guc_capture_getlistsize(struct xe_guc *guc, u32 owner, u32 > type, u32 classid, size_t *size); > int xe_guc_capture_getnullheader(struct xe_guc *guc, void **outptr, > size_t *size); > +const struct __guc_mmio_reg_descr_group * > +xe_guc_capture_get_reg_desc_list(u32 owner, u32 type, u32 > engine_classid); > +void xe_hw_engine_find_and_copy_guc_capture_snapshot(struct > xe_hw_engine *hwe, > + struct > xe_hw_engine_snapshot *snapshot); > +void xe_guc_capture_free(struct xe_guc *guc); > int xe_guc_capture_init(struct xe_guc *guc); > > #endif /* _XE_GUC_CAPTURE_H */ > diff --git a/drivers/gpu/drm/xe/xe_guc_capture_fwif.h > b/drivers/gpu/drm/xe/xe_guc_capture_fwif.h > index 199e3c0108a4..5ef8c20fe9bc 100644 > --- a/drivers/gpu/drm/xe/xe_guc_capture_fwif.h > +++ b/drivers/gpu/drm/xe/xe_guc_capture_fwif.h > @@ -10,6 +10,51 @@ > > #include "xe_guc_fwif.h" > > +/* > + * struct __guc_capture_bufstate > + * > + * Book-keeping structure used to track read and write pointers > + * as we extract error capture data from the GuC-log-buffer's > + * error-capture region as a stream of dwords. > + */ > +struct __guc_capture_bufstate { > + u32 size; > + u32 data_offset; > + u32 rd; > + u32 wr; > +}; > + > +/* > + * struct __guc_capture_parsed_output - extracted error capture node > + * > + * A single unit of extracted error-capture output data grouped > together > + * at an engine-instance level. We keep these nodes in a linked > list. > + * See cachelist and outlist below. > + */ > +struct __guc_capture_parsed_output { > + /* > + * A single set of 3 capture lists: a global-list > + * an engine-class-list and an engine-instance list. > + * outlist in __guc_capture_parsed_output will keep > + * a linked list of these nodes that will eventually > + * be detached from outlist and attached into to > + * xe_codedump in response to a context reset > + */ > + struct list_head link; > + bool is_partial; > + u32 eng_class; > + u32 eng_inst; > + u32 guc_id; > + u32 lrca; > + struct gcap_reg_list_info { > + u32 vfid; > + u32 num_regs; > + struct guc_mmio_reg *regs; > + } reginfo[GUC_CAPTURE_LIST_TYPE_MAX]; > +#define GCAP_PARSED_REGLIST_INDEX_GLOBAL > BIT(GUC_CAPTURE_LIST_TYPE_GLOBAL) > +#define GCAP_PARSED_REGLIST_INDEX_ENGCLASS > BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS) > +}; > + > /* > * struct guc_debug_capture_list_header / struct > guc_debug_capture_list > * > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c > b/drivers/gpu/drm/xe/xe_guc_ct.c > index c1f258348f5c..865b58bb4fd9 100644 > --- a/drivers/gpu/drm/xe/xe_guc_ct.c > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c > @@ -1045,6 +1045,8 @@ static int process_g2h_msg(struct xe_guc_ct > *ct, u32 *msg, u32 len) > /* Selftest only at the moment */ > break; > case XE_GUC_ACTION_STATE_CAPTURE_NOTIFICATION: > + ret = xe_guc_error_capture_handler(guc, payload, > adj_len); > + break; > case XE_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE: > /* FIXME: Handle this */ > break; > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h > b/drivers/gpu/drm/xe/xe_guc_fwif.h > index 908298791c93..f8f9c76eb7ac 100644 > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h > @@ -206,6 +206,12 @@ enum guc_capture_type { > GUC_CAPTURE_LIST_TYPE_MAX, > }; > > +/* GuC support limited registers range to be captured for debug > purpose, > + * for unsupported registers, direct read is the only way to save > the data. > + * GuC capture handling will ignore all lists with this type: > GUC_CAPTURE_LIST_TYPE_DIRECT_READ > + */ > +#define GUC_CAPTURE_LIST_TYPE_DIRECT_READ GUC_CAPTURE_LIST_TYPE_MAX > + > /* Class indecies for capture_class and capture_instance arrays */ > enum { > GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE = 0, > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c > b/drivers/gpu/drm/xe/xe_guc_submit.c > index 47aab04cf34f..f02f4c0c9568 100644 > --- a/drivers/gpu/drm/xe/xe_guc_submit.c > +++ b/drivers/gpu/drm/xe/xe_guc_submit.c > @@ -25,6 +25,7 @@ > #include "xe_gt.h" > #include "xe_gt_printk.h" > #include "xe_guc.h" > +#include "xe_guc_capture.h" > #include "xe_guc_ct.h" > #include "xe_guc_exec_queue_types.h" > #include "xe_guc_id_mgr.h" > @@ -769,7 +770,7 @@ static void guc_exec_queue_free_job(struct > drm_sched_job *drm_job) > xe_sched_job_put(job); > } > > -static int guc_read_stopped(struct xe_guc *guc) > +int xe_guc_read_stopped(struct xe_guc *guc) > { > return atomic_read(&guc->submission_state.stopped); > } > @@ -791,7 +792,7 @@ static void disable_scheduling_deregister(struct > xe_guc *guc, > set_min_preemption_timeout(guc, q); > smp_rmb(); > ret = wait_event_timeout(guc->ct.wq, > !exec_queue_pending_enable(q) || > - guc_read_stopped(guc), HZ * 5); > + xe_guc_read_stopped(guc), HZ * 5); > if (!ret) { > struct xe_gpu_scheduler *sched = &q->guc->sched; > > @@ -906,7 +907,7 @@ static void xe_guc_exec_queue_lr_cleanup(struct > work_struct *w) > */ > ret = wait_event_timeout(guc->ct.wq, > > !exec_queue_pending_disable(q) || > - guc_read_stopped(guc), HZ * > 5); > + xe_guc_read_stopped(guc), HZ > * 5); > if (!ret) { > drm_warn(&xe->drm, "Schedule disable failed > to respond"); > xe_sched_submission_start(sched); > @@ -929,6 +930,8 @@ guc_exec_queue_timedout_job(struct drm_sched_job > *drm_job) > int err = -ETIME; > int i = 0; > bool wedged; > + bool reset_status = exec_queue_reset(q); > + bool guc_en = xe_device_uc_enabled(xe); > > /* > * TDR has fired before free job worker. Common if exec queue > @@ -948,7 +951,15 @@ guc_exec_queue_timedout_job(struct drm_sched_job > *drm_job) > xe_gt_WARN(q->gt, q->flags & EXEC_QUEUE_FLAG_VM && > !exec_queue_killed(q), > "VM job timed out on non-killed execqueue\n"); > > - if (!exec_queue_killed(q)) > + /* take devcoredump on: > + * 1. GuC not enabled > + * 2. GuC enabled with GuC reset status == 1 > + * When GuC enabled, register value is captured by GuC, GuC > will notify host > + * with capture notification message, which is right before > reset. > + * GuC reset status 1 also means capture ready. > + * If not ready, will take snapshot after wait event within > this function. > + */ > + if (!exec_queue_killed(q) && (!guc_en || (guc_en && > reset_status))) > xe_devcoredump(job); > > trace_xe_sched_job_timedout(job); > @@ -996,8 +1007,8 @@ guc_exec_queue_timedout_job(struct drm_sched_job > *drm_job) > smp_rmb(); > ret = wait_event_timeout(guc->ct.wq, > > !exec_queue_pending_disable(q) || > - guc_read_stopped(guc), HZ * > 5); > - if (!ret || guc_read_stopped(guc)) { > + xe_guc_read_stopped(guc), HZ > * 5); > + if (!ret || xe_guc_read_stopped(guc)) { > drm_warn(&xe->drm, "Schedule disable failed > to respond"); > xe_sched_add_pending_job(sched, job); > xe_sched_submission_start(sched); > @@ -1007,6 +1018,10 @@ guc_exec_queue_timedout_job(struct > drm_sched_job *drm_job) > } > } > > + /* When entring this function, if capture/reset not ready, > now is time to take snapshot */ > + if (!exec_queue_killed(q) && guc_en && !reset_status) > + xe_devcoredump(job); > + > /* Stop fence signaling */ > xe_hw_fence_irq_stop(q->fence_irq); > > @@ -1112,7 +1127,7 @@ static void suspend_fence_signal(struct > xe_exec_queue *q) > struct xe_device *xe = guc_to_xe(guc); > > xe_assert(xe, exec_queue_suspended(q) || exec_queue_killed(q) > || > - guc_read_stopped(guc)); > + xe_guc_read_stopped(guc)); > xe_assert(xe, q->guc->suspend_pending); > > q->guc->suspend_pending = false; > @@ -1128,9 +1143,9 @@ static void > __guc_exec_queue_process_msg_suspend(struct xe_sched_msg *msg) > if (guc_exec_queue_allowed_to_change_state(q) && > !exec_queue_suspended(q) && > exec_queue_enabled(q)) { > wait_event(guc->ct.wq, q->guc->resume_time != > RESUME_PENDING || > - guc_read_stopped(guc)); > + xe_guc_read_stopped(guc)); > > - if (!guc_read_stopped(guc)) { > + if (!xe_guc_read_stopped(guc)) { > MAKE_SCHED_CONTEXT_ACTION(q, DISABLE); > s64 since_resume_ms = > ktime_ms_delta(ktime_get(), > @@ -1258,7 +1273,7 @@ static int guc_exec_queue_init(struct > xe_exec_queue *q) > > q->entity = &ge->entity; > > - if (guc_read_stopped(guc)) > + if (xe_guc_read_stopped(guc)) > xe_sched_stop(sched); > > mutex_unlock(&guc->submission_state.lock); > @@ -1385,7 +1400,7 @@ static void guc_exec_queue_suspend_wait(struct > xe_exec_queue *q) > struct xe_guc *guc = exec_queue_to_guc(q); > > wait_event(q->guc->suspend_wait, !q->guc->suspend_pending || > - guc_read_stopped(guc)); > + xe_guc_read_stopped(guc)); > } > > static void guc_exec_queue_resume(struct xe_exec_queue *q) > @@ -1495,7 +1510,7 @@ int xe_guc_submit_reset_prepare(struct xe_guc > *guc) > > void xe_guc_submit_reset_wait(struct xe_guc *guc) > { > - wait_event(guc->ct.wq, !guc_read_stopped(guc)); > + wait_event(guc->ct.wq, !xe_guc_read_stopped(guc)); > } > > void xe_guc_submit_stop(struct xe_guc *guc) > @@ -1504,7 +1519,7 @@ void xe_guc_submit_stop(struct xe_guc *guc) > unsigned long index; > struct xe_device *xe = guc_to_xe(guc); > > - xe_assert(xe, guc_read_stopped(guc) == 1); > + xe_assert(xe, xe_guc_read_stopped(guc) == 1); > > mutex_lock(&guc->submission_state.lock); > > @@ -1542,7 +1557,7 @@ int xe_guc_submit_start(struct xe_guc *guc) > unsigned long index; > struct xe_device *xe = guc_to_xe(guc); > > - xe_assert(xe, guc_read_stopped(guc) == 1); > + xe_assert(xe, xe_guc_read_stopped(guc) == 1); > > mutex_lock(&guc->submission_state.lock); > atomic_dec(&guc->submission_state.stopped); > @@ -1698,8 +1713,6 @@ int xe_guc_exec_queue_reset_handler(struct > xe_guc *guc, u32 *msg, u32 len) > xe_gt_info(gt, "Engine reset: engine_class=%s, logical_mask: > 0x%x, guc_id=%d", > xe_hw_engine_class_to_str(q->class), q- > >logical_mask, guc_id); > > - /* FIXME: Do error capture, most likely async */ > - > trace_xe_exec_queue_reset(q); > > /* > @@ -1715,6 +1728,24 @@ int xe_guc_exec_queue_reset_handler(struct > xe_guc *guc, u32 *msg, u32 len) > return 0; > } > > +int xe_guc_error_capture_handler(struct xe_guc *guc, u32 *msg, u32 > len) > +{ > + u32 status; > + > + if (unlikely(len != 1)) { > + xe_gt_dbg(guc_to_gt(guc), "Invalid length %u", len); > + return -EPROTO; > + } > + > + status = msg[0] & XE_GUC_STATE_CAPTURE_EVENT_STATUS_MASK; > + if (status == XE_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE) > + xe_gt_warn(guc_to_gt(guc), "G2H-Error capture no > space"); > + > + xe_guc_capture_process(guc); > + > + return 0; > +} > + > int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, > u32 *msg, > u32 len) > { > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.h > b/drivers/gpu/drm/xe/xe_guc_submit.h > index 4ad5f4c1b084..d92256de473e 100644 > --- a/drivers/gpu/drm/xe/xe_guc_submit.h > +++ b/drivers/gpu/drm/xe/xe_guc_submit.h > @@ -19,12 +19,14 @@ void xe_guc_submit_reset_wait(struct xe_guc > *guc); > void xe_guc_submit_stop(struct xe_guc *guc); > int xe_guc_submit_start(struct xe_guc *guc); > > +int xe_guc_read_stopped(struct xe_guc *guc); > int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 > len); > int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 > len); > int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, > u32 len); > int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, > u32 *msg, > u32 len); > int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 > *msg, u32 len); > +int xe_guc_error_capture_handler(struct xe_guc *guc, u32 *msg, u32 > len); > > struct xe_guc_submit_exec_queue_snapshot * > xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q); > diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c > b/drivers/gpu/drm/xe/xe_hw_engine.c > index 0a83506e1ad8..3bc88fbad952 100644 > --- a/drivers/gpu/drm/xe/xe_hw_engine.c > +++ b/drivers/gpu/drm/xe/xe_hw_engine.c > @@ -20,6 +20,9 @@ > #include "xe_gt_printk.h" > #include "xe_gt_mcr.h" > #include "xe_gt_topology.h" > +#include "xe_guc.h" > +#include "xe_guc_capture.h" > +#include "xe_guc_capture_fwif.h" > #include "xe_hw_fence.h" > #include "xe_irq.h" > #include "xe_lrc.h" > @@ -287,6 +290,7 @@ static void hw_engine_mmio_write32(struct > xe_hw_engine *hwe, struct xe_reg reg, > static u32 hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct > xe_reg reg) > { > xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base)); > + > xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain); > > reg.addr += hwe->mmio_base; > @@ -825,6 +829,62 @@ xe_hw_engine_snapshot_instdone_capture(struct > xe_hw_engine *hwe, > } > } > > +static void > +xe_hw_engine_snapshot_from_hw_by_type(struct xe_hw_engine *hwe, > + struct xe_hw_engine_snapshot > *snapshot, int type) > +{ > + const struct __guc_mmio_reg_descr_group *list; > + u16 capture_class = xe_engine_class_to_guc_capture_class(hwe- > >class); > + int i; > + > + list = > xe_guc_capture_get_reg_desc_list(GUC_CAPTURE_LIST_INDEX_PF, type, > capture_class); > + if (!list) > + return; > + > + for (i = 0; i < list->num_regs; i++) { > + u32 *field; > + > + /* loop until extra operation registers zone */ > + if (list->list[i].reg.addr == > XE_GUC_SNAPSHOT_EXTRA_OPERATION_REGS_START_REG_ADDR) > + break; > + > + field = (u32 *)((uintptr_t)&snapshot->reg + > + list->list[i].position_in_snapshot); > + if (type == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) > + *field = hw_engine_mmio_read32(hwe, list- > >list[i].reg); > + else > + *field = xe_mmio_read32(hwe->gt, list- > >list[i].reg); > + } > +} > + > +/** > + * xe_hw_engine_snapshot_from_hw - Take a quick engine snapshot from > HW. > + * @hwe: Xe HW Engine. > + * @snapshot: Point to the Xe HW Engine snapshot object to save > data. > + * > + * This can be printed out in a later stage like during dev_coredump > + * analysis. > + * > + * Returns: None > + */ > +static void > +xe_hw_engine_snapshot_from_hw(struct xe_hw_engine *hwe, struct > xe_hw_engine_snapshot *snapshot) > +{ > + int type; > + > + for (type = GUC_CAPTURE_LIST_TYPE_GLOBAL; type < > GUC_CAPTURE_LIST_TYPE_MAX; type++) > + xe_hw_engine_snapshot_from_hw_by_type(hwe, snapshot, > type); > + > + /* Extra operation required registers zone - start */ > + if (xe_gt_has_indirect_ring_state(hwe->gt)) > + snapshot->reg.indirect_ring_state = > + hw_engine_mmio_read32(hwe, > INDIRECT_RING_STATE(0)); > + /* Extra operation required registers zone - End */ > + > + /* Capture steering registers */ > + xe_hw_engine_snapshot_instdone_capture(hwe, snapshot); > +} > + > /** > * xe_hw_engine_snapshot_capture - Take a quick snapshot of the HW > Engine. > * @hwe: Xe HW Engine. > @@ -839,8 +899,12 @@ struct xe_hw_engine_snapshot * > xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe) > { > struct xe_hw_engine_snapshot *snapshot; > + struct xe_gt *gt = hwe->gt; > + struct xe_device *xe = gt_to_xe(gt); > + struct xe_guc *guc = >->uc.guc; > alan:snip > + /* Check GuC settings, job is set and capture outlist not > empty, > + * otherwise take it from engine > + */ > + if (xe_device_uc_enabled(xe) && xe->wedged.mode >= 1 && > + !list_empty(&guc->capture->outlist) && xe- > >devcoredump.job) > + xe_hw_engine_find_and_copy_guc_capture_snapshot(hwe, > snapshot); > + else > + xe_hw_engine_snapshot_from_hw(hwe, snapshot); alan: in the above if-else check, we are assuming that guc's capture list not being empty means we have the captured node for this devcoredump triger... however, in larger scale platforms we could have multiple captured nodes from multiple engines so we should not be relying on just whether its empty or not, rather the check should call guc capture to find matching node based on lrc, guc-id, engnine etc (i.e. basically call xe_hw_engine_find_and_copy_guc_capture_snapshot directly to see if we have a dump.) alan:snip. I'll review the rest of this patch after rev9 is out since there are other changes incoming as per my first review comments on top. ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v9 4/4] drm/xe/guc: Extract GuC capture lists to register snapshot 2024-06-13 23:26 ` Teres Alexis, Alan Previn @ 2024-06-19 20:17 ` Dong, Zhanjun 0 siblings, 0 replies; 24+ messages in thread From: Dong, Zhanjun @ 2024-06-19 20:17 UTC (permalink / raw) To: Teres Alexis, Alan Previn, intel-xe@lists.freedesktop.org See my comments below. Regards, Zhanjun On 2024-06-13 7:26 p.m., Teres Alexis, Alan Previn wrote: > alan: Hi there Zhanjun, as per offline conversation, i was surprised to > see you squash the "Guc-error-capture-extraction" together with the > "Plumb GuC-capture into dev coredump" patch but now realize i made a > regrettable typo in my rev8 review comments - when i mentioned about > posisbly squashing pre-allocate-nodes with node-extraction i said > "patch 4 and patch 6" but what i meant was "patch 4 and patch 5". > I'm terribly sorry about this mistake. Since we know that you > have to redo this patch anyways based on offline conversation to > resolve race between drm-tdr vs guc-context-reset, thanks for agreeing > to keep extraction separate again. And ofc we don't need pre-allocating > of nodes now. will put patch 4 back > > On Thu, 2024-06-06 at 17:07 -0700, Zhanjun Dong wrote: >> Upon the G2H Notify-Err-Capture event, parse through the >> GuC Log Buffer (error-capture-subregion) and generate one or >> more capture-nodes. A single node represents a single "engine- >> instance-capture-dump" and contains at least 3 register lists: >> global, engine-class and engine-instance. An internal link >> list is maintained to store one or more nodes. >> Because the link-list node generation happen before the call >> to devcoredump, duplicate global and engine-class register >> lists for each engine-instance register dump if we find >> dependent-engine resets in a engine-capture-group. >> When xe_devcoredump calls into snapshot_from_capture_engine, ... >> + >> +static inline u16 xe_engine_class_to_guc_capture_class(enum >> xe_engine_class class) >> +{ >> + return >> xe_guc_class_to_capture_class(xe_guc_class_to_capture_class(class)); >> +} >> + >> static inline struct xe_gt *guc_to_gt(struct xe_guc *guc) >> { >> return container_of(guc, struct xe_gt, uc.guc); >> > > alan:snip. > >> +static void >> +__guc_capture_create_prealloc_nodes(struct xe_guc *guc) >> +{ >> + struct __guc_capture_parsed_output *node = NULL; >> + int i; >> + >> + for (i = 0; i < PREALLOC_NODES_MAX_COUNT; ++i) { >> + node = guc_capture_alloc_one_node(guc); >> + if (!node) { >> + xe_gt_warn(guc_to_gt(guc), "Register capture >> pre-alloc-cache failure\n"); >> + /* dont free the priors, use what we got and >> cleanup at shutdown */ >> + return; >> + } >> + guc_capture_add_node_to_cachelist(guc->capture, >> node); >> + } >> +} >> + > btw, why are we still using this pre-allocated-nodes framework and > functions? i thought we decided we didn't need it for the case of Xe? > (since we'll serialize the extraction-flow vs any reset-flow vs the > devcoredump-printing by putting them on the same workqueue). In that > case we can remove the prealocated nodes' cachelist extraction code > requiring new ndes can dynamically by calling > guc_capture_alloc_one_node directly Current code is still using the pre-alloced node, I will try dynamic alloc later. Another concern is the GFP_ATOMIC may alloc from emergency pools, it might not be the better choice for debug purposed feature like this. > > alan:snip. same comment above for below hnk. >> +static void >> +guc_capture_create_prealloc_nodes(struct xe_guc *guc) >> +{ >> + /* skip if we've already done the pre-alloc */ > ... >> /** >> * xe_hw_engine_snapshot_capture - Take a quick snapshot of the HW >> Engine. >> * @hwe: Xe HW Engine. >> @@ -839,8 +899,12 @@ struct xe_hw_engine_snapshot * >> xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe) >> { >> struct xe_hw_engine_snapshot *snapshot; >> + struct xe_gt *gt = hwe->gt; >> + struct xe_device *xe = gt_to_xe(gt); >> + struct xe_guc *guc = >->uc.guc; >> > alan:snip > >> + /* Check GuC settings, job is set and capture outlist not >> empty, >> + * otherwise take it from engine >> + */ >> + if (xe_device_uc_enabled(xe) && xe->wedged.mode >= 1 && >> + !list_empty(&guc->capture->outlist) && xe- >>> devcoredump.job) >> + xe_hw_engine_find_and_copy_guc_capture_snapshot(hwe, >> snapshot); >> + else >> + xe_hw_engine_snapshot_from_hw(hwe, snapshot); > > alan: in the above if-else check, we are assuming that guc's capture > list not being empty means we have the captured node for this > devcoredump triger... however, in larger scale platforms we could have > multiple captured nodes from multiple engines so we should not > be relying on just whether its empty or not, rather the check should > call guc capture to find matching node based on lrc, guc-id, engnine > etc (i.e. basically call > xe_hw_engine_find_and_copy_guc_capture_snapshot directly to see if we > have a dump.) Good point, I will add the capture ready for job functions in next rev. > > alan:snip. > > I'll review the rest of this patch after rev9 is out since there are > other changes incoming as per my first review comments on top. ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v9 4/4] drm/xe/guc: Extract GuC capture lists to register snapshot 2024-06-07 0:07 ` [PATCH v9 4/4] drm/xe/guc: Extract GuC capture lists to register snapshot Zhanjun Dong 2024-06-13 23:26 ` Teres Alexis, Alan Previn @ 2024-06-14 12:31 ` Michal Wajdeczko 2024-06-19 20:04 ` Dong, Zhanjun 1 sibling, 1 reply; 24+ messages in thread From: Michal Wajdeczko @ 2024-06-14 12:31 UTC (permalink / raw) To: Zhanjun Dong, intel-xe On 07.06.2024 02:07, Zhanjun Dong wrote: > Upon the G2H Notify-Err-Capture event, parse through the > GuC Log Buffer (error-capture-subregion) and generate one or > more capture-nodes. A single node represents a single "engine- > instance-capture-dump" and contains at least 3 register lists: > global, engine-class and engine-instance. An internal link > list is maintained to store one or more nodes. > Because the link-list node generation happen before the call > to devcoredump, duplicate global and engine-class register > lists for each engine-instance register dump if we find > dependent-engine resets in a engine-capture-group. > When xe_devcoredump calls into snapshot_from_capture_engine, > we detach the matching node (guc-id, LRCA, etc) from the link list > above and attach it to snapshot_regs structure when have > matching LRCA/guc-id/engine-instance. > > To avoid dynamically allocate the output nodes during gt reset, > pre-allocate a fixed number of empty nodes up front (at the > time of ADS registration) that we can consume from or return to > an internal cached list of nodes. > Add guc capture data structure definition. > > Add xe_hw_engine_snapshot_from_capture to take snapshot from capture > node list. > Move snapshot register struct out of engine snapshot struct. > Add offset in snapshot register to register definition list at > xe_guc_capture.c. > Snapshot could be split into global, engine class, engine instance > and steering register zone, few macros defined to separate zones. > Support combines 2 32bit registers as a 64bit register in snapshot, > perform endian convert if needed. > > Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> > --- > drivers/gpu/drm/xe/abi/guc_actions_abi.h | 7 + > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 + > drivers/gpu/drm/xe/xe_devcoredump.c | 4 + > drivers/gpu/drm/xe/xe_devcoredump_types.h | 2 + > drivers/gpu/drm/xe/xe_guc.h | 23 + > drivers/gpu/drm/xe/xe_guc_capture.c | 876 +++++++++++++++++++++- > drivers/gpu/drm/xe/xe_guc_capture.h | 9 + > drivers/gpu/drm/xe/xe_guc_capture_fwif.h | 45 ++ > drivers/gpu/drm/xe/xe_guc_ct.c | 2 + > drivers/gpu/drm/xe/xe_guc_fwif.h | 6 + > drivers/gpu/drm/xe/xe_guc_submit.c | 63 +- > drivers/gpu/drm/xe/xe_guc_submit.h | 2 + > drivers/gpu/drm/xe/xe_hw_engine.c | 218 ++++-- > drivers/gpu/drm/xe/xe_hw_engine_types.h | 159 ++-- > drivers/gpu/drm/xe/xe_lrc.h | 1 + > 15 files changed, 1244 insertions(+), 175 deletions(-) > > diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h > index 79ba98a169f9..ed1eeea34e8e 100644 > --- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h > +++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h > @@ -182,6 +182,13 @@ enum xe_guc_sleep_state_status { > #define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT) > #define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8) > > +enum intel_guc_state_capture_event_status { > + XE_GUC_STATE_CAPTURE_EVENT_STATUS_SUCCESS = 0x0, > + XE_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE = 0x1, > +}; > + > +#define XE_GUC_STATE_CAPTURE_EVENT_STATUS_MASK 0x000000FF > + > #define XE_GUC_TLB_INVAL_TYPE_SHIFT 0 > #define XE_GUC_TLB_INVAL_MODE_SHIFT 8 > /* Flush PPC or SMRO caches along with TLB invalidation request */ > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h > index d09b2473259f..c6bd50738e2b 100644 > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h > @@ -574,4 +574,6 @@ > #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) > #define GT_RENDER_USER_INTERRUPT REG_BIT(0) > > +#define SFC_DONE(n) XE_REG(0x1cc000 + (n) * 0x1000) > + > #endif > diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c > index d7f2d19a77c1..5e80710d3cc8 100644 > --- a/drivers/gpu/drm/xe/xe_devcoredump.c > +++ b/drivers/gpu/drm/xe/xe_devcoredump.c > @@ -16,6 +16,7 @@ > #include "xe_force_wake.h" > #include "xe_gt.h" > #include "xe_gt_printk.h" > +#include "xe_guc_capture.h" > #include "xe_guc_ct.h" > #include "xe_guc_submit.h" > #include "xe_hw_engine.h" > @@ -149,10 +150,12 @@ static void xe_devcoredump_free(void *data) > if (coredump->snapshot.hwe[i]) > xe_hw_engine_snapshot_free(coredump->snapshot.hwe[i]); > xe_vm_snapshot_free(coredump->snapshot.vm); > + xe_guc_capture_free(&coredump->snapshot.gt->uc.guc); > > /* To prevent stale data on next snapshot, clear everything */ > memset(&coredump->snapshot, 0, sizeof(coredump->snapshot)); > coredump->captured = false; > + coredump->job = NULL; > drm_info(&coredump_to_xe(coredump)->drm, > "Xe device coredump has been deleted.\n"); > } > @@ -186,6 +189,7 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump, > put_task_struct(task); > > ss->gt = q->gt; > + coredump->job = job; > INIT_WORK(&ss->work, xe_devcoredump_deferred_snap_work); > > cookie = dma_fence_begin_signalling(); > diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h > index 923cdf72a816..c39ab73a9f6a 100644 > --- a/drivers/gpu/drm/xe/xe_devcoredump_types.h > +++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h > @@ -61,6 +61,8 @@ struct xe_devcoredump { > bool captured; > /** @snapshot: Snapshot is captured at time of the first crash */ > struct xe_devcoredump_snapshot snapshot; > + /** @job: Point to the issue job */ > + struct xe_sched_job *job; > }; > > #endif > diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h > index ddfa855458ab..e1afda9070f4 100644 > --- a/drivers/gpu/drm/xe/xe_guc.h > +++ b/drivers/gpu/drm/xe/xe_guc.h > @@ -59,6 +59,29 @@ static inline u16 xe_engine_class_to_guc_class(enum xe_engine_class class) > } > } > > +static inline u16 xe_guc_class_to_capture_class(uint class) > +{ > + switch (class) { > + case GUC_RENDER_CLASS: > + case GUC_COMPUTE_CLASS: > + return GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE; > + case GUC_GSC_OTHER_CLASS: > + return GUC_CAPTURE_LIST_CLASS_GSC_OTHER; > + case GUC_VIDEO_CLASS: > + case GUC_VIDEOENHANCE_CLASS: > + case GUC_BLITTER_CLASS: > + return class; > + default: > + XE_WARN_ON(class); > + return -1; it doesn't look like a safe value nor that you handle it correctly > + } > +} > + > +static inline u16 xe_engine_class_to_guc_capture_class(enum xe_engine_class class) > +{ > + return xe_guc_class_to_capture_class(xe_guc_class_to_capture_class(class)); are you sure this is correct ? > +} > + > static inline struct xe_gt *guc_to_gt(struct xe_guc *guc) > { > return container_of(guc, struct xe_gt, uc.guc); > diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c > index 0c90def290de..f18933503672 100644 > --- a/drivers/gpu/drm/xe/xe_guc_capture.c > +++ b/drivers/gpu/drm/xe/xe_guc_capture.c > @@ -26,10 +26,13 @@ > #include "xe_guc_capture_fwif.h" > #include "xe_guc_ct.h" > #include "xe_guc_log.h" > +#include "xe_guc_submit_types.h" > #include "xe_guc_submit.h" > #include "xe_hw_engine_types.h" > +#include "xe_lrc.h" > #include "xe_macros.h" > #include "xe_map.h" > +#include "xe_sched_job.h" > > /* > * Define all device tables of GuC error capture register lists > @@ -37,28 +40,81 @@ > * from the engine-mmio-base > */ > #define COMMON_XELP_BASE_GLOBAL \ > - { FORCEWAKE_GT, 0, 0} > + { FORCEWAKE_GT, 0, 0, "FORCEWAKE_GT",\ > + offsetof(struct snapshot_regs, forcewake_gt) } > > #define COMMON_BASE_ENGINE_INSTANCE \ > - { RING_ESR(0), 0, 0}, \ > - { RING_EMR(0), 0, 0}, \ > - { RING_EIR(0), 0, 0}, \ > - { RING_EXECLIST_STATUS_HI(0), 0, 0}, \ > - { RING_EXECLIST_STATUS_LO(0), 0, 0}, \ > - { RING_DMA_FADD(0), 0, 0}, \ > - { RING_DMA_FADD_UDW(0), 0, 0}, \ > - { RING_IPEHR(0), 0, 0}, \ > - { RING_BBADDR(0), 0, 0}, \ > - { RING_BBADDR_UDW(0), 0, 0}, \ > - { RING_ACTHD(0), 0, 0}, \ > - { RING_ACTHD_UDW(0), 0, 0}, \ > - { RING_START(0), 0, 0}, \ > - { RING_HEAD(0), 0, 0}, \ > - { RING_TAIL(0), 0, 0}, \ > - { RING_CTL(0), 0, 0}, \ > - { RING_MI_MODE(0), 0, 0}, \ > - { RING_HWS_PGA(0), 0, 0}, \ > - { RING_MODE(0), 0, 0} > + { RING_HWSTAM(0), 0, 0, "HWSTAM",\ > + offsetof(struct snapshot_regs, ring_hwstam) }, \ > + { RING_HWS_PGA(0), 0, 0, "RING_HWS_PGA",\ > + offsetof(struct snapshot_regs, ring_hws_pga) }, \ > + { RING_HEAD(0), 0, 0, "RING_HEAD",\ > + offsetof(struct snapshot_regs, ring_head) }, \ > + { RING_TAIL(0), 0, 0, "RING_TAIL",\ > + offsetof(struct snapshot_regs, ring_tail) }, \ > + { RING_CTL(0), 0, 0, "RING_CTL",\ > + offsetof(struct snapshot_regs, ring_ctl) }, \ > + { RING_MI_MODE(0), 0, 0, "RING_MI_MODE",\ > + offsetof(struct snapshot_regs, ring_mi_mode) }, \ > + { RING_MODE(0), 0, 0, "RING_MODE",\ > + offsetof(struct snapshot_regs, ring_mode) }, \ > + { RING_ESR(0), 0, 0, "RING_ESR",\ > + offsetof(struct snapshot_regs, ring_esr) }, \ > + { RING_EMR(0), 0, 0, "RING_EMR",\ > + offsetof(struct snapshot_regs, ring_emr) }, \ > + { RING_EIR(0), 0, 0, "RING_EIR",\ > + offsetof(struct snapshot_regs, ring_eir) }, \ > + { RING_IMR(0), 0, 0, "RING_IMR",\ > + offsetof(struct snapshot_regs, ring_imr) }, \ > + { RING_IPEHR(0), 0, 0, "IPEHR",\ > + offsetof(struct snapshot_regs, ipehr) }, \ > + /* 64 bit register - Start */ \ > + /* defined XE_GUC_SNAPSHOT_REGS_U64_START_REG_ADDR to the address of 1st register below */ \ > + /* into xe_hw_engine_types.h */ \ > + { RING_ACTHD(0), 0, 0, "ACTHD",\ > + offsetof(struct snapshot_regs, ring_acthd) }, \ > + { RING_ACTHD_UDW(0), 0, 0, NULL,\ > + offsetof(struct snapshot_regs, ring_acthd) + 4}, \ > + { RING_BBADDR(0), 0, 0, "RING_BBADDR",\ > + offsetof(struct snapshot_regs, ring_bbaddr) }, \ > + { RING_BBADDR_UDW(0), 0, 0, NULL,\ > + offsetof(struct snapshot_regs, ring_bbaddr) + 4}, \ > + { RING_START(0), 0, 0, "RING_START",\ > + offsetof(struct snapshot_regs, ring_start) }, \ > + { RING_START_UDW(0), 0, 0, NULL,\ > + offsetof(struct snapshot_regs, ring_start) + 4}, \ > + { RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD",\ > + offsetof(struct snapshot_regs, ring_dma_fadd) }, \ > + { RING_DMA_FADD_UDW(0), 0, 0, NULL,\ > + offsetof(struct snapshot_regs, ring_dma_fadd) + 4}, \ > + { RING_EXECLIST_STATUS_LO(0), 0, 0, "RING_EXECLIST_STATUS",\ > + offsetof(struct snapshot_regs, ring_execlist_status)}, \ > + { RING_EXECLIST_STATUS_HI(0), 0, 0, NULL,\ > + offsetof(struct snapshot_regs, ring_execlist_status) + 4}, \ > + { RING_EXECLIST_SQ_CONTENTS_LO(0), 0, 0, "RING_EXECLIST_SQ_CONTENTS",\ > + offsetof(struct snapshot_regs, ring_execlist_sq_contents)}, \ > + { RING_EXECLIST_SQ_CONTENTS_HI(0), 0, 0, NULL,\ > + offsetof(struct snapshot_regs, ring_execlist_sq_contents) + 4}, \ > + /* 64 bit register - End */ \ > + /* Extra handling registers */ \ > + /* define XE_GUC_SNAPSHOT_EXTRA_OPERATION_REGS_START_REG_ADDR to the address of 1st */ \ > + /* register below into xe_hw_engine_types.h */ \ > + { INDIRECT_RING_STATE(0), 0, 0, "INDIRECT_RING_STATE",\ > + offsetof(struct snapshot_regs, indirect_ring_state)} > + > +#define COMMON_XELP_RC_CLASS \ > + { RCU_MODE, 0, 0, "RCU_MODE",\ > + offsetof(struct snapshot_regs, rcu_mode) } > + > +#define XELP_DIRECT_READ_VEC_CLASS \ > + { SFC_DONE(0), 0, 0, "SFC_DONE[0]", \ > + offsetof(struct snapshot_regs, sfc_done_0) }, \ > + { SFC_DONE(1), 0, 0, "SFC_DONE[1]", \ > + offsetof(struct snapshot_regs, sfc_done_1) }, \ > + { SFC_DONE(2), 0, 0, "SFC_DONE[2]", \ > + offsetof(struct snapshot_regs, sfc_done_2) }, \ > + { SFC_DONE(3), 0, 0, "SFC_DONE[3]", \ > + offsetof(struct snapshot_regs, sfc_done_3) } > > /* XE_LP Global */ > static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = { > @@ -70,6 +126,11 @@ static const struct __guc_mmio_reg_descr xe_rc_inst_regs[] = { > COMMON_BASE_ENGINE_INSTANCE, > }; > > +/* Render / Compute Per-Engine-Instance */ > +static const struct __guc_mmio_reg_descr xe_rc_class_regs[] = { > + COMMON_XELP_RC_CLASS, > +}; > + > /* Media Decode/Encode Per-Engine-Instance */ > static const struct __guc_mmio_reg_descr xe_vd_inst_regs[] = { > COMMON_BASE_ENGINE_INSTANCE, > @@ -80,6 +141,11 @@ static const struct __guc_mmio_reg_descr xe_vec_inst_regs[] = { > COMMON_BASE_ENGINE_INSTANCE, > }; > > +/* Video Enhancement Per-Engine-Class */ > +static const struct __guc_mmio_reg_descr xe_vec_direct_read_regs[] = { > + XELP_DIRECT_READ_VEC_CLASS, > +}; > + > /* Blitter Per-Engine-Instance */ > static const struct __guc_mmio_reg_descr xe_blt_inst_regs[] = { > COMMON_BASE_ENGINE_INSTANCE, > @@ -112,12 +178,13 @@ static const struct __guc_mmio_reg_descr empty_regs_list[] = { > /* List of lists */ > static const struct __guc_mmio_reg_descr_group xe_lp_lists[] = { > MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0), > - MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE), > + MAKE_REGLIST(xe_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE), > MAKE_REGLIST(xe_rc_inst_regs, PF, ENGINE_INSTANCE, > GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE), > MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO), > MAKE_REGLIST(xe_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO), > MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE), > + MAKE_REGLIST(xe_vec_direct_read_regs, PF, DIRECT_READ, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE), > MAKE_REGLIST(xe_vec_inst_regs, PF, ENGINE_INSTANCE, > GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE), > MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER), > @@ -148,6 +215,7 @@ static const char * const capture_engine_class_names[] = { > */ > #define get_item_with_default(ar, index) (ar[(index) >= ARRAY_SIZE(ar) ? ARRAY_SIZE(ar) - 1 : \ > (index)]) > +static void guc_capture_create_prealloc_nodes(struct xe_guc *guc); > > static const struct __guc_mmio_reg_descr_group * > guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists, > @@ -167,6 +235,12 @@ guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists, > return NULL; > } > > +const struct __guc_mmio_reg_descr_group * > +xe_guc_capture_get_reg_desc_list(u32 owner, u32 type, u32 engine_classid) > +{ > + return guc_capture_get_one_list(xe_lp_lists, owner, type, engine_classid); > +} > + > static struct __guc_mmio_reg_descr_group * > guc_capture_get_one_ext_list(struct __guc_mmio_reg_descr_group *reglists, > u32 owner, u32 type, u32 id) > @@ -430,6 +504,12 @@ xe_guc_capture_getlist(struct xe_guc *guc, u32 owner, u32 type, u32 classid, voi > return cache->status; > } > > + /* > + * ADS population of input registers is a good > + * time to pre-allocate cachelist output nodes > + */ > + guc_capture_create_prealloc_nodes(guc); > + > ret = xe_guc_capture_getlistsize(guc, owner, type, classid, &size); > if (ret) { > cache->is_valid = true; > @@ -567,6 +647,756 @@ static void check_guc_capture_size(struct xe_guc *guc) > buffer_size, spare_size, capture_size); > } > > +static void > +guc_capture_add_node_to_list(struct __guc_capture_parsed_output *node, > + struct list_head *list) > +{ > + list_add_tail(&node->link, list); > +} > + > +static void > +guc_capture_add_node_to_outlist(struct xe_guc_state_capture *guc, > + struct __guc_capture_parsed_output *node) > +{ > + guc_capture_add_node_to_list(node, &guc->outlist); > +} > + > +static void > +guc_capture_add_node_to_cachelist(struct xe_guc_state_capture *guc, > + struct __guc_capture_parsed_output *node) > +{ > + guc_capture_add_node_to_list(node, &guc->cachelist); > +} > + > +static void > +guc_capture_init_node(struct xe_guc *guc, struct __guc_capture_parsed_output *node) > +{ > + struct guc_mmio_reg *tmp[GUC_CAPTURE_LIST_TYPE_MAX]; > + int i; > + > + for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { > + tmp[i] = node->reginfo[i].regs; > + memset(tmp[i], 0, sizeof(struct guc_mmio_reg) * > + guc->capture->max_mmio_per_node); > + } > + memset(node, 0, sizeof(*node)); > + for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) > + node->reginfo[i].regs = tmp[i]; > + > + INIT_LIST_HEAD(&node->link); > +} > + > +/* > + * KMD Init time flows: > + * -------------------- > + * --> alloc A: GuC input capture regs lists (registered to GuC via ADS). > + * xe_guc_ads acquires the register lists by calling > + * xe_guc_capture_list_size and xe_guc_capture_list_get 'n' times, > + * where n = 1 for global-reg-list + > + * num_engine_classes for class-reg-list + > + * num_engine_classes for instance-reg-list > + * (since all instances of the same engine-class type > + * have an identical engine-instance register-list). > + * ADS module also calls separately for PF vs VF. > + * > + * --> alloc B: GuC output capture buf (registered via guc_init_params(log_param)) > + * Size = #define CAPTURE_BUFFER_SIZE (warns if on too-small) > + * Note2: 'x 3' to hold multiple capture groups > + * > + * GUC Runtime notify capture: > + * -------------------------- > + * --> G2H STATE_CAPTURE_NOTIFICATION > + * L--> xe_guc_capture_process > + * L--> Loop through B (head..tail) and for each engine instance's > + * err-state-captured register-list we find, we alloc 'C': > + * --> alloc C: A capture-output-node structure that includes misc capture info along > + * with 3 register list dumps (global, engine-class and engine-instance) > + * This node is created from a pre-allocated list of blank nodes in > + * guc->capture->cachelist and populated with the error-capture > + * data from GuC and then it's added into guc->capture->outlist linked > + * list. This list is used for matchup and printout by xe_devcoredump_read > + * and xe_hw_engine_snapshot_print, (when user invokes the devcoredump sysfs). > + * > + * GUC --> notify context reset: > + * ----------------------------- > + * --> guc_exec_queue_timedout_job > + * L--> xe_devcoredump > + * L--> devcoredump_snapshot(..IS_GUC_CAPTURE) > + * --> xe_hw_engine_snapshot_capture(..IS_GUC_CAPTURE) > + * L--> xe_hw_engine_find_and_copy_guc_capture_snapshot is where > + * detach C from internal linked list and add it into > + * xe_hw_engine_snapshot struct (if the context and > + * engine of the event notification matches a node > + * in the link list). > + * > + * User Sysfs / Debugfs > + * -------------------- > + * --> xe_devcoredump_read-> > + * L--> xxx_snapshot_print > + * L--> xe_hw_engine_snapshot_print > + * register lists values of the xe_hw_engine_snapshot > + * saved from the error-engine-dump. > + * > + */ > + > +static int guc_capture_buf_cnt(struct __guc_capture_bufstate *buf) > +{ > + if (buf->wr >= buf->rd) > + return (buf->wr - buf->rd); > + return (buf->size - buf->rd) + buf->wr; > +} > + > +static int guc_capture_buf_cnt_to_end(struct __guc_capture_bufstate *buf) > +{ > + if (buf->rd > buf->wr) > + return (buf->size - buf->rd); > + return (buf->wr - buf->rd); > +} > + > +/* > + * GuC's error-capture output is a ring buffer populated in a byte-stream fashion: > + * > + * The GuC Log buffer region for error-capture is managed like a ring buffer. > + * The GuC firmware dumps error capture logs into this ring in a byte-stream flow. > + * Additionally, as per the current and foreseeable future, all packed error- > + * capture output structures are dword aligned. > + * > + * That said, if the GuC firmware is in the midst of writing a structure that is larger > + * than one dword but the tail end of the err-capture buffer-region has lesser space left, > + * we would need to extract that structure one dword at a time straddled across the end, > + * onto the start of the ring. > + * > + * Below function, guc_capture_log_remove_dw is a helper for that. All callers of this > + * function would typically do a straight-up memcpy from the ring contents and will only > + * call this helper if their structure-extraction is straddling across the end of the > + * ring. GuC firmware does not add any padding. The reason for the no-padding is to ease > + * scalability for future expansion of output data types without requiring a redesign > + * of the flow controls. > + */ > +static int > +guc_capture_log_remove_dw(struct xe_guc *guc, struct __guc_capture_bufstate *buf, > + u32 *dw) > +{ > + int tries = 2; > + int avail = 0; > + > + if (!guc_capture_buf_cnt(buf)) > + return 0; > + > + while (tries--) { > + avail = guc_capture_buf_cnt_to_end(buf); > + if (avail >= sizeof(u32)) { > + *dw = xe_map_rd(guc_to_xe(guc), &guc->log.bo->vmap, > + buf->data_offset + buf->rd, u32); > + buf->rd += 4; > + return 4; > + } > + if (avail) > + xe_gt_dbg(guc_to_gt(guc), "Register capture log not dword aligned, skipping.\n"); > + buf->rd = 0; > + } > + > + return 0; > +} > + > +static bool > +guc_capture_data_extracted(struct xe_guc *guc, struct __guc_capture_bufstate *b, > + int size, void *dest) > +{ > + if (guc_capture_buf_cnt_to_end(b) >= size) { > + xe_map_memcpy_from(guc_to_xe(guc), dest, &guc->log.bo->vmap, > + b->data_offset + b->rd, size); > + b->rd += size; > + return true; > + } > + return false; > +} > + > +static int > +guc_capture_log_get_group_hdr(struct xe_guc *guc, struct __guc_capture_bufstate *buf, > + struct guc_state_capture_group_header_t *ghdr) > +{ > + int read = 0; > + int fullsize = sizeof(struct guc_state_capture_group_header_t); > + > + if (fullsize > guc_capture_buf_cnt(buf)) > + return -1; > + > + if (guc_capture_data_extracted(guc, buf, fullsize, (void *)ghdr)) > + return 0; > + > + read += guc_capture_log_remove_dw(guc, buf, &ghdr->owner); > + read += guc_capture_log_remove_dw(guc, buf, &ghdr->info); > + if (read != fullsize) > + return -1; > + > + return 0; > +} > + > +static int > +guc_capture_log_get_data_hdr(struct xe_guc *guc, struct __guc_capture_bufstate *buf, > + struct guc_state_capture_header_t *hdr) > +{ > + int read = 0; > + int fullsize = sizeof(struct guc_state_capture_header_t); > + > + if (fullsize > guc_capture_buf_cnt(buf)) > + return -1; > + > + if (guc_capture_data_extracted(guc, buf, fullsize, (void *)hdr)) > + return 0; > + > + read += guc_capture_log_remove_dw(guc, buf, &hdr->owner); > + read += guc_capture_log_remove_dw(guc, buf, &hdr->info); > + read += guc_capture_log_remove_dw(guc, buf, &hdr->lrca); > + read += guc_capture_log_remove_dw(guc, buf, &hdr->guc_id); > + read += guc_capture_log_remove_dw(guc, buf, &hdr->num_mmios); > + if (read != fullsize) > + return -1; > + > + return 0; > +} > + > +static int > +guc_capture_log_get_register(struct xe_guc *guc, struct __guc_capture_bufstate *buf, > + struct guc_mmio_reg *reg) > +{ > + int read = 0; > + int fullsize = sizeof(struct guc_mmio_reg); > + > + if (fullsize > guc_capture_buf_cnt(buf)) > + return -1; > + > + if (guc_capture_data_extracted(guc, buf, fullsize, (void *)reg)) > + return 0; > + > + read += guc_capture_log_remove_dw(guc, buf, ®->offset); > + read += guc_capture_log_remove_dw(guc, buf, ®->value); > + read += guc_capture_log_remove_dw(guc, buf, ®->flags); > + read += guc_capture_log_remove_dw(guc, buf, ®->mask); > + if (read != fullsize) > + return -1; > + > + return 0; > +} > + > +static struct __guc_capture_parsed_output * > +guc_capture_get_prealloc_node(struct xe_guc *guc) > +{ > + struct __guc_capture_parsed_output *found = NULL; > + > + if (!list_empty(&guc->capture->cachelist)) { > + struct __guc_capture_parsed_output *n, *ntmp; > + > + /* get first avail node from the cache list */ > + list_for_each_entry_safe(n, ntmp, &guc->capture->cachelist, link) { > + found = n; > + break; > + } > + } else { > + struct __guc_capture_parsed_output *n, *ntmp; > + > + /* traverse down and steal back the oldest node already allocated */ > + list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) { > + found = n; > + } > + } > + if (found) { > + list_del(&found->link); > + guc_capture_init_node(guc, found); > + } > + > + return found; > +} > + > +static struct __guc_capture_parsed_output * > +guc_capture_clone_node(struct xe_guc *guc, struct __guc_capture_parsed_output *original, > + u32 keep_reglist_mask) > +{ > + struct __guc_capture_parsed_output *new; > + int i; > + > + new = guc_capture_get_prealloc_node(guc); > + if (!new) > + return NULL; > + if (!original) > + return new; > + > + new->is_partial = original->is_partial; > + > + /* copy reg-lists that we want to clone */ > + for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { > + if (keep_reglist_mask & BIT(i)) { > + XE_WARN_ON(original->reginfo[i].num_regs > > + guc->capture->max_mmio_per_node); > + > + memcpy(new->reginfo[i].regs, original->reginfo[i].regs, > + original->reginfo[i].num_regs * sizeof(struct guc_mmio_reg)); > + > + new->reginfo[i].num_regs = original->reginfo[i].num_regs; > + new->reginfo[i].vfid = original->reginfo[i].vfid; > + > + if (i == GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS) { > + new->eng_class = original->eng_class; > + } else if (i == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) { > + new->eng_inst = original->eng_inst; > + new->guc_id = original->guc_id; > + new->lrca = original->lrca; > + } > + } > + } > + > + return new; > +} > + > +static int > +guc_capture_extract_reglists(struct xe_guc *guc, struct __guc_capture_bufstate *buf) > +{ > + struct xe_gt *gt = guc_to_gt(guc); > + struct guc_state_capture_group_header_t ghdr = {0}; > + struct guc_state_capture_header_t hdr = {0}; > + struct __guc_capture_parsed_output *node = NULL; > + struct guc_mmio_reg *regs = NULL; > + int i, numlists, numregs, ret = 0; > + enum guc_capture_type datatype; > + struct guc_mmio_reg tmp; > + bool is_partial = false; > + > + i = guc_capture_buf_cnt(buf); > + if (!i) > + return -ENODATA; > + > + if (i % sizeof(u32)) { > + xe_gt_warn(gt, "Got mis-aligned register capture entries\n"); > + ret = -EIO; > + goto bailout; > + } > + > + /* first get the capture group header */ > + if (guc_capture_log_get_group_hdr(guc, buf, &ghdr)) { > + ret = -EIO; > + goto bailout; > + } > + /* > + * we would typically expect a layout as below where n would be expected to be > + * anywhere between 3 to n where n > 3 if we are seeing multiple dependent engine > + * instances being reset together. > + * ____________________________________________ > + * | Capture Group | > + * | ________________________________________ | > + * | | Capture Group Header: | | > + * | | - num_captures = 5 | | > + * | |______________________________________| | > + * | ________________________________________ | > + * | | Capture1: | | > + * | | Hdr: GLOBAL, numregs=a | | > + * | | ____________________________________ | | > + * | | | Reglist | | | > + * | | | - reg1, reg2, ... rega | | | > + * | | |__________________________________| | | > + * | |______________________________________| | > + * | ________________________________________ | > + * | | Capture2: | | > + * | | Hdr: CLASS=RENDER/COMPUTE, numregs=b| | > + * | | ____________________________________ | | > + * | | | Reglist | | | > + * | | | - reg1, reg2, ... regb | | | > + * | | |__________________________________| | | > + * | |______________________________________| | > + * | ________________________________________ | > + * | | Capture3: | | > + * | | Hdr: INSTANCE=RCS, numregs=c | | > + * | | ____________________________________ | | > + * | | | Reglist | | | > + * | | | - reg1, reg2, ... regc | | | > + * | | |__________________________________| | | > + * | |______________________________________| | > + * | ________________________________________ | > + * | | Capture4: | | > + * | | Hdr: CLASS=RENDER/COMPUTE, numregs=d| | > + * | | ____________________________________ | | > + * | | | Reglist | | | > + * | | | - reg1, reg2, ... regd | | | > + * | | |__________________________________| | | > + * | |______________________________________| | > + * | ________________________________________ | > + * | | Capture5: | | > + * | | Hdr: INSTANCE=CCS0, numregs=e | | > + * | | ____________________________________ | | > + * | | | Reglist | | | > + * | | | - reg1, reg2, ... rege | | | > + * | | |__________________________________| | | > + * | |______________________________________| | > + * |__________________________________________| > + */ > + is_partial = FIELD_GET(CAP_GRP_HDR_CAPTURE_TYPE, ghdr.info); > + numlists = FIELD_GET(CAP_GRP_HDR_NUM_CAPTURES, ghdr.info); > + > + while (numlists--) { > + if (guc_capture_log_get_data_hdr(guc, buf, &hdr)) { > + ret = -EIO; > + break; > + } > + > + datatype = FIELD_GET(CAP_HDR_CAPTURE_TYPE, hdr.info); > + if (datatype > GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) { > + /* unknown capture type - skip over to next capture set */ > + numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios); > + while (numregs--) { > + if (guc_capture_log_get_register(guc, buf, &tmp)) { > + ret = -EIO; > + break; > + } > + } > + continue; > + } else if (node) { > + /* > + * Based on the current capture type and what we have so far, > + * decide if we should add the current node into the internal > + * linked list for match-up when xe_devcoredump calls later > + * (and alloc a blank node for the next set of reglists) > + * or continue with the same node or clone the current node > + * but only retain the global or class registers (such as the > + * case of dependent engine resets). > + */ > + if (datatype == GUC_CAPTURE_LIST_TYPE_GLOBAL) { > + guc_capture_add_node_to_outlist(guc->capture, node); > + node = NULL; > + } else if (datatype == GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS && > + node->reginfo[GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS].num_regs) { > + /* Add to list, clone node and duplicate global list */ > + guc_capture_add_node_to_outlist(guc->capture, node); > + node = guc_capture_clone_node(guc, node, > + GCAP_PARSED_REGLIST_INDEX_GLOBAL); > + } else if (datatype == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE && > + node->reginfo[GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE].num_regs) { > + /* Add to list, clone node and duplicate global + class lists */ > + guc_capture_add_node_to_outlist(guc->capture, node); > + node = guc_capture_clone_node(guc, node, > + (GCAP_PARSED_REGLIST_INDEX_GLOBAL | > + GCAP_PARSED_REGLIST_INDEX_ENGCLASS)); > + } > + } > + > + if (!node) { > + node = guc_capture_get_prealloc_node(guc); > + if (!node) { > + ret = -ENOMEM; > + break; > + } > + if (datatype != GUC_CAPTURE_LIST_TYPE_GLOBAL) > + xe_gt_dbg(gt, "Register capture missing global dump: %08x!\n", > + datatype); > + } > + node->is_partial = is_partial; > + node->reginfo[datatype].vfid = FIELD_GET(CAP_HDR_CAPTURE_VFID, hdr.owner); > + > + switch (datatype) { > + case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE: > + node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info); > + node->eng_inst = FIELD_GET(CAP_HDR_ENGINE_INSTANCE, hdr.info); > + node->lrca = hdr.lrca; > + node->guc_id = hdr.guc_id; > + break; > + case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS: > + node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info); > + break; > + default: > + break; > + } > + > + numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios); > + if (numregs > guc->capture->max_mmio_per_node) { > + xe_gt_dbg(gt, "Register capture list extraction clipped by prealloc!\n"); > + numregs = guc->capture->max_mmio_per_node; > + } > + node->reginfo[datatype].num_regs = numregs; > + regs = node->reginfo[datatype].regs; > + i = 0; > + while (numregs--) { > + if (guc_capture_log_get_register(guc, buf, ®s[i++])) { > + ret = -EIO; > + break; > + } > + } > + } > + > +bailout: > + if (node) { > + /* If we have data, add to linked list for match-up when xe_devcoredump calls */ > + for (i = GUC_CAPTURE_LIST_TYPE_GLOBAL; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { > + if (node->reginfo[i].regs) { > + guc_capture_add_node_to_outlist(guc->capture, node); > + node = NULL; > + break; > + } > + } > + if (node) /* else return it back to cache list */ > + guc_capture_add_node_to_cachelist(guc->capture, node); > + } > + return ret; > +} > + > +static int __guc_capture_flushlog_complete(struct xe_guc *guc) > +{ > + u32 action[] = { > + XE_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE, > + GUC_CAPTURE_LOG_BUFFER > + }; > + > + return xe_guc_ct_send_g2h_handler(&guc->ct, action, ARRAY_SIZE(action)); > +} > + > +static void __guc_capture_process_output(struct xe_guc *guc) > +{ > + unsigned int buffer_size, read_offset, write_offset, full_count; > + struct xe_uc *uc = container_of(guc, typeof(*uc), guc); > + struct guc_log_buffer_state log_buf_state_local; > + struct __guc_capture_bufstate buf; > + bool new_overflow; > + int ret; > + u32 log_buf_state_offset; > + u32 src_data_offset; > + > + log_buf_state_offset = sizeof(struct guc_log_buffer_state) * GUC_CAPTURE_LOG_BUFFER; > + src_data_offset = xe_guc_get_log_buffer_offset(&guc->log, GUC_CAPTURE_LOG_BUFFER); > + > + /* > + * Make a copy of the state structure, inside GuC log buffer > + * (which is uncached mapped), on the stack to avoid reading > + * from it multiple times. > + */ > + xe_map_memcpy_from(guc_to_xe(guc), &log_buf_state_local, &guc->log.bo->vmap, > + log_buf_state_offset, sizeof(struct guc_log_buffer_state)); > + > + buffer_size = xe_guc_get_log_buffer_size(&guc->log, GUC_CAPTURE_LOG_BUFFER); > + read_offset = log_buf_state_local.read_ptr; > + write_offset = log_buf_state_local.sampled_write_ptr; > + full_count = log_buf_state_local.buffer_full_cnt; > + > + /* Bookkeeping stuff */ > + guc->log.stats[GUC_CAPTURE_LOG_BUFFER].flush += log_buf_state_local.flush_to_file; > + new_overflow = xe_guc_check_log_buf_overflow(&guc->log, GUC_CAPTURE_LOG_BUFFER, > + full_count); > + > + /* Now copy the actual logs. */ > + if (unlikely(new_overflow)) { > + /* copy the whole buffer in case of overflow */ > + read_offset = 0; > + write_offset = buffer_size; > + } else if (unlikely((read_offset > buffer_size) || > + (write_offset > buffer_size))) { > + xe_gt_err(guc_to_gt(guc), > + "Register capture buffer in invalid state: read = 0x%X, size = 0x%X!\n", > + read_offset, buffer_size); > + /* copy whole buffer as offsets are unreliable */ > + read_offset = 0; > + write_offset = buffer_size; > + } > + > + buf.size = buffer_size; > + buf.rd = read_offset; > + buf.wr = write_offset; > + buf.data_offset = src_data_offset; > + > + if (!xe_guc_read_stopped(guc)) { > + do { > + ret = guc_capture_extract_reglists(guc, &buf); > + } while (ret >= 0); > + } > + > + /* Update the state of log buffer err-cap state */ > + xe_map_wr(guc_to_xe(guc), &guc->log.bo->vmap, > + log_buf_state_offset + offsetof(struct guc_log_buffer_state, read_ptr), u32, > + write_offset); > + /* Clear the flush_to_file from local first, the local was loaded by above > + * xe_map_memcpy_from. > + */ > + log_buf_state_local.flush_to_file = 0; > + /* Then write out the "updated local" through xe_map_wr() */ > + xe_map_wr(guc_to_xe(guc), &guc->log.bo->vmap, > + log_buf_state_offset + offsetof(struct guc_log_buffer_state, flags), u32, > + log_buf_state_local.flags); > + __guc_capture_flushlog_complete(guc); > +} > + public functions require kernel-doc > +void xe_guc_capture_process(struct xe_guc *guc) > +{ > + if (guc->capture) > + __guc_capture_process_output(guc); > +} > + > +static struct __guc_capture_parsed_output * > +guc_capture_alloc_one_node(struct xe_guc *guc) > +{ > + struct drm_device *drm = guc_to_drm(guc); > + struct __guc_capture_parsed_output *new; > + int i; > + > + new = drmm_kzalloc(drm, sizeof(*new), GFP_KERNEL); > + if (!new) > + return NULL; > + > + for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { > + new->reginfo[i].regs = drmm_kzalloc(drm, guc->capture->max_mmio_per_node * > + sizeof(struct guc_mmio_reg), GFP_KERNEL); > + if (!new->reginfo[i].regs) { > + while (i) > + drmm_kfree(drm, new->reginfo[--i].regs); > + drmm_kfree(drm, new); > + return NULL; > + } > + } > + guc_capture_init_node(guc, new); > + > + return new; > +} > + > +static void > +__guc_capture_create_prealloc_nodes(struct xe_guc *guc) > +{ > + struct __guc_capture_parsed_output *node = NULL; > + int i; > + > + for (i = 0; i < PREALLOC_NODES_MAX_COUNT; ++i) { > + node = guc_capture_alloc_one_node(guc); > + if (!node) { > + xe_gt_warn(guc_to_gt(guc), "Register capture pre-alloc-cache failure\n"); > + /* dont free the priors, use what we got and cleanup at shutdown */ > + return; > + } > + guc_capture_add_node_to_cachelist(guc->capture, node); > + } > +} > + > +static int > +guc_get_max_reglist_count(struct xe_guc *guc) > +{ > + int i, j, k, tmp, maxregcount = 0; > + > + for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; ++i) { > + for (j = 0; j < GUC_CAPTURE_LIST_TYPE_MAX; ++j) { > + for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) { > + if (j == GUC_CAPTURE_LIST_TYPE_GLOBAL && k > 0) > + continue; > + > + tmp = guc_cap_list_num_regs(guc->capture, i, j, k); > + if (tmp > maxregcount) > + maxregcount = tmp; > + } > + } > + } > + if (!maxregcount) > + maxregcount = PREALLOC_NODES_DEFAULT_NUMREGS; > + > + return maxregcount; > +} > + > +static void > +guc_capture_create_prealloc_nodes(struct xe_guc *guc) > +{ > + /* skip if we've already done the pre-alloc */ > + if (guc->capture->max_mmio_per_node) > + return; > + > + guc->capture->max_mmio_per_node = guc_get_max_reglist_count(guc); > + __guc_capture_create_prealloc_nodes(guc); > +} > + > +static void cp_reg_to_snapshot(int type, u16 hwe_guc_class, u32 offset, u32 value, > + struct snapshot_regs *regs) > +{ > + int i; > + const struct __guc_mmio_reg_descr_group *list; > + > + /* Get register list for the type/class */ > + list = xe_guc_capture_get_reg_desc_list(GUC_CAPTURE_LIST_INDEX_PF, type, > + xe_guc_class_to_capture_class(hwe_guc_class)); > + if (!list) > + return; > + > + for (i = 0; i < list->num_regs; i++) > + if (offset == list->list[i].reg.addr) { > + u32 *field = (u32 *)((uintptr_t)regs + list->list[i].position_in_snapshot); > + *field = value; > + return; > + } > +} > + > +static void guc_capture_parse_reglist(struct __guc_capture_parsed_output *node, > + struct xe_hw_engine_snapshot *snapshot, u16 hwe_guc_class) > +{ > + int i, type; > + > + if (!node) > + return; > + > + for (type = GUC_CAPTURE_LIST_TYPE_GLOBAL; type < GUC_CAPTURE_LIST_TYPE_MAX; type++) { > + struct gcap_reg_list_info *reginfo = &node->reginfo[type]; > + struct guc_mmio_reg *regs = reginfo->regs; > + > + for (i = 0; i < reginfo->num_regs; i++) > + cp_reg_to_snapshot(type, hwe_guc_class, regs[i].offset, regs[i].value, > + &snapshot->reg); > + } > +} > + > +/** > + * xe_hw_engine_find_and_copy_guc_capture_snapshot - Take a engine snapshot from GuC capture. > + * @hwe: Xe HW Engine. > + * @snapshot: Xe HW Engine snapshot object to save data, copied from error capture > + * > + * This can be printed out in a later stage like during dev_coredump > + * analysis. > + * > + * Returns: None > + */ > +void > +xe_hw_engine_find_and_copy_guc_capture_snapshot(struct xe_hw_engine *hwe, > + struct xe_hw_engine_snapshot *snapshot) > +{ > + struct xe_gt *gt = hwe->gt; > + struct xe_device *xe = gt_to_xe(gt); > + struct xe_guc *guc = >->uc.guc; > + struct __guc_capture_parsed_output *n, *ntmp; > + struct xe_devcoredump *devcoredump = &xe->devcoredump; > + struct list_head *list = &guc->capture->outlist; > + struct xe_sched_job *job = devcoredump->job; > + struct xe_guc_submit_exec_queue_snapshot *ge = devcoredump->snapshot.ge; > + u16 guc_id = ge->guc.id; > + u32 lrca; > + u16 hwe_guc_class = xe_engine_class_to_guc_class(hwe->class); > + > + lrca = xe_lrc_ggtt_addr(job->q->lrc[0]) & LRC_GTT_ADDRESS_MASK; > + > + /* > + * Look for a matching GuC reported error capture node from > + * the internal output link-list based on engine class and instance. > + */ > + list_for_each_entry_safe(n, ntmp, list, link) { > + if (n->eng_class == hwe_guc_class && n->eng_inst == hwe->instance && > + n->guc_id == guc_id && (n->lrca & LRC_GTT_ADDRESS_MASK) == lrca) { > + guc_capture_parse_reglist(n, snapshot, hwe_guc_class); > + list_del(&n->link); > + return; > + } > + } > +} > + > +void xe_guc_capture_free(struct xe_guc *guc) > +{ > + if (guc->capture && !list_empty(&guc->capture->outlist)) { > + struct __guc_capture_parsed_output *n, *ntmp; > + > + list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) { > + list_del(&n->link); > + /* put node back to cache list */ > + /* No need to init here, guc_capture_get_prealloc_node init it later */ > + guc_capture_add_node_to_cachelist(guc->capture, n); > + } > + } > +} > + > int xe_guc_capture_init(struct xe_guc *guc) > { > guc->capture = drmm_kzalloc(guc_to_drm(guc), sizeof(*guc->capture), GFP_KERNEL); > @@ -574,7 +1404,9 @@ int xe_guc_capture_init(struct xe_guc *guc) > return -ENOMEM; > > guc->capture->reglists = guc_capture_get_device_reglist(guc); > - > check_guc_capture_size(guc); > + INIT_LIST_HEAD(&guc->capture->outlist); > + INIT_LIST_HEAD(&guc->capture->cachelist); > + > return 0; > } > diff --git a/drivers/gpu/drm/xe/xe_guc_capture.h b/drivers/gpu/drm/xe/xe_guc_capture.h > index a62b1dbd47a6..c0bada99c9ec 100644 > --- a/drivers/gpu/drm/xe/xe_guc_capture.h > +++ b/drivers/gpu/drm/xe/xe_guc_capture.h > @@ -10,6 +10,8 @@ > #include "regs/xe_reg_defs.h" > > struct xe_guc; > +struct xe_hw_engine; > +struct xe_hw_engine_snapshot; > > /* > * struct __guc_mmio_reg_descr / struct __guc_mmio_reg_descr_group > @@ -25,6 +27,7 @@ struct __guc_mmio_reg_descr { > u32 flags; > u32 mask; > const char *regname; > + u32 position_in_snapshot; > }; > > struct __guc_mmio_reg_descr_group { > @@ -36,9 +39,15 @@ struct __guc_mmio_reg_descr_group { > struct __guc_mmio_reg_descr *extlist; /* only used for steered registers */ > }; > > +void xe_guc_capture_process(struct xe_guc *guc); > int xe_guc_capture_getlist(struct xe_guc *guc, u32 owner, u32 type, u32 classid, void **outptr); > int xe_guc_capture_getlistsize(struct xe_guc *guc, u32 owner, u32 type, u32 classid, size_t *size); > int xe_guc_capture_getnullheader(struct xe_guc *guc, void **outptr, size_t *size); > +const struct __guc_mmio_reg_descr_group * > +xe_guc_capture_get_reg_desc_list(u32 owner, u32 type, u32 engine_classid); > +void xe_hw_engine_find_and_copy_guc_capture_snapshot(struct xe_hw_engine *hwe, > + struct xe_hw_engine_snapshot *snapshot); > +void xe_guc_capture_free(struct xe_guc *guc); > int xe_guc_capture_init(struct xe_guc *guc); > > #endif /* _XE_GUC_CAPTURE_H */ > diff --git a/drivers/gpu/drm/xe/xe_guc_capture_fwif.h b/drivers/gpu/drm/xe/xe_guc_capture_fwif.h > index 199e3c0108a4..5ef8c20fe9bc 100644 > --- a/drivers/gpu/drm/xe/xe_guc_capture_fwif.h > +++ b/drivers/gpu/drm/xe/xe_guc_capture_fwif.h > @@ -10,6 +10,51 @@ > > #include "xe_guc_fwif.h" > > +/* > + * struct __guc_capture_bufstate > + * > + * Book-keeping structure used to track read and write pointers > + * as we extract error capture data from the GuC-log-buffer's > + * error-capture region as a stream of dwords. > + */ > +struct __guc_capture_bufstate { > + u32 size; > + u32 data_offset; > + u32 rd; > + u32 wr; > +}; > + > +/* > + * struct __guc_capture_parsed_output - extracted error capture node > + * > + * A single unit of extracted error-capture output data grouped together > + * at an engine-instance level. We keep these nodes in a linked list. > + * See cachelist and outlist below. > + */ > +struct __guc_capture_parsed_output { > + /* > + * A single set of 3 capture lists: a global-list > + * an engine-class-list and an engine-instance list. > + * outlist in __guc_capture_parsed_output will keep > + * a linked list of these nodes that will eventually > + * be detached from outlist and attached into to > + * xe_codedump in response to a context reset > + */ > + struct list_head link; > + bool is_partial; > + u32 eng_class; > + u32 eng_inst; > + u32 guc_id; > + u32 lrca; > + struct gcap_reg_list_info { > + u32 vfid; > + u32 num_regs; > + struct guc_mmio_reg *regs; > + } reginfo[GUC_CAPTURE_LIST_TYPE_MAX]; > +#define GCAP_PARSED_REGLIST_INDEX_GLOBAL BIT(GUC_CAPTURE_LIST_TYPE_GLOBAL) > +#define GCAP_PARSED_REGLIST_INDEX_ENGCLASS BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS) > +}; > + > /* > * struct guc_debug_capture_list_header / struct guc_debug_capture_list > * > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c > index c1f258348f5c..865b58bb4fd9 100644 > --- a/drivers/gpu/drm/xe/xe_guc_ct.c > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c > @@ -1045,6 +1045,8 @@ static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len) > /* Selftest only at the moment */ > break; > case XE_GUC_ACTION_STATE_CAPTURE_NOTIFICATION: > + ret = xe_guc_error_capture_handler(guc, payload, adj_len); > + break; > case XE_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE: > /* FIXME: Handle this */ > break; > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h > index 908298791c93..f8f9c76eb7ac 100644 > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h > @@ -206,6 +206,12 @@ enum guc_capture_type { > GUC_CAPTURE_LIST_TYPE_MAX, > }; > > +/* GuC support limited registers range to be captured for debug purpose, > + * for unsupported registers, direct read is the only way to save the data. > + * GuC capture handling will ignore all lists with this type: GUC_CAPTURE_LIST_TYPE_DIRECT_READ > + */ > +#define GUC_CAPTURE_LIST_TYPE_DIRECT_READ GUC_CAPTURE_LIST_TYPE_MAX > + > /* Class indecies for capture_class and capture_instance arrays */ > enum { > GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE = 0, > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c > index 47aab04cf34f..f02f4c0c9568 100644 > --- a/drivers/gpu/drm/xe/xe_guc_submit.c > +++ b/drivers/gpu/drm/xe/xe_guc_submit.c > @@ -25,6 +25,7 @@ > #include "xe_gt.h" > #include "xe_gt_printk.h" > #include "xe_guc.h" > +#include "xe_guc_capture.h" > #include "xe_guc_ct.h" > #include "xe_guc_exec_queue_types.h" > #include "xe_guc_id_mgr.h" > @@ -769,7 +770,7 @@ static void guc_exec_queue_free_job(struct drm_sched_job *drm_job) > xe_sched_job_put(job); > } > > -static int guc_read_stopped(struct xe_guc *guc) > +int xe_guc_read_stopped(struct xe_guc *guc) > { > return atomic_read(&guc->submission_state.stopped); > } > @@ -791,7 +792,7 @@ static void disable_scheduling_deregister(struct xe_guc *guc, > set_min_preemption_timeout(guc, q); > smp_rmb(); > ret = wait_event_timeout(guc->ct.wq, !exec_queue_pending_enable(q) || > - guc_read_stopped(guc), HZ * 5); > + xe_guc_read_stopped(guc), HZ * 5); > if (!ret) { > struct xe_gpu_scheduler *sched = &q->guc->sched; > > @@ -906,7 +907,7 @@ static void xe_guc_exec_queue_lr_cleanup(struct work_struct *w) > */ > ret = wait_event_timeout(guc->ct.wq, > !exec_queue_pending_disable(q) || > - guc_read_stopped(guc), HZ * 5); > + xe_guc_read_stopped(guc), HZ * 5); > if (!ret) { > drm_warn(&xe->drm, "Schedule disable failed to respond"); > xe_sched_submission_start(sched); > @@ -929,6 +930,8 @@ guc_exec_queue_timedout_job(struct drm_sched_job *drm_job) > int err = -ETIME; > int i = 0; > bool wedged; > + bool reset_status = exec_queue_reset(q); > + bool guc_en = xe_device_uc_enabled(xe); > > /* > * TDR has fired before free job worker. Common if exec queue > @@ -948,7 +951,15 @@ guc_exec_queue_timedout_job(struct drm_sched_job *drm_job) > xe_gt_WARN(q->gt, q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q), > "VM job timed out on non-killed execqueue\n"); > > - if (!exec_queue_killed(q)) > + /* take devcoredump on: > + * 1. GuC not enabled > + * 2. GuC enabled with GuC reset status == 1 > + * When GuC enabled, register value is captured by GuC, GuC will notify host > + * with capture notification message, which is right before reset. > + * GuC reset status 1 also means capture ready. > + * If not ready, will take snapshot after wait event within this function. > + */ > + if (!exec_queue_killed(q) && (!guc_en || (guc_en && reset_status))) > xe_devcoredump(job); > > trace_xe_sched_job_timedout(job); > @@ -996,8 +1007,8 @@ guc_exec_queue_timedout_job(struct drm_sched_job *drm_job) > smp_rmb(); > ret = wait_event_timeout(guc->ct.wq, > !exec_queue_pending_disable(q) || > - guc_read_stopped(guc), HZ * 5); > - if (!ret || guc_read_stopped(guc)) { > + xe_guc_read_stopped(guc), HZ * 5); > + if (!ret || xe_guc_read_stopped(guc)) { > drm_warn(&xe->drm, "Schedule disable failed to respond"); > xe_sched_add_pending_job(sched, job); > xe_sched_submission_start(sched); > @@ -1007,6 +1018,10 @@ guc_exec_queue_timedout_job(struct drm_sched_job *drm_job) > } > } > > + /* When entring this function, if capture/reset not ready, now is time to take snapshot */ > + if (!exec_queue_killed(q) && guc_en && !reset_status) > + xe_devcoredump(job); > + > /* Stop fence signaling */ > xe_hw_fence_irq_stop(q->fence_irq); > > @@ -1112,7 +1127,7 @@ static void suspend_fence_signal(struct xe_exec_queue *q) > struct xe_device *xe = guc_to_xe(guc); > > xe_assert(xe, exec_queue_suspended(q) || exec_queue_killed(q) || > - guc_read_stopped(guc)); > + xe_guc_read_stopped(guc)); > xe_assert(xe, q->guc->suspend_pending); > > q->guc->suspend_pending = false; > @@ -1128,9 +1143,9 @@ static void __guc_exec_queue_process_msg_suspend(struct xe_sched_msg *msg) > if (guc_exec_queue_allowed_to_change_state(q) && !exec_queue_suspended(q) && > exec_queue_enabled(q)) { > wait_event(guc->ct.wq, q->guc->resume_time != RESUME_PENDING || > - guc_read_stopped(guc)); > + xe_guc_read_stopped(guc)); > > - if (!guc_read_stopped(guc)) { > + if (!xe_guc_read_stopped(guc)) { > MAKE_SCHED_CONTEXT_ACTION(q, DISABLE); > s64 since_resume_ms = > ktime_ms_delta(ktime_get(), > @@ -1258,7 +1273,7 @@ static int guc_exec_queue_init(struct xe_exec_queue *q) > > q->entity = &ge->entity; > > - if (guc_read_stopped(guc)) > + if (xe_guc_read_stopped(guc)) > xe_sched_stop(sched); > > mutex_unlock(&guc->submission_state.lock); > @@ -1385,7 +1400,7 @@ static void guc_exec_queue_suspend_wait(struct xe_exec_queue *q) > struct xe_guc *guc = exec_queue_to_guc(q); > > wait_event(q->guc->suspend_wait, !q->guc->suspend_pending || > - guc_read_stopped(guc)); > + xe_guc_read_stopped(guc)); > } > > static void guc_exec_queue_resume(struct xe_exec_queue *q) > @@ -1495,7 +1510,7 @@ int xe_guc_submit_reset_prepare(struct xe_guc *guc) > > void xe_guc_submit_reset_wait(struct xe_guc *guc) > { > - wait_event(guc->ct.wq, !guc_read_stopped(guc)); > + wait_event(guc->ct.wq, !xe_guc_read_stopped(guc)); > } > > void xe_guc_submit_stop(struct xe_guc *guc) > @@ -1504,7 +1519,7 @@ void xe_guc_submit_stop(struct xe_guc *guc) > unsigned long index; > struct xe_device *xe = guc_to_xe(guc); > > - xe_assert(xe, guc_read_stopped(guc) == 1); > + xe_assert(xe, xe_guc_read_stopped(guc) == 1); > > mutex_lock(&guc->submission_state.lock); > > @@ -1542,7 +1557,7 @@ int xe_guc_submit_start(struct xe_guc *guc) > unsigned long index; > struct xe_device *xe = guc_to_xe(guc); > > - xe_assert(xe, guc_read_stopped(guc) == 1); > + xe_assert(xe, xe_guc_read_stopped(guc) == 1); > > mutex_lock(&guc->submission_state.lock); > atomic_dec(&guc->submission_state.stopped); > @@ -1698,8 +1713,6 @@ int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) > xe_gt_info(gt, "Engine reset: engine_class=%s, logical_mask: 0x%x, guc_id=%d", > xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id); > > - /* FIXME: Do error capture, most likely async */ > - > trace_xe_exec_queue_reset(q); > > /* > @@ -1715,6 +1728,24 @@ int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) > return 0; > } > missing kerne-doc > +int xe_guc_error_capture_handler(struct xe_guc *guc, u32 *msg, u32 len) maybe this should be defined as xe_guc_capture_msg_handler() and placed in xe_guc_capture.c as it doesn't look that it needs anything from xe_guc_submit.c code > +{ > + u32 status; > + > + if (unlikely(len != 1)) { magic "1" > + xe_gt_dbg(guc_to_gt(guc), "Invalid length %u", len); > + return -EPROTO; > + } > + > + status = msg[0] & XE_GUC_STATE_CAPTURE_EVENT_STATUS_MASK; > + if (status == XE_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE) > + xe_gt_warn(guc_to_gt(guc), "G2H-Error capture no space"); btw, is there anything to capture if GuC reported 'NOSPACE' ? > + > + xe_guc_capture_process(guc); > + > + return 0; > +} > + > int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, > u32 len) > { > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.h b/drivers/gpu/drm/xe/xe_guc_submit.h > index 4ad5f4c1b084..d92256de473e 100644 > --- a/drivers/gpu/drm/xe/xe_guc_submit.h > +++ b/drivers/gpu/drm/xe/xe_guc_submit.h > @@ -19,12 +19,14 @@ void xe_guc_submit_reset_wait(struct xe_guc *guc); > void xe_guc_submit_stop(struct xe_guc *guc); > int xe_guc_submit_start(struct xe_guc *guc); > > +int xe_guc_read_stopped(struct xe_guc *guc); > int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len); > int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len); > int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len); > int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, > u32 len); > int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len); > +int xe_guc_error_capture_handler(struct xe_guc *guc, u32 *msg, u32 len); > > struct xe_guc_submit_exec_queue_snapshot * > xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q); > diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c > index 0a83506e1ad8..3bc88fbad952 100644 > --- a/drivers/gpu/drm/xe/xe_hw_engine.c > +++ b/drivers/gpu/drm/xe/xe_hw_engine.c > @@ -20,6 +20,9 @@ > #include "xe_gt_printk.h" > #include "xe_gt_mcr.h" > #include "xe_gt_topology.h" > +#include "xe_guc.h" > +#include "xe_guc_capture.h" > +#include "xe_guc_capture_fwif.h" > #include "xe_hw_fence.h" > #include "xe_irq.h" > #include "xe_lrc.h" > @@ -287,6 +290,7 @@ static void hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg, > static u32 hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg) > { > xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base)); > + unrelated > xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain); > > reg.addr += hwe->mmio_base; > @@ -825,6 +829,62 @@ xe_hw_engine_snapshot_instdone_capture(struct xe_hw_engine *hwe, > } > } > > +static void > +xe_hw_engine_snapshot_from_hw_by_type(struct xe_hw_engine *hwe, > + struct xe_hw_engine_snapshot *snapshot, int type) > +{ > + const struct __guc_mmio_reg_descr_group *list; > + u16 capture_class = xe_engine_class_to_guc_capture_class(hwe->class); > + int i; > + > + list = xe_guc_capture_get_reg_desc_list(GUC_CAPTURE_LIST_INDEX_PF, type, capture_class); > + if (!list) > + return; > + > + for (i = 0; i < list->num_regs; i++) { > + u32 *field; > + > + /* loop until extra operation registers zone */ > + if (list->list[i].reg.addr == XE_GUC_SNAPSHOT_EXTRA_OPERATION_REGS_START_REG_ADDR) > + break; > + > + field = (u32 *)((uintptr_t)&snapshot->reg + > + list->list[i].position_in_snapshot); > + if (type == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) > + *field = hw_engine_mmio_read32(hwe, list->list[i].reg); > + else > + *field = xe_mmio_read32(hwe->gt, list->list[i].reg); > + } > +} > + > +/** this is static function, no need to have true kernel-doc > + * xe_hw_engine_snapshot_from_hw - Take a quick engine snapshot from HW. > + * @hwe: Xe HW Engine. > + * @snapshot: Point to the Xe HW Engine snapshot object to save data. > + * > + * This can be printed out in a later stage like during dev_coredump > + * analysis. > + * > + * Returns: None > + */ > +static void > +xe_hw_engine_snapshot_from_hw(struct xe_hw_engine *hwe, struct xe_hw_engine_snapshot *snapshot) > +{ > + int type; > + > + for (type = GUC_CAPTURE_LIST_TYPE_GLOBAL; type < GUC_CAPTURE_LIST_TYPE_MAX; type++) > + xe_hw_engine_snapshot_from_hw_by_type(hwe, snapshot, type); > + > + /* Extra operation required registers zone - start */ > + if (xe_gt_has_indirect_ring_state(hwe->gt)) > + snapshot->reg.indirect_ring_state = > + hw_engine_mmio_read32(hwe, INDIRECT_RING_STATE(0)); > + /* Extra operation required registers zone - End */ > + > + /* Capture steering registers */ > + xe_hw_engine_snapshot_instdone_capture(hwe, snapshot); > +} > + > /** > * xe_hw_engine_snapshot_capture - Take a quick snapshot of the HW Engine. > * @hwe: Xe HW Engine. > @@ -839,8 +899,12 @@ struct xe_hw_engine_snapshot * > xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe) > { > struct xe_hw_engine_snapshot *snapshot; > + struct xe_gt *gt = hwe->gt; > + struct xe_device *xe = gt_to_xe(gt); > + struct xe_guc *guc = >->uc.guc; > size_t len; > - u64 val; > + u32 i; > + bool endian_convert_required; > > if (!xe_hw_engine_is_valid(hwe)) > return NULL; > @@ -850,6 +914,9 @@ xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe) > if (!snapshot) > return NULL; > > + i = 0x01020304; > + endian_convert_required = (i != le32_to_cpu(i)); > + > /* Because XE_MAX_DSS_FUSE_BITS is defined in xe_gt_types.h and it > * includes xe_hw_engine_types.h the length of this 3 registers can't be > * set in struct xe_hw_engine_snapshot, so here doing additional > @@ -881,62 +948,35 @@ xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe) > snapshot->mmio_base = hwe->mmio_base; > > /* no more VF accessible data below this point */ > - if (IS_SRIOV_VF(gt_to_xe(hwe->gt))) > + if (IS_SRIOV_VF(xe)) > return snapshot; > > - snapshot->reg.ring_execlist_status = > - hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0)); > - val = hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0)); > - snapshot->reg.ring_execlist_status |= val << 32; > - > - snapshot->reg.ring_execlist_sq_contents = > - hw_engine_mmio_read32(hwe, RING_EXECLIST_SQ_CONTENTS_LO(0)); > - val = hw_engine_mmio_read32(hwe, RING_EXECLIST_SQ_CONTENTS_HI(0)); > - snapshot->reg.ring_execlist_sq_contents |= val << 32; > - > - snapshot->reg.ring_acthd = hw_engine_mmio_read32(hwe, RING_ACTHD(0)); > - val = hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0)); > - snapshot->reg.ring_acthd |= val << 32; > - > - snapshot->reg.ring_bbaddr = hw_engine_mmio_read32(hwe, RING_BBADDR(0)); > - val = hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0)); > - snapshot->reg.ring_bbaddr |= val << 32; > - > - snapshot->reg.ring_dma_fadd = > - hw_engine_mmio_read32(hwe, RING_DMA_FADD(0)); > - val = hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0)); > - snapshot->reg.ring_dma_fadd |= val << 32; > - > - snapshot->reg.ring_hwstam = hw_engine_mmio_read32(hwe, RING_HWSTAM(0)); > - snapshot->reg.ring_hws_pga = hw_engine_mmio_read32(hwe, RING_HWS_PGA(0)); > - snapshot->reg.ring_start = hw_engine_mmio_read32(hwe, RING_START(0)); > - if (GRAPHICS_VERx100(hwe->gt->tile->xe) >= 2000) { > - val = hw_engine_mmio_read32(hwe, RING_START_UDW(0)); > - snapshot->reg.ring_start |= val << 32; > - } > - if (xe_gt_has_indirect_ring_state(hwe->gt)) { > - snapshot->reg.indirect_ring_state = > - hw_engine_mmio_read32(hwe, INDIRECT_RING_STATE(0)); > + /* Check GuC settings, job is set and capture outlist not empty, > + * otherwise take it from engine > + */ > + if (xe_device_uc_enabled(xe) && xe->wedged.mode >= 1 && > + !list_empty(&guc->capture->outlist) && xe->devcoredump.job) > + xe_hw_engine_find_and_copy_guc_capture_snapshot(hwe, snapshot); > + else > + xe_hw_engine_snapshot_from_hw(hwe, snapshot); > + > + /* Read registers defined in "Direct read" list */ > + xe_hw_engine_snapshot_from_hw_by_type(hwe, snapshot, GUC_CAPTURE_LIST_TYPE_DIRECT_READ); > + > + /* appy mask for ring head and tail */ > + snapshot->reg.ring_head &= HEAD_ADDR; > + snapshot->reg.ring_tail &= TAIL_ADDR; > + > + /* adjust u64 endine in snapshot if needed */ > + if (endian_convert_required) { > + for (i = 0; i < XE_GUC_SNAPSHOT_REGS_U32_START_OFFSET; i += sizeof(u64)) { > + u64 *pdata = (u64 *)((ulong)&snapshot->reg + i); > + u32 *pl = (u32 *)pdata; > + u32 *ph = (u32 *)((ulong)pdata + 4); > + *pdata = ((u64)*ph) << 32 | *pl; > + } > } > > - snapshot->reg.ring_head = > - hw_engine_mmio_read32(hwe, RING_HEAD(0)) & HEAD_ADDR; > - snapshot->reg.ring_tail = > - hw_engine_mmio_read32(hwe, RING_TAIL(0)) & TAIL_ADDR; > - snapshot->reg.ring_ctl = hw_engine_mmio_read32(hwe, RING_CTL(0)); > - snapshot->reg.ring_mi_mode = > - hw_engine_mmio_read32(hwe, RING_MI_MODE(0)); > - snapshot->reg.ring_mode = hw_engine_mmio_read32(hwe, RING_MODE(0)); > - snapshot->reg.ring_imr = hw_engine_mmio_read32(hwe, RING_IMR(0)); > - snapshot->reg.ring_esr = hw_engine_mmio_read32(hwe, RING_ESR(0)); > - snapshot->reg.ring_emr = hw_engine_mmio_read32(hwe, RING_EMR(0)); > - snapshot->reg.ring_eir = hw_engine_mmio_read32(hwe, RING_EIR(0)); > - snapshot->reg.ipehr = hw_engine_mmio_read32(hwe, RING_IPEHR(0)); > - xe_hw_engine_snapshot_instdone_capture(hwe, snapshot); > - > - if (snapshot->hwe->class == XE_ENGINE_CLASS_COMPUTE) > - snapshot->reg.rcu_mode = xe_mmio_read32(hwe->gt, RCU_MODE); > - > return snapshot; > } > > @@ -993,6 +1033,8 @@ xe_hw_engine_snapshot_instdone_print(struct xe_hw_engine_snapshot *snapshot, str > void xe_hw_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot, > struct drm_printer *p) > { > + int i, type; > + > if (!snapshot) > return; > > @@ -1001,34 +1043,52 @@ void xe_hw_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot, > snapshot->logical_instance); > drm_printf(p, "\tForcewake: domain 0x%x, ref %d\n", > snapshot->forcewake.domain, snapshot->forcewake.ref); > - drm_printf(p, "\tHWSTAM: 0x%08x\n", snapshot->reg.ring_hwstam); > - drm_printf(p, "\tRING_HWS_PGA: 0x%08x\n", snapshot->reg.ring_hws_pga); > - drm_printf(p, "\tRING_EXECLIST_STATUS: 0x%016llx\n", > - snapshot->reg.ring_execlist_status); > - drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS: 0x%016llx\n", > - snapshot->reg.ring_execlist_sq_contents); > - drm_printf(p, "\tRING_START: 0x%016llx\n", snapshot->reg.ring_start); > - drm_printf(p, "\tRING_HEAD: 0x%08x\n", snapshot->reg.ring_head); > - drm_printf(p, "\tRING_TAIL: 0x%08x\n", snapshot->reg.ring_tail); > - drm_printf(p, "\tRING_CTL: 0x%08x\n", snapshot->reg.ring_ctl); > - drm_printf(p, "\tRING_MI_MODE: 0x%08x\n", snapshot->reg.ring_mi_mode); > - drm_printf(p, "\tRING_MODE: 0x%08x\n", > - snapshot->reg.ring_mode); > - drm_printf(p, "\tRING_IMR: 0x%08x\n", snapshot->reg.ring_imr); > - drm_printf(p, "\tRING_ESR: 0x%08x\n", snapshot->reg.ring_esr); > - drm_printf(p, "\tRING_EMR: 0x%08x\n", snapshot->reg.ring_emr); > - drm_printf(p, "\tRING_EIR: 0x%08x\n", snapshot->reg.ring_eir); > - drm_printf(p, "\tACTHD: 0x%016llx\n", snapshot->reg.ring_acthd); > - drm_printf(p, "\tBBADDR: 0x%016llx\n", snapshot->reg.ring_bbaddr); > - drm_printf(p, "\tDMA_FADDR: 0x%016llx\n", snapshot->reg.ring_dma_fadd); > - drm_printf(p, "\tINDIRECT_RING_STATE: 0x%08x\n", > - snapshot->reg.indirect_ring_state); > - drm_printf(p, "\tIPEHR: 0x%08x\n", snapshot->reg.ipehr); > + > + /* Print will include direct read list in this main loop */ > + for (type = GUC_CAPTURE_LIST_TYPE_GLOBAL; type <= GUC_CAPTURE_LIST_TYPE_DIRECT_READ; > + type++) { > + const struct __guc_mmio_reg_descr_group *list; > + u16 capture_class = xe_engine_class_to_guc_capture_class(snapshot->hwe->class); > + > + /* Capture engine registers */ > + list = xe_guc_capture_get_reg_desc_list(GUC_CAPTURE_LIST_INDEX_PF, type, > + capture_class); > + if (!list) > + continue; > + > + /* loop 32bit registers until 64 bit registers */ > + for (i = 0; i < list->num_regs; i++) { > + u32 *field; > + > + if (list->list[i].reg.addr == XE_GUC_SNAPSHOT_REGS_U64_START_REG_ADDR) > + break; > + field = (u32 *)((uintptr_t)&snapshot->reg + > + list->list[i].position_in_snapshot); > + drm_printf(p, "\t%s: 0x%08x\n", list->list[i].regname, *field); > + } > + > + if (type != GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) > + continue; /* 64bit and special registers is for engine instance only */ > + > + /* loop 64 bit registers until special registers */ > + for (; i < list->num_regs; i += 2) { > + u64 *field; > + > + if (list->list[i].reg.addr == > + XE_GUC_SNAPSHOT_EXTRA_OPERATION_REGS_START_REG_ADDR) > + break; > + field = (u64 *)((uintptr_t)&snapshot->reg + > + list->list[i].position_in_snapshot); > + drm_printf(p, "\t%s: 0x%016llx\n", list->list[i].regname, *field); > + } > + > + /* Handling special registers - Start */ > + drm_printf(p, "\tINDIRECT_RING_STATE: 0x%08x\n", snapshot->reg.indirect_ring_state); > + /* Handling special registers - End */ > + } > + > xe_hw_engine_snapshot_instdone_print(snapshot, p); > > - if (snapshot->hwe->class == XE_ENGINE_CLASS_COMPUTE) > - drm_printf(p, "\tRCU_MODE: 0x%08x\n", > - snapshot->reg.rcu_mode); > drm_puts(p, "\n"); > } > > diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h > index 580bbd7e83b2..617101dca272 100644 > --- a/drivers/gpu/drm/xe/xe_hw_engine_types.h > +++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h > @@ -150,6 +150,106 @@ struct xe_hw_engine { > struct xe_hw_engine_class_intf *eclass; > }; > > +/** > + * struct xe_hw_engine_snapshot - Hardware engine snapshot > + * > + * Contains the snapshot of useful hardware engine info and registers. > + */ > +struct snapshot_regs { > + /* Engine instance type - start */ > + /* 64 bit registers zone - start */ > + /* > + * u64 data captured by 2 u32s from GuC or by hw read. > + * Save data into this u64 zone will always write in format of: > + * offset + 0000: [low 32] > + * offset + 0004: [high 32] > + * Once all data captured, data will be converted to CPU endian order if needed at the > + * end of xe_hw_engine_snapshot_capture > + */ > + #define XE_GUC_SNAPSHOT_REGS_U64_START_REG_ADDR RING_ACTHD(0).addr > + /** @ring_acthd: RING_ACTHD */ > + u64 ring_acthd; > + /** @ring_bbaddr: RING_BBADDR */ > + u64 ring_bbaddr; > + /** @ring_start: RING_START */ > + u64 ring_start; > + /** @ring_dma_fadd: RING_DMA_FADD */ > + u64 ring_dma_fadd; > + /** @ring_execlist_status: RING_EXECLIST_STATUS */ > + u64 ring_execlist_status; > + /** @ring_execlist_sq_contents: RING_EXECLIST_SQ_CONTENTS */ > + u64 ring_execlist_sq_contents; > + /* 64 bit registers zone - end */ > + > + /* 32 bit registers zone - start */ > + /** @reg.ring_hwstam: RING_HWSTAM */ > + u32 ring_hwstam; > + #define XE_GUC_SNAPSHOT_REGS_U32_START_OFFSET offsetof(struct snapshot_regs, ring_hwstam) > + > + /** @reg.ring_hws_pga: RING_HWS_PGA */ > + u32 ring_hws_pga; > + u32 ring_head; > + /** @reg.ring_tail: RING_TAIL */ > + u32 ring_tail; > + /** @reg.ring_ctl: RING_CTL */ > + u32 ring_ctl; > + /** @reg.ring_mi_mode: RING_MI_MODE */ > + u32 ring_mi_mode; > + /** @reg.ring_mode: RING_MODE */ > + u32 ring_mode; > + /** @reg.ring_imr: RING_IMR */ > + u32 ring_imr; > + /** @reg.ring_esr: RING_ESR */ > + u32 ring_esr; > + /** @reg.ring_emr: RING_EMR */ > + u32 ring_emr; > + /** @reg.ring_eir: RING_EIR */ > + u32 ring_eir; > + /** @reg.ipehr: IPEHR */ > + u32 ipehr; > + /* Engine instance type - end */ > + > + /* Engine class type - start */ > + /** @reg.rcu_mode: RCU_MODE */ > + u32 rcu_mode; > + /** @reg.sfc_done_[0-3]: SFC_DONE[0-3] */ > + u32 sfc_done_0; > + u32 sfc_done_1; > + u32 sfc_done_2; > + u32 sfc_done_3; > + /* Engine class type - end */ > + > + /* Global type - start */ > + /** @reg.forcewake_gt: FORCEWAKE_GT */ > + u32 forcewake_gt; > + /* Global type - end */ > + > + /* Extra operation Registers zone - start */ > + /* registers requires extra code to handling */ > + #define XE_GUC_SNAPSHOT_EXTRA_OPERATION_REGS_START_REG_ADDR INDIRECT_RING_STATE(0).addr > + /** @reg.indirect_ring_state: INDIRECT_RING_STATE */ > + u32 indirect_ring_state; > + /* Special registers zone - end */ > + > + /* Steering registers */ > + struct { > + /** @reg.instdone.ring: RING_INSTDONE */ > + u32 ring; > + /** @reg.instdone.slice_common: SC_INSTDONE */ > + u32 *slice_common; > + /** @reg.instdone.slice_common_extra: SC_INSTDONE_EXTRA */ > + u32 *slice_common_extra; > + /** @reg.instdone.slice_common_extra2: SC_INSTDONE_EXTRA2 */ > + u32 *slice_common_extra2; > + /** @reg.instdone.sampler: SAMPLER_INSTDONE */ > + u32 *sampler; > + /** @reg.instdone.row: ROW_INSTDONE */ > + u32 *row; > + /** @reg.instdone.geom_svg: INSTDONE_GEOM_SVGUNIT */ > + u32 *geom_svg; > + } instdone; > +}; > + > /** > * struct xe_hw_engine_snapshot - Hardware engine snapshot > * > @@ -172,64 +272,7 @@ struct xe_hw_engine_snapshot { > /** @mmio_base: MMIO base address of this hw engine*/ > u32 mmio_base; > /** @reg: Useful MMIO register snapshot */ > - struct { > - /** @reg.ring_execlist_status: RING_EXECLIST_STATUS */ > - u64 ring_execlist_status; > - /** @reg.ring_execlist_sq_contents: RING_EXECLIST_SQ_CONTENTS */ > - u64 ring_execlist_sq_contents; > - /** @reg.ring_acthd: RING_ACTHD */ > - u64 ring_acthd; > - /** @reg.ring_bbaddr: RING_BBADDR */ > - u64 ring_bbaddr; > - /** @reg.ring_dma_fadd: RING_DMA_FADD */ > - u64 ring_dma_fadd; > - /** @reg.ring_hwstam: RING_HWSTAM */ > - u32 ring_hwstam; > - /** @reg.ring_hws_pga: RING_HWS_PGA */ > - u32 ring_hws_pga; > - /** @reg.ring_start: RING_START */ > - u64 ring_start; > - /** @reg.ring_head: RING_HEAD */ > - u32 ring_head; > - /** @reg.ring_tail: RING_TAIL */ > - u32 ring_tail; > - /** @reg.ring_ctl: RING_CTL */ > - u32 ring_ctl; > - /** @reg.ring_mi_mode: RING_MI_MODE */ > - u32 ring_mi_mode; > - /** @reg.ring_mode: RING_MODE */ > - u32 ring_mode; > - /** @reg.ring_imr: RING_IMR */ > - u32 ring_imr; > - /** @reg.ring_esr: RING_ESR */ > - u32 ring_esr; > - /** @reg.ring_emr: RING_EMR */ > - u32 ring_emr; > - /** @reg.ring_eir: RING_EIR */ > - u32 ring_eir; > - /** @reg.indirect_ring_state: INDIRECT_RING_STATE */ > - u32 indirect_ring_state; > - /** @reg.ipehr: IPEHR */ > - u32 ipehr; > - /** @reg.rcu_mode: RCU_MODE */ > - u32 rcu_mode; > - struct { > - /** @reg.instdone.ring: RING_INSTDONE */ > - u32 ring; > - /** @reg.instdone.slice_common: SC_INSTDONE */ > - u32 *slice_common; > - /** @reg.instdone.slice_common_extra: SC_INSTDONE_EXTRA */ > - u32 *slice_common_extra; > - /** @reg.instdone.slice_common_extra2: SC_INSTDONE_EXTRA2 */ > - u32 *slice_common_extra2; > - /** @reg.instdone.sampler: SAMPLER_INSTDONE */ > - u32 *sampler; > - /** @reg.instdone.row: ROW_INSTDONE */ > - u32 *row; > - /** @reg.instdone.geom_svg: INSTDONE_GEOM_SVGUNIT */ > - u32 *geom_svg; > - } instdone; > - } reg; > + struct snapshot_regs reg; > }; > > #endif > diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h > index 882c3437ba5c..8c83601fc695 100644 > --- a/drivers/gpu/drm/xe/xe_lrc.h > +++ b/drivers/gpu/drm/xe/xe_lrc.h > @@ -21,6 +21,7 @@ struct xe_lrc_snapshot; > struct xe_vm; > > #define LRC_PPHWSP_SCRATCH_ADDR (0x34 * 4) > +#define LRC_GTT_ADDRESS_MASK GENMASK(31, 12) > > struct xe_lrc *xe_lrc_create(struct xe_hw_engine *hwe, struct xe_vm *vm, > u32 ring_size); ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v9 4/4] drm/xe/guc: Extract GuC capture lists to register snapshot 2024-06-14 12:31 ` Michal Wajdeczko @ 2024-06-19 20:04 ` Dong, Zhanjun 0 siblings, 0 replies; 24+ messages in thread From: Dong, Zhanjun @ 2024-06-19 20:04 UTC (permalink / raw) To: Michal Wajdeczko, intel-xe Please see my comments inline below. Zhanjun On 2024-06-14 8:31 a.m., Michal Wajdeczko wrote: ... >> diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h >> index ddfa855458ab..e1afda9070f4 100644 >> --- a/drivers/gpu/drm/xe/xe_guc.h >> +++ b/drivers/gpu/drm/xe/xe_guc.h >> @@ -59,6 +59,29 @@ static inline u16 xe_engine_class_to_guc_class(enum xe_engine_class class) >> } >> } >> >> +static inline u16 xe_guc_class_to_capture_class(uint class) >> +{ >> + switch (class) { >> + case GUC_RENDER_CLASS: >> + case GUC_COMPUTE_CLASS: >> + return GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE; >> + case GUC_GSC_OTHER_CLASS: >> + return GUC_CAPTURE_LIST_CLASS_GSC_OTHER; >> + case GUC_VIDEO_CLASS: >> + case GUC_VIDEOENHANCE_CLASS: >> + case GUC_BLITTER_CLASS: >> + return class; >> + default: >> + XE_WARN_ON(class); >> + return -1; > > it doesn't look like a safe value nor that you handle it correctly The converted class ID will be used to find the match class in the list and NOT be used as index of array, so the -1 for search is safe. > >> + } >> +} >> + >> +static inline u16 xe_engine_class_to_guc_capture_class(enum xe_engine_class class) >> +{ >> + return xe_guc_class_to_capture_class(xe_guc_class_to_capture_class(class)); > > are you sure this is correct ? Oops, that's a bug. Thanks for point out. ... >> + /* Update the state of log buffer err-cap state */ >> + xe_map_wr(guc_to_xe(guc), &guc->log.bo->vmap, >> + log_buf_state_offset + offsetof(struct guc_log_buffer_state, read_ptr), u32, >> + write_offset); >> + /* Clear the flush_to_file from local first, the local was loaded by above >> + * xe_map_memcpy_from. >> + */ >> + log_buf_state_local.flush_to_file = 0; >> + /* Then write out the "updated local" through xe_map_wr() */ >> + xe_map_wr(guc_to_xe(guc), &guc->log.bo->vmap, >> + log_buf_state_offset + offsetof(struct guc_log_buffer_state, flags), u32, >> + log_buf_state_local.flags); >> + __guc_capture_flushlog_complete(guc); >> +} >> + > > public functions require kernel-doc > >> +void xe_guc_capture_process(struct xe_guc *guc) >> +{ >> + if (guc->capture) >> + __guc_capture_process_output(guc); >> +} Will add ... >> trace_xe_exec_queue_reset(q); >> >> /* >> @@ -1715,6 +1728,24 @@ int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) >> return 0; >> } >> > > missing kerne-doc Will add > >> +int xe_guc_error_capture_handler(struct xe_guc *guc, u32 *msg, u32 len) > > maybe this should be defined as xe_guc_capture_msg_handler() and placed > in xe_guc_capture.c as it doesn't look that it needs anything from > xe_guc_submit.c code > >> +{ >> + u32 status; >> + >> + if (unlikely(len != 1)) { > > magic "1" Will changed to a macro define > >> + xe_gt_dbg(guc_to_gt(guc), "Invalid length %u", len); >> + return -EPROTO; >> + } >> + >> + status = msg[0] & XE_GUC_STATE_CAPTURE_EVENT_STATUS_MASK; >> + if (status == XE_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE) >> + xe_gt_warn(guc_to_gt(guc), "G2H-Error capture no space"); > > btw, is there anything to capture if GuC reported 'NOSPACE' ? We have the gt_warn to warn it in dmesg, let user know what happens. The next guc_capture_process will try to process whatever received. ... ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ CI.Patch_applied: success for drm/xe/guc: Add GuC based register capture for error capture (rev9) 2024-06-07 0:07 [PATCH v9 0/4] drm/xe/guc: Add GuC based register capture for error capture Zhanjun Dong ` (3 preceding siblings ...) 2024-06-07 0:07 ` [PATCH v9 4/4] drm/xe/guc: Extract GuC capture lists to register snapshot Zhanjun Dong @ 2024-06-07 0:12 ` Patchwork 2024-06-07 0:12 ` ✗ CI.checkpatch: warning " Patchwork ` (6 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-06-07 0:12 UTC (permalink / raw) To: Zhanjun Dong; +Cc: intel-xe == Series Details == Series: drm/xe/guc: Add GuC based register capture for error capture (rev9) URL : https://patchwork.freedesktop.org/series/128077/ State : success == Summary == === Applying kernel patches on branch 'drm-tip' with base: === Base commit: ed13bc296bbe drm-tip: 2024y-06m-06d-22h-42m-34s UTC integration manifest === git am output follows === Applying: drm/xe/guc: Prepare GuC register list and update ADS size for error capture Applying: drm/xe/guc: Add XE_LP steered register lists Applying: drm/xe/guc: Add capture size check in GuC log buffer Applying: drm/xe/guc: Extract GuC capture lists to register snapshot ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ CI.checkpatch: warning for drm/xe/guc: Add GuC based register capture for error capture (rev9) 2024-06-07 0:07 [PATCH v9 0/4] drm/xe/guc: Add GuC based register capture for error capture Zhanjun Dong ` (4 preceding siblings ...) 2024-06-07 0:12 ` ✓ CI.Patch_applied: success for drm/xe/guc: Add GuC based register capture for error capture (rev9) Patchwork @ 2024-06-07 0:12 ` Patchwork 2024-06-07 0:13 ` ✓ CI.KUnit: success " Patchwork ` (5 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-06-07 0:12 UTC (permalink / raw) To: Zhanjun Dong; +Cc: intel-xe == Series Details == Series: drm/xe/guc: Add GuC based register capture for error capture (rev9) URL : https://patchwork.freedesktop.org/series/128077/ State : warning == Summary == + KERNEL=/kernel + git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt Cloning into 'mt'... warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/ + git -C mt rev-list -n1 origin/master 51ce9f6cd981d42d7467409d7dbc559a450abc1e + cd /kernel + git config --global --add safe.directory /kernel + git log -n1 commit 17808d3b49ecb1f0a11f6eb09543edd0c97a20bc Author: Zhanjun Dong <zhanjun.dong@intel.com> Date: Thu Jun 6 17:07:19 2024 -0700 drm/xe/guc: Extract GuC capture lists to register snapshot Upon the G2H Notify-Err-Capture event, parse through the GuC Log Buffer (error-capture-subregion) and generate one or more capture-nodes. A single node represents a single "engine- instance-capture-dump" and contains at least 3 register lists: global, engine-class and engine-instance. An internal link list is maintained to store one or more nodes. Because the link-list node generation happen before the call to devcoredump, duplicate global and engine-class register lists for each engine-instance register dump if we find dependent-engine resets in a engine-capture-group. When xe_devcoredump calls into snapshot_from_capture_engine, we detach the matching node (guc-id, LRCA, etc) from the link list above and attach it to snapshot_regs structure when have matching LRCA/guc-id/engine-instance. To avoid dynamically allocate the output nodes during gt reset, pre-allocate a fixed number of empty nodes up front (at the time of ADS registration) that we can consume from or return to an internal cached list of nodes. Add guc capture data structure definition. Add xe_hw_engine_snapshot_from_capture to take snapshot from capture node list. Move snapshot register struct out of engine snapshot struct. Add offset in snapshot register to register definition list at xe_guc_capture.c. Snapshot could be split into global, engine class, engine instance and steering register zone, few macros defined to separate zones. Support combines 2 32bit registers as a 64bit register in snapshot, perform endian convert if needed. Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> + /mt/dim checkpatch ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462 drm-intel 6b651e28699e drm/xe/guc: Prepare GuC register list and update ADS size for error capture Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in <module> from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in <module> from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in <module> from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:295: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #295: FILE: drivers/gpu/drm/xe/xe_guc_ads.c:690: + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, -:387: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #387: new file mode 100644 -:432: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #432: FILE: drivers/gpu/drm/xe/xe_guc_capture.c:41: +#define COMMON_BASE_ENGINE_INSTANCE \ + { RING_ESR(0), 0, 0}, \ + { RING_EMR(0), 0, 0}, \ + { RING_EIR(0), 0, 0}, \ + { RING_EXECLIST_STATUS_HI(0), 0, 0}, \ + { RING_EXECLIST_STATUS_LO(0), 0, 0}, \ + { RING_DMA_FADD(0), 0, 0}, \ + { RING_DMA_FADD_UDW(0), 0, 0}, \ + { RING_IPEHR(0), 0, 0}, \ + { RING_BBADDR(0), 0, 0}, \ + { RING_BBADDR_UDW(0), 0, 0}, \ + { RING_ACTHD(0), 0, 0}, \ + { RING_ACTHD_UDW(0), 0, 0}, \ + { RING_START(0), 0, 0}, \ + { RING_HEAD(0), 0, 0}, \ + { RING_TAIL(0), 0, 0}, \ + { RING_CTL(0), 0, 0}, \ + { RING_MI_MODE(0), 0, 0}, \ + { RING_HWS_PGA(0), 0, 0}, \ + { RING_MODE(0), 0, 0} -:492: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'regslist' - possible side-effects? #492: FILE: drivers/gpu/drm/xe/xe_guc_capture.c:101: +#define MAKE_REGLIST(regslist, regsowner, regstype, class) \ + { \ + regslist, \ + ARRAY_SIZE(regslist), \ + TO_GCAP_DEF_OWNER(regsowner), \ + TO_GCAP_DEF_TYPE(regstype), \ + class, \ + } -:538: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ar' - possible side-effects? #538: FILE: drivers/gpu/drm/xe/xe_guc_capture.c:147: +#define get_item_with_default(ar, index) (ar[(index) >= ARRAY_SIZE(ar) ? ARRAY_SIZE(ar) - 1 : \ + (index)]) -:538: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #538: FILE: drivers/gpu/drm/xe/xe_guc_capture.c:147: +#define get_item_with_default(ar, index) (ar[(index) >= ARRAY_SIZE(ar) ? ARRAY_SIZE(ar) - 1 : \ + (index)]) total: 1 errors, 2 warnings, 3 checks, 915 lines checked aeca579ef624 drm/xe/guc: Add XE_LP steered register lists 98b12441983d drm/xe/guc: Add capture size check in GuC log buffer 17808d3b49ec drm/xe/guc: Extract GuC capture lists to register snapshot -:256: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #256: FILE: drivers/gpu/drm/xe/xe_guc_capture.c:109: +#define XELP_DIRECT_READ_VEC_CLASS \ + { SFC_DONE(0), 0, 0, "SFC_DONE[0]", \ + offsetof(struct snapshot_regs, sfc_done_0) }, \ + { SFC_DONE(1), 0, 0, "SFC_DONE[1]", \ + offsetof(struct snapshot_regs, sfc_done_1) }, \ + { SFC_DONE(2), 0, 0, "SFC_DONE[2]", \ + offsetof(struct snapshot_regs, sfc_done_2) }, \ + { SFC_DONE(3), 0, 0, "SFC_DONE[3]", \ + offsetof(struct snapshot_regs, sfc_done_3) } total: 1 errors, 0 warnings, 0 checks, 1761 lines checked ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ CI.KUnit: success for drm/xe/guc: Add GuC based register capture for error capture (rev9) 2024-06-07 0:07 [PATCH v9 0/4] drm/xe/guc: Add GuC based register capture for error capture Zhanjun Dong ` (5 preceding siblings ...) 2024-06-07 0:12 ` ✗ CI.checkpatch: warning " Patchwork @ 2024-06-07 0:13 ` Patchwork 2024-06-07 0:25 ` ✓ CI.Build: " Patchwork ` (4 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-06-07 0:13 UTC (permalink / raw) To: Zhanjun Dong; +Cc: intel-xe == Series Details == Series: drm/xe/guc: Add GuC based register capture for error capture (rev9) URL : https://patchwork.freedesktop.org/series/128077/ State : success == Summary == + trap cleanup EXIT + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig [00:12:54] Configuring KUnit Kernel ... Generating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [00:12:58] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make ARCH=um O=.kunit --jobs=48 ../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes] 156 | u64 ioread64_lo_hi(const void __iomem *addr) | ^~~~~~~~~~~~~~ ../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes] 163 | u64 ioread64_hi_lo(const void __iomem *addr) | ^~~~~~~~~~~~~~ ../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes] 170 | u64 ioread64be_lo_hi(const void __iomem *addr) | ^~~~~~~~~~~~~~~~ ../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes] 178 | u64 ioread64be_hi_lo(const void __iomem *addr) | ^~~~~~~~~~~~~~~~ ../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes] 264 | void iowrite64_lo_hi(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~ ../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes] 272 | void iowrite64_hi_lo(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~ ../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes] 280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~~~ ../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes] 288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~~~ [00:13:24] Starting KUnit Kernel (1/1)... [00:13:24] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [00:13:24] =================== guc_dbm (7 subtests) =================== [00:13:24] [PASSED] test_empty [00:13:24] [PASSED] test_default [00:13:24] ======================== test_size ======================== [00:13:24] [PASSED] 4 [00:13:24] [PASSED] 8 [00:13:24] [PASSED] 32 [00:13:24] [PASSED] 256 [00:13:24] ==================== [PASSED] test_size ==================== [00:13:24] ======================= test_reuse ======================== [00:13:24] [PASSED] 4 [00:13:24] [PASSED] 8 [00:13:24] [PASSED] 32 [00:13:24] [PASSED] 256 [00:13:24] =================== [PASSED] test_reuse ==================== [00:13:24] =================== test_range_overlap ==================== [00:13:24] [PASSED] 4 [00:13:24] [PASSED] 8 [00:13:24] [PASSED] 32 [00:13:24] [PASSED] 256 [00:13:24] =============== [PASSED] test_range_overlap ================ [00:13:24] =================== test_range_compact ==================== [00:13:24] [PASSED] 4 [00:13:24] [PASSED] 8 [00:13:24] [PASSED] 32 [00:13:24] [PASSED] 256 [00:13:24] =============== [PASSED] test_range_compact ================ [00:13:24] ==================== test_range_spare ===================== [00:13:24] [PASSED] 4 [00:13:24] [PASSED] 8 [00:13:24] [PASSED] 32 [00:13:24] [PASSED] 256 [00:13:24] ================ [PASSED] test_range_spare ================= [00:13:24] ===================== [PASSED] guc_dbm ===================== [00:13:24] =================== guc_idm (6 subtests) =================== [00:13:24] [PASSED] bad_init [00:13:24] [PASSED] no_init [00:13:24] [PASSED] init_fini [00:13:24] [PASSED] check_used [00:13:24] [PASSED] check_quota [00:13:24] [PASSED] check_all [00:13:24] ===================== [PASSED] guc_idm ===================== [00:13:24] ================== no_relay (3 subtests) =================== [00:13:24] [PASSED] xe_drops_guc2pf_if_not_ready [00:13:24] [PASSED] xe_drops_guc2vf_if_not_ready [00:13:24] [PASSED] xe_rejects_send_if_not_ready [00:13:24] ==================== [PASSED] no_relay ===================== [00:13:24] ================== pf_relay (14 subtests) ================== [00:13:24] [PASSED] pf_rejects_guc2pf_too_short [00:13:24] [PASSED] pf_rejects_guc2pf_too_long [00:13:24] [PASSED] pf_rejects_guc2pf_no_payload [00:13:24] [PASSED] pf_fails_no_payload [00:13:24] [PASSED] pf_fails_bad_origin [00:13:24] [PASSED] pf_fails_bad_type [00:13:24] [PASSED] pf_txn_reports_error [00:13:24] [PASSED] pf_txn_sends_pf2guc [00:13:24] [PASSED] pf_sends_pf2guc [00:13:24] [SKIPPED] pf_loopback_nop [00:13:24] [SKIPPED] pf_loopback_echo [00:13:24] [SKIPPED] pf_loopback_fail [00:13:24] [SKIPPED] pf_loopback_busy [00:13:24] [SKIPPED] pf_loopback_retry [00:13:24] ==================== [PASSED] pf_relay ===================== [00:13:24] ================== vf_relay (3 subtests) =================== [00:13:24] [PASSED] vf_rejects_guc2vf_too_short [00:13:24] [PASSED] vf_rejects_guc2vf_too_long [00:13:24] [PASSED] vf_rejects_guc2vf_no_payload [00:13:24] ==================== [PASSED] vf_relay ===================== [00:13:24] ================= pf_service (11 subtests) ================= [00:13:24] [PASSED] pf_negotiate_any [00:13:24] [PASSED] pf_negotiate_base_match [00:13:24] [PASSED] pf_negotiate_base_newer [00:13:24] [PASSED] pf_negotiate_base_next [00:13:24] [SKIPPED] pf_negotiate_base_older [00:13:24] [PASSED] pf_negotiate_base_prev [00:13:24] [PASSED] pf_negotiate_latest_match [00:13:24] [PASSED] pf_negotiate_latest_newer [00:13:24] [PASSED] pf_negotiate_latest_next [00:13:24] [SKIPPED] pf_negotiate_latest_older [00:13:24] [SKIPPED] pf_negotiate_latest_prev [00:13:24] =================== [PASSED] pf_service ==================== [00:13:24] ===================== lmtt (1 subtest) ===================== [00:13:24] ======================== test_ops ========================= [00:13:24] [PASSED] 2-level [00:13:24] [PASSED] multi-level [00:13:24] ==================== [PASSED] test_ops ===================== [00:13:24] ====================== [PASSED] lmtt ======================= [00:13:24] ==================== xe_bo (2 subtests) ==================== [00:13:24] [SKIPPED] xe_ccs_migrate_kunit [00:13:24] [SKIPPED] xe_bo_evict_kunit [00:13:24] ===================== [SKIPPED] xe_bo ====================== [00:13:24] ================== xe_dma_buf (1 subtest) ================== [00:13:24] [SKIPPED] xe_dma_buf_kunit [00:13:24] =================== [SKIPPED] xe_dma_buf =================== [00:13:24] ================== xe_migrate (1 subtest) ================== [00:13:24] [SKIPPED] xe_migrate_sanity_kunit [00:13:24] =================== [SKIPPED] xe_migrate =================== [00:13:24] =================== xe_mocs (2 subtests) =================== [00:13:24] [SKIPPED] xe_live_mocs_kernel_kunit [00:13:24] [SKIPPED] xe_live_mocs_reset_kunit [00:13:24] ==================== [SKIPPED] xe_mocs ===================== [00:13:24] ==================== args (11 subtests) ==================== [00:13:24] [PASSED] count_args_test [00:13:24] [PASSED] call_args_example [00:13:24] [PASSED] call_args_test [00:13:24] [PASSED] drop_first_arg_example [00:13:24] [PASSED] drop_first_arg_test [00:13:24] [PASSED] first_arg_example [00:13:24] [PASSED] first_arg_test [00:13:24] [PASSED] last_arg_example [00:13:24] [PASSED] last_arg_test [00:13:24] [PASSED] pick_arg_example [00:13:24] [PASSED] sep_comma_example [00:13:24] ====================== [PASSED] args ======================= [00:13:24] =================== xe_pci (2 subtests) ==================== [00:13:24] [PASSED] xe_gmdid_graphics_ip [00:13:24] [PASSED] xe_gmdid_media_ip [00:13:24] ===================== [PASSED] xe_pci ====================== [00:13:24] ==================== xe_rtp (1 subtest) ==================== [00:13:24] ================== xe_rtp_process_tests =================== [00:13:24] [PASSED] coalesce-same-reg [00:13:24] [PASSED] no-match-no-add [00:13:24] [PASSED] no-match-no-add-multiple-rules [00:13:24] [PASSED] two-regs-two-entries [00:13:24] [PASSED] clr-one-set-other [00:13:24] [PASSED] set-field [00:13:24] [PASSED] conflict-duplicate [00:13:24] [PASSED] conflict-not-disjoint [00:13:24] [PASSED] conflict-reg-type [00:13:24] ============== [PASSED] xe_rtp_process_tests =============== stty: 'standard input': Inappropriate ioctl for device [00:13:24] ===================== [PASSED] xe_rtp ====================== [00:13:24] ==================== xe_wa (1 subtest) ===================== [00:13:24] ======================== xe_wa_gt ========================= [00:13:24] [PASSED] TIGERLAKE (B0) [00:13:24] [PASSED] DG1 (A0) [00:13:24] [PASSED] DG1 (B0) [00:13:24] [PASSED] ALDERLAKE_S (A0) [00:13:24] [PASSED] ALDERLAKE_S (B0) [00:13:24] [PASSED] ALDERLAKE_S (C0) [00:13:24] [PASSED] ALDERLAKE_S (D0) [00:13:24] [PASSED] ALDERLAKE_P (A0) [00:13:24] [PASSED] ALDERLAKE_P (B0) [00:13:24] [PASSED] ALDERLAKE_P (C0) [00:13:24] [PASSED] ALDERLAKE_S_RPLS (D0) [00:13:24] [PASSED] ALDERLAKE_P_RPLU (E0) [00:13:24] [PASSED] DG2_G10 (C0) [00:13:24] [PASSED] DG2_G11 (B1) [00:13:24] [PASSED] DG2_G12 (A1) [00:13:24] [PASSED] METEORLAKE (g:A0, m:A0) [00:13:24] [PASSED] METEORLAKE (g:A0, m:A0) [00:13:24] [PASSED] METEORLAKE (g:A0, m:A0) [00:13:24] [PASSED] LUNARLAKE (g:A0, m:A0) [00:13:24] [PASSED] LUNARLAKE (g:B0, m:A0) [00:13:24] ==================== [PASSED] xe_wa_gt ===================== [00:13:24] ====================== [PASSED] xe_wa ====================== [00:13:24] ============================================================ [00:13:24] Testing complete. Ran 109 tests: passed: 95, skipped: 14 [00:13:24] Elapsed time: 29.894s total, 4.243s configuring, 25.380s building, 0.234s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig [00:13:24] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [00:13:26] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make ARCH=um O=.kunit --jobs=48 ../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes] 156 | u64 ioread64_lo_hi(const void __iomem *addr) | ^~~~~~~~~~~~~~ ../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes] 163 | u64 ioread64_hi_lo(const void __iomem *addr) | ^~~~~~~~~~~~~~ ../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes] 170 | u64 ioread64be_lo_hi(const void __iomem *addr) | ^~~~~~~~~~~~~~~~ ../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes] 178 | u64 ioread64be_hi_lo(const void __iomem *addr) | ^~~~~~~~~~~~~~~~ ../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes] 264 | void iowrite64_lo_hi(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~ ../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes] 272 | void iowrite64_hi_lo(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~ ../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes] 280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~~~ ../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes] 288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~~~ [00:13:47] Starting KUnit Kernel (1/1)... [00:13:47] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [00:13:47] ============ drm_test_pick_cmdline (2 subtests) ============ [00:13:47] [PASSED] drm_test_pick_cmdline_res_1920_1080_60 [00:13:47] =============== drm_test_pick_cmdline_named =============== [00:13:47] [PASSED] NTSC [00:13:47] [PASSED] NTSC-J [00:13:47] [PASSED] PAL [00:13:47] [PASSED] PAL-M [00:13:47] =========== [PASSED] drm_test_pick_cmdline_named =========== [00:13:47] ============== [PASSED] drm_test_pick_cmdline ============== [00:13:47] ================== drm_buddy (7 subtests) ================== [00:13:47] [PASSED] drm_test_buddy_alloc_limit [00:13:47] [PASSED] drm_test_buddy_alloc_optimistic [00:13:47] [PASSED] drm_test_buddy_alloc_pessimistic [00:13:47] [PASSED] drm_test_buddy_alloc_pathological [00:13:47] [PASSED] drm_test_buddy_alloc_contiguous [00:13:47] [PASSED] drm_test_buddy_alloc_clear [00:13:47] [PASSED] drm_test_buddy_alloc_range_bias [00:13:47] ==================== [PASSED] drm_buddy ==================== [00:13:47] ============= drm_cmdline_parser (40 subtests) ============= [00:13:47] [PASSED] drm_test_cmdline_force_d_only [00:13:47] [PASSED] drm_test_cmdline_force_D_only_dvi [00:13:47] [PASSED] drm_test_cmdline_force_D_only_hdmi [00:13:47] [PASSED] drm_test_cmdline_force_D_only_not_digital [00:13:47] [PASSED] drm_test_cmdline_force_e_only [00:13:47] [PASSED] drm_test_cmdline_res [00:13:47] [PASSED] drm_test_cmdline_res_vesa [00:13:47] [PASSED] drm_test_cmdline_res_vesa_rblank [00:13:47] [PASSED] drm_test_cmdline_res_rblank [00:13:47] [PASSED] drm_test_cmdline_res_bpp [00:13:47] [PASSED] drm_test_cmdline_res_refresh [00:13:47] [PASSED] drm_test_cmdline_res_bpp_refresh [00:13:47] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced [00:13:47] [PASSED] drm_test_cmdline_res_bpp_refresh_margins [00:13:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off [00:13:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on [00:13:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog [00:13:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital [00:13:47] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on [00:13:47] [PASSED] drm_test_cmdline_res_margins_force_on [00:13:47] [PASSED] drm_test_cmdline_res_vesa_margins [00:13:47] [PASSED] drm_test_cmdline_name [00:13:47] [PASSED] drm_test_cmdline_name_bpp [00:13:47] [PASSED] drm_test_cmdline_name_option [00:13:47] [PASSED] drm_test_cmdline_name_bpp_option [00:13:47] [PASSED] drm_test_cmdline_rotate_0 [00:13:47] [PASSED] drm_test_cmdline_rotate_90 [00:13:47] [PASSED] drm_test_cmdline_rotate_180 [00:13:47] [PASSED] drm_test_cmdline_rotate_270 [00:13:47] [PASSED] drm_test_cmdline_hmirror [00:13:47] [PASSED] drm_test_cmdline_vmirror [00:13:47] [PASSED] drm_test_cmdline_margin_options [00:13:47] [PASSED] drm_test_cmdline_multiple_options [00:13:47] [PASSED] drm_test_cmdline_bpp_extra_and_option [00:13:47] [PASSED] drm_test_cmdline_extra_and_option [00:13:47] [PASSED] drm_test_cmdline_freestanding_options [00:13:47] [PASSED] drm_test_cmdline_freestanding_force_e_and_options [00:13:47] [PASSED] drm_test_cmdline_panel_orientation [00:13:47] ================ drm_test_cmdline_invalid ================= [00:13:47] [PASSED] margin_only [00:13:47] [PASSED] interlace_only [00:13:47] [PASSED] res_missing_x [00:13:47] [PASSED] res_missing_y [00:13:47] [PASSED] res_bad_y [00:13:47] [PASSED] res_missing_y_bpp [00:13:47] [PASSED] res_bad_bpp [00:13:47] [PASSED] res_bad_refresh [00:13:47] [PASSED] res_bpp_refresh_force_on_off [00:13:47] [PASSED] res_invalid_mode [00:13:47] [PASSED] res_bpp_wrong_place_mode [00:13:47] [PASSED] name_bpp_refresh [00:13:47] [PASSED] name_refresh [00:13:47] [PASSED] name_refresh_wrong_mode [00:13:47] [PASSED] name_refresh_invalid_mode [00:13:47] [PASSED] rotate_multiple [00:13:47] [PASSED] rotate_invalid_val [00:13:47] [PASSED] rotate_truncated [00:13:47] [PASSED] invalid_option [00:13:47] [PASSED] invalid_tv_option [00:13:47] [PASSED] truncated_tv_option [00:13:47] ============ [PASSED] drm_test_cmdline_invalid ============= [00:13:47] =============== drm_test_cmdline_tv_options =============== [00:13:47] [PASSED] NTSC [00:13:47] [PASSED] NTSC_443 [00:13:47] [PASSED] NTSC_J [00:13:47] [PASSED] PAL [00:13:47] [PASSED] PAL_M [00:13:47] [PASSED] PAL_N [00:13:47] [PASSED] SECAM [00:13:47] =========== [PASSED] drm_test_cmdline_tv_options =========== [00:13:47] =============== [PASSED] drm_cmdline_parser ================ [00:13:47] ========== drmm_connector_hdmi_init (19 subtests) ========== [00:13:47] [PASSED] drm_test_connector_hdmi_init_valid [00:13:47] [PASSED] drm_test_connector_hdmi_init_bpc_8 [00:13:47] [PASSED] drm_test_connector_hdmi_init_bpc_10 [00:13:47] [PASSED] drm_test_connector_hdmi_init_bpc_12 [00:13:47] [PASSED] drm_test_connector_hdmi_init_bpc_invalid [00:13:47] [PASSED] drm_test_connector_hdmi_init_bpc_null [00:13:47] [PASSED] drm_test_connector_hdmi_init_formats_empty [00:13:47] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb [00:13:47] [PASSED] drm_test_connector_hdmi_init_null_ddc [00:13:47] [PASSED] drm_test_connector_hdmi_init_null_product [00:13:47] [PASSED] drm_test_connector_hdmi_init_null_vendor [00:13:47] [PASSED] drm_test_connector_hdmi_init_product_length_exact [00:13:47] [PASSED] drm_test_connector_hdmi_init_product_length_too_long [00:13:47] [PASSED] drm_test_connector_hdmi_init_product_valid [00:13:47] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact [00:13:47] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long [00:13:47] [PASSED] drm_test_connector_hdmi_init_vendor_valid [00:13:47] ========= drm_test_connector_hdmi_init_type_valid ========= [00:13:47] [PASSED] HDMI-A [00:13:47] [PASSED] HDMI-B [00:13:47] ===== [PASSED] drm_test_connector_hdmi_init_type_valid ===== [00:13:47] ======== drm_test_connector_hdmi_init_type_invalid ======== [00:13:47] [PASSED] Unknown [00:13:47] [PASSED] VGA [00:13:47] [PASSED] DVI-I [00:13:47] [PASSED] DVI-D [00:13:47] [PASSED] DVI-A [00:13:47] [PASSED] Composite [00:13:47] [PASSED] SVIDEO [00:13:47] [PASSED] LVDS [00:13:47] [PASSED] Component [00:13:47] [PASSED] DIN [00:13:47] [PASSED] DP [00:13:47] [PASSED] TV [00:13:47] [PASSED] eDP [00:13:47] [PASSED] Virtual [00:13:47] [PASSED] DSI [00:13:47] [PASSED] DPI [00:13:47] [PASSED] Writeback [00:13:47] [PASSED] SPI [00:13:47] [PASSED] USB [00:13:47] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ==== [00:13:47] ============ [PASSED] drmm_connector_hdmi_init ============= [00:13:47] ============= drmm_connector_init (3 subtests) ============= [00:13:47] [PASSED] drm_test_drmm_connector_init [00:13:47] [PASSED] drm_test_drmm_connector_init_null_ddc [00:13:47] ========= drm_test_drmm_connector_init_type_valid ========= [00:13:47] [PASSED] Unknown [00:13:47] [PASSED] VGA [00:13:47] [PASSED] DVI-I [00:13:47] [PASSED] DVI-D [00:13:47] [PASSED] DVI-A [00:13:47] [PASSED] Composite [00:13:47] [PASSED] SVIDEO [00:13:47] [PASSED] LVDS [00:13:47] [PASSED] Component [00:13:47] [PASSED] DIN [00:13:47] [PASSED] DP [00:13:47] [PASSED] HDMI-A [00:13:47] [PASSED] HDMI-B [00:13:47] [PASSED] TV [00:13:47] [PASSED] eDP [00:13:47] [PASSED] Virtual [00:13:47] [PASSED] DSI [00:13:47] [PASSED] DPI [00:13:47] [PASSED] Writeback [00:13:47] [PASSED] SPI [00:13:47] [PASSED] USB [00:13:47] ===== [PASSED] drm_test_drmm_connector_init_type_valid ===== [00:13:47] =============== [PASSED] drmm_connector_init =============== [00:13:47] = drm_connector_attach_broadcast_rgb_property (2 subtests) = [00:13:47] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property [00:13:47] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector [00:13:47] === [PASSED] drm_connector_attach_broadcast_rgb_property === [00:13:47] ========== drm_get_tv_mode_from_name (2 subtests) ========== [00:13:47] ========== drm_test_get_tv_mode_from_name_valid =========== [00:13:47] [PASSED] NTSC [00:13:47] [PASSED] NTSC-443 [00:13:47] [PASSED] NTSC-J [00:13:47] [PASSED] PAL [00:13:47] [PASSED] PAL-M [00:13:47] [PASSED] PAL-N [00:13:47] [PASSED] SECAM [00:13:47] ====== [PASSED] drm_test_get_tv_mode_from_name_valid ======= [00:13:47] [PASSED] drm_test_get_tv_mode_from_name_truncated [00:13:47] ============ [PASSED] drm_get_tv_mode_from_name ============ [00:13:47] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) = [00:13:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb [00:13:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc [00:13:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1 [00:13:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc [00:13:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1 [00:13:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double [00:13:47] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid = [00:13:47] [PASSED] VIC 96 [00:13:47] [PASSED] VIC 97 [00:13:47] [PASSED] VIC 101 [00:13:47] [PASSED] VIC 102 [00:13:47] [PASSED] VIC 106 [00:13:47] [PASSED] VIC 107 [00:13:47] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid === [00:13:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc [00:13:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc [00:13:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc [00:13:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc [00:13:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc [00:13:47] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ==== [00:13:47] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) == [00:13:47] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ==== [00:13:47] [PASSED] Automatic [00:13:47] [PASSED] Full [00:13:47] [PASSED] Limited 16:235 [00:13:47] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name === [00:13:47] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid [00:13:47] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ==== [00:13:47] == drm_hdmi_connector_get_output_format_name (2 subtests) == [00:13:47] === drm_test_drm_hdmi_connector_get_output_format_name ==== [00:13:47] [PASSED] RGB [00:13:47] [PASSED] YUV 4:2:0 [00:13:47] [PASSED] YUV 4:2:2 [00:13:47] [PASSED] YUV 4:4:4 [00:13:47] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name === [00:13:47] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid [00:13:47] ==== [PASSED] drm_hdmi_connector_get_output_format_name ==== [00:13:47] ============= drm_damage_helper (21 subtests) ============== [00:13:47] [PASSED] drm_test_damage_iter_no_damage [00:13:47] [PASSED] drm_test_damage_iter_no_damage_fractional_src [00:13:47] [PASSED] drm_test_damage_iter_no_damage_src_moved [00:13:47] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved [00:13:47] [PASSED] drm_test_damage_iter_no_damage_not_visible [00:13:47] [PASSED] drm_test_damage_iter_no_damage_no_crtc [00:13:47] [PASSED] drm_test_damage_iter_no_damage_no_fb [00:13:47] [PASSED] drm_test_damage_iter_simple_damage [00:13:47] [PASSED] drm_test_damage_iter_single_damage [00:13:47] [PASSED] drm_test_damage_iter_single_damage_intersect_src [00:13:47] [PASSED] drm_test_damage_iter_single_damage_outside_src [00:13:47] [PASSED] drm_test_damage_iter_single_damage_fractional_src [00:13:47] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src [00:13:47] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src [00:13:47] [PASSED] drm_test_damage_iter_single_damage_src_moved [00:13:47] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved [00:13:47] [PASSED] drm_test_damage_iter_damage [00:13:47] [PASSED] drm_test_damage_iter_damage_one_intersect [00:13:47] [PASSED] drm_test_damage_iter_damage_one_outside [00:13:47] [PASSED] drm_test_damage_iter_damage_src_moved [00:13:47] [PASSED] drm_test_damage_iter_damage_not_visible [00:13:47] ================ [PASSED] drm_damage_helper ================ [00:13:47] ============== drm_dp_mst_helper (3 subtests) ============== [00:13:47] ============== drm_test_dp_mst_calc_pbn_mode ============== [00:13:47] [PASSED] Clock 154000 BPP 30 DSC disabled [00:13:47] [PASSED] Clock 234000 BPP 30 DSC disabled [00:13:47] [PASSED] Clock 297000 BPP 24 DSC disabled [00:13:47] [PASSED] Clock 332880 BPP 24 DSC enabled [00:13:47] [PASSED] Clock 324540 BPP 24 DSC enabled [00:13:47] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ========== [00:13:47] ============== drm_test_dp_mst_calc_pbn_div =============== [00:13:47] [PASSED] Link rate 2000000 lane count 4 [00:13:47] [PASSED] Link rate 2000000 lane count 2 [00:13:47] [PASSED] Link rate 2000000 lane count 1 [00:13:47] [PASSED] Link rate 1350000 lane count 4 [00:13:47] [PASSED] Link rate 1350000 lane count 2 [00:13:47] [PASSED] Link rate 1350000 lane count 1 [00:13:47] [PASSED] Link rate 1000000 lane count 4 [00:13:47] [PASSED] Link rate 1000000 lane count 2 [00:13:47] [PASSED] Link rate 1000000 lane count 1 [00:13:47] [PASSED] Link rate 810000 lane count 4 [00:13:47] [PASSED] Link rate 810000 lane count 2 [00:13:47] [PASSED] Link rate 810000 lane count 1 [00:13:47] [PASSED] Link rate 540000 lane count 4 [00:13:47] [PASSED] Link rate 540000 lane count 2 [00:13:47] [PASSED] Link rate 540000 lane count 1 [00:13:47] [PASSED] Link rate 270000 lane count 4 [00:13:47] [PASSED] Link rate 270000 lane count 2 [00:13:47] [PASSED] Link rate 270000 lane count 1 [00:13:47] [PASSED] Link rate 162000 lane count 4 [00:13:47] [PASSED] Link rate 162000 lane count 2 [00:13:47] [PASSED] Link rate 162000 lane count 1 [00:13:47] ========== [PASSED] drm_test_dp_mst_calc_pbn_div =========== [00:13:47] ========= drm_test_dp_mst_sideband_msg_req_decode ========= [00:13:47] [PASSED] DP_ENUM_PATH_RESOURCES with port number [00:13:47] [PASSED] DP_POWER_UP_PHY with port number [00:13:47] [PASSED] DP_POWER_DOWN_PHY with port number [00:13:47] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks [00:13:47] [PASSED] DP_ALLOCATE_PAYLOAD with port number [00:13:47] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI [00:13:47] [PASSED] DP_ALLOCATE_PAYLOAD with PBN [00:13:47] [PASSED] DP_QUERY_PAYLOAD with port number [00:13:47] [PASSED] DP_QUERY_PAYLOAD with VCPI [00:13:47] [PASSED] DP_REMOTE_DPCD_READ with port number [00:13:47] [PASSED] DP_REMOTE_DPCD_READ with DPCD address [00:13:47] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes [00:13:47] [PASSED] DP_REMOTE_DPCD_WRITE with port number [00:13:47] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address [00:13:47] [PASSED] DP_REMOTE_DPCD_WRITE with data array [00:13:47] [PASSED] DP_REMOTE_I2C_READ with port number [00:13:47] [PASSED] DP_REMOTE_I2C_READ with I2C device ID [00:13:47] [PASSED] DP_REMOTE_I2C_READ with transactions array [00:13:47] [PASSED] DP_REMOTE_I2C_WRITE with port number [00:13:47] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID [00:13:47] [PASSED] DP_REMOTE_I2C_WRITE with data array [00:13:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID [00:13:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID [00:13:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event [00:13:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event [00:13:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior [00:13:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior [00:13:47] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode ===== [00:13:47] ================ [PASSED] drm_dp_mst_helper ================ [00:13:47] ================== drm_exec (7 subtests) =================== [00:13:47] [PASSED] sanitycheck [00:13:47] [PASSED] test_lock [00:13:47] [PASSED] test_lock_unlock [00:13:47] [PASSED] test_duplicates [00:13:47] [PASSED] test_prepare [00:13:47] [PASSED] test_prepare_array [00:13:47] [PASSED] test_multiple_loops [00:13:47] ==================== [PASSED] drm_exec ===================== [00:13:47] =========== drm_format_helper_test (17 subtests) =========== [00:13:47] ============== drm_test_fb_xrgb8888_to_gray8 ============== [00:13:47] [PASSED] single_pixel_source_buffer [00:13:47] [PASSED] single_pixel_clip_rectangle [00:13:47] [PASSED] well_known_colors [00:13:47] [PASSED] destination_pitch [00:13:47] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ========== [00:13:47] ============= drm_test_fb_xrgb8888_to_rgb332 ============== [00:13:47] [PASSED] single_pixel_source_buffer [00:13:47] [PASSED] single_pixel_clip_rectangle [00:13:47] [PASSED] well_known_colors [00:13:47] [PASSED] destination_pitch [00:13:47] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ========== [00:13:47] ============= drm_test_fb_xrgb8888_to_rgb565 ============== [00:13:47] [PASSED] single_pixel_source_buffer [00:13:47] [PASSED] single_pixel_clip_rectangle [00:13:47] [PASSED] well_known_colors [00:13:47] [PASSED] destination_pitch [00:13:47] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ========== [00:13:47] ============ drm_test_fb_xrgb8888_to_xrgb1555 ============= [00:13:47] [PASSED] single_pixel_source_buffer [00:13:47] [PASSED] single_pixel_clip_rectangle [00:13:47] [PASSED] well_known_colors [00:13:47] [PASSED] destination_pitch [00:13:47] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 ========= [00:13:47] ============ drm_test_fb_xrgb8888_to_argb1555 ============= [00:13:47] [PASSED] single_pixel_source_buffer [00:13:47] [PASSED] single_pixel_clip_rectangle [00:13:47] [PASSED] well_known_colors [00:13:47] [PASSED] destination_pitch [00:13:47] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 ========= [00:13:47] ============ drm_test_fb_xrgb8888_to_rgba5551 ============= [00:13:47] [PASSED] single_pixel_source_buffer [00:13:47] [PASSED] single_pixel_clip_rectangle [00:13:47] [PASSED] well_known_colors [00:13:47] [PASSED] destination_pitch [00:13:47] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 ========= [00:13:47] ============= drm_test_fb_xrgb8888_to_rgb888 ============== [00:13:47] [PASSED] single_pixel_source_buffer [00:13:47] [PASSED] single_pixel_clip_rectangle [00:13:47] [PASSED] well_known_colors [00:13:47] [PASSED] destination_pitch [00:13:47] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ========== [00:13:47] ============ drm_test_fb_xrgb8888_to_argb8888 ============= [00:13:47] [PASSED] single_pixel_source_buffer [00:13:47] [PASSED] single_pixel_clip_rectangle [00:13:47] [PASSED] well_known_colors [00:13:47] [PASSED] destination_pitch [00:13:47] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 ========= [00:13:47] =========== drm_test_fb_xrgb8888_to_xrgb2101010 =========== [00:13:47] [PASSED] single_pixel_source_buffer [00:13:47] [PASSED] single_pixel_clip_rectangle [00:13:47] [PASSED] well_known_colors [00:13:47] [PASSED] destination_pitch [00:13:47] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 ======= [00:13:47] =========== drm_test_fb_xrgb8888_to_argb2101010 =========== [00:13:47] [PASSED] single_pixel_source_buffer [00:13:47] [PASSED] single_pixel_clip_rectangle [00:13:47] [PASSED] well_known_colors [00:13:47] [PASSED] destination_pitch [00:13:47] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 ======= [00:13:47] ============== drm_test_fb_xrgb8888_to_mono =============== [00:13:47] [PASSED] single_pixel_source_buffer [00:13:47] [PASSED] single_pixel_clip_rectangle [00:13:47] [PASSED] well_known_colors [00:13:47] [PASSED] destination_pitch [00:13:47] ========== [PASSED] drm_test_fb_xrgb8888_to_mono =========== [00:13:47] ==================== drm_test_fb_swab ===================== [00:13:47] [PASSED] single_pixel_source_buffer [00:13:47] [PASSED] single_pixel_clip_rectangle [00:13:47] [PASSED] well_known_colors [00:13:47] [PASSED] destination_pitch [00:13:47] ================ [PASSED] drm_test_fb_swab ================= [00:13:47] ============ drm_test_fb_xrgb8888_to_xbgr8888 ============= [00:13:47] [PASSED] single_pixel_source_buffer [00:13:47] [PASSED] single_pixel_clip_rectangle [00:13:47] [PASSED] well_known_colors [00:13:47] [PASSED] destination_pitch [00:13:47] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 ========= [00:13:47] ============ drm_test_fb_xrgb8888_to_abgr8888 ============= [00:13:47] [PASSED] single_pixel_source_buffer [00:13:47] [PASSED] single_pixel_clip_rectangle [00:13:47] [PASSED] well_known_colors [00:13:47] [PASSED] destination_pitch [00:13:47] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 ========= [00:13:47] ================= drm_test_fb_clip_offset ================= [00:13:47] [PASSED] pass through [00:13:47] [PASSED] horizontal offset [00:13:47] [PASSED] vertical offset [00:13:47] [PASSED] horizontal and vertical offset [00:13:47] [PASSED] horizontal offset (custom pitch) [00:13:47] [PASSED] vertical offset (custom pitch) [00:13:47] [PASSED] horizontal and vertical offset (custom pitch) [00:13:47] ============= [PASSED] drm_test_fb_clip_offset ============= [00:13:47] ============== drm_test_fb_build_fourcc_list ============== [00:13:47] [PASSED] no native formats [00:13:47] [PASSED] XRGB8888 as native format [00:13:47] [PASSED] remove duplicates [00:13:47] [PASSED] convert alpha formats [00:13:47] [PASSED] random formats [00:13:47] ========== [PASSED] drm_test_fb_build_fourcc_list ========== [00:13:47] =================== drm_test_fb_memcpy ==================== [00:13:47] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258) [00:13:47] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258) [00:13:47] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559) [00:13:47] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258) [00:13:47] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258) [00:13:47] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559) [00:13:47] [PASSED] well_known_colors: XB24 little-endian (0x34324258) [00:13:47] [PASSED] well_known_colors: XRA8 little-endian (0x38415258) [00:13:47] [PASSED] well_known_colors: YU24 little-endian (0x34325559) [00:13:47] [PASSED] destination_pitch: XB24 little-endian (0x34324258) [00:13:47] [PASSED] destination_pitch: XRA8 little-endian (0x38415258) [00:13:47] [PASSED] destination_pitch: YU24 little-endian (0x34325559) [00:13:47] =============== [PASSED] drm_test_fb_memcpy ================ [00:13:47] ============= [PASSED] drm_format_helper_test ============== [00:13:47] ================= drm_format (18 subtests) ================= [00:13:47] [PASSED] drm_test_format_block_width_invalid [00:13:47] [PASSED] drm_test_format_block_width_one_plane [00:13:47] [PASSED] drm_test_format_block_width_two_plane [00:13:47] [PASSED] drm_test_format_block_width_three_plane [00:13:47] [PASSED] drm_test_format_block_width_tiled [00:13:47] [PASSED] drm_test_format_block_height_invalid [00:13:47] [PASSED] drm_test_format_block_height_one_plane [00:13:47] [PASSED] drm_test_format_block_height_two_plane [00:13:47] [PASSED] drm_test_format_block_height_three_plane [00:13:47] [PASSED] drm_test_format_block_height_tiled [00:13:47] [PASSED] drm_test_format_min_pitch_invalid [00:13:47] [PASSED] drm_test_format_min_pitch_one_plane_8bpp [00:13:47] [PASSED] drm_test_format_min_pitch_one_plane_16bpp [00:13:47] [PASSED] drm_test_format_min_pitch_one_plane_24bpp [00:13:47] [PASSED] drm_test_format_min_pitch_one_plane_32bpp [00:13:47] [PASSED] drm_test_format_min_pitch_two_plane [00:13:47] [PASSED] drm_test_format_min_pitch_three_plane_8bpp [00:13:47] [PASSED] drm_test_format_min_pitch_tiled [00:13:47] =================== [PASSED] drm_format ==================== [00:13:47] =============== drm_framebuffer (1 subtest) ================ [00:13:47] =============== drm_test_framebuffer_create =============== [00:13:47] [PASSED] ABGR8888 normal sizes [00:13:47] [PASSED] ABGR8888 max sizes [00:13:47] [PASSED] ABGR8888 pitch greater than min required [00:13:47] [PASSED] ABGR8888 pitch less than min required [00:13:47] [PASSED] ABGR8888 Invalid width [00:13:47] [PASSED] ABGR8888 Invalid buffer handle [00:13:47] [PASSED] No pixel format [00:13:47] [PASSED] ABGR8888 Width 0 [00:13:47] [PASSED] ABGR8888 Height 0 [00:13:47] [PASSED] ABGR8888 Out of bound height * pitch combination [00:13:47] [PASSED] ABGR8888 Large buffer offset [00:13:47] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers [00:13:47] [PASSED] ABGR8888 Valid buffer modifier [00:13:47] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE) [00:13:47] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS [00:13:47] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS [00:13:47] [PASSED] NV12 Normal sizes [00:13:47] [PASSED] NV12 Max sizes [00:13:47] [PASSED] NV12 Invalid pitch [00:13:47] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag [00:13:47] [PASSED] NV12 different modifier per-plane [00:13:47] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE [00:13:47] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS [00:13:47] [PASSED] NV12 Modifier for inexistent plane [00:13:47] [PASSED] NV12 Handle for inexistent plane [00:13:47] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS [00:13:47] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier [00:13:47] [PASSED] YVU420 Normal sizes [00:13:47] [PASSED] YVU420 Max sizes [00:13:47] [PASSED] YVU420 Invalid pitch [00:13:47] [PASSED] YVU420 Different pitches [00:13:47] [PASSED] YVU420 Different buffer offsets/pitches [00:13:47] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS [00:13:47] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS [00:13:47] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS [00:13:47] [PASSED] YVU420 Valid modifier [00:13:47] [PASSED] YVU420 Different modifiers per plane [00:13:47] [PASSED] YVU420 Modifier for inexistent plane [00:13:47] [PASSED] X0L2 Normal sizes [00:13:47] [PASSED] X0L2 Max sizes [00:13:47] [PASSED] X0L2 Invalid pitch [00:13:47] [PASSED] X0L2 Pitch greater than minimum required [00:13:47] [PASSED] X0L2 Handle for inexistent plane [00:13:47] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set [00:13:47] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set [00:13:47] [PASSED] X0L2 Valid modifier [00:13:47] [PASSED] X0L2 Modifier for inexistent plane [00:13:47] =========== [PASSED] drm_test_framebuffer_create =========== [00:13:47] ================= [PASSED] drm_framebuffer ================= [00:13:47] ================ drm_gem_shmem (8 subtests) ================ [00:13:47] [PASSED] drm_gem_shmem_test_obj_create [00:13:47] [PASSED] drm_gem_shmem_test_obj_create_private [00:13:47] [PASSED] drm_gem_shmem_test_pin_pages [00:13:47] [PASSED] drm_gem_shmem_test_vmap [00:13:47] [PASSED] drm_gem_shmem_test_get_pages_sgt [00:13:47] [PASSED] drm_gem_shmem_test_get_sg_table [00:13:47] [PASSED] drm_gem_shmem_test_madvise [00:13:47] [PASSED] drm_gem_shmem_test_purge [00:13:47] ================== [PASSED] drm_gem_shmem ================== [00:13:47] === drm_atomic_helper_connector_hdmi_check (22 subtests) === [00:13:47] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode [00:13:47] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1 [00:13:47] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode [00:13:47] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1 [00:13:47] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode [00:13:47] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1 [00:13:47] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed [00:13:47] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed [00:13:47] [PASSED] drm_test_check_hdmi_funcs_reject_rate [00:13:47] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback [00:13:47] [PASSED] drm_test_check_max_tmds_rate_format_fallback [00:13:47] [PASSED] drm_test_check_output_bpc_crtc_mode_changed [00:13:47] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed [00:13:47] [PASSED] drm_test_check_output_bpc_dvi [00:13:47] [PASSED] drm_test_check_output_bpc_format_vic_1 [00:13:47] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only [00:13:47] [PASSED] drm_test_check_output_bpc_format_display_rgb_only [00:13:47] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only [00:13:47] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only [00:13:47] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc [00:13:47] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc [00:13:47] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc [00:13:47] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ====== [00:13:47] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ==== [00:13:47] [PASSED] drm_test_check_broadcast_rgb_value [00:13:47] [PASSED] drm_test_check_bpc_8_value [00:13:47] [PASSED] drm_test_check_bpc_10_value [00:13:47] [PASSED] drm_test_check_bpc_12_value [00:13:47] [PASSED] drm_test_check_format_value [00:13:47] [PASSED] drm_test_check_tmds_char_value [00:13:47] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ====== [00:13:47] ================= drm_managed (2 subtests) ================= [00:13:47] [PASSED] drm_test_managed_release_action [00:13:47] [PASSED] drm_test_managed_run_action [00:13:47] =================== [PASSED] drm_managed =================== [00:13:47] =================== drm_mm (6 subtests) ==================== [00:13:47] [PASSED] drm_test_mm_init [00:13:47] [PASSED] drm_test_mm_debug [00:13:47] [PASSED] drm_test_mm_align32 [00:13:47] [PASSED] drm_test_mm_align64 [00:13:47] [PASSED] drm_test_mm_lowest [00:13:47] [PASSED] drm_test_mm_highest [00:13:47] ===================== [PASSED] drm_mm ====================== [00:13:47] ============= drm_modes_analog_tv (4 subtests) ============= [00:13:47] [PASSED] drm_test_modes_analog_tv_ntsc_480i [00:13:47] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined [00:13:47] [PASSED] drm_test_modes_analog_tv_pal_576i [00:13:47] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined [00:13:47] =============== [PASSED] drm_modes_analog_tv =============== [00:13:47] ============== drm_plane_helper (2 subtests) =============== [00:13:47] =============== drm_test_check_plane_state ================ [00:13:47] [PASSED] clipping_simple [00:13:47] [PASSED] clipping_rotate_reflect [00:13:47] [PASSED] positioning_simple [00:13:47] [PASSED] upscaling [00:13:47] [PASSED] downscaling [00:13:47] [PASSED] rounding1 [00:13:47] [PASSED] rounding2 [00:13:47] [PASSED] rounding3 [00:13:47] [PASSED] rounding4 [00:13:47] =========== [PASSED] drm_test_check_plane_state ============ [00:13:47] =========== drm_test_check_invalid_plane_state ============ [00:13:47] [PASSED] positioning_invalid [00:13:47] [PASSED] upscaling_invalid [00:13:47] [PASSED] downscaling_invalid [00:13:47] ======= [PASSED] drm_test_check_invalid_plane_state ======== [00:13:47] ================ [PASSED] drm_plane_helper ================= stty: 'standard input': Inappropriate ioctl for device [00:13:47] ====== drm_connector_helper_tv_get_modes (1 subtest) ======= [00:13:47] ====== drm_test_connector_helper_tv_get_modes_check ======= [00:13:47] [PASSED] None [00:13:47] [PASSED] PAL [00:13:47] [PASSED] NTSC [00:13:47] [PASSED] Both, NTSC Default [00:13:47] [PASSED] Both, PAL Default [00:13:47] [PASSED] Both, NTSC Default, with PAL on command-line [00:13:47] [PASSED] Both, PAL Default, with NTSC on command-line [00:13:47] == [PASSED] drm_test_connector_helper_tv_get_modes_check === [00:13:47] ======== [PASSED] drm_connector_helper_tv_get_modes ======== [00:13:47] ================== drm_rect (9 subtests) =================== [00:13:47] [PASSED] drm_test_rect_clip_scaled_div_by_zero [00:13:47] [PASSED] drm_test_rect_clip_scaled_not_clipped [00:13:47] [PASSED] drm_test_rect_clip_scaled_clipped [00:13:47] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned [00:13:47] ================= drm_test_rect_intersect ================= [00:13:47] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0 [00:13:47] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1 [00:13:47] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0 [00:13:47] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1 [00:13:47] [PASSED] right x left: 2x1+0+0 x 3x1+1+0 [00:13:47] [PASSED] left x right: 3x1+1+0 x 2x1+0+0 [00:13:47] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1 [00:13:47] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0 [00:13:47] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1 [00:13:47] [PASSED] touching side: 1x1+0+0 x 1x1+1+0 [00:13:47] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0 [00:13:47] [PASSED] inside another: 2x2+0+0 x 1x1+1+1 [00:13:47] [PASSED] far away: 1x1+0+0 x 1x1+3+6 [00:13:47] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10 [00:13:47] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10 [00:13:47] ============= [PASSED] drm_test_rect_intersect ============= [00:13:47] ================ drm_test_rect_calc_hscale ================ [00:13:47] [PASSED] normal use [00:13:47] [PASSED] out of max range [00:13:47] [PASSED] out of min range [00:13:47] [PASSED] zero dst [00:13:47] [PASSED] negative src [00:13:47] [PASSED] negative dst [00:13:47] ============ [PASSED] drm_test_rect_calc_hscale ============ [00:13:47] ================ drm_test_rect_calc_vscale ================ [00:13:47] [PASSED] normal use [00:13:47] [PASSED] out of max range [00:13:47] [PASSED] out of min range [00:13:47] [PASSED] zero dst [00:13:47] [PASSED] negative src [00:13:47] [PASSED] negative dst [00:13:47] ============ [PASSED] drm_test_rect_calc_vscale ============ [00:13:47] ================== drm_test_rect_rotate =================== [00:13:47] [PASSED] reflect-x [00:13:47] [PASSED] reflect-y [00:13:47] [PASSED] rotate-0 [00:13:47] [PASSED] rotate-90 [00:13:47] [PASSED] rotate-180 [00:13:47] [PASSED] rotate-270 [00:13:47] ============== [PASSED] drm_test_rect_rotate =============== [00:13:47] ================ drm_test_rect_rotate_inv ================= [00:13:47] [PASSED] reflect-x [00:13:47] [PASSED] reflect-y [00:13:47] [PASSED] rotate-0 [00:13:47] [PASSED] rotate-90 [00:13:47] [PASSED] rotate-180 [00:13:47] [PASSED] rotate-270 [00:13:47] ============ [PASSED] drm_test_rect_rotate_inv ============= [00:13:47] ==================== [PASSED] drm_rect ===================== [00:13:47] ============================================================ [00:13:47] Testing complete. Ran 511 tests: passed: 511 [00:13:47] Elapsed time: 23.393s total, 1.738s configuring, 21.457s building, 0.195s running + cleanup ++ stat -c %u:%g /kernel + chown -R 1003:1003 /kernel ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ CI.Build: success for drm/xe/guc: Add GuC based register capture for error capture (rev9) 2024-06-07 0:07 [PATCH v9 0/4] drm/xe/guc: Add GuC based register capture for error capture Zhanjun Dong ` (6 preceding siblings ...) 2024-06-07 0:13 ` ✓ CI.KUnit: success " Patchwork @ 2024-06-07 0:25 ` Patchwork 2024-06-07 0:27 ` ✗ CI.Hooks: failure " Patchwork ` (3 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-06-07 0:25 UTC (permalink / raw) To: Zhanjun Dong; +Cc: intel-xe == Series Details == Series: drm/xe/guc: Add GuC based register capture for error capture (rev9) URL : https://patchwork.freedesktop.org/series/128077/ State : success == Summary == lib/modules/6.10.0-rc2-xe/kernel/sound/core/seq/ lib/modules/6.10.0-rc2-xe/kernel/sound/core/seq/snd-seq.ko lib/modules/6.10.0-rc2-xe/kernel/sound/core/snd-seq-device.ko lib/modules/6.10.0-rc2-xe/kernel/sound/core/snd-hwdep.ko lib/modules/6.10.0-rc2-xe/kernel/sound/core/snd.ko lib/modules/6.10.0-rc2-xe/kernel/sound/core/snd-pcm.ko lib/modules/6.10.0-rc2-xe/kernel/sound/core/snd-compress.ko lib/modules/6.10.0-rc2-xe/kernel/sound/core/snd-timer.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soundcore.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/ lib/modules/6.10.0-rc2-xe/kernel/sound/soc/intel/ lib/modules/6.10.0-rc2-xe/kernel/sound/soc/intel/atom/ lib/modules/6.10.0-rc2-xe/kernel/sound/soc/intel/atom/snd-soc-sst-atom-hifi2-platform.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/intel/atom/sst/ lib/modules/6.10.0-rc2-xe/kernel/sound/soc/intel/atom/sst/snd-intel-sst-acpi.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/intel/atom/sst/snd-intel-sst-core.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/intel/common/ lib/modules/6.10.0-rc2-xe/kernel/sound/soc/intel/common/snd-soc-acpi-intel-match.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/amd/ lib/modules/6.10.0-rc2-xe/kernel/sound/soc/amd/snd-acp-config.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/ lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/intel/ lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-tgl.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-mlink.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-cnl.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-lnl.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-common.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-generic.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-mtl.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/amd/ lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/amd/snd-sof-amd-renoir.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/amd/snd-sof-amd-acp.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/snd-sof-utils.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/snd-sof-pci.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/snd-sof.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/snd-sof-probes.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/xtensa/ lib/modules/6.10.0-rc2-xe/kernel/sound/soc/sof/xtensa/snd-sof-xtensa-dsp.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/snd-soc-core.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/snd-soc-acpi.ko lib/modules/6.10.0-rc2-xe/kernel/sound/soc/codecs/ lib/modules/6.10.0-rc2-xe/kernel/sound/soc/codecs/snd-soc-hdac-hda.ko lib/modules/6.10.0-rc2-xe/kernel/sound/hda/ lib/modules/6.10.0-rc2-xe/kernel/sound/hda/snd-intel-sdw-acpi.ko lib/modules/6.10.0-rc2-xe/kernel/sound/hda/ext/ lib/modules/6.10.0-rc2-xe/kernel/sound/hda/ext/snd-hda-ext-core.ko lib/modules/6.10.0-rc2-xe/kernel/sound/hda/snd-intel-dspcfg.ko lib/modules/6.10.0-rc2-xe/kernel/sound/hda/snd-hda-core.ko lib/modules/6.10.0-rc2-xe/kernel/arch/ lib/modules/6.10.0-rc2-xe/kernel/arch/x86/ lib/modules/6.10.0-rc2-xe/kernel/arch/x86/kernel/ lib/modules/6.10.0-rc2-xe/kernel/arch/x86/kernel/msr.ko lib/modules/6.10.0-rc2-xe/kernel/arch/x86/kernel/cpuid.ko lib/modules/6.10.0-rc2-xe/kernel/arch/x86/crypto/ lib/modules/6.10.0-rc2-xe/kernel/arch/x86/crypto/sha512-ssse3.ko lib/modules/6.10.0-rc2-xe/kernel/arch/x86/crypto/crct10dif-pclmul.ko lib/modules/6.10.0-rc2-xe/kernel/arch/x86/crypto/ghash-clmulni-intel.ko lib/modules/6.10.0-rc2-xe/kernel/arch/x86/crypto/sha1-ssse3.ko lib/modules/6.10.0-rc2-xe/kernel/arch/x86/crypto/crc32-pclmul.ko lib/modules/6.10.0-rc2-xe/kernel/arch/x86/crypto/sha256-ssse3.ko lib/modules/6.10.0-rc2-xe/kernel/arch/x86/crypto/aesni-intel.ko lib/modules/6.10.0-rc2-xe/kernel/arch/x86/crypto/polyval-clmulni.ko lib/modules/6.10.0-rc2-xe/kernel/arch/x86/events/ lib/modules/6.10.0-rc2-xe/kernel/arch/x86/events/intel/ lib/modules/6.10.0-rc2-xe/kernel/arch/x86/events/intel/intel-cstate.ko lib/modules/6.10.0-rc2-xe/kernel/arch/x86/events/rapl.ko lib/modules/6.10.0-rc2-xe/kernel/arch/x86/kvm/ lib/modules/6.10.0-rc2-xe/kernel/arch/x86/kvm/kvm.ko lib/modules/6.10.0-rc2-xe/kernel/arch/x86/kvm/kvm-intel.ko lib/modules/6.10.0-rc2-xe/kernel/crypto/ lib/modules/6.10.0-rc2-xe/kernel/crypto/crypto_simd.ko lib/modules/6.10.0-rc2-xe/kernel/crypto/cmac.ko lib/modules/6.10.0-rc2-xe/kernel/crypto/ccm.ko lib/modules/6.10.0-rc2-xe/kernel/crypto/cryptd.ko lib/modules/6.10.0-rc2-xe/kernel/crypto/polyval-generic.ko lib/modules/6.10.0-rc2-xe/kernel/crypto/async_tx/ lib/modules/6.10.0-rc2-xe/kernel/crypto/async_tx/async_xor.ko lib/modules/6.10.0-rc2-xe/kernel/crypto/async_tx/async_tx.ko lib/modules/6.10.0-rc2-xe/kernel/crypto/async_tx/async_memcpy.ko lib/modules/6.10.0-rc2-xe/kernel/crypto/async_tx/async_pq.ko lib/modules/6.10.0-rc2-xe/kernel/crypto/async_tx/async_raid6_recov.ko lib/modules/6.10.0-rc2-xe/build lib/modules/6.10.0-rc2-xe/modules.alias.bin lib/modules/6.10.0-rc2-xe/modules.builtin lib/modules/6.10.0-rc2-xe/modules.softdep lib/modules/6.10.0-rc2-xe/modules.alias lib/modules/6.10.0-rc2-xe/modules.order lib/modules/6.10.0-rc2-xe/modules.symbols lib/modules/6.10.0-rc2-xe/modules.dep.bin + mv kernel-nodebug.tar.gz .. + cd .. + rm -rf archive ++ date +%s ^[[0Ksection_end:1717719907:package_x86_64_nodebug ^[[0K + echo -e '\e[0Ksection_end:1717719907:package_x86_64_nodebug\r\e[0K' + sync + cleanup ++ stat -c %u:%g /kernel + chown -R 1003:1003 /kernel ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ CI.Hooks: failure for drm/xe/guc: Add GuC based register capture for error capture (rev9) 2024-06-07 0:07 [PATCH v9 0/4] drm/xe/guc: Add GuC based register capture for error capture Zhanjun Dong ` (7 preceding siblings ...) 2024-06-07 0:25 ` ✓ CI.Build: " Patchwork @ 2024-06-07 0:27 ` Patchwork 2024-06-07 0:28 ` ✓ CI.checksparse: success " Patchwork ` (2 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-06-07 0:27 UTC (permalink / raw) To: Zhanjun Dong; +Cc: intel-xe == Series Details == Series: drm/xe/guc: Add GuC based register capture for error capture (rev9) URL : https://patchwork.freedesktop.org/series/128077/ State : failure == Summary == run-parts: executing /workspace/ci/hooks/00-showenv + export + grep -Ei '(^|\W)CI_' declare -x CI_KERNEL_BUILD_DIR="/workspace/kernel/build64-default" declare -x CI_KERNEL_SRC_DIR="/workspace/kernel" declare -x CI_TOOLS_SRC_DIR="/workspace/ci" declare -x CI_WORKSPACE_DIR="/workspace" run-parts: executing /workspace/ci/hooks/10-build-W1 + SRC_DIR=/workspace/kernel + RESTORE_DISPLAY_CONFIG=0 + '[' -n /workspace/kernel/build64-default ']' + BUILD_DIR=/workspace/kernel/build64-default + cd /workspace/kernel ++ nproc + make -j48 O=/workspace/kernel/build64-default modules_prepare make[1]: Entering directory '/workspace/kernel/build64-default' GEN Makefile UPD include/generated/compile.h UPD include/config/kernel.release mkdir -p /workspace/kernel/build64-default/tools/objtool && make O=/workspace/kernel/build64-default subdir=tools/objtool --no-print-directory -C objtool UPD include/generated/utsrelease.h HOSTCC /workspace/kernel/build64-default/tools/objtool/fixdep.o CALL ../scripts/checksyscalls.sh HOSTLD /workspace/kernel/build64-default/tools/objtool/fixdep-in.o LINK /workspace/kernel/build64-default/tools/objtool/fixdep INSTALL libsubcmd_headers CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/exec-cmd.o CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/help.o CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/pager.o CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/parse-options.o CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/run-command.o CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/sigchain.o CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/subcmd-config.o LD /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd-in.o AR /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd.a CC /workspace/kernel/build64-default/tools/objtool/weak.o CC /workspace/kernel/build64-default/tools/objtool/check.o CC /workspace/kernel/build64-default/tools/objtool/special.o CC /workspace/kernel/build64-default/tools/objtool/builtin-check.o CC /workspace/kernel/build64-default/tools/objtool/elf.o CC /workspace/kernel/build64-default/tools/objtool/objtool.o CC /workspace/kernel/build64-default/tools/objtool/orc_gen.o CC /workspace/kernel/build64-default/tools/objtool/orc_dump.o CC /workspace/kernel/build64-default/tools/objtool/libstring.o CC /workspace/kernel/build64-default/tools/objtool/libctype.o CC /workspace/kernel/build64-default/tools/objtool/str_error_r.o CC /workspace/kernel/build64-default/tools/objtool/librbtree.o CC /workspace/kernel/build64-default/tools/objtool/arch/x86/special.o CC /workspace/kernel/build64-default/tools/objtool/arch/x86/decode.o CC /workspace/kernel/build64-default/tools/objtool/arch/x86/orc.o LD /workspace/kernel/build64-default/tools/objtool/arch/x86/objtool-in.o LD /workspace/kernel/build64-default/tools/objtool/objtool-in.o LINK /workspace/kernel/build64-default/tools/objtool/objtool make[1]: Leaving directory '/workspace/kernel/build64-default' ++ nproc + make -j48 O=/workspace/kernel/build64-default W=1 drivers/gpu/drm/xe make[1]: Entering directory '/workspace/kernel/build64-default' make[2]: Nothing to be done for 'drivers/gpu/drm/xe'. make[1]: Leaving directory '/workspace/kernel/build64-default' run-parts: executing /workspace/ci/hooks/11-build-32b +++ realpath /workspace/ci/hooks/11-build-32b ++ dirname /workspace/ci/hooks/11-build-32b + THIS_SCRIPT_DIR=/workspace/ci/hooks + SRC_DIR=/workspace/kernel + TOOLS_SRC_DIR=/workspace/ci + '[' -n /workspace/kernel/build64-default ']' + BUILD_DIR=/workspace/kernel/build64-default + BUILD_DIR=/workspace/kernel/build64-default/build32 + cd /workspace/kernel + mkdir -p /workspace/kernel/build64-default/build32 ++ nproc + make -j48 ARCH=i386 O=/workspace/kernel/build64-default/build32 defconfig make[1]: Entering directory '/workspace/kernel/build64-default/build32' GEN Makefile HOSTCC scripts/basic/fixdep HOSTCC scripts/kconfig/conf.o HOSTCC scripts/kconfig/confdata.o HOSTCC scripts/kconfig/expr.o LEX scripts/kconfig/lexer.lex.c YACC scripts/kconfig/parser.tab.[ch] HOSTCC scripts/kconfig/menu.o HOSTCC scripts/kconfig/preprocess.o HOSTCC scripts/kconfig/symbol.o HOSTCC scripts/kconfig/util.o HOSTCC scripts/kconfig/lexer.lex.o HOSTCC scripts/kconfig/parser.tab.o HOSTLD scripts/kconfig/conf *** Default configuration is based on 'i386_defconfig' # # configuration written to .config # make[1]: Leaving directory '/workspace/kernel/build64-default/build32' + cd /workspace/kernel/build64-default/build32 + /workspace/kernel/scripts/kconfig/merge_config.sh .config /workspace/ci/kernel/10-xe.fragment Using .config as base Merging /workspace/ci/kernel/10-xe.fragment Value of CONFIG_DRM_XE is redefined by fragment /workspace/ci/kernel/10-xe.fragment: Previous value: # CONFIG_DRM_XE is not set New value: CONFIG_DRM_XE=m Value of CONFIG_SND_DEBUG is redefined by fragment /workspace/ci/kernel/10-xe.fragment: Previous value: # CONFIG_SND_DEBUG is not set New value: CONFIG_SND_DEBUG=y Value of CONFIG_SND_HDA_INTEL is redefined by fragment /workspace/ci/kernel/10-xe.fragment: Previous value: CONFIG_SND_HDA_INTEL=y New value: CONFIG_SND_HDA_INTEL=m Value of CONFIG_SND_HDA_CODEC_HDMI is redefined by fragment /workspace/ci/kernel/10-xe.fragment: Previous value: # CONFIG_SND_HDA_CODEC_HDMI is not set New value: CONFIG_SND_HDA_CODEC_HDMI=m GEN Makefile WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n] Selected by [m]: - DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] # # configuration written to .config # Value requested for CONFIG_HAVE_UID16 not in final .config Requested value: CONFIG_HAVE_UID16=y Actual value: Value requested for CONFIG_UID16 not in final .config Requested value: CONFIG_UID16=y Actual value: Value requested for CONFIG_X86_32 not in final .config Requested value: CONFIG_X86_32=y Actual value: Value requested for CONFIG_OUTPUT_FORMAT not in final .config Requested value: CONFIG_OUTPUT_FORMAT="elf32-i386" Actual value: CONFIG_OUTPUT_FORMAT="elf64-x86-64" Value requested for CONFIG_ARCH_MMAP_RND_BITS_MIN not in final .config Requested value: CONFIG_ARCH_MMAP_RND_BITS_MIN=8 Actual value: CONFIG_ARCH_MMAP_RND_BITS_MIN=28 Value requested for CONFIG_ARCH_MMAP_RND_BITS_MAX not in final .config Requested value: CONFIG_ARCH_MMAP_RND_BITS_MAX=16 Actual value: CONFIG_ARCH_MMAP_RND_BITS_MAX=32 Value requested for CONFIG_PGTABLE_LEVELS not in final .config Requested value: CONFIG_PGTABLE_LEVELS=2 Actual value: CONFIG_PGTABLE_LEVELS=5 Value requested for CONFIG_X86_BIGSMP not in final .config Requested value: # CONFIG_X86_BIGSMP is not set Actual value: Value requested for CONFIG_X86_INTEL_QUARK not in final .config Requested value: # CONFIG_X86_INTEL_QUARK is not set Actual value: Value requested for CONFIG_X86_RDC321X not in final .config Requested value: # CONFIG_X86_RDC321X is not set Actual value: Value requested for CONFIG_X86_32_NON_STANDARD not in final .config Requested value: # CONFIG_X86_32_NON_STANDARD is not set Actual value: Value requested for CONFIG_X86_32_IRIS not in final .config Requested value: # CONFIG_X86_32_IRIS is not set Actual value: Value requested for CONFIG_M486SX not in final .config Requested value: # CONFIG_M486SX is not set Actual value: Value requested for CONFIG_M486 not in final .config Requested value: # CONFIG_M486 is not set Actual value: Value requested for CONFIG_M586 not in final .config Requested value: # CONFIG_M586 is not set Actual value: Value requested for CONFIG_M586TSC not in final .config Requested value: # CONFIG_M586TSC is not set Actual value: Value requested for CONFIG_M586MMX not in final .config Requested value: # CONFIG_M586MMX is not set Actual value: Value requested for CONFIG_M686 not in final .config Requested value: CONFIG_M686=y Actual value: Value requested for CONFIG_MPENTIUMII not in final .config Requested value: # CONFIG_MPENTIUMII is not set Actual value: Value requested for CONFIG_MPENTIUMIII not in final .config Requested value: # CONFIG_MPENTIUMIII is not set Actual value: Value requested for CONFIG_MPENTIUMM not in final .config Requested value: # CONFIG_MPENTIUMM is not set Actual value: Value requested for CONFIG_MPENTIUM4 not in final .config Requested value: # CONFIG_MPENTIUM4 is not set Actual value: Value requested for CONFIG_MK6 not in final .config Requested value: # CONFIG_MK6 is not set Actual value: Value requested for CONFIG_MK7 not in final .config Requested value: # CONFIG_MK7 is not set Actual value: Value requested for CONFIG_MCRUSOE not in final .config Requested value: # CONFIG_MCRUSOE is not set Actual value: Value requested for CONFIG_MEFFICEON not in final .config Requested value: # CONFIG_MEFFICEON is not set Actual value: Value requested for CONFIG_MWINCHIPC6 not in final .config Requested value: # CONFIG_MWINCHIPC6 is not set Actual value: Value requested for CONFIG_MWINCHIP3D not in final .config Requested value: # CONFIG_MWINCHIP3D is not set Actual value: Value requested for CONFIG_MELAN not in final .config Requested value: # CONFIG_MELAN is not set Actual value: Value requested for CONFIG_MGEODEGX1 not in final .config Requested value: # CONFIG_MGEODEGX1 is not set Actual value: Value requested for CONFIG_MGEODE_LX not in final .config Requested value: # CONFIG_MGEODE_LX is not set Actual value: Value requested for CONFIG_MCYRIXIII not in final .config Requested value: # CONFIG_MCYRIXIII is not set Actual value: Value requested for CONFIG_MVIAC3_2 not in final .config Requested value: # CONFIG_MVIAC3_2 is not set Actual value: Value requested for CONFIG_MVIAC7 not in final .config Requested value: # CONFIG_MVIAC7 is not set Actual value: Value requested for CONFIG_X86_GENERIC not in final .config Requested value: # CONFIG_X86_GENERIC is not set Actual value: Value requested for CONFIG_X86_INTERNODE_CACHE_SHIFT not in final .config Requested value: CONFIG_X86_INTERNODE_CACHE_SHIFT=5 Actual value: CONFIG_X86_INTERNODE_CACHE_SHIFT=6 Value requested for CONFIG_X86_L1_CACHE_SHIFT not in final .config Requested value: CONFIG_X86_L1_CACHE_SHIFT=5 Actual value: CONFIG_X86_L1_CACHE_SHIFT=6 Value requested for CONFIG_X86_USE_PPRO_CHECKSUM not in final .config Requested value: CONFIG_X86_USE_PPRO_CHECKSUM=y Actual value: Value requested for CONFIG_X86_MINIMUM_CPU_FAMILY not in final .config Requested value: CONFIG_X86_MINIMUM_CPU_FAMILY=6 Actual value: CONFIG_X86_MINIMUM_CPU_FAMILY=64 Value requested for CONFIG_CPU_SUP_TRANSMETA_32 not in final .config Requested value: CONFIG_CPU_SUP_TRANSMETA_32=y Actual value: Value requested for CONFIG_CPU_SUP_VORTEX_32 not in final .config Requested value: CONFIG_CPU_SUP_VORTEX_32=y Actual value: Value requested for CONFIG_HPET_TIMER not in final .config Requested value: # CONFIG_HPET_TIMER is not set Actual value: CONFIG_HPET_TIMER=y Value requested for CONFIG_NR_CPUS_RANGE_END not in final .config Requested value: CONFIG_NR_CPUS_RANGE_END=8 Actual value: CONFIG_NR_CPUS_RANGE_END=512 Value requested for CONFIG_NR_CPUS_DEFAULT not in final .config Requested value: CONFIG_NR_CPUS_DEFAULT=8 Actual value: CONFIG_NR_CPUS_DEFAULT=64 Value requested for CONFIG_X86_ANCIENT_MCE not in final .config Requested value: # CONFIG_X86_ANCIENT_MCE is not set Actual value: Value requested for CONFIG_X86_LEGACY_VM86 not in final .config Requested value: # CONFIG_X86_LEGACY_VM86 is not set Actual value: Value requested for CONFIG_X86_ESPFIX32 not in final .config Requested value: CONFIG_X86_ESPFIX32=y Actual value: Value requested for CONFIG_TOSHIBA not in final .config Requested value: # CONFIG_TOSHIBA is not set Actual value: Value requested for CONFIG_X86_REBOOTFIXUPS not in final .config Requested value: # CONFIG_X86_REBOOTFIXUPS is not set Actual value: Value requested for CONFIG_MICROCODE_INITRD32 not in final .config Requested value: CONFIG_MICROCODE_INITRD32=y Actual value: Value requested for CONFIG_NOHIGHMEM not in final .config Requested value: # CONFIG_NOHIGHMEM is not set Actual value: Value requested for CONFIG_HIGHMEM4G not in final .config Requested value: CONFIG_HIGHMEM4G=y Actual value: Value requested for CONFIG_HIGHMEM64G not in final .config Requested value: # CONFIG_HIGHMEM64G is not set Actual value: Value requested for CONFIG_PAGE_OFFSET not in final .config Requested value: CONFIG_PAGE_OFFSET=0xC0000000 Actual value: Value requested for CONFIG_HIGHMEM not in final .config Requested value: CONFIG_HIGHMEM=y Actual value: Value requested for CONFIG_X86_PAE not in final .config Requested value: # CONFIG_X86_PAE is not set Actual value: Value requested for CONFIG_ARCH_FLATMEM_ENABLE not in final .config Requested value: CONFIG_ARCH_FLATMEM_ENABLE=y Actual value: Value requested for CONFIG_ARCH_SELECT_MEMORY_MODEL not in final .config Requested value: CONFIG_ARCH_SELECT_MEMORY_MODEL=y Actual value: Value requested for CONFIG_ILLEGAL_POINTER_VALUE not in final .config Requested value: CONFIG_ILLEGAL_POINTER_VALUE=0 Actual value: CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 Value requested for CONFIG_HIGHPTE not in final .config Requested value: # CONFIG_HIGHPTE is not set Actual value: Value requested for CONFIG_COMPAT_VDSO not in final .config Requested value: # CONFIG_COMPAT_VDSO is not set Actual value: Value requested for CONFIG_FUNCTION_PADDING_CFI not in final .config Requested value: CONFIG_FUNCTION_PADDING_CFI=0 Actual value: CONFIG_FUNCTION_PADDING_CFI=11 Value requested for CONFIG_FUNCTION_PADDING_BYTES not in final .config Requested value: CONFIG_FUNCTION_PADDING_BYTES=4 Actual value: CONFIG_FUNCTION_PADDING_BYTES=16 Value requested for CONFIG_APM not in final .config Requested value: # CONFIG_APM is not set Actual value: Value requested for CONFIG_X86_POWERNOW_K6 not in final .config Requested value: # CONFIG_X86_POWERNOW_K6 is not set Actual value: Value requested for CONFIG_X86_POWERNOW_K7 not in final .config Requested value: # CONFIG_X86_POWERNOW_K7 is not set Actual value: Value requested for CONFIG_X86_GX_SUSPMOD not in final .config Requested value: # CONFIG_X86_GX_SUSPMOD is not set Actual value: Value requested for CONFIG_X86_SPEEDSTEP_ICH not in final .config Requested value: # CONFIG_X86_SPEEDSTEP_ICH is not set Actual value: Value requested for CONFIG_X86_SPEEDSTEP_SMI not in final .config Requested value: # CONFIG_X86_SPEEDSTEP_SMI is not set Actual value: Value requested for CONFIG_X86_CPUFREQ_NFORCE2 not in final .config Requested value: # CONFIG_X86_CPUFREQ_NFORCE2 is not set Actual value: Value requested for CONFIG_X86_LONGRUN not in final .config Requested value: # CONFIG_X86_LONGRUN is not set Actual value: Value requested for CONFIG_X86_LONGHAUL not in final .config Requested value: # CONFIG_X86_LONGHAUL is not set Actual value: Value requested for CONFIG_X86_E_POWERSAVER not in final .config Requested value: # CONFIG_X86_E_POWERSAVER is not set Actual value: Value requested for CONFIG_PCI_GOBIOS not in final .config Requested value: # CONFIG_PCI_GOBIOS is not set Actual value: Value requested for CONFIG_PCI_GOMMCONFIG not in final .config Requested value: # CONFIG_PCI_GOMMCONFIG is not set Actual value: Value requested for CONFIG_PCI_GODIRECT not in final .config Requested value: # CONFIG_PCI_GODIRECT is not set Actual value: Value requested for CONFIG_PCI_GOANY not in final .config Requested value: CONFIG_PCI_GOANY=y Actual value: Value requested for CONFIG_PCI_BIOS not in final .config Requested value: CONFIG_PCI_BIOS=y Actual value: Value requested for CONFIG_ISA not in final .config Requested value: # CONFIG_ISA is not set Actual value: Value requested for CONFIG_SCx200 not in final .config Requested value: # CONFIG_SCx200 is not set Actual value: Value requested for CONFIG_OLPC not in final .config Requested value: # CONFIG_OLPC is not set Actual value: Value requested for CONFIG_ALIX not in final .config Requested value: # CONFIG_ALIX is not set Actual value: Value requested for CONFIG_NET5501 not in final .config Requested value: # CONFIG_NET5501 is not set Actual value: Value requested for CONFIG_GEOS not in final .config Requested value: # CONFIG_GEOS is not set Actual value: Value requested for CONFIG_COMPAT_32 not in final .config Requested value: CONFIG_COMPAT_32=y Actual value: Value requested for CONFIG_HAVE_ATOMIC_IOMAP not in final .config Requested value: CONFIG_HAVE_ATOMIC_IOMAP=y Actual value: Value requested for CONFIG_ARCH_32BIT_OFF_T not in final .config Requested value: CONFIG_ARCH_32BIT_OFF_T=y Actual value: Value requested for CONFIG_ARCH_WANT_IPC_PARSE_VERSION not in final .config Requested value: CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y Actual value: Value requested for CONFIG_MODULES_USE_ELF_REL not in final .config Requested value: CONFIG_MODULES_USE_ELF_REL=y Actual value: Value requested for CONFIG_ARCH_MMAP_RND_BITS not in final .config Requested value: CONFIG_ARCH_MMAP_RND_BITS=8 Actual value: CONFIG_ARCH_MMAP_RND_BITS=28 Value requested for CONFIG_CLONE_BACKWARDS not in final .config Requested value: CONFIG_CLONE_BACKWARDS=y Actual value: Value requested for CONFIG_OLD_SIGSUSPEND3 not in final .config Requested value: CONFIG_OLD_SIGSUSPEND3=y Actual value: Value requested for CONFIG_OLD_SIGACTION not in final .config Requested value: CONFIG_OLD_SIGACTION=y Actual value: Value requested for CONFIG_ARCH_SPLIT_ARG64 not in final .config Requested value: CONFIG_ARCH_SPLIT_ARG64=y Actual value: Value requested for CONFIG_FUNCTION_ALIGNMENT not in final .config Requested value: CONFIG_FUNCTION_ALIGNMENT=4 Actual value: CONFIG_FUNCTION_ALIGNMENT=16 Value requested for CONFIG_SELECT_MEMORY_MODEL not in final .config Requested value: CONFIG_SELECT_MEMORY_MODEL=y Actual value: Value requested for CONFIG_FLATMEM_MANUAL not in final .config Requested value: CONFIG_FLATMEM_MANUAL=y Actual value: Value requested for CONFIG_SPARSEMEM_MANUAL not in final .config Requested value: # CONFIG_SPARSEMEM_MANUAL is not set Actual value: Value requested for CONFIG_FLATMEM not in final .config Requested value: CONFIG_FLATMEM=y Actual value: Value requested for CONFIG_SPARSEMEM_STATIC not in final .config Requested value: CONFIG_SPARSEMEM_STATIC=y Actual value: Value requested for CONFIG_BOUNCE not in final .config Requested value: CONFIG_BOUNCE=y Actual value: Value requested for CONFIG_KMAP_LOCAL not in final .config Requested value: CONFIG_KMAP_LOCAL=y Actual value: Value requested for CONFIG_HOTPLUG_PCI_COMPAQ not in final .config Requested value: # CONFIG_HOTPLUG_PCI_COMPAQ is not set Actual value: Value requested for CONFIG_HOTPLUG_PCI_IBM not in final .config Requested value: # CONFIG_HOTPLUG_PCI_IBM is not set Actual value: Value requested for CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH not in final .config Requested value: CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH=y Actual value: Value requested for CONFIG_PCH_PHUB not in final .config Requested value: # CONFIG_PCH_PHUB is not set Actual value: Value requested for CONFIG_SCSI_NSP32 not in final .config Requested value: # CONFIG_SCSI_NSP32 is not set Actual value: Value requested for CONFIG_PATA_CS5520 not in final .config Requested value: # CONFIG_PATA_CS5520 is not set Actual value: Value requested for CONFIG_PATA_CS5530 not in final .config Requested value: # CONFIG_PATA_CS5530 is not set Actual value: Value requested for CONFIG_PATA_CS5535 not in final .config Requested value: # CONFIG_PATA_CS5535 is not set Actual value: Value requested for CONFIG_PATA_CS5536 not in final .config Requested value: # CONFIG_PATA_CS5536 is not set Actual value: Value requested for CONFIG_PATA_SC1200 not in final .config Requested value: # CONFIG_PATA_SC1200 is not set Actual value: Value requested for CONFIG_PCH_GBE not in final .config Requested value: # CONFIG_PCH_GBE is not set Actual value: Value requested for CONFIG_INPUT_WISTRON_BTNS not in final .config Requested value: # CONFIG_INPUT_WISTRON_BTNS is not set Actual value: Value requested for CONFIG_SERIAL_TIMBERDALE not in final .config Requested value: # CONFIG_SERIAL_TIMBERDALE is not set Actual value: Value requested for CONFIG_SERIAL_PCH_UART not in final .config Requested value: # CONFIG_SERIAL_PCH_UART is not set Actual value: Value requested for CONFIG_HW_RANDOM_GEODE not in final .config Requested value: CONFIG_HW_RANDOM_GEODE=y Actual value: Value requested for CONFIG_SONYPI not in final .config Requested value: # CONFIG_SONYPI is not set Actual value: Value requested for CONFIG_PC8736x_GPIO not in final .config Requested value: # CONFIG_PC8736x_GPIO is not set Actual value: Value requested for CONFIG_NSC_GPIO not in final .config Requested value: # CONFIG_NSC_GPIO is not set Actual value: Value requested for CONFIG_I2C_EG20T not in final .config Requested value: # CONFIG_I2C_EG20T is not set Actual value: Value requested for CONFIG_SCx200_ACB not in final .config Requested value: # CONFIG_SCx200_ACB is not set Actual value: Value requested for CONFIG_PTP_1588_CLOCK_PCH not in final .config Requested value: # CONFIG_PTP_1588_CLOCK_PCH is not set Actual value: Value requested for CONFIG_SBC8360_WDT not in final .config Requested value: # CONFIG_SBC8360_WDT is not set Actual value: Value requested for CONFIG_SBC7240_WDT not in final .config Requested value: # CONFIG_SBC7240_WDT is not set Actual value: Value requested for CONFIG_MFD_CS5535 not in final .config Requested value: # CONFIG_MFD_CS5535 is not set Actual value: Value requested for CONFIG_AGP_ALI not in final .config Requested value: # CONFIG_AGP_ALI is not set Actual value: Value requested for CONFIG_AGP_ATI not in final .config Requested value: # CONFIG_AGP_ATI is not set Actual value: Value requested for CONFIG_AGP_AMD not in final .config Requested value: # CONFIG_AGP_AMD is not set Actual value: Value requested for CONFIG_AGP_NVIDIA not in final .config Requested value: # CONFIG_AGP_NVIDIA is not set Actual value: Value requested for CONFIG_AGP_SWORKS not in final .config Requested value: # CONFIG_AGP_SWORKS is not set Actual value: Value requested for CONFIG_AGP_EFFICEON not in final .config Requested value: # CONFIG_AGP_EFFICEON is not set Actual value: Value requested for CONFIG_SND_PCM not in final .config Requested value: CONFIG_SND_PCM=y Actual value: CONFIG_SND_PCM=m Value requested for CONFIG_SND_HWDEP not in final .config Requested value: CONFIG_SND_HWDEP=y Actual value: CONFIG_SND_HWDEP=m Value requested for CONFIG_SND_DYNAMIC_MINORS not in final .config Requested value: # CONFIG_SND_DYNAMIC_MINORS is not set Actual value: CONFIG_SND_DYNAMIC_MINORS=y Value requested for CONFIG_SND_CS5530 not in final .config Requested value: # CONFIG_SND_CS5530 is not set Actual value: Value requested for CONFIG_SND_CS5535AUDIO not in final .config Requested value: # CONFIG_SND_CS5535AUDIO is not set Actual value: Value requested for CONFIG_SND_SIS7019 not in final .config Requested value: # CONFIG_SND_SIS7019 is not set Actual value: Value requested for CONFIG_SND_HDA not in final .config Requested value: CONFIG_SND_HDA=y Actual value: CONFIG_SND_HDA=m Value requested for CONFIG_SND_HDA_CORE not in final .config Requested value: CONFIG_SND_HDA_CORE=y Actual value: CONFIG_SND_HDA_CORE=m Value requested for CONFIG_SND_INTEL_DSP_CONFIG not in final .config Requested value: CONFIG_SND_INTEL_DSP_CONFIG=y Actual value: CONFIG_SND_INTEL_DSP_CONFIG=m Value requested for CONFIG_SND_INTEL_SOUNDWIRE_ACPI not in final .config Requested value: CONFIG_SND_INTEL_SOUNDWIRE_ACPI=y Actual value: CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m Value requested for CONFIG_LEDS_OT200 not in final .config Requested value: # CONFIG_LEDS_OT200 is not set Actual value: Value requested for CONFIG_PCH_DMA not in final .config Requested value: # CONFIG_PCH_DMA is not set Actual value: Value requested for CONFIG_CLKSRC_I8253 not in final .config Requested value: CONFIG_CLKSRC_I8253=y Actual value: Value requested for CONFIG_MAILBOX not in final .config Requested value: # CONFIG_MAILBOX is not set Actual value: CONFIG_MAILBOX=y Value requested for CONFIG_CRYPTO_SERPENT_SSE2_586 not in final .config Requested value: # CONFIG_CRYPTO_SERPENT_SSE2_586 is not set Actual value: Value requested for CONFIG_CRYPTO_TWOFISH_586 not in final .config Requested value: # CONFIG_CRYPTO_TWOFISH_586 is not set Actual value: Value requested for CONFIG_CRYPTO_DEV_GEODE not in final .config Requested value: # CONFIG_CRYPTO_DEV_GEODE is not set Actual value: Value requested for CONFIG_CRYPTO_DEV_HIFN_795X not in final .config Requested value: # CONFIG_CRYPTO_DEV_HIFN_795X is not set Actual value: Value requested for CONFIG_CRYPTO_LIB_POLY1305_RSIZE not in final .config Requested value: CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 Actual value: CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 Value requested for CONFIG_AUDIT_GENERIC not in final .config Requested value: CONFIG_AUDIT_GENERIC=y Actual value: Value requested for CONFIG_GENERIC_VDSO_32 not in final .config Requested value: CONFIG_GENERIC_VDSO_32=y Actual value: Value requested for CONFIG_DEBUG_KMAP_LOCAL not in final .config Requested value: # CONFIG_DEBUG_KMAP_LOCAL is not set Actual value: Value requested for CONFIG_DEBUG_HIGHMEM not in final .config Requested value: # CONFIG_DEBUG_HIGHMEM is not set Actual value: Value requested for CONFIG_HAVE_DEBUG_STACKOVERFLOW not in final .config Requested value: CONFIG_HAVE_DEBUG_STACKOVERFLOW=y Actual value: Value requested for CONFIG_DEBUG_STACKOVERFLOW not in final .config Requested value: # CONFIG_DEBUG_STACKOVERFLOW is not set Actual value: Value requested for CONFIG_HAVE_FUNCTION_GRAPH_TRACER not in final .config Requested value: CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y Actual value: Value requested for CONFIG_HAVE_FUNCTION_GRAPH_RETVAL not in final .config Requested value: CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y Actual value: Value requested for CONFIG_DRM_KUNIT_TEST not in final .config Requested value: CONFIG_DRM_KUNIT_TEST=m Actual value: Value requested for CONFIG_DRM_XE_WERROR not in final .config Requested value: CONFIG_DRM_XE_WERROR=y Actual value: Value requested for CONFIG_DRM_XE_DEBUG not in final .config Requested value: CONFIG_DRM_XE_DEBUG=y Actual value: Value requested for CONFIG_DRM_XE_DEBUG_MEM not in final .config Requested value: CONFIG_DRM_XE_DEBUG_MEM=y Actual value: Value requested for CONFIG_DRM_XE_KUNIT_TEST not in final .config Requested value: CONFIG_DRM_XE_KUNIT_TEST=m Actual value: ++ nproc + make -j48 ARCH=i386 olddefconfig GEN Makefile WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n] Selected by [m]: - DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] # # configuration written to .config # ++ nproc + make -j48 ARCH=i386 SYNC include/config/auto.conf.cmd GEN Makefile WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n] Selected by [m]: - DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n] Selected by [m]: - DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n] Selected by [m]: - DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] GEN Makefile WRAP arch/x86/include/generated/uapi/asm/bpf_perf_event.h WRAP arch/x86/include/generated/uapi/asm/errno.h WRAP arch/x86/include/generated/uapi/asm/fcntl.h UPD include/generated/uapi/linux/version.h WRAP arch/x86/include/generated/uapi/asm/ioctl.h WRAP arch/x86/include/generated/uapi/asm/ioctls.h WRAP arch/x86/include/generated/uapi/asm/ipcbuf.h WRAP arch/x86/include/generated/uapi/asm/param.h WRAP arch/x86/include/generated/uapi/asm/poll.h WRAP arch/x86/include/generated/uapi/asm/resource.h WRAP arch/x86/include/generated/uapi/asm/socket.h WRAP arch/x86/include/generated/uapi/asm/sockios.h WRAP arch/x86/include/generated/uapi/asm/termbits.h WRAP arch/x86/include/generated/uapi/asm/termios.h WRAP arch/x86/include/generated/uapi/asm/types.h SYSHDR arch/x86/include/generated/uapi/asm/unistd_32.h SYSHDR arch/x86/include/generated/uapi/asm/unistd_64.h SYSHDR arch/x86/include/generated/uapi/asm/unistd_x32.h SYSTBL arch/x86/include/generated/asm/syscalls_32.h HOSTCC arch/x86/tools/relocs_32.o HOSTCC arch/x86/tools/relocs_64.o UPD include/generated/compile.h HOSTCC arch/x86/tools/relocs_common.o WRAP arch/x86/include/generated/asm/early_ioremap.h WRAP arch/x86/include/generated/asm/mcs_spinlock.h WRAP arch/x86/include/generated/asm/irq_regs.h WRAP arch/x86/include/generated/asm/kmap_size.h WRAP arch/x86/include/generated/asm/local64.h WRAP arch/x86/include/generated/asm/mmiowb.h WRAP arch/x86/include/generated/asm/module.lds.h WRAP arch/x86/include/generated/asm/rwonce.h WRAP arch/x86/include/generated/asm/unaligned.h HOSTCC scripts/kallsyms HOSTCC scripts/sorttable HOSTCC scripts/asn1_compiler HOSTCC scripts/selinux/genheaders/genheaders HOSTCC scripts/selinux/mdp/mdp HOSTLD arch/x86/tools/relocs UPD include/config/kernel.release UPD include/generated/utsrelease.h CC scripts/mod/empty.o HOSTCC scripts/mod/mk_elfconfig CC scripts/mod/devicetable-offsets.s UPD scripts/mod/devicetable-offsets.h MKELF scripts/mod/elfconfig.h HOSTCC scripts/mod/modpost.o HOSTCC scripts/mod/file2alias.o HOSTCC scripts/mod/sumversion.o HOSTCC scripts/mod/symsearch.o HOSTLD scripts/mod/modpost CC kernel/bounds.s CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-arch-fallback.h CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-instrumented.h CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-long.h UPD include/generated/timeconst.h UPD include/generated/bounds.h CC arch/x86/kernel/asm-offsets.s UPD include/generated/asm-offsets.h CALL /workspace/kernel/scripts/checksyscalls.sh LDS scripts/module.lds CC ipc/util.o CC ipc/msgutil.o HOSTCC usr/gen_init_cpio CC ipc/msg.o CC init/main.o CC ipc/sem.o CC ipc/shm.o CC certs/system_keyring.o CC ipc/syscall.o AS arch/x86/lib/atomic64_cx8_32.o AS arch/x86/lib/checksum_32.o CC arch/x86/video/video-common.o CC ipc/ipc_sysctl.o CC arch/x86/lib/cmdline.o CC io_uring/io_uring.o CC init/do_mounts.o AS arch/x86/lib/cmpxchg8b_emu.o CC io_uring/opdef.o CC ipc/mqueue.o UPD init/utsversion-tmp.h CC mm/filemap.o CC arch/x86/pci/i386.o AR arch/x86/net/built-in.a CC arch/x86/realmode/init.o CC arch/x86/power/cpu.o AR arch/x86/crypto/built-in.a AR drivers/cache/built-in.a CC security/keys/gc.o AR drivers/irqchip/built-in.a AR virt/lib/built-in.a GEN security/selinux/flask.h security/selinux/av_permissions.h CC block/partitions/core.o AR arch/x86/virt/svm/built-in.a CC lib/math/div64.o CC arch/x86/events/amd/core.o CC security/integrity/iint.o CC arch/x86/events/amd/lbr.o AR arch/x86/platform/atom/built-in.a AR sound/i2c/other/built-in.a CC net/core/sock.o CC security/selinux/avc.o CC arch/x86/kernel/fpu/init.o AR virt/built-in.a AR sound/isa/ad1816a/built-in.a CC fs/notify/dnotify/dnotify.o AR sound/drivers/opl3/built-in.a AR sound/i2c/built-in.a CC arch/x86/mm/pat/set_memory.o CC sound/core/seq/seq.o CC arch/x86/events/amd/ibs.o AR sound/ppc/built-in.a AR arch/x86/virt/vmx/built-in.a CC arch/x86/events/intel/core.o AR sound/pci/ac97/built-in.a AR drivers/bus/mhi/built-in.a AR arch/x86/platform/ce4100/built-in.a CC arch/x86/platform/efi/memmap.o CC fs/nfs_common/nfsacl.o AR arch/x86/virt/built-in.a AR sound/drivers/opl4/built-in.a CC arch/x86/entry/vdso/vma.o CC fs/nfs_common/grace.o AR sound/isa/ad1848/built-in.a AR sound/drivers/mpu401/built-in.a CC arch/x86/mm/pat/memtype.o AR drivers/bus/built-in.a CC sound/core/sound.o AR sound/pci/ali5451/built-in.a CC arch/x86/events/intel/bts.o CC kernel/sched/core.o AR sound/isa/cs423x/built-in.a AR sound/pci/asihpi/built-in.a AR sound/arm/built-in.a AR sound/drivers/vx/built-in.a AR sound/isa/es1688/built-in.a AR drivers/pwm/built-in.a AR sound/pci/au88x0/built-in.a CC crypto/asymmetric_keys/asymmetric_type.o AR sound/drivers/pcsp/built-in.a CC drivers/pci/msi/pcidev_msi.o CC kernel/sched/fair.o CC arch/x86/lib/cpu.o AR sound/isa/galaxy/built-in.a AR sound/pci/aw2/built-in.a AR sound/drivers/built-in.a AR sound/pci/ctxfi/built-in.a AR sound/isa/gus/built-in.a CC lib/math/gcd.o CC arch/x86/pci/init.o AR sound/pci/ca0106/built-in.a AR sound/isa/msnd/built-in.a AR sound/pci/cs46xx/built-in.a AR sound/isa/opti9xx/built-in.a AR sound/pci/cs5535audio/built-in.a AR sound/isa/sb/built-in.a CC lib/math/lcm.o AR sound/pci/lola/built-in.a AR sound/isa/wavefront/built-in.a AR sound/isa/wss/built-in.a AR sound/pci/lx6464es/built-in.a AR sound/isa/built-in.a AR sound/pci/echoaudio/built-in.a CC lib/math/int_log.o AR sound/pci/emu10k1/built-in.a AR sound/pci/hda/built-in.a CC drivers/video/console/dummycon.o GEN usr/initramfs_data.cpio CC [M] sound/pci/hda/hda_bind.o COPY usr/initramfs_inc_data AS usr/initramfs_data.o HOSTCC certs/extract-cert CC arch/x86/kernel/fpu/bugs.o AR usr/built-in.a CC lib/math/int_pow.o CC drivers/video/backlight/backlight.o CC lib/math/int_sqrt.o CC arch/x86/kernel/fpu/core.o CC mm/mempool.o CC arch/x86/lib/delay.o CC lib/math/reciprocal_div.o CC sound/core/seq/seq_lock.o AS arch/x86/realmode/rm/header.o AR arch/x86/video/built-in.a AS arch/x86/realmode/rm/trampoline_32.o CC io_uring/kbuf.o CC lib/math/rational.o CERT certs/x509_certificate_list CERT certs/signing_key.x509 AS certs/system_certificates.o AS arch/x86/realmode/rm/stack.o CC arch/x86/mm/init.o AS arch/x86/realmode/rm/reboot.o AR certs/built-in.a CC kernel/sched/build_policy.o CC ipc/namespace.o CC security/integrity/integrity_audit.o CC sound/core/init.o CC net/ethernet/eth.o AS arch/x86/realmode/rm/wakeup_asm.o CC mm/oom_kill.o CC drivers/pci/msi/api.o CC arch/x86/realmode/rm/wakemain.o CC security/keys/key.o AR fs/nfs_common/built-in.a CC arch/x86/entry/vdso/extable.o CC mm/fadvise.o CC crypto/asymmetric_keys/restrict.o AR fs/notify/dnotify/built-in.a CC arch/x86/platform/efi/quirks.o AS arch/x86/lib/getuser.o CC fs/notify/inotify/inotify_fsnotify.o CC arch/x86/power/hibernate_32.o CC arch/x86/pci/pcbios.o GEN arch/x86/lib/inat-tables.c CC arch/x86/pci/mmconfig_32.o CC arch/x86/realmode/rm/video-mode.o CC fs/notify/inotify/inotify_user.o CC arch/x86/lib/insn-eval.o CC lib/crypto/mpi/generic_mpih-lshift.o CC drivers/video/console/vgacon.o CC block/partitions/msdos.o CC sound/core/seq/seq_clientmgr.o AS arch/x86/realmode/rm/copy.o AS arch/x86/realmode/rm/bioscall.o CC arch/x86/realmode/rm/regs.o AR lib/math/built-in.a CC lib/crypto/memneq.o AR drivers/idle/built-in.a CC block/bdev.o AR arch/x86/entry/vsyscall/built-in.a AR drivers/char/ipmi/built-in.a CC lib/crypto/utils.o CC arch/x86/realmode/rm/video-vga.o CC [M] sound/pci/hda/hda_codec.o CC drivers/acpi/acpica/dsargs.o CC lib/crypto/chacha.o CC arch/x86/events/amd/uncore.o CC arch/x86/realmode/rm/video-vesa.o CC block/partitions/efi.o CC drivers/pci/msi/msi.o CC crypto/asymmetric_keys/signature.o AR drivers/video/backlight/built-in.a CC arch/x86/mm/init_32.o AR sound/pci/ice1712/built-in.a AR drivers/video/fbdev/core/built-in.a CC io_uring/rsrc.o CC arch/x86/realmode/rm/video-bios.o AR drivers/video/fbdev/omap/built-in.a CC crypto/asymmetric_keys/public_key.o AS arch/x86/entry/entry.o AR drivers/video/fbdev/omap2/omapfb/dss/built-in.a AR drivers/video/fbdev/omap2/omapfb/displays/built-in.a CC arch/x86/mm/pat/memtype_interval.o AR drivers/video/fbdev/omap2/omapfb/built-in.a AR drivers/acpi/pmic/built-in.a PASYMS arch/x86/realmode/rm/pasyms.h AR drivers/video/fbdev/omap2/built-in.a CC [M] sound/pci/hda/hda_jack.o LDS arch/x86/realmode/rm/realmode.lds AR drivers/video/fbdev/built-in.a LD arch/x86/realmode/rm/realmode.elf AR security/integrity/built-in.a RELOCS arch/x86/realmode/rm/realmode.relocs OBJCOPY arch/x86/realmode/rm/realmode.bin CC drivers/acpi/acpica/dscontrol.o AS arch/x86/realmode/rmpiggy.o CC lib/zlib_inflate/inffast.o CC drivers/acpi/acpica/dsdebug.o AR sound/pci/korg1212/built-in.a CC drivers/acpi/acpica/dsfield.o CC security/commoncap.o AR arch/x86/realmode/built-in.a CC lib/zlib_inflate/inflate.o CC drivers/acpi/acpica/dsinit.o CC init/do_mounts_initrd.o CC lib/crypto/mpi/generic_mpih-mul1.o AS arch/x86/power/hibernate_asm_32.o CC drivers/acpi/acpica/dsmethod.o AS arch/x86/entry/entry_32.o CC arch/x86/power/hibernate.o CC arch/x86/pci/direct.o LDS arch/x86/entry/vdso/vdso32/vdso32.lds CC init/initramfs.o CC security/selinux/hooks.o CC security/keys/keyring.o AS arch/x86/entry/vdso/vdso32/note.o ASN.1 crypto/asymmetric_keys/x509.asn1.[ch] CC sound/core/memory.o CC ipc/mq_sysctl.o CC sound/core/control.o AS arch/x86/entry/vdso/vdso32/system_call.o AS arch/x86/entry/vdso/vdso32/sigreturn.o CC init/calibrate.o CC arch/x86/entry/vdso/vdso32/vclock_gettime.o CC arch/x86/kernel/fpu/regset.o CC arch/x86/platform/efi/efi.o AR sound/pci/mixart/built-in.a CC arch/x86/lib/insn.o CC [M] sound/pci/hda/hda_auto_parser.o CC [M] sound/pci/hda/hda_sysfs.o CC arch/x86/entry/vdso/vdso32/vgetcpu.o AR fs/notify/inotify/built-in.a ASN.1 crypto/asymmetric_keys/x509_akid.asn1.[ch] CC init/init_task.o AR fs/notify/fanotify/built-in.a HOSTCC arch/x86/entry/vdso/vdso2c CC arch/x86/lib/kaslr.o CC fs/notify/fsnotify.o CC io_uring/notif.o CC lib/zlib_deflate/deflate.o CC crypto/api.o CC fs/notify/notification.o AR drivers/video/console/built-in.a CC crypto/asymmetric_keys/x509_loader.o CC drivers/video/aperture.o AR arch/x86/mm/pat/built-in.a CC drivers/acpi/acpica/dsmthdat.o CC crypto/cipher.o AR ipc/built-in.a CC arch/x86/mm/fault.o AR net/ethernet/built-in.a CC drivers/pci/pcie/portdrv.o CC crypto/compress.o CC lib/crypto/mpi/generic_mpih-mul2.o CC arch/x86/lib/memcpy_32.o CC lib/zlib_inflate/infutil.o AS arch/x86/lib/memmove_32.o CC drivers/pci/msi/irqdomain.o CC arch/x86/lib/misc.o CC drivers/pci/pcie/rcec.o CC crypto/asymmetric_keys/x509_public_key.o AR block/partitions/built-in.a CC sound/core/seq/seq_memory.o CC lib/crypto/aes.o AR net/802/built-in.a CC block/fops.o CC arch/x86/lib/pc-conf-reg.o CC lib/zlib_inflate/inftrees.o AR arch/x86/power/built-in.a AR arch/x86/events/amd/built-in.a CC lib/lzo/lzo1x_compress.o CC lib/lzo/lzo1x_decompress_safe.o CC drivers/pci/pcie/aspm.o CC arch/x86/pci/mmconfig-shared.o CC arch/x86/pci/fixup.o CC arch/x86/entry/vdso/vdso32-setup.o CC arch/x86/platform/efi/efi_32.o CC [M] sound/pci/hda/hda_controller.o CC lib/lz4/lz4_decompress.o AS arch/x86/lib/putuser.o CC drivers/acpi/acpica/dsobject.o CC lib/zlib_inflate/inflate_syms.o AS arch/x86/lib/retpoline.o CC [M] sound/pci/hda/hda_proc.o CC arch/x86/lib/string_32.o CC arch/x86/kernel/fpu/signal.o CC arch/x86/pci/acpi.o CC arch/x86/lib/strstr_32.o CC init/version.o CC kernel/sched/build_utility.o CC arch/x86/lib/usercopy.o CC sound/core/misc.o VDSO arch/x86/entry/vdso/vdso32.so.dbg OBJCOPY arch/x86/entry/vdso/vdso32.so CC crypto/algapi.o VDSO2C arch/x86/entry/vdso/vdso-image-32.c CC arch/x86/entry/vdso/vdso-image-32.o CC arch/x86/pci/legacy.o CC fs/notify/group.o CC arch/x86/pci/irq.o CC lib/zlib_deflate/deftree.o CC lib/crypto/mpi/generic_mpih-mul3.o CC fs/notify/mark.o CC arch/x86/lib/usercopy_32.o AR lib/lzo/built-in.a CC drivers/pci/pcie/pme.o CC drivers/video/cmdline.o AR arch/x86/platform/geode/built-in.a CC security/keys/keyctl.o ASN.1 crypto/asymmetric_keys/pkcs7.asn1.[ch] CC crypto/asymmetric_keys/pkcs7_trust.o CC lib/zlib_deflate/deflate_syms.o CC lib/crypto/arc4.o CC arch/x86/pci/common.o CC arch/x86/events/intel/ds.o AR init/built-in.a AR lib/zlib_inflate/built-in.a CC security/keys/permission.o CC security/keys/process_keys.o CC security/keys/request_key.o CC drivers/acpi/acpica/dsopcode.o CC fs/notify/fdinfo.o AR arch/x86/entry/vdso/built-in.a CC arch/x86/entry/syscall_32.o CC drivers/video/nomodeset.o AR drivers/pci/msi/built-in.a CC arch/x86/mm/ioremap.o CC crypto/asymmetric_keys/pkcs7_verify.o CC sound/core/seq/seq_queue.o CC net/core/request_sock.o CC net/core/skbuff.o CC arch/x86/lib/msr-smp.o CC mm/maccess.o CC crypto/asymmetric_keys/x509.asn1.o CC crypto/asymmetric_keys/x509_akid.asn1.o CC crypto/asymmetric_keys/x509_cert_parser.o CC net/core/datagram.o CC arch/x86/entry/common.o CC [M] sound/pci/hda/hda_hwdep.o AS arch/x86/platform/efi/efi_stub_32.o CC crypto/asymmetric_keys/pkcs7.asn1.o CC arch/x86/platform/efi/runtime-map.o CC crypto/asymmetric_keys/pkcs7_parser.o CC arch/x86/pci/early.o CC arch/x86/events/intel/knc.o CC sound/core/device.o CC security/keys/request_key_auth.o AR lib/zlib_deflate/built-in.a CC block/bio.o CC sound/core/info.o CC arch/x86/events/intel/lbr.o CC sound/core/isadma.o CC lib/crypto/mpi/generic_mpih-rshift.o CC drivers/acpi/acpica/dspkginit.o CC arch/x86/lib/cache-smp.o CC security/lsm_syscalls.o CC arch/x86/kernel/fpu/xstate.o CC arch/x86/events/zhaoxin/core.o CC arch/x86/events/core.o AR drivers/pci/pcie/built-in.a CC drivers/video/hdmi.o CC arch/x86/events/probe.o CC drivers/pci/hotplug/pci_hotplug_core.o CC arch/x86/lib/msr.o AS arch/x86/lib/msr-reg.o CC [M] sound/pci/hda/patch_hdmi.o CC arch/x86/events/utils.o AR lib/lz4/built-in.a CC crypto/scatterwalk.o CC block/elevator.o AR fs/notify/built-in.a CC fs/iomap/trace.o CC fs/iomap/iter.o CC io_uring/tctx.o CC mm/page-writeback.o CC fs/iomap/buffered-io.o CC drivers/pci/hotplug/acpi_pcihp.o CC arch/x86/mm/extable.o CC drivers/acpi/acpica/dsutils.o CC drivers/acpi/acpica/dswexec.o AR crypto/asymmetric_keys/built-in.a CC arch/x86/lib/msr-reg-export.o CC lib/zstd/zstd_decompress_module.o CC sound/core/seq/seq_fifo.o CC crypto/proc.o CC io_uring/filetable.o CC sound/core/vmaster.o AR drivers/pci/controller/dwc/built-in.a CC arch/x86/pci/bus_numa.o CC crypto/aead.o CC security/keys/user_defined.o AR drivers/pci/switch/built-in.a AR drivers/pci/controller/mobiveil/built-in.a CC lib/crypto/mpi/generic_mpih-sub1.o CC lib/crypto/mpi/generic_mpih-add1.o AR drivers/pci/controller/built-in.a CC security/keys/proc.o CC fs/quota/dquot.o CC drivers/acpi/acpica/dswload.o CC lib/xz/xz_dec_syms.o AR arch/x86/platform/efi/built-in.a AR arch/x86/platform/iris/built-in.a CC arch/x86/platform/intel/iosf_mbi.o CC lib/xz/xz_dec_stream.o AS arch/x86/entry/thunk.o CC fs/iomap/direct-io.o CC arch/x86/events/intel/p4.o CC lib/zstd/decompress/huf_decompress.o AR arch/x86/entry/built-in.a CC fs/proc/task_mmu.o CC security/keys/sysctl.o AS arch/x86/lib/hweight.o CC fs/proc/inode.o CC kernel/locking/mutex.o AR arch/x86/events/zhaoxin/built-in.a AR drivers/video/built-in.a CC drivers/acpi/acpica/dswload2.o CC security/selinux/selinuxfs.o AR arch/x86/platform/intel-mid/built-in.a AR arch/x86/platform/intel-quark/built-in.a CC kernel/power/qos.o CC security/keys/keyctl_pkey.o AR arch/x86/platform/olpc/built-in.a CC security/min_addr.o CC arch/x86/lib/iomem.o CC kernel/power/main.o AR sound/pci/nm256/built-in.a AR sound/pci/oxygen/built-in.a CC drivers/acpi/acpica/dswscope.o CC sound/core/seq/seq_prioq.o AR sound/pci/pcxhr/built-in.a CC kernel/power/console.o CC arch/x86/events/rapl.o AR drivers/pci/hotplug/built-in.a CC arch/x86/events/msr.o CC drivers/pci/access.o CC lib/crypto/mpi/ec.o CC fs/iomap/fiemap.o AR sound/pci/riptide/built-in.a CC fs/proc/root.o CC kernel/printk/printk.o CC arch/x86/pci/amd_bus.o CC kernel/printk/conopt.o AR arch/x86/kernel/fpu/built-in.a CC fs/proc/base.o CC arch/x86/kernel/cpu/mce/core.o CC fs/proc/generic.o CC lib/xz/xz_dec_lzma2.o CC arch/x86/mm/mmap.o CC arch/x86/kernel/cpu/mce/severity.o CC fs/iomap/seek.o CC crypto/geniv.o CC arch/x86/kernel/cpu/mtrr/mtrr.o CC io_uring/rw.o CC arch/x86/lib/atomic64_32.o CC arch/x86/kernel/cpu/mtrr/if.o CC lib/crypto/mpi/mpicoder.o CC drivers/acpi/acpica/dswstate.o CC block/blk-core.o AR arch/x86/platform/intel/built-in.a CC arch/x86/lib/inat.o AR arch/x86/platform/scx200/built-in.a AR arch/x86/platform/ts5500/built-in.a AR arch/x86/platform/uv/built-in.a AR arch/x86/platform/built-in.a CC arch/x86/mm/pgtable.o AR security/keys/built-in.a CC kernel/irq/irqdesc.o AR sound/pci/rme9652/built-in.a CC kernel/power/process.o CC lib/zstd/decompress/zstd_ddict.o CC kernel/power/suspend.o AR arch/x86/lib/built-in.a AR arch/x86/lib/lib.a CC kernel/irq/handle.o CC sound/core/seq/seq_timer.o CC kernel/locking/semaphore.o CC fs/quota/quota_v2.o CC arch/x86/events/intel/p6.o CC sound/core/ctljack.o CC lib/zstd/decompress/zstd_decompress.o CC crypto/lskcipher.o CC drivers/acpi/acpica/evevent.o CC fs/kernfs/mount.o CC drivers/acpi/acpica/evgpe.o CC arch/x86/mm/physaddr.o CC kernel/printk/printk_safe.o CC fs/proc/array.o CC drivers/acpi/acpica/evgpeblk.o CC fs/proc/fd.o CC drivers/pci/bus.o AR arch/x86/pci/built-in.a CC lib/xz/xz_dec_bcj.o CC net/core/stream.o CC fs/iomap/swapfile.o CC security/security.o CC [M] sound/pci/hda/hda_eld.o CC fs/sysfs/file.o CC net/core/scm.o CC fs/sysfs/dir.o CC fs/sysfs/symlink.o CC kernel/power/hibernate.o CC arch/x86/kernel/cpu/mtrr/generic.o CC fs/sysfs/mount.o CC lib/crypto/mpi/mpi-add.o CC net/core/gen_stats.o CC lib/zstd/decompress/zstd_decompress_block.o CC arch/x86/kernel/cpu/mtrr/cleanup.o CC fs/proc/proc_tty.o CC security/lsm_audit.o CC kernel/irq/manage.o CC mm/folio-compat.o CC fs/sysfs/group.o CC crypto/skcipher.o CC io_uring/net.o CC drivers/acpi/acpica/evgpeinit.o CC sound/core/seq/seq_system.o CC arch/x86/mm/tlb.o CC sound/core/jack.o AR lib/xz/built-in.a CC kernel/locking/rwsem.o CC sound/core/timer.o CC io_uring/poll.o CC arch/x86/events/intel/pt.o CC kernel/rcu/update.o CC lib/zstd/zstd_common_module.o CC fs/quota/quota_tree.o CC kernel/rcu/sync.o CC fs/kernfs/inode.o CC security/selinux/netlink.o CC sound/core/hrtimer.o CC drivers/pci/probe.o AR fs/iomap/built-in.a AR sound/pci/trident/built-in.a AR kernel/sched/built-in.a CC drivers/acpi/acpica/evgpeutil.o AR sound/pci/ymfpci/built-in.a AR kernel/livepatch/built-in.a CC fs/quota/quota.o CC fs/quota/kqid.o CC kernel/dma/mapping.o CC kernel/locking/percpu-rwsem.o CC kernel/dma/direct.o CC io_uring/uring_cmd.o CC kernel/power/snapshot.o CC drivers/pci/host-bridge.o CC fs/devpts/inode.o CC lib/crypto/mpi/mpi-bit.o CC fs/proc/cmdline.o CC [M] sound/pci/hda/hda_intel.o CC kernel/entry/common.o CC kernel/module/main.o AR fs/sysfs/built-in.a CC arch/x86/kernel/cpu/mce/genpool.o CC mm/readahead.o CC fs/netfs/buffered_read.o CC kernel/module/strict_rwx.o CC fs/netfs/buffered_write.o CC fs/proc/consoles.o CC sound/core/seq/seq_ports.o CC arch/x86/kernel/cpu/mtrr/amd.o CC lib/crypto/gf128mul.o CC fs/ext4/balloc.o CC kernel/printk/nbcon.o CC drivers/acpi/acpica/evglock.o CC lib/crypto/blake2s.o CC kernel/entry/syscall_user_dispatch.o CC block/blk-sysfs.o CC drivers/acpi/dptf/int340x_thermal.o CC drivers/acpi/x86/apple.o CC kernel/time/time.o CC kernel/locking/spinlock.o CC kernel/time/timer.o CC fs/kernfs/dir.o CC arch/x86/mm/cpu_entry_area.o CC security/selinux/nlmsgtab.o CC crypto/seqiv.o CC sound/core/seq_device.o CC kernel/dma/ops_helpers.o CC kernel/locking/osq_lock.o CC kernel/rcu/srcutree.o CC crypto/echainiv.o CC drivers/acpi/acpica/evhandler.o CC kernel/printk/printk_ringbuffer.o CC lib/crypto/mpi/mpi-cmp.o CC crypto/ahash.o CC arch/x86/kernel/cpu/mce/intel.o CC fs/proc/cpuinfo.o CC kernel/irq/spurious.o AR fs/devpts/built-in.a CC arch/x86/kernel/cpu/mtrr/cyrix.o CC kernel/irq/resend.o CC kernel/module/kmod.o CC arch/x86/events/intel/uncore.o CC drivers/acpi/tables.o CC kernel/locking/qspinlock.o AR drivers/acpi/dptf/built-in.a CC kernel/irq/chip.o CC arch/x86/mm/maccess.o CC fs/proc/devices.o CC arch/x86/kernel/cpu/mtrr/centaur.o CC security/selinux/netif.o CC drivers/acpi/x86/cmos_rtc.o CC sound/core/seq/seq_info.o CC fs/quota/netlink.o CC drivers/acpi/acpica/evmisc.o AR kernel/entry/built-in.a CC drivers/acpi/x86/lpss.o CC mm/swap.o CC kernel/futex/core.o CC arch/x86/mm/pgprot.o CC net/core/gen_estimator.o CC kernel/cgroup/cgroup.o CC arch/x86/mm/pgtable_32.o CC security/selinux/netnode.o CC arch/x86/kernel/cpu/microcode/core.o CC arch/x86/kernel/cpu/cacheinfo.o CC kernel/dma/dummy.o CC kernel/printk/sysctl.o CC io_uring/openclose.o CC lib/zstd/common/debug.o CC lib/crypto/mpi/mpi-sub-ui.o CC lib/crypto/mpi/mpi-div.o CC arch/x86/kernel/cpu/mce/amd.o CC arch/x86/kernel/cpu/mce/threshold.o CC lib/crypto/mpi/mpi-inv.o CC fs/netfs/direct_read.o CC fs/kernfs/file.o CC kernel/locking/rtmutex_api.o CC kernel/locking/qrwlock.o CC lib/zstd/common/entropy_common.o CC drivers/pci/remove.o CC block/blk-flush.o CC kernel/time/hrtimer.o AR kernel/printk/built-in.a CC arch/x86/kernel/cpu/mtrr/legacy.o CC security/selinux/netport.o CC kernel/trace/trace_clock.o CC drivers/acpi/acpica/evregion.o CC lib/zstd/common/error_private.o CC kernel/power/swap.o LD [M] sound/pci/hda/snd-hda-codec.o LD [M] sound/pci/hda/snd-hda-codec-hdmi.o LD [M] sound/pci/hda/snd-hda-intel.o CC fs/proc/interrupts.o CC lib/zstd/common/fse_decompress.o AR sound/pci/vx222/built-in.a AR sound/pci/built-in.a CC kernel/trace/ring_buffer.o CC fs/ext4/bitmap.o CC sound/core/seq/seq_dummy.o CC kernel/dma/remap.o CC kernel/irq/dummychip.o CC fs/proc/loadavg.o CC crypto/shash.o CC fs/kernfs/symlink.o CC fs/proc/meminfo.o CC security/selinux/status.o CC kernel/module/tree_lookup.o CC kernel/rcu/tree.o CC kernel/rcu/rcu_segcblist.o AR arch/x86/kernel/cpu/mtrr/built-in.a CC drivers/acpi/x86/s2idle.o CC kernel/power/user.o CC lib/crypto/blake2s-generic.o AR fs/quota/built-in.a AR sound/sh/built-in.a CC arch/x86/mm/iomap_32.o CC arch/x86/mm/hugetlbpage.o CC kernel/module/kallsyms.o CC kernel/trace/trace.o CC lib/crypto/sha1.o CC arch/x86/kernel/cpu/microcode/intel.o CC lib/crypto/mpi/mpi-mod.o CC drivers/acpi/acpica/evrgnini.o CC kernel/futex/syscalls.o CC drivers/pci/pci.o CC security/device_cgroup.o CC io_uring/sqpoll.o CC lib/zstd/common/zstd_common.o CC arch/x86/kernel/cpu/microcode/amd.o CC kernel/irq/devres.o CC net/core/net_namespace.o CC fs/netfs/direct_write.o AR lib/zstd/built-in.a AR sound/core/seq/built-in.a AR kernel/dma/built-in.a CC lib/dim/dim.o CC [M] sound/core/hwdep.o CC kernel/bpf/core.o CC lib/dim/net_dim.o CC kernel/events/core.o CC block/blk-settings.o AR kernel/locking/built-in.a CC kernel/events/ring_buffer.o CC kernel/fork.o CC kernel/events/callchain.o CC drivers/pci/pci-driver.o CC kernel/power/poweroff.o CC kernel/events/hw_breakpoint.o CC arch/x86/events/intel/uncore_nhmex.o CC kernel/events/uprobes.o CC fs/ext4/block_validity.o CC drivers/pnp/pnpacpi/core.o CC drivers/pnp/core.o CC drivers/pnp/pnpacpi/rsparser.o CC drivers/acpi/acpica/evsci.o AR fs/kernfs/built-in.a CC fs/proc/stat.o CC drivers/acpi/acpica/evxface.o CC block/blk-ioc.o CC fs/proc/uptime.o CC arch/x86/mm/dump_pagetables.o CC mm/truncate.o CC lib/crypto/mpi/mpi-mul.o CC fs/jbd2/transaction.o CC crypto/akcipher.o CC fs/jbd2/commit.o CC kernel/irq/autoprobe.o CC kernel/module/procfs.o CC fs/netfs/io.o CC fs/ramfs/inode.o CC lib/dim/rdma_dim.o CC fs/hugetlbfs/inode.o CC drivers/acpi/x86/utils.o CC drivers/acpi/x86/blacklist.o AR kernel/power/built-in.a AR arch/x86/kernel/cpu/mce/built-in.a CC arch/x86/mm/highmem_32.o CC security/selinux/ss/ebitmap.o CC net/core/secure_seq.o CC kernel/futex/pi.o CC kernel/time/timekeeping.o CC [M] sound/core/pcm.o AR arch/x86/kernel/cpu/microcode/built-in.a CC arch/x86/kernel/cpu/scattered.o CC drivers/acpi/acpica/evxfevnt.o CC fs/ext4/dir.o CC io_uring/xattr.o AR sound/synth/emux/built-in.a CC fs/proc/util.o AR sound/synth/built-in.a AR lib/dim/built-in.a CC fs/proc/version.o AR sound/usb/misc/built-in.a CC kernel/exec_domain.o AR sound/usb/usx2y/built-in.a CC kernel/irq/irqdomain.o AR sound/usb/caiaq/built-in.a CC kernel/panic.o CC fs/ext4/ext4_jbd2.o CC lib/crypto/mpi/mpih-cmp.o AR sound/usb/6fire/built-in.a AR sound/usb/hiface/built-in.a AR sound/usb/bcd2000/built-in.a CC net/sched/sch_generic.o AR sound/usb/built-in.a CC kernel/module/sysfs.o CC net/sched/sch_mq.o CC net/sched/sch_frag.o AR sound/firewire/built-in.a CC fs/ext4/extents.o CC net/sched/sch_api.o AR drivers/acpi/x86/built-in.a CC block/blk-map.o CC drivers/acpi/osi.o AR drivers/pnp/pnpacpi/built-in.a CC block/blk-merge.o CC drivers/pnp/card.o CC drivers/acpi/acpica/evxfgpe.o CC arch/x86/kernel/cpu/topology_common.o CC fs/ramfs/file-mmu.o AR arch/x86/mm/built-in.a CC io_uring/nop.o CC crypto/sig.o CC fs/ext4/extents_status.o CC arch/x86/events/intel/uncore_snb.o CC mm/vmscan.o CC net/core/flow_dissector.o CC net/netlink/af_netlink.o CC drivers/pci/search.o CC fs/proc/softirqs.o CC net/netlink/genetlink.o CC kernel/futex/requeue.o CC lib/crypto/mpi/mpih-div.o CC fs/netfs/iterator.o CC kernel/cpu.o CC lib/crypto/mpi/mpih-mul.o CC drivers/acpi/acpica/evxfregn.o CC drivers/pci/rom.o CC [M] sound/core/pcm_native.o CC arch/x86/kernel/cpu/topology_ext.o CC net/sched/sch_blackhole.o AR kernel/module/built-in.a CC crypto/kpp.o CC kernel/exit.o CC io_uring/fs.o CC fs/jbd2/recovery.o AR fs/hugetlbfs/built-in.a CC drivers/acpi/acpica/exconcat.o CC fs/fat/cache.o CC drivers/pnp/driver.o CC security/selinux/ss/hashtab.o AR fs/ramfs/built-in.a CC fs/fat/dir.o CC fs/proc/namespaces.o CC fs/isofs/namei.o CC net/netlink/policy.o CC kernel/softirq.o CC io_uring/splice.o CC kernel/irq/proc.o CC net/core/sysctl_net_core.o ASN.1 crypto/rsapubkey.asn1.[ch] ASN.1 crypto/rsaprivkey.asn1.[ch] CC fs/ext4/file.o CC kernel/irq/migration.o CC kernel/futex/waitwake.o CC arch/x86/kernel/cpu/topology_amd.o CC kernel/time/ntp.o CC drivers/acpi/acpica/exconfig.o AR sound/sparc/built-in.a CC drivers/acpi/acpica/exconvrt.o CC net/sched/cls_api.o CC arch/x86/events/intel/uncore_snbep.o CC security/selinux/ss/symtab.o CC net/sched/act_api.o CC drivers/pci/setup-res.o CC kernel/trace/trace_output.o CC drivers/pnp/resource.o CC lib/crypto/mpi/mpi-pow.o CC kernel/resource.o CC security/selinux/ss/sidtab.o CC crypto/rsa.o CC block/blk-timeout.o CC arch/x86/kernel/cpu/common.o CC block/blk-lib.o CC fs/isofs/inode.o CC crypto/rsa_helper.o CC kernel/sysctl.o CC fs/proc/self.o CC drivers/acpi/acpica/excreate.o AR sound/spi/built-in.a CC fs/netfs/locking.o CC io_uring/sync.o CC io_uring/msg_ring.o AR kernel/bpf/built-in.a CC kernel/irq/cpuhotplug.o AR sound/parisc/built-in.a CC crypto/rsa-pkcs1pad.o AR sound/pcmcia/vx/built-in.a AR sound/pcmcia/pdaudiocf/built-in.a AR sound/pcmcia/built-in.a AR sound/mips/built-in.a CC fs/fat/fatent.o CC fs/jbd2/checkpoint.o AR kernel/futex/built-in.a CC kernel/trace/trace_seq.o CC fs/jbd2/revoke.o CC kernel/trace/trace_stat.o CC mm/shrinker.o CC arch/x86/kernel/cpu/rdrand.o CC kernel/time/clocksource.o CC kernel/cgroup/rstat.o AR drivers/amba/built-in.a CC fs/jbd2/journal.o AR drivers/clk/actions/built-in.a CC kernel/trace/trace_printk.o CC drivers/acpi/acpica/exdebug.o AR drivers/clk/analogbits/built-in.a CC lib/crypto/mpi/mpiutil.o AR drivers/clk/bcm/built-in.a CC drivers/pci/irq.o AR drivers/clk/imgtec/built-in.a CC drivers/pci/vpd.o AR drivers/clk/imx/built-in.a AR drivers/clk/ingenic/built-in.a AR drivers/clk/mediatek/built-in.a AR drivers/clk/microchip/built-in.a CC drivers/pci/setup-bus.o AR drivers/clk/mstar/built-in.a CC fs/proc/thread_self.o CC block/blk-mq.o AR drivers/clk/mvebu/built-in.a CC kernel/cgroup/namespace.o AR drivers/clk/ralink/built-in.a AR drivers/clk/renesas/built-in.a CC block/blk-mq-tag.o CC block/blk-stat.o AR drivers/clk/socfpga/built-in.a CC net/core/dev.o AR drivers/clk/sophgo/built-in.a CC arch/x86/kernel/acpi/boot.o AR drivers/clk/sprd/built-in.a AR drivers/clk/starfive/built-in.a AR drivers/clk/sunxi-ng/built-in.a AR drivers/clk/ti/built-in.a AR drivers/clk/versatile/built-in.a AR drivers/clk/xilinx/built-in.a AR drivers/clk/built-in.a CC drivers/pci/vc.o CC drivers/pnp/manager.o CC kernel/irq/pm.o CC drivers/pci/mmap.o CC drivers/pci/devres.o CC drivers/acpi/acpica/exdump.o AR kernel/rcu/built-in.a CC arch/x86/kernel/apic/apic.o CC crypto/acompress.o CC crypto/scompress.o CC kernel/cgroup/cgroup-v1.o CC fs/netfs/main.o CC drivers/pci/proc.o AR net/bpf/built-in.a CC io_uring/advise.o CC fs/proc/proc_sysctl.o CC arch/x86/kernel/cpu/match.o CC drivers/acpi/acpica/exfield.o CC security/selinux/ss/avtab.o AR net/netlink/built-in.a CC security/selinux/ss/policydb.o AR lib/crypto/mpi/built-in.a CC security/selinux/ss/services.o CC drivers/pci/pci-sysfs.o CC net/ethtool/ioctl.o CC lib/crypto/sha256.o CC drivers/pci/slot.o CC fs/isofs/dir.o CC security/selinux/ss/conditional.o CC io_uring/epoll.o CC kernel/time/jiffies.o CC kernel/trace/pid_list.o CC fs/fat/file.o CC drivers/acpi/acpica/exfldio.o CC fs/proc/proc_net.o CC fs/netfs/misc.o CC drivers/pnp/support.o CC mm/shmem.o CC [M] sound/core/pcm_lib.o CC arch/x86/events/intel/uncore_discovery.o CC kernel/trace/trace_sched_switch.o CC arch/x86/kernel/cpu/bugs.o CC [M] sound/core/pcm_misc.o CC drivers/acpi/acpica/exmisc.o CC kernel/trace/trace_nop.o CC fs/netfs/objects.o CC [M] sound/core/pcm_memory.o CC fs/netfs/write_collect.o CC kernel/irq/msi.o CC fs/nfs/client.o CC kernel/time/timer_list.o CC crypto/algboss.o CC fs/exportfs/expfs.o CC arch/x86/events/intel/cstate.o AR lib/crypto/built-in.a CC lib/fonts/fonts.o CC fs/isofs/util.o CC arch/x86/kernel/acpi/sleep.o CC net/core/dev_addr_lists.o CC net/ethtool/common.o CC drivers/pnp/interface.o CC net/core/dst.o AS arch/x86/kernel/acpi/wakeup_32.o CC drivers/acpi/acpica/exmutex.o CC security/selinux/ss/mls.o CC lib/argv_split.o CC fs/lockd/clntlock.o CC io_uring/statx.o CC fs/lockd/clntproc.o CC fs/nfs/dir.o CC net/sched/sch_fifo.o CC lib/fonts/font_8x16.o CC net/core/netevent.o CC fs/netfs/write_issue.o CC kernel/trace/blktrace.o CC arch/x86/kernel/cpu/aperfmperf.o CC fs/fat/inode.o CC fs/fat/misc.o CC drivers/pci/pci-acpi.o CC drivers/acpi/acpica/exnames.o CC kernel/cgroup/freezer.o AR fs/exportfs/built-in.a CC kernel/time/timeconv.o CC fs/nfs/file.o CC kernel/time/timecounter.o CC fs/isofs/rock.o CC net/core/neighbour.o CC drivers/pci/iomap.o CC net/sched/cls_cgroup.o CC drivers/pnp/quirks.o CC fs/proc/kcore.o CC arch/x86/kernel/acpi/cstate.o AR lib/fonts/built-in.a CC lib/bug.o CC fs/ext4/fsmap.o CC kernel/capability.o AR arch/x86/events/intel/built-in.a CC fs/ext4/fsync.o CC crypto/testmgr.o AR arch/x86/events/built-in.a CC fs/ext4/hash.o CC kernel/irq/affinity.o CC arch/x86/kernel/apic/apic_common.o CC drivers/acpi/acpica/exoparg1.o CC kernel/time/alarmtimer.o CC crypto/cmac.o CC net/ethtool/netlink.o CC io_uring/timeout.o CC io_uring/fdinfo.o AR fs/jbd2/built-in.a CC io_uring/cancel.o CC kernel/trace/trace_events.o AR sound/soc/built-in.a CC kernel/trace/trace_export.o CC [M] sound/core/memalloc.o CC arch/x86/kernel/cpu/cpuid-deps.o CC drivers/acpi/osl.o AR arch/x86/kernel/acpi/built-in.a CC security/selinux/ss/context.o CC fs/nfs/getroot.o CC fs/fat/nfs.o CC drivers/pci/quirks.o CC [M] sound/core/pcm_timer.o AR kernel/events/built-in.a CC kernel/irq/matrix.o AR sound/atmel/built-in.a CC fs/proc/vmcore.o CC fs/proc/kmsg.o CC fs/lockd/clntxdr.o CC arch/x86/kernel/apic/apic_noop.o CC lib/buildid.o CC fs/lockd/host.o CC drivers/acpi/acpica/exoparg2.o CC fs/lockd/svc.o CC drivers/pnp/system.o CC crypto/hmac.o CC fs/isofs/export.o CC kernel/cgroup/legacy_freezer.o CC drivers/pci/pci-label.o CC arch/x86/kernel/cpu/umwait.o CC net/core/rtnetlink.o AR fs/netfs/built-in.a CC kernel/ptrace.o CC fs/nls/nls_base.o CC fs/ext4/ialloc.o CC net/ethtool/bitset.o CC fs/lockd/svclock.o CC fs/nls/nls_cp437.o CC fs/proc/page.o CC net/sched/ematch.o CC arch/x86/kernel/apic/ipi.o CC fs/fat/namei_vfat.o LD [M] sound/core/snd-hwdep.o CC drivers/acpi/acpica/exoparg3.o CC kernel/time/posix-timers.o AR drivers/pnp/built-in.a CC mm/util.o CC fs/nls/nls_ascii.o CC drivers/dma/dw/core.o AR drivers/soc/apple/built-in.a CC lib/clz_tab.o CC drivers/dma/dw/dw.o AR drivers/soc/aspeed/built-in.a AR drivers/soc/bcm/built-in.a CC lib/cmdline.o AR drivers/soc/fsl/built-in.a AR drivers/soc/fujitsu/built-in.a AR drivers/soc/hisilicon/built-in.a AR drivers/soc/imx/built-in.a AR sound/core/built-in.a CC io_uring/waitid.o AR drivers/soc/ixp4xx/built-in.a LD [M] sound/core/snd-pcm.o AR drivers/soc/loongson/built-in.a CC drivers/virtio/virtio.o CC fs/isofs/joliet.o AR sound/hda/built-in.a CC drivers/dma/hsu/hsu.o AR drivers/soc/mediatek/built-in.a AR drivers/soc/microchip/built-in.a CC [M] sound/hda/hda_bus_type.o CC kernel/trace/trace_event_perf.o CC crypto/crypto_null.o CC fs/nls/nls_iso8859-1.o CC drivers/pci/vgaarb.o AR drivers/soc/nuvoton/built-in.a CC lib/cpumask.o CC kernel/cgroup/pids.o AR drivers/soc/pxa/built-in.a CC security/selinux/netlabel.o AR drivers/soc/amlogic/built-in.a CC kernel/time/posix-cpu-timers.o AR drivers/soc/qcom/built-in.a CC kernel/trace/trace_events_filter.o AR drivers/soc/renesas/built-in.a CC drivers/acpi/acpica/exoparg6.o MKCAP arch/x86/kernel/cpu/capflags.c CC [M] sound/hda/hdac_bus.o CC arch/x86/kernel/apic/vector.o AR drivers/soc/rockchip/built-in.a AR drivers/soc/sunxi/built-in.a AR drivers/soc/ti/built-in.a AR drivers/soc/xilinx/built-in.a AR drivers/soc/built-in.a CC block/blk-mq-sysfs.o CC net/ethtool/strset.o CC kernel/time/posix-clock.o CC [M] sound/hda/hdac_device.o CC kernel/time/itimer.o CC fs/fat/namei_msdos.o CC fs/lockd/svcshare.o AR fs/proc/built-in.a CC fs/nls/nls_utf8.o AR fs/unicode/built-in.a CC fs/ext4/indirect.o CC crypto/md5.o CC fs/lockd/svcproc.o CC drivers/virtio/virtio_ring.o CC drivers/dma/dw/idma32.o CC drivers/acpi/acpica/exprep.o AR kernel/irq/built-in.a CC fs/ext4/inline.o CC fs/ext4/inode.o CC fs/nfs/inode.o CC fs/isofs/compress.o CC lib/ctype.o CC drivers/acpi/utils.o CC kernel/cgroup/rdma.o CC lib/dec_and_lock.o CC [M] sound/hda/hdac_sysfs.o CC kernel/user.o AR net/sched/built-in.a CC kernel/cgroup/cpuset.o AR fs/nls/built-in.a CC net/ethtool/linkinfo.o CC arch/x86/kernel/cpu/powerflags.o CC block/blk-mq-cpumap.o CC io_uring/register.o AR drivers/dma/hsu/built-in.a CC mm/mmzone.o AR drivers/dma/idxd/built-in.a CC lib/decompress.o CC crypto/sha256_generic.o CC fs/nfs/super.o CC io_uring/truncate.o CC net/ethtool/linkmodes.o CC lib/decompress_bunzip2.o CC mm/vmstat.o CC drivers/acpi/acpica/exregion.o CC drivers/acpi/acpica/exresnte.o CC kernel/trace/trace_events_trigger.o CC kernel/trace/trace_eprobe.o CC kernel/cgroup/misc.o CC kernel/cgroup/debug.o CC mm/backing-dev.o CC mm/mm_init.o CC block/blk-mq-sched.o AR fs/fat/built-in.a CC block/ioctl.o AR drivers/pci/built-in.a CC net/netfilter/core.o CC block/genhd.o CC block/ioprio.o CC drivers/dma/dw/acpi.o CC kernel/time/clockevents.o CC net/ipv4/netfilter/nf_defrag_ipv4.o CC net/ipv4/route.o CC net/xfrm/xfrm_policy.o CC net/ipv4/inetpeer.o CC net/ethtool/rss.o AR security/selinux/built-in.a AR security/built-in.a CC net/ipv4/protocol.o CC drivers/acpi/acpica/exresolv.o CC net/unix/af_unix.o CC net/xfrm/xfrm_state.o CC net/ipv6/netfilter/ip6_tables.o CC net/ipv6/af_inet6.o CC crypto/sha512_generic.o CC [M] sound/hda/hdac_regmap.o CC net/ipv6/anycast.o AR fs/isofs/built-in.a CC drivers/virtio/virtio_anchor.o CC block/badblocks.o CC fs/lockd/svcsubs.o CC net/ipv6/netfilter/ip6table_filter.o CC lib/decompress_inflate.o CC net/ethtool/linkstate.o CC arch/x86/kernel/apic/init.o CC drivers/acpi/acpica/exresop.o CC fs/nfs/io.o CC drivers/acpi/acpica/exserial.o CC kernel/time/tick-common.o AR drivers/dma/dw/built-in.a AR drivers/dma/mediatek/built-in.a CC fs/nfs/direct.o AR drivers/dma/qcom/built-in.a AR drivers/dma/ti/built-in.a AR drivers/dma/xilinx/built-in.a CC net/ipv6/ip6_output.o CC drivers/dma/dmaengine.o CC net/ipv6/ip6_input.o CC kernel/signal.o CC drivers/dma/virt-dma.o CC net/ipv4/ip_input.o CC drivers/virtio/virtio_pci_modern_dev.o CC lib/decompress_unlz4.o CC net/ipv4/netfilter/nf_reject_ipv4.o CC arch/x86/kernel/apic/hw_nmi.o CC net/ipv4/netfilter/ip_tables.o CC net/ipv4/netfilter/iptable_filter.o CC kernel/trace/trace_kprobe.o CC drivers/acpi/acpica/exstore.o CC net/ipv4/netfilter/iptable_mangle.o CC kernel/trace/error_report-traces.o CC kernel/trace/power-traces.o CC net/ipv4/ip_fragment.o CC [M] sound/hda/hdac_controller.o CC net/ipv6/addrconf.o CC drivers/dma/acpi-dma.o CC mm/percpu.o CC crypto/sha3_generic.o CC block/blk-rq-qos.o CC io_uring/memmap.o CC io_uring/io-wq.o CC [M] sound/hda/hdac_stream.o CC net/netfilter/nf_log.o CC block/disk-events.o CC drivers/acpi/acpica/exstoren.o CC lib/decompress_unlzma.o CC fs/lockd/mon.o CC net/ethtool/debug.o CC net/ethtool/wol.o CC net/ipv6/netfilter/ip6table_mangle.o CC net/netfilter/nf_queue.o CC arch/x86/kernel/apic/io_apic.o AR kernel/cgroup/built-in.a CC net/ipv6/addrlabel.o CC net/ipv4/ip_forward.o CC crypto/ecb.o CC drivers/virtio/virtio_pci_legacy_dev.o CC kernel/time/tick-broadcast.o CC net/ipv6/route.o CC net/ipv6/ip6_fib.o CC net/packet/af_packet.o AR net/dsa/built-in.a CC drivers/acpi/acpica/exstorob.o CC fs/lockd/trace.o CC net/sunrpc/auth_gss/auth_gss.o CC net/core/utils.o AR drivers/dma/built-in.a CC net/sunrpc/auth_gss/gss_generic_token.o CC lib/decompress_unlzo.o CC drivers/tty/vt/vt_ioctl.o CC block/blk-ia-ranges.o CC drivers/tty/hvc/hvc_console.o CC net/ipv4/netfilter/ipt_REJECT.o CC crypto/cbc.o CC net/core/link_watch.o CC kernel/trace/rpm-traces.o CC drivers/acpi/acpica/exsystem.o CC net/ethtool/features.o CC net/ipv4/ip_options.o CC block/early-lookup.o CC [M] sound/hda/array.o CC drivers/tty/vt/vc_screen.o CC drivers/virtio/virtio_pci_modern.o CC [M] net/ipv4/netfilter/iptable_nat.o CC kernel/time/tick-broadcast-hrtimer.o CC net/unix/garbage.o CC net/xfrm/xfrm_hash.o CC net/ipv4/ip_output.o CC kernel/time/tick-oneshot.o CC drivers/virtio/virtio_pci_common.o CC lib/decompress_unxz.o CC drivers/acpi/acpica/extrace.o CC fs/lockd/xdr.o CC crypto/ctr.o CC net/sunrpc/auth_gss/gss_mech_switch.o CC io_uring/futex.o CC io_uring/napi.o CC mm/slab_common.o CC net/ipv6/netfilter/nf_defrag_ipv6_hooks.o CC net/ipv4/ip_sockglue.o CC block/bounce.o CC net/netfilter/nf_sockopt.o CC fs/lockd/clnt4xdr.o CC kernel/time/tick-sched.o CC net/xfrm/xfrm_input.o AR drivers/tty/hvc/built-in.a CC fs/nfs/pagelist.o CC fs/nfs/read.o CC drivers/tty/serial/8250/8250_core.o CC [M] sound/hda/hdmi_chmap.o CC block/bsg.o CC drivers/tty/serial/8250/8250_pnp.o CC mm/compaction.o CC drivers/acpi/acpica/exutils.o CC lib/decompress_unzstd.o CC drivers/tty/serial/8250/8250_port.o CC net/xfrm/xfrm_output.o CC mm/show_mem.o CC crypto/gcm.o CC mm/shmem_quota.o AR net/wireless/tests/built-in.a CC net/wireless/core.o CC kernel/trace/trace_dynevent.o CC drivers/tty/vt/selection.o AR net/mac80211/tests/built-in.a CC arch/x86/kernel/apic/msi.o CC net/mac80211/main.o CC net/core/filter.o CC lib/dump_stack.o CC drivers/virtio/virtio_pci_legacy.o CC net/ethtool/privflags.o CC fs/autofs/init.o CC drivers/acpi/acpica/hwacpi.o CC fs/autofs/inode.o AR net/ipv4/netfilter/built-in.a CC net/unix/sysctl_net_unix.o CC net/ipv4/inet_hashtables.o CC fs/autofs/root.o CC mm/interval_tree.o CC fs/autofs/symlink.o CC drivers/tty/serial/8250/8250_dma.o CC [M] sound/hda/trace.o CC block/blk-cgroup.o CC fs/ext4/ioctl.o CC net/netfilter/utils.o CC drivers/acpi/acpica/hwesleep.o CC net/ethtool/rings.o CC net/ethtool/channels.o CC mm/list_lru.o CC lib/earlycpio.o CC fs/lockd/xdr4.o CC drivers/virtio/virtio_pci_admin_legacy_io.o CC drivers/tty/vt/keyboard.o CC lib/extable.o CC arch/x86/kernel/apic/probe_32.o CC kernel/time/timer_migration.o CC net/netfilter/nfnetlink.o CC kernel/trace/trace_probe.o CC net/ipv6/netfilter/nf_conntrack_reasm.o CC net/ipv6/netfilter/nf_reject_ipv6.o CC mm/workingset.o CC net/sunrpc/auth_gss/svcauth_gss.o CC kernel/trace/trace_uprobe.o CC crypto/ccm.o CC kernel/trace/rethook.o AR io_uring/built-in.a CC drivers/tty/vt/vt.o CC drivers/acpi/acpica/hwgpe.o CC net/ethtool/coalesce.o CC arch/x86/kernel/cpu/topology.o CC net/netfilter/nfnetlink_log.o CC fs/ext4/mballoc.o CC net/ipv6/ipv6_sockglue.o CC fs/ext4/migrate.o CC lib/flex_proportions.o AR drivers/tty/ipwireless/built-in.a CC net/core/sock_diag.o CC drivers/tty/tty_io.o AR arch/x86/kernel/apic/built-in.a CC mm/debug.o CC fs/autofs/waitq.o AR net/unix/built-in.a CC net/xfrm/xfrm_sysctl.o CC arch/x86/kernel/cpu/proc.o CC net/xfrm/xfrm_replay.o CC net/netlabel/netlabel_user.o CC drivers/virtio/virtio_input.o CC drivers/tty/serial/8250/8250_dwlib.o CC net/ethtool/pause.o CC drivers/acpi/acpica/hwregs.o CC [M] sound/hda/hdac_component.o AR net/packet/built-in.a CC net/rfkill/core.o CC lib/idr.o CC net/9p/mod.o CC arch/x86/kernel/cpu/feat_ctl.o CC drivers/acpi/acpica/hwsleep.o CC net/dns_resolver/dns_key.o CC net/handshake/alert.o CC net/ipv6/ndisc.o CC crypto/aes_generic.o CC fs/nfs/symlink.o CC net/handshake/genl.o CC fs/lockd/svc4proc.o CC arch/x86/kernel/cpu/intel.o CC net/netfilter/nf_conntrack_core.o CC crypto/crc32c_generic.o CC crypto/authenc.o CC drivers/acpi/acpica/hwvalid.o CC block/blk-ioprio.o CC [M] sound/hda/hdac_i915.o CC arch/x86/kernel/cpu/intel_pconfig.o CC net/netfilter/nf_conntrack_standalone.o CC fs/autofs/expire.o CC lib/irq_regs.o CC net/9p/client.o CC drivers/virtio/virtio_dma_buf.o CC mm/gup.o COPY drivers/tty/vt/defkeymap.c CC fs/ext4/mmp.o CC net/9p/error.o CC drivers/tty/serial/8250/8250_pcilib.o CC drivers/tty/n_tty.o CC fs/autofs/dev-ioctl.o CC net/ipv6/netfilter/ip6t_ipv6header.o CC kernel/time/vsyscall.o CC net/netfilter/nf_conntrack_expect.o CC lib/is_single_threaded.o CC net/dns_resolver/dns_query.o CC net/ethtool/eee.o CC net/netlabel/netlabel_kapi.o CC net/ipv4/inet_timewait_sock.o CC net/xfrm/xfrm_device.o CC block/blk-iolatency.o CC net/core/dev_ioctl.o CC drivers/acpi/acpica/hwxface.o CC net/core/tso.o CC net/rfkill/input.o CC net/ipv6/udp.o AR kernel/trace/built-in.a CC net/xfrm/xfrm_algo.o CC crypto/authencesn.o CC drivers/acpi/acpica/hwxfsleep.o CC kernel/sys.o CC net/core/sock_reuseport.o CC net/9p/protocol.o CC kernel/time/timekeeping_debug.o CC lib/klist.o AR drivers/virtio/built-in.a CC fs/nfs/unlink.o CC [M] sound/hda/intel-dsp-config.o CC drivers/tty/tty_ioctl.o CC crypto/lzo.o CC crypto/lzo-rle.o CC drivers/tty/serial/8250/8250_early.o CC net/sunrpc/auth_gss/gss_rpc_upcall.o CC lib/kobject.o CC net/ethtool/tsinfo.o CC drivers/tty/vt/consolemap.o CC drivers/acpi/acpica/hwpci.o CC net/handshake/netlink.o CC fs/lockd/procfs.o AR net/dns_resolver/built-in.a CC arch/x86/kernel/kprobes/core.o HOSTCC drivers/tty/vt/conmakehash CC arch/x86/kernel/kprobes/opt.o CC [M] sound/hda/intel-nhlt.o CC net/mac80211/status.o CC fs/ext4/move_extent.o CC arch/x86/kernel/cpu/tsx.o AR fs/autofs/built-in.a AR net/rfkill/built-in.a CC fs/ext4/namei.o CC net/ipv6/udplite.o CC net/ipv6/netfilter/ip6t_REJECT.o CC drivers/tty/serial/serial_core.o CC net/wireless/sysfs.o CC net/9p/trans_common.o CC fs/9p/vfs_super.o CC kernel/time/namespace.o CC drivers/acpi/acpica/nsaccess.o CC fs/9p/vfs_inode.o CC arch/x86/kernel/cpu/intel_epb.o CC crypto/rng.o CC net/9p/trans_fd.o CC drivers/tty/serial/8250/8250_exar.o CC drivers/tty/serial/8250/8250_lpss.o CC drivers/tty/serial/8250/8250_mid.o CC net/ipv4/inet_connection_sock.o CC lib/kobject_uevent.o CC block/blk-iocost.o CC drivers/tty/serial/serial_base_bus.o CC net/wireless/radiotap.o CC net/netlabel/netlabel_domainhash.o CC [M] sound/hda/intel-sdw-acpi.o CC net/sunrpc/auth_gss/gss_rpc_xdr.o CC net/xfrm/xfrm_user.o AR fs/lockd/built-in.a CC drivers/tty/tty_ldisc.o AR fs/hostfs/built-in.a CC drivers/tty/tty_buffer.o CC fs/debugfs/inode.o CC net/core/fib_notifier.o CC fs/debugfs/file.o CC net/netfilter/nf_conntrack_helper.o CC drivers/acpi/acpica/nsalloc.o CC block/mq-deadline.o CC net/wireless/util.o CC drivers/tty/vt/defkeymap.o CC net/ethtool/cabletest.o CC arch/x86/kernel/cpu/amd.o CC arch/x86/kernel/cpu/hygon.o CC mm/mmap_lock.o CC fs/nfs/write.o CC net/core/xdp.o AR arch/x86/kernel/kprobes/built-in.a CONMK drivers/tty/vt/consolemap_deftbl.c CC net/sunrpc/auth_gss/trace.o CC drivers/tty/vt/consolemap_deftbl.o CC drivers/acpi/acpica/nsarguments.o CC fs/ext4/page-io.o AR drivers/tty/vt/built-in.a AR kernel/time/built-in.a CC drivers/tty/tty_port.o CC kernel/umh.o LD [M] sound/hda/snd-hda-core.o CC fs/9p/vfs_inode_dotl.o LD [M] sound/hda/snd-intel-dspcfg.o CC net/handshake/request.o CC net/core/flow_offload.o LD [M] sound/hda/snd-intel-sdw-acpi.o CC drivers/tty/serial/8250/8250_pci.o CC lib/logic_pio.o AR sound/x86/built-in.a CC drivers/tty/serial/serial_ctrl.o CC crypto/drbg.o CC fs/ext4/readpage.o AR sound/xen/built-in.a CC fs/ext4/resize.o CC net/ipv6/raw.o AR sound/virtio/built-in.a AR net/ipv6/netfilter/built-in.a CC sound/sound_core.o CC net/ipv6/icmp.o CC drivers/acpi/acpica/nsconvert.o CC net/sunrpc/auth_gss/gss_krb5_mech.o CC drivers/tty/serial/8250/8250_pericom.o CC drivers/tty/tty_mutex.o CC fs/ext4/super.o CC net/netfilter/nf_conntrack_proto.o CC net/ipv4/tcp.o LDS arch/x86/kernel/vmlinux.lds AS arch/x86/kernel/head_32.o CC arch/x86/kernel/head32.o CC net/9p/trans_virtio.o CC net/ethtool/tunnels.o CC arch/x86/kernel/ebda.o CC sound/last.o CC arch/x86/kernel/cpu/centaur.o CC kernel/workqueue.o CC mm/highmem.o CC net/netlabel/netlabel_addrlist.o CC lib/maple_tree.o CC mm/memory.o AR fs/debugfs/built-in.a CC kernel/pid.o CC drivers/acpi/acpica/nsdump.o CC drivers/tty/tty_ldsem.o CC lib/memcat_p.o CC fs/tracefs/inode.o CC drivers/tty/serial/serial_port.o CC fs/9p/vfs_addr.o CC drivers/char/hw_random/core.o AR drivers/iommu/amd/built-in.a AR drivers/iommu/intel/built-in.a CC drivers/char/hw_random/intel-rng.o CC drivers/char/agp/backend.o AR drivers/iommu/arm/arm-smmu/built-in.a CC drivers/char/agp/generic.o AR drivers/iommu/arm/arm-smmu-v3/built-in.a AR drivers/iommu/arm/built-in.a CC crypto/jitterentropy.o CC drivers/char/mem.o AR drivers/iommu/iommufd/built-in.a CC drivers/iommu/iommu.o CC crypto/jitterentropy-kcapi.o CC arch/x86/kernel/cpu/transmeta.o CC drivers/acpi/acpica/nseval.o CC drivers/iommu/iommu-traces.o AR sound/built-in.a CC drivers/char/agp/isoch.o CC lib/nmi_backtrace.o CC net/netlabel/netlabel_mgmt.o CC net/netlabel/netlabel_unlabeled.o CC net/wireless/reg.o CC arch/x86/kernel/platform-quirks.o CC net/core/gro.o CC mm/mincore.o AR drivers/tty/serial/8250/built-in.a CC drivers/tty/serial/earlycon.o CC net/handshake/tlshd.o CC drivers/tty/tty_baudrate.o CC crypto/ghash-generic.o CC drivers/acpi/acpica/nsinit.o CC net/devres.o CC net/sunrpc/auth_gss/gss_krb5_seal.o CC net/netlabel/netlabel_cipso_v4.o CC net/core/netdev-genl.o CC [M] fs/efivarfs/inode.o CC net/mac80211/driver-ops.o CC fs/tracefs/event_inode.o CC net/core/netdev-genl-gen.o CC arch/x86/kernel/cpu/zhaoxin.o CC drivers/char/hw_random/amd-rng.o CC mm/mlock.o CC fs/9p/vfs_file.o CC mm/mmap.o CC net/netfilter/nf_conntrack_proto_generic.o CC net/ipv6/mcast.o AR net/9p/built-in.a CC net/netfilter/nf_conntrack_proto_tcp.o CC drivers/char/agp/amd64-agp.o CC drivers/char/agp/intel-agp.o CC net/ethtool/fec.o CC crypto/hash_info.o CC drivers/acpi/acpica/nsload.o CC crypto/rsapubkey.asn1.o CC drivers/char/hw_random/geode-rng.o CC drivers/char/random.o CC drivers/acpi/reboot.o AR net/xfrm/built-in.a CC crypto/rsaprivkey.asn1.o CC block/kyber-iosched.o CC net/sunrpc/auth_gss/gss_krb5_unseal.o AR crypto/built-in.a CC net/netlabel/netlabel_calipso.o CC drivers/char/agp/intel-gtt.o CC net/ipv4/tcp_input.o CC drivers/char/hw_random/via-rng.o CC arch/x86/kernel/cpu/vortex.o AR drivers/tty/serial/built-in.a CC drivers/tty/tty_jobctrl.o CC drivers/acpi/nvs.o CC net/sunrpc/auth_gss/gss_krb5_wrap.o CC mm/mmu_gather.o CC [M] fs/efivarfs/file.o CC net/sunrpc/auth_gss/gss_krb5_crypto.o CC drivers/acpi/acpica/nsnames.o CC fs/nfs/namespace.o CC net/core/gso.o CC drivers/acpi/wakeup.o CC lib/objpool.o CC net/handshake/trace.o CC net/ethtool/eeprom.o CC net/netfilter/nf_conntrack_proto_udp.o CC arch/x86/kernel/cpu/perfctr-watchdog.o CC drivers/tty/n_null.o CC fs/9p/vfs_dir.o CC net/core/net-sysfs.o AR drivers/char/hw_random/built-in.a CC drivers/char/misc.o AR fs/tracefs/built-in.a CC lib/plist.o CC lib/radix-tree.o CC drivers/tty/pty.o CC net/netfilter/nf_conntrack_proto_icmp.o CC arch/x86/kernel/cpu/vmware.o CC arch/x86/kernel/process_32.o CC net/sunrpc/auth_gss/gss_krb5_keys.o CC fs/open.o CC drivers/acpi/acpica/nsobject.o CC drivers/iommu/iommu-sysfs.o CC fs/ext4/symlink.o CC net/socket.o CC [M] fs/efivarfs/super.o CC drivers/char/virtio_console.o CC fs/9p/vfs_dentry.o CC drivers/char/hpet.o CC net/wireless/scan.o CC fs/ext4/sysfs.o CC fs/ext4/xattr.o CC kernel/task_work.o AR drivers/char/agp/built-in.a CC drivers/iommu/dma-iommu.o CC [M] fs/efivarfs/vars.o CC net/core/hotdata.o CC drivers/acpi/sleep.o AR net/netlabel/built-in.a CC drivers/iommu/iova.o CC drivers/acpi/acpica/nsparse.o CC net/netfilter/nf_conntrack_extend.o CC drivers/char/nvram.o CC kernel/extable.o CC net/ethtool/stats.o CC arch/x86/kernel/cpu/hypervisor.o CC fs/nfs/mount_clnt.o CC net/core/net-procfs.o CC net/core/netpoll.o CC drivers/tty/tty_audit.o CC drivers/tty/sysrq.o CC fs/ext4/xattr_hurd.o CC fs/9p/v9fs.o CC fs/9p/fid.o CC net/core/fib_rules.o CC net/core/net-traces.o CC drivers/acpi/acpica/nspredef.o AR net/sunrpc/auth_gss/built-in.a CC net/sunrpc/clnt.o CC net/sysctl_net.o CC arch/x86/kernel/cpu/mshyperv.o CC fs/read_write.o CC block/blk-mq-pci.o AR drivers/gpu/host1x/built-in.a CC arch/x86/kernel/signal.o CC net/netfilter/nf_conntrack_acct.o LD [M] fs/efivarfs/efivarfs.o CC arch/x86/kernel/signal_32.o AR drivers/gpu/vga/built-in.a CC fs/nfs/nfstrace.o CC fs/nfs/export.o CC arch/x86/kernel/traps.o CC net/ipv4/tcp_output.o CC drivers/acpi/device_sysfs.o AR drivers/gpu/drm/tests/built-in.a AR drivers/gpu/drm/arm/built-in.a AR net/handshake/built-in.a CC drivers/gpu/drm/display/drm_display_helper_mod.o CC net/netfilter/nf_conntrack_seqadj.o CC drivers/acpi/acpica/nsprepkg.o CC drivers/acpi/device_pm.o CC fs/file_table.o CC net/core/selftests.o CC drivers/gpu/drm/ttm/ttm_tt.o AR drivers/char/built-in.a CC fs/super.o CC drivers/gpu/drm/ttm/ttm_bo.o CC net/netfilter/nf_conntrack_proto_icmpv6.o CC mm/mprotect.o CC kernel/params.o CC net/sunrpc/xprt.o CC lib/ratelimit.o CC fs/9p/xattr.o CC fs/char_dev.o CC drivers/gpu/drm/display/drm_dp_dual_mode_helper.o CC net/core/ptp_classifier.o CC drivers/acpi/proc.o AR drivers/iommu/built-in.a CC net/ipv6/reassembly.o CC drivers/connector/cn_queue.o CC block/blk-mq-virtio.o CC drivers/acpi/acpica/nsrepair.o CC net/ethtool/phc_vclocks.o AR drivers/tty/built-in.a CC net/ethtool/mm.o CC drivers/acpi/bus.o CC drivers/connector/connector.o CC net/netfilter/nf_conntrack_netlink.o CC net/mac80211/sta_info.o CC net/core/netprio_cgroup.o CC fs/nfs/sysfs.o CC arch/x86/kernel/cpu/debugfs.o CC mm/mremap.o CC mm/msync.o CC net/netfilter/nf_conntrack_ftp.o CC drivers/acpi/acpica/nsrepair2.o CC net/ipv4/tcp_timer.o CC fs/stat.o AR fs/9p/built-in.a CC drivers/gpu/drm/ttm/ttm_bo_util.o CC fs/exec.o CC fs/ext4/xattr_trusted.o CC fs/ext4/xattr_user.o CC net/core/netclassid_cgroup.o CC fs/ext4/fast_commit.o CC arch/x86/kernel/cpu/capflags.o CC net/core/dst_cache.o CC fs/pipe.o CC fs/namei.o CC drivers/gpu/drm/display/drm_dp_helper.o CC net/netfilter/nf_conntrack_irc.o CC block/blk-mq-debugfs.o AR arch/x86/kernel/cpu/built-in.a CC fs/nfs/fs_context.o CC fs/nfs/nfsroot.o CC arch/x86/kernel/idt.o CC kernel/kthread.o CC net/sunrpc/socklib.o CC mm/page_vma_mapped.o CC drivers/acpi/acpica/nssearch.o CC net/ethtool/module.o CC net/wireless/nl80211.o CC drivers/connector/cn_proc.o CC mm/pagewalk.o CC net/core/gro_cells.o CC arch/x86/kernel/irq.o CC arch/x86/kernel/irq_32.o CC drivers/acpi/acpica/nsutils.o CC mm/pgtable-generic.o CC net/sunrpc/xprtsock.o CC net/mac80211/wep.o CC fs/nfs/sysctl.o CC net/wireless/mlme.o CC mm/rmap.o CC drivers/acpi/glue.o CC fs/ext4/orphan.o CC fs/fcntl.o CC net/ipv6/tcp_ipv6.o CC lib/rbtree.o CC drivers/gpu/drm/ttm/ttm_bo_vm.o CC drivers/acpi/acpica/nswalk.o CC net/core/failover.o CC arch/x86/kernel/dumpstack_32.o CC net/wireless/ibss.o CC net/wireless/sme.o CC block/blk-pm.o CC net/netfilter/nf_conntrack_sip.o CC block/holder.o CC net/mac80211/aead_api.o CC net/sunrpc/sched.o CC lib/seq_buf.o CC kernel/sys_ni.o CC net/sunrpc/auth.o CC drivers/gpu/drm/ttm/ttm_module.o CC net/netfilter/nf_nat_core.o CC drivers/acpi/acpica/nsxfeval.o CC net/ethtool/pse-pd.o CC arch/x86/kernel/time.o CC drivers/acpi/acpica/nsxfname.o CC lib/siphash.o CC lib/string.o AR drivers/connector/built-in.a CC drivers/base/power/sysfs.o CC drivers/base/firmware_loader/builtin/main.o CC drivers/base/firmware_loader/main.o CC net/netfilter/nf_nat_proto.o CC drivers/block/loop.o CC kernel/nsproxy.o CC drivers/gpu/drm/ttm/ttm_execbuf_util.o CC drivers/block/virtio_blk.o CC drivers/gpu/drm/ttm/ttm_range_manager.o CC drivers/acpi/acpica/nsxfobj.o CC net/ipv4/tcp_ipv4.o CC net/mac80211/wpa.o CC lib/timerqueue.o AR drivers/misc/eeprom/built-in.a AR drivers/misc/cb710/built-in.a AR drivers/misc/ti-st/built-in.a CC arch/x86/kernel/ioport.o CC arch/x86/kernel/dumpstack.o AR drivers/mfd/built-in.a CC net/wireless/chan.o CC mm/vmalloc.o CC fs/ext4/acl.o AR drivers/misc/lis3lv02d/built-in.a CC net/wireless/ethtool.o CC net/netfilter/nf_nat_helper.o AR drivers/misc/cardreader/built-in.a CC drivers/gpu/drm/display/drm_dp_mst_topology.o AR drivers/misc/built-in.a AR block/built-in.a CC net/ipv4/tcp_minisocks.o CC net/ethtool/plca.o AR drivers/base/firmware_loader/builtin/built-in.a CC drivers/acpi/acpica/psargs.o CC arch/x86/kernel/nmi.o CC net/netfilter/nf_nat_masquerade.o CC lib/vsprintf.o CC net/ipv6/ping.o CC net/wireless/mesh.o CC drivers/base/power/generic_ops.o CC mm/process_vm_access.o CC net/sunrpc/auth_null.o CC net/mac80211/scan.o CC drivers/gpu/drm/ttm/ttm_resource.o CC drivers/gpu/drm/ttm/ttm_pool.o CC net/ipv4/tcp_cong.o CC drivers/acpi/acpica/psloop.o AR net/core/built-in.a CC drivers/acpi/acpica/psobject.o CC mm/page_alloc.o AR drivers/base/firmware_loader/built-in.a CC arch/x86/kernel/ldt.o CC drivers/base/power/common.o CC drivers/base/regmap/regmap.o CC arch/x86/kernel/setup.o CC drivers/base/regmap/regcache.o CC kernel/notifier.o CC drivers/base/regmap/regcache-rbtree.o CC mm/init-mm.o CC drivers/acpi/acpica/psopcode.o CC drivers/acpi/acpica/psopinfo.o AR net/ethtool/built-in.a AR drivers/base/test/built-in.a CC fs/ioctl.o CC drivers/base/component.o CC mm/memblock.o CC drivers/base/core.o CC fs/readdir.o CC arch/x86/kernel/x86_init.o CC drivers/gpu/drm/i915/i915_config.o CC fs/nfs/nfs3super.o CC net/ipv6/exthdrs.o CC drivers/base/power/qos.o AR drivers/block/built-in.a CC arch/x86/kernel/i8259.o AR drivers/gpu/drm/renesas/rcar-du/built-in.a AR drivers/gpu/drm/renesas/rz-du/built-in.a AR drivers/nfc/built-in.a AR drivers/gpu/drm/renesas/built-in.a CC drivers/acpi/acpica/psparse.o CC drivers/base/power/runtime.o CC net/sunrpc/auth_tls.o AR drivers/dax/hmem/built-in.a AR drivers/dax/built-in.a CC drivers/gpu/drm/ttm/ttm_device.o CC arch/x86/kernel/irqinit.o CC drivers/acpi/acpica/psscope.o CC drivers/base/power/wakeirq.o CC drivers/gpu/drm/i915/i915_driver.o CC net/netfilter/nf_nat_ftp.o CC drivers/acpi/scan.o CC lib/win_minmax.o CC fs/ext4/xattr_security.o CC arch/x86/kernel/jump_label.o CC arch/x86/kernel/irq_work.o CC drivers/base/regmap/regcache-flat.o CC fs/nfs/nfs3client.o CC drivers/base/regmap/regcache-maple.o CC net/mac80211/offchannel.o CC drivers/gpu/drm/i915/i915_drm_client.o CC drivers/acpi/acpica/pstree.o CC kernel/ksysfs.o CC drivers/gpu/drm/i915/i915_getparam.o CC net/sunrpc/auth_unix.o CC mm/slub.o CC net/ipv4/tcp_metrics.o CC mm/madvise.o CC drivers/base/power/main.o CC net/ipv4/tcp_fastopen.o CC net/wireless/ap.o CC drivers/base/power/wakeup.o CC net/ipv6/datagram.o CC fs/select.o CC fs/dcache.o CC net/wireless/trace.o CC net/mac80211/ht.o CC drivers/gpu/drm/ttm/ttm_sys_manager.o CC drivers/gpu/drm/ttm/ttm_agp_backend.o CC drivers/acpi/acpica/psutils.o CC mm/page_io.o CC arch/x86/kernel/probe_roms.o CC mm/swap_state.o AR fs/ext4/built-in.a CC drivers/base/power/wakeup_stats.o CC net/wireless/ocb.o CC net/ipv4/tcp_rate.o CC drivers/base/regmap/regmap-debugfs.o CC net/ipv6/ip6_flowlabel.o CC kernel/cred.o CC lib/xarray.o CC net/netfilter/nf_nat_irc.o CC drivers/base/power/trace.o CC drivers/acpi/acpica/pswalk.o CC drivers/acpi/acpica/psxface.o CC drivers/dma-buf/dma-buf.o CC fs/nfs/nfs3proc.o CC arch/x86/kernel/sys_ia32.o CC fs/inode.o CC drivers/dma-buf/dma-fence.o CC net/ipv4/tcp_recovery.o CC drivers/gpu/drm/display/drm_dsc_helper.o AR drivers/gpu/drm/ttm/built-in.a CC drivers/gpu/drm/display/drm_hdcp_helper.o CC fs/attr.o CC drivers/acpi/mipi-disco-img.o CC drivers/acpi/resource.o CC net/wireless/pmsr.o GEN net/wireless/shipped-certs.c CC net/wireless/shipped-certs.o CC arch/x86/kernel/ksysfs.o CC drivers/acpi/acpica/rsaddr.o CC net/sunrpc/svc.o CC drivers/gpu/drm/i915/i915_ioctl.o CC arch/x86/kernel/bootflag.o CC drivers/gpu/drm/i915/i915_irq.o CC drivers/gpu/drm/display/drm_hdmi_helper.o AR drivers/gpu/drm/omapdrm/built-in.a CC mm/swapfile.o AR drivers/base/regmap/built-in.a CC drivers/dma-buf/dma-fence-array.o CC kernel/reboot.o CC drivers/acpi/acpica/rscalc.o CC drivers/dma-buf/dma-fence-chain.o CC mm/swap_slots.o CC net/ipv4/tcp_ulp.o CC drivers/acpi/acpica/rscreate.o CC drivers/acpi/acpi_processor.o CC drivers/gpu/drm/i915/i915_mitigations.o CC arch/x86/kernel/e820.o CC kernel/async.o CC drivers/dma-buf/dma-fence-unwrap.o CC net/ipv4/tcp_offload.o CC net/netfilter/nf_nat_sip.o AR drivers/base/power/built-in.a CC drivers/acpi/processor_core.o CC net/ipv4/tcp_plb.o CC drivers/base/bus.o AR drivers/gpu/drm/tilcdc/built-in.a CC drivers/gpu/drm/i915/i915_module.o CC fs/bad_inode.o CC drivers/gpu/drm/virtio/virtgpu_drv.o CC mm/dmapool.o CC lib/lockref.o CC drivers/gpu/drm/virtio/virtgpu_kms.o CC arch/x86/kernel/pci-dma.o CC net/ipv6/inet6_connection_sock.o CC drivers/acpi/acpica/rsdumpinfo.o CC drivers/gpu/drm/display/drm_scdc_helper.o CC lib/bcd.o CC fs/file.o CC drivers/acpi/acpica/rsinfo.o CC mm/hugetlb.o CC net/ipv6/udp_offload.o CC drivers/gpu/drm/virtio/virtgpu_gem.o CC mm/mmu_notifier.o CC drivers/acpi/processor_pdc.o CC drivers/acpi/ec.o CC lib/sort.o CC drivers/dma-buf/dma-resv.o AR drivers/cxl/core/built-in.a AR drivers/cxl/built-in.a CC drivers/dma-buf/sync_file.o AR drivers/gpu/drm/imx/built-in.a CC lib/parser.o CC fs/nfs/nfs3xdr.o CC lib/debug_locks.o CC fs/nfs/nfs3acl.o CC net/ipv6/seg6.o CC fs/filesystems.o CC drivers/gpu/drm/virtio/virtgpu_vram.o CC drivers/acpi/acpica/rsio.o CC fs/namespace.o CC net/netfilter/x_tables.o CC kernel/range.o CC drivers/acpi/dock.o CC drivers/base/dd.o CC drivers/acpi/pci_root.o CC net/mac80211/agg-tx.o CC kernel/smpboot.o CC drivers/acpi/acpica/rsirq.o CC net/ipv6/fib6_notifier.o CC drivers/acpi/pci_link.o CC drivers/base/syscore.o CC arch/x86/kernel/quirks.o CC lib/random32.o CC net/netfilter/xt_tcpudp.o CC drivers/gpu/drm/virtio/virtgpu_display.o CC fs/seq_file.o CC net/netfilter/xt_CONNSECMARK.o AR drivers/gpu/drm/display/built-in.a CC fs/xattr.o CC arch/x86/kernel/kdebugfs.o CC drivers/gpu/drm/i915/i915_params.o CC mm/migrate.o CC drivers/acpi/acpica/rslist.o CC net/netfilter/xt_NFLOG.o CC drivers/gpu/drm/virtio/virtgpu_vq.o CC mm/page_counter.o CC drivers/acpi/acpica/rsmemory.o CC drivers/gpu/drm/i915/i915_pci.o CC fs/libfs.o AR drivers/dma-buf/built-in.a CC lib/bust_spinlocks.o CC drivers/macintosh/mac_hid.o CC lib/kasprintf.o CC drivers/gpu/drm/virtio/virtgpu_fence.o CC net/ipv6/rpl.o CC drivers/gpu/drm/virtio/virtgpu_object.o CC net/ipv6/ioam6.o CC drivers/gpu/drm/virtio/virtgpu_debugfs.o CC net/netfilter/xt_SECMARK.o CC fs/fs-writeback.o CC drivers/acpi/acpica/rsmisc.o CC kernel/ucount.o CC net/ipv4/datagram.o CC fs/nfs/nfs4proc.o CC drivers/acpi/acpica/rsserial.o AR drivers/gpu/drm/i2c/built-in.a AR drivers/gpu/drm/panel/built-in.a CC arch/x86/kernel/alternative.o CC drivers/gpu/drm/virtio/virtgpu_plane.o CC net/ipv6/sysctl_net_ipv6.o CC net/ipv4/raw.o CC lib/bitmap.o CC drivers/base/driver.o CC drivers/acpi/pci_irq.o CC fs/nfs/nfs4xdr.o CC drivers/acpi/acpi_apd.o CC fs/pnode.o CC lib/scatterlist.o CC mm/hugetlb_cgroup.o CC net/ipv4/udp.o AR drivers/macintosh/built-in.a CC kernel/regset.o CC arch/x86/kernel/i8253.o CC kernel/ksyms_common.o CC fs/splice.o CC drivers/acpi/acpica/rsutils.o CC net/ipv6/xfrm6_policy.o CC mm/early_ioremap.o CC net/ipv6/xfrm6_state.o CC net/sunrpc/svcsock.o CC net/netfilter/xt_TCPMSS.o CC fs/sync.o CC drivers/gpu/drm/virtio/virtgpu_ioctl.o CC drivers/base/class.o CC net/ipv6/xfrm6_input.o CC drivers/gpu/drm/virtio/virtgpu_prime.o CC net/mac80211/agg-rx.o CC drivers/gpu/drm/i915/i915_scatterlist.o CC drivers/gpu/drm/i915/i915_suspend.o CC drivers/acpi/acpi_platform.o CC fs/nfs/nfs4state.o CC arch/x86/kernel/hw_breakpoint.o CC net/mac80211/vht.o CC drivers/base/platform.o CC drivers/acpi/acpica/rsxface.o CC drivers/base/cpu.o CC lib/list_sort.o CC kernel/groups.o CC drivers/acpi/acpi_pnp.o CC fs/utimes.o CC net/netfilter/xt_conntrack.o CC drivers/acpi/power.o CC drivers/acpi/acpica/tbdata.o CC net/ipv6/xfrm6_output.o CC kernel/kcmp.o CC arch/x86/kernel/tsc.o CC net/ipv6/xfrm6_protocol.o CC net/sunrpc/svcauth.o CC drivers/acpi/event.o CC mm/secretmem.o CC drivers/gpu/drm/virtio/virtgpu_trace_points.o AR drivers/scsi/pcmcia/built-in.a CC drivers/acpi/acpica/tbfadt.o CC drivers/scsi/scsi.o CC lib/uuid.o CC mm/hmm.o CC fs/d_path.o CC drivers/acpi/evged.o CC drivers/base/firmware.o CC arch/x86/kernel/tsc_msr.o CC lib/iov_iter.o CC drivers/acpi/acpica/tbfind.o CC drivers/acpi/sysfs.o CC drivers/base/init.o CC drivers/base/map.o CC drivers/acpi/acpica/tbinstal.o CC drivers/scsi/hosts.o CC net/ipv6/netfilter.o CC net/netfilter/xt_policy.o CC drivers/acpi/property.o CC kernel/freezer.o CC net/mac80211/he.o CC lib/clz_ctz.o CC drivers/acpi/acpica/tbprint.o AR drivers/gpu/drm/bridge/analogix/built-in.a AR drivers/gpu/drm/bridge/cadence/built-in.a AR drivers/gpu/drm/bridge/imx/built-in.a AR drivers/gpu/drm/bridge/synopsys/built-in.a AR drivers/gpu/drm/bridge/built-in.a CC drivers/acpi/acpica/tbutils.o CC lib/bsearch.o AR drivers/gpu/drm/hisilicon/built-in.a CC net/netfilter/xt_state.o CC [M] net/netfilter/nf_log_syslog.o CC net/mac80211/s1g.o CC fs/stack.o CC kernel/profile.o CC drivers/acpi/acpica/tbxface.o CC drivers/gpu/drm/i915/i915_switcheroo.o CC arch/x86/kernel/io_delay.o CC drivers/acpi/debugfs.o CC arch/x86/kernel/rtc.o CC [M] net/netfilter/xt_mark.o CC lib/find_bit.o CC drivers/base/devres.o CC arch/x86/kernel/resource.o AS arch/x86/kernel/irqflags.o CC arch/x86/kernel/static_call.o CC mm/memfd.o CC drivers/scsi/scsi_ioctl.o CC drivers/scsi/scsicam.o CC drivers/gpu/drm/virtio/virtgpu_submit.o CC drivers/acpi/acpica/tbxfload.o CC drivers/acpi/acpi_lpat.o CC arch/x86/kernel/process.o CC arch/x86/kernel/ptrace.o CC mm/ptdump.o CC lib/llist.o CC drivers/scsi/scsi_error.o CC drivers/base/attribute_container.o CC net/sunrpc/svcauth_unix.o CC drivers/gpu/drm/i915/i915_sysfs.o CC fs/fs_struct.o CC net/ipv6/proc.o CC lib/lwq.o CC drivers/base/transport_class.o CC net/sunrpc/addr.o CC fs/statfs.o CC mm/execmem.o CC drivers/acpi/acpi_pcc.o CC arch/x86/kernel/tls.o CC net/ipv6/syncookies.o CC lib/memweight.o CC lib/kfifo.o CC drivers/base/topology.o CC drivers/acpi/acpica/tbxfroot.o CC lib/percpu-refcount.o CC kernel/stacktrace.o CC net/sunrpc/rpcb_clnt.o CC drivers/gpu/drm/i915/i915_utils.o CC drivers/acpi/ac.o CC drivers/scsi/scsi_lib.o CC kernel/dma.o CC fs/nfs/nfs4renewd.o CC drivers/acpi/acpica/utaddress.o CC kernel/smp.o CC lib/rhashtable.o CC arch/x86/kernel/step.o CC net/ipv6/calipso.o CC net/mac80211/ibss.o CC kernel/uid16.o CC [M] net/netfilter/xt_nat.o AR drivers/gpu/drm/virtio/built-in.a CC drivers/acpi/button.o CC drivers/acpi/fan_core.o CC kernel/kallsyms.o CC drivers/gpu/drm/i915/intel_clock_gating.o CC drivers/gpu/drm/i915/intel_device_info.o CC fs/fs_pin.o AR mm/built-in.a CC drivers/scsi/constants.o CC fs/nsfs.o CC fs/fs_types.o CC net/ipv4/udplite.o CC drivers/acpi/acpica/utalloc.o CC drivers/base/container.o CC arch/x86/kernel/i8237.o CC fs/fs_context.o CC net/mac80211/iface.o CC kernel/acct.o CC drivers/acpi/fan_attr.o CC fs/fs_parser.o CC net/mac80211/link.o CC drivers/gpu/drm/i915/intel_memory_region.o CC lib/base64.o CC lib/once.o CC drivers/base/property.o CC net/mac80211/rate.o CC fs/fsopen.o CC net/ipv6/ah6.o CC net/sunrpc/timer.o CC arch/x86/kernel/stacktrace.o CC net/ipv4/udp_offload.o CC fs/nfs/nfs4super.o CC arch/x86/kernel/reboot.o CC drivers/acpi/acpica/utascii.o CC arch/x86/kernel/msr.o CC [M] net/netfilter/xt_LOG.o CC fs/init.o CC drivers/acpi/acpi_video.o CC net/sunrpc/xdr.o CC net/ipv4/arp.o CC drivers/scsi/scsi_lib_dma.o CC drivers/acpi/acpica/utbuffer.o CC drivers/acpi/acpica/utcksum.o CC kernel/vmcore_info.o CC lib/refcount.o CC net/ipv6/esp6.o CC fs/nfs/nfs4file.o CC net/sunrpc/sunrpc_syms.o CC lib/rcuref.o CC fs/kernel_read_file.o CC drivers/scsi/scsi_scan.o CC net/mac80211/michael.o CC kernel/elfcorehdr.o AR drivers/nvme/common/built-in.a AR drivers/nvme/host/built-in.a AR drivers/nvme/target/built-in.a CC [M] net/netfilter/xt_MASQUERADE.o AR drivers/nvme/built-in.a CC lib/usercopy.o CC drivers/ata/libata-core.o CC fs/mnt_idmapping.o CC drivers/ata/libata-scsi.o CC drivers/acpi/acpica/utcopy.o CC fs/remap_range.o CC drivers/gpu/drm/i915/intel_pcode.o CC [M] net/netfilter/xt_addrtype.o CC drivers/ata/libata-eh.o CC drivers/acpi/video_detect.o CC drivers/ata/libata-transport.o CC fs/pidfs.o CC fs/nfs/delegation.o CC net/mac80211/tkip.o CC drivers/acpi/acpica/utexcep.o CC drivers/gpu/drm/i915/intel_region_ttm.o CC fs/buffer.o CC lib/errseq.o CC fs/mpage.o CC drivers/ata/libata-trace.o CC net/mac80211/aes_cmac.o CC arch/x86/kernel/cpuid.o GEN drivers/scsi/scsi_devinfo_tbl.c CC drivers/scsi/scsi_devinfo.o CC lib/bucket_locks.o CC drivers/scsi/scsi_sysctl.o CC drivers/base/cacheinfo.o CC drivers/base/swnode.o CC drivers/gpu/drm/i915/intel_runtime_pm.o CC kernel/crash_reserve.o CC drivers/acpi/acpica/utdebug.o CC drivers/acpi/acpica/utdecode.o CC drivers/ata/libata-sata.o CC drivers/base/auxiliary.o CC net/ipv6/sit.o CC lib/generic-radix-tree.o CC drivers/acpi/processor_driver.o CC net/mac80211/aes_gmac.o CC net/mac80211/fils_aead.o CC drivers/scsi/scsi_proc.o CC fs/proc_namespace.o CC drivers/ata/libata-sff.o CC drivers/acpi/acpica/utdelete.o CC net/mac80211/cfg.o CC arch/x86/kernel/early-quirks.o CC drivers/scsi/scsi_debugfs.o CC drivers/acpi/acpica/uterror.o CC drivers/ata/libata-pmp.o CC drivers/base/devtmpfs.o CC drivers/gpu/drm/i915/intel_sbi.o CC fs/direct-io.o CC drivers/base/module.o CC drivers/scsi/scsi_trace.o CC lib/bitmap-str.o CC lib/string_helpers.o CC drivers/scsi/scsi_logging.o CC drivers/acpi/acpica/uteval.o CC net/ipv4/icmp.o CC net/sunrpc/cache.o CC drivers/acpi/acpica/utglobal.o CC net/mac80211/ethtool.o CC net/mac80211/rx.o CC drivers/ata/libata-acpi.o CC kernel/kexec_core.o CC drivers/acpi/acpica/uthex.o AR net/netfilter/built-in.a CC net/ipv6/addrconf_core.o CC fs/eventpoll.o CC fs/anon_inodes.o CC drivers/acpi/processor_thermal.o CC fs/nfs/nfs4idmap.o CC drivers/ata/libata-pata-timings.o CC arch/x86/kernel/smp.o CC drivers/acpi/acpica/utids.o CC drivers/acpi/acpica/utinit.o CC net/ipv4/devinet.o AR drivers/net/phy/qcom/built-in.a CC drivers/net/phy/mdio-boardinfo.o CC fs/signalfd.o CC drivers/gpu/drm/i915/intel_step.o CC fs/timerfd.o CC drivers/net/phy/stubs.o CC drivers/gpu/drm/i915/intel_uncore.o CC net/mac80211/spectmgmt.o CC fs/eventfd.o AR drivers/net/pse-pd/built-in.a CC arch/x86/kernel/smpboot.o CC lib/hexdump.o CC drivers/base/devcoredump.o CC net/mac80211/tx.o CC net/mac80211/key.o CC net/mac80211/util.o CC drivers/ata/ahci.o CC fs/aio.o CC lib/kstrtox.o CC drivers/gpu/drm/i915/intel_wakeref.o CC drivers/acpi/acpica/utlock.o CC drivers/scsi/scsi_pm.o CC drivers/acpi/processor_idle.o CC fs/locks.o CC drivers/scsi/scsi_bsg.o CC drivers/ata/libahci.o CC drivers/gpu/drm/i915/vlv_sideband.o CC fs/nfs/callback.o CC fs/binfmt_misc.o CC drivers/ata/ata_piix.o CC net/ipv6/exthdrs_core.o CC kernel/crash_core.o CC drivers/acpi/acpica/utmath.o AR drivers/gpu/drm/mxsfb/built-in.a AR drivers/gpu/drm/tiny/built-in.a CC lib/iomap.o CC drivers/scsi/scsi_common.o AR drivers/gpu/drm/xlnx/built-in.a CC lib/iomap_copy.o CC arch/x86/kernel/tsc_sync.o CC drivers/net/phy/mdio_devres.o CC drivers/net/phy/phy.o CC drivers/scsi/scsi_transport_spi.o CC arch/x86/kernel/setup_percpu.o CC drivers/base/platform-msi.o CC kernel/kexec.o CC drivers/acpi/acpica/utmisc.o CC lib/devres.o CC net/mac80211/parse.o CC drivers/net/mdio/acpi_mdio.o AR drivers/net/pcs/built-in.a CC drivers/net/mdio/fwnode_mdio.o CC net/ipv6/ip6_checksum.o CC drivers/ata/pata_amd.o CC drivers/acpi/acpica/utmutex.o CC fs/binfmt_script.o CC net/sunrpc/rpc_pipe.o CC drivers/ata/pata_oldpiix.o CC drivers/net/phy/phy-c45.o CC drivers/ata/pata_sch.o CC arch/x86/kernel/mpparse.o CC drivers/gpu/drm/i915/vlv_suspend.o AR net/wireless/built-in.a CC fs/binfmt_elf.o CC net/mac80211/wme.o AR drivers/gpu/drm/gud/built-in.a CC net/ipv4/af_inet.o CC drivers/gpu/drm/i915/soc/intel_dram.o AR drivers/gpu/drm/solomon/built-in.a CC drivers/base/physical_location.o CC arch/x86/kernel/trace_clock.o CC net/ipv4/igmp.o CC drivers/ata/pata_mpiix.o CC drivers/ata/ata_generic.o CC drivers/acpi/acpica/utnonansi.o CC drivers/acpi/acpica/utobject.o CC lib/check_signature.o CC kernel/utsname.o CC [M] drivers/gpu/drm/scheduler/sched_main.o CC drivers/acpi/processor_throttling.o CC net/mac80211/chan.o CC [M] drivers/gpu/drm/xe/xe_bb.o CC drivers/gpu/drm/drm_aperture.o CC [M] drivers/gpu/drm/xe/xe_bo.o CC lib/interval_tree.o CC [M] drivers/gpu/drm/scheduler/sched_fence.o CC drivers/net/phy/phy-core.o CC fs/nfs/callback_xdr.o CC fs/nfs/callback_proc.o CC net/ipv4/fib_frontend.o CC drivers/base/trace.o AR drivers/net/mdio/built-in.a CC drivers/acpi/acpica/utosi.o CC lib/assoc_array.o CC net/ipv4/fib_semantics.o CC kernel/pid_namespace.o CC kernel/stop_machine.o CC fs/mbcache.o CC drivers/scsi/virtio_scsi.o CC net/sunrpc/sysfs.o CC kernel/audit.o CC drivers/gpu/drm/drm_atomic.o CC drivers/net/phy/phy_device.o CC drivers/acpi/acpica/utownerid.o CC drivers/acpi/acpica/utpredef.o CC net/ipv6/ip6_icmp.o CC [M] drivers/gpu/drm/scheduler/sched_entity.o CC drivers/net/phy/linkmode.o CC arch/x86/kernel/trace.o CC fs/posix_acl.o CC drivers/scsi/sd.o CC fs/coredump.o CC kernel/auditfilter.o CC kernel/auditsc.o AR drivers/ata/built-in.a CC arch/x86/kernel/rethook.o CC drivers/scsi/sr.o AR drivers/net/ethernet/3com/built-in.a CC drivers/net/ethernet/8390/ne2k-pci.o CC drivers/net/phy/mdio_bus.o CC net/mac80211/trace.o AR drivers/net/wireless/admtek/built-in.a CC net/mac80211/mlme.o CC drivers/acpi/acpica/utresdecode.o AR drivers/net/wireless/ath/built-in.a AR drivers/net/wireless/atmel/built-in.a AR drivers/net/wireless/broadcom/built-in.a CC net/ipv6/output_core.o CC drivers/gpu/drm/i915/soc/intel_gmch.o CC net/ipv6/protocol.o AR drivers/net/wireless/intel/built-in.a AR drivers/net/wireless/intersil/built-in.a AR drivers/net/wireless/marvell/built-in.a CC net/ipv6/ip6_offload.o AR drivers/net/ethernet/adaptec/built-in.a AR drivers/net/wireless/mediatek/built-in.a CC fs/drop_caches.o AR drivers/net/wireless/microchip/built-in.a AR drivers/net/wireless/purelifi/built-in.a CC lib/bitrev.o CC lib/crc-ccitt.o AR drivers/base/built-in.a AR drivers/net/wireless/quantenna/built-in.a CC fs/sysctls.o CC net/sunrpc/svc_xprt.o AR drivers/net/wireless/ralink/built-in.a AR drivers/net/wireless/realtek/built-in.a AR drivers/net/wireless/rsi/built-in.a AR drivers/net/wireless/silabs/built-in.a AR drivers/net/wireless/st/built-in.a AR drivers/net/wireless/ti/built-in.a CC kernel/audit_watch.o AR drivers/net/wireless/zydas/built-in.a CC kernel/audit_fsnotify.o AR drivers/net/wireless/virtual/built-in.a AR drivers/net/wireless/built-in.a CC drivers/acpi/acpica/utresrc.o CC drivers/acpi/acpica/utstate.o LD [M] drivers/gpu/drm/scheduler/gpu-sched.o CC drivers/gpu/drm/drm_atomic_uapi.o CC drivers/gpu/drm/drm_auth.o CC kernel/audit_tree.o CC fs/fhandle.o CC arch/x86/kernel/vmcore_info_32.o CC drivers/net/ethernet/8390/8390.o CC net/mac80211/tdls.o CC lib/crc16.o CC drivers/acpi/processor_perflib.o CC drivers/firewire/init_ohci1394_dma.o CC net/sunrpc/xprtmultipath.o CC drivers/acpi/acpica/utstring.o HOSTCC lib/gen_crc32table CC [M] drivers/gpu/drm/xe/xe_bo_evict.o AR drivers/net/usb/built-in.a CC [M] drivers/gpu/drm/xe/xe_debugfs.o CC kernel/kprobes.o AR drivers/net/ethernet/agere/built-in.a CC lib/xxhash.o CC drivers/cdrom/cdrom.o AR drivers/net/ethernet/alacritech/built-in.a AR drivers/auxdisplay/built-in.a CC drivers/net/mii.o CC drivers/gpu/drm/drm_blend.o AR drivers/net/ethernet/alteon/built-in.a CC fs/nfs/nfs4namespace.o CC lib/genalloc.o CC net/ipv4/fib_trie.o CC fs/nfs/nfs4getroot.o CC drivers/net/loopback.o CC arch/x86/kernel/machine_kexec_32.o CC net/ipv6/tcpv6_offload.o CC drivers/scsi/sr_ioctl.o CC drivers/gpu/drm/i915/soc/intel_pch.o CC drivers/acpi/acpica/utstrsuppt.o CC drivers/scsi/sr_vendor.o CC drivers/gpu/drm/i915/i915_memcpy.o CC drivers/gpu/drm/drm_bridge.o CC fs/nfs/nfs4client.o CC net/ipv4/fib_notifier.o CC kernel/seccomp.o CC drivers/acpi/acpica/utstrtoul64.o CC drivers/acpi/acpica/utxface.o AR drivers/firewire/built-in.a CC drivers/gpu/drm/drm_cache.o CC kernel/relay.o CC net/mac80211/ocb.o CC fs/nfs/nfs4session.o CC drivers/net/phy/mdio_device.o CC drivers/net/phy/swphy.o CC drivers/acpi/acpica/utxfinit.o CC drivers/gpu/drm/drm_client.o CC lib/percpu_counter.o CC kernel/utsname_sysctl.o CC drivers/acpi/acpica/utxferror.o CC net/mac80211/airtime.o CC drivers/gpu/drm/i915/i915_mm.o CC [M] drivers/gpu/drm/xe/xe_devcoredump.o AR drivers/net/ethernet/8390/built-in.a CC drivers/scsi/sg.o AR drivers/net/ethernet/amazon/built-in.a AR drivers/net/ethernet/amd/built-in.a CC drivers/gpu/drm/i915/i915_sw_fence.o AR drivers/net/ethernet/aquantia/built-in.a CC drivers/gpu/drm/i915/i915_sw_fence_work.o AR drivers/net/ethernet/arc/built-in.a CC drivers/gpu/drm/i915/i915_syncmap.o CC drivers/gpu/drm/i915/i915_user_extensions.o AR drivers/net/ethernet/asix/built-in.a CC drivers/net/phy/fixed_phy.o AR drivers/net/ethernet/atheros/built-in.a CC lib/audit.o AR drivers/net/ethernet/cadence/built-in.a AS arch/x86/kernel/relocate_kernel_32.o CC drivers/net/ethernet/broadcom/bnx2.o AR drivers/net/ethernet/brocade/built-in.a CC lib/syscall.o CC drivers/scsi/scsi_sysfs.o CC arch/x86/kernel/crash_dump_32.o CC net/mac80211/eht.o CC drivers/gpu/drm/i915/i915_debugfs.o CC drivers/gpu/drm/i915/i915_debugfs_params.o CC drivers/acpi/acpica/utxfmutex.o CC drivers/net/phy/realtek.o CC drivers/pcmcia/cs.o CC drivers/acpi/container.o CC drivers/pcmcia/socket_sysfs.o CC drivers/acpi/thermal_lib.o CC drivers/pcmcia/cardbus.o CC fs/nfs/dns_resolve.o CC kernel/delayacct.o CC drivers/pcmcia/ds.o CC arch/x86/kernel/crash.o CC lib/errname.o CC drivers/net/netconsole.o CC drivers/gpu/drm/i915/i915_pmu.o CC drivers/gpu/drm/i915/gt/gen2_engine_cs.o CC net/ipv6/exthdrs_offload.o CC drivers/gpu/drm/i915/gt/gen6_engine_cs.o AR drivers/net/ethernet/cavium/common/built-in.a CC net/ipv4/inet_fragment.o AR drivers/net/ethernet/cavium/thunder/built-in.a CC kernel/taskstats.o CC drivers/gpu/drm/i915/gt/gen6_ppgtt.o CC kernel/tsacct.o AR drivers/net/ethernet/cavium/liquidio/built-in.a AR drivers/net/ethernet/cavium/octeon/built-in.a CC kernel/tracepoint.o CC drivers/gpu/drm/i915/gt/gen7_renderclear.o AR drivers/net/ethernet/cavium/built-in.a CC net/ipv4/ping.o AR drivers/acpi/acpica/built-in.a AR drivers/net/ethernet/chelsio/built-in.a AR drivers/net/ethernet/cisco/built-in.a CC drivers/gpu/drm/i915/gt/gen8_engine_cs.o AR drivers/net/ethernet/cortina/built-in.a CC drivers/gpu/drm/drm_client_modeset.o CC drivers/net/virtio_net.o CC lib/nlattr.o CC [M] drivers/gpu/drm/xe/xe_device.o AR drivers/net/ethernet/dec/tulip/built-in.a AR drivers/net/ethernet/dec/built-in.a CC [M] drivers/gpu/drm/xe/xe_device_sysfs.o AR drivers/net/ethernet/dlink/built-in.a AR drivers/net/ethernet/emulex/built-in.a AR drivers/net/ethernet/engleder/built-in.a AR drivers/net/ethernet/ezchip/built-in.a CC drivers/acpi/thermal.o CC fs/nfs/nfs4trace.o CC [M] drivers/gpu/drm/xe/xe_dma_buf.o CC drivers/gpu/drm/i915/gt/gen8_ppgtt.o AR drivers/cdrom/built-in.a AR drivers/net/ethernet/fujitsu/built-in.a CC lib/cpu_rmap.o CC fs/nfs/nfs4sysctl.o CC kernel/irq_work.o CC drivers/pcmcia/pcmcia_resource.o CC net/ipv4/ip_tunnel_core.o CC net/ipv4/gre_offload.o CC arch/x86/kernel/module.o CC kernel/static_call.o CC drivers/pcmcia/cistpl.o CC kernel/padata.o CC net/ipv6/inet6_hashtables.o CC drivers/gpu/drm/i915/gt/intel_breadcrumbs.o CC kernel/jump_label.o CC lib/dynamic_queue_limits.o CC lib/glob.o CC lib/strncpy_from_user.o CC net/sunrpc/stats.o CC drivers/net/net_failover.o AR drivers/net/phy/built-in.a CC [M] drivers/gpu/drm/xe/xe_drm_client.o CC drivers/usb/common/common.o CC net/ipv6/mcast_snoop.o CC drivers/usb/core/usb.o AR drivers/usb/phy/built-in.a CC drivers/usb/core/hub.o CC drivers/usb/mon/mon_main.o CC [M] drivers/gpu/drm/xe/xe_exec.o CC drivers/gpu/drm/i915/gt/intel_context.o AR drivers/scsi/built-in.a CC drivers/pcmcia/pcmcia_cis.o CC drivers/usb/mon/mon_stat.o CC [M] drivers/gpu/drm/xe/xe_execlist.o CC drivers/usb/core/hcd.o CC drivers/pcmcia/rsrc_mgr.o CC drivers/gpu/drm/i915/gt/intel_context_sseu.o CC drivers/acpi/nhlt.o CC drivers/usb/host/pci-quirks.o CC drivers/acpi/acpi_memhotplug.o CC arch/x86/kernel/doublefault_32.o CC drivers/net/ethernet/broadcom/tg3.o CC drivers/gpu/drm/i915/gt/intel_engine_cs.o CC drivers/usb/core/urb.o CC kernel/context_tracking.o CC [M] drivers/gpu/drm/xe/xe_exec_queue.o CC net/mac80211/led.o CC [M] drivers/gpu/drm/xe/xe_force_wake.o CC lib/strnlen_user.o CC drivers/gpu/drm/drm_color_mgmt.o CC arch/x86/kernel/early_printk.o CC net/ipv4/metrics.o CC drivers/acpi/ioapic.o CC drivers/gpu/drm/i915/gt/intel_engine_heartbeat.o CC drivers/pcmcia/rsrc_nonstatic.o CC net/ipv4/netlink.o CC net/sunrpc/sysctl.o CC lib/net_utils.o CC drivers/usb/common/debug.o CC lib/sg_pool.o CC drivers/usb/mon/mon_text.o AR drivers/net/ethernet/fungible/built-in.a CC lib/stackdepot.o AR drivers/net/ethernet/google/built-in.a AR drivers/net/ethernet/huawei/built-in.a CC drivers/net/ethernet/intel/e1000/e1000_main.o AR drivers/usb/common/built-in.a CC drivers/usb/mon/mon_bin.o CC drivers/net/ethernet/intel/e1000e/82571.o CC drivers/acpi/battery.o CC drivers/net/ethernet/intel/e1000/e1000_hw.o CC drivers/input/serio/serio.o CC drivers/net/ethernet/intel/e1000/e1000_ethtool.o CC drivers/input/serio/i8042.o CC drivers/net/ethernet/intel/e1000/e1000_param.o CC drivers/pcmcia/yenta_socket.o CC [M] drivers/gpu/drm/xe/xe_ggtt.o CC net/ipv4/nexthop.o CC kernel/iomem.o CC kernel/rseq.o CC [M] drivers/gpu/drm/xe/xe_gpu_scheduler.o CC drivers/usb/host/ehci-hcd.o CC arch/x86/kernel/hpet.o HOSTCC drivers/gpu/drm/xe/xe_gen_wa_oob CC drivers/net/ethernet/intel/e1000e/ich8lan.o CC drivers/gpu/drm/drm_connector.o CC drivers/acpi/bgrt.o CC net/ipv4/udp_tunnel_stub.o CC drivers/usb/class/usblp.o CC drivers/usb/storage/scsiglue.o CC drivers/acpi/spcr.o AR net/ipv6/built-in.a CC drivers/gpu/drm/i915/gt/intel_engine_pm.o CC drivers/usb/storage/protocol.o AR drivers/net/ethernet/i825xx/built-in.a CC [M] drivers/gpu/drm/xe/xe_gsc_proxy.o CC drivers/gpu/drm/drm_crtc.o CC lib/asn1_decoder.o CC arch/x86/kernel/amd_nb.o CC drivers/input/keyboard/atkbd.o CC drivers/input/mouse/psmouse-base.o AR drivers/input/joystick/built-in.a CC drivers/input/mouse/synaptics.o AR drivers/input/tablet/built-in.a AR drivers/input/touchscreen/built-in.a CC net/mac80211/pm.o CC net/ipv4/ip_tunnel.o AR drivers/input/misc/built-in.a CC drivers/input/input.o AR drivers/usb/misc/built-in.a CC drivers/usb/early/ehci-dbgp.o CC drivers/input/serio/serport.o CC drivers/input/serio/libps2.o CC drivers/usb/storage/transport.o CC drivers/gpu/drm/drm_displayid.o AR drivers/usb/mon/built-in.a CC drivers/gpu/drm/drm_drv.o CC drivers/gpu/drm/drm_dumb_buffers.o CC drivers/usb/core/message.o GEN lib/oid_registry_data.c CC lib/ucs2_string.o CC [M] drivers/gpu/drm/xe/xe_gsc_submit.o CC drivers/input/input-compat.o AR kernel/built-in.a AR drivers/acpi/built-in.a CC drivers/usb/core/driver.o AR drivers/net/ethernet/microsoft/built-in.a AR drivers/net/ethernet/litex/built-in.a AR drivers/net/ethernet/marvell/octeon_ep/built-in.a AR drivers/net/ethernet/marvell/octeon_ep_vf/built-in.a AR drivers/net/ethernet/marvell/octeontx2/built-in.a CC arch/x86/kernel/kvm.o CC drivers/net/ethernet/marvell/sky2.o AR drivers/net/ethernet/marvell/prestera/built-in.a CC arch/x86/kernel/kvmclock.o CC drivers/input/mouse/focaltech.o CC net/ipv4/sysctl_net_ipv4.o AR drivers/net/ethernet/mellanox/built-in.a CC drivers/usb/storage/usb.o AR drivers/net/ethernet/micrel/built-in.a CC drivers/net/ethernet/intel/e1000e/80003es2lan.o AR drivers/usb/class/built-in.a CC net/ipv4/proc.o CC drivers/gpu/drm/drm_edid.o AR drivers/pcmcia/built-in.a CC drivers/net/ethernet/intel/e100.o AR net/sunrpc/built-in.a CC arch/x86/kernel/paravirt.o CC drivers/usb/core/config.o CC [M] drivers/gpu/drm/xe/xe_gt.o CC lib/sbitmap.o CC drivers/input/mouse/alps.o CC drivers/gpu/drm/drm_eld.o CC drivers/gpu/drm/drm_encoder.o AR drivers/input/serio/built-in.a CC arch/x86/kernel/pvclock.o CC drivers/input/input-mt.o AR drivers/input/keyboard/built-in.a CC drivers/gpu/drm/drm_file.o CC lib/group_cpus.o CC drivers/input/input-poller.o AR drivers/usb/early/built-in.a CC drivers/usb/host/ehci-pci.o CC drivers/input/mouse/byd.o CC drivers/input/mouse/logips2pp.o CC drivers/usb/core/file.o CC drivers/usb/core/buffer.o CC drivers/rtc/lib.o CC drivers/gpu/drm/i915/gt/intel_engine_user.o AR fs/nfs/built-in.a AR fs/built-in.a CC drivers/rtc/class.o CC drivers/rtc/interface.o CC arch/x86/kernel/pcspeaker.o CC lib/fw_table.o CC drivers/input/mouse/lifebook.o CC drivers/gpu/drm/drm_fourcc.o CC drivers/input/ff-core.o CC drivers/gpu/drm/drm_framebuffer.o CC drivers/input/touchscreen.o CC drivers/usb/storage/initializers.o CC arch/x86/kernel/check.o CC arch/x86/kernel/uprobes.o AR lib/lib.a CC net/mac80211/rc80211_minstrel_ht.o CC arch/x86/kernel/perf_regs.o GEN lib/crc32table.h CC lib/oid_registry.o CC drivers/input/mouse/trackpoint.o CC drivers/usb/core/sysfs.o CC drivers/rtc/nvmem.o CC [M] drivers/gpu/drm/xe/xe_gt_ccs_mode.o CC arch/x86/kernel/tracepoint.o CC drivers/input/mouse/cypress_ps2.o CC drivers/usb/core/endpoint.o CC drivers/gpu/drm/i915/gt/intel_execlists_submission.o CC drivers/rtc/dev.o CC drivers/usb/core/devio.o CC drivers/usb/storage/sierra_ms.o CC lib/crc32.o CC drivers/input/mouse/psmouse-smbus.o CC drivers/gpu/drm/drm_gem.o CC drivers/usb/core/notify.o CC drivers/usb/core/generic.o CC drivers/i2c/algos/i2c-algo-bit.o CC [M] drivers/gpu/drm/xe/xe_gt_clock.o CC drivers/usb/core/quirks.o CC drivers/rtc/proc.o CC net/ipv4/fib_rules.o AR drivers/i3c/built-in.a CC drivers/net/ethernet/intel/e1000e/mac.o CC drivers/gpu/drm/drm_ioctl.o CC drivers/usb/core/devices.o CC net/ipv4/ipmr.o CC arch/x86/kernel/itmt.o CC drivers/i2c/busses/i2c-i801.o CC arch/x86/kernel/umip.o CC net/ipv4/ipmr_base.o CC drivers/net/ethernet/intel/e1000e/manage.o CC arch/x86/kernel/unwind_frame.o CC drivers/gpu/drm/i915/gt/intel_ggtt.o CC drivers/rtc/sysfs.o AR drivers/i2c/muxes/built-in.a CC drivers/i2c/i2c-boardinfo.o CC drivers/usb/storage/option_ms.o AR drivers/net/ethernet/intel/e1000/built-in.a CC drivers/usb/core/phy.o CC net/ipv4/syncookies.o CC drivers/usb/host/ohci-hcd.o AR lib/built-in.a CC drivers/usb/host/ohci-pci.o CC drivers/usb/host/uhci-hcd.o CC drivers/gpu/drm/i915/gt/intel_ggtt_fencing.o CC [M] drivers/gpu/drm/xe/xe_gt_debugfs.o CC drivers/net/ethernet/intel/e1000e/nvm.o CC drivers/usb/host/xhci.o CC drivers/usb/core/port.o CC net/ipv4/tunnel4.o CC drivers/input/ff-memless.o CC drivers/gpu/drm/drm_lease.o CC drivers/gpu/drm/drm_managed.o CC drivers/input/sparse-keymap.o CC [M] drivers/gpu/drm/xe/xe_gt_freq.o CC net/mac80211/wbrf.o CC drivers/gpu/drm/drm_mm.o AR drivers/input/mouse/built-in.a CC drivers/input/vivaldi-fmap.o CC drivers/usb/host/xhci-mem.o CC drivers/net/ethernet/intel/e1000e/phy.o CC drivers/usb/core/hcd-pci.o CC drivers/usb/core/usb-acpi.o CC [M] drivers/gpu/drm/xe/xe_gt_idle.o CC drivers/rtc/rtc-mc146818-lib.o CC drivers/rtc/rtc-cmos.o CC [M] drivers/gpu/drm/xe/xe_gt_mcr.o CC [M] drivers/gpu/drm/xe/xe_gt_pagefault.o AR drivers/i2c/algos/built-in.a CC drivers/usb/host/xhci-ext-caps.o CC drivers/gpu/drm/drm_mode_config.o AR arch/x86/kernel/built-in.a AR arch/x86/built-in.a CC drivers/gpu/drm/i915/gt/intel_gt.o CC drivers/usb/storage/usual-tables.o CC drivers/i2c/i2c-core-base.o CC drivers/i2c/i2c-core-smbus.o CC drivers/gpu/drm/drm_mode_object.o CC drivers/gpu/drm/drm_modes.o CC drivers/gpu/drm/drm_modeset_lock.o CC drivers/input/input-leds.o CC [M] drivers/gpu/drm/xe/xe_gt_sysfs.o CC drivers/input/evdev.o CC drivers/net/ethernet/intel/e1000e/param.o CC drivers/net/ethernet/intel/e1000e/ethtool.o CC drivers/net/ethernet/intel/e1000e/netdev.o AR drivers/i2c/busses/built-in.a CC [M] drivers/gpu/drm/xe/xe_gt_throttle.o CC drivers/i2c/i2c-core-acpi.o AR drivers/net/ethernet/microchip/built-in.a CC drivers/gpu/drm/drm_plane.o AR drivers/net/ethernet/mscc/built-in.a AR drivers/net/ethernet/myricom/built-in.a AR drivers/net/ethernet/natsemi/built-in.a AR drivers/net/ethernet/neterion/built-in.a CC [M] drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o CC [M] drivers/gpu/drm/xe/xe_gt_topology.o CC drivers/net/ethernet/intel/e1000e/ptp.o CC drivers/i2c/i2c-smbus.o GEN xe_wa_oob.c xe_wa_oob.h CC [M] drivers/gpu/drm/xe/xe_guc_capture.o AR drivers/net/ethernet/netronome/built-in.a CC net/ipv4/ipconfig.o AR drivers/usb/storage/built-in.a CC [M] drivers/gpu/drm/xe/xe_guc_ct.o CC [M] drivers/gpu/drm/xe/xe_guc_db_mgr.o CC drivers/gpu/drm/drm_prime.o CC drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.o CC net/ipv4/netfilter.o AR drivers/net/ethernet/marvell/built-in.a CC drivers/gpu/drm/drm_print.o AR drivers/media/i2c/built-in.a AR drivers/net/ethernet/ni/built-in.a CC drivers/net/ethernet/nvidia/forcedeth.o AR drivers/media/tuners/built-in.a AR drivers/usb/core/built-in.a AR drivers/pps/clients/built-in.a AR drivers/media/rc/keymaps/built-in.a AR drivers/media/rc/built-in.a AR drivers/media/common/b2c2/built-in.a AR drivers/pps/generators/built-in.a CC drivers/pps/pps.o AR drivers/media/platform/allegro-dvt/built-in.a AR drivers/media/pci/ttpci/built-in.a AR drivers/media/common/saa7146/built-in.a AR drivers/media/pci/b2c2/built-in.a CC drivers/pps/kapi.o AR drivers/media/common/siano/built-in.a AR drivers/media/pci/pluto2/built-in.a AR drivers/media/platform/amlogic/meson-ge2d/built-in.a AR drivers/media/common/v4l2-tpg/built-in.a AR drivers/media/pci/dm1105/built-in.a AR drivers/media/platform/amlogic/built-in.a AR drivers/media/pci/pt1/built-in.a CC drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.o AR drivers/media/platform/amphion/built-in.a CC drivers/gpu/drm/i915/gt/intel_gt_clock_utils.o AR drivers/media/common/videobuf2/built-in.a AR drivers/media/pci/pt3/built-in.a AR drivers/media/common/built-in.a AR drivers/media/pci/mantis/built-in.a AR drivers/media/platform/aspeed/built-in.a AR drivers/media/pci/ngene/built-in.a AR drivers/media/platform/atmel/built-in.a AR drivers/media/platform/broadcom/built-in.a CC [M] drivers/gpu/drm/xe/xe_guc_debugfs.o AR drivers/media/pci/ddbridge/built-in.a AR drivers/media/platform/cadence/built-in.a CC drivers/ptp/ptp_clock.o CC drivers/ptp/ptp_chardev.o AR drivers/media/pci/saa7146/built-in.a AR drivers/rtc/built-in.a AR drivers/media/platform/chips-media/coda/built-in.a AR drivers/media/platform/chips-media/wave5/built-in.a AR drivers/media/pci/smipcie/built-in.a AR drivers/media/platform/chips-media/built-in.a AR drivers/media/pci/netup_unidvb/built-in.a CC [M] drivers/gpu/drm/xe/xe_guc_hwconfig.o CC [M] drivers/gpu/drm/xe/xe_guc_id_mgr.o AR drivers/media/pci/intel/ipu3/built-in.a AR drivers/media/platform/intel/built-in.a AR drivers/media/pci/intel/ivsc/built-in.a AR drivers/media/platform/marvell/built-in.a AR drivers/media/pci/intel/built-in.a AR drivers/media/platform/mediatek/jpeg/built-in.a AR drivers/media/pci/built-in.a CC drivers/gpu/drm/i915/gt/intel_gt_debugfs.o AR drivers/media/platform/mediatek/mdp/built-in.a CC drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.o AR drivers/media/platform/mediatek/vcodec/common/built-in.a AR drivers/media/platform/mediatek/vcodec/encoder/built-in.a AR drivers/media/platform/mediatek/vcodec/decoder/built-in.a AR drivers/media/platform/mediatek/vcodec/built-in.a CC drivers/pps/sysfs.o CC net/ipv4/tcp_cubic.o AR drivers/media/platform/mediatek/vpu/built-in.a AR drivers/media/platform/mediatek/mdp3/built-in.a AR drivers/media/platform/mediatek/built-in.a CC drivers/power/supply/power_supply_core.o CC net/ipv4/tcp_sigpool.o AR drivers/media/platform/microchip/built-in.a AR drivers/media/platform/nuvoton/built-in.a AR drivers/media/platform/nvidia/tegra-vde/built-in.a AR drivers/media/platform/nvidia/built-in.a AR drivers/media/platform/nxp/dw100/built-in.a AR drivers/media/platform/nxp/imx-jpeg/built-in.a CC drivers/power/supply/power_supply_sysfs.o AR drivers/media/platform/nxp/imx8-isi/built-in.a AR drivers/media/platform/nxp/built-in.a CC drivers/gpu/drm/drm_property.o AR drivers/media/platform/qcom/camss/built-in.a AR drivers/media/platform/renesas/rcar-vin/built-in.a AR drivers/input/built-in.a CC net/ipv4/cipso_ipv4.o CC drivers/usb/host/xhci-ring.o AR drivers/media/platform/qcom/venus/built-in.a AR drivers/media/platform/renesas/rzg2l-cru/built-in.a AR drivers/media/platform/qcom/built-in.a CC drivers/power/supply/power_supply_leds.o AR drivers/media/platform/renesas/vsp1/built-in.a CC net/ipv4/xfrm4_policy.o AR drivers/media/platform/renesas/built-in.a CC drivers/usb/host/xhci-hub.o AR drivers/media/usb/b2c2/built-in.a AR drivers/media/usb/dvb-usb/built-in.a CC drivers/usb/host/xhci-dbg.o AR drivers/media/platform/rockchip/rga/built-in.a AR drivers/media/platform/rockchip/rkisp1/built-in.a AR drivers/media/platform/samsung/exynos-gsc/built-in.a CC drivers/usb/host/xhci-trace.o AR drivers/media/platform/rockchip/built-in.a AR drivers/media/usb/dvb-usb-v2/built-in.a CC drivers/usb/host/xhci-debugfs.o AR drivers/media/platform/samsung/exynos4-is/built-in.a CC net/ipv4/xfrm4_state.o CC [M] drivers/gpu/drm/xe/xe_guc_klv_helpers.o AR drivers/media/usb/s2255/built-in.a AR drivers/media/platform/samsung/s3c-camif/built-in.a AR drivers/media/usb/siano/built-in.a AR drivers/media/platform/samsung/s5p-g2d/built-in.a AR drivers/media/usb/ttusb-budget/built-in.a AR drivers/media/usb/ttusb-dec/built-in.a AR drivers/media/platform/samsung/s5p-jpeg/built-in.a CC net/ipv4/xfrm4_input.o AR drivers/media/usb/built-in.a AR drivers/media/platform/samsung/s5p-mfc/built-in.a AR drivers/pps/built-in.a AR drivers/media/platform/samsung/built-in.a CC [M] drivers/gpu/drm/xe/xe_guc_log.o CC [M] drivers/gpu/drm/xe/xe_guc_pc.o AR drivers/media/mmc/siano/built-in.a AR drivers/media/mmc/built-in.a CC [M] drivers/gpu/drm/xe/xe_guc_submit.o CC [M] drivers/gpu/drm/xe/xe_heci_gsc.o CC drivers/gpu/drm/drm_syncobj.o AR drivers/media/platform/st/sti/bdisp/built-in.a CC drivers/gpu/drm/drm_sysfs.o AR drivers/media/platform/st/sti/c8sectpfe/built-in.a AR drivers/media/platform/st/sti/delta/built-in.a CC drivers/gpu/drm/i915/gt/intel_gt_irq.o AR drivers/media/platform/sunxi/sun4i-csi/built-in.a CC drivers/gpu/drm/i915/gt/intel_gt_mcr.o AR drivers/media/platform/st/sti/hva/built-in.a AR drivers/media/platform/sunxi/sun6i-csi/built-in.a AR drivers/media/platform/st/stm32/built-in.a AR drivers/media/platform/st/built-in.a AR drivers/media/platform/sunxi/sun6i-mipi-csi2/built-in.a CC drivers/gpu/drm/drm_trace_points.o AR drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/built-in.a CC [M] drivers/gpu/drm/xe/xe_hw_engine.o AR drivers/media/platform/sunxi/sun8i-di/built-in.a AR drivers/net/ethernet/oki-semi/built-in.a CC drivers/gpu/drm/i915/gt/intel_gt_pm.o AR drivers/media/platform/sunxi/sun8i-rotate/built-in.a AR drivers/net/ethernet/packetengines/built-in.a AR drivers/media/platform/sunxi/built-in.a AR drivers/media/firewire/built-in.a CC net/ipv4/xfrm4_output.o AR drivers/media/spi/built-in.a CC drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.o CC drivers/gpu/drm/drm_vblank.o AR drivers/media/test-drivers/built-in.a AR drivers/media/platform/ti/am437x/built-in.a CC drivers/gpu/drm/i915/gt/intel_gt_pm_irq.o CC drivers/gpu/drm/i915/gt/intel_gt_requests.o AR drivers/media/platform/ti/vpe/built-in.a AR drivers/media/platform/ti/cal/built-in.a CC net/ipv4/xfrm4_protocol.o CC drivers/gpu/drm/i915/gt/intel_gt_sysfs.o AR drivers/media/platform/ti/davinci/built-in.a CC drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.o AR drivers/media/platform/ti/j721e-csi2rx/built-in.a CC drivers/power/supply/power_supply_hwmon.o AR drivers/media/platform/ti/omap/built-in.a AR drivers/media/platform/ti/omap3isp/built-in.a AR drivers/media/platform/verisilicon/built-in.a AR drivers/media/platform/ti/built-in.a CC drivers/gpu/drm/drm_vblank_work.o AR drivers/i2c/built-in.a AR drivers/media/platform/via/built-in.a CC drivers/gpu/drm/i915/gt/intel_gtt.o CC drivers/usb/host/xhci-pci.o CC drivers/hwmon/hwmon.o AR drivers/media/platform/xilinx/built-in.a CC drivers/ptp/ptp_sysfs.o AR drivers/media/platform/built-in.a CC drivers/gpu/drm/i915/gt/intel_llc.o CC drivers/gpu/drm/drm_vma_manager.o AR drivers/thermal/broadcom/built-in.a AR drivers/thermal/samsung/built-in.a AR net/mac80211/built-in.a AR drivers/media/built-in.a CC drivers/gpu/drm/i915/gt/intel_lrc.o CC drivers/gpu/drm/drm_writeback.o CC drivers/thermal/intel/intel_tcc.o CC drivers/thermal/intel/therm_throt.o CC drivers/gpu/drm/drm_panel.o AR drivers/watchdog/built-in.a CC drivers/gpu/drm/drm_pci.o CC [M] drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.o CC drivers/md/md.o AR drivers/power/supply/built-in.a CC drivers/cpufreq/cpufreq.o AR drivers/power/built-in.a CC drivers/md/md-bitmap.o CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.o CC drivers/cpufreq/freq_table.o CC drivers/cpufreq/cpufreq_performance.o CC drivers/ptp/ptp_vclock.o AR drivers/thermal/st/built-in.a CC drivers/gpu/drm/drm_debugfs.o CC [M] drivers/gpu/drm/xe/xe_hw_fence.o CC drivers/gpu/drm/drm_debugfs_crc.o CC drivers/cpuidle/governors/menu.o CC drivers/cpuidle/cpuidle.o CC [M] drivers/gpu/drm/xe/xe_huc.o CC drivers/gpu/drm/drm_panel_orientation_quirks.o AR drivers/mmc/built-in.a CC [M] drivers/gpu/drm/xe/xe_huc_debugfs.o CC drivers/gpu/drm/i915/gt/intel_migrate.o CC drivers/gpu/drm/i915/gt/intel_mocs.o CC drivers/gpu/drm/i915/gt/intel_ppgtt.o CC drivers/gpu/drm/i915/gt/intel_rc6.o CC drivers/ptp/ptp_kvm_x86.o CC drivers/gpu/drm/i915/gt/intel_region_lmem.o CC drivers/gpu/drm/drm_buddy.o CC drivers/cpufreq/cpufreq_userspace.o CC drivers/gpu/drm/drm_gem_shmem_helper.o CC drivers/cpufreq/cpufreq_ondemand.o CC drivers/gpu/drm/i915/gt/intel_renderstate.o CC drivers/md/md-autodetect.o CC drivers/ptp/ptp_kvm_common.o CC drivers/gpu/drm/drm_atomic_helper.o CC drivers/gpu/drm/i915/gt/intel_reset.o CC drivers/gpu/drm/drm_atomic_state_helper.o CC drivers/cpufreq/cpufreq_governor.o AR drivers/thermal/qcom/built-in.a CC drivers/cpuidle/governors/haltpoll.o CC drivers/gpu/drm/i915/gt/intel_ring.o CC [M] drivers/gpu/drm/xe/xe_irq.o AR net/ipv4/built-in.a AR net/built-in.a AR drivers/hwmon/built-in.a AR drivers/ufs/built-in.a AR drivers/leds/trigger/built-in.a AR drivers/firmware/arm_ffa/built-in.a AR drivers/net/ethernet/qlogic/built-in.a AR drivers/crypto/stm32/built-in.a AR drivers/leds/blink/built-in.a AR drivers/firmware/arm_scmi/built-in.a AR drivers/crypto/xilinx/built-in.a AR drivers/leds/simple/built-in.a CC drivers/leds/led-core.o CC [M] drivers/gpu/drm/xe/xe_lrc.o AR drivers/firmware/broadcom/built-in.a AR drivers/crypto/hisilicon/built-in.a CC [M] drivers/gpu/drm/xe/xe_migrate.o AR drivers/crypto/starfive/built-in.a AR drivers/firmware/cirrus/built-in.a CC drivers/gpu/drm/i915/gt/intel_ring_submission.o AR drivers/crypto/intel/keembay/built-in.a CC drivers/gpu/drm/i915/gt/intel_rps.o AR drivers/firmware/meson/built-in.a AR drivers/crypto/intel/ixp4xx/built-in.a CC [M] drivers/gpu/drm/xe/xe_mmio.o AR drivers/crypto/intel/built-in.a AR drivers/firmware/microchip/built-in.a CC drivers/cpufreq/cpufreq_governor_attr_set.o AR drivers/firmware/imx/built-in.a AR drivers/crypto/built-in.a CC drivers/gpu/drm/drm_bridge_connector.o CC drivers/firmware/efi/efi-bgrt.o AR drivers/thermal/intel/built-in.a AR drivers/firmware/psci/built-in.a CC [M] drivers/gpu/drm/xe/xe_mocs.o CC drivers/gpu/drm/i915/gt/intel_sa_media.o AR drivers/thermal/tegra/built-in.a CC drivers/firmware/efi/libstub/efi-stub-helper.o CC drivers/gpu/drm/i915/gt/intel_sseu.o AR drivers/thermal/mediatek/built-in.a CC drivers/thermal/thermal_core.o CC drivers/gpu/drm/drm_crtc_helper.o CC [M] drivers/gpu/drm/xe/xe_module.o AR drivers/firmware/qcom/built-in.a AR drivers/firmware/smccc/built-in.a AR drivers/firmware/tegra/built-in.a CC drivers/gpu/drm/drm_damage_helper.o CC drivers/clocksource/acpi_pm.o AR drivers/net/ethernet/nvidia/built-in.a CC drivers/gpu/drm/drm_encoder_slave.o CC drivers/hid/usbhid/hid-core.o CC drivers/hid/hid-core.o CC drivers/hid/usbhid/hiddev.o AR drivers/ptp/built-in.a CC drivers/cpufreq/acpi-cpufreq.o AR drivers/platform/x86/amd/built-in.a AR drivers/platform/x86/intel/built-in.a CC drivers/platform/x86/wmi.o AR drivers/platform/surface/built-in.a CC drivers/cpufreq/amd-pstate.o CC drivers/leds/led-class.o CC drivers/platform/x86/wmi-bmof.o CC drivers/cpufreq/amd-pstate-trace.o CC drivers/clocksource/i8253.o CC drivers/platform/x86/eeepc-laptop.o CC drivers/cpuidle/driver.o CC drivers/leds/led-triggers.o CC drivers/gpu/drm/drm_flip_work.o CC drivers/gpu/drm/drm_format_helper.o AR drivers/usb/host/built-in.a CC drivers/gpu/drm/i915/gt/intel_sseu_debugfs.o AR drivers/usb/built-in.a CC drivers/md/dm.o CC [M] drivers/gpu/drm/xe/xe_pat.o CC drivers/mailbox/mailbox.o CC [M] drivers/gpu/drm/xe/xe_pci.o CC drivers/mailbox/pcc.o AR drivers/cpuidle/governors/built-in.a CC drivers/gpu/drm/i915/gt/intel_timeline.o CC [M] drivers/gpu/drm/xe/xe_pcode.o CC drivers/hid/usbhid/hid-pidff.o AR drivers/net/ethernet/qualcomm/emac/built-in.a AR drivers/net/ethernet/qualcomm/built-in.a CC drivers/md/dm-table.o AR drivers/firmware/xilinx/built-in.a CC drivers/hid/hid-input.o CC drivers/firmware/efi/efi.o CC drivers/firmware/efi/libstub/gop.o CC drivers/hid/hid-quirks.o AR drivers/clocksource/built-in.a AR drivers/net/ethernet/intel/e1000e/built-in.a CC drivers/gpu/drm/drm_gem_atomic_helper.o AR drivers/net/ethernet/intel/built-in.a CC drivers/gpu/drm/drm_gem_framebuffer_helper.o CC drivers/hid/hid-debug.o CC drivers/cpufreq/intel_pstate.o CC drivers/gpu/drm/i915/gt/intel_tlb.o CC drivers/firmware/efi/vars.o CC drivers/cpuidle/governor.o CC drivers/cpuidle/sysfs.o CC drivers/firmware/efi/libstub/secureboot.o CC drivers/platform/x86/p2sb.o CC drivers/gpu/drm/drm_kms_helper_common.o CC [M] drivers/gpu/drm/xe/xe_pm.o AR drivers/leds/built-in.a AR drivers/perf/built-in.a CC [M] drivers/gpu/drm/xe/xe_preempt_fence.o CC drivers/gpu/drm/drm_modeset_helper.o AR drivers/hwtracing/intel_th/built-in.a CC [M] drivers/gpu/drm/xe/xe_pt.o CC [M] drivers/gpu/drm/xe/xe_pt_walk.o CC drivers/firmware/efi/reboot.o CC drivers/firmware/efi/libstub/tpm.o CC drivers/gpu/drm/drm_plane_helper.o CC drivers/md/dm-target.o AR drivers/mailbox/built-in.a AR drivers/android/built-in.a CC drivers/gpu/drm/i915/gt/intel_wopcm.o AR drivers/nvmem/layouts/built-in.a AR drivers/net/ethernet/broadcom/built-in.a CC drivers/cpuidle/poll_state.o CC drivers/nvmem/core.o CC [M] drivers/gpu/drm/xe/xe_query.o CC drivers/net/ethernet/realtek/8139too.o CC drivers/cpuidle/cpuidle-haltpoll.o CC drivers/md/dm-linear.o CC drivers/thermal/thermal_trip.o CC drivers/thermal/thermal_sysfs.o CC drivers/thermal/thermal_helpers.o CC drivers/net/ethernet/realtek/r8169_main.o CC drivers/thermal/thermal_hwmon.o CC drivers/net/ethernet/realtek/r8169_firmware.o CC drivers/firmware/efi/memattr.o CC drivers/firmware/efi/tpm.o AR drivers/net/ethernet/renesas/built-in.a CC drivers/gpu/drm/drm_probe_helper.o CC drivers/hid/hidraw.o AR drivers/net/ethernet/rdc/built-in.a CC drivers/gpu/drm/drm_rect.o AR drivers/net/ethernet/rocker/built-in.a CC drivers/hid/hid-generic.o CC drivers/thermal/gov_step_wise.o CC drivers/hid/hid-a4tech.o CC drivers/firmware/efi/memmap.o CC drivers/firmware/efi/libstub/file.o CC drivers/hid/hid-apple.o AR drivers/platform/x86/built-in.a AR drivers/platform/built-in.a CC drivers/firmware/dmi_scan.o AR drivers/hid/usbhid/built-in.a CC drivers/hid/hid-belkin.o CC drivers/md/dm-stripe.o CC drivers/firmware/efi/capsule.o CC drivers/thermal/gov_user_space.o CC [M] drivers/gpu/drm/xe/xe_range_fence.o CC drivers/hid/hid-cherry.o CC drivers/gpu/drm/i915/gt/intel_workarounds.o CC drivers/firmware/dmi-id.o CC drivers/hid/hid-chicony.o AR drivers/cpuidle/built-in.a CC drivers/hid/hid-cypress.o CC drivers/gpu/drm/drm_self_refresh_helper.o CC drivers/net/ethernet/realtek/r8169_phy_config.o CC drivers/firmware/memmap.o AR drivers/net/ethernet/samsung/built-in.a CC [M] drivers/gpu/drm/xe/xe_reg_sr.o CC drivers/gpu/drm/i915/gt/shmem_utils.o CC drivers/firmware/efi/libstub/mem.o CC drivers/firmware/efi/libstub/random.o CC drivers/gpu/drm/i915/gt/sysfs_engines.o AR drivers/net/ethernet/seeq/built-in.a CC [M] drivers/gpu/drm/xe/xe_reg_whitelist.o CC [M] drivers/gpu/drm/xe/xe_rtp.o CC [M] drivers/gpu/drm/xe/xe_ring_ops.o CC drivers/hid/hid-ezkey.o AR drivers/net/ethernet/silan/built-in.a AR drivers/net/ethernet/sfc/built-in.a AR drivers/net/ethernet/sis/built-in.a AR drivers/net/ethernet/smsc/built-in.a AR drivers/net/ethernet/socionext/built-in.a CC drivers/gpu/drm/i915/gt/intel_ggtt_gmch.o AR drivers/net/ethernet/stmicro/built-in.a AR drivers/net/ethernet/sun/built-in.a AR drivers/net/ethernet/tehuti/built-in.a AR drivers/net/ethernet/ti/built-in.a AR drivers/net/ethernet/via/built-in.a AR drivers/net/ethernet/vertexcom/built-in.a CC drivers/firmware/efi/esrt.o AR drivers/net/ethernet/wangxun/built-in.a AR drivers/net/ethernet/wiznet/built-in.a CC drivers/md/dm-ioctl.o AR drivers/net/ethernet/xilinx/built-in.a AR drivers/thermal/built-in.a CC drivers/md/dm-io.o CC drivers/hid/hid-gyration.o CC drivers/firmware/efi/runtime-wrappers.o CC drivers/gpu/drm/drm_simple_kms_helper.o CC drivers/hid/hid-ite.o CC drivers/hid/hid-kensington.o CC drivers/md/dm-kcopyd.o CC drivers/hid/hid-lg.o CC drivers/hid/hid-lgff.o CC drivers/firmware/efi/libstub/randomalloc.o CC drivers/firmware/efi/capsule-loader.o AR drivers/net/ethernet/xircom/built-in.a CC [M] drivers/gpu/drm/xe/xe_sa.o AR drivers/net/ethernet/synopsys/built-in.a AR drivers/nvmem/built-in.a CC [M] drivers/gpu/drm/xe/xe_sched_job.o AR drivers/net/ethernet/pensando/built-in.a CC drivers/firmware/efi/libstub/pci.o CC [M] drivers/gpu/drm/xe/xe_step.o CC drivers/hid/hid-lg4ff.o CC drivers/hid/hid-lg-g15.o CC drivers/firmware/efi/earlycon.o CC drivers/gpu/drm/bridge/panel.o CC [M] drivers/gpu/drm/xe/xe_sync.o CC [M] drivers/gpu/drm/xe/xe_tile.o CC drivers/md/dm-sysfs.o CC drivers/hid/hid-microsoft.o CC drivers/md/dm-stats.o CC drivers/hid/hid-monterey.o CC drivers/firmware/efi/libstub/skip_spaces.o CC drivers/md/dm-rq.o CC drivers/hid/hid-ntrig.o CC drivers/hid/hid-pl.o CC drivers/md/dm-io-rewind.o CC drivers/firmware/efi/libstub/lib-cmdline.o CC drivers/hid/hid-petalynx.o CC [M] drivers/gpu/drm/xe/xe_tile_sysfs.o CC drivers/hid/hid-redragon.o CC drivers/hid/hid-samsung.o CC drivers/firmware/efi/libstub/lib-ctype.o CC drivers/firmware/efi/libstub/alignedmem.o AR drivers/cpufreq/built-in.a CC drivers/hid/hid-sony.o CC [M] drivers/gpu/drm/xe/xe_trace.o CC drivers/md/dm-builtin.o CC drivers/md/dm-raid1.o CC [M] drivers/gpu/drm/xe/xe_ttm_sys_mgr.o CC drivers/hid/hid-sunplus.o CC drivers/gpu/drm/i915/gt/gen6_renderstate.o CC drivers/hid/hid-topseed.o CC drivers/gpu/drm/drm_mipi_dsi.o CC drivers/gpu/drm/i915/gt/gen7_renderstate.o CC drivers/firmware/efi/libstub/relocate.o CC drivers/gpu/drm/i915/gt/gen8_renderstate.o CC drivers/gpu/drm/i915/gt/gen9_renderstate.o CC drivers/gpu/drm/i915/gem/i915_gem_busy.o CC [M] drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o CC drivers/gpu/drm/i915/gem/i915_gem_clflush.o CC drivers/gpu/drm/i915/gem/i915_gem_context.o CC drivers/md/dm-log.o CC drivers/firmware/efi/libstub/printk.o CC [M] drivers/gpu/drm/xe/xe_ttm_vram_mgr.o CC [M] drivers/gpu/drm/xe/xe_tuning.o AR drivers/firmware/efi/built-in.a CC [M] drivers/gpu/drm/drm_exec.o CC [M] drivers/gpu/drm/drm_gpuvm.o CC [M] drivers/gpu/drm/xe/xe_uc.o CC [M] drivers/gpu/drm/xe/xe_uc_debugfs.o CC drivers/gpu/drm/i915/gem/i915_gem_create.o CC drivers/md/dm-region-hash.o CC drivers/md/dm-zero.o CC drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o CC [M] drivers/gpu/drm/drm_suballoc.o CC drivers/gpu/drm/i915/gem/i915_gem_domain.o CC drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o CC drivers/gpu/drm/i915/gem/i915_gem_internal.o CC [M] drivers/gpu/drm/xe/xe_uc_fw.o CC drivers/firmware/efi/libstub/vsprintf.o CC [M] drivers/gpu/drm/xe/xe_vm.o CC [M] drivers/gpu/drm/drm_gem_ttm_helper.o CC drivers/firmware/efi/libstub/x86-stub.o CC [M] drivers/gpu/drm/xe/xe_vram.o CC drivers/gpu/drm/i915/gem/i915_gem_lmem.o CC [M] drivers/gpu/drm/xe/xe_vram_freq.o CC [M] drivers/gpu/drm/xe/xe_wait_user_fence.o CC [M] drivers/gpu/drm/xe/xe_wa.o CC [M] drivers/gpu/drm/xe/xe_wopcm.o CC [M] drivers/gpu/drm/xe/xe_hmm.o CC [M] drivers/gpu/drm/xe/xe_hwmon.o CC drivers/gpu/drm/i915/gem/i915_gem_mman.o STUBCPY drivers/firmware/efi/libstub/alignedmem.stub.o STUBCPY drivers/firmware/efi/libstub/efi-stub-helper.stub.o CC drivers/gpu/drm/i915/gem/i915_gem_object.o CC [M] drivers/gpu/drm/xe/xe_gt_sriov_vf.o CC [M] drivers/gpu/drm/xe/xe_gt_sriov_vf_debugfs.o CC [M] drivers/gpu/drm/xe/xe_guc_relay.o CC [M] drivers/gpu/drm/xe/xe_memirq.o CC [M] drivers/gpu/drm/xe/xe_sriov.o CC [M] drivers/gpu/drm/xe/display/ext/i915_irq.o STUBCPY drivers/firmware/efi/libstub/file.stub.o CC [M] drivers/gpu/drm/xe/display/ext/i915_utils.o STUBCPY drivers/firmware/efi/libstub/gop.stub.o CC [M] drivers/gpu/drm/xe/display/intel_fb_bo.o STUBCPY drivers/firmware/efi/libstub/lib-cmdline.stub.o CC drivers/gpu/drm/i915/gem/i915_gem_pages.o CC drivers/gpu/drm/i915/gem/i915_gem_phys.o CC [M] drivers/gpu/drm/xe/display/intel_fbdev_fb.o CC drivers/gpu/drm/i915/gem/i915_gem_pm.o STUBCPY drivers/firmware/efi/libstub/lib-ctype.stub.o STUBCPY drivers/firmware/efi/libstub/mem.stub.o STUBCPY drivers/firmware/efi/libstub/pci.stub.o STUBCPY drivers/firmware/efi/libstub/printk.stub.o CC drivers/gpu/drm/i915/gem/i915_gem_region.o STUBCPY drivers/firmware/efi/libstub/random.stub.o CC [M] drivers/gpu/drm/xe/display/xe_display.o STUBCPY drivers/firmware/efi/libstub/randomalloc.stub.o CC drivers/gpu/drm/i915/gem/i915_gem_shmem.o STUBCPY drivers/firmware/efi/libstub/relocate.stub.o STUBCPY drivers/firmware/efi/libstub/secureboot.stub.o STUBCPY drivers/firmware/efi/libstub/skip_spaces.stub.o CC [M] drivers/gpu/drm/xe/display/xe_display_misc.o STUBCPY drivers/firmware/efi/libstub/tpm.stub.o STUBCPY drivers/firmware/efi/libstub/vsprintf.stub.o AR drivers/hid/built-in.a LD [M] drivers/gpu/drm/drm_suballoc_helper.o CC [M] drivers/gpu/drm/xe/display/xe_display_rps.o CC drivers/gpu/drm/i915/gem/i915_gem_shrinker.o LD [M] drivers/gpu/drm/drm_ttm_helper.o CC drivers/gpu/drm/i915/gem/i915_gem_stolen.o CC [M] drivers/gpu/drm/xe/display/xe_dsb_buffer.o CC drivers/gpu/drm/i915/gem/i915_gem_throttle.o CC [M] drivers/gpu/drm/xe/display/xe_fb_pin.o CC [M] drivers/gpu/drm/xe/display/xe_hdcp_gsc.o CC [M] drivers/gpu/drm/xe/display/xe_plane_initial.o AR drivers/net/ethernet/realtek/built-in.a CC [M] drivers/gpu/drm/xe/display/xe_tdf.o CC drivers/gpu/drm/i915/gem/i915_gem_tiling.o AR drivers/net/ethernet/built-in.a CC [M] drivers/gpu/drm/xe/i915-soc/intel_dram.o AR drivers/md/built-in.a CC [M] drivers/gpu/drm/xe/i915-soc/intel_pch.o CC [M] drivers/gpu/drm/xe/i915-display/icl_dsi.o CC [M] drivers/gpu/drm/xe/i915-display/intel_alpm.o STUBCPY drivers/firmware/efi/libstub/x86-stub.stub.o AR drivers/firmware/efi/libstub/lib.a CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic.o AR drivers/firmware/built-in.a AR drivers/net/built-in.a CC drivers/gpu/drm/i915/gem/i915_gem_ttm.o CC drivers/gpu/drm/i915/gem/i915_gem_ttm_move.o CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic_plane.o CC drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.o CC [M] drivers/gpu/drm/xe/i915-display/intel_audio.o CC [M] drivers/gpu/drm/xe/i915-display/intel_backlight.o CC [M] drivers/gpu/drm/xe/i915-display/intel_bios.o CC [M] drivers/gpu/drm/xe/i915-display/intel_bw.o CC [M] drivers/gpu/drm/xe/i915-display/intel_cdclk.o CC drivers/gpu/drm/i915/gem/i915_gem_userptr.o CC drivers/gpu/drm/i915/gem/i915_gem_wait.o CC drivers/gpu/drm/i915/gem/i915_gemfs.o CC drivers/gpu/drm/i915/i915_active.o CC [M] drivers/gpu/drm/xe/i915-display/intel_color.o CC drivers/gpu/drm/i915/i915_cmd_parser.o CC [M] drivers/gpu/drm/xe/i915-display/intel_combo_phy.o CC [M] drivers/gpu/drm/xe/i915-display/intel_connector.o CC drivers/gpu/drm/i915/i915_deps.o CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc_state_dump.o CC [M] drivers/gpu/drm/xe/i915-display/intel_cursor.o CC [M] drivers/gpu/drm/xe/i915-display/intel_cx0_phy.o CC drivers/gpu/drm/i915/i915_gem.o CC drivers/gpu/drm/i915/i915_gem_evict.o CC drivers/gpu/drm/i915/i915_gem_gtt.o CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi.o CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi_buf_trans.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display.o CC drivers/gpu/drm/i915/i915_gem_ww.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_device.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_driver.o CC drivers/gpu/drm/i915/i915_query.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_irq.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_params.o CC drivers/gpu/drm/i915/i915_request.o CC drivers/gpu/drm/i915/i915_scheduler.o CC drivers/gpu/drm/i915/i915_trace_points.o CC drivers/gpu/drm/i915/i915_ttm_buddy_manager.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power.o CC drivers/gpu/drm/i915/i915_vma.o CC drivers/gpu/drm/i915/i915_vma_resource.o CC drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_map.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_well.o CC drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.o CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.o CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.o CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.o CC drivers/gpu/drm/i915/gt/uc/intel_guc.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_trace.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_ct.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_wa.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dkl_phy.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_fw.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux_backlight.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_log.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_hdcp.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_link_training.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_mst.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_rc.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll_mgr.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o CC drivers/gpu/drm/i915/gt/uc/intel_huc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dpt_common.o CC drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.o CC drivers/gpu/drm/i915/gt/uc/intel_huc_fw.o CC [M] drivers/gpu/drm/xe/i915-display/intel_drrs.o CC drivers/gpu/drm/i915/gt/uc/intel_uc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dsb.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi.o CC drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.o CC drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o CC drivers/gpu/drm/i915/gt/intel_gsc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_dcs_backlight.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_vbt.o CC drivers/gpu/drm/i915/i915_hwmon.o CC [M] drivers/gpu/drm/xe/i915-display/intel_fb.o CC drivers/gpu/drm/i915/display/hsw_ips.o CC drivers/gpu/drm/i915/display/i9xx_plane.o CC [M] drivers/gpu/drm/xe/i915-display/intel_fbc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_fdi.o CC drivers/gpu/drm/i915/display/i9xx_wm.o CC drivers/gpu/drm/i915/display/intel_alpm.o CC drivers/gpu/drm/i915/display/intel_atomic.o CC drivers/gpu/drm/i915/display/intel_atomic_plane.o CC drivers/gpu/drm/i915/display/intel_audio.o CC [M] drivers/gpu/drm/xe/i915-display/intel_fifo_underrun.o CC [M] drivers/gpu/drm/xe/i915-display/intel_frontbuffer.o CC drivers/gpu/drm/i915/display/intel_bios.o CC drivers/gpu/drm/i915/display/intel_bw.o CC [M] drivers/gpu/drm/xe/i915-display/intel_global_state.o CC drivers/gpu/drm/i915/display/intel_cdclk.o CC drivers/gpu/drm/i915/display/intel_color.o CC [M] drivers/gpu/drm/xe/i915-display/intel_gmbus.o CC drivers/gpu/drm/i915/display/intel_combo_phy.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp_gsc_message.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hdmi.o CC drivers/gpu/drm/i915/display/intel_connector.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug_irq.o CC drivers/gpu/drm/i915/display/intel_crtc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hti.o CC [M] drivers/gpu/drm/xe/i915-display/intel_link_bw.o CC drivers/gpu/drm/i915/display/intel_crtc_state_dump.o CC drivers/gpu/drm/i915/display/intel_cursor.o CC [M] drivers/gpu/drm/xe/i915-display/intel_lspcon.o CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_lock.o CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_setup.o CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_verify.o CC drivers/gpu/drm/i915/display/intel_display.o CC drivers/gpu/drm/i915/display/intel_display_driver.o CC [M] drivers/gpu/drm/xe/i915-display/intel_panel.o CC [M] drivers/gpu/drm/xe/i915-display/intel_pmdemand.o CC [M] drivers/gpu/drm/xe/i915-display/intel_pps.o CC drivers/gpu/drm/i915/display/intel_display_irq.o CC [M] drivers/gpu/drm/xe/i915-display/intel_psr.o CC drivers/gpu/drm/i915/display/intel_display_params.o CC [M] drivers/gpu/drm/xe/i915-display/intel_qp_tables.o CC drivers/gpu/drm/i915/display/intel_display_power.o CC drivers/gpu/drm/i915/display/intel_display_power_map.o CC [M] drivers/gpu/drm/xe/i915-display/intel_quirks.o CC [M] drivers/gpu/drm/xe/i915-display/intel_snps_phy.o CC [M] drivers/gpu/drm/xe/i915-display/intel_tc.o CC drivers/gpu/drm/i915/display/intel_display_power_well.o CC [M] drivers/gpu/drm/xe/i915-display/intel_vblank.o CC [M] drivers/gpu/drm/xe/i915-display/intel_vdsc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_vga.o CC [M] drivers/gpu/drm/xe/i915-display/intel_vrr.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc_wl.o CC [M] drivers/gpu/drm/xe/i915-display/intel_wm.o CC drivers/gpu/drm/i915/display/intel_display_reset.o CC drivers/gpu/drm/i915/display/intel_display_rps.o CC [M] drivers/gpu/drm/xe/i915-display/skl_scaler.o CC [M] drivers/gpu/drm/xe/i915-display/skl_universal_plane.o CC [M] drivers/gpu/drm/xe/i915-display/skl_watermark.o CC [M] drivers/gpu/drm/xe/i915-display/intel_acpi.o CC [M] drivers/gpu/drm/xe/i915-display/intel_opregion.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs.o CC drivers/gpu/drm/i915/display/intel_display_wa.o CC drivers/gpu/drm/i915/display/intel_dmc.o CC drivers/gpu/drm/i915/display/intel_dmc_wl.o CC drivers/gpu/drm/i915/display/intel_dpio_phy.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs_params.o CC [M] drivers/gpu/drm/xe/i915-display/intel_pipe_crc.o CC drivers/gpu/drm/i915/display/intel_dpll.o CC drivers/gpu/drm/i915/display/intel_dpll_mgr.o CC drivers/gpu/drm/i915/display/intel_dpt.o CC drivers/gpu/drm/i915/display/intel_dpt_common.o CC [M] drivers/gpu/drm/xe/xe_gsc.o CC drivers/gpu/drm/i915/display/intel_drrs.o CC [M] drivers/gpu/drm/xe/xe_guc.o CC [M] drivers/gpu/drm/xe/xe_guc_ads.o CC drivers/gpu/drm/i915/display/intel_dsb.o CC drivers/gpu/drm/i915/display/intel_dsb_buffer.o CC drivers/gpu/drm/i915/display/intel_fb.o CC drivers/gpu/drm/i915/display/intel_fb_bo.o CC drivers/gpu/drm/i915/display/intel_fb_pin.o CC drivers/gpu/drm/i915/display/intel_fbc.o CC drivers/gpu/drm/i915/display/intel_fdi.o CC drivers/gpu/drm/i915/display/intel_fifo_underrun.o CC drivers/gpu/drm/i915/display/intel_frontbuffer.o CC drivers/gpu/drm/i915/display/intel_global_state.o CC drivers/gpu/drm/i915/display/intel_hdcp.o CC drivers/gpu/drm/i915/display/intel_hdcp_gsc.o CC drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.o CC drivers/gpu/drm/i915/display/intel_hotplug.o CC drivers/gpu/drm/i915/display/intel_hotplug_irq.o CC drivers/gpu/drm/i915/display/intel_hti.o CC drivers/gpu/drm/i915/display/intel_link_bw.o CC drivers/gpu/drm/i915/display/intel_load_detect.o CC drivers/gpu/drm/i915/display/intel_lpe_audio.o CC drivers/gpu/drm/i915/display/intel_modeset_lock.o CC drivers/gpu/drm/i915/display/intel_modeset_setup.o CC drivers/gpu/drm/i915/display/intel_modeset_verify.o CC drivers/gpu/drm/i915/display/intel_overlay.o CC drivers/gpu/drm/i915/display/intel_pch_display.o CC drivers/gpu/drm/i915/display/intel_pch_refclk.o CC drivers/gpu/drm/i915/display/intel_plane_initial.o CC drivers/gpu/drm/i915/display/intel_pmdemand.o CC drivers/gpu/drm/i915/display/intel_psr.o CC drivers/gpu/drm/i915/display/intel_quirks.o CC drivers/gpu/drm/i915/display/intel_sprite.o CC drivers/gpu/drm/i915/display/intel_sprite_uapi.o CC drivers/gpu/drm/i915/display/intel_tc.o CC drivers/gpu/drm/i915/display/intel_vblank.o CC drivers/gpu/drm/i915/display/intel_vga.o CC drivers/gpu/drm/i915/display/intel_wm.o CC drivers/gpu/drm/i915/display/skl_scaler.o CC drivers/gpu/drm/i915/display/skl_universal_plane.o CC drivers/gpu/drm/i915/display/skl_watermark.o CC drivers/gpu/drm/i915/display/intel_acpi.o CC drivers/gpu/drm/i915/display/intel_opregion.o CC drivers/gpu/drm/i915/display/intel_display_debugfs.o CC drivers/gpu/drm/i915/display/intel_display_debugfs_params.o CC drivers/gpu/drm/i915/display/intel_pipe_crc.o CC drivers/gpu/drm/i915/display/dvo_ch7017.o CC drivers/gpu/drm/i915/display/dvo_ch7xxx.o CC drivers/gpu/drm/i915/display/dvo_ivch.o CC drivers/gpu/drm/i915/display/dvo_ns2501.o CC drivers/gpu/drm/i915/display/dvo_sil164.o CC drivers/gpu/drm/i915/display/dvo_tfp410.o CC drivers/gpu/drm/i915/display/g4x_dp.o CC drivers/gpu/drm/i915/display/g4x_hdmi.o CC drivers/gpu/drm/i915/display/icl_dsi.o CC drivers/gpu/drm/i915/display/intel_backlight.o CC drivers/gpu/drm/i915/display/intel_crt.o CC drivers/gpu/drm/i915/display/intel_cx0_phy.o CC drivers/gpu/drm/i915/display/intel_ddi.o CC drivers/gpu/drm/i915/display/intel_ddi_buf_trans.o CC drivers/gpu/drm/i915/display/intel_display_device.o CC drivers/gpu/drm/i915/display/intel_display_trace.o CC drivers/gpu/drm/i915/display/intel_dkl_phy.o CC drivers/gpu/drm/i915/display/intel_dp.o CC drivers/gpu/drm/i915/display/intel_dp_aux.o CC drivers/gpu/drm/i915/display/intel_dp_aux_backlight.o CC drivers/gpu/drm/i915/display/intel_dp_hdcp.o CC drivers/gpu/drm/i915/display/intel_dp_link_training.o CC drivers/gpu/drm/i915/display/intel_dp_mst.o CC drivers/gpu/drm/i915/display/intel_dsi.o CC drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.o CC drivers/gpu/drm/i915/display/intel_dsi_vbt.o CC drivers/gpu/drm/i915/display/intel_dvo.o CC drivers/gpu/drm/i915/display/intel_gmbus.o CC drivers/gpu/drm/i915/display/intel_hdmi.o CC drivers/gpu/drm/i915/display/intel_lspcon.o CC drivers/gpu/drm/i915/display/intel_lvds.o LD [M] drivers/gpu/drm/xe/xe.o CC drivers/gpu/drm/i915/display/intel_panel.o CC drivers/gpu/drm/i915/display/intel_pps.o CC drivers/gpu/drm/i915/display/intel_qp_tables.o CC drivers/gpu/drm/i915/display/intel_sdvo.o CC drivers/gpu/drm/i915/display/intel_snps_phy.o CC drivers/gpu/drm/i915/display/intel_tv.o CC drivers/gpu/drm/i915/display/intel_vdsc.o CC drivers/gpu/drm/i915/display/intel_vrr.o CC drivers/gpu/drm/i915/display/vlv_dsi.o CC drivers/gpu/drm/i915/display/vlv_dsi_pll.o CC drivers/gpu/drm/i915/i915_perf.o CC drivers/gpu/drm/i915/pxp/intel_pxp.o CC drivers/gpu/drm/i915/pxp/intel_pxp_huc.o CC drivers/gpu/drm/i915/pxp/intel_pxp_tee.o CC drivers/gpu/drm/i915/i915_gpu_error.o CC drivers/gpu/drm/i915/i915_vgpu.o AR drivers/gpu/drm/i915/built-in.a AR drivers/gpu/drm/built-in.a AR drivers/gpu/built-in.a AR drivers/built-in.a AR built-in.a AR vmlinux.a LD vmlinux.o OBJCOPY modules.builtin.modinfo GEN modules.builtin MODPOST Module.symvers CC .vmlinux.export.o CC [M] fs/efivarfs/efivarfs.mod.o CC [M] drivers/gpu/drm/drm_exec.mod.o CC [M] drivers/gpu/drm/drm_gpuvm.mod.o CC [M] drivers/gpu/drm/drm_suballoc_helper.mod.o CC [M] drivers/gpu/drm/drm_ttm_helper.mod.o CC [M] drivers/gpu/drm/scheduler/gpu-sched.mod.o CC [M] drivers/gpu/drm/xe/xe.mod.o CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.mod.o CC [M] sound/core/snd-hwdep.mod.o CC [M] sound/core/snd-pcm.mod.o CC [M] sound/pci/hda/snd-hda-codec.mod.o CC [M] sound/pci/hda/snd-hda-codec-hdmi.mod.o CC [M] sound/pci/hda/snd-hda-intel.mod.o CC [M] sound/hda/snd-hda-core.mod.o CC [M] sound/hda/snd-intel-dspcfg.mod.o CC [M] sound/hda/snd-intel-sdw-acpi.mod.o CC [M] net/netfilter/nf_log_syslog.mod.o CC [M] net/netfilter/xt_mark.mod.o CC [M] net/netfilter/xt_nat.mod.o CC [M] net/netfilter/xt_LOG.mod.o CC [M] net/netfilter/xt_addrtype.mod.o CC [M] net/netfilter/xt_MASQUERADE.mod.o CC [M] net/ipv4/netfilter/iptable_nat.mod.o LD [M] drivers/gpu/drm/drm_suballoc_helper.ko LD [M] drivers/gpu/drm/drm_ttm_helper.ko LD [M] net/netfilter/xt_mark.ko LD [M] net/netfilter/xt_LOG.ko LD [M] net/netfilter/nf_log_syslog.ko LD [M] drivers/gpu/drm/scheduler/gpu-sched.ko LD [M] drivers/gpu/drm/drm_exec.ko LD [M] sound/pci/hda/snd-hda-codec.ko LD [M] sound/pci/hda/snd-hda-intel.ko LD [M] net/netfilter/xt_nat.ko LD [M] net/ipv4/netfilter/iptable_nat.ko LD [M] fs/efivarfs/efivarfs.ko LD [M] net/netfilter/xt_addrtype.ko LD [M] net/netfilter/xt_MASQUERADE.ko LD [M] sound/pci/hda/snd-hda-codec-hdmi.ko LD [M] sound/core/snd-pcm.ko LD [M] sound/core/snd-hwdep.ko LD [M] sound/hda/snd-hda-core.ko LD [M] drivers/gpu/drm/drm_gpuvm.ko LD [M] drivers/gpu/drm/xe/xe.ko LD [M] sound/hda/snd-intel-dspcfg.ko LD [M] sound/hda/snd-intel-sdw-acpi.ko LD [M] drivers/thermal/intel/x86_pkg_temp_thermal.ko UPD include/generated/utsversion.h CC init/version-timestamp.o LD .tmp_vmlinux.kallsyms1 NM .tmp_vmlinux.kallsyms1.syms KSYMS .tmp_vmlinux.kallsyms1.S AS .tmp_vmlinux.kallsyms1.o LD .tmp_vmlinux.kallsyms2 NM .tmp_vmlinux.kallsyms2.syms KSYMS .tmp_vmlinux.kallsyms2.S AS .tmp_vmlinux.kallsyms2.o LD vmlinux NM System.map SORTTAB vmlinux RELOCS arch/x86/boot/compressed/vmlinux.relocs RSTRIP vmlinux CC arch/x86/boot/a20.o AS arch/x86/boot/bioscall.o CC arch/x86/boot/cmdline.o AS arch/x86/boot/copy.o HOSTCC arch/x86/boot/mkcpustr CC arch/x86/boot/cpuflags.o CC arch/x86/boot/cpucheck.o CC arch/x86/boot/early_serial_console.o CC arch/x86/boot/edd.o CC arch/x86/boot/main.o CC arch/x86/boot/memory.o CC arch/x86/boot/pm.o AS arch/x86/boot/pmjump.o CC arch/x86/boot/printf.o CC arch/x86/boot/regs.o CC arch/x86/boot/string.o CC arch/x86/boot/tty.o CC arch/x86/boot/video.o CC arch/x86/boot/video-mode.o CC arch/x86/boot/version.o CC arch/x86/boot/video-vga.o CC arch/x86/boot/video-vesa.o CC arch/x86/boot/video-bios.o HOSTCC arch/x86/boot/tools/build CPUSTR arch/x86/boot/cpustr.h CC arch/x86/boot/cpu.o LDS arch/x86/boot/compressed/vmlinux.lds AS arch/x86/boot/compressed/kernel_info.o AS arch/x86/boot/compressed/head_32.o VOFFSET arch/x86/boot/compressed/../voffset.h CC arch/x86/boot/compressed/string.o CC arch/x86/boot/compressed/cmdline.o CC arch/x86/boot/compressed/error.o OBJCOPY arch/x86/boot/compressed/vmlinux.bin HOSTCC arch/x86/boot/compressed/mkpiggy CC arch/x86/boot/compressed/cpuflags.o CC arch/x86/boot/compressed/early_serial_console.o CC arch/x86/boot/compressed/kaslr.o CC arch/x86/boot/compressed/acpi.o CC arch/x86/boot/compressed/efi.o GZIP arch/x86/boot/compressed/vmlinux.bin.gz CC arch/x86/boot/compressed/misc.o MKPIGGY arch/x86/boot/compressed/piggy.S AS arch/x86/boot/compressed/piggy.o LD arch/x86/boot/compressed/vmlinux ZOFFSET arch/x86/boot/zoffset.h OBJCOPY arch/x86/boot/vmlinux.bin AS arch/x86/boot/header.o LD arch/x86/boot/setup.elf OBJCOPY arch/x86/boot/setup.bin BUILD arch/x86/boot/bzImage Kernel: arch/x86/boot/bzImage is ready (#1) run-parts: executing /workspace/ci/hooks/20-kernel-doc + SRC_DIR=/workspace/kernel + cd /workspace/kernel + find drivers/gpu/drm/xe/ -name '*.[ch]' -not -path 'drivers/gpu/drm/xe/display/*' + xargs ./scripts/kernel-doc -Werror -none include/uapi/drm/xe_drm.h drivers/gpu/drm/xe/xe_hw_engine_types.h:252: warning: expecting prototype for struct xe_hw_engine_snapshot. Prototype was for struct snapshot_regs instead drivers/gpu/drm/xe/xe_guc_log_types.h:46: warning: Function parameter or struct member 'sizes' not described in 'xe_guc_log' drivers/gpu/drm/xe/xe_guc_log_types.h:46: warning: Function parameter or struct member 'sizes_initialised' not described in 'xe_guc_log' drivers/gpu/drm/xe/xe_guc_log_types.h:46: warning: Function parameter or struct member 'stats' not described in 'xe_guc_log' 4 warnings as Errors run-parts: /workspace/ci/hooks/20-kernel-doc exited with return code 123 ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ CI.checksparse: success for drm/xe/guc: Add GuC based register capture for error capture (rev9) 2024-06-07 0:07 [PATCH v9 0/4] drm/xe/guc: Add GuC based register capture for error capture Zhanjun Dong ` (8 preceding siblings ...) 2024-06-07 0:27 ` ✗ CI.Hooks: failure " Patchwork @ 2024-06-07 0:28 ` Patchwork 2024-06-07 1:11 ` ✓ CI.BAT: " Patchwork 2024-06-07 10:57 ` ✗ CI.FULL: failure " Patchwork 11 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-06-07 0:28 UTC (permalink / raw) To: Zhanjun Dong; +Cc: intel-xe == Series Details == Series: drm/xe/guc: Add GuC based register capture for error capture (rev9) URL : https://patchwork.freedesktop.org/series/128077/ State : success == Summary == + trap cleanup EXIT + KERNEL=/kernel + MT=/root/linux/maintainer-tools + git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools Cloning into '/root/linux/maintainer-tools'... warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/ + make -C /root/linux/maintainer-tools make: Entering directory '/root/linux/maintainer-tools' cc -O2 -g -Wextra -o remap-log remap-log.c make: Leaving directory '/root/linux/maintainer-tools' + cd /kernel + git config --global --add safe.directory /kernel + /root/linux/maintainer-tools/dim sparse --fast ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462 Sparse version: 0.6.1 (Ubuntu: 0.6.1-2build1) Fast mode used, each commit won't be checked separately. Okay! + cleanup ++ stat -c %u:%g /kernel + chown -R 1003:1003 /kernel ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ CI.BAT: success for drm/xe/guc: Add GuC based register capture for error capture (rev9) 2024-06-07 0:07 [PATCH v9 0/4] drm/xe/guc: Add GuC based register capture for error capture Zhanjun Dong ` (9 preceding siblings ...) 2024-06-07 0:28 ` ✓ CI.checksparse: success " Patchwork @ 2024-06-07 1:11 ` Patchwork 2024-06-07 10:57 ` ✗ CI.FULL: failure " Patchwork 11 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-06-07 1:11 UTC (permalink / raw) To: Zhanjun Dong; +Cc: intel-xe [-- Attachment #1: Type: text/plain, Size: 4208 bytes --] == Series Details == Series: drm/xe/guc: Add GuC based register capture for error capture (rev9) URL : https://patchwork.freedesktop.org/series/128077/ State : success == Summary == CI Bug Log - changes from xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462_BAT -> xe-pw-128077v9_BAT ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (3 -> 4) ------------------------------ Additional (1): bat-adlp-7 Known issues ------------ Here are the changes found in xe-pw-128077v9_BAT that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_dsc@dsc-basic: - bat-adlp-7: NOTRUN -> [SKIP][1] ([Intel XE#455]) [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/bat-adlp-7/igt@kms_dsc@dsc-basic.html * igt@kms_frontbuffer_tracking@basic: - bat-adlp-7: NOTRUN -> [DMESG-FAIL][2] ([Intel XE#324]) [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html * igt@xe_evict@evict-small-cm: - bat-adlp-7: NOTRUN -> [SKIP][3] ([Intel XE#261] / [Intel XE#688]) +15 other tests skip [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/bat-adlp-7/igt@xe_evict@evict-small-cm.html * igt@xe_evict_ccs@evict-overcommit-simple: - bat-adlp-7: NOTRUN -> [SKIP][4] ([Intel XE#688]) +1 other test skip [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/bat-adlp-7/igt@xe_evict_ccs@evict-overcommit-simple.html * igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch: - bat-adlp-7: NOTRUN -> [SKIP][5] ([Intel XE#288]) +32 other tests skip [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/bat-adlp-7/igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch.html * igt@xe_mmap@vram: - bat-adlp-7: NOTRUN -> [SKIP][6] ([Intel XE#1008]) [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/bat-adlp-7/igt@xe_mmap@vram.html * igt@xe_pat@pat-index-xe2: - bat-adlp-7: NOTRUN -> [SKIP][7] ([Intel XE#977]) [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/bat-adlp-7/igt@xe_pat@pat-index-xe2.html * igt@xe_pat@pat-index-xehpc: - bat-adlp-7: NOTRUN -> [SKIP][8] ([Intel XE#979]) +1 other test skip [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/bat-adlp-7/igt@xe_pat@pat-index-xehpc.html #### Possible fixes #### * igt@xe_exec_compute_mode@twice-bindexecqueue-userptr-invalidate: - {bat-lnl-1}: [FAIL][9] ([Intel XE#1069]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/bat-lnl-1/igt@xe_exec_compute_mode@twice-bindexecqueue-userptr-invalidate.html [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/bat-lnl-1/igt@xe_exec_compute_mode@twice-bindexecqueue-userptr-invalidate.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [Intel XE#1008]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1008 [Intel XE#1069]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1069 [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261 [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288 [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324 [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455 [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688 [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977 [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979 Build changes ------------- * Linux: xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462 -> xe-pw-128077v9 IGT_7880: 73618605b4370cf902267aaf1d25666ff5e26112 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462: ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462 xe-pw-128077v9: 128077v9 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/index.html [-- Attachment #2: Type: text/html, Size: 5054 bytes --] ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ CI.FULL: failure for drm/xe/guc: Add GuC based register capture for error capture (rev9) 2024-06-07 0:07 [PATCH v9 0/4] drm/xe/guc: Add GuC based register capture for error capture Zhanjun Dong ` (10 preceding siblings ...) 2024-06-07 1:11 ` ✓ CI.BAT: " Patchwork @ 2024-06-07 10:57 ` Patchwork 11 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-06-07 10:57 UTC (permalink / raw) To: Zhanjun Dong; +Cc: intel-xe [-- Attachment #1: Type: text/plain, Size: 67593 bytes --] == Series Details == Series: drm/xe/guc: Add GuC based register capture for error capture (rev9) URL : https://patchwork.freedesktop.org/series/128077/ State : failure == Summary == CI Bug Log - changes from xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462_full -> xe-pw-128077v9_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with xe-pw-128077v9_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in xe-pw-128077v9_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (3 -> 3) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in xe-pw-128077v9_full: ### IGT changes ### #### Possible regressions #### * igt@kms_flip@flip-vs-suspend-interruptible@b-dp4: - shard-dg2-set2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-434/igt@kms_flip@flip-vs-suspend-interruptible@b-dp4.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_flip@flip-vs-suspend-interruptible@b-dp4.html #### Warnings #### * igt@kms_vblank@ts-continuation-suspend@pipe-d-hdmi-a-1: - shard-adlp: [DMESG-FAIL][3] ([Intel XE#1608]) -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-adlp-8/igt@kms_vblank@ts-continuation-suspend@pipe-d-hdmi-a-1.html [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-2/igt@kms_vblank@ts-continuation-suspend@pipe-d-hdmi-a-1.html Known issues ------------ Here are the changes found in xe-pw-128077v9_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-6: - shard-dg2-set2: [PASS][5] -> [FAIL][6] ([Intel XE#827]) +1 other test fail [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-6.html [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-436/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-6.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-c-hdmi-a-1: - shard-adlp: [PASS][7] -> [FAIL][8] ([Intel XE#827]) +1 other test fail [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-adlp-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-hdmi-a-1.html [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-8/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-hdmi-a-1.html * igt@kms_big_fb@x-tiled-32bpp-rotate-90: - shard-adlp: NOTRUN -> [SKIP][9] ([Intel XE#1201] / [Intel XE#316]) +4 other tests skip [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: - shard-adlp: NOTRUN -> [FAIL][10] ([Intel XE#1231]) [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-adlp: NOTRUN -> [FAIL][11] ([Intel XE#1874]) +1 other test fail [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_big_fb@yf-tiled-8bpp-rotate-180: - shard-adlp: NOTRUN -> [SKIP][12] ([Intel XE#1124] / [Intel XE#1201]) +9 other tests skip [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html * igt@kms_bw@linear-tiling-2-displays-3840x2160p: - shard-adlp: NOTRUN -> [SKIP][13] ([Intel XE#1201] / [Intel XE#367]) +2 other tests skip [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@kms_bw@linear-tiling-2-displays-3840x2160p.html * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs: - shard-adlp: NOTRUN -> [SKIP][14] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +19 other tests skip [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-1: - shard-adlp: NOTRUN -> [SKIP][15] ([Intel XE#1201] / [Intel XE#787]) +29 other tests skip [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-1/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-1.html * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs: - shard-adlp: NOTRUN -> [SKIP][16] ([Intel XE#1201] / [Intel XE#1252]) [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs.html * igt@kms_chamelium_color@ctm-blue-to-red: - shard-adlp: NOTRUN -> [SKIP][17] ([Intel XE#1201] / [Intel XE#306]) [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@kms_chamelium_color@ctm-blue-to-red.html * igt@kms_chamelium_frames@dp-crc-multiple: - shard-adlp: NOTRUN -> [SKIP][18] ([Intel XE#1201] / [Intel XE#373]) +6 other tests skip [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@kms_chamelium_frames@dp-crc-multiple.html * igt@kms_content_protection@legacy: - shard-adlp: NOTRUN -> [SKIP][19] ([Intel XE#1201] / [Intel XE#455]) +14 other tests skip [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-1/igt@kms_content_protection@legacy.html * igt@kms_cursor_crc@cursor-onscreen-512x170: - shard-adlp: NOTRUN -> [SKIP][20] ([Intel XE#1201] / [Intel XE#308]) [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@kms_cursor_crc@cursor-onscreen-512x170.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size: - shard-adlp: NOTRUN -> [SKIP][21] ([Intel XE#1201] / [Intel XE#323]) [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html * igt@kms_cursor_legacy@cursor-vs-flip-toggle: - shard-dg2-set2: [PASS][22] -> [DMESG-WARN][23] ([Intel XE#1214] / [Intel XE#282]) +3 other tests dmesg-warn [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-466/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-433/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions: - shard-adlp: NOTRUN -> [SKIP][24] ([Intel XE#1201] / [Intel XE#309]) +2 other tests skip [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html * igt@kms_feature_discovery@display-4x: - shard-adlp: NOTRUN -> [SKIP][25] ([Intel XE#1138] / [Intel XE#1201]) [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@kms_feature_discovery@display-4x.html * igt@kms_flip@2x-flip-vs-rmfb-interruptible: - shard-adlp: NOTRUN -> [SKIP][26] ([Intel XE#1201] / [Intel XE#310]) +1 other test skip [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-1/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-adlp: NOTRUN -> [FAIL][27] ([Intel XE#1861]) [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbc-tiling-4: - shard-adlp: NOTRUN -> [SKIP][28] ([Intel XE#1151] / [Intel XE#1201]) [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-1/igt@kms_frontbuffer_tracking@fbc-tiling-4.html * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-blt: - shard-adlp: NOTRUN -> [SKIP][29] ([Intel XE#1201] / [Intel XE#651]) +9 other tests skip [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary: - shard-adlp: NOTRUN -> [SKIP][30] ([Intel XE#1201] / [Intel XE#653]) +5 other tests skip [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-1/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-render: - shard-adlp: NOTRUN -> [SKIP][31] ([Intel XE#1201] / [Intel XE#656]) +30 other tests skip [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-render.html * igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-6: - shard-dg2-set2: NOTRUN -> [FAIL][32] ([Intel XE#616]) [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-466/igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-6.html * igt@kms_pm_backlight@bad-brightness: - shard-adlp: NOTRUN -> [SKIP][33] ([Intel XE#1201] / [Intel XE#870]) [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@kms_pm_backlight@bad-brightness.html * igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf: - shard-adlp: NOTRUN -> [SKIP][34] ([Intel XE#1201]) +2 other tests skip [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html * igt@kms_psr@fbc-psr2-cursor-plane-move: - shard-adlp: NOTRUN -> [SKIP][35] ([Intel XE#1201] / [Intel XE#929]) +7 other tests skip [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@kms_psr@fbc-psr2-cursor-plane-move.html * igt@kms_rotation_crc@bad-pixel-format: - shard-adlp: NOTRUN -> [SKIP][36] ([Intel XE#1201] / [Intel XE#327]) [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@kms_rotation_crc@bad-pixel-format.html * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0: - shard-adlp: NOTRUN -> [SKIP][37] ([Intel XE#1127] / [Intel XE#1201]) [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html * igt@kms_vblank@ts-continuation-dpms-rpm@pipe-a-hdmi-a-1: - shard-adlp: NOTRUN -> [SKIP][38] ([Intel XE#1201] / [Intel XE#1207]) [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@kms_vblank@ts-continuation-dpms-rpm@pipe-a-hdmi-a-1.html * igt@kms_writeback@writeback-invalid-parameters: - shard-adlp: NOTRUN -> [SKIP][39] ([Intel XE#1201] / [Intel XE#756]) [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@kms_writeback@writeback-invalid-parameters.html * igt@sriov_basic@bind-unbind-vf: - shard-adlp: NOTRUN -> [SKIP][40] ([Intel XE#1201] / [Intel XE#1932]) [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@sriov_basic@bind-unbind-vf.html * igt@xe_ccs@block-copy-compressed-inc-dimension: - shard-adlp: NOTRUN -> [SKIP][41] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#488]) [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@xe_ccs@block-copy-compressed-inc-dimension.html * igt@xe_copy_basic@mem-set-linear-0xfffe: - shard-adlp: NOTRUN -> [SKIP][42] ([Intel XE#1126] / [Intel XE#1201]) [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@xe_copy_basic@mem-set-linear-0xfffe.html * igt@xe_create@create-big-vram: - shard-adlp: NOTRUN -> [SKIP][43] ([Intel XE#1062] / [Intel XE#1201]) [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@xe_create@create-big-vram.html * igt@xe_evict@evict-beng-cm-threads-large: - shard-dg2-set2: [PASS][44] -> [TIMEOUT][45] ([Intel XE#1473] / [Intel XE#392]) [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-433/igt@xe_evict@evict-beng-cm-threads-large.html [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-434/igt@xe_evict@evict-beng-cm-threads-large.html * igt@xe_evict@evict-beng-large-multi-vm: - shard-adlp: NOTRUN -> [SKIP][46] ([Intel XE#1201] / [Intel XE#261]) +3 other tests skip [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-1/igt@xe_evict@evict-beng-large-multi-vm.html * igt@xe_evict@evict-beng-large-multi-vm-cm: - shard-dg2-set2: [PASS][47] -> [FAIL][48] ([Intel XE#1600]) [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-435/igt@xe_evict@evict-beng-large-multi-vm-cm.html [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-466/igt@xe_evict@evict-beng-large-multi-vm-cm.html * igt@xe_evict@evict-beng-mixed-threads-large: - shard-dg2-set2: [PASS][49] -> [INCOMPLETE][50] ([Intel XE#1195] / [Intel XE#1473] / [Intel XE#392]) [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-436/igt@xe_evict@evict-beng-mixed-threads-large.html [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-435/igt@xe_evict@evict-beng-mixed-threads-large.html * igt@xe_evict@evict-mixed-threads-large: - shard-dg2-set2: [PASS][51] -> [TIMEOUT][52] ([Intel XE#1041] / [Intel XE#1473] / [Intel XE#392]) [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-433/igt@xe_evict@evict-mixed-threads-large.html [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-435/igt@xe_evict@evict-mixed-threads-large.html * igt@xe_evict@evict-small-multi-vm-cm: - shard-adlp: NOTRUN -> [SKIP][53] ([Intel XE#1201] / [Intel XE#261] / [Intel XE#688]) +2 other tests skip [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@xe_evict@evict-small-multi-vm-cm.html * igt@xe_exec_basic@multigpu-no-exec-null-defer-bind: - shard-adlp: NOTRUN -> [SKIP][54] ([Intel XE#1201] / [Intel XE#1392]) +4 other tests skip [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@xe_exec_basic@multigpu-no-exec-null-defer-bind.html * igt@xe_exec_fault_mode@once-bindexecqueue-userptr: - shard-adlp: NOTRUN -> [SKIP][55] ([Intel XE#1201] / [Intel XE#288]) +20 other tests skip [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@xe_exec_fault_mode@once-bindexecqueue-userptr.html * igt@xe_mmap@vram: - shard-adlp: NOTRUN -> [SKIP][56] ([Intel XE#1008] / [Intel XE#1201]) [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@xe_mmap@vram.html * igt@xe_module_load@force-load: - shard-adlp: NOTRUN -> [SKIP][57] ([Intel XE#1201] / [Intel XE#378]) [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@xe_module_load@force-load.html * igt@xe_pm@s2idle-basic: - shard-adlp: NOTRUN -> [DMESG-FAIL][58] ([Intel XE#1608] / [Intel XE#2034]) [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@xe_pm@s2idle-basic.html * igt@xe_pm@s2idle-multiple-execs: - shard-adlp: NOTRUN -> [FAIL][59] ([Intel XE#1924]) +2 other tests fail [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@xe_pm@s2idle-multiple-execs.html * igt@xe_pm@s4-basic-exec: - shard-adlp: [PASS][60] -> [DMESG-WARN][61] ([Intel XE#1214]) +1 other test dmesg-warn [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-adlp-8/igt@xe_pm@s4-basic-exec.html [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-2/igt@xe_pm@s4-basic-exec.html * igt@xe_query@multigpu-query-invalid-extension: - shard-adlp: NOTRUN -> [SKIP][62] ([Intel XE#1201] / [Intel XE#944]) +1 other test skip [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@xe_query@multigpu-query-invalid-extension.html #### Possible fixes #### * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions: - shard-dg2-set2: [DMESG-WARN][63] ([Intel XE#1214] / [Intel XE#282]) -> [PASS][64] +8 other tests pass [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-433/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-463/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html * igt@kms_cursor_legacy@torture-move@pipe-a: - shard-adlp: [DMESG-WARN][65] ([Intel XE#1214] / [Intel XE#877]) -> [PASS][66] +1 other test pass [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-adlp-6/igt@kms_cursor_legacy@torture-move@pipe-a.html [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@kms_cursor_legacy@torture-move@pipe-a.html * igt@kms_flip@blocking-wf_vblank: - {shard-lnl}: [FAIL][67] ([Intel XE#480] / [Intel XE#886]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-lnl-2/igt@kms_flip@blocking-wf_vblank.html [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-lnl-4/igt@kms_flip@blocking-wf_vblank.html * igt@kms_flip@blocking-wf_vblank@a-edp1: - {shard-lnl}: [FAIL][69] ([Intel XE#886]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-lnl-2/igt@kms_flip@blocking-wf_vblank@a-edp1.html [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-lnl-4/igt@kms_flip@blocking-wf_vblank@a-edp1.html * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-6: - shard-dg2-set2: [DMESG-WARN][71] ([Intel XE#1214]) -> [PASS][72] +2 other tests pass [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-436/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-6.html [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-434/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-6.html * igt@kms_pm_rpm@drm-resources-equal: - {shard-lnl}: [SKIP][73] ([Intel XE#1211]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-lnl-1/igt@kms_pm_rpm@drm-resources-equal.html [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-lnl-1/igt@kms_pm_rpm@drm-resources-equal.html * igt@xe_exec_compute_mode@many-userptr-invalidate-race: - {shard-lnl}: [DMESG-WARN][75] ([Intel XE#1330] / [Intel XE#1796]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-lnl-7/igt@xe_exec_compute_mode@many-userptr-invalidate-race.html [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-lnl-1/igt@xe_exec_compute_mode@many-userptr-invalidate-race.html * igt@xe_exercise_blt@fast-copy-inc-dimension: - {shard-lnl}: [INCOMPLETE][77] ([Intel XE#1330]) -> [PASS][78] +1 other test pass [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-lnl-3/igt@xe_exercise_blt@fast-copy-inc-dimension.html [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-lnl-4/igt@xe_exercise_blt@fast-copy-inc-dimension.html * igt@xe_live_ktest@xe_migrate: - {shard-lnl}: [SKIP][79] ([Intel XE#1192]) -> [PASS][80] [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-lnl-3/igt@xe_live_ktest@xe_migrate.html [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-lnl-6/igt@xe_live_ktest@xe_migrate.html * igt@xe_pm@s4-vm-bind-prefetch: - shard-adlp: [DMESG-WARN][81] ([Intel XE#1214]) -> [PASS][82] [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-adlp-4/igt@xe_pm@s4-vm-bind-prefetch.html [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-8/igt@xe_pm@s4-vm-bind-prefetch.html * igt@xe_pm@s4-vm-bind-unbind-all: - shard-adlp: [ABORT][83] ([Intel XE#1794]) -> [PASS][84] [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-adlp-9/igt@xe_pm@s4-vm-bind-unbind-all.html [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-1/igt@xe_pm@s4-vm-bind-unbind-all.html #### Warnings #### * igt@kms_big_fb@linear-16bpp-rotate-270: - shard-dg2-set2: [SKIP][85] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][86] ([Intel XE#316]) +2 other tests skip [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_big_fb@linear-16bpp-rotate-270.html [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_big_fb@linear-16bpp-rotate-270.html * igt@kms_big_fb@linear-16bpp-rotate-90: - shard-dg2-set2: [SKIP][87] ([Intel XE#316]) -> [SKIP][88] ([Intel XE#1201] / [Intel XE#316]) +1 other test skip [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_big_fb@linear-16bpp-rotate-90.html [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-435/igt@kms_big_fb@linear-16bpp-rotate-90.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-adlp: [FAIL][89] ([Intel XE#1231]) -> [DMESG-FAIL][90] ([Intel XE#324]) [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-adlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-dg2-set2: [SKIP][91] ([Intel XE#1124]) -> [SKIP][92] ([Intel XE#1124] / [Intel XE#1201]) +9 other tests skip [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-436/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip: - shard-adlp: [DMESG-FAIL][93] ([Intel XE#324]) -> [FAIL][94] ([Intel XE#1231]) [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-adlp-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html * igt@kms_big_fb@yf-tiled-8bpp-rotate-270: - shard-dg2-set2: [SKIP][95] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][96] ([Intel XE#1124]) +6 other tests skip [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html * igt@kms_bw@linear-tiling-1-displays-1920x1080p: - shard-dg2-set2: [SKIP][97] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][98] ([Intel XE#367]) +2 other tests skip [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html * igt@kms_bw@linear-tiling-2-displays-2560x1440p: - shard-dg2-set2: [SKIP][99] ([Intel XE#367]) -> [SKIP][100] ([Intel XE#1201] / [Intel XE#367]) [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-435/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-dp-4: - shard-dg2-set2: [SKIP][101] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][102] ([Intel XE#455] / [Intel XE#787]) +9 other tests skip [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-dp-4.html [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-dp-4.html * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-c-dp-4: - shard-dg2-set2: [SKIP][103] ([Intel XE#787]) -> [SKIP][104] ([Intel XE#1201] / [Intel XE#787]) +62 other tests skip [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-c-dp-4.html [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-433/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-c-dp-4.html * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4: - shard-dg2-set2: [SKIP][105] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][106] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +17 other tests skip [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-435/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html * igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs: - shard-dg2-set2: [SKIP][107] ([Intel XE#1252]) -> [SKIP][108] ([Intel XE#1201] / [Intel XE#1252]) [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs.html [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-433/igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs.html * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6: - shard-dg2-set2: [SKIP][109] ([Intel XE#1201] / [Intel XE#787]) -> [SKIP][110] ([Intel XE#787]) +34 other tests skip [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html * igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs: - shard-dg2-set2: [SKIP][111] ([Intel XE#1201] / [Intel XE#1252]) -> [SKIP][112] ([Intel XE#1252]) [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs.html [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs.html * igt@kms_cdclk@mode-transition-all-outputs: - shard-dg2-set2: [SKIP][113] ([Intel XE#1201] / [Intel XE#314]) -> [SKIP][114] ([Intel XE#314]) [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_cdclk@mode-transition-all-outputs.html [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_cdclk@mode-transition-all-outputs.html * igt@kms_cdclk@plane-scaling@pipe-b-dp-4: - shard-dg2-set2: [SKIP][115] ([Intel XE#1152]) -> [SKIP][116] ([Intel XE#1152] / [Intel XE#1201]) +3 other tests skip [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-433/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html * igt@kms_chamelium_color@ctm-0-75: - shard-dg2-set2: [SKIP][117] ([Intel XE#306]) -> [SKIP][118] ([Intel XE#1201] / [Intel XE#306]) [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_chamelium_color@ctm-0-75.html [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-433/igt@kms_chamelium_color@ctm-0-75.html * igt@kms_chamelium_color@degamma: - shard-dg2-set2: [SKIP][119] ([Intel XE#1201] / [Intel XE#306]) -> [SKIP][120] ([Intel XE#306]) [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_chamelium_color@degamma.html [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_chamelium_color@degamma.html * igt@kms_chamelium_frames@dp-crc-fast: - shard-dg2-set2: [SKIP][121] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][122] ([Intel XE#373]) +5 other tests skip [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_chamelium_frames@dp-crc-fast.html [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_chamelium_frames@dp-crc-fast.html * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode: - shard-dg2-set2: [SKIP][123] ([Intel XE#373]) -> [SKIP][124] ([Intel XE#1201] / [Intel XE#373]) +5 other tests skip [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-435/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html * igt@kms_content_protection@dp-mst-lic-type-0: - shard-dg2-set2: [SKIP][125] ([Intel XE#307]) -> [SKIP][126] ([Intel XE#1201] / [Intel XE#307]) +1 other test skip [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_content_protection@dp-mst-lic-type-0.html [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-436/igt@kms_content_protection@dp-mst-lic-type-0.html * igt@kms_content_protection@dp-mst-type-0: - shard-dg2-set2: [SKIP][127] ([Intel XE#1201] / [Intel XE#307]) -> [SKIP][128] ([Intel XE#307]) [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-434/igt@kms_content_protection@dp-mst-type-0.html [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_content_protection@dp-mst-type-0.html * igt@kms_cursor_crc@cursor-offscreen-512x512: - shard-dg2-set2: [SKIP][129] ([Intel XE#1201] / [Intel XE#308]) -> [SKIP][130] ([Intel XE#308]) [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-434/igt@kms_cursor_crc@cursor-offscreen-512x512.html [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_cursor_crc@cursor-offscreen-512x512.html * igt@kms_cursor_crc@cursor-onscreen-256x256@pipe-a-hdmi-a-6: - shard-dg2-set2: [DMESG-WARN][131] ([Intel XE#1214] / [Intel XE#282]) -> [DMESG-WARN][132] ([Intel XE#282]) +4 other tests dmesg-warn [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_cursor_crc@cursor-onscreen-256x256@pipe-a-hdmi-a-6.html [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_cursor_crc@cursor-onscreen-256x256@pipe-a-hdmi-a-6.html * igt@kms_cursor_crc@cursor-onscreen-512x512: - shard-dg2-set2: [SKIP][133] ([Intel XE#308]) -> [SKIP][134] ([Intel XE#1201] / [Intel XE#308]) [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_cursor_crc@cursor-onscreen-512x512.html [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-436/igt@kms_cursor_crc@cursor-onscreen-512x512.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-dg2-set2: [DMESG-WARN][135] ([Intel XE#1214] / [Intel XE#282]) -> [DMESG-WARN][136] ([Intel XE#1214] / [Intel XE#282] / [Intel XE#910]) [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-433/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-434/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size: - shard-dg2-set2: [DMESG-WARN][137] ([Intel XE#1214] / [Intel XE#282] / [Intel XE#910]) -> [DMESG-WARN][138] ([Intel XE#282] / [Intel XE#910]) [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-434/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-dg2-set2: [DMESG-WARN][139] ([Intel XE#282]) -> [DMESG-WARN][140] ([Intel XE#1214] / [Intel XE#282]) +12 other tests dmesg-warn [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-433/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle: - shard-dg2-set2: [SKIP][141] ([Intel XE#323]) -> [SKIP][142] ([Intel XE#1201] / [Intel XE#323]) +1 other test skip [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-436/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-dp-4: - shard-dg2-set2: [SKIP][143] ([Intel XE#455] / [Intel XE#929]) -> [SKIP][144] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#929]) [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-dp-4.html [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-436/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-dp-4.html * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-6: - shard-dg2-set2: [SKIP][145] ([Intel XE#1927]) -> [SKIP][146] ([Intel XE#1201] / [Intel XE#1927]) [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-6.html [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-436/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-6.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-adlp: [INCOMPLETE][147] ([Intel XE#1195] / [Intel XE#927]) -> [DMESG-FAIL][148] ([Intel XE#1608]) [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-adlp-1/igt@kms_fbcon_fbt@fbc-suspend.html [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-6/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_feature_discovery@chamelium: - shard-dg2-set2: [SKIP][149] ([Intel XE#1201] / [Intel XE#701]) -> [SKIP][150] ([Intel XE#701]) [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_feature_discovery@chamelium.html [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_feature_discovery@chamelium.html * igt@kms_feature_discovery@dp-mst: - shard-dg2-set2: [SKIP][151] ([Intel XE#1137]) -> [SKIP][152] ([Intel XE#1137] / [Intel XE#1201]) [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_feature_discovery@dp-mst.html [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-433/igt@kms_feature_discovery@dp-mst.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-dg2-set2: [DMESG-WARN][153] ([Intel XE#1214] / [Intel XE#1551]) -> [INCOMPLETE][154] ([Intel XE#1551]) [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-434/igt@kms_flip@flip-vs-suspend-interruptible.html [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_flip@flip-vs-suspend-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a6: - shard-dg2-set2: [DMESG-WARN][155] ([Intel XE#1214] / [Intel XE#1551]) -> [DMESG-WARN][156] ([Intel XE#1551]) [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-434/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a6.html [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a6.html * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen: - shard-dg2-set2: [SKIP][157] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][158] ([Intel XE#651]) +19 other tests skip [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html * igt@kms_frontbuffer_tracking@drrs-suspend: - shard-dg2-set2: [SKIP][159] ([Intel XE#651]) -> [SKIP][160] ([Intel XE#1201] / [Intel XE#651]) +22 other tests skip [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-suspend.html [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render: - shard-dg2-set2: [SKIP][161] ([Intel XE#653]) -> [SKIP][162] ([Intel XE#1201] / [Intel XE#653]) +21 other tests skip [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render.html [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc: - shard-dg2-set2: [SKIP][163] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][164] ([Intel XE#653]) +20 other tests skip [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html * igt@kms_getfb@getfb-reject-ccs: - shard-dg2-set2: [SKIP][165] ([Intel XE#1201] / [Intel XE#605]) -> [SKIP][166] ([Intel XE#605]) [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_getfb@getfb-reject-ccs.html [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_getfb@getfb-reject-ccs.html * igt@kms_plane@plane-panning-bottom-right-suspend: - shard-adlp: [DMESG-FAIL][167] ([Intel XE#1608] / [Intel XE#2034]) -> [ABORT][168] ([Intel XE#1035] / [Intel XE#1608]) [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-adlp-8/igt@kms_plane@plane-panning-bottom-right-suspend.html [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-2/igt@kms_plane@plane-panning-bottom-right-suspend.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b: - shard-adlp: [DMESG-FAIL][169] ([Intel XE#1608]) -> [ABORT][170] ([Intel XE#1035]) [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-adlp-8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation: - shard-dg2-set2: [SKIP][171] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#498]) -> [SKIP][172] ([Intel XE#455] / [Intel XE#498]) +1 other test skip [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-6: - shard-dg2-set2: [SKIP][173] ([Intel XE#1201] / [Intel XE#498]) -> [SKIP][174] ([Intel XE#498]) +2 other tests skip [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-6.html [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-6.html * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a-hdmi-a-6: - shard-dg2-set2: [SKIP][175] ([Intel XE#305]) -> [SKIP][176] ([Intel XE#1201] / [Intel XE#305]) +2 other tests skip [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a-hdmi-a-6.html [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-436/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a-hdmi-a-6.html * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-6: - shard-dg2-set2: [SKIP][177] ([Intel XE#305] / [Intel XE#455]) -> [SKIP][178] ([Intel XE#1201] / [Intel XE#305] / [Intel XE#455]) +1 other test skip [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-6.html [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-436/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-6.html * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25: - shard-dg2-set2: [SKIP][179] ([Intel XE#1201] / [Intel XE#305] / [Intel XE#455]) -> [SKIP][180] ([Intel XE#305] / [Intel XE#455]) +1 other test skip [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-6: - shard-dg2-set2: [SKIP][181] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][182] ([Intel XE#455]) +15 other tests skip [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-6.html [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-6.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-hdmi-a-6: - shard-dg2-set2: [SKIP][183] ([Intel XE#1201] / [Intel XE#305]) -> [SKIP][184] ([Intel XE#305]) +5 other tests skip [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-434/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-hdmi-a-6.html [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-hdmi-a-6.html * igt@kms_pm_dc@dc6-psr: - shard-dg2-set2: [SKIP][185] ([Intel XE#1129] / [Intel XE#1201]) -> [SKIP][186] ([Intel XE#1129]) [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_pm_dc@dc6-psr.html [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_pm_dc@dc6-psr.html * igt@kms_pm_dc@deep-pkgc: - shard-dg2-set2: [SKIP][187] ([Intel XE#908]) -> [SKIP][188] ([Intel XE#1201] / [Intel XE#908]) [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_pm_dc@deep-pkgc.html [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-433/igt@kms_pm_dc@deep-pkgc.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area: - shard-dg2-set2: [SKIP][189] ([Intel XE#929]) -> [SKIP][190] ([Intel XE#1201] / [Intel XE#929]) +12 other tests skip [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-433/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html * igt@kms_psr@fbc-psr2-cursor-plane-onoff: - shard-dg2-set2: [SKIP][191] ([Intel XE#1201] / [Intel XE#929]) -> [SKIP][192] ([Intel XE#929]) +11 other tests skip [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-434/igt@kms_psr@fbc-psr2-cursor-plane-onoff.html [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_psr@fbc-psr2-cursor-plane-onoff.html * igt@kms_rotation_crc@bad-tiling: - shard-dg2-set2: [SKIP][193] ([Intel XE#1201] / [Intel XE#327]) -> [SKIP][194] ([Intel XE#327]) [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-434/igt@kms_rotation_crc@bad-tiling.html [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_rotation_crc@bad-tiling.html * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180: - shard-dg2-set2: [SKIP][195] ([Intel XE#1127] / [Intel XE#1201]) -> [SKIP][196] ([Intel XE#1127]) [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-434/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270: - shard-dg2-set2: [SKIP][197] ([Intel XE#327]) -> [SKIP][198] ([Intel XE#1201] / [Intel XE#327]) +1 other test skip [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-433/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html * igt@kms_tiled_display@basic-test-pattern-with-chamelium: - shard-dg2-set2: [SKIP][199] ([Intel XE#1201] / [Intel XE#362]) -> [SKIP][200] ([Intel XE#1500]) [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html * igt@kms_vrr@flipline: - shard-dg2-set2: [SKIP][201] ([Intel XE#455]) -> [SKIP][202] ([Intel XE#1201] / [Intel XE#455]) +14 other tests skip [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@kms_vrr@flipline.html [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-436/igt@kms_vrr@flipline.html * igt@kms_writeback@writeback-fb-id: - shard-dg2-set2: [SKIP][203] ([Intel XE#1201] / [Intel XE#756]) -> [SKIP][204] ([Intel XE#756]) [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@kms_writeback@writeback-fb-id.html [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@kms_writeback@writeback-fb-id.html * igt@sriov_basic@enable-vfs-autoprobe-on: - shard-dg2-set2: [SKIP][205] ([Intel XE#1091] / [Intel XE#1201]) -> [SKIP][206] ([Intel XE#1091]) [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@sriov_basic@enable-vfs-autoprobe-on.html [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@sriov_basic@enable-vfs-autoprobe-on.html * igt@xe_compute_preempt@compute-preempt-many: - shard-dg2-set2: [SKIP][207] ([Intel XE#1280] / [Intel XE#455]) -> [SKIP][208] ([Intel XE#1201] / [Intel XE#1280] / [Intel XE#455]) +1 other test skip [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@xe_compute_preempt@compute-preempt-many.html [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-433/igt@xe_compute_preempt@compute-preempt-many.html * igt@xe_copy_basic@mem-copy-linear-0xfd: - shard-dg2-set2: [SKIP][209] ([Intel XE#1123] / [Intel XE#1201]) -> [SKIP][210] ([Intel XE#1123]) [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@xe_copy_basic@mem-copy-linear-0xfd.html [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@xe_copy_basic@mem-copy-linear-0xfd.html * igt@xe_copy_basic@mem-set-linear-0x369: - shard-dg2-set2: [SKIP][211] ([Intel XE#1126] / [Intel XE#1201]) -> [SKIP][212] ([Intel XE#1126]) [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-434/igt@xe_copy_basic@mem-set-linear-0x369.html [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@xe_copy_basic@mem-set-linear-0x369.html * igt@xe_create@multigpu-create-massive-size: - shard-dg2-set2: [SKIP][213] ([Intel XE#944]) -> [SKIP][214] ([Intel XE#1201] / [Intel XE#944]) +1 other test skip [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@xe_create@multigpu-create-massive-size.html [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-436/igt@xe_create@multigpu-create-massive-size.html * igt@xe_exec_fault_mode@twice-bindexecqueue-rebind-imm: - shard-dg2-set2: [SKIP][215] ([Intel XE#288]) -> [SKIP][216] ([Intel XE#1201] / [Intel XE#288]) +17 other tests skip [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@xe_exec_fault_mode@twice-bindexecqueue-rebind-imm.html [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-433/igt@xe_exec_fault_mode@twice-bindexecqueue-rebind-imm.html * igt@xe_exec_fault_mode@twice-userptr-rebind-imm: - shard-dg2-set2: [SKIP][217] ([Intel XE#1201] / [Intel XE#288]) -> [SKIP][218] ([Intel XE#288]) +17 other tests skip [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-434/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html * igt@xe_exec_reset@gt-reset-stress: - shard-dg2-set2: [DMESG-WARN][219] ([Intel XE#1214] / [Intel XE#1638]) -> [DMESG-WARN][220] ([Intel XE#1638]) [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@xe_exec_reset@gt-reset-stress.html [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@xe_exec_reset@gt-reset-stress.html * igt@xe_huc_copy@huc_copy: - shard-dg2-set2: [SKIP][221] ([Intel XE#255]) -> [SKIP][222] ([Intel XE#1201] / [Intel XE#255]) [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@xe_huc_copy@huc_copy.html [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-436/igt@xe_huc_copy@huc_copy.html * igt@xe_mmap@small-bar: - shard-dg2-set2: [SKIP][223] ([Intel XE#512]) -> [SKIP][224] ([Intel XE#1201] / [Intel XE#512]) [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@xe_mmap@small-bar.html [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-435/igt@xe_mmap@small-bar.html * igt@xe_module_load@reload: - shard-dg2-set2: [DMESG-WARN][225] -> [DMESG-WARN][226] ([Intel XE#1214]) [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@xe_module_load@reload.html [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-436/igt@xe_module_load@reload.html * igt@xe_pm@d3cold-basic: - shard-dg2-set2: [SKIP][227] ([Intel XE#366]) -> [SKIP][228] ([Intel XE#1201] / [Intel XE#366]) [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@xe_pm@d3cold-basic.html [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-436/igt@xe_pm@d3cold-basic.html * igt@xe_pm@s2idle-exec-after: - shard-adlp: [DMESG-FAIL][229] ([Intel XE#1608] / [Intel XE#2034]) -> [INCOMPLETE][230] ([Intel XE#1195] / [Intel XE#1358]) [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-adlp-4/igt@xe_pm@s2idle-exec-after.html [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-1/igt@xe_pm@s2idle-exec-after.html * igt@xe_pm@s3-basic-exec: - shard-dg2-set2: [DMESG-WARN][231] ([Intel XE#1551]) -> [DMESG-WARN][232] ([Intel XE#1214] / [Intel XE#1551]) [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-432/igt@xe_pm@s3-basic-exec.html [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-433/igt@xe_pm@s3-basic-exec.html * igt@xe_pm@s3-vm-bind-userptr: - shard-adlp: [INCOMPLETE][233] ([Intel XE#1195]) -> [DMESG-FAIL][234] ([Intel XE#1608]) [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-adlp-1/igt@xe_pm@s3-vm-bind-userptr.html [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-4/igt@xe_pm@s3-vm-bind-userptr.html * igt@xe_pm@s4-d3hot-basic-exec: - shard-adlp: [DMESG-WARN][235] ([Intel XE#1214]) -> [INCOMPLETE][236] ([Intel XE#1195] / [Intel XE#1358]) [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-adlp-6/igt@xe_pm@s4-d3hot-basic-exec.html [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-9/igt@xe_pm@s4-d3hot-basic-exec.html * igt@xe_wedged@basic-wedged: - shard-dg2-set2: [DMESG-WARN][237] ([Intel XE#1214] / [Intel XE#1760]) -> [DMESG-WARN][238] ([Intel XE#1760]) [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-dg2-463/igt@xe_wedged@basic-wedged.html [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-dg2-432/igt@xe_wedged@basic-wedged.html * igt@xe_wedged@wedged-at-any-timeout: - shard-adlp: [DMESG-WARN][239] ([Intel XE#1214] / [Intel XE#1760]) -> [DMESG-FAIL][240] ([Intel XE#1760]) [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462/shard-adlp-4/igt@xe_wedged@wedged-at-any-timeout.html [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/shard-adlp-1/igt@xe_wedged@wedged-at-any-timeout.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [Intel XE#1008]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1008 [Intel XE#1035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1035 [Intel XE#1041]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1041 [Intel XE#1062]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1062 [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091 [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123 [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124 [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126 [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127 [Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129 [Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137 [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138 [Intel XE#1151]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1151 [Intel XE#1152]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1152 [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192 [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195 [Intel XE#1201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1201 [Intel XE#1207]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1207 [Intel XE#1211]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1211 [Intel XE#1214]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1214 [Intel XE#1231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1231 [Intel XE#1252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1252 [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280 [Intel XE#1330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1330 [Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358 [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392 [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397 [Intel XE#1399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1399 [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401 [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407 [Intel XE#1413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1413 [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421 [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424 [Intel XE#1430]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1430 [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435 [Intel XE#1437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1437 [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439 [Intel XE#1446]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1446 [Intel XE#1467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1467 [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470 [Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473 [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500 [Intel XE#1551]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1551 [Intel XE#1595]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1595 [Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600 [Intel XE#1608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1608 [Intel XE#1638]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1638 [Intel XE#1659]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1659 [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745 [Intel XE#1760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1760 [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794 [Intel XE#1796]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1796 [Intel XE#1861]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1861 [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874 [Intel XE#1901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1901 [Intel XE#1924]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1924 [Intel XE#1927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1927 [Intel XE#1932]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1932 [Intel XE#2022]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2022 [Intel XE#2023]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2023 [Intel XE#2024]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2024 [Intel XE#2028]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2028 [Intel XE#2034]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2034 [Intel XE#2043]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2043 [Intel XE#255]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/255 [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261 [Intel XE#282]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/282 [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288 [Intel XE#305]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/305 [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306 [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307 [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308 [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309 [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310 [Intel XE#314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/314 [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316 [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323 [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324 [Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327 [Intel XE#352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/352 [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362 [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366 [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367 [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373 [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378 [Intel XE#392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/392 [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455 [Intel XE#480]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/480 [Intel XE#488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/488 [Intel XE#498]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/498 [Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512 [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584 [Intel XE#605]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/605 [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616 [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651 [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653 [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656 [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688 [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701 [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756 [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787 [Intel XE#827]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/827 [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870 [Intel XE#873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/873 [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877 [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886 [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908 [Intel XE#910]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/910 [Intel XE#927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/927 [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929 [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944 [Intel XE#958]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/958 Build changes ------------- * Linux: xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462 -> xe-pw-128077v9 IGT_7880: 73618605b4370cf902267aaf1d25666ff5e26112 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git xe-1417-ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462: ed13bc296bbebf04f8a7dabadf2d9f44cc6b5462 xe-pw-128077v9: 128077v9 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-128077v9/index.html [-- Attachment #2: Type: text/html, Size: 88093 bytes --] ^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2024-06-19 22:56 UTC | newest] Thread overview: 24+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-06-07 0:07 [PATCH v9 0/4] drm/xe/guc: Add GuC based register capture for error capture Zhanjun Dong 2024-06-07 0:07 ` [PATCH v9 1/4] drm/xe/guc: Prepare GuC register list and update ADS size " Zhanjun Dong 2024-06-14 11:50 ` Michal Wajdeczko 2024-06-19 19:36 ` Dong, Zhanjun 2024-06-07 0:07 ` [PATCH v9 2/4] drm/xe/guc: Add XE_LP steered register lists Zhanjun Dong 2024-06-13 19:02 ` Teres Alexis, Alan Previn 2024-06-07 0:07 ` [PATCH v9 3/4] drm/xe/guc: Add capture size check in GuC log buffer Zhanjun Dong 2024-06-14 12:13 ` Michal Wajdeczko 2024-06-19 19:44 ` Dong, Zhanjun 2024-06-19 22:28 ` Michal Wajdeczko 2024-06-19 22:56 ` Dong, Zhanjun 2024-06-07 0:07 ` [PATCH v9 4/4] drm/xe/guc: Extract GuC capture lists to register snapshot Zhanjun Dong 2024-06-13 23:26 ` Teres Alexis, Alan Previn 2024-06-19 20:17 ` Dong, Zhanjun 2024-06-14 12:31 ` Michal Wajdeczko 2024-06-19 20:04 ` Dong, Zhanjun 2024-06-07 0:12 ` ✓ CI.Patch_applied: success for drm/xe/guc: Add GuC based register capture for error capture (rev9) Patchwork 2024-06-07 0:12 ` ✗ CI.checkpatch: warning " Patchwork 2024-06-07 0:13 ` ✓ CI.KUnit: success " Patchwork 2024-06-07 0:25 ` ✓ CI.Build: " Patchwork 2024-06-07 0:27 ` ✗ CI.Hooks: failure " Patchwork 2024-06-07 0:28 ` ✓ CI.checksparse: success " Patchwork 2024-06-07 1:11 ` ✓ CI.BAT: " Patchwork 2024-06-07 10:57 ` ✗ CI.FULL: failure " Patchwork
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