[PATCH v7 0/2] drm/xe: Separate out GuC RC code

[PATCH v7 0/2] drm/xe: Separate out GuC RC code

[Vinay Belgaumkar]

This allows us to independently toggle GuC RC feature. The previous
review for this series was at-
https://patchwork.freedesktop.org/series/159128/

Cc: Riana Tauro <riana.tauro@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
---
v2: Address review comments (Michal W)
v3: Add info about guc_rc, guc_pc and gtidle interaction (Michal W)
v4: Address remaining comments from v3 (Michal W)
v5: Review comments (Riana)
v6: Some more review comments (Riana)
v6: Some nits and other comments (Michal W)
---

Vinay Belgaumkar (2):
  drm/xe: Decouple GuC RC code from xe_guc_pc
  drm/xe: Add a wrapper for SLPC set/unset params

 Documentation/gpu/xe/xe_firmware.rst |   3 +
 drivers/gpu/drm/xe/Makefile          |   1 +
 drivers/gpu/drm/xe/xe_gt.c           |   1 -
 drivers/gpu/drm/xe/xe_guc.c          |   6 +
 drivers/gpu/drm/xe/xe_guc_pc.c       | 118 +++++++-------------
 drivers/gpu/drm/xe/xe_guc_pc.h       |   6 +-
 drivers/gpu/drm/xe/xe_guc_rc.c       | 159 +++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_guc_rc.h       |  18 +++
 drivers/gpu/drm/xe/xe_oa.c           |   9 +-
 drivers/gpu/drm/xe/xe_uc.c           |  10 +-
 drivers/gpu/drm/xe/xe_uc.h           |   1 -
 11 files changed, 238 insertions(+), 94 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_guc_rc.c
 create mode 100644 drivers/gpu/drm/xe/xe_guc_rc.h

-- 
2.38.1

[PATCH v7 1/2] drm/xe: Decouple GuC RC code from xe_guc_pc

[Vinay Belgaumkar]

Move enable/disable GuC RC logic into the new file. This will
allow us to independently enable/disable GuC RC and not rely
on SLPC related functions. GuC already provides separate H2G
interfaces to setup GuC RC and SLPC.

Cc: Riana Tauro <riana.tauro@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
---
v2: Comments (Michal W), remove duplicate c6_enable calls from
xe_guc_pc.

v3: Clarify crosss interactions between xe_guc_rc and xe_guc_pc
(Michal W)

v4: More comments (Michal W)

v5: Remove rc_init and use enable/disable (Riana)

v6: Link to kernel docs (Riana)

v7: Don't call devm_add_action_or_reset() in rc_enable (Michal W)
---
 Documentation/gpu/xe/xe_firmware.rst |   3 +
 drivers/gpu/drm/xe/Makefile          |   1 +
 drivers/gpu/drm/xe/xe_gt.c           |   1 -
 drivers/gpu/drm/xe/xe_guc.c          |   6 ++
 drivers/gpu/drm/xe/xe_guc_pc.c       |  70 +++------------
 drivers/gpu/drm/xe/xe_guc_pc.h       |   1 -
 drivers/gpu/drm/xe/xe_guc_rc.c       | 129 +++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_guc_rc.h       |  15 ++++
 drivers/gpu/drm/xe/xe_uc.c           |  10 +--
 drivers/gpu/drm/xe/xe_uc.h           |   1 -
 10 files changed, 172 insertions(+), 65 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_guc_rc.c
 create mode 100644 drivers/gpu/drm/xe/xe_guc_rc.h

diff --git a/Documentation/gpu/xe/xe_firmware.rst b/Documentation/gpu/xe/xe_firmware.rst
index 5d23e9f27391..9c15a300bc62 100644
--- a/Documentation/gpu/xe/xe_firmware.rst
+++ b/Documentation/gpu/xe/xe_firmware.rst
@@ -31,6 +31,9 @@ GuC Power Conservation (PC)
 .. kernel-doc:: drivers/gpu/drm/xe/xe_guc_pc.c
    :doc: GuC Power Conservation (PC)
 
+.. kernel-doc:: drivers/gpu/drm/xe/xe_guc_rc.c
+   :doc: GuC Render C-states (GuC RC)
+
 PCIe Gen5 Limitations
 =====================
 
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 51a9a531fb7e..41ec698b3cc1 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -74,6 +74,7 @@ xe-y += xe_bb.o \
 	xe_guc_log.o \
 	xe_guc_pagefault.o \
 	xe_guc_pc.o \
+	xe_guc_rc.o \
 	xe_guc_submit.o \
 	xe_guc_tlb_inval.o \
 	xe_heci_gsc.o \
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 9d090d0f2438..c8a1d44bbf3a 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -852,7 +852,6 @@ static void gt_reset_worker(struct work_struct *w)
 	if (IS_SRIOV_PF(gt_to_xe(gt)))
 		xe_gt_sriov_pf_stop_prepare(gt);
 
-	xe_uc_gucrc_disable(&gt->uc);
 	xe_uc_stop_prepare(&gt->uc);
 	xe_pagefault_reset(gt_to_xe(gt), gt);
 
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 2efc4678fa73..dc198d499da3 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -35,6 +35,7 @@
 #include "xe_guc_klv_helpers.h"
 #include "xe_guc_log.h"
 #include "xe_guc_pc.h"
+#include "xe_guc_rc.h"
 #include "xe_guc_relay.h"
 #include "xe_guc_submit.h"
 #include "xe_memirq.h"
@@ -880,6 +881,10 @@ int xe_guc_init_post_hwconfig(struct xe_guc *guc)
 	if (ret)
 		return ret;
 
+	ret = xe_guc_rc_init(guc);
+	if (ret)
+		return ret;
+
 	ret = xe_guc_engine_activity_init(guc);
 	if (ret)
 		return ret;
@@ -1620,6 +1625,7 @@ void xe_guc_stop_prepare(struct xe_guc *guc)
 	if (!IS_SRIOV_VF(guc_to_xe(guc))) {
 		int err;
 
+		xe_guc_rc_disable(guc);
 		err = xe_guc_pc_stop(&guc->pc);
 		xe_gt_WARN(guc_to_gt(guc), err, "Failed to stop GuC PC: %pe\n",
 			   ERR_PTR(err));
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 5e5495a39a3c..878eb273c3e6 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -92,6 +92,17 @@
  * Render-C states is also a GuC PC feature that is now enabled in Xe for
  * all platforms.
  *
+ * Implementation details:
+ * -----------------------
+ * The implementation for GuC Power Management features is split as follows:
+ *
+ * xe_guc_rc:  Logic for handling GuC RC
+ * xe_gt_idle: Host side logic for RC6 and Coarse Power gating (CPG)
+ * xe_guc_pc:  Logic for all other SLPC related features
+ *
+ * There is some cross interaction between these where host C6 will need to be
+ * enabled when we plan to skip GuC RC. Also, the GuC RC mode is currently
+ * overridden through 0x3003 which is an SLPC H2G call.
  */
 
 static struct xe_guc *pc_to_guc(struct xe_guc_pc *pc)
@@ -253,22 +264,6 @@ static int pc_action_unset_param(struct xe_guc_pc *pc, u8 id)
 	return ret;
 }
 
-static int pc_action_setup_gucrc(struct xe_guc_pc *pc, u32 mode)
-{
-	struct xe_guc_ct *ct = pc_to_ct(pc);
-	u32 action[] = {
-		GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC,
-		mode,
-	};
-	int ret;
-
-	ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0);
-	if (ret && !(xe_device_wedged(pc_to_xe(pc)) && ret == -ECANCELED))
-		xe_gt_err(pc_to_gt(pc), "GuC RC enable mode=%u failed: %pe\n",
-			  mode, ERR_PTR(ret));
-	return ret;
-}
-
 static u32 decode_freq(u32 raw)
 {
 	return DIV_ROUND_CLOSEST(raw * GT_FREQUENCY_MULTIPLIER,
@@ -1050,30 +1045,6 @@ int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc)
 	return ret;
 }
 
-/**
- * xe_guc_pc_gucrc_disable - Disable GuC RC
- * @pc: Xe_GuC_PC instance
- *
- * Disables GuC RC by taking control of RC6 back from GuC.
- *
- * Return: 0 on success, negative error code on error.
- */
-int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc)
-{
-	struct xe_device *xe = pc_to_xe(pc);
-	struct xe_gt *gt = pc_to_gt(pc);
-	int ret = 0;
-
-	if (xe->info.skip_guc_pc)
-		return 0;
-
-	ret = pc_action_setup_gucrc(pc, GUCRC_HOST_CONTROL);
-	if (ret)
-		return ret;
-
-	return xe_gt_idle_disable_c6(gt);
-}
-
 /**
  * xe_guc_pc_override_gucrc_mode - override GUCRC mode
  * @pc: Xe_GuC_PC instance
@@ -1247,9 +1218,6 @@ int xe_guc_pc_start(struct xe_guc_pc *pc)
 		return -ETIMEDOUT;
 
 	if (xe->info.skip_guc_pc) {
-		if (xe->info.platform != XE_PVC)
-			xe_gt_idle_enable_c6(gt);
-
 		/* Request max possible since dynamic freq mgmt is not enabled */
 		pc_set_cur_freq(pc, UINT_MAX);
 		return 0;
@@ -1291,15 +1259,6 @@ int xe_guc_pc_start(struct xe_guc_pc *pc)
 	if (ret)
 		return ret;
 
-	if (xe->info.platform == XE_PVC) {
-		xe_guc_pc_gucrc_disable(pc);
-		return 0;
-	}
-
-	ret = pc_action_setup_gucrc(pc, GUCRC_FIRMWARE_CONTROL);
-	if (ret)
-		return ret;
-
 	/* Enable SLPC Optimized Strategy for compute */
 	ret = pc_action_set_strategy(pc, SLPC_OPTIMIZED_STRATEGY_COMPUTE);
 
@@ -1319,10 +1278,8 @@ int xe_guc_pc_stop(struct xe_guc_pc *pc)
 {
 	struct xe_device *xe = pc_to_xe(pc);
 
-	if (xe->info.skip_guc_pc) {
-		xe_gt_idle_disable_c6(pc_to_gt(pc));
+	if (xe->info.skip_guc_pc)
 		return 0;
-	}
 
 	mutex_lock(&pc->freq_lock);
 	pc->freq_ready = false;
@@ -1343,8 +1300,7 @@ static void xe_guc_pc_fini_hw(void *arg)
 	if (xe_device_wedged(xe))
 		return;
 
-	CLASS(xe_force_wake, fw_ref)(gt_to_fw(pc_to_gt(pc)), XE_FORCEWAKE_ALL);
-	xe_guc_pc_gucrc_disable(pc);
+	CLASS(xe_force_wake, fw_ref)(gt_to_fw(pc_to_gt(pc)), XE_FW_GT);
 	XE_WARN_ON(xe_guc_pc_stop(pc));
 
 	/* Bind requested freq to mert_freq_cap before unload */
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h b/drivers/gpu/drm/xe/xe_guc_pc.h
index 0e31396f103c..1b95873b262e 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.h
+++ b/drivers/gpu/drm/xe/xe_guc_pc.h
@@ -15,7 +15,6 @@ struct drm_printer;
 int xe_guc_pc_init(struct xe_guc_pc *pc);
 int xe_guc_pc_start(struct xe_guc_pc *pc);
 int xe_guc_pc_stop(struct xe_guc_pc *pc);
-int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc);
 int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode);
 int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc);
 void xe_guc_pc_print(struct xe_guc_pc *pc, struct drm_printer *p);
diff --git a/drivers/gpu/drm/xe/xe_guc_rc.c b/drivers/gpu/drm/xe/xe_guc_rc.c
new file mode 100644
index 000000000000..55eeee7b1011
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_guc_rc.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <drm/drm_print.h>
+
+#include "abi/guc_actions_slpc_abi.h"
+#include "xe_device.h"
+#include "xe_force_wake.h"
+#include "xe_gt.h"
+#include "xe_gt_idle.h"
+#include "xe_gt_printk.h"
+#include "xe_guc.h"
+#include "xe_guc_ct.h"
+#include "xe_guc_rc.h"
+#include "xe_pm.h"
+
+/**
+ * DOC: GuC RC (Render C-states)
+ *
+ * GuC handles the GT transition to deeper C-states in conjunction with Pcode.
+ * GuC RC can be enabled independently of the frequency component in SLPC,
+ * which is also controlled by GuC.
+ *
+ * This file will contain all H2G related logic for handling Render C-states.
+ * There are some calls to xe_gt_idle, where we enable host C6 when GuC RC is
+ * skipped. GuC RC is mostly independent of xe_guc_pc with the exception of
+ * functions that override the mode for which we have to rely on the SLPC H2G
+ * calls.
+ */
+
+static int guc_action_setup_gucrc(struct xe_guc *guc, u32 control)
+{
+	u32 action[] = {
+		GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC,
+		control,
+	};
+	int ret;
+
+	ret = xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
+	if (ret && !(xe_device_wedged(guc_to_xe(guc)) && ret == -ECANCELED))
+		xe_gt_err(guc_to_gt(guc),
+			  "GuC RC setup %s(%u) failed (%pe)\n",
+			   control == GUCRC_HOST_CONTROL ? "HOST_CONTROL" :
+			   control == GUCRC_FIRMWARE_CONTROL ? "FIRMWARE_CONTROL" :
+			   "UNKNOWN", control, ERR_PTR(ret));
+	return ret;
+}
+
+/**
+ * xe_guc_rc_disable() - Disable GuC RC
+ * @guc: Xe GuC instance
+ *
+ * Disables GuC RC by taking control of RC6 back from GuC.
+ */
+void xe_guc_rc_disable(struct xe_guc *guc)
+{
+	struct xe_device *xe = guc_to_xe(guc);
+
+	if (!xe->info.skip_guc_pc && xe->info.platform != XE_PVC)
+		if (guc_action_setup_gucrc(guc, GUCRC_HOST_CONTROL))
+			return;
+
+	xe_gt_WARN_ON(guc_to_gt(guc), xe_gt_idle_disable_c6(guc_to_gt(guc)));
+}
+
+static void xe_guc_rc_fini_hw(void *arg)
+{
+	struct xe_guc *guc = arg;
+	struct xe_device *xe = guc_to_xe(guc);
+	struct xe_gt *gt = guc_to_gt(guc);
+
+	if (xe_device_wedged(xe))
+		return;
+
+	CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
+	xe_guc_rc_disable(guc);
+}
+
+/**
+ * xe_guc_rc_init() - Init GuC RC
+ * @guc: Xe GuC instance
+ *
+ * Add callback action for GuC RC
+ *
+ * Return: 0 on success, negative error code on error.
+ */
+int xe_guc_rc_init(struct xe_guc *guc)
+{
+	struct xe_device *xe = guc_to_xe(guc);
+	struct xe_gt *gt = guc_to_gt(guc);
+
+	xe_gt_assert(gt, xe_device_uc_enabled(xe));
+
+	return devm_add_action_or_reset(xe->drm.dev, xe_guc_rc_fini_hw, guc);
+}
+
+/**
+ * xe_guc_rc_enable() - Enable GuC RC feature if applicable
+ * @guc: Xe GuC instance
+ *
+ * Enables GuC RC feature.
+ *
+ * Return: 0 on success, negative error code on error.
+ */
+int xe_guc_rc_enable(struct xe_guc *guc)
+{
+	struct xe_device *xe = guc_to_xe(guc);
+	struct xe_gt *gt = guc_to_gt(guc);
+
+	xe_gt_assert(gt, xe_device_uc_enabled(xe));
+
+	CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
+	if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FW_GT))
+		return -ETIMEDOUT;
+
+	if (xe->info.platform == XE_PVC) {
+		xe_guc_rc_disable(guc);
+		return 0;
+	}
+
+	if (xe->info.skip_guc_pc) {
+		xe_gt_idle_enable_c6(gt);
+		return 0;
+	}
+
+	return guc_action_setup_gucrc(guc, GUCRC_FIRMWARE_CONTROL);
+}
diff --git a/drivers/gpu/drm/xe/xe_guc_rc.h b/drivers/gpu/drm/xe/xe_guc_rc.h
new file mode 100644
index 000000000000..35fabb82cb0e
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_guc_rc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_GUC_RC_H_
+#define _XE_GUC_RC_H_
+
+struct xe_guc;
+
+int xe_guc_rc_init(struct xe_guc *guc);
+void xe_guc_rc_disable(struct xe_guc *guc);
+int xe_guc_rc_enable(struct xe_guc *guc);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c
index 3f63c2a7e86d..d9aa845a308d 100644
--- a/drivers/gpu/drm/xe/xe_uc.c
+++ b/drivers/gpu/drm/xe/xe_uc.c
@@ -13,6 +13,7 @@
 #include "xe_gt_sriov_vf.h"
 #include "xe_guc.h"
 #include "xe_guc_pc.h"
+#include "xe_guc_rc.h"
 #include "xe_guc_engine_activity.h"
 #include "xe_huc.h"
 #include "xe_sriov.h"
@@ -214,6 +215,10 @@ int xe_uc_load_hw(struct xe_uc *uc)
 	if (ret)
 		goto err_out;
 
+	ret = xe_guc_rc_enable(&uc->guc);
+	if (ret)
+		goto err_out;
+
 	xe_guc_engine_activity_enable_stats(&uc->guc);
 
 	/* We don't fail the driver load if HuC fails to auth */
@@ -242,11 +247,6 @@ int xe_uc_reset_prepare(struct xe_uc *uc)
 	return xe_guc_reset_prepare(&uc->guc);
 }
 
-void xe_uc_gucrc_disable(struct xe_uc *uc)
-{
-	XE_WARN_ON(xe_guc_pc_gucrc_disable(&uc->guc.pc));
-}
-
 void xe_uc_stop_prepare(struct xe_uc *uc)
 {
 	xe_gsc_stop_prepare(&uc->gsc);
diff --git a/drivers/gpu/drm/xe/xe_uc.h b/drivers/gpu/drm/xe/xe_uc.h
index 5398da1a8097..255a54a8f876 100644
--- a/drivers/gpu/drm/xe/xe_uc.h
+++ b/drivers/gpu/drm/xe/xe_uc.h
@@ -12,7 +12,6 @@ int xe_uc_init_noalloc(struct xe_uc *uc);
 int xe_uc_init(struct xe_uc *uc);
 int xe_uc_init_post_hwconfig(struct xe_uc *uc);
 int xe_uc_load_hw(struct xe_uc *uc);
-void xe_uc_gucrc_disable(struct xe_uc *uc);
 int xe_uc_reset_prepare(struct xe_uc *uc);
 void xe_uc_runtime_resume(struct xe_uc *uc);
 void xe_uc_runtime_suspend(struct xe_uc *uc);
-- 
2.38.1

Re: [PATCH v7 1/2] drm/xe: Decouple GuC RC code from xe_guc_pc

[Riana Tauro]

On 1/28/2026 7:53 AM, Vinay Belgaumkar wrote:
> Move enable/disable GuC RC logic into the new file. This will
> allow us to independently enable/disable GuC RC and not rely
> on SLPC related functions. GuC already provides separate H2G
> interfaces to setup GuC RC and SLPC.
> 
> Cc: Riana Tauro <riana.tauro@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>

LGTM
Reviewed-by: Riana Tauro <riana.tauro@intel.com>

> ---
> v2: Comments (Michal W), remove duplicate c6_enable calls from
> xe_guc_pc.
> 
> v3: Clarify crosss interactions between xe_guc_rc and xe_guc_pc
> (Michal W)
> 
> v4: More comments (Michal W)
> 
> v5: Remove rc_init and use enable/disable (Riana)
> 
> v6: Link to kernel docs (Riana)
> 
> v7: Don't call devm_add_action_or_reset() in rc_enable (Michal W)
> ---
>   Documentation/gpu/xe/xe_firmware.rst |   3 +
>   drivers/gpu/drm/xe/Makefile          |   1 +
>   drivers/gpu/drm/xe/xe_gt.c           |   1 -
>   drivers/gpu/drm/xe/xe_guc.c          |   6 ++
>   drivers/gpu/drm/xe/xe_guc_pc.c       |  70 +++------------
>   drivers/gpu/drm/xe/xe_guc_pc.h       |   1 -
>   drivers/gpu/drm/xe/xe_guc_rc.c       | 129 +++++++++++++++++++++++++++
>   drivers/gpu/drm/xe/xe_guc_rc.h       |  15 ++++
>   drivers/gpu/drm/xe/xe_uc.c           |  10 +--
>   drivers/gpu/drm/xe/xe_uc.h           |   1 -
>   10 files changed, 172 insertions(+), 65 deletions(-)
>   create mode 100644 drivers/gpu/drm/xe/xe_guc_rc.c
>   create mode 100644 drivers/gpu/drm/xe/xe_guc_rc.h
> 
> diff --git a/Documentation/gpu/xe/xe_firmware.rst b/Documentation/gpu/xe/xe_firmware.rst
> index 5d23e9f27391..9c15a300bc62 100644
> --- a/Documentation/gpu/xe/xe_firmware.rst
> +++ b/Documentation/gpu/xe/xe_firmware.rst
> @@ -31,6 +31,9 @@ GuC Power Conservation (PC)
>   .. kernel-doc:: drivers/gpu/drm/xe/xe_guc_pc.c
>      :doc: GuC Power Conservation (PC)
>   
> +.. kernel-doc:: drivers/gpu/drm/xe/xe_guc_rc.c
> +   :doc: GuC Render C-states (GuC RC)
> +
>   PCIe Gen5 Limitations
>   =====================
>   
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 51a9a531fb7e..41ec698b3cc1 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -74,6 +74,7 @@ xe-y += xe_bb.o \
>   	xe_guc_log.o \
>   	xe_guc_pagefault.o \
>   	xe_guc_pc.o \
> +	xe_guc_rc.o \
>   	xe_guc_submit.o \
>   	xe_guc_tlb_inval.o \
>   	xe_heci_gsc.o \
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 9d090d0f2438..c8a1d44bbf3a 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -852,7 +852,6 @@ static void gt_reset_worker(struct work_struct *w)
>   	if (IS_SRIOV_PF(gt_to_xe(gt)))
>   		xe_gt_sriov_pf_stop_prepare(gt);
>   
> -	xe_uc_gucrc_disable(&gt->uc);
>   	xe_uc_stop_prepare(&gt->uc);
>   	xe_pagefault_reset(gt_to_xe(gt), gt);
>   
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 2efc4678fa73..dc198d499da3 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -35,6 +35,7 @@
>   #include "xe_guc_klv_helpers.h"
>   #include "xe_guc_log.h"
>   #include "xe_guc_pc.h"
> +#include "xe_guc_rc.h"
>   #include "xe_guc_relay.h"
>   #include "xe_guc_submit.h"
>   #include "xe_memirq.h"
> @@ -880,6 +881,10 @@ int xe_guc_init_post_hwconfig(struct xe_guc *guc)
>   	if (ret)
>   		return ret;
>   
> +	ret = xe_guc_rc_init(guc);
> +	if (ret)
> +		return ret;
> +
>   	ret = xe_guc_engine_activity_init(guc);
>   	if (ret)
>   		return ret;
> @@ -1620,6 +1625,7 @@ void xe_guc_stop_prepare(struct xe_guc *guc)
>   	if (!IS_SRIOV_VF(guc_to_xe(guc))) {
>   		int err;
>   
> +		xe_guc_rc_disable(guc);
>   		err = xe_guc_pc_stop(&guc->pc);
>   		xe_gt_WARN(guc_to_gt(guc), err, "Failed to stop GuC PC: %pe\n",
>   			   ERR_PTR(err));
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index 5e5495a39a3c..878eb273c3e6 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -92,6 +92,17 @@
>    * Render-C states is also a GuC PC feature that is now enabled in Xe for
>    * all platforms.
>    *
> + * Implementation details:
> + * -----------------------
> + * The implementation for GuC Power Management features is split as follows:
> + *
> + * xe_guc_rc:  Logic for handling GuC RC
> + * xe_gt_idle: Host side logic for RC6 and Coarse Power gating (CPG)
> + * xe_guc_pc:  Logic for all other SLPC related features
> + *
> + * There is some cross interaction between these where host C6 will need to be
> + * enabled when we plan to skip GuC RC. Also, the GuC RC mode is currently
> + * overridden through 0x3003 which is an SLPC H2G call.
>    */
>   
>   static struct xe_guc *pc_to_guc(struct xe_guc_pc *pc)
> @@ -253,22 +264,6 @@ static int pc_action_unset_param(struct xe_guc_pc *pc, u8 id)
>   	return ret;
>   }
>   
> -static int pc_action_setup_gucrc(struct xe_guc_pc *pc, u32 mode)
> -{
> -	struct xe_guc_ct *ct = pc_to_ct(pc);
> -	u32 action[] = {
> -		GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC,
> -		mode,
> -	};
> -	int ret;
> -
> -	ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0);
> -	if (ret && !(xe_device_wedged(pc_to_xe(pc)) && ret == -ECANCELED))
> -		xe_gt_err(pc_to_gt(pc), "GuC RC enable mode=%u failed: %pe\n",
> -			  mode, ERR_PTR(ret));
> -	return ret;
> -}
> -
>   static u32 decode_freq(u32 raw)
>   {
>   	return DIV_ROUND_CLOSEST(raw * GT_FREQUENCY_MULTIPLIER,
> @@ -1050,30 +1045,6 @@ int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc)
>   	return ret;
>   }
>   
> -/**
> - * xe_guc_pc_gucrc_disable - Disable GuC RC
> - * @pc: Xe_GuC_PC instance
> - *
> - * Disables GuC RC by taking control of RC6 back from GuC.
> - *
> - * Return: 0 on success, negative error code on error.
> - */
> -int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc)
> -{
> -	struct xe_device *xe = pc_to_xe(pc);
> -	struct xe_gt *gt = pc_to_gt(pc);
> -	int ret = 0;
> -
> -	if (xe->info.skip_guc_pc)
> -		return 0;
> -
> -	ret = pc_action_setup_gucrc(pc, GUCRC_HOST_CONTROL);
> -	if (ret)
> -		return ret;
> -
> -	return xe_gt_idle_disable_c6(gt);
> -}
> -
>   /**
>    * xe_guc_pc_override_gucrc_mode - override GUCRC mode
>    * @pc: Xe_GuC_PC instance
> @@ -1247,9 +1218,6 @@ int xe_guc_pc_start(struct xe_guc_pc *pc)
>   		return -ETIMEDOUT;
>   
>   	if (xe->info.skip_guc_pc) {
> -		if (xe->info.platform != XE_PVC)
> -			xe_gt_idle_enable_c6(gt);
> -
>   		/* Request max possible since dynamic freq mgmt is not enabled */
>   		pc_set_cur_freq(pc, UINT_MAX);
>   		return 0;
> @@ -1291,15 +1259,6 @@ int xe_guc_pc_start(struct xe_guc_pc *pc)
>   	if (ret)
>   		return ret;
>   
> -	if (xe->info.platform == XE_PVC) {
> -		xe_guc_pc_gucrc_disable(pc);
> -		return 0;
> -	}
> -
> -	ret = pc_action_setup_gucrc(pc, GUCRC_FIRMWARE_CONTROL);
> -	if (ret)
> -		return ret;
> -
>   	/* Enable SLPC Optimized Strategy for compute */
>   	ret = pc_action_set_strategy(pc, SLPC_OPTIMIZED_STRATEGY_COMPUTE);
>   
> @@ -1319,10 +1278,8 @@ int xe_guc_pc_stop(struct xe_guc_pc *pc)
>   {
>   	struct xe_device *xe = pc_to_xe(pc);
>   
> -	if (xe->info.skip_guc_pc) {
> -		xe_gt_idle_disable_c6(pc_to_gt(pc));
> +	if (xe->info.skip_guc_pc)
>   		return 0;
> -	}
>   
>   	mutex_lock(&pc->freq_lock);
>   	pc->freq_ready = false;
> @@ -1343,8 +1300,7 @@ static void xe_guc_pc_fini_hw(void *arg)
>   	if (xe_device_wedged(xe))
>   		return;
>   
> -	CLASS(xe_force_wake, fw_ref)(gt_to_fw(pc_to_gt(pc)), XE_FORCEWAKE_ALL);
> -	xe_guc_pc_gucrc_disable(pc);
> +	CLASS(xe_force_wake, fw_ref)(gt_to_fw(pc_to_gt(pc)), XE_FW_GT);
>   	XE_WARN_ON(xe_guc_pc_stop(pc));
>   
>   	/* Bind requested freq to mert_freq_cap before unload */
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h b/drivers/gpu/drm/xe/xe_guc_pc.h
> index 0e31396f103c..1b95873b262e 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.h
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.h
> @@ -15,7 +15,6 @@ struct drm_printer;
>   int xe_guc_pc_init(struct xe_guc_pc *pc);
>   int xe_guc_pc_start(struct xe_guc_pc *pc);
>   int xe_guc_pc_stop(struct xe_guc_pc *pc);
> -int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc);
>   int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode);
>   int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc);
>   void xe_guc_pc_print(struct xe_guc_pc *pc, struct drm_printer *p);
> diff --git a/drivers/gpu/drm/xe/xe_guc_rc.c b/drivers/gpu/drm/xe/xe_guc_rc.c
> new file mode 100644
> index 000000000000..55eeee7b1011
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_guc_rc.c
> @@ -0,0 +1,129 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include <drm/drm_print.h>
> +
> +#include "abi/guc_actions_slpc_abi.h"
> +#include "xe_device.h"
> +#include "xe_force_wake.h"
> +#include "xe_gt.h"
> +#include "xe_gt_idle.h"
> +#include "xe_gt_printk.h"
> +#include "xe_guc.h"
> +#include "xe_guc_ct.h"
> +#include "xe_guc_rc.h"
> +#include "xe_pm.h"
> +
> +/**
> + * DOC: GuC RC (Render C-states)
> + *
> + * GuC handles the GT transition to deeper C-states in conjunction with Pcode.
> + * GuC RC can be enabled independently of the frequency component in SLPC,
> + * which is also controlled by GuC.
> + *
> + * This file will contain all H2G related logic for handling Render C-states.
> + * There are some calls to xe_gt_idle, where we enable host C6 when GuC RC is
> + * skipped. GuC RC is mostly independent of xe_guc_pc with the exception of
> + * functions that override the mode for which we have to rely on the SLPC H2G
> + * calls.
> + */
> +
> +static int guc_action_setup_gucrc(struct xe_guc *guc, u32 control)
> +{
> +	u32 action[] = {
> +		GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC,
> +		control,
> +	};
> +	int ret;
> +
> +	ret = xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
> +	if (ret && !(xe_device_wedged(guc_to_xe(guc)) && ret == -ECANCELED))
> +		xe_gt_err(guc_to_gt(guc),
> +			  "GuC RC setup %s(%u) failed (%pe)\n",
> +			   control == GUCRC_HOST_CONTROL ? "HOST_CONTROL" :
> +			   control == GUCRC_FIRMWARE_CONTROL ? "FIRMWARE_CONTROL" :
> +			   "UNKNOWN", control, ERR_PTR(ret));
> +	return ret;
> +}
> +
> +/**
> + * xe_guc_rc_disable() - Disable GuC RC
> + * @guc: Xe GuC instance
> + *
> + * Disables GuC RC by taking control of RC6 back from GuC.
> + */
> +void xe_guc_rc_disable(struct xe_guc *guc)
> +{
> +	struct xe_device *xe = guc_to_xe(guc);
> +
> +	if (!xe->info.skip_guc_pc && xe->info.platform != XE_PVC)
> +		if (guc_action_setup_gucrc(guc, GUCRC_HOST_CONTROL))
> +			return;
> +
> +	xe_gt_WARN_ON(guc_to_gt(guc), xe_gt_idle_disable_c6(guc_to_gt(guc)));
> +}
> +
> +static void xe_guc_rc_fini_hw(void *arg)
> +{
> +	struct xe_guc *guc = arg;
> +	struct xe_device *xe = guc_to_xe(guc);
> +	struct xe_gt *gt = guc_to_gt(guc);
> +
> +	if (xe_device_wedged(xe))
> +		return;
> +
> +	CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
> +	xe_guc_rc_disable(guc);
> +}
> +
> +/**
> + * xe_guc_rc_init() - Init GuC RC
> + * @guc: Xe GuC instance
> + *
> + * Add callback action for GuC RC
> + *
> + * Return: 0 on success, negative error code on error.
> + */
> +int xe_guc_rc_init(struct xe_guc *guc)
> +{
> +	struct xe_device *xe = guc_to_xe(guc);
> +	struct xe_gt *gt = guc_to_gt(guc);
> +
> +	xe_gt_assert(gt, xe_device_uc_enabled(xe));
> +
> +	return devm_add_action_or_reset(xe->drm.dev, xe_guc_rc_fini_hw, guc);
> +}
> +
> +/**
> + * xe_guc_rc_enable() - Enable GuC RC feature if applicable
> + * @guc: Xe GuC instance
> + *
> + * Enables GuC RC feature.
> + *
> + * Return: 0 on success, negative error code on error.
> + */
> +int xe_guc_rc_enable(struct xe_guc *guc)
> +{
> +	struct xe_device *xe = guc_to_xe(guc);
> +	struct xe_gt *gt = guc_to_gt(guc);
> +
> +	xe_gt_assert(gt, xe_device_uc_enabled(xe));
> +
> +	CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
> +	if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FW_GT))
> +		return -ETIMEDOUT;
> +
> +	if (xe->info.platform == XE_PVC) {
> +		xe_guc_rc_disable(guc);
> +		return 0;
> +	}
> +
> +	if (xe->info.skip_guc_pc) {
> +		xe_gt_idle_enable_c6(gt);
> +		return 0;
> +	}
> +
> +	return guc_action_setup_gucrc(guc, GUCRC_FIRMWARE_CONTROL);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_guc_rc.h b/drivers/gpu/drm/xe/xe_guc_rc.h
> new file mode 100644
> index 000000000000..35fabb82cb0e
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_guc_rc.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_GUC_RC_H_
> +#define _XE_GUC_RC_H_
> +
> +struct xe_guc;
> +
> +int xe_guc_rc_init(struct xe_guc *guc);
> +void xe_guc_rc_disable(struct xe_guc *guc);
> +int xe_guc_rc_enable(struct xe_guc *guc);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c
> index 3f63c2a7e86d..d9aa845a308d 100644
> --- a/drivers/gpu/drm/xe/xe_uc.c
> +++ b/drivers/gpu/drm/xe/xe_uc.c
> @@ -13,6 +13,7 @@
>   #include "xe_gt_sriov_vf.h"
>   #include "xe_guc.h"
>   #include "xe_guc_pc.h"
> +#include "xe_guc_rc.h"
>   #include "xe_guc_engine_activity.h"
>   #include "xe_huc.h"
>   #include "xe_sriov.h"
> @@ -214,6 +215,10 @@ int xe_uc_load_hw(struct xe_uc *uc)
>   	if (ret)
>   		goto err_out;
>   
> +	ret = xe_guc_rc_enable(&uc->guc);
> +	if (ret)
> +		goto err_out;
> +
>   	xe_guc_engine_activity_enable_stats(&uc->guc);
>   
>   	/* We don't fail the driver load if HuC fails to auth */
> @@ -242,11 +247,6 @@ int xe_uc_reset_prepare(struct xe_uc *uc)
>   	return xe_guc_reset_prepare(&uc->guc);
>   }
>   
> -void xe_uc_gucrc_disable(struct xe_uc *uc)
> -{
> -	XE_WARN_ON(xe_guc_pc_gucrc_disable(&uc->guc.pc));
> -}
> -
>   void xe_uc_stop_prepare(struct xe_uc *uc)
>   {
>   	xe_gsc_stop_prepare(&uc->gsc);
> diff --git a/drivers/gpu/drm/xe/xe_uc.h b/drivers/gpu/drm/xe/xe_uc.h
> index 5398da1a8097..255a54a8f876 100644
> --- a/drivers/gpu/drm/xe/xe_uc.h
> +++ b/drivers/gpu/drm/xe/xe_uc.h
> @@ -12,7 +12,6 @@ int xe_uc_init_noalloc(struct xe_uc *uc);
>   int xe_uc_init(struct xe_uc *uc);
>   int xe_uc_init_post_hwconfig(struct xe_uc *uc);
>   int xe_uc_load_hw(struct xe_uc *uc);
> -void xe_uc_gucrc_disable(struct xe_uc *uc);
>   int xe_uc_reset_prepare(struct xe_uc *uc);
>   void xe_uc_runtime_resume(struct xe_uc *uc);
>   void xe_uc_runtime_suspend(struct xe_uc *uc);

Re: [PATCH v7 1/2] drm/xe: Decouple GuC RC code from xe_guc_pc

[Michal Wajdeczko]

On 1/28/2026 3:23 AM, Vinay Belgaumkar wrote:
> Move enable/disable GuC RC logic into the new file. This will
> allow us to independently enable/disable GuC RC and not rely
> on SLPC related functions. GuC already provides separate H2G
> interfaces to setup GuC RC and SLPC.
> 
> Cc: Riana Tauro <riana.tauro@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> ---
> v2: Comments (Michal W), remove duplicate c6_enable calls from
> xe_guc_pc.
> 
> v3: Clarify crosss interactions between xe_guc_rc and xe_guc_pc
> (Michal W)
> 
> v4: More comments (Michal W)
> 
> v5: Remove rc_init and use enable/disable (Riana)
> 
> v6: Link to kernel docs (Riana)
> 
> v7: Don't call devm_add_action_or_reset() in rc_enable (Michal W)
> ---
>  Documentation/gpu/xe/xe_firmware.rst |   3 +
>  drivers/gpu/drm/xe/Makefile          |   1 +
>  drivers/gpu/drm/xe/xe_gt.c           |   1 -
>  drivers/gpu/drm/xe/xe_guc.c          |   6 ++
>  drivers/gpu/drm/xe/xe_guc_pc.c       |  70 +++------------
>  drivers/gpu/drm/xe/xe_guc_pc.h       |   1 -
>  drivers/gpu/drm/xe/xe_guc_rc.c       | 129 +++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_guc_rc.h       |  15 ++++
>  drivers/gpu/drm/xe/xe_uc.c           |  10 +--
>  drivers/gpu/drm/xe/xe_uc.h           |   1 -
>  10 files changed, 172 insertions(+), 65 deletions(-)
>  create mode 100644 drivers/gpu/drm/xe/xe_guc_rc.c
>  create mode 100644 drivers/gpu/drm/xe/xe_guc_rc.h
> 
> diff --git a/Documentation/gpu/xe/xe_firmware.rst b/Documentation/gpu/xe/xe_firmware.rst
> index 5d23e9f27391..9c15a300bc62 100644
> --- a/Documentation/gpu/xe/xe_firmware.rst
> +++ b/Documentation/gpu/xe/xe_firmware.rst
> @@ -31,6 +31,9 @@ GuC Power Conservation (PC)
>  .. kernel-doc:: drivers/gpu/drm/xe/xe_guc_pc.c
>     :doc: GuC Power Conservation (PC)
>  
> +.. kernel-doc:: drivers/gpu/drm/xe/xe_guc_rc.c
> +   :doc: GuC Render C-states (GuC RC)
> +
>  PCIe Gen5 Limitations
>  =====================
>  
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 51a9a531fb7e..41ec698b3cc1 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -74,6 +74,7 @@ xe-y += xe_bb.o \
>  	xe_guc_log.o \
>  	xe_guc_pagefault.o \
>  	xe_guc_pc.o \
> +	xe_guc_rc.o \
>  	xe_guc_submit.o \
>  	xe_guc_tlb_inval.o \
>  	xe_heci_gsc.o \
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 9d090d0f2438..c8a1d44bbf3a 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -852,7 +852,6 @@ static void gt_reset_worker(struct work_struct *w)
>  	if (IS_SRIOV_PF(gt_to_xe(gt)))
>  		xe_gt_sriov_pf_stop_prepare(gt);
>  
> -	xe_uc_gucrc_disable(&gt->uc);
>  	xe_uc_stop_prepare(&gt->uc);
>  	xe_pagefault_reset(gt_to_xe(gt), gt);
>  
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 2efc4678fa73..dc198d499da3 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -35,6 +35,7 @@
>  #include "xe_guc_klv_helpers.h"
>  #include "xe_guc_log.h"
>  #include "xe_guc_pc.h"
> +#include "xe_guc_rc.h"
>  #include "xe_guc_relay.h"
>  #include "xe_guc_submit.h"
>  #include "xe_memirq.h"
> @@ -880,6 +881,10 @@ int xe_guc_init_post_hwconfig(struct xe_guc *guc)
>  	if (ret)
>  		return ret;
>  
> +	ret = xe_guc_rc_init(guc);
> +	if (ret)
> +		return ret;
> +
>  	ret = xe_guc_engine_activity_init(guc);
>  	if (ret)
>  		return ret;
> @@ -1620,6 +1625,7 @@ void xe_guc_stop_prepare(struct xe_guc *guc)
>  	if (!IS_SRIOV_VF(guc_to_xe(guc))) {
>  		int err;
>  
> +		xe_guc_rc_disable(guc);
>  		err = xe_guc_pc_stop(&guc->pc);
>  		xe_gt_WARN(guc_to_gt(guc), err, "Failed to stop GuC PC: %pe\n",
>  			   ERR_PTR(err));
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index 5e5495a39a3c..878eb273c3e6 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -92,6 +92,17 @@
>   * Render-C states is also a GuC PC feature that is now enabled in Xe for
>   * all platforms.
>   *
> + * Implementation details:
> + * -----------------------
> + * The implementation for GuC Power Management features is split as follows:
> + *
> + * xe_guc_rc:  Logic for handling GuC RC
> + * xe_gt_idle: Host side logic for RC6 and Coarse Power gating (CPG)
> + * xe_guc_pc:  Logic for all other SLPC related features
> + *
> + * There is some cross interaction between these where host C6 will need to be
> + * enabled when we plan to skip GuC RC. Also, the GuC RC mode is currently
> + * overridden through 0x3003 which is an SLPC H2G call.
>   */
>  
>  static struct xe_guc *pc_to_guc(struct xe_guc_pc *pc)
> @@ -253,22 +264,6 @@ static int pc_action_unset_param(struct xe_guc_pc *pc, u8 id)
>  	return ret;
>  }
>  
> -static int pc_action_setup_gucrc(struct xe_guc_pc *pc, u32 mode)
> -{
> -	struct xe_guc_ct *ct = pc_to_ct(pc);
> -	u32 action[] = {
> -		GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC,
> -		mode,
> -	};
> -	int ret;
> -
> -	ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0);
> -	if (ret && !(xe_device_wedged(pc_to_xe(pc)) && ret == -ECANCELED))
> -		xe_gt_err(pc_to_gt(pc), "GuC RC enable mode=%u failed: %pe\n",
> -			  mode, ERR_PTR(ret));
> -	return ret;
> -}
> -
>  static u32 decode_freq(u32 raw)
>  {
>  	return DIV_ROUND_CLOSEST(raw * GT_FREQUENCY_MULTIPLIER,
> @@ -1050,30 +1045,6 @@ int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc)
>  	return ret;
>  }
>  
> -/**
> - * xe_guc_pc_gucrc_disable - Disable GuC RC
> - * @pc: Xe_GuC_PC instance
> - *
> - * Disables GuC RC by taking control of RC6 back from GuC.
> - *
> - * Return: 0 on success, negative error code on error.
> - */
> -int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc)
> -{
> -	struct xe_device *xe = pc_to_xe(pc);
> -	struct xe_gt *gt = pc_to_gt(pc);
> -	int ret = 0;
> -
> -	if (xe->info.skip_guc_pc)
> -		return 0;
> -
> -	ret = pc_action_setup_gucrc(pc, GUCRC_HOST_CONTROL);
> -	if (ret)
> -		return ret;
> -
> -	return xe_gt_idle_disable_c6(gt);
> -}
> -
>  /**
>   * xe_guc_pc_override_gucrc_mode - override GUCRC mode
>   * @pc: Xe_GuC_PC instance
> @@ -1247,9 +1218,6 @@ int xe_guc_pc_start(struct xe_guc_pc *pc)
>  		return -ETIMEDOUT;
>  
>  	if (xe->info.skip_guc_pc) {
> -		if (xe->info.platform != XE_PVC)
> -			xe_gt_idle_enable_c6(gt);
> -
>  		/* Request max possible since dynamic freq mgmt is not enabled */
>  		pc_set_cur_freq(pc, UINT_MAX);
>  		return 0;
> @@ -1291,15 +1259,6 @@ int xe_guc_pc_start(struct xe_guc_pc *pc)
>  	if (ret)
>  		return ret;
>  
> -	if (xe->info.platform == XE_PVC) {
> -		xe_guc_pc_gucrc_disable(pc);
> -		return 0;
> -	}
> -
> -	ret = pc_action_setup_gucrc(pc, GUCRC_FIRMWARE_CONTROL);
> -	if (ret)
> -		return ret;
> -
>  	/* Enable SLPC Optimized Strategy for compute */
>  	ret = pc_action_set_strategy(pc, SLPC_OPTIMIZED_STRATEGY_COMPUTE);
>  
> @@ -1319,10 +1278,8 @@ int xe_guc_pc_stop(struct xe_guc_pc *pc)
>  {
>  	struct xe_device *xe = pc_to_xe(pc);
>  
> -	if (xe->info.skip_guc_pc) {
> -		xe_gt_idle_disable_c6(pc_to_gt(pc));
> +	if (xe->info.skip_guc_pc)
>  		return 0;
> -	}
>  
>  	mutex_lock(&pc->freq_lock);
>  	pc->freq_ready = false;
> @@ -1343,8 +1300,7 @@ static void xe_guc_pc_fini_hw(void *arg)
>  	if (xe_device_wedged(xe))
>  		return;
>  
> -	CLASS(xe_force_wake, fw_ref)(gt_to_fw(pc_to_gt(pc)), XE_FORCEWAKE_ALL);
> -	xe_guc_pc_gucrc_disable(pc);
> +	CLASS(xe_force_wake, fw_ref)(gt_to_fw(pc_to_gt(pc)), XE_FW_GT);

this FW_ALL => FW_GT change probably should be done in a separate patch

>  	XE_WARN_ON(xe_guc_pc_stop(pc));
>  
>  	/* Bind requested freq to mert_freq_cap before unload */
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h b/drivers/gpu/drm/xe/xe_guc_pc.h
> index 0e31396f103c..1b95873b262e 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.h
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.h
> @@ -15,7 +15,6 @@ struct drm_printer;
>  int xe_guc_pc_init(struct xe_guc_pc *pc);
>  int xe_guc_pc_start(struct xe_guc_pc *pc);
>  int xe_guc_pc_stop(struct xe_guc_pc *pc);
> -int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc);
>  int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode);
>  int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc);
>  void xe_guc_pc_print(struct xe_guc_pc *pc, struct drm_printer *p);
> diff --git a/drivers/gpu/drm/xe/xe_guc_rc.c b/drivers/gpu/drm/xe/xe_guc_rc.c
> new file mode 100644
> index 000000000000..55eeee7b1011
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_guc_rc.c
> @@ -0,0 +1,129 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include <drm/drm_print.h>
> +
> +#include "abi/guc_actions_slpc_abi.h"
> +#include "xe_device.h"
> +#include "xe_force_wake.h"
> +#include "xe_gt.h"
> +#include "xe_gt_idle.h"
> +#include "xe_gt_printk.h"
> +#include "xe_guc.h"
> +#include "xe_guc_ct.h"
> +#include "xe_guc_rc.h"
> +#include "xe_pm.h"
> +
> +/**
> + * DOC: GuC RC (Render C-states)
> + *
> + * GuC handles the GT transition to deeper C-states in conjunction with Pcode.
> + * GuC RC can be enabled independently of the frequency component in SLPC,
> + * which is also controlled by GuC.
> + *
> + * This file will contain all H2G related logic for handling Render C-states.
> + * There are some calls to xe_gt_idle, where we enable host C6 when GuC RC is
> + * skipped. GuC RC is mostly independent of xe_guc_pc with the exception of
> + * functions that override the mode for which we have to rely on the SLPC H2G
> + * calls.
> + */
> +
> +static int guc_action_setup_gucrc(struct xe_guc *guc, u32 control)
> +{
> +	u32 action[] = {
> +		GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC,
> +		control,
> +	};
> +	int ret;
> +
> +	ret = xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
> +	if (ret && !(xe_device_wedged(guc_to_xe(guc)) && ret == -ECANCELED))

nit: I still think we should have this 'H2G canceled due to wedge' logic inside a CTB layer as this is applicable scenario for other H2G actions as well, but this could be improved later

> +		xe_gt_err(guc_to_gt(guc),
> +			  "GuC RC setup %s(%u) failed (%pe)\n",
> +			   control == GUCRC_HOST_CONTROL ? "HOST_CONTROL" :
> +			   control == GUCRC_FIRMWARE_CONTROL ? "FIRMWARE_CONTROL" :
> +			   "UNKNOWN", control, ERR_PTR(ret));
> +	return ret;
> +}
> +
> +/**
> + * xe_guc_rc_disable() - Disable GuC RC
> + * @guc: Xe GuC instance
> + *
> + * Disables GuC RC by taking control of RC6 back from GuC.
> + */
> +void xe_guc_rc_disable(struct xe_guc *guc)
> +{
> +	struct xe_device *xe = guc_to_xe(guc);
> +
> +	if (!xe->info.skip_guc_pc && xe->info.platform != XE_PVC)
> +		if (guc_action_setup_gucrc(guc, GUCRC_HOST_CONTROL))
> +			return;
> +
> +	xe_gt_WARN_ON(guc_to_gt(guc), xe_gt_idle_disable_c6(guc_to_gt(guc)));

nit: maybe it's worth to have local var:

	struct xe_gt *gt = guc_to_gt(guc);

> +}
> +
> +static void xe_guc_rc_fini_hw(void *arg)
> +{
> +	struct xe_guc *guc = arg;
> +	struct xe_device *xe = guc_to_xe(guc);
> +	struct xe_gt *gt = guc_to_gt(guc);
> +
> +	if (xe_device_wedged(xe))
> +		return;
> +
> +	CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
> +	xe_guc_rc_disable(guc);
> +}
> +
> +/**
> + * xe_guc_rc_init() - Init GuC RC
> + * @guc: Xe GuC instance
> + *
> + * Add callback action for GuC RC
> + *
> + * Return: 0 on success, negative error code on error.
> + */
> +int xe_guc_rc_init(struct xe_guc *guc)
> +{
> +	struct xe_device *xe = guc_to_xe(guc);
> +	struct xe_gt *gt = guc_to_gt(guc);
> +
> +	xe_gt_assert(gt, xe_device_uc_enabled(xe));
> +
> +	return devm_add_action_or_reset(xe->drm.dev, xe_guc_rc_fini_hw, guc);
> +}
> +
> +/**
> + * xe_guc_rc_enable() - Enable GuC RC feature if applicable
> + * @guc: Xe GuC instance
> + *
> + * Enables GuC RC feature.
> + *
> + * Return: 0 on success, negative error code on error.
> + */
> +int xe_guc_rc_enable(struct xe_guc *guc)
> +{
> +	struct xe_device *xe = guc_to_xe(guc);
> +	struct xe_gt *gt = guc_to_gt(guc);
> +
> +	xe_gt_assert(gt, xe_device_uc_enabled(xe));
> +
> +	CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
> +	if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FW_GT))
> +		return -ETIMEDOUT;
> +
> +	if (xe->info.platform == XE_PVC) {
> +		xe_guc_rc_disable(guc);
> +		return 0;
> +	}
> +
> +	if (xe->info.skip_guc_pc) {
> +		xe_gt_idle_enable_c6(gt);
> +		return 0;
> +	}
> +
> +	return guc_action_setup_gucrc(guc, GUCRC_FIRMWARE_CONTROL);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_guc_rc.h b/drivers/gpu/drm/xe/xe_guc_rc.h
> new file mode 100644
> index 000000000000..35fabb82cb0e
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_guc_rc.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_GUC_RC_H_
> +#define _XE_GUC_RC_H_
> +
> +struct xe_guc;
> +
> +int xe_guc_rc_init(struct xe_guc *guc);
> +void xe_guc_rc_disable(struct xe_guc *guc);
> +int xe_guc_rc_enable(struct xe_guc *guc);

nit: maybe they should be listed in the use-order?

	init
	enable
	disable

> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c
> index 3f63c2a7e86d..d9aa845a308d 100644
> --- a/drivers/gpu/drm/xe/xe_uc.c
> +++ b/drivers/gpu/drm/xe/xe_uc.c
> @@ -13,6 +13,7 @@
>  #include "xe_gt_sriov_vf.h"
>  #include "xe_guc.h"
>  #include "xe_guc_pc.h"
> +#include "xe_guc_rc.h"
>  #include "xe_guc_engine_activity.h"
>  #include "xe_huc.h"
>  #include "xe_sriov.h"
> @@ -214,6 +215,10 @@ int xe_uc_load_hw(struct xe_uc *uc)
>  	if (ret)
>  		goto err_out;
>  
> +	ret = xe_guc_rc_enable(&uc->guc);
> +	if (ret)
> +		goto err_out;
> +
>  	xe_guc_engine_activity_enable_stats(&uc->guc);
>  
>  	/* We don't fail the driver load if HuC fails to auth */
> @@ -242,11 +247,6 @@ int xe_uc_reset_prepare(struct xe_uc *uc)
>  	return xe_guc_reset_prepare(&uc->guc);
>  }
>  
> -void xe_uc_gucrc_disable(struct xe_uc *uc)
> -{
> -	XE_WARN_ON(xe_guc_pc_gucrc_disable(&uc->guc.pc));
> -}
> -
>  void xe_uc_stop_prepare(struct xe_uc *uc)
>  {
>  	xe_gsc_stop_prepare(&uc->gsc);
> diff --git a/drivers/gpu/drm/xe/xe_uc.h b/drivers/gpu/drm/xe/xe_uc.h
> index 5398da1a8097..255a54a8f876 100644
> --- a/drivers/gpu/drm/xe/xe_uc.h
> +++ b/drivers/gpu/drm/xe/xe_uc.h
> @@ -12,7 +12,6 @@ int xe_uc_init_noalloc(struct xe_uc *uc);
>  int xe_uc_init(struct xe_uc *uc);
>  int xe_uc_init_post_hwconfig(struct xe_uc *uc);
>  int xe_uc_load_hw(struct xe_uc *uc);
> -void xe_uc_gucrc_disable(struct xe_uc *uc);
>  int xe_uc_reset_prepare(struct xe_uc *uc);
>  void xe_uc_runtime_resume(struct xe_uc *uc);
>  void xe_uc_runtime_suspend(struct xe_uc *uc);

IMO one change deserves a separate patch
also few nits, but otherwise looks good,

Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

Re: [PATCH v7 1/2] drm/xe: Decouple GuC RC code from xe_guc_pc

[Belgaumkar, Vinay]

On 2/3/2026 8:46 AM, Michal Wajdeczko wrote:
> On 1/28/2026 3:23 AM, Vinay Belgaumkar wrote:
>> Move enable/disable GuC RC logic into the new file. This will
>> allow us to independently enable/disable GuC RC and not rely
>> on SLPC related functions. GuC already provides separate H2G
>> interfaces to setup GuC RC and SLPC.
>>
>> Cc: Riana Tauro<riana.tauro@intel.com>
>> Cc: Michal Wajdeczko<michal.wajdeczko@intel.com>
>> Signed-off-by: Vinay Belgaumkar<vinay.belgaumkar@intel.com>
>> ---
>> v2: Comments (Michal W), remove duplicate c6_enable calls from
>> xe_guc_pc.
>>
>> v3: Clarify crosss interactions between xe_guc_rc and xe_guc_pc
>> (Michal W)
>>
>> v4: More comments (Michal W)
>>
>> v5: Remove rc_init and use enable/disable (Riana)
>>
>> v6: Link to kernel docs (Riana)
>>
>> v7: Don't call devm_add_action_or_reset() in rc_enable (Michal W)
>> ---
>>   Documentation/gpu/xe/xe_firmware.rst |   3 +
>>   drivers/gpu/drm/xe/Makefile          |   1 +
>>   drivers/gpu/drm/xe/xe_gt.c           |   1 -
>>   drivers/gpu/drm/xe/xe_guc.c          |   6 ++
>>   drivers/gpu/drm/xe/xe_guc_pc.c       |  70 +++------------
>>   drivers/gpu/drm/xe/xe_guc_pc.h       |   1 -
>>   drivers/gpu/drm/xe/xe_guc_rc.c       | 129 +++++++++++++++++++++++++++
>>   drivers/gpu/drm/xe/xe_guc_rc.h       |  15 ++++
>>   drivers/gpu/drm/xe/xe_uc.c           |  10 +--
>>   drivers/gpu/drm/xe/xe_uc.h           |   1 -
>>   10 files changed, 172 insertions(+), 65 deletions(-)
>>   create mode 100644 drivers/gpu/drm/xe/xe_guc_rc.c
>>   create mode 100644 drivers/gpu/drm/xe/xe_guc_rc.h
>>
>> diff --git a/Documentation/gpu/xe/xe_firmware.rst b/Documentation/gpu/xe/xe_firmware.rst
>> index 5d23e9f27391..9c15a300bc62 100644
>> --- a/Documentation/gpu/xe/xe_firmware.rst
>> +++ b/Documentation/gpu/xe/xe_firmware.rst
>> @@ -31,6 +31,9 @@ GuC Power Conservation (PC)
>>   .. kernel-doc:: drivers/gpu/drm/xe/xe_guc_pc.c
>>      :doc: GuC Power Conservation (PC)
>>   
>> +.. kernel-doc:: drivers/gpu/drm/xe/xe_guc_rc.c
>> +   :doc: GuC Render C-states (GuC RC)
>> +
>>   PCIe Gen5 Limitations
>>   =====================
>>   
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index 51a9a531fb7e..41ec698b3cc1 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -74,6 +74,7 @@ xe-y += xe_bb.o \
>>   	xe_guc_log.o \
>>   	xe_guc_pagefault.o \
>>   	xe_guc_pc.o \
>> +	xe_guc_rc.o \
>>   	xe_guc_submit.o \
>>   	xe_guc_tlb_inval.o \
>>   	xe_heci_gsc.o \
>> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>> index 9d090d0f2438..c8a1d44bbf3a 100644
>> --- a/drivers/gpu/drm/xe/xe_gt.c
>> +++ b/drivers/gpu/drm/xe/xe_gt.c
>> @@ -852,7 +852,6 @@ static void gt_reset_worker(struct work_struct *w)
>>   	if (IS_SRIOV_PF(gt_to_xe(gt)))
>>   		xe_gt_sriov_pf_stop_prepare(gt);
>>   
>> -	xe_uc_gucrc_disable(&gt->uc);
>>   	xe_uc_stop_prepare(&gt->uc);
>>   	xe_pagefault_reset(gt_to_xe(gt), gt);
>>   
>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>> index 2efc4678fa73..dc198d499da3 100644
>> --- a/drivers/gpu/drm/xe/xe_guc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>> @@ -35,6 +35,7 @@
>>   #include "xe_guc_klv_helpers.h"
>>   #include "xe_guc_log.h"
>>   #include "xe_guc_pc.h"
>> +#include "xe_guc_rc.h"
>>   #include "xe_guc_relay.h"
>>   #include "xe_guc_submit.h"
>>   #include "xe_memirq.h"
>> @@ -880,6 +881,10 @@ int xe_guc_init_post_hwconfig(struct xe_guc *guc)
>>   	if (ret)
>>   		return ret;
>>   
>> +	ret = xe_guc_rc_init(guc);
>> +	if (ret)
>> +		return ret;
>> +
>>   	ret = xe_guc_engine_activity_init(guc);
>>   	if (ret)
>>   		return ret;
>> @@ -1620,6 +1625,7 @@ void xe_guc_stop_prepare(struct xe_guc *guc)
>>   	if (!IS_SRIOV_VF(guc_to_xe(guc))) {
>>   		int err;
>>   
>> +		xe_guc_rc_disable(guc);
>>   		err = xe_guc_pc_stop(&guc->pc);
>>   		xe_gt_WARN(guc_to_gt(guc), err, "Failed to stop GuC PC: %pe\n", ERR_PTR(err)); diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c 
>> b/drivers/gpu/drm/xe/xe_guc_pc.c index 5e5495a39a3c..878eb273c3e6 
>> 100644 --- a/drivers/gpu/drm/xe/xe_guc_pc.c +++ 
>> b/drivers/gpu/drm/xe/xe_guc_pc.c @@ -92,6 +92,17 @@ * Render-C states 
>> is also a GuC PC feature that is now enabled in Xe for * all 
>> platforms. * + * Implementation details: + * ----------------------- 
>> + * The implementation for GuC Power Management features is split as 
>> follows: + * + * xe_guc_rc: Logic for handling GuC RC + * xe_gt_idle: 
>> Host side logic for RC6 and Coarse Power gating (CPG) + * xe_guc_pc: 
>> Logic for all other SLPC related features + * + * There is some cross 
>> interaction between these where host C6 will need to be + * enabled 
>> when we plan to skip GuC RC. Also, the GuC RC mode is currently + * 
>> overridden through 0x3003 which is an SLPC H2G call. */ static struct 
>> xe_guc *pc_to_guc(struct xe_guc_pc *pc) @@ -253,22 +264,6 @@ static 
>> int pc_action_unset_param(struct xe_guc_pc *pc, u8 id) return ret; } 
>> -static int pc_action_setup_gucrc(struct xe_guc_pc *pc, u32 mode) -{ 
>> - struct xe_guc_ct *ct = pc_to_ct(pc); - u32 action[] = { - 
>> GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC, - mode, - }; - int ret; - - ret = 
>> xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0); - if (ret && 
>> !(xe_device_wedged(pc_to_xe(pc)) && ret == -ECANCELED)) - 
>> xe_gt_err(pc_to_gt(pc), "GuC RC enable mode=%u failed: %pe\n",
>> -			  mode, ERR_PTR(ret));
>> -	return ret;
>> -}
>> -
>>   static u32 decode_freq(u32 raw)
>>   {
>>   	return DIV_ROUND_CLOSEST(raw * GT_FREQUENCY_MULTIPLIER,
>> @@ -1050,30 +1045,6 @@ int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc)
>>   	return ret;
>>   }
>>   
>> -/**
>> - * xe_guc_pc_gucrc_disable - Disable GuC RC
>> - * @pc: Xe_GuC_PC instance
>> - *
>> - * Disables GuC RC by taking control of RC6 back from GuC.
>> - *
>> - * Return: 0 on success, negative error code on error.
>> - */
>> -int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc)
>> -{
>> -	struct xe_device *xe = pc_to_xe(pc);
>> -	struct xe_gt *gt = pc_to_gt(pc);
>> -	int ret = 0;
>> -
>> -	if (xe->info.skip_guc_pc)
>> -		return 0;
>> -
>> -	ret = pc_action_setup_gucrc(pc, GUCRC_HOST_CONTROL);
>> -	if (ret)
>> -		return ret;
>> -
>> -	return xe_gt_idle_disable_c6(gt);
>> -}
>> -
>>   /**
>>    * xe_guc_pc_override_gucrc_mode - override GUCRC mode
>>    * @pc: Xe_GuC_PC instance
>> @@ -1247,9 +1218,6 @@ int xe_guc_pc_start(struct xe_guc_pc *pc)
>>   		return -ETIMEDOUT;
>>   
>>   	if (xe->info.skip_guc_pc) {
>> -		if (xe->info.platform != XE_PVC)
>> -			xe_gt_idle_enable_c6(gt);
>> -
>>   		/* Request max possible since dynamic freq mgmt is not enabled */
>>   		pc_set_cur_freq(pc, UINT_MAX);
>>   		return 0;
>> @@ -1291,15 +1259,6 @@ int xe_guc_pc_start(struct xe_guc_pc *pc)
>>   	if (ret)
>>   		return ret;
>>   
>> -	if (xe->info.platform == XE_PVC) {
>> -		xe_guc_pc_gucrc_disable(pc);
>> -		return 0;
>> -	}
>> -
>> -	ret = pc_action_setup_gucrc(pc, GUCRC_FIRMWARE_CONTROL);
>> -	if (ret)
>> -		return ret;
>> -
>>   	/* Enable SLPC Optimized Strategy for compute */
>>   	ret = pc_action_set_strategy(pc, SLPC_OPTIMIZED_STRATEGY_COMPUTE);
>>   
>> @@ -1319,10 +1278,8 @@ int xe_guc_pc_stop(struct xe_guc_pc *pc)
>>   {
>>   	struct xe_device *xe = pc_to_xe(pc);
>>   
>> -	if (xe->info.skip_guc_pc) {
>> -		xe_gt_idle_disable_c6(pc_to_gt(pc));
>> +	if (xe->info.skip_guc_pc)
>>   		return 0;
>> -	}
>>   
>>   	mutex_lock(&pc->freq_lock);
>>   	pc->freq_ready = false;
>> @@ -1343,8 +1300,7 @@ static void xe_guc_pc_fini_hw(void *arg)
>>   	if (xe_device_wedged(xe))
>>   		return;
>>   
>> -	CLASS(xe_force_wake, fw_ref)(gt_to_fw(pc_to_gt(pc)), XE_FORCEWAKE_ALL);
>> -	xe_guc_pc_gucrc_disable(pc);
>> +	CLASS(xe_force_wake, fw_ref)(gt_to_fw(pc_to_gt(pc)), XE_FW_GT);
> this FW_ALL => FW_GT change probably should be done in a separate patch
ok.
>>   	XE_WARN_ON(xe_guc_pc_stop(pc));
>>   
>>   	/* Bind requested freq to mert_freq_cap before unload */
>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h b/drivers/gpu/drm/xe/xe_guc_pc.h
>> index 0e31396f103c..1b95873b262e 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_pc.h
>> +++ b/drivers/gpu/drm/xe/xe_guc_pc.h
>> @@ -15,7 +15,6 @@ struct drm_printer;
>>   int xe_guc_pc_init(struct xe_guc_pc *pc);
>>   int xe_guc_pc_start(struct xe_guc_pc *pc);
>>   int xe_guc_pc_stop(struct xe_guc_pc *pc);
>> -int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc);
>>   int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode);
>>   int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc);
>>   void xe_guc_pc_print(struct xe_guc_pc *pc, struct drm_printer *p);
>> diff --git a/drivers/gpu/drm/xe/xe_guc_rc.c b/drivers/gpu/drm/xe/xe_guc_rc.c
>> new file mode 100644
>> index 000000000000..55eeee7b1011
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_guc_rc.c
>> @@ -0,0 +1,129 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2026 Intel Corporation
>> + */
>> +
>> +#include <drm/drm_print.h>
>> +
>> +#include "abi/guc_actions_slpc_abi.h"
>> +#include "xe_device.h"
>> +#include "xe_force_wake.h"
>> +#include "xe_gt.h"
>> +#include "xe_gt_idle.h"
>> +#include "xe_gt_printk.h"
>> +#include "xe_guc.h"
>> +#include "xe_guc_ct.h"
>> +#include "xe_guc_rc.h"
>> +#include "xe_pm.h"
>> +
>> +/**
>> + * DOC: GuC RC (Render C-states)
>> + *
>> + * GuC handles the GT transition to deeper C-states in conjunction with Pcode.
>> + * GuC RC can be enabled independently of the frequency component in SLPC,
>> + * which is also controlled by GuC.
>> + *
>> + * This file will contain all H2G related logic for handling Render C-states.
>> + * There are some calls to xe_gt_idle, where we enable host C6 when GuC RC is
>> + * skipped. GuC RC is mostly independent of xe_guc_pc with the exception of
>> + * functions that override the mode for which we have to rely on the SLPC H2G
>> + * calls.
>> + */
>> +
>> +static int guc_action_setup_gucrc(struct xe_guc *guc, u32 control)
>> +{
>> +	u32 action[] = {
>> +		GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC,
>> +		control,
>> +	};
>> +	int ret;
>> +
>> +	ret = xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
>> +	if (ret && !(xe_device_wedged(guc_to_xe(guc)) && ret == -ECANCELED))
> nit: I still think we should have this 'H2G canceled due to wedge' logic inside a CTB layer as this is applicable scenario for other H2G actions as well, but this could be improved later
ok.
>> +		xe_gt_err(guc_to_gt(guc),
>> +			  "GuC RC setup %s(%u) failed (%pe)\n",
>> +			   control == GUCRC_HOST_CONTROL ? "HOST_CONTROL" :
>> +			   control == GUCRC_FIRMWARE_CONTROL ? "FIRMWARE_CONTROL" :
>> +			   "UNKNOWN", control, ERR_PTR(ret));
>> +	return ret;
>> +}
>> +
>> +/**
>> + * xe_guc_rc_disable() - Disable GuC RC
>> + * @guc: Xe GuC instance
>> + *
>> + * Disables GuC RC by taking control of RC6 back from GuC.
>> + */
>> +void xe_guc_rc_disable(struct xe_guc *guc)
>> +{
>> +	struct xe_device *xe = guc_to_xe(guc);
>> +
>> +	if (!xe->info.skip_guc_pc && xe->info.platform != XE_PVC)
>> +		if (guc_action_setup_gucrc(guc, GUCRC_HOST_CONTROL))
>> +			return;
>> +
>> +	xe_gt_WARN_ON(guc_to_gt(guc), xe_gt_idle_disable_c6(guc_to_gt(guc)));
> nit: maybe it's worth to have local var:
>
> 	struct xe_gt *gt = guc_to_gt(guc);
ok.
>> +}
>> +
>> +static void xe_guc_rc_fini_hw(void *arg)
>> +{
>> +	struct xe_guc *guc = arg;
>> +	struct xe_device *xe = guc_to_xe(guc);
>> +	struct xe_gt *gt = guc_to_gt(guc);
>> +
>> +	if (xe_device_wedged(xe))
>> +		return;
>> +
>> +	CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
>> +	xe_guc_rc_disable(guc);
>> +}
>> +
>> +/**
>> + * xe_guc_rc_init() - Init GuC RC
>> + * @guc: Xe GuC instance
>> + *
>> + * Add callback action for GuC RC
>> + *
>> + * Return: 0 on success, negative error code on error.
>> + */
>> +int xe_guc_rc_init(struct xe_guc *guc)
>> +{
>> +	struct xe_device *xe = guc_to_xe(guc);
>> +	struct xe_gt *gt = guc_to_gt(guc);
>> +
>> +	xe_gt_assert(gt, xe_device_uc_enabled(xe));
>> +
>> +	return devm_add_action_or_reset(xe->drm.dev, xe_guc_rc_fini_hw, guc);
>> +}
>> +
>> +/**
>> + * xe_guc_rc_enable() - Enable GuC RC feature if applicable
>> + * @guc: Xe GuC instance
>> + *
>> + * Enables GuC RC feature.
>> + *
>> + * Return: 0 on success, negative error code on error.
>> + */
>> +int xe_guc_rc_enable(struct xe_guc *guc)
>> +{
>> +	struct xe_device *xe = guc_to_xe(guc);
>> +	struct xe_gt *gt = guc_to_gt(guc);
>> +
>> +	xe_gt_assert(gt, xe_device_uc_enabled(xe));
>> +
>> +	CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
>> +	if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FW_GT))
>> +		return -ETIMEDOUT;
>> +
>> +	if (xe->info.platform == XE_PVC) {
>> +		xe_guc_rc_disable(guc);
>> +		return 0;
>> +	}
>> +
>> +	if (xe->info.skip_guc_pc) {
>> +		xe_gt_idle_enable_c6(gt);
>> +		return 0;
>> +	}
>> +
>> +	return guc_action_setup_gucrc(guc, GUCRC_FIRMWARE_CONTROL);
>> +}
>> diff --git a/drivers/gpu/drm/xe/xe_guc_rc.h b/drivers/gpu/drm/xe/xe_guc_rc.h
>> new file mode 100644
>> index 000000000000..35fabb82cb0e
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_guc_rc.h
>> @@ -0,0 +1,15 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2026 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_GUC_RC_H_
>> +#define _XE_GUC_RC_H_
>> +
>> +struct xe_guc;
>> +
>> +int xe_guc_rc_init(struct xe_guc *guc);
>> +void xe_guc_rc_disable(struct xe_guc *guc);
>> +int xe_guc_rc_enable(struct xe_guc *guc);
> nit: maybe they should be listed in the use-order?
>
> 	init
> 	enable
> 	disable
ok.
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c
>> index 3f63c2a7e86d..d9aa845a308d 100644
>> --- a/drivers/gpu/drm/xe/xe_uc.c
>> +++ b/drivers/gpu/drm/xe/xe_uc.c
>> @@ -13,6 +13,7 @@
>>   #include "xe_gt_sriov_vf.h"
>>   #include "xe_guc.h"
>>   #include "xe_guc_pc.h"
>> +#include "xe_guc_rc.h"
>>   #include "xe_guc_engine_activity.h"
>>   #include "xe_huc.h"
>>   #include "xe_sriov.h"
>> @@ -214,6 +215,10 @@ int xe_uc_load_hw(struct xe_uc *uc)
>>   	if (ret)
>>   		goto err_out;
>>   
>> +	ret = xe_guc_rc_enable(&uc->guc);
>> +	if (ret)
>> +		goto err_out;
>> +
>>   	xe_guc_engine_activity_enable_stats(&uc->guc);
>>   
>>   	/* We don't fail the driver load if HuC fails to auth */
>> @@ -242,11 +247,6 @@ int xe_uc_reset_prepare(struct xe_uc *uc)
>>   	return xe_guc_reset_prepare(&uc->guc);
>>   }
>>   
>> -void xe_uc_gucrc_disable(struct xe_uc *uc)
>> -{
>> -	XE_WARN_ON(xe_guc_pc_gucrc_disable(&uc->guc.pc));
>> -}
>> -
>>   void xe_uc_stop_prepare(struct xe_uc *uc)
>>   {
>>   	xe_gsc_stop_prepare(&uc->gsc);
>> diff --git a/drivers/gpu/drm/xe/xe_uc.h b/drivers/gpu/drm/xe/xe_uc.h
>> index 5398da1a8097..255a54a8f876 100644
>> --- a/drivers/gpu/drm/xe/xe_uc.h
>> +++ b/drivers/gpu/drm/xe/xe_uc.h
>> @@ -12,7 +12,6 @@ int xe_uc_init_noalloc(struct xe_uc *uc);
>>   int xe_uc_init(struct xe_uc *uc);
>>   int xe_uc_init_post_hwconfig(struct xe_uc *uc);
>>   int xe_uc_load_hw(struct xe_uc *uc);
>> -void xe_uc_gucrc_disable(struct xe_uc *uc);
>>   int xe_uc_reset_prepare(struct xe_uc *uc);
>>   void xe_uc_runtime_resume(struct xe_uc *uc);
>>   void xe_uc_runtime_suspend(struct xe_uc *uc);
> IMO one change deserves a separate patch
> also few nits, but otherwise looks good,
>
> Reviewed-by: Michal Wajdeczko<michal.wajdeczko@intel.com>

Thanks,

Vinay,

>

[PATCH v7 2/2] drm/xe: Add a wrapper for SLPC set/unset params

[Vinay Belgaumkar]

Also, extract out the GuC RC related set/unset param functions
into xe_guc_rc file. GuC still allows us to override GuC RC mode
using an SLPC H2G interface. Continue to use that interface, but
move the related code to the newly created xe_guc_rc file.

Cc: Riana Tauro <riana.tauro@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
---
v2: xe_guc_rc functions to use guc pointer instead of gt (Michal W)
v3: Assert if runtime pm ref is not held (Michal W)
v4: Review comments (Riana)
v5: Use noresume instead of full resume, update title (Michal)
---
 drivers/gpu/drm/xe/xe_guc_pc.c | 56 +++++++++++++++++++---------------
 drivers/gpu/drm/xe/xe_guc_pc.h |  5 ++-
 drivers/gpu/drm/xe/xe_guc_rc.c | 30 ++++++++++++++++++
 drivers/gpu/drm/xe/xe_guc_rc.h |  3 ++
 drivers/gpu/drm/xe/xe_oa.c     |  9 +++---
 5 files changed, 70 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 878eb273c3e6..21fe73ab4583 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -264,6 +264,37 @@ static int pc_action_unset_param(struct xe_guc_pc *pc, u8 id)
 	return ret;
 }
 
+/**
+ * xe_guc_pc_action_set_param() - Set value of SLPC param
+ * @pc: Xe_GuC_PC instance
+ * @id: Param id
+ * @value: Value to set
+ *
+ * This function can be used to set any SLPC param.
+ *
+ * Return: 0 on Success
+ */
+int xe_guc_pc_action_set_param(struct xe_guc_pc *pc, u8 id, u32 value)
+{
+	xe_device_assert_mem_access(pc_to_xe(pc));
+	return pc_action_set_param(pc, id, value);
+}
+
+/**
+ * xe_guc_pc_action_unset_param() - Revert to default value
+ * @pc: Xe_GuC_PC instance
+ * @id: Param id
+ *
+ * This function can be used revert any SLPC param to its default value.
+ *
+ * Return: 0 on Success
+ */
+int xe_guc_pc_action_unset_param(struct xe_guc_pc *pc, u8 id)
+{
+	xe_device_assert_mem_access(pc_to_xe(pc));
+	return pc_action_unset_param(pc, id);
+}
+
 static u32 decode_freq(u32 raw)
 {
 	return DIV_ROUND_CLOSEST(raw * GT_FREQUENCY_MULTIPLIER,
@@ -1045,31 +1076,6 @@ int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc)
 	return ret;
 }
 
-/**
- * xe_guc_pc_override_gucrc_mode - override GUCRC mode
- * @pc: Xe_GuC_PC instance
- * @mode: new value of the mode.
- *
- * Return: 0 on success, negative error code on error
- */
-int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode)
-{
-	guard(xe_pm_runtime)(pc_to_xe(pc));
-	return pc_action_set_param(pc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
-}
-
-/**
- * xe_guc_pc_unset_gucrc_mode - unset GUCRC mode override
- * @pc: Xe_GuC_PC instance
- *
- * Return: 0 on success, negative error code on error
- */
-int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc)
-{
-	guard(xe_pm_runtime)(pc_to_xe(pc));
-	return pc_action_unset_param(pc, SLPC_PARAM_PWRGATE_RC_MODE);
-}
-
 static void pc_init_pcode_freq(struct xe_guc_pc *pc)
 {
 	u32 min = DIV_ROUND_CLOSEST(pc->rpn_freq, GT_FREQUENCY_MULTIPLIER);
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h b/drivers/gpu/drm/xe/xe_guc_pc.h
index 1b95873b262e..0678a4e787b3 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.h
+++ b/drivers/gpu/drm/xe/xe_guc_pc.h
@@ -9,15 +9,14 @@
 #include <linux/types.h>
 
 struct xe_guc_pc;
-enum slpc_gucrc_mode;
 struct drm_printer;
 
 int xe_guc_pc_init(struct xe_guc_pc *pc);
 int xe_guc_pc_start(struct xe_guc_pc *pc);
 int xe_guc_pc_stop(struct xe_guc_pc *pc);
-int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode);
-int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc);
 void xe_guc_pc_print(struct xe_guc_pc *pc, struct drm_printer *p);
+int xe_guc_pc_action_set_param(struct xe_guc_pc *pc, u8 id, u32 value);
+int xe_guc_pc_action_unset_param(struct xe_guc_pc *pc, u8 id);
 
 u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc);
 int xe_guc_pc_get_cur_freq(struct xe_guc_pc *pc, u32 *freq);
diff --git a/drivers/gpu/drm/xe/xe_guc_rc.c b/drivers/gpu/drm/xe/xe_guc_rc.c
index 55eeee7b1011..a20b20e3dab3 100644
--- a/drivers/gpu/drm/xe/xe_guc_rc.c
+++ b/drivers/gpu/drm/xe/xe_guc_rc.c
@@ -13,6 +13,7 @@
 #include "xe_gt_printk.h"
 #include "xe_guc.h"
 #include "xe_guc_ct.h"
+#include "xe_guc_pc.h"
 #include "xe_guc_rc.h"
 #include "xe_pm.h"
 
@@ -127,3 +128,32 @@ int xe_guc_rc_enable(struct xe_guc *guc)
 
 	return guc_action_setup_gucrc(guc, GUCRC_FIRMWARE_CONTROL);
 }
+
+/**
+ * xe_guc_rc_set_mode() - set GUCRC mode
+ * @guc: Xe GuC instance
+ * @mode: new value of the mode.
+ *
+ * Function to set GuC RC mode to one of the enum values.
+ *
+ * Returns: 0 on success, negative error code on error
+ */
+int xe_guc_rc_set_mode(struct xe_guc *guc, enum slpc_gucrc_mode mode)
+{
+	guard(xe_pm_runtime_noresume)(guc_to_xe(guc));
+	return xe_guc_pc_action_set_param(&guc->pc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
+}
+
+/**
+ * xe_guc_rc_unset_mode() - revert to default mode
+ * @guc: Xe GuC instance
+ *
+ * Function to revert GuC RC mode to platform defaults.
+ *
+ * Returns: 0 on success, negative error code on error
+ */
+int xe_guc_rc_unset_mode(struct xe_guc *guc)
+{
+	guard(xe_pm_runtime_noresume)(guc_to_xe(guc));
+	return xe_guc_pc_action_unset_param(&guc->pc, SLPC_PARAM_PWRGATE_RC_MODE);
+}
diff --git a/drivers/gpu/drm/xe/xe_guc_rc.h b/drivers/gpu/drm/xe/xe_guc_rc.h
index 35fabb82cb0e..36d41329dd0a 100644
--- a/drivers/gpu/drm/xe/xe_guc_rc.h
+++ b/drivers/gpu/drm/xe/xe_guc_rc.h
@@ -7,9 +7,12 @@
 #define _XE_GUC_RC_H_
 
 struct xe_guc;
+enum slpc_gucrc_mode;
 
 int xe_guc_rc_init(struct xe_guc *guc);
 void xe_guc_rc_disable(struct xe_guc *guc);
 int xe_guc_rc_enable(struct xe_guc *guc);
+int xe_guc_rc_set_mode(struct xe_guc *guc, enum slpc_gucrc_mode mode);
+int xe_guc_rc_unset_mode(struct xe_guc *guc);
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index abf87fe0b345..f7752719b74f 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -29,7 +29,7 @@
 #include "xe_gt.h"
 #include "xe_gt_mcr.h"
 #include "xe_gt_printk.h"
-#include "xe_guc_pc.h"
+#include "xe_guc_rc.h"
 #include "xe_macros.h"
 #include "xe_mmio.h"
 #include "xe_oa.h"
@@ -875,7 +875,7 @@ static void xe_oa_stream_destroy(struct xe_oa_stream *stream)
 
 	/* Wa_1509372804:pvc: Unset the override of GUCRC mode to enable rc6 */
 	if (stream->override_gucrc)
-		xe_gt_WARN_ON(gt, xe_guc_pc_unset_gucrc_mode(&gt->uc.guc.pc));
+		xe_gt_WARN_ON(gt, xe_guc_rc_unset_mode(&gt->uc.guc));
 
 	xe_oa_free_configs(stream);
 	xe_file_put(stream->xef);
@@ -1765,8 +1765,7 @@ static int xe_oa_stream_init(struct xe_oa_stream *stream,
 	 * state. Prevent this by overriding GUCRC mode.
 	 */
 	if (XE_GT_WA(stream->gt, 1509372804)) {
-		ret = xe_guc_pc_override_gucrc_mode(&gt->uc.guc.pc,
-						    SLPC_GUCRC_MODE_GUCRC_NO_RC6);
+		ret = xe_guc_rc_set_mode(&gt->uc.guc, SLPC_GUCRC_MODE_GUCRC_NO_RC6);
 		if (ret)
 			goto err_free_configs;
 
@@ -1824,7 +1823,7 @@ static int xe_oa_stream_init(struct xe_oa_stream *stream,
 	xe_force_wake_put(gt_to_fw(gt), stream->fw_ref);
 	xe_pm_runtime_put(stream->oa->xe);
 	if (stream->override_gucrc)
-		xe_gt_WARN_ON(gt, xe_guc_pc_unset_gucrc_mode(&gt->uc.guc.pc));
+		xe_gt_WARN_ON(gt, xe_guc_rc_unset_mode(&gt->uc.guc));
 err_free_configs:
 	xe_oa_free_configs(stream);
 exit:
-- 
2.38.1

Re: [PATCH v7 2/2] drm/xe: Add a wrapper for SLPC set/unset params

[Michal Wajdeczko]

On 1/28/2026 3:23 AM, Vinay Belgaumkar wrote:
> Also, extract out the GuC RC related set/unset param functions
> into xe_guc_rc file. GuC still allows us to override GuC RC mode
> using an SLPC H2G interface. Continue to use that interface, but
> move the related code to the newly created xe_guc_rc file.
> 
> Cc: Riana Tauro <riana.tauro@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Reviewed-by: Riana Tauro <riana.tauro@intel.com>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> ---
> v2: xe_guc_rc functions to use guc pointer instead of gt (Michal W)
> v3: Assert if runtime pm ref is not held (Michal W)
> v4: Review comments (Riana)
> v5: Use noresume instead of full resume, update title (Michal)
> ---
>  drivers/gpu/drm/xe/xe_guc_pc.c | 56 +++++++++++++++++++---------------
>  drivers/gpu/drm/xe/xe_guc_pc.h |  5 ++-
>  drivers/gpu/drm/xe/xe_guc_rc.c | 30 ++++++++++++++++++
>  drivers/gpu/drm/xe/xe_guc_rc.h |  3 ++
>  drivers/gpu/drm/xe/xe_oa.c     |  9 +++---
>  5 files changed, 70 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index 878eb273c3e6..21fe73ab4583 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -264,6 +264,37 @@ static int pc_action_unset_param(struct xe_guc_pc *pc, u8 id)
>  	return ret;
>  }
>  
> +/**
> + * xe_guc_pc_action_set_param() - Set value of SLPC param
> + * @pc: Xe_GuC_PC instance
> + * @id: Param id
> + * @value: Value to set
> + *
> + * This function can be used to set any SLPC param.
> + *
> + * Return: 0 on Success
> + */
> +int xe_guc_pc_action_set_param(struct xe_guc_pc *pc, u8 id, u32 value)
> +{
> +	xe_device_assert_mem_access(pc_to_xe(pc));
> +	return pc_action_set_param(pc, id, value);
> +}
> +
> +/**
> + * xe_guc_pc_action_unset_param() - Revert to default value
> + * @pc: Xe_GuC_PC instance
> + * @id: Param id
> + *
> + * This function can be used revert any SLPC param to its default value.
> + *
> + * Return: 0 on Success
> + */
> +int xe_guc_pc_action_unset_param(struct xe_guc_pc *pc, u8 id)
> +{
> +	xe_device_assert_mem_access(pc_to_xe(pc));
> +	return pc_action_unset_param(pc, id);
> +}
> +
>  static u32 decode_freq(u32 raw)
>  {
>  	return DIV_ROUND_CLOSEST(raw * GT_FREQUENCY_MULTIPLIER,
> @@ -1045,31 +1076,6 @@ int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc)
>  	return ret;
>  }
>  
> -/**
> - * xe_guc_pc_override_gucrc_mode - override GUCRC mode
> - * @pc: Xe_GuC_PC instance
> - * @mode: new value of the mode.
> - *
> - * Return: 0 on success, negative error code on error
> - */
> -int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode)
> -{
> -	guard(xe_pm_runtime)(pc_to_xe(pc));
> -	return pc_action_set_param(pc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
> -}
> -
> -/**
> - * xe_guc_pc_unset_gucrc_mode - unset GUCRC mode override
> - * @pc: Xe_GuC_PC instance
> - *
> - * Return: 0 on success, negative error code on error
> - */
> -int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc)
> -{
> -	guard(xe_pm_runtime)(pc_to_xe(pc));
> -	return pc_action_unset_param(pc, SLPC_PARAM_PWRGATE_RC_MODE);
> -}
> -
>  static void pc_init_pcode_freq(struct xe_guc_pc *pc)
>  {
>  	u32 min = DIV_ROUND_CLOSEST(pc->rpn_freq, GT_FREQUENCY_MULTIPLIER);
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h b/drivers/gpu/drm/xe/xe_guc_pc.h
> index 1b95873b262e..0678a4e787b3 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.h
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.h
> @@ -9,15 +9,14 @@
>  #include <linux/types.h>
>  
>  struct xe_guc_pc;
> -enum slpc_gucrc_mode;
>  struct drm_printer;
>  
>  int xe_guc_pc_init(struct xe_guc_pc *pc);
>  int xe_guc_pc_start(struct xe_guc_pc *pc);
>  int xe_guc_pc_stop(struct xe_guc_pc *pc);
> -int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode);
> -int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc);
>  void xe_guc_pc_print(struct xe_guc_pc *pc, struct drm_printer *p);
> +int xe_guc_pc_action_set_param(struct xe_guc_pc *pc, u8 id, u32 value);
> +int xe_guc_pc_action_unset_param(struct xe_guc_pc *pc, u8 id);
>  
>  u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc);
>  int xe_guc_pc_get_cur_freq(struct xe_guc_pc *pc, u32 *freq);
> diff --git a/drivers/gpu/drm/xe/xe_guc_rc.c b/drivers/gpu/drm/xe/xe_guc_rc.c
> index 55eeee7b1011..a20b20e3dab3 100644
> --- a/drivers/gpu/drm/xe/xe_guc_rc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_rc.c
> @@ -13,6 +13,7 @@
>  #include "xe_gt_printk.h"
>  #include "xe_guc.h"
>  #include "xe_guc_ct.h"
> +#include "xe_guc_pc.h"
>  #include "xe_guc_rc.h"
>  #include "xe_pm.h"
>  
> @@ -127,3 +128,32 @@ int xe_guc_rc_enable(struct xe_guc *guc)
>  
>  	return guc_action_setup_gucrc(guc, GUCRC_FIRMWARE_CONTROL);
>  }
> +
> +/**
> + * xe_guc_rc_set_mode() - set GUCRC mode

nit:
	... - Set new GuC RC mode.

> + * @guc: Xe GuC instance
> + * @mode: new value of the mode.
> + *
> + * Function to set GuC RC mode to one of the enum values.
> + *
> + * Returns: 0 on success, negative error code on error
> + */
> +int xe_guc_rc_set_mode(struct xe_guc *guc, enum slpc_gucrc_mode mode)

nit: maybe instead of exposing enum from the GuC ABI just provide explicitly named helper(s)?

	int xe_guc_rc_set_no_rc6_mode(guc);
	int xe_guc_rc_set_static_mode(guc);
	int xe_guc_rc_set_dynamic_mode(guc);


> +{
> +	guard(xe_pm_runtime_noresume)(guc_to_xe(guc));
> +	return xe_guc_pc_action_set_param(&guc->pc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
> +}
> +
> +/**
> + * xe_guc_rc_unset_mode() - revert to default mode
> + * @guc: Xe GuC instance
> + *
> + * Function to revert GuC RC mode to platform defaults.
> + *
> + * Returns: 0 on success, negative error code on error
> + */
> +int xe_guc_rc_unset_mode(struct xe_guc *guc)
> +{
> +	guard(xe_pm_runtime_noresume)(guc_to_xe(guc));
> +	return xe_guc_pc_action_unset_param(&guc->pc, SLPC_PARAM_PWRGATE_RC_MODE);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_guc_rc.h b/drivers/gpu/drm/xe/xe_guc_rc.h
> index 35fabb82cb0e..36d41329dd0a 100644
> --- a/drivers/gpu/drm/xe/xe_guc_rc.h
> +++ b/drivers/gpu/drm/xe/xe_guc_rc.h
> @@ -7,9 +7,12 @@
>  #define _XE_GUC_RC_H_
>  
>  struct xe_guc;
> +enum slpc_gucrc_mode;
>  
>  int xe_guc_rc_init(struct xe_guc *guc);
>  void xe_guc_rc_disable(struct xe_guc *guc);
>  int xe_guc_rc_enable(struct xe_guc *guc);
> +int xe_guc_rc_set_mode(struct xe_guc *guc, enum slpc_gucrc_mode mode);
> +int xe_guc_rc_unset_mode(struct xe_guc *guc);
>  
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
> index abf87fe0b345..f7752719b74f 100644
> --- a/drivers/gpu/drm/xe/xe_oa.c
> +++ b/drivers/gpu/drm/xe/xe_oa.c
> @@ -29,7 +29,7 @@
>  #include "xe_gt.h"
>  #include "xe_gt_mcr.h"
>  #include "xe_gt_printk.h"
> -#include "xe_guc_pc.h"
> +#include "xe_guc_rc.h"
>  #include "xe_macros.h"
>  #include "xe_mmio.h"
>  #include "xe_oa.h"
> @@ -875,7 +875,7 @@ static void xe_oa_stream_destroy(struct xe_oa_stream *stream)
>  
>  	/* Wa_1509372804:pvc: Unset the override of GUCRC mode to enable rc6 */
>  	if (stream->override_gucrc)
> -		xe_gt_WARN_ON(gt, xe_guc_pc_unset_gucrc_mode(&gt->uc.guc.pc));
> +		xe_gt_WARN_ON(gt, xe_guc_rc_unset_mode(&gt->uc.guc));
>  
>  	xe_oa_free_configs(stream);
>  	xe_file_put(stream->xef);
> @@ -1765,8 +1765,7 @@ static int xe_oa_stream_init(struct xe_oa_stream *stream,
>  	 * state. Prevent this by overriding GUCRC mode.
>  	 */
>  	if (XE_GT_WA(stream->gt, 1509372804)) {
> -		ret = xe_guc_pc_override_gucrc_mode(&gt->uc.guc.pc,
> -						    SLPC_GUCRC_MODE_GUCRC_NO_RC6);
> +		ret = xe_guc_rc_set_mode(&gt->uc.guc, SLPC_GUCRC_MODE_GUCRC_NO_RC6);
>  		if (ret)
>  			goto err_free_configs;
>  
> @@ -1824,7 +1823,7 @@ static int xe_oa_stream_init(struct xe_oa_stream *stream,
>  	xe_force_wake_put(gt_to_fw(gt), stream->fw_ref);
>  	xe_pm_runtime_put(stream->oa->xe);
>  	if (stream->override_gucrc)
> -		xe_gt_WARN_ON(gt, xe_guc_pc_unset_gucrc_mode(&gt->uc.guc.pc));
> +		xe_gt_WARN_ON(gt, xe_guc_rc_unset_mode(&gt->uc.guc));

nit: it looks that all callers of the unset_mode() always use only WARN,
there is true error handling, so maybe this WARN should be moved to unset_mode()

nit2: is there any solid reason why these 'unset' in OA are called _after_ RPM and FW are put?

>  err_free_configs:
>  	xe_oa_free_configs(stream);
>  exit:

just nits, so

Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

Re: [PATCH v7 2/2] drm/xe: Add a wrapper for SLPC set/unset params

[Belgaumkar, Vinay]

On 2/3/2026 8:47 AM, Michal Wajdeczko wrote:
>
> On 1/28/2026 3:23 AM, Vinay Belgaumkar wrote:
>> Also, extract out the GuC RC related set/unset param functions
>> into xe_guc_rc file. GuC still allows us to override GuC RC mode
>> using an SLPC H2G interface. Continue to use that interface, but
>> move the related code to the newly created xe_guc_rc file.
>>
>> Cc: Riana Tauro <riana.tauro@intel.com>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Reviewed-by: Riana Tauro <riana.tauro@intel.com>
>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> ---
>> v2: xe_guc_rc functions to use guc pointer instead of gt (Michal W)
>> v3: Assert if runtime pm ref is not held (Michal W)
>> v4: Review comments (Riana)
>> v5: Use noresume instead of full resume, update title (Michal)
>> ---
>>   drivers/gpu/drm/xe/xe_guc_pc.c | 56 +++++++++++++++++++---------------
>>   drivers/gpu/drm/xe/xe_guc_pc.h |  5 ++-
>>   drivers/gpu/drm/xe/xe_guc_rc.c | 30 ++++++++++++++++++
>>   drivers/gpu/drm/xe/xe_guc_rc.h |  3 ++
>>   drivers/gpu/drm/xe/xe_oa.c     |  9 +++---
>>   5 files changed, 70 insertions(+), 33 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
>> index 878eb273c3e6..21fe73ab4583 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
>> @@ -264,6 +264,37 @@ static int pc_action_unset_param(struct xe_guc_pc *pc, u8 id)
>>   	return ret;
>>   }
>>   
>> +/**
>> + * xe_guc_pc_action_set_param() - Set value of SLPC param
>> + * @pc: Xe_GuC_PC instance
>> + * @id: Param id
>> + * @value: Value to set
>> + *
>> + * This function can be used to set any SLPC param.
>> + *
>> + * Return: 0 on Success
>> + */
>> +int xe_guc_pc_action_set_param(struct xe_guc_pc *pc, u8 id, u32 value)
>> +{
>> +	xe_device_assert_mem_access(pc_to_xe(pc));
>> +	return pc_action_set_param(pc, id, value);
>> +}
>> +
>> +/**
>> + * xe_guc_pc_action_unset_param() - Revert to default value
>> + * @pc: Xe_GuC_PC instance
>> + * @id: Param id
>> + *
>> + * This function can be used revert any SLPC param to its default value.
>> + *
>> + * Return: 0 on Success
>> + */
>> +int xe_guc_pc_action_unset_param(struct xe_guc_pc *pc, u8 id)
>> +{
>> +	xe_device_assert_mem_access(pc_to_xe(pc));
>> +	return pc_action_unset_param(pc, id);
>> +}
>> +
>>   static u32 decode_freq(u32 raw)
>>   {
>>   	return DIV_ROUND_CLOSEST(raw * GT_FREQUENCY_MULTIPLIER,
>> @@ -1045,31 +1076,6 @@ int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc)
>>   	return ret;
>>   }
>>   
>> -/**
>> - * xe_guc_pc_override_gucrc_mode - override GUCRC mode
>> - * @pc: Xe_GuC_PC instance
>> - * @mode: new value of the mode.
>> - *
>> - * Return: 0 on success, negative error code on error
>> - */
>> -int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode)
>> -{
>> -	guard(xe_pm_runtime)(pc_to_xe(pc));
>> -	return pc_action_set_param(pc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
>> -}
>> -
>> -/**
>> - * xe_guc_pc_unset_gucrc_mode - unset GUCRC mode override
>> - * @pc: Xe_GuC_PC instance
>> - *
>> - * Return: 0 on success, negative error code on error
>> - */
>> -int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc)
>> -{
>> -	guard(xe_pm_runtime)(pc_to_xe(pc));
>> -	return pc_action_unset_param(pc, SLPC_PARAM_PWRGATE_RC_MODE);
>> -}
>> -
>>   static void pc_init_pcode_freq(struct xe_guc_pc *pc)
>>   {
>>   	u32 min = DIV_ROUND_CLOSEST(pc->rpn_freq, GT_FREQUENCY_MULTIPLIER);
>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h b/drivers/gpu/drm/xe/xe_guc_pc.h
>> index 1b95873b262e..0678a4e787b3 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_pc.h
>> +++ b/drivers/gpu/drm/xe/xe_guc_pc.h
>> @@ -9,15 +9,14 @@
>>   #include <linux/types.h>
>>   
>>   struct xe_guc_pc;
>> -enum slpc_gucrc_mode;
>>   struct drm_printer;
>>   
>>   int xe_guc_pc_init(struct xe_guc_pc *pc);
>>   int xe_guc_pc_start(struct xe_guc_pc *pc);
>>   int xe_guc_pc_stop(struct xe_guc_pc *pc);
>> -int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode);
>> -int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc);
>>   void xe_guc_pc_print(struct xe_guc_pc *pc, struct drm_printer *p);
>> +int xe_guc_pc_action_set_param(struct xe_guc_pc *pc, u8 id, u32 value);
>> +int xe_guc_pc_action_unset_param(struct xe_guc_pc *pc, u8 id);
>>   
>>   u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc);
>>   int xe_guc_pc_get_cur_freq(struct xe_guc_pc *pc, u32 *freq);
>> diff --git a/drivers/gpu/drm/xe/xe_guc_rc.c b/drivers/gpu/drm/xe/xe_guc_rc.c
>> index 55eeee7b1011..a20b20e3dab3 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_rc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_rc.c
>> @@ -13,6 +13,7 @@
>>   #include "xe_gt_printk.h"
>>   #include "xe_guc.h"
>>   #include "xe_guc_ct.h"
>> +#include "xe_guc_pc.h"
>>   #include "xe_guc_rc.h"
>>   #include "xe_pm.h"
>>   
>> @@ -127,3 +128,32 @@ int xe_guc_rc_enable(struct xe_guc *guc)
>>   
>>   	return guc_action_setup_gucrc(guc, GUCRC_FIRMWARE_CONTROL);
>>   }
>> +
>> +/**
>> + * xe_guc_rc_set_mode() - set GUCRC mode
> nit:
> 	... - Set new GuC RC mode.
ok.
>
>> + * @guc: Xe GuC instance
>> + * @mode: new value of the mode.
>> + *
>> + * Function to set GuC RC mode to one of the enum values.
>> + *
>> + * Returns: 0 on success, negative error code on error
>> + */
>> +int xe_guc_rc_set_mode(struct xe_guc *guc, enum slpc_gucrc_mode mode)
> nit: maybe instead of exposing enum from the GuC ABI just provide explicitly named helper(s)?
>
> 	int xe_guc_rc_set_no_rc6_mode(guc);
> 	int xe_guc_rc_set_static_mode(guc);
> 	int xe_guc_rc_set_dynamic_mode(guc);
Can add this in a later patch. So far, setting this mode is only done by 
KMD, there is no debugfs/sysfs (yet) for this.
>
>
>> +{
>> +	guard(xe_pm_runtime_noresume)(guc_to_xe(guc));
>> +	return xe_guc_pc_action_set_param(&guc->pc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
>> +}
>> +
>> +/**
>> + * xe_guc_rc_unset_mode() - revert to default mode
>> + * @guc: Xe GuC instance
>> + *
>> + * Function to revert GuC RC mode to platform defaults.
>> + *
>> + * Returns: 0 on success, negative error code on error
>> + */
>> +int xe_guc_rc_unset_mode(struct xe_guc *guc)
>> +{
>> +	guard(xe_pm_runtime_noresume)(guc_to_xe(guc));
>> +	return xe_guc_pc_action_unset_param(&guc->pc, SLPC_PARAM_PWRGATE_RC_MODE);
>> +}
>> diff --git a/drivers/gpu/drm/xe/xe_guc_rc.h b/drivers/gpu/drm/xe/xe_guc_rc.h
>> index 35fabb82cb0e..36d41329dd0a 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_rc.h
>> +++ b/drivers/gpu/drm/xe/xe_guc_rc.h
>> @@ -7,9 +7,12 @@
>>   #define _XE_GUC_RC_H_
>>   
>>   struct xe_guc;
>> +enum slpc_gucrc_mode;
>>   
>>   int xe_guc_rc_init(struct xe_guc *guc);
>>   void xe_guc_rc_disable(struct xe_guc *guc);
>>   int xe_guc_rc_enable(struct xe_guc *guc);
>> +int xe_guc_rc_set_mode(struct xe_guc *guc, enum slpc_gucrc_mode mode);
>> +int xe_guc_rc_unset_mode(struct xe_guc *guc);
>>   
>>   #endif
>> diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
>> index abf87fe0b345..f7752719b74f 100644
>> --- a/drivers/gpu/drm/xe/xe_oa.c
>> +++ b/drivers/gpu/drm/xe/xe_oa.c
>> @@ -29,7 +29,7 @@
>>   #include "xe_gt.h"
>>   #include "xe_gt_mcr.h"
>>   #include "xe_gt_printk.h"
>> -#include "xe_guc_pc.h"
>> +#include "xe_guc_rc.h"
>>   #include "xe_macros.h"
>>   #include "xe_mmio.h"
>>   #include "xe_oa.h"
>> @@ -875,7 +875,7 @@ static void xe_oa_stream_destroy(struct xe_oa_stream *stream)
>>   
>>   	/* Wa_1509372804:pvc: Unset the override of GUCRC mode to enable rc6 */
>>   	if (stream->override_gucrc)
>> -		xe_gt_WARN_ON(gt, xe_guc_pc_unset_gucrc_mode(&gt->uc.guc.pc));
>> +		xe_gt_WARN_ON(gt, xe_guc_rc_unset_mode(&gt->uc.guc));
>>   
>>   	xe_oa_free_configs(stream);
>>   	xe_file_put(stream->xef);
>> @@ -1765,8 +1765,7 @@ static int xe_oa_stream_init(struct xe_oa_stream *stream,
>>   	 * state. Prevent this by overriding GUCRC mode.
>>   	 */
>>   	if (XE_GT_WA(stream->gt, 1509372804)) {
>> -		ret = xe_guc_pc_override_gucrc_mode(&gt->uc.guc.pc,
>> -						    SLPC_GUCRC_MODE_GUCRC_NO_RC6);
>> +		ret = xe_guc_rc_set_mode(&gt->uc.guc, SLPC_GUCRC_MODE_GUCRC_NO_RC6);
>>   		if (ret)
>>   			goto err_free_configs;
>>   
>> @@ -1824,7 +1823,7 @@ static int xe_oa_stream_init(struct xe_oa_stream *stream,
>>   	xe_force_wake_put(gt_to_fw(gt), stream->fw_ref);
>>   	xe_pm_runtime_put(stream->oa->xe);
>>   	if (stream->override_gucrc)
>> -		xe_gt_WARN_ON(gt, xe_guc_pc_unset_gucrc_mode(&gt->uc.guc.pc));
>> +		xe_gt_WARN_ON(gt, xe_guc_rc_unset_mode(&gt->uc.guc));
> nit: it looks that all callers of the unset_mode() always use only WARN,
> there is true error handling, so maybe this WARN should be moved to unset_mode()
Will modify this in a later patch.
>
> nit2: is there any solid reason why these 'unset' in OA are called _after_ RPM and FW are put?
We don't need fwake anyways for H2G messages, but might be a good idea 
to call unset before the runtime put. Will address this separately.
>
>>   err_free_configs:
>>   	xe_oa_free_configs(stream);
>>   exit:
> just nits, so
>
> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

Thanks,

Vinay.

>

✗ CI.checkpatch: warning for drm/xe: Separate out GuC RC code (rev4)

[Patchwork]

== Series Details ==

Series: drm/xe: Separate out GuC RC code (rev4)
URL   : https://patchwork.freedesktop.org/series/158581/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit b94772cfa19cd624515a2f9fe54ad7eafcf7326f
Author: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Date:   Tue Jan 27 18:23:20 2026 -0800

    drm/xe: Add a wrapper for SLPC set/unset params
    
    Also, extract out the GuC RC related set/unset param functions
    into xe_guc_rc file. GuC still allows us to override GuC RC mode
    using an SLPC H2G interface. Continue to use that interface, but
    move the related code to the newly created xe_guc_rc file.
    
    Cc: Riana Tauro <riana.tauro@intel.com>
    Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
    Reviewed-by: Riana Tauro <riana.tauro@intel.com>
    Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
+ /mt/dim checkpatch ba05f22d6945596fac691e952c98f566696c24ad drm-intel
291234639769 drm/xe: Decouple GuC RC code from xe_guc_pc
-:221: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#221: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 346 lines checked
b94772cfa19c drm/xe: Add a wrapper for SLPC set/unset params

✓ CI.KUnit: success for drm/xe: Separate out GuC RC code (rev4)

[Patchwork]

== Series Details ==

Series: drm/xe: Separate out GuC RC code (rev4)
URL   : https://patchwork.freedesktop.org/series/158581/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[02:32:10] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[02:32:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[02:32:46] Starting KUnit Kernel (1/1)...
[02:32:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[02:32:46] ================== guc_buf (11 subtests) ===================
[02:32:46] [PASSED] test_smallest
[02:32:46] [PASSED] test_largest
[02:32:46] [PASSED] test_granular
[02:32:46] [PASSED] test_unique
[02:32:46] [PASSED] test_overlap
[02:32:46] [PASSED] test_reusable
[02:32:46] [PASSED] test_too_big
[02:32:46] [PASSED] test_flush
[02:32:46] [PASSED] test_lookup
[02:32:46] [PASSED] test_data
[02:32:46] [PASSED] test_class
[02:32:46] ===================== [PASSED] guc_buf =====================
[02:32:46] =================== guc_dbm (7 subtests) ===================
[02:32:46] [PASSED] test_empty
[02:32:46] [PASSED] test_default
[02:32:46] ======================== test_size  ========================
[02:32:46] [PASSED] 4
[02:32:46] [PASSED] 8
[02:32:46] [PASSED] 32
[02:32:46] [PASSED] 256
[02:32:46] ==================== [PASSED] test_size ====================
[02:32:46] ======================= test_reuse  ========================
[02:32:46] [PASSED] 4
[02:32:46] [PASSED] 8
[02:32:46] [PASSED] 32
[02:32:46] [PASSED] 256
[02:32:46] =================== [PASSED] test_reuse ====================
[02:32:46] =================== test_range_overlap  ====================
[02:32:46] [PASSED] 4
[02:32:46] [PASSED] 8
[02:32:46] [PASSED] 32
[02:32:46] [PASSED] 256
[02:32:46] =============== [PASSED] test_range_overlap ================
[02:32:46] =================== test_range_compact  ====================
[02:32:46] [PASSED] 4
[02:32:46] [PASSED] 8
[02:32:46] [PASSED] 32
[02:32:46] [PASSED] 256
[02:32:46] =============== [PASSED] test_range_compact ================
[02:32:46] ==================== test_range_spare  =====================
[02:32:46] [PASSED] 4
[02:32:46] [PASSED] 8
[02:32:46] [PASSED] 32
[02:32:46] [PASSED] 256
[02:32:46] ================ [PASSED] test_range_spare =================
[02:32:46] ===================== [PASSED] guc_dbm =====================
[02:32:46] =================== guc_idm (6 subtests) ===================
[02:32:46] [PASSED] bad_init
[02:32:46] [PASSED] no_init
[02:32:46] [PASSED] init_fini
[02:32:46] [PASSED] check_used
[02:32:46] [PASSED] check_quota
[02:32:46] [PASSED] check_all
[02:32:46] ===================== [PASSED] guc_idm =====================
[02:32:46] ================== no_relay (3 subtests) ===================
[02:32:46] [PASSED] xe_drops_guc2pf_if_not_ready
[02:32:46] [PASSED] xe_drops_guc2vf_if_not_ready
[02:32:46] [PASSED] xe_rejects_send_if_not_ready
[02:32:46] ==================== [PASSED] no_relay =====================
[02:32:46] ================== pf_relay (14 subtests) ==================
[02:32:46] [PASSED] pf_rejects_guc2pf_too_short
[02:32:46] [PASSED] pf_rejects_guc2pf_too_long
[02:32:46] [PASSED] pf_rejects_guc2pf_no_payload
[02:32:46] [PASSED] pf_fails_no_payload
[02:32:46] [PASSED] pf_fails_bad_origin
[02:32:46] [PASSED] pf_fails_bad_type
[02:32:46] [PASSED] pf_txn_reports_error
[02:32:46] [PASSED] pf_txn_sends_pf2guc
[02:32:46] [PASSED] pf_sends_pf2guc
[02:32:46] [SKIPPED] pf_loopback_nop
[02:32:46] [SKIPPED] pf_loopback_echo
[02:32:46] [SKIPPED] pf_loopback_fail
[02:32:46] [SKIPPED] pf_loopback_busy
[02:32:46] [SKIPPED] pf_loopback_retry
[02:32:46] ==================== [PASSED] pf_relay =====================
[02:32:46] ================== vf_relay (3 subtests) ===================
[02:32:46] [PASSED] vf_rejects_guc2vf_too_short
[02:32:46] [PASSED] vf_rejects_guc2vf_too_long
[02:32:46] [PASSED] vf_rejects_guc2vf_no_payload
[02:32:46] ==================== [PASSED] vf_relay =====================
[02:32:46] ================ pf_gt_config (6 subtests) =================
[02:32:46] [PASSED] fair_contexts_1vf
[02:32:46] [PASSED] fair_doorbells_1vf
[02:32:46] [PASSED] fair_ggtt_1vf
[02:32:46] ====================== fair_contexts  ======================
[02:32:46] [PASSED] 1 VF
[02:32:46] [PASSED] 2 VFs
[02:32:46] [PASSED] 3 VFs
[02:32:46] [PASSED] 4 VFs
[02:32:46] [PASSED] 5 VFs
[02:32:46] [PASSED] 6 VFs
[02:32:46] [PASSED] 7 VFs
[02:32:46] [PASSED] 8 VFs
[02:32:46] [PASSED] 9 VFs
[02:32:46] [PASSED] 10 VFs
[02:32:46] [PASSED] 11 VFs
[02:32:46] [PASSED] 12 VFs
[02:32:46] [PASSED] 13 VFs
[02:32:46] [PASSED] 14 VFs
[02:32:46] [PASSED] 15 VFs
[02:32:46] [PASSED] 16 VFs
[02:32:46] [PASSED] 17 VFs
[02:32:46] [PASSED] 18 VFs
[02:32:46] [PASSED] 19 VFs
[02:32:46] [PASSED] 20 VFs
[02:32:46] [PASSED] 21 VFs
[02:32:46] [PASSED] 22 VFs
[02:32:46] [PASSED] 23 VFs
[02:32:46] [PASSED] 24 VFs
[02:32:46] [PASSED] 25 VFs
[02:32:46] [PASSED] 26 VFs
[02:32:46] [PASSED] 27 VFs
[02:32:46] [PASSED] 28 VFs
[02:32:46] [PASSED] 29 VFs
[02:32:46] [PASSED] 30 VFs
[02:32:46] [PASSED] 31 VFs
[02:32:46] [PASSED] 32 VFs
[02:32:46] [PASSED] 33 VFs
[02:32:46] [PASSED] 34 VFs
[02:32:46] [PASSED] 35 VFs
[02:32:46] [PASSED] 36 VFs
[02:32:46] [PASSED] 37 VFs
[02:32:46] [PASSED] 38 VFs
[02:32:46] [PASSED] 39 VFs
[02:32:46] [PASSED] 40 VFs
[02:32:46] [PASSED] 41 VFs
[02:32:46] [PASSED] 42 VFs
[02:32:46] [PASSED] 43 VFs
[02:32:46] [PASSED] 44 VFs
[02:32:46] [PASSED] 45 VFs
[02:32:46] [PASSED] 46 VFs
[02:32:46] [PASSED] 47 VFs
[02:32:46] [PASSED] 48 VFs
[02:32:46] [PASSED] 49 VFs
[02:32:46] [PASSED] 50 VFs
[02:32:46] [PASSED] 51 VFs
[02:32:46] [PASSED] 52 VFs
[02:32:46] [PASSED] 53 VFs
[02:32:46] [PASSED] 54 VFs
[02:32:46] [PASSED] 55 VFs
[02:32:46] [PASSED] 56 VFs
[02:32:46] [PASSED] 57 VFs
[02:32:46] [PASSED] 58 VFs
[02:32:46] [PASSED] 59 VFs
[02:32:46] [PASSED] 60 VFs
[02:32:46] [PASSED] 61 VFs
[02:32:46] [PASSED] 62 VFs
[02:32:46] [PASSED] 63 VFs
[02:32:46] ================== [PASSED] fair_contexts ==================
[02:32:46] ===================== fair_doorbells  ======================
[02:32:46] [PASSED] 1 VF
[02:32:46] [PASSED] 2 VFs
[02:32:46] [PASSED] 3 VFs
[02:32:46] [PASSED] 4 VFs
[02:32:46] [PASSED] 5 VFs
[02:32:46] [PASSED] 6 VFs
[02:32:46] [PASSED] 7 VFs
[02:32:46] [PASSED] 8 VFs
[02:32:46] [PASSED] 9 VFs
[02:32:46] [PASSED] 10 VFs
[02:32:46] [PASSED] 11 VFs
[02:32:46] [PASSED] 12 VFs
[02:32:47] [PASSED] 13 VFs
[02:32:47] [PASSED] 14 VFs
[02:32:47] [PASSED] 15 VFs
[02:32:47] [PASSED] 16 VFs
[02:32:47] [PASSED] 17 VFs
[02:32:47] [PASSED] 18 VFs
[02:32:47] [PASSED] 19 VFs
[02:32:47] [PASSED] 20 VFs
[02:32:47] [PASSED] 21 VFs
[02:32:47] [PASSED] 22 VFs
[02:32:47] [PASSED] 23 VFs
[02:32:47] [PASSED] 24 VFs
[02:32:47] [PASSED] 25 VFs
[02:32:47] [PASSED] 26 VFs
[02:32:47] [PASSED] 27 VFs
[02:32:47] [PASSED] 28 VFs
[02:32:47] [PASSED] 29 VFs
[02:32:47] [PASSED] 30 VFs
[02:32:47] [PASSED] 31 VFs
[02:32:47] [PASSED] 32 VFs
[02:32:47] [PASSED] 33 VFs
[02:32:47] [PASSED] 34 VFs
[02:32:47] [PASSED] 35 VFs
[02:32:47] [PASSED] 36 VFs
[02:32:47] [PASSED] 37 VFs
[02:32:47] [PASSED] 38 VFs
[02:32:47] [PASSED] 39 VFs
[02:32:47] [PASSED] 40 VFs
[02:32:47] [PASSED] 41 VFs
[02:32:47] [PASSED] 42 VFs
[02:32:47] [PASSED] 43 VFs
[02:32:47] [PASSED] 44 VFs
[02:32:47] [PASSED] 45 VFs
[02:32:47] [PASSED] 46 VFs
[02:32:47] [PASSED] 47 VFs
[02:32:47] [PASSED] 48 VFs
[02:32:47] [PASSED] 49 VFs
[02:32:47] [PASSED] 50 VFs
[02:32:47] [PASSED] 51 VFs
[02:32:47] [PASSED] 52 VFs
[02:32:47] [PASSED] 53 VFs
[02:32:47] [PASSED] 54 VFs
[02:32:47] [PASSED] 55 VFs
[02:32:47] [PASSED] 56 VFs
[02:32:47] [PASSED] 57 VFs
[02:32:47] [PASSED] 58 VFs
[02:32:47] [PASSED] 59 VFs
[02:32:47] [PASSED] 60 VFs
[02:32:47] [PASSED] 61 VFs
[02:32:47] [PASSED] 62 VFs
[02:32:47] [PASSED] 63 VFs
[02:32:47] ================= [PASSED] fair_doorbells ==================
[02:32:47] ======================== fair_ggtt  ========================
[02:32:47] [PASSED] 1 VF
[02:32:47] [PASSED] 2 VFs
[02:32:47] [PASSED] 3 VFs
[02:32:47] [PASSED] 4 VFs
[02:32:47] [PASSED] 5 VFs
[02:32:47] [PASSED] 6 VFs
[02:32:47] [PASSED] 7 VFs
[02:32:47] [PASSED] 8 VFs
[02:32:47] [PASSED] 9 VFs
[02:32:47] [PASSED] 10 VFs
[02:32:47] [PASSED] 11 VFs
[02:32:47] [PASSED] 12 VFs
[02:32:47] [PASSED] 13 VFs
[02:32:47] [PASSED] 14 VFs
[02:32:47] [PASSED] 15 VFs
[02:32:47] [PASSED] 16 VFs
[02:32:47] [PASSED] 17 VFs
[02:32:47] [PASSED] 18 VFs
[02:32:47] [PASSED] 19 VFs
[02:32:47] [PASSED] 20 VFs
[02:32:47] [PASSED] 21 VFs
[02:32:47] [PASSED] 22 VFs
[02:32:47] [PASSED] 23 VFs
[02:32:47] [PASSED] 24 VFs
[02:32:47] [PASSED] 25 VFs
[02:32:47] [PASSED] 26 VFs
[02:32:47] [PASSED] 27 VFs
[02:32:47] [PASSED] 28 VFs
[02:32:47] [PASSED] 29 VFs
[02:32:47] [PASSED] 30 VFs
[02:32:47] [PASSED] 31 VFs
[02:32:47] [PASSED] 32 VFs
[02:32:47] [PASSED] 33 VFs
[02:32:47] [PASSED] 34 VFs
[02:32:47] [PASSED] 35 VFs
[02:32:47] [PASSED] 36 VFs
[02:32:47] [PASSED] 37 VFs
[02:32:47] [PASSED] 38 VFs
[02:32:47] [PASSED] 39 VFs
[02:32:47] [PASSED] 40 VFs
[02:32:47] [PASSED] 41 VFs
[02:32:47] [PASSED] 42 VFs
[02:32:47] [PASSED] 43 VFs
[02:32:47] [PASSED] 44 VFs
[02:32:47] [PASSED] 45 VFs
[02:32:47] [PASSED] 46 VFs
[02:32:47] [PASSED] 47 VFs
[02:32:47] [PASSED] 48 VFs
[02:32:47] [PASSED] 49 VFs
[02:32:47] [PASSED] 50 VFs
[02:32:47] [PASSED] 51 VFs
[02:32:47] [PASSED] 52 VFs
[02:32:47] [PASSED] 53 VFs
[02:32:47] [PASSED] 54 VFs
[02:32:47] [PASSED] 55 VFs
[02:32:47] [PASSED] 56 VFs
[02:32:47] [PASSED] 57 VFs
[02:32:47] [PASSED] 58 VFs
[02:32:47] [PASSED] 59 VFs
[02:32:47] [PASSED] 60 VFs
[02:32:47] [PASSED] 61 VFs
[02:32:47] [PASSED] 62 VFs
[02:32:47] [PASSED] 63 VFs
[02:32:47] ==================== [PASSED] fair_ggtt ====================
[02:32:47] ================== [PASSED] pf_gt_config ===================
[02:32:47] ===================== lmtt (1 subtest) =====================
[02:32:47] ======================== test_ops  =========================
[02:32:47] [PASSED] 2-level
[02:32:47] [PASSED] multi-level
[02:32:47] ==================== [PASSED] test_ops =====================
[02:32:47] ====================== [PASSED] lmtt =======================
[02:32:47] ================= pf_service (11 subtests) =================
[02:32:47] [PASSED] pf_negotiate_any
[02:32:47] [PASSED] pf_negotiate_base_match
[02:32:47] [PASSED] pf_negotiate_base_newer
[02:32:47] [PASSED] pf_negotiate_base_next
[02:32:47] [SKIPPED] pf_negotiate_base_older
[02:32:47] [PASSED] pf_negotiate_base_prev
[02:32:47] [PASSED] pf_negotiate_latest_match
[02:32:47] [PASSED] pf_negotiate_latest_newer
[02:32:47] [PASSED] pf_negotiate_latest_next
[02:32:47] [SKIPPED] pf_negotiate_latest_older
[02:32:47] [SKIPPED] pf_negotiate_latest_prev
[02:32:47] =================== [PASSED] pf_service ====================
[02:32:47] ================= xe_guc_g2g (2 subtests) ==================
[02:32:47] ============== xe_live_guc_g2g_kunit_default  ==============
[02:32:47] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[02:32:47] ============== xe_live_guc_g2g_kunit_allmem  ===============
[02:32:47] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[02:32:47] =================== [SKIPPED] xe_guc_g2g ===================
[02:32:47] =================== xe_mocs (2 subtests) ===================
[02:32:47] ================ xe_live_mocs_kernel_kunit  ================
[02:32:47] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[02:32:47] ================ xe_live_mocs_reset_kunit  =================
[02:32:47] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[02:32:47] ==================== [SKIPPED] xe_mocs =====================
[02:32:47] ================= xe_migrate (2 subtests) ==================
[02:32:47] ================= xe_migrate_sanity_kunit  =================
[02:32:47] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[02:32:47] ================== xe_validate_ccs_kunit  ==================
[02:32:47] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[02:32:47] =================== [SKIPPED] xe_migrate ===================
[02:32:47] ================== xe_dma_buf (1 subtest) ==================
[02:32:47] ==================== xe_dma_buf_kunit  =====================
[02:32:47] ================ [SKIPPED] xe_dma_buf_kunit ================
[02:32:47] =================== [SKIPPED] xe_dma_buf ===================
[02:32:47] ================= xe_bo_shrink (1 subtest) =================
[02:32:47] =================== xe_bo_shrink_kunit  ====================
[02:32:47] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[02:32:47] ================== [SKIPPED] xe_bo_shrink ==================
[02:32:47] ==================== xe_bo (2 subtests) ====================
[02:32:47] ================== xe_ccs_migrate_kunit  ===================
[02:32:47] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[02:32:47] ==================== xe_bo_evict_kunit  ====================
[02:32:47] =============== [SKIPPED] xe_bo_evict_kunit ================
[02:32:47] ===================== [SKIPPED] xe_bo ======================
[02:32:47] ==================== args (13 subtests) ====================
[02:32:47] [PASSED] count_args_test
[02:32:47] [PASSED] call_args_example
[02:32:47] [PASSED] call_args_test
[02:32:47] [PASSED] drop_first_arg_example
[02:32:47] [PASSED] drop_first_arg_test
[02:32:47] [PASSED] first_arg_example
[02:32:47] [PASSED] first_arg_test
[02:32:47] [PASSED] last_arg_example
[02:32:47] [PASSED] last_arg_test
[02:32:47] [PASSED] pick_arg_example
[02:32:47] [PASSED] if_args_example
[02:32:47] [PASSED] if_args_test
[02:32:47] [PASSED] sep_comma_example
[02:32:47] ====================== [PASSED] args =======================
[02:32:47] =================== xe_pci (3 subtests) ====================
[02:32:47] ==================== check_graphics_ip  ====================
[02:32:47] [PASSED] 12.00 Xe_LP
[02:32:47] [PASSED] 12.10 Xe_LP+
[02:32:47] [PASSED] 12.55 Xe_HPG
[02:32:47] [PASSED] 12.60 Xe_HPC
[02:32:47] [PASSED] 12.70 Xe_LPG
[02:32:47] [PASSED] 12.71 Xe_LPG
[02:32:47] [PASSED] 12.74 Xe_LPG+
[02:32:47] [PASSED] 20.01 Xe2_HPG
[02:32:47] [PASSED] 20.02 Xe2_HPG
[02:32:47] [PASSED] 20.04 Xe2_LPG
[02:32:47] [PASSED] 30.00 Xe3_LPG
[02:32:47] [PASSED] 30.01 Xe3_LPG
[02:32:47] [PASSED] 30.03 Xe3_LPG
[02:32:47] [PASSED] 30.04 Xe3_LPG
[02:32:47] [PASSED] 30.05 Xe3_LPG
[02:32:47] [PASSED] 35.11 Xe3p_XPC
[02:32:47] ================ [PASSED] check_graphics_ip ================
[02:32:47] ===================== check_media_ip  ======================
[02:32:47] [PASSED] 12.00 Xe_M
[02:32:47] [PASSED] 12.55 Xe_HPM
[02:32:47] [PASSED] 13.00 Xe_LPM+
[02:32:47] [PASSED] 13.01 Xe2_HPM
[02:32:47] [PASSED] 20.00 Xe2_LPM
[02:32:47] [PASSED] 30.00 Xe3_LPM
[02:32:47] [PASSED] 30.02 Xe3_LPM
[02:32:47] [PASSED] 35.00 Xe3p_LPM
[02:32:47] [PASSED] 35.03 Xe3p_HPM
[02:32:47] ================= [PASSED] check_media_ip ==================
[02:32:47] =================== check_platform_desc  ===================
[02:32:47] [PASSED] 0x9A60 (TIGERLAKE)
[02:32:47] [PASSED] 0x9A68 (TIGERLAKE)
[02:32:47] [PASSED] 0x9A70 (TIGERLAKE)
[02:32:47] [PASSED] 0x9A40 (TIGERLAKE)
[02:32:47] [PASSED] 0x9A49 (TIGERLAKE)
[02:32:47] [PASSED] 0x9A59 (TIGERLAKE)
[02:32:47] [PASSED] 0x9A78 (TIGERLAKE)
[02:32:47] [PASSED] 0x9AC0 (TIGERLAKE)
[02:32:47] [PASSED] 0x9AC9 (TIGERLAKE)
[02:32:47] [PASSED] 0x9AD9 (TIGERLAKE)
[02:32:47] [PASSED] 0x9AF8 (TIGERLAKE)
[02:32:47] [PASSED] 0x4C80 (ROCKETLAKE)
[02:32:47] [PASSED] 0x4C8A (ROCKETLAKE)
[02:32:47] [PASSED] 0x4C8B (ROCKETLAKE)
[02:32:47] [PASSED] 0x4C8C (ROCKETLAKE)
[02:32:47] [PASSED] 0x4C90 (ROCKETLAKE)
[02:32:47] [PASSED] 0x4C9A (ROCKETLAKE)
[02:32:47] [PASSED] 0x4680 (ALDERLAKE_S)
[02:32:47] [PASSED] 0x4682 (ALDERLAKE_S)
[02:32:47] [PASSED] 0x4688 (ALDERLAKE_S)
[02:32:47] [PASSED] 0x468A (ALDERLAKE_S)
[02:32:47] [PASSED] 0x468B (ALDERLAKE_S)
[02:32:47] [PASSED] 0x4690 (ALDERLAKE_S)
[02:32:47] [PASSED] 0x4692 (ALDERLAKE_S)
[02:32:47] [PASSED] 0x4693 (ALDERLAKE_S)
[02:32:47] [PASSED] 0x46A0 (ALDERLAKE_P)
[02:32:47] [PASSED] 0x46A1 (ALDERLAKE_P)
[02:32:47] [PASSED] 0x46A2 (ALDERLAKE_P)
[02:32:47] [PASSED] 0x46A3 (ALDERLAKE_P)
[02:32:47] [PASSED] 0x46A6 (ALDERLAKE_P)
[02:32:47] [PASSED] 0x46A8 (ALDERLAKE_P)
[02:32:47] [PASSED] 0x46AA (ALDERLAKE_P)
[02:32:47] [PASSED] 0x462A (ALDERLAKE_P)
[02:32:47] [PASSED] 0x4626 (ALDERLAKE_P)
[02:32:47] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[02:32:47] [PASSED] 0x46B0 (ALDERLAKE_P)
[02:32:47] [PASSED] 0x46B1 (ALDERLAKE_P)
[02:32:47] [PASSED] 0x46B2 (ALDERLAKE_P)
[02:32:47] [PASSED] 0x46B3 (ALDERLAKE_P)
[02:32:47] [PASSED] 0x46C0 (ALDERLAKE_P)
[02:32:47] [PASSED] 0x46C1 (ALDERLAKE_P)
[02:32:47] [PASSED] 0x46C2 (ALDERLAKE_P)
[02:32:47] [PASSED] 0x46C3 (ALDERLAKE_P)
[02:32:47] [PASSED] 0x46D0 (ALDERLAKE_N)
[02:32:47] [PASSED] 0x46D1 (ALDERLAKE_N)
[02:32:47] [PASSED] 0x46D2 (ALDERLAKE_N)
[02:32:47] [PASSED] 0x46D3 (ALDERLAKE_N)
[02:32:47] [PASSED] 0x46D4 (ALDERLAKE_N)
[02:32:47] [PASSED] 0xA721 (ALDERLAKE_P)
[02:32:47] [PASSED] 0xA7A1 (ALDERLAKE_P)
[02:32:47] [PASSED] 0xA7A9 (ALDERLAKE_P)
[02:32:47] [PASSED] 0xA7AC (ALDERLAKE_P)
[02:32:47] [PASSED] 0xA7AD (ALDERLAKE_P)
[02:32:47] [PASSED] 0xA720 (ALDERLAKE_P)
[02:32:47] [PASSED] 0xA7A0 (ALDERLAKE_P)
[02:32:47] [PASSED] 0xA7A8 (ALDERLAKE_P)
[02:32:47] [PASSED] 0xA7AA (ALDERLAKE_P)
[02:32:47] [PASSED] 0xA7AB (ALDERLAKE_P)
[02:32:47] [PASSED] 0xA780 (ALDERLAKE_S)
[02:32:47] [PASSED] 0xA781 (ALDERLAKE_S)
[02:32:47] [PASSED] 0xA782 (ALDERLAKE_S)
[02:32:47] [PASSED] 0xA783 (ALDERLAKE_S)
[02:32:47] [PASSED] 0xA788 (ALDERLAKE_S)
[02:32:47] [PASSED] 0xA789 (ALDERLAKE_S)
[02:32:47] [PASSED] 0xA78A (ALDERLAKE_S)
[02:32:47] [PASSED] 0xA78B (ALDERLAKE_S)
[02:32:47] [PASSED] 0x4905 (DG1)
[02:32:47] [PASSED] 0x4906 (DG1)
[02:32:47] [PASSED] 0x4907 (DG1)
[02:32:47] [PASSED] 0x4908 (DG1)
[02:32:47] [PASSED] 0x4909 (DG1)
[02:32:47] [PASSED] 0x56C0 (DG2)
[02:32:47] [PASSED] 0x56C2 (DG2)
[02:32:47] [PASSED] 0x56C1 (DG2)
[02:32:47] [PASSED] 0x7D51 (METEORLAKE)
[02:32:47] [PASSED] 0x7DD1 (METEORLAKE)
[02:32:47] [PASSED] 0x7D41 (METEORLAKE)
[02:32:47] [PASSED] 0x7D67 (METEORLAKE)
[02:32:47] [PASSED] 0xB640 (METEORLAKE)
[02:32:47] [PASSED] 0x56A0 (DG2)
[02:32:47] [PASSED] 0x56A1 (DG2)
[02:32:47] [PASSED] 0x56A2 (DG2)
[02:32:47] [PASSED] 0x56BE (DG2)
[02:32:47] [PASSED] 0x56BF (DG2)
[02:32:47] [PASSED] 0x5690 (DG2)
[02:32:47] [PASSED] 0x5691 (DG2)
[02:32:47] [PASSED] 0x5692 (DG2)
[02:32:47] [PASSED] 0x56A5 (DG2)
[02:32:47] [PASSED] 0x56A6 (DG2)
[02:32:47] [PASSED] 0x56B0 (DG2)
[02:32:47] [PASSED] 0x56B1 (DG2)
[02:32:47] [PASSED] 0x56BA (DG2)
[02:32:47] [PASSED] 0x56BB (DG2)
[02:32:47] [PASSED] 0x56BC (DG2)
[02:32:47] [PASSED] 0x56BD (DG2)
[02:32:47] [PASSED] 0x5693 (DG2)
[02:32:47] [PASSED] 0x5694 (DG2)
[02:32:47] [PASSED] 0x5695 (DG2)
[02:32:47] [PASSED] 0x56A3 (DG2)
[02:32:47] [PASSED] 0x56A4 (DG2)
[02:32:47] [PASSED] 0x56B2 (DG2)
[02:32:47] [PASSED] 0x56B3 (DG2)
[02:32:47] [PASSED] 0x5696 (DG2)
[02:32:47] [PASSED] 0x5697 (DG2)
[02:32:47] [PASSED] 0xB69 (PVC)
[02:32:47] [PASSED] 0xB6E (PVC)
[02:32:47] [PASSED] 0xBD4 (PVC)
[02:32:47] [PASSED] 0xBD5 (PVC)
[02:32:47] [PASSED] 0xBD6 (PVC)
[02:32:47] [PASSED] 0xBD7 (PVC)
[02:32:47] [PASSED] 0xBD8 (PVC)
[02:32:47] [PASSED] 0xBD9 (PVC)
[02:32:47] [PASSED] 0xBDA (PVC)
[02:32:47] [PASSED] 0xBDB (PVC)
[02:32:47] [PASSED] 0xBE0 (PVC)
[02:32:47] [PASSED] 0xBE1 (PVC)
[02:32:47] [PASSED] 0xBE5 (PVC)
[02:32:47] [PASSED] 0x7D40 (METEORLAKE)
[02:32:47] [PASSED] 0x7D45 (METEORLAKE)
[02:32:47] [PASSED] 0x7D55 (METEORLAKE)
[02:32:47] [PASSED] 0x7D60 (METEORLAKE)
[02:32:47] [PASSED] 0x7DD5 (METEORLAKE)
[02:32:47] [PASSED] 0x6420 (LUNARLAKE)
[02:32:47] [PASSED] 0x64A0 (LUNARLAKE)
[02:32:47] [PASSED] 0x64B0 (LUNARLAKE)
[02:32:47] [PASSED] 0xE202 (BATTLEMAGE)
[02:32:47] [PASSED] 0xE209 (BATTLEMAGE)
[02:32:47] [PASSED] 0xE20B (BATTLEMAGE)
[02:32:47] [PASSED] 0xE20C (BATTLEMAGE)
[02:32:47] [PASSED] 0xE20D (BATTLEMAGE)
[02:32:47] [PASSED] 0xE210 (BATTLEMAGE)
[02:32:47] [PASSED] 0xE211 (BATTLEMAGE)
[02:32:47] [PASSED] 0xE212 (BATTLEMAGE)
[02:32:47] [PASSED] 0xE216 (BATTLEMAGE)
[02:32:47] [PASSED] 0xE220 (BATTLEMAGE)
[02:32:47] [PASSED] 0xE221 (BATTLEMAGE)
[02:32:47] [PASSED] 0xE222 (BATTLEMAGE)
[02:32:47] [PASSED] 0xE223 (BATTLEMAGE)
[02:32:47] [PASSED] 0xB080 (PANTHERLAKE)
[02:32:47] [PASSED] 0xB081 (PANTHERLAKE)
[02:32:47] [PASSED] 0xB082 (PANTHERLAKE)
[02:32:47] [PASSED] 0xB083 (PANTHERLAKE)
[02:32:47] [PASSED] 0xB084 (PANTHERLAKE)
[02:32:47] [PASSED] 0xB085 (PANTHERLAKE)
[02:32:47] [PASSED] 0xB086 (PANTHERLAKE)
[02:32:47] [PASSED] 0xB087 (PANTHERLAKE)
[02:32:47] [PASSED] 0xB08F (PANTHERLAKE)
[02:32:47] [PASSED] 0xB090 (PANTHERLAKE)
[02:32:47] [PASSED] 0xB0A0 (PANTHERLAKE)
[02:32:47] [PASSED] 0xB0B0 (PANTHERLAKE)
[02:32:47] [PASSED] 0xFD80 (PANTHERLAKE)
[02:32:47] [PASSED] 0xFD81 (PANTHERLAKE)
[02:32:47] [PASSED] 0xD740 (NOVALAKE_S)
[02:32:47] [PASSED] 0xD741 (NOVALAKE_S)
[02:32:47] [PASSED] 0xD742 (NOVALAKE_S)
[02:32:47] [PASSED] 0xD743 (NOVALAKE_S)
[02:32:47] [PASSED] 0xD744 (NOVALAKE_S)
[02:32:47] [PASSED] 0xD745 (NOVALAKE_S)
[02:32:47] [PASSED] 0x674C (CRESCENTISLAND)
[02:32:47] =============== [PASSED] check_platform_desc ===============
[02:32:47] ===================== [PASSED] xe_pci ======================
[02:32:47] =================== xe_rtp (2 subtests) ====================
[02:32:47] =============== xe_rtp_process_to_sr_tests  ================
[02:32:47] [PASSED] coalesce-same-reg
[02:32:47] [PASSED] no-match-no-add
[02:32:47] [PASSED] match-or
[02:32:47] [PASSED] match-or-xfail
[02:32:47] [PASSED] no-match-no-add-multiple-rules
[02:32:47] [PASSED] two-regs-two-entries
[02:32:47] [PASSED] clr-one-set-other
[02:32:47] [PASSED] set-field
[02:32:47] [PASSED] conflict-duplicate
[02:32:47] [PASSED] conflict-not-disjoint
[02:32:47] [PASSED] conflict-reg-type
[02:32:47] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[02:32:47] ================== xe_rtp_process_tests  ===================
[02:32:47] [PASSED] active1
[02:32:47] [PASSED] active2
[02:32:47] [PASSED] active-inactive
[02:32:47] [PASSED] inactive-active
[02:32:47] [PASSED] inactive-1st_or_active-inactive
[02:32:47] [PASSED] inactive-2nd_or_active-inactive
[02:32:47] [PASSED] inactive-last_or_active-inactive
[02:32:47] [PASSED] inactive-no_or_active-inactive
[02:32:47] ============== [PASSED] xe_rtp_process_tests ===============
[02:32:47] ===================== [PASSED] xe_rtp ======================
[02:32:47] ==================== xe_wa (1 subtest) =====================
[02:32:47] ======================== xe_wa_gt  =========================
[02:32:47] [PASSED] TIGERLAKE B0
[02:32:47] [PASSED] DG1 A0
[02:32:47] [PASSED] DG1 B0
[02:32:47] [PASSED] ALDERLAKE_S A0
[02:32:47] [PASSED] ALDERLAKE_S B0
[02:32:47] [PASSED] ALDERLAKE_S C0
[02:32:47] [PASSED] ALDERLAKE_S D0
[02:32:47] [PASSED] ALDERLAKE_P A0
[02:32:47] [PASSED] ALDERLAKE_P B0
[02:32:47] [PASSED] ALDERLAKE_P C0
[02:32:47] [PASSED] ALDERLAKE_S RPLS D0
[02:32:47] [PASSED] ALDERLAKE_P RPLU E0
[02:32:47] [PASSED] DG2 G10 C0
[02:32:47] [PASSED] DG2 G11 B1
[02:32:47] [PASSED] DG2 G12 A1
[02:32:47] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[02:32:47] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[02:32:47] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[02:32:47] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[02:32:47] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[02:32:47] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[02:32:47] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[02:32:47] ==================== [PASSED] xe_wa_gt =====================
[02:32:47] ====================== [PASSED] xe_wa ======================
[02:32:47] ============================================================
[02:32:47] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[02:32:47] Elapsed time: 36.381s total, 4.216s configuring, 31.648s building, 0.469s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[02:32:47] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[02:32:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[02:33:14] Starting KUnit Kernel (1/1)...
[02:33:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[02:33:14] ============ drm_test_pick_cmdline (2 subtests) ============
[02:33:14] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[02:33:14] =============== drm_test_pick_cmdline_named  ===============
[02:33:14] [PASSED] NTSC
[02:33:14] [PASSED] NTSC-J
[02:33:14] [PASSED] PAL
[02:33:14] [PASSED] PAL-M
[02:33:14] =========== [PASSED] drm_test_pick_cmdline_named ===========
[02:33:14] ============== [PASSED] drm_test_pick_cmdline ==============
[02:33:14] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[02:33:14] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[02:33:14] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[02:33:14] =========== drm_validate_clone_mode (2 subtests) ===========
[02:33:14] ============== drm_test_check_in_clone_mode  ===============
[02:33:14] [PASSED] in_clone_mode
[02:33:14] [PASSED] not_in_clone_mode
[02:33:14] ========== [PASSED] drm_test_check_in_clone_mode ===========
[02:33:14] =============== drm_test_check_valid_clones  ===============
[02:33:14] [PASSED] not_in_clone_mode
[02:33:14] [PASSED] valid_clone
[02:33:14] [PASSED] invalid_clone
[02:33:14] =========== [PASSED] drm_test_check_valid_clones ===========
[02:33:14] ============= [PASSED] drm_validate_clone_mode =============
[02:33:14] ============= drm_validate_modeset (1 subtest) =============
[02:33:14] [PASSED] drm_test_check_connector_changed_modeset
[02:33:14] ============== [PASSED] drm_validate_modeset ===============
[02:33:14] ====== drm_test_bridge_get_current_state (2 subtests) ======
[02:33:14] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[02:33:14] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[02:33:14] ======== [PASSED] drm_test_bridge_get_current_state ========
[02:33:14] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[02:33:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[02:33:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[02:33:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[02:33:14] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[02:33:14] ============== drm_bridge_alloc (2 subtests) ===============
[02:33:14] [PASSED] drm_test_drm_bridge_alloc_basic
[02:33:14] [PASSED] drm_test_drm_bridge_alloc_get_put
[02:33:14] ================ [PASSED] drm_bridge_alloc =================
[02:33:14] ================== drm_buddy (9 subtests) ==================
[02:33:14] [PASSED] drm_test_buddy_alloc_limit
[02:33:14] [PASSED] drm_test_buddy_alloc_optimistic
[02:33:14] [PASSED] drm_test_buddy_alloc_pessimistic
[02:33:14] [PASSED] drm_test_buddy_alloc_pathological
[02:33:14] [PASSED] drm_test_buddy_alloc_contiguous
[02:33:14] [PASSED] drm_test_buddy_alloc_clear
[02:33:14] [PASSED] drm_test_buddy_alloc_range_bias
[02:33:14] [PASSED] drm_test_buddy_fragmentation_performance
[02:33:14] [PASSED] drm_test_buddy_alloc_exceeds_max_order
[02:33:14] ==================== [PASSED] drm_buddy ====================
[02:33:14] ============= drm_cmdline_parser (40 subtests) =============
[02:33:14] [PASSED] drm_test_cmdline_force_d_only
[02:33:14] [PASSED] drm_test_cmdline_force_D_only_dvi
[02:33:14] [PASSED] drm_test_cmdline_force_D_only_hdmi
[02:33:14] [PASSED] drm_test_cmdline_force_D_only_not_digital
[02:33:14] [PASSED] drm_test_cmdline_force_e_only
[02:33:14] [PASSED] drm_test_cmdline_res
[02:33:14] [PASSED] drm_test_cmdline_res_vesa
[02:33:14] [PASSED] drm_test_cmdline_res_vesa_rblank
[02:33:14] [PASSED] drm_test_cmdline_res_rblank
[02:33:14] [PASSED] drm_test_cmdline_res_bpp
[02:33:14] [PASSED] drm_test_cmdline_res_refresh
[02:33:14] [PASSED] drm_test_cmdline_res_bpp_refresh
[02:33:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[02:33:14] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[02:33:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[02:33:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[02:33:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[02:33:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[02:33:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[02:33:14] [PASSED] drm_test_cmdline_res_margins_force_on
[02:33:14] [PASSED] drm_test_cmdline_res_vesa_margins
[02:33:14] [PASSED] drm_test_cmdline_name
[02:33:14] [PASSED] drm_test_cmdline_name_bpp
[02:33:14] [PASSED] drm_test_cmdline_name_option
[02:33:14] [PASSED] drm_test_cmdline_name_bpp_option
[02:33:14] [PASSED] drm_test_cmdline_rotate_0
[02:33:14] [PASSED] drm_test_cmdline_rotate_90
[02:33:14] [PASSED] drm_test_cmdline_rotate_180
[02:33:14] [PASSED] drm_test_cmdline_rotate_270
[02:33:14] [PASSED] drm_test_cmdline_hmirror
[02:33:14] [PASSED] drm_test_cmdline_vmirror
[02:33:14] [PASSED] drm_test_cmdline_margin_options
[02:33:14] [PASSED] drm_test_cmdline_multiple_options
[02:33:14] [PASSED] drm_test_cmdline_bpp_extra_and_option
[02:33:14] [PASSED] drm_test_cmdline_extra_and_option
[02:33:14] [PASSED] drm_test_cmdline_freestanding_options
[02:33:14] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[02:33:14] [PASSED] drm_test_cmdline_panel_orientation
[02:33:14] ================ drm_test_cmdline_invalid  =================
[02:33:14] [PASSED] margin_only
[02:33:14] [PASSED] interlace_only
[02:33:14] [PASSED] res_missing_x
[02:33:14] [PASSED] res_missing_y
[02:33:14] [PASSED] res_bad_y
[02:33:14] [PASSED] res_missing_y_bpp
[02:33:14] [PASSED] res_bad_bpp
[02:33:14] [PASSED] res_bad_refresh
[02:33:14] [PASSED] res_bpp_refresh_force_on_off
[02:33:14] [PASSED] res_invalid_mode
[02:33:14] [PASSED] res_bpp_wrong_place_mode
[02:33:14] [PASSED] name_bpp_refresh
[02:33:14] [PASSED] name_refresh
[02:33:14] [PASSED] name_refresh_wrong_mode
[02:33:14] [PASSED] name_refresh_invalid_mode
[02:33:14] [PASSED] rotate_multiple
[02:33:14] [PASSED] rotate_invalid_val
[02:33:14] [PASSED] rotate_truncated
[02:33:14] [PASSED] invalid_option
[02:33:14] [PASSED] invalid_tv_option
[02:33:14] [PASSED] truncated_tv_option
[02:33:14] ============ [PASSED] drm_test_cmdline_invalid =============
[02:33:14] =============== drm_test_cmdline_tv_options  ===============
[02:33:14] [PASSED] NTSC
[02:33:14] [PASSED] NTSC_443
[02:33:14] [PASSED] NTSC_J
[02:33:14] [PASSED] PAL
[02:33:14] [PASSED] PAL_M
[02:33:14] [PASSED] PAL_N
[02:33:14] [PASSED] SECAM
[02:33:14] [PASSED] MONO_525
[02:33:14] [PASSED] MONO_625
[02:33:14] =========== [PASSED] drm_test_cmdline_tv_options ===========
[02:33:14] =============== [PASSED] drm_cmdline_parser ================
[02:33:14] ========== drmm_connector_hdmi_init (20 subtests) ==========
[02:33:14] [PASSED] drm_test_connector_hdmi_init_valid
[02:33:14] [PASSED] drm_test_connector_hdmi_init_bpc_8
[02:33:14] [PASSED] drm_test_connector_hdmi_init_bpc_10
[02:33:14] [PASSED] drm_test_connector_hdmi_init_bpc_12
[02:33:14] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[02:33:14] [PASSED] drm_test_connector_hdmi_init_bpc_null
[02:33:14] [PASSED] drm_test_connector_hdmi_init_formats_empty
[02:33:14] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[02:33:14] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[02:33:14] [PASSED] supported_formats=0x9 yuv420_allowed=1
[02:33:14] [PASSED] supported_formats=0x9 yuv420_allowed=0
[02:33:14] [PASSED] supported_formats=0x3 yuv420_allowed=1
[02:33:14] [PASSED] supported_formats=0x3 yuv420_allowed=0
[02:33:14] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[02:33:14] [PASSED] drm_test_connector_hdmi_init_null_ddc
[02:33:14] [PASSED] drm_test_connector_hdmi_init_null_product
[02:33:14] [PASSED] drm_test_connector_hdmi_init_null_vendor
[02:33:14] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[02:33:14] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[02:33:14] [PASSED] drm_test_connector_hdmi_init_product_valid
[02:33:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[02:33:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[02:33:14] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[02:33:14] ========= drm_test_connector_hdmi_init_type_valid  =========
[02:33:14] [PASSED] HDMI-A
[02:33:14] [PASSED] HDMI-B
[02:33:14] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[02:33:14] ======== drm_test_connector_hdmi_init_type_invalid  ========
[02:33:14] [PASSED] Unknown
[02:33:14] [PASSED] VGA
[02:33:14] [PASSED] DVI-I
[02:33:14] [PASSED] DVI-D
[02:33:14] [PASSED] DVI-A
[02:33:14] [PASSED] Composite
[02:33:14] [PASSED] SVIDEO
[02:33:14] [PASSED] LVDS
[02:33:14] [PASSED] Component
[02:33:14] [PASSED] DIN
[02:33:14] [PASSED] DP
[02:33:14] [PASSED] TV
[02:33:14] [PASSED] eDP
[02:33:14] [PASSED] Virtual
[02:33:14] [PASSED] DSI
[02:33:14] [PASSED] DPI
[02:33:14] [PASSED] Writeback
[02:33:14] [PASSED] SPI
[02:33:14] [PASSED] USB
[02:33:14] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[02:33:14] ============ [PASSED] drmm_connector_hdmi_init =============
[02:33:14] ============= drmm_connector_init (3 subtests) =============
[02:33:14] [PASSED] drm_test_drmm_connector_init
[02:33:14] [PASSED] drm_test_drmm_connector_init_null_ddc
[02:33:14] ========= drm_test_drmm_connector_init_type_valid  =========
[02:33:14] [PASSED] Unknown
[02:33:14] [PASSED] VGA
[02:33:14] [PASSED] DVI-I
[02:33:14] [PASSED] DVI-D
[02:33:14] [PASSED] DVI-A
[02:33:14] [PASSED] Composite
[02:33:14] [PASSED] SVIDEO
[02:33:14] [PASSED] LVDS
[02:33:14] [PASSED] Component
[02:33:14] [PASSED] DIN
[02:33:14] [PASSED] DP
[02:33:14] [PASSED] HDMI-A
[02:33:14] [PASSED] HDMI-B
[02:33:14] [PASSED] TV
[02:33:14] [PASSED] eDP
[02:33:14] [PASSED] Virtual
[02:33:14] [PASSED] DSI
[02:33:14] [PASSED] DPI
[02:33:14] [PASSED] Writeback
[02:33:14] [PASSED] SPI
[02:33:14] [PASSED] USB
[02:33:14] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[02:33:14] =============== [PASSED] drmm_connector_init ===============
[02:33:14] ========= drm_connector_dynamic_init (6 subtests) ==========
[02:33:14] [PASSED] drm_test_drm_connector_dynamic_init
[02:33:14] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[02:33:14] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[02:33:14] [PASSED] drm_test_drm_connector_dynamic_init_properties
[02:33:14] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[02:33:14] [PASSED] Unknown
[02:33:14] [PASSED] VGA
[02:33:14] [PASSED] DVI-I
[02:33:14] [PASSED] DVI-D
[02:33:14] [PASSED] DVI-A
[02:33:14] [PASSED] Composite
[02:33:14] [PASSED] SVIDEO
[02:33:14] [PASSED] LVDS
[02:33:14] [PASSED] Component
[02:33:14] [PASSED] DIN
[02:33:14] [PASSED] DP
[02:33:14] [PASSED] HDMI-A
[02:33:14] [PASSED] HDMI-B
[02:33:14] [PASSED] TV
[02:33:14] [PASSED] eDP
[02:33:14] [PASSED] Virtual
[02:33:14] [PASSED] DSI
[02:33:14] [PASSED] DPI
[02:33:14] [PASSED] Writeback
[02:33:14] [PASSED] SPI
[02:33:14] [PASSED] USB
[02:33:14] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[02:33:14] ======== drm_test_drm_connector_dynamic_init_name  =========
[02:33:14] [PASSED] Unknown
[02:33:14] [PASSED] VGA
[02:33:14] [PASSED] DVI-I
[02:33:14] [PASSED] DVI-D
[02:33:14] [PASSED] DVI-A
[02:33:14] [PASSED] Composite
[02:33:14] [PASSED] SVIDEO
[02:33:14] [PASSED] LVDS
[02:33:14] [PASSED] Component
[02:33:14] [PASSED] DIN
[02:33:14] [PASSED] DP
[02:33:14] [PASSED] HDMI-A
[02:33:14] [PASSED] HDMI-B
[02:33:14] [PASSED] TV
[02:33:14] [PASSED] eDP
[02:33:14] [PASSED] Virtual
[02:33:14] [PASSED] DSI
[02:33:14] [PASSED] DPI
[02:33:14] [PASSED] Writeback
[02:33:14] [PASSED] SPI
[02:33:14] [PASSED] USB
[02:33:14] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[02:33:14] =========== [PASSED] drm_connector_dynamic_init ============
[02:33:14] ==== drm_connector_dynamic_register_early (4 subtests) =====
[02:33:14] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[02:33:14] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[02:33:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[02:33:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[02:33:14] ====== [PASSED] drm_connector_dynamic_register_early =======
[02:33:14] ======= drm_connector_dynamic_register (7 subtests) ========
[02:33:14] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[02:33:14] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[02:33:14] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[02:33:14] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[02:33:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[02:33:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[02:33:14] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[02:33:14] ========= [PASSED] drm_connector_dynamic_register ==========
[02:33:14] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[02:33:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[02:33:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[02:33:14] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[02:33:14] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[02:33:14] ========== drm_test_get_tv_mode_from_name_valid  ===========
[02:33:14] [PASSED] NTSC
[02:33:14] [PASSED] NTSC-443
[02:33:14] [PASSED] NTSC-J
[02:33:14] [PASSED] PAL
[02:33:14] [PASSED] PAL-M
[02:33:14] [PASSED] PAL-N
[02:33:14] [PASSED] SECAM
[02:33:14] [PASSED] Mono
[02:33:14] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[02:33:14] [PASSED] drm_test_get_tv_mode_from_name_truncated
[02:33:14] ============ [PASSED] drm_get_tv_mode_from_name ============
[02:33:14] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[02:33:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[02:33:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[02:33:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[02:33:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[02:33:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[02:33:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[02:33:14] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[02:33:14] [PASSED] VIC 96
[02:33:14] [PASSED] VIC 97
[02:33:14] [PASSED] VIC 101
[02:33:14] [PASSED] VIC 102
[02:33:14] [PASSED] VIC 106
[02:33:14] [PASSED] VIC 107
[02:33:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[02:33:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[02:33:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[02:33:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[02:33:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[02:33:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[02:33:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[02:33:14] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[02:33:14] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[02:33:14] [PASSED] Automatic
[02:33:14] [PASSED] Full
[02:33:14] [PASSED] Limited 16:235
[02:33:14] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[02:33:14] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[02:33:14] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[02:33:14] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[02:33:14] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[02:33:14] [PASSED] RGB
[02:33:14] [PASSED] YUV 4:2:0
[02:33:14] [PASSED] YUV 4:2:2
[02:33:14] [PASSED] YUV 4:4:4
[02:33:14] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[02:33:14] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[02:33:14] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[02:33:14] ============= drm_damage_helper (21 subtests) ==============
[02:33:14] [PASSED] drm_test_damage_iter_no_damage
[02:33:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[02:33:14] [PASSED] drm_test_damage_iter_no_damage_src_moved
[02:33:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[02:33:14] [PASSED] drm_test_damage_iter_no_damage_not_visible
[02:33:14] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[02:33:14] [PASSED] drm_test_damage_iter_no_damage_no_fb
[02:33:14] [PASSED] drm_test_damage_iter_simple_damage
[02:33:14] [PASSED] drm_test_damage_iter_single_damage
[02:33:14] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[02:33:14] [PASSED] drm_test_damage_iter_single_damage_outside_src
[02:33:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[02:33:14] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[02:33:14] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[02:33:14] [PASSED] drm_test_damage_iter_single_damage_src_moved
[02:33:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[02:33:14] [PASSED] drm_test_damage_iter_damage
[02:33:14] [PASSED] drm_test_damage_iter_damage_one_intersect
[02:33:14] [PASSED] drm_test_damage_iter_damage_one_outside
[02:33:14] [PASSED] drm_test_damage_iter_damage_src_moved
[02:33:14] [PASSED] drm_test_damage_iter_damage_not_visible
[02:33:14] ================ [PASSED] drm_damage_helper ================
[02:33:14] ============== drm_dp_mst_helper (3 subtests) ==============
[02:33:14] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[02:33:14] [PASSED] Clock 154000 BPP 30 DSC disabled
[02:33:14] [PASSED] Clock 234000 BPP 30 DSC disabled
[02:33:14] [PASSED] Clock 297000 BPP 24 DSC disabled
[02:33:14] [PASSED] Clock 332880 BPP 24 DSC enabled
[02:33:14] [PASSED] Clock 324540 BPP 24 DSC enabled
[02:33:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[02:33:14] ============== drm_test_dp_mst_calc_pbn_div  ===============
[02:33:14] [PASSED] Link rate 2000000 lane count 4
[02:33:14] [PASSED] Link rate 2000000 lane count 2
[02:33:14] [PASSED] Link rate 2000000 lane count 1
[02:33:14] [PASSED] Link rate 1350000 lane count 4
[02:33:14] [PASSED] Link rate 1350000 lane count 2
[02:33:14] [PASSED] Link rate 1350000 lane count 1
[02:33:14] [PASSED] Link rate 1000000 lane count 4
[02:33:14] [PASSED] Link rate 1000000 lane count 2
[02:33:14] [PASSED] Link rate 1000000 lane count 1
[02:33:14] [PASSED] Link rate 810000 lane count 4
[02:33:14] [PASSED] Link rate 810000 lane count 2
[02:33:14] [PASSED] Link rate 810000 lane count 1
[02:33:14] [PASSED] Link rate 540000 lane count 4
[02:33:14] [PASSED] Link rate 540000 lane count 2
[02:33:14] [PASSED] Link rate 540000 lane count 1
[02:33:14] [PASSED] Link rate 270000 lane count 4
[02:33:14] [PASSED] Link rate 270000 lane count 2
[02:33:14] [PASSED] Link rate 270000 lane count 1
[02:33:14] [PASSED] Link rate 162000 lane count 4
[02:33:14] [PASSED] Link rate 162000 lane count 2
[02:33:14] [PASSED] Link rate 162000 lane count 1
[02:33:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[02:33:14] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[02:33:14] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[02:33:14] [PASSED] DP_POWER_UP_PHY with port number
[02:33:14] [PASSED] DP_POWER_DOWN_PHY with port number
[02:33:14] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[02:33:14] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[02:33:14] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[02:33:14] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[02:33:14] [PASSED] DP_QUERY_PAYLOAD with port number
[02:33:14] [PASSED] DP_QUERY_PAYLOAD with VCPI
[02:33:14] [PASSED] DP_REMOTE_DPCD_READ with port number
[02:33:14] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[02:33:14] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[02:33:14] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[02:33:14] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[02:33:14] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[02:33:14] [PASSED] DP_REMOTE_I2C_READ with port number
[02:33:14] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[02:33:14] [PASSED] DP_REMOTE_I2C_READ with transactions array
[02:33:14] [PASSED] DP_REMOTE_I2C_WRITE with port number
[02:33:14] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[02:33:14] [PASSED] DP_REMOTE_I2C_WRITE with data array
[02:33:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[02:33:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[02:33:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[02:33:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[02:33:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[02:33:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[02:33:14] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[02:33:14] ================ [PASSED] drm_dp_mst_helper ================
[02:33:14] ================== drm_exec (7 subtests) ===================
[02:33:14] [PASSED] sanitycheck
[02:33:14] [PASSED] test_lock
[02:33:14] [PASSED] test_lock_unlock
[02:33:14] [PASSED] test_duplicates
[02:33:14] [PASSED] test_prepare
[02:33:14] [PASSED] test_prepare_array
[02:33:14] [PASSED] test_multiple_loops
[02:33:14] ==================== [PASSED] drm_exec =====================
[02:33:14] =========== drm_format_helper_test (17 subtests) ===========
[02:33:14] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[02:33:14] [PASSED] single_pixel_source_buffer
[02:33:14] [PASSED] single_pixel_clip_rectangle
[02:33:14] [PASSED] well_known_colors
[02:33:14] [PASSED] destination_pitch
[02:33:14] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[02:33:14] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[02:33:14] [PASSED] single_pixel_source_buffer
[02:33:14] [PASSED] single_pixel_clip_rectangle
[02:33:14] [PASSED] well_known_colors
[02:33:14] [PASSED] destination_pitch
[02:33:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[02:33:14] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[02:33:14] [PASSED] single_pixel_source_buffer
[02:33:14] [PASSED] single_pixel_clip_rectangle
[02:33:14] [PASSED] well_known_colors
[02:33:14] [PASSED] destination_pitch
[02:33:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[02:33:14] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[02:33:14] [PASSED] single_pixel_source_buffer
[02:33:14] [PASSED] single_pixel_clip_rectangle
[02:33:14] [PASSED] well_known_colors
[02:33:14] [PASSED] destination_pitch
[02:33:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[02:33:14] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[02:33:14] [PASSED] single_pixel_source_buffer
[02:33:14] [PASSED] single_pixel_clip_rectangle
[02:33:14] [PASSED] well_known_colors
[02:33:14] [PASSED] destination_pitch
[02:33:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[02:33:14] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[02:33:14] [PASSED] single_pixel_source_buffer
[02:33:14] [PASSED] single_pixel_clip_rectangle
[02:33:14] [PASSED] well_known_colors
[02:33:14] [PASSED] destination_pitch
[02:33:14] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[02:33:14] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[02:33:14] [PASSED] single_pixel_source_buffer
[02:33:14] [PASSED] single_pixel_clip_rectangle
[02:33:14] [PASSED] well_known_colors
[02:33:14] [PASSED] destination_pitch
[02:33:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[02:33:14] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[02:33:14] [PASSED] single_pixel_source_buffer
[02:33:14] [PASSED] single_pixel_clip_rectangle
[02:33:14] [PASSED] well_known_colors
[02:33:14] [PASSED] destination_pitch
[02:33:14] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[02:33:14] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[02:33:14] [PASSED] single_pixel_source_buffer
[02:33:14] [PASSED] single_pixel_clip_rectangle
[02:33:14] [PASSED] well_known_colors
[02:33:14] [PASSED] destination_pitch
[02:33:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[02:33:14] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[02:33:14] [PASSED] single_pixel_source_buffer
[02:33:14] [PASSED] single_pixel_clip_rectangle
[02:33:14] [PASSED] well_known_colors
[02:33:14] [PASSED] destination_pitch
[02:33:14] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[02:33:14] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[02:33:14] [PASSED] single_pixel_source_buffer
[02:33:14] [PASSED] single_pixel_clip_rectangle
[02:33:14] [PASSED] well_known_colors
[02:33:14] [PASSED] destination_pitch
[02:33:14] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[02:33:14] ============== drm_test_fb_xrgb8888_to_mono  ===============
[02:33:14] [PASSED] single_pixel_source_buffer
[02:33:14] [PASSED] single_pixel_clip_rectangle
[02:33:14] [PASSED] well_known_colors
[02:33:14] [PASSED] destination_pitch
[02:33:14] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[02:33:14] ==================== drm_test_fb_swab  =====================
[02:33:14] [PASSED] single_pixel_source_buffer
[02:33:14] [PASSED] single_pixel_clip_rectangle
[02:33:14] [PASSED] well_known_colors
[02:33:14] [PASSED] destination_pitch
[02:33:14] ================ [PASSED] drm_test_fb_swab =================
[02:33:14] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[02:33:14] [PASSED] single_pixel_source_buffer
[02:33:14] [PASSED] single_pixel_clip_rectangle
[02:33:14] [PASSED] well_known_colors
[02:33:14] [PASSED] destination_pitch
[02:33:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[02:33:14] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[02:33:14] [PASSED] single_pixel_source_buffer
[02:33:14] [PASSED] single_pixel_clip_rectangle
[02:33:14] [PASSED] well_known_colors
[02:33:14] [PASSED] destination_pitch
[02:33:14] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[02:33:14] ================= drm_test_fb_clip_offset  =================
[02:33:14] [PASSED] pass through
[02:33:14] [PASSED] horizontal offset
[02:33:14] [PASSED] vertical offset
[02:33:14] [PASSED] horizontal and vertical offset
[02:33:14] [PASSED] horizontal offset (custom pitch)
[02:33:14] [PASSED] vertical offset (custom pitch)
[02:33:14] [PASSED] horizontal and vertical offset (custom pitch)
[02:33:14] ============= [PASSED] drm_test_fb_clip_offset =============
[02:33:14] =================== drm_test_fb_memcpy  ====================
[02:33:14] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[02:33:14] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[02:33:14] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[02:33:14] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[02:33:14] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[02:33:14] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[02:33:14] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[02:33:14] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[02:33:14] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[02:33:14] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[02:33:14] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[02:33:14] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[02:33:14] =============== [PASSED] drm_test_fb_memcpy ================
[02:33:14] ============= [PASSED] drm_format_helper_test ==============
[02:33:14] ================= drm_format (18 subtests) =================
[02:33:14] [PASSED] drm_test_format_block_width_invalid
[02:33:14] [PASSED] drm_test_format_block_width_one_plane
[02:33:14] [PASSED] drm_test_format_block_width_two_plane
[02:33:14] [PASSED] drm_test_format_block_width_three_plane
[02:33:14] [PASSED] drm_test_format_block_width_tiled
[02:33:14] [PASSED] drm_test_format_block_height_invalid
[02:33:14] [PASSED] drm_test_format_block_height_one_plane
[02:33:14] [PASSED] drm_test_format_block_height_two_plane
[02:33:14] [PASSED] drm_test_format_block_height_three_plane
[02:33:14] [PASSED] drm_test_format_block_height_tiled
[02:33:14] [PASSED] drm_test_format_min_pitch_invalid
[02:33:14] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[02:33:14] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[02:33:14] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[02:33:14] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[02:33:14] [PASSED] drm_test_format_min_pitch_two_plane
[02:33:14] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[02:33:14] [PASSED] drm_test_format_min_pitch_tiled
[02:33:14] =================== [PASSED] drm_format ====================
[02:33:14] ============== drm_framebuffer (10 subtests) ===============
[02:33:14] ========== drm_test_framebuffer_check_src_coords  ==========
[02:33:14] [PASSED] Success: source fits into fb
[02:33:14] [PASSED] Fail: overflowing fb with x-axis coordinate
[02:33:14] [PASSED] Fail: overflowing fb with y-axis coordinate
[02:33:14] [PASSED] Fail: overflowing fb with source width
[02:33:14] [PASSED] Fail: overflowing fb with source height
[02:33:14] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[02:33:14] [PASSED] drm_test_framebuffer_cleanup
[02:33:14] =============== drm_test_framebuffer_create  ===============
[02:33:14] [PASSED] ABGR8888 normal sizes
[02:33:14] [PASSED] ABGR8888 max sizes
[02:33:14] [PASSED] ABGR8888 pitch greater than min required
[02:33:14] [PASSED] ABGR8888 pitch less than min required
[02:33:14] [PASSED] ABGR8888 Invalid width
[02:33:14] [PASSED] ABGR8888 Invalid buffer handle
[02:33:14] [PASSED] No pixel format
[02:33:14] [PASSED] ABGR8888 Width 0
[02:33:14] [PASSED] ABGR8888 Height 0
[02:33:14] [PASSED] ABGR8888 Out of bound height * pitch combination
[02:33:14] [PASSED] ABGR8888 Large buffer offset
[02:33:14] [PASSED] ABGR8888 Buffer offset for inexistent plane
[02:33:14] [PASSED] ABGR8888 Invalid flag
[02:33:14] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[02:33:14] [PASSED] ABGR8888 Valid buffer modifier
[02:33:14] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[02:33:14] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[02:33:14] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[02:33:14] [PASSED] NV12 Normal sizes
[02:33:14] [PASSED] NV12 Max sizes
[02:33:14] [PASSED] NV12 Invalid pitch
[02:33:14] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[02:33:14] [PASSED] NV12 different  modifier per-plane
[02:33:14] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[02:33:14] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[02:33:14] [PASSED] NV12 Modifier for inexistent plane
[02:33:14] [PASSED] NV12 Handle for inexistent plane
[02:33:14] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[02:33:14] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[02:33:14] [PASSED] YVU420 Normal sizes
[02:33:14] [PASSED] YVU420 Max sizes
[02:33:14] [PASSED] YVU420 Invalid pitch
[02:33:14] [PASSED] YVU420 Different pitches
[02:33:14] [PASSED] YVU420 Different buffer offsets/pitches
[02:33:14] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[02:33:14] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[02:33:14] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[02:33:14] [PASSED] YVU420 Valid modifier
[02:33:14] [PASSED] YVU420 Different modifiers per plane
[02:33:14] [PASSED] YVU420 Modifier for inexistent plane
[02:33:14] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[02:33:14] [PASSED] X0L2 Normal sizes
[02:33:14] [PASSED] X0L2 Max sizes
[02:33:14] [PASSED] X0L2 Invalid pitch
[02:33:14] [PASSED] X0L2 Pitch greater than minimum required
[02:33:14] [PASSED] X0L2 Handle for inexistent plane
[02:33:14] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[02:33:14] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[02:33:14] [PASSED] X0L2 Valid modifier
[02:33:14] [PASSED] X0L2 Modifier for inexistent plane
[02:33:14] =========== [PASSED] drm_test_framebuffer_create ===========
[02:33:14] [PASSED] drm_test_framebuffer_free
[02:33:14] [PASSED] drm_test_framebuffer_init
[02:33:14] [PASSED] drm_test_framebuffer_init_bad_format
[02:33:14] [PASSED] drm_test_framebuffer_init_dev_mismatch
[02:33:14] [PASSED] drm_test_framebuffer_lookup
[02:33:14] [PASSED] drm_test_framebuffer_lookup_inexistent
[02:33:14] [PASSED] drm_test_framebuffer_modifiers_not_supported
[02:33:14] ================= [PASSED] drm_framebuffer =================
[02:33:14] ================ drm_gem_shmem (8 subtests) ================
[02:33:14] [PASSED] drm_gem_shmem_test_obj_create
[02:33:14] [PASSED] drm_gem_shmem_test_obj_create_private
[02:33:14] [PASSED] drm_gem_shmem_test_pin_pages
[02:33:14] [PASSED] drm_gem_shmem_test_vmap
[02:33:14] [PASSED] drm_gem_shmem_test_get_sg_table
[02:33:14] [PASSED] drm_gem_shmem_test_get_pages_sgt
[02:33:14] [PASSED] drm_gem_shmem_test_madvise
[02:33:14] [PASSED] drm_gem_shmem_test_purge
[02:33:14] ================== [PASSED] drm_gem_shmem ==================
[02:33:14] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[02:33:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[02:33:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[02:33:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[02:33:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[02:33:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[02:33:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[02:33:14] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[02:33:14] [PASSED] Automatic
[02:33:14] [PASSED] Full
[02:33:14] [PASSED] Limited 16:235
[02:33:14] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[02:33:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[02:33:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[02:33:14] [PASSED] drm_test_check_disable_connector
[02:33:14] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[02:33:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[02:33:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[02:33:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[02:33:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[02:33:14] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[02:33:14] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[02:33:14] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[02:33:14] [PASSED] drm_test_check_output_bpc_dvi
[02:33:14] [PASSED] drm_test_check_output_bpc_format_vic_1
[02:33:14] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[02:33:14] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[02:33:14] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[02:33:14] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[02:33:14] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[02:33:14] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[02:33:14] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[02:33:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[02:33:14] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[02:33:14] [PASSED] drm_test_check_broadcast_rgb_value
[02:33:14] [PASSED] drm_test_check_bpc_8_value
[02:33:14] [PASSED] drm_test_check_bpc_10_value
[02:33:14] [PASSED] drm_test_check_bpc_12_value
[02:33:14] [PASSED] drm_test_check_format_value
[02:33:14] [PASSED] drm_test_check_tmds_char_value
[02:33:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[02:33:14] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[02:33:14] [PASSED] drm_test_check_mode_valid
[02:33:14] [PASSED] drm_test_check_mode_valid_reject
[02:33:14] [PASSED] drm_test_check_mode_valid_reject_rate
[02:33:14] [PASSED] drm_test_check_mode_valid_reject_max_clock
[02:33:14] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[02:33:14] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[02:33:14] [PASSED] drm_test_check_infoframes
[02:33:14] [PASSED] drm_test_check_reject_avi_infoframe
[02:33:14] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[02:33:14] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[02:33:14] [PASSED] drm_test_check_reject_audio_infoframe
[02:33:14] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[02:33:14] ================= drm_managed (2 subtests) =================
[02:33:14] [PASSED] drm_test_managed_release_action
[02:33:14] [PASSED] drm_test_managed_run_action
[02:33:14] =================== [PASSED] drm_managed ===================
[02:33:14] =================== drm_mm (6 subtests) ====================
[02:33:14] [PASSED] drm_test_mm_init
[02:33:14] [PASSED] drm_test_mm_debug
[02:33:14] [PASSED] drm_test_mm_align32
[02:33:14] [PASSED] drm_test_mm_align64
[02:33:14] [PASSED] drm_test_mm_lowest
[02:33:14] [PASSED] drm_test_mm_highest
[02:33:14] ===================== [PASSED] drm_mm ======================
[02:33:14] ============= drm_modes_analog_tv (5 subtests) =============
[02:33:14] [PASSED] drm_test_modes_analog_tv_mono_576i
[02:33:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[02:33:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[02:33:14] [PASSED] drm_test_modes_analog_tv_pal_576i
[02:33:14] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[02:33:14] =============== [PASSED] drm_modes_analog_tv ===============
[02:33:14] ============== drm_plane_helper (2 subtests) ===============
[02:33:14] =============== drm_test_check_plane_state  ================
[02:33:14] [PASSED] clipping_simple
[02:33:14] [PASSED] clipping_rotate_reflect
[02:33:14] [PASSED] positioning_simple
[02:33:14] [PASSED] upscaling
[02:33:14] [PASSED] downscaling
[02:33:14] [PASSED] rounding1
[02:33:14] [PASSED] rounding2
[02:33:14] [PASSED] rounding3
[02:33:14] [PASSED] rounding4
[02:33:14] =========== [PASSED] drm_test_check_plane_state ============
[02:33:14] =========== drm_test_check_invalid_plane_state  ============
[02:33:14] [PASSED] positioning_invalid
[02:33:14] [PASSED] upscaling_invalid
[02:33:14] [PASSED] downscaling_invalid
[02:33:14] ======= [PASSED] drm_test_check_invalid_plane_state ========
[02:33:14] ================ [PASSED] drm_plane_helper =================
[02:33:14] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[02:33:14] ====== drm_test_connector_helper_tv_get_modes_check  =======
[02:33:14] [PASSED] None
[02:33:14] [PASSED] PAL
[02:33:14] [PASSED] NTSC
[02:33:14] [PASSED] Both, NTSC Default
[02:33:14] [PASSED] Both, PAL Default
[02:33:14] [PASSED] Both, NTSC Default, with PAL on command-line
[02:33:14] [PASSED] Both, PAL Default, with NTSC on command-line
[02:33:14] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[02:33:14] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[02:33:14] ================== drm_rect (9 subtests) ===================
[02:33:14] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[02:33:14] [PASSED] drm_test_rect_clip_scaled_not_clipped
[02:33:14] [PASSED] drm_test_rect_clip_scaled_clipped
[02:33:14] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[02:33:14] ================= drm_test_rect_intersect  =================
[02:33:14] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[02:33:14] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[02:33:14] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[02:33:14] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[02:33:14] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[02:33:14] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[02:33:14] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[02:33:14] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[02:33:14] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[02:33:14] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[02:33:14] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[02:33:14] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[02:33:14] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[02:33:14] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[02:33:14] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
stty: 'standard input': Inappropriate ioctl for device
[02:33:14] ============= [PASSED] drm_test_rect_intersect =============
[02:33:14] ================ drm_test_rect_calc_hscale  ================
[02:33:14] [PASSED] normal use
[02:33:14] [PASSED] out of max range
[02:33:14] [PASSED] out of min range
[02:33:14] [PASSED] zero dst
[02:33:14] [PASSED] negative src
[02:33:14] [PASSED] negative dst
[02:33:14] ============ [PASSED] drm_test_rect_calc_hscale ============
[02:33:14] ================ drm_test_rect_calc_vscale  ================
[02:33:14] [PASSED] normal use
[02:33:14] [PASSED] out of max range
[02:33:14] [PASSED] out of min range
[02:33:14] [PASSED] zero dst
[02:33:14] [PASSED] negative src
[02:33:14] [PASSED] negative dst
[02:33:14] ============ [PASSED] drm_test_rect_calc_vscale ============
[02:33:14] ================== drm_test_rect_rotate  ===================
[02:33:14] [PASSED] reflect-x
[02:33:14] [PASSED] reflect-y
[02:33:14] [PASSED] rotate-0
[02:33:14] [PASSED] rotate-90
[02:33:14] [PASSED] rotate-180
[02:33:14] [PASSED] rotate-270
[02:33:14] ============== [PASSED] drm_test_rect_rotate ===============
[02:33:14] ================ drm_test_rect_rotate_inv  =================
[02:33:14] [PASSED] reflect-x
[02:33:14] [PASSED] reflect-y
[02:33:14] [PASSED] rotate-0
[02:33:14] [PASSED] rotate-90
[02:33:14] [PASSED] rotate-180
[02:33:14] [PASSED] rotate-270
[02:33:14] ============ [PASSED] drm_test_rect_rotate_inv =============
[02:33:14] ==================== [PASSED] drm_rect =====================
[02:33:14] ============ drm_sysfb_modeset_test (1 subtest) ============
[02:33:14] ============ drm_test_sysfb_build_fourcc_list  =============
[02:33:14] [PASSED] no native formats
[02:33:14] [PASSED] XRGB8888 as native format
[02:33:14] [PASSED] remove duplicates
[02:33:14] [PASSED] convert alpha formats
[02:33:14] [PASSED] random formats
[02:33:14] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[02:33:14] ============= [PASSED] drm_sysfb_modeset_test ==============
[02:33:14] ================== drm_fixp (2 subtests) ===================
[02:33:14] [PASSED] drm_test_int2fixp
[02:33:14] [PASSED] drm_test_sm2fixp
[02:33:14] ==================== [PASSED] drm_fixp =====================
[02:33:14] ============================================================
[02:33:14] Testing complete. Ran 630 tests: passed: 630
[02:33:14] Elapsed time: 27.579s total, 1.693s configuring, 25.465s building, 0.387s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[02:33:14] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[02:33:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[02:33:25] Starting KUnit Kernel (1/1)...
[02:33:25] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[02:33:26] ================= ttm_device (5 subtests) ==================
[02:33:26] [PASSED] ttm_device_init_basic
[02:33:26] [PASSED] ttm_device_init_multiple
[02:33:26] [PASSED] ttm_device_fini_basic
[02:33:26] [PASSED] ttm_device_init_no_vma_man
[02:33:26] ================== ttm_device_init_pools  ==================
[02:33:26] [PASSED] No DMA allocations, no DMA32 required
[02:33:26] [PASSED] DMA allocations, DMA32 required
[02:33:26] [PASSED] No DMA allocations, DMA32 required
[02:33:26] [PASSED] DMA allocations, no DMA32 required
[02:33:26] ============== [PASSED] ttm_device_init_pools ==============
[02:33:26] =================== [PASSED] ttm_device ====================
[02:33:26] ================== ttm_pool (8 subtests) ===================
[02:33:26] ================== ttm_pool_alloc_basic  ===================
[02:33:26] [PASSED] One page
[02:33:26] [PASSED] More than one page
[02:33:26] [PASSED] Above the allocation limit
[02:33:26] [PASSED] One page, with coherent DMA mappings enabled
[02:33:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[02:33:26] ============== [PASSED] ttm_pool_alloc_basic ===============
[02:33:26] ============== ttm_pool_alloc_basic_dma_addr  ==============
[02:33:26] [PASSED] One page
[02:33:26] [PASSED] More than one page
[02:33:26] [PASSED] Above the allocation limit
[02:33:26] [PASSED] One page, with coherent DMA mappings enabled
[02:33:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[02:33:26] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[02:33:26] [PASSED] ttm_pool_alloc_order_caching_match
[02:33:26] [PASSED] ttm_pool_alloc_caching_mismatch
[02:33:26] [PASSED] ttm_pool_alloc_order_mismatch
[02:33:26] [PASSED] ttm_pool_free_dma_alloc
[02:33:26] [PASSED] ttm_pool_free_no_dma_alloc
[02:33:26] [PASSED] ttm_pool_fini_basic
[02:33:26] ==================== [PASSED] ttm_pool =====================
[02:33:26] ================ ttm_resource (8 subtests) =================
[02:33:26] ================= ttm_resource_init_basic  =================
[02:33:26] [PASSED] Init resource in TTM_PL_SYSTEM
[02:33:26] [PASSED] Init resource in TTM_PL_VRAM
[02:33:26] [PASSED] Init resource in a private placement
[02:33:26] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[02:33:26] ============= [PASSED] ttm_resource_init_basic =============
[02:33:26] [PASSED] ttm_resource_init_pinned
[02:33:26] [PASSED] ttm_resource_fini_basic
[02:33:26] [PASSED] ttm_resource_manager_init_basic
[02:33:26] [PASSED] ttm_resource_manager_usage_basic
[02:33:26] [PASSED] ttm_resource_manager_set_used_basic
[02:33:26] [PASSED] ttm_sys_man_alloc_basic
[02:33:26] [PASSED] ttm_sys_man_free_basic
[02:33:26] ================== [PASSED] ttm_resource ===================
[02:33:26] =================== ttm_tt (15 subtests) ===================
[02:33:26] ==================== ttm_tt_init_basic  ====================
[02:33:26] [PASSED] Page-aligned size
[02:33:26] [PASSED] Extra pages requested
[02:33:26] ================ [PASSED] ttm_tt_init_basic ================
[02:33:26] [PASSED] ttm_tt_init_misaligned
[02:33:26] [PASSED] ttm_tt_fini_basic
[02:33:26] [PASSED] ttm_tt_fini_sg
[02:33:26] [PASSED] ttm_tt_fini_shmem
[02:33:26] [PASSED] ttm_tt_create_basic
[02:33:26] [PASSED] ttm_tt_create_invalid_bo_type
[02:33:26] [PASSED] ttm_tt_create_ttm_exists
[02:33:26] [PASSED] ttm_tt_create_failed
[02:33:26] [PASSED] ttm_tt_destroy_basic
[02:33:26] [PASSED] ttm_tt_populate_null_ttm
[02:33:26] [PASSED] ttm_tt_populate_populated_ttm
[02:33:26] [PASSED] ttm_tt_unpopulate_basic
[02:33:26] [PASSED] ttm_tt_unpopulate_empty_ttm
[02:33:26] [PASSED] ttm_tt_swapin_basic
[02:33:26] ===================== [PASSED] ttm_tt ======================
[02:33:26] =================== ttm_bo (14 subtests) ===================
[02:33:26] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[02:33:26] [PASSED] Cannot be interrupted and sleeps
[02:33:26] [PASSED] Cannot be interrupted, locks straight away
[02:33:26] [PASSED] Can be interrupted, sleeps
[02:33:26] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[02:33:26] [PASSED] ttm_bo_reserve_locked_no_sleep
[02:33:26] [PASSED] ttm_bo_reserve_no_wait_ticket
[02:33:26] [PASSED] ttm_bo_reserve_double_resv
[02:33:26] [PASSED] ttm_bo_reserve_interrupted
[02:33:26] [PASSED] ttm_bo_reserve_deadlock
[02:33:26] [PASSED] ttm_bo_unreserve_basic
[02:33:26] [PASSED] ttm_bo_unreserve_pinned
[02:33:26] [PASSED] ttm_bo_unreserve_bulk
[02:33:26] [PASSED] ttm_bo_fini_basic
[02:33:26] [PASSED] ttm_bo_fini_shared_resv
[02:33:26] [PASSED] ttm_bo_pin_basic
[02:33:26] [PASSED] ttm_bo_pin_unpin_resource
[02:33:26] [PASSED] ttm_bo_multiple_pin_one_unpin
[02:33:26] ===================== [PASSED] ttm_bo ======================
[02:33:26] ============== ttm_bo_validate (21 subtests) ===============
[02:33:26] ============== ttm_bo_init_reserved_sys_man  ===============
[02:33:26] [PASSED] Buffer object for userspace
[02:33:26] [PASSED] Kernel buffer object
[02:33:26] [PASSED] Shared buffer object
[02:33:26] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[02:33:26] ============== ttm_bo_init_reserved_mock_man  ==============
[02:33:26] [PASSED] Buffer object for userspace
[02:33:26] [PASSED] Kernel buffer object
[02:33:26] [PASSED] Shared buffer object
[02:33:26] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[02:33:26] [PASSED] ttm_bo_init_reserved_resv
[02:33:26] ================== ttm_bo_validate_basic  ==================
[02:33:26] [PASSED] Buffer object for userspace
[02:33:26] [PASSED] Kernel buffer object
[02:33:26] [PASSED] Shared buffer object
[02:33:26] ============== [PASSED] ttm_bo_validate_basic ==============
[02:33:26] [PASSED] ttm_bo_validate_invalid_placement
[02:33:26] ============= ttm_bo_validate_same_placement  ==============
[02:33:26] [PASSED] System manager
[02:33:26] [PASSED] VRAM manager
[02:33:26] ========= [PASSED] ttm_bo_validate_same_placement ==========
[02:33:26] [PASSED] ttm_bo_validate_failed_alloc
[02:33:26] [PASSED] ttm_bo_validate_pinned
[02:33:26] [PASSED] ttm_bo_validate_busy_placement
[02:33:26] ================ ttm_bo_validate_multihop  =================
[02:33:26] [PASSED] Buffer object for userspace
[02:33:26] [PASSED] Kernel buffer object
[02:33:26] [PASSED] Shared buffer object
[02:33:26] ============ [PASSED] ttm_bo_validate_multihop =============
[02:33:26] ========== ttm_bo_validate_no_placement_signaled  ==========
[02:33:26] [PASSED] Buffer object in system domain, no page vector
[02:33:26] [PASSED] Buffer object in system domain with an existing page vector
[02:33:26] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[02:33:26] ======== ttm_bo_validate_no_placement_not_signaled  ========
[02:33:26] [PASSED] Buffer object for userspace
[02:33:26] [PASSED] Kernel buffer object
[02:33:26] [PASSED] Shared buffer object
[02:33:26] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[02:33:26] [PASSED] ttm_bo_validate_move_fence_signaled
[02:33:26] ========= ttm_bo_validate_move_fence_not_signaled  =========
[02:33:26] [PASSED] Waits for GPU
[02:33:26] [PASSED] Tries to lock straight away
[02:33:26] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[02:33:26] [PASSED] ttm_bo_validate_happy_evict
[02:33:26] [PASSED] ttm_bo_validate_all_pinned_evict
[02:33:26] [PASSED] ttm_bo_validate_allowed_only_evict
[02:33:26] [PASSED] ttm_bo_validate_deleted_evict
[02:33:26] [PASSED] ttm_bo_validate_busy_domain_evict
[02:33:26] [PASSED] ttm_bo_validate_evict_gutting
[02:33:26] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[02:33:26] ================= [PASSED] ttm_bo_validate =================
[02:33:26] ============================================================
[02:33:26] Testing complete. Ran 101 tests: passed: 101
[02:33:26] Elapsed time: 11.223s total, 1.599s configuring, 9.409s building, 0.181s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe: Separate out GuC RC code (rev4)

[Patchwork]

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== Series Details ==

Series: drm/xe: Separate out GuC RC code (rev4)
URL   : https://patchwork.freedesktop.org/series/158581/
State : success

== Summary ==

CI Bug Log - changes from xe-4462-ba05f22d6945596fac691e952c98f566696c24ad_BAT -> xe-pw-158581v4_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-158581v4_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@reltime:
    - bat-dg2-oem2:       [PASS][1] -> [FAIL][2] ([Intel XE#6520])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4462-ba05f22d6945596fac691e952c98f566696c24ad/bat-dg2-oem2/igt@xe_waitfence@reltime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158581v4/bat-dg2-oem2/igt@xe_waitfence@reltime.html

  
  [Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520


Build changes
-------------

  * Linux: xe-4462-ba05f22d6945596fac691e952c98f566696c24ad -> xe-pw-158581v4

  IGT_8721: 3707bb4267de22a18d61b232c4ab5fbaf61db90c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4462-ba05f22d6945596fac691e952c98f566696c24ad: ba05f22d6945596fac691e952c98f566696c24ad
  xe-pw-158581v4: 158581v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158581v4/index.html

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