From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: <intel-gfx@lists.freedesktop.org>,
<intel-xe@lists.freedesktop.org>, <jani.nikula@linux.intel.com>,
<mitulkumar.ajitkumar.golani@intel.com>
Subject: Re: [PATCH 15/16] drm/i915/display: Separate out functions to get/set VTOTAL register
Date: Tue, 25 Mar 2025 21:23:35 +0530 [thread overview]
Message-ID: <55cb4b81-dfc6-4e89-90c9-13750777a658@intel.com> (raw)
In-Reply-To: <Z-Kze5WxTVVs5bbi@intel.com>
On 3/25/2025 7:15 PM, Ville Syrjälä wrote:
> On Tue, Mar 25, 2025 at 11:52:24AM +0530, Nautiyal, Ankit K wrote:
>> On 3/24/2025 11:32 PM, Ville Syrjälä wrote:
>>> On Mon, Mar 24, 2025 at 07:02:47PM +0530, Ankit Nautiyal wrote:
>>>> Introduce helpers to get and set TRANS_VTOTAL registers.
>>>> This will pave way to avoid reading/writing VTOTAL.Vtotal bits for
>>>> platforms that always use VRR timing generator.
>>>>
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_display.c | 41 +++++++++++++-------
>>>> 1 file changed, 27 insertions(+), 14 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>>> index ae1dc32044fb..fa9c6793357e 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>>> @@ -2638,6 +2638,15 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
>>>> PIPE_LINK_N2(display, transcoder));
>>>> }
>>>>
>>>> +static void intel_crtc_set_vtotal(struct intel_display *display,
>>>> + enum transcoder cpu_transcoder,
>>>> + u32 crtc_vdisplay, u32 crtc_vtotal)
>>>> +{
>>>> + intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
>>>> + VACTIVE(crtc_vdisplay - 1) |
>>>> + VTOTAL(crtc_vtotal - 1));
>>>> +}
>>>> +
>>>> static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>>>> {
>>>> struct intel_display *display = to_intel_display(crtc_state);
>>>> @@ -2702,9 +2711,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>>>> HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
>>>> HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
>>>>
>>>> - intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
>>>> - VACTIVE(crtc_vdisplay - 1) |
>>>> - VTOTAL(crtc_vtotal - 1));
>>>> + intel_crtc_set_vtotal(display, cpu_transcoder, crtc_vdisplay, crtc_vtotal);
>>>> +
>>>> intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
>>>> VBLANK_START(crtc_vblank_start - 1) |
>>>> VBLANK_END(crtc_vblank_end - 1));
>>>> @@ -2718,9 +2726,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>>>> * bits. */
>>>> if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP &&
>>>> (pipe == PIPE_B || pipe == PIPE_C))
>>>> - intel_de_write(display, TRANS_VTOTAL(display, pipe),
>>>> - VACTIVE(crtc_vdisplay - 1) |
>>>> - VTOTAL(crtc_vtotal - 1));
>>>> + intel_crtc_set_vtotal(display, (enum transcoder)pipe,
>>>> + crtc_vdisplay, crtc_vtotal);
>>>> }
>>>>
>>>> static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
>>>> @@ -2766,9 +2773,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
>>>> * The double buffer latch point for TRANS_VTOTAL
>>>> * is the transcoder's undelayed vblank.
>>>> */
>>>> - intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
>>>> - VACTIVE(crtc_vdisplay - 1) |
>>>> - VTOTAL(crtc_vtotal - 1));
>>>> + intel_crtc_set_vtotal(display, cpu_transcoder, crtc_vdisplay, crtc_vtotal);
>>> Not really a fan of special casing this that much. I think we should
>>> probably handle it the same way we deal with the VBLANK_START vs.
>>> TRANS_SET_CONTEXT_LATENCY.
>> Hmm I can do away with the helper, and avoid having VTOTAL.Vtotal bits
>> set for specific cases in intel_vrr_set_transcoder_{timings, timings_lrr}.
>>> The readount should perhaps just be handled in intel_vrr_get_config().
>> I can try this out.
>>
>>
>>> But I think we'll need somehting like transcoder_has_vrr() to exclude
>>> the DSI transcoders in a consistent way.
>> If I understand correctly you mean that wherever we are avoiding VRR
>> related register read/write for DSI, use trans_has_vrr() instead of
>> !transcoder_is_dsi(),
>>
>> with trans_has_vrr having call to transcoder_is_dsi()?
> Yeah something like that.
>
>> Will perhaps add this as a separate patch.
> These two last patches aren't needed to get this stuff actually
> working right? Or is the GOP leaving TRANS_VOTAL.vtotal unset?
> So yeah, if not needed right now probably best to leave this
> stuff for a seaprate series.
Yes we can have a separate series for the last one.
though, I have sent new revision, we can get the patches-1-14 merge as
suggested.
Thanks Ville!
Regards,
Ankit
>
next prev parent reply other threads:[~2025-03-25 15:53 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-24 13:32 [PATCH 00/16] Use VRR timing generator for fixed refresh rate modes Ankit Nautiyal
2025-03-24 13:32 ` [PATCH 01/16] drm/i915/hdmi: Use VRR Timing generator for HDMI for fixed_rr Ankit Nautiyal
2025-03-24 13:32 ` [PATCH 02/16] drm/i915/dp_mst: Use VRR Timing generator for DP MST " Ankit Nautiyal
2025-03-24 17:42 ` Ville Syrjälä
2025-03-25 4:35 ` Nautiyal, Ankit K
2025-03-24 13:32 ` [PATCH 03/16] drm/i915/display: Disable PSR before disabling VRR Ankit Nautiyal
2025-03-24 13:32 ` [PATCH 04/16] drm/i915/display: Move intel_psr_post_plane_update() at the later Ankit Nautiyal
2025-03-24 17:00 ` Nautiyal, Ankit K
2025-03-24 13:32 ` [PATCH 05/16] drm/i915/vrr: Refactor condition for computing vmax and LRR Ankit Nautiyal
2025-03-24 13:32 ` [PATCH 06/16] drm/i915/vrr: Always set vrr vmax/vmin/flipline in vrr_{enable/disable} Ankit Nautiyal
2025-03-24 13:32 ` [PATCH 07/16] drm/i915/vrr: Set vrr.enable for VRR TG with fixed_rr Ankit Nautiyal
2025-03-24 13:32 ` [PATCH 08/16] drm/i915/display: Use fixed_rr timings in modeset sequence Ankit Nautiyal
2025-03-24 13:32 ` [PATCH 09/16] drm/i915/vrr: Use fixed timings for platforms that support VRR Ankit Nautiyal
2025-03-24 13:32 ` [PATCH 10/16] drm/i915/display: Use fixed rr timings in intel_set_transcoder_timings_lrr() Ankit Nautiyal
2025-03-24 13:32 ` [PATCH 11/16] drm/i915/display: Move vrr.guardband/pipeline_full out of !fastset block Ankit Nautiyal
2025-03-24 13:32 ` [PATCH 12/16] drm/i915/vrr: Allow fixed_rr with pipe joiner Ankit Nautiyal
2025-03-24 13:32 ` [PATCH 13/16] drm/i915/vrr: Always use VRR timing generator for PTL+ Ankit Nautiyal
2025-03-24 13:32 ` [PATCH 14/16] drm/i915/vrr: Set trans_vrr_ctl in intel_vrr_set_transcoder_timings() Ankit Nautiyal
2025-03-24 17:55 ` Ville Syrjälä
2025-03-24 13:32 ` [PATCH 15/16] drm/i915/display: Separate out functions to get/set VTOTAL register Ankit Nautiyal
2025-03-24 18:02 ` Ville Syrjälä
2025-03-25 6:22 ` Nautiyal, Ankit K
2025-03-25 13:45 ` Ville Syrjälä
2025-03-25 15:53 ` Nautiyal, Ankit K [this message]
2025-03-24 13:32 ` [PATCH 16/16] drm/i915/display: Avoid use of VTOTAL.Vtotal bits Ankit Nautiyal
2025-03-24 14:19 ` ✓ CI.Patch_applied: success for Use VRR timing generator for fixed refresh rate modes (rev11) Patchwork
2025-03-24 14:19 ` ✓ CI.checkpatch: " Patchwork
2025-03-24 14:20 ` ✓ CI.KUnit: " Patchwork
2025-03-24 14:37 ` ✓ CI.Build: " Patchwork
2025-03-24 14:39 ` ✓ CI.Hooks: " Patchwork
2025-03-24 14:41 ` ✗ CI.checksparse: warning " Patchwork
2025-03-24 15:01 ` ✓ Xe.CI.BAT: success " Patchwork
2025-03-24 17:00 ` ✗ Xe.CI.Full: failure " Patchwork
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