Re: [PATCH 04/12] drm/i915/dp: Add helper to get AS SDP Transmission Line

["Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>]

On 4/13/2026 2:04 PM, Jani Nikula wrote:
> On Mon, 13 Apr 2026, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> Introduce a DP helper to compute the Adaptive Sync SDP transmission line
>> and use it when programming the EMP_AS_SDP_TL register.
>>
>> Currently the AS SDP transmission line is programmed to the T1 position.
>> This can be extended in the future to support programming the T2 position
>> as well.
>>
>> While at it, improve the documentation: the AS SDP transmission line
>> corresponds to the T1 position, which maps to the start of the VSYNC
>> pulse.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c  | 12 ++++++++++++
>>   drivers/gpu/drm/i915/display/intel_dp.h  |  2 ++
>>   drivers/gpu/drm/i915/display/intel_vrr.c |  4 ++--
>>   3 files changed, 16 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 4955bd8b11d7..fd668babd641 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -7415,3 +7415,15 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>>   
>>   	return true;
>>   }
>> +
>> +int intel_dp_sdp_as_tl(const struct intel_crtc_state *crtc_state)
> So the name of the function is Intel display port secondary data packet
> adaptive sync transmission line.
>
> The function name doesn't say what the function *does*.

I agree. I will make the function reflect what the function does.


Thanks & Regards,

Ankit


>
>> +{
>> +	/*
>> +	 * EMP_AS_SDP_TL defines the T1 position as the default AS SDP
>> +	 * Transmission Line, which corresponds to the start of the
>> +	 * VSYNC pulse.
>> +	 *
>> +	 * Use the T1 position for now.
>> +	 */
>> +	return crtc_state->vrr.vsync_start;
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index 2849b9ecdc71..7024fd0ace0a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -238,4 +238,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>>   	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>>   		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
>>   
>> +int intel_dp_sdp_as_tl(const struct intel_crtc_state *crtc_state);
>> +
>>   #endif /* __INTEL_DP_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 5164d8c354e0..b700da4e9256 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -607,11 +607,11 @@ void intel_vrr_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
>>   
>>   	/*
>>   	 * Since currently we support VRR only for DP/eDP, so this is programmed
>> -	 * only for Adaptive Sync SDP to Vsync start.
>> +	 * only for Adaptive Sync SDP.
>>   	 */
>>   	intel_de_write(display,
>>   		       EMP_AS_SDP_TL(display, cpu_transcoder),
>> -		       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
>> +		       EMP_AS_SDP_DB_TL(intel_dp_sdp_as_tl(crtc_state)));
>>   }
>>   
>>   void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)