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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>,
	intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org,
	mitulkumar.ajitkumar.golani@intel.com,
	ankit.k.nautiyal@intel.com, uma.shankar@intel.com,
	ville.syrjala@linux.intel.com
Subject: Re: [RESEND, 17/22] drm/i915/dsb: Add pipedmc dc balance enable/disable
Date: Mon, 03 Nov 2025 12:02:42 +0200	[thread overview]
Message-ID: <73cbd5c241eb2838ccc91a452e9f88a71a339050@intel.com> (raw)
In-Reply-To: <20251103053002.3002695-18-mitulkumar.ajitkumar.golani@intel.com>

On Mon, 03 Nov 2025, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add function to control DC balance enable/disable bit via DSB.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dmc.c | 17 +++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dmc.h |  4 ++++
>  2 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 0bddb20a7c86..3e3f4438d739 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -1748,3 +1748,20 @@ u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc)
>  
>  	return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0;
>  }
> +
> +void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	enum pipe pipe = crtc->pipe;
> +
> +	intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe),
> +			   PIPEDMC_ADAPTIVE_DCB_ENABLE);
> +}
> +
> +void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	enum pipe pipe = crtc->pipe;
> +
> +	intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 40e9dcb033cc..132d6cfc8e8b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -10,11 +10,13 @@
>  
>  enum pipe;
>  enum pipedmc_event_id;
> +struct intel_crtc;
>  struct drm_printer;
>  struct intel_crtc;
>  struct intel_crtc_state;
>  struct intel_display;
>  struct intel_dmc_snapshot;
> +struct intel_dsb;

Please keep forward declarations sorted.

>  
>  void intel_dmc_init(struct intel_display *display);
>  void intel_dmc_load_program(struct intel_display *display);
> @@ -39,6 +41,8 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star
>  void assert_main_dmc_loaded(struct intel_display *display);
>  
>  void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
> +void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc);
> +void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc);
>  
>  u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc);
>  void intel_pipedmc_enable_event(struct intel_crtc *crtc,

-- 
Jani Nikula, Intel

  reply	other threads:[~2025-11-03 10:02 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-03  5:29 [RESEND, 00/22] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-11-03  5:29 ` [RESEND, 01/22] drm/i915/display: Add source param for dc balance Mitul Golani
2025-11-03  5:29 ` [RESEND, 02/22] drm/i915/dmc: Add pipe dmc registers and bits for DC Balance Mitul Golani
2025-11-05  4:15   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 03/22] drm/i915/vrr: Add VRR DC balance registers Mitul Golani
2025-11-03  9:59   ` Jani Nikula
2025-11-05  4:19   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 04/22] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
2025-11-03  5:29 ` [RESEND, 05/22] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
2025-11-05  4:24   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 06/22] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
2025-11-05  4:25   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 07/22] drm/i915/vrr: Add compute config " Mitul Golani
2025-11-05  4:27   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 08/22] drm/i915/display: Add DC Balance flip counter in crtc Mitul Golani
2025-11-05  4:28   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 09/22] drm/i915/vrr: Increment DC balance flip count on every flip Mitul Golani
2025-11-03 10:01   ` Jani Nikula
2025-11-05  4:51   ` Nautiyal, Ankit K
2025-11-05  6:15   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 10/22] drm/i915/vrr: Add function to reset DC Balance flip count Mitul Golani
2025-11-05  4:52   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 11/22] drm/i915/vrr: Add function reset DC balance accumulated params Mitul Golani
2025-11-05  4:54   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 12/22] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
2025-11-05  4:56   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 13/22] drm/i915/vrr: Configure DC balance flipline adjustment Mitul Golani
2025-11-05  4:57   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 14/22] drm/i915/vblank: Extract vrr_vblank_start() Mitul Golani
2025-11-03  5:29 ` [RESEND, 15/22] drm/i915/vrr: Implement vblank evasion with DC balancing Mitul Golani
2025-11-03  5:29 ` [RESEND, 16/22] drm/i915/display: Wait for VRR PUSH status update Mitul Golani
2025-11-05  5:59   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 17/22] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
2025-11-03 10:02   ` Jani Nikula [this message]
2025-11-03  5:29 ` [RESEND, 18/22] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
2025-11-03  5:29 ` [RESEND, 19/22] drm/i915/display: Add function to configure event for dc balance Mitul Golani
2025-11-05  6:18   ` Nautiyal, Ankit K
2025-11-03  5:30 ` [RESEND, 20/22] drm/i915/vrr: Enable Adaptive sync counter bit Mitul Golani
2025-11-05  6:02   ` Nautiyal, Ankit K
2025-11-03  5:30 ` [RESEND, 21/22] drm/i915/vrr: Enable DC Balance Mitul Golani
2025-11-03  5:30 ` [RESEND, 22/22] drm/i915/vrr: Add function to check if DC Balance Possible Mitul Golani
2025-11-05  6:04   ` Nautiyal, Ankit K
2025-11-03  5:38 ` ✗ CI.checkpatch: warning for Enable/Disable DC balance along with VRR DSB Patchwork
2025-11-03  5:39 ` ✓ CI.KUnit: success " Patchwork

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