From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>,
<intel-gfx@lists.freedesktop.org>
Cc: <intel-xe@lists.freedesktop.org>, <uma.shankar@intel.com>,
<ville.syrjala@linux.intel.com>
Subject: Re: [RESEND, 11/22] drm/i915/vrr: Add function reset DC balance accumulated params
Date: Wed, 5 Nov 2025 10:24:10 +0530 [thread overview]
Message-ID: <9316274c-2379-4e96-be4a-26b36406a5f0@intel.com> (raw)
In-Reply-To: <20251103053002.3002695-12-mitulkumar.ajitkumar.golani@intel.com>
On 11/3/2025 10:59 AM, Mitul Golani wrote:
> Add function which resets all accumulated DC Balance parameters
> whenever adaptive mode of VRR goes off. This helps to give a
> fresh start when VRR is re-enabled.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 13 +++++++++++++
> drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++
> 3 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 323293f4bf6d..b256517d58cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1149,6 +1149,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
> if (intel_crtc_vrr_disabling(state, crtc)) {
> intel_vrr_disable(old_crtc_state);
> intel_vrr_dcb_reset_flip_count(old_crtc_state, crtc);
> + intel_vrr_dcb_balance_reset(old_crtc_state, crtc);
Lets have both the reset functions in the intel_vrr_dcb_balance_reset().
Move this patch before the dcb_flip_count introduction patch.
Call the function to reset the flip_count from intel_vrr_dcb_balance_reset()
Regards,
Ankit
> intel_crtc_update_active_timings(old_crtc_state, false);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 2ae27751e5b4..6168caff9cf0 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -639,6 +639,19 @@ void intel_vrr_dcb_reset_flip_count(const struct intel_crtc_state *crtc_state,
> intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0);
> }
>
> +void
> +intel_vrr_dcb_balance_reset(const struct intel_crtc_state *crtc_state,
> + struct intel_crtc *crtc)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum pipe pipe = crtc->pipe;
> +
> + if (!crtc_state->vrr.dc_balance.enable)
> + return;
> +
> + intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0);
> +}
> +
> void intel_vrr_send_push(struct intel_dsb *dsb,
> const struct intel_crtc_state *crtc_state)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 8f97525b8e2d..a713d1a1e3dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -44,6 +44,8 @@ void intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
> struct intel_crtc *crtc);
> void intel_vrr_dcb_reset_flip_count(const struct intel_crtc_state *crtc_state,
> struct intel_crtc *crtc);
> +void intel_vrr_dcb_balance_reset(const struct intel_crtc_state *crtc_state,
> + struct intel_crtc *crtc);
> bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
> int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
> int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
next prev parent reply other threads:[~2025-11-05 4:54 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-03 5:29 [RESEND, 00/22] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-11-03 5:29 ` [RESEND, 01/22] drm/i915/display: Add source param for dc balance Mitul Golani
2025-11-03 5:29 ` [RESEND, 02/22] drm/i915/dmc: Add pipe dmc registers and bits for DC Balance Mitul Golani
2025-11-05 4:15 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 03/22] drm/i915/vrr: Add VRR DC balance registers Mitul Golani
2025-11-03 9:59 ` Jani Nikula
2025-11-05 4:19 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 04/22] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
2025-11-03 5:29 ` [RESEND, 05/22] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
2025-11-05 4:24 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 06/22] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
2025-11-05 4:25 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 07/22] drm/i915/vrr: Add compute config " Mitul Golani
2025-11-05 4:27 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 08/22] drm/i915/display: Add DC Balance flip counter in crtc Mitul Golani
2025-11-05 4:28 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 09/22] drm/i915/vrr: Increment DC balance flip count on every flip Mitul Golani
2025-11-03 10:01 ` Jani Nikula
2025-11-05 4:51 ` Nautiyal, Ankit K
2025-11-05 6:15 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 10/22] drm/i915/vrr: Add function to reset DC Balance flip count Mitul Golani
2025-11-05 4:52 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 11/22] drm/i915/vrr: Add function reset DC balance accumulated params Mitul Golani
2025-11-05 4:54 ` Nautiyal, Ankit K [this message]
2025-11-03 5:29 ` [RESEND, 12/22] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
2025-11-05 4:56 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 13/22] drm/i915/vrr: Configure DC balance flipline adjustment Mitul Golani
2025-11-05 4:57 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 14/22] drm/i915/vblank: Extract vrr_vblank_start() Mitul Golani
2025-11-03 5:29 ` [RESEND, 15/22] drm/i915/vrr: Implement vblank evasion with DC balancing Mitul Golani
2025-11-03 5:29 ` [RESEND, 16/22] drm/i915/display: Wait for VRR PUSH status update Mitul Golani
2025-11-05 5:59 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 17/22] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
2025-11-03 10:02 ` Jani Nikula
2025-11-03 5:29 ` [RESEND, 18/22] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
2025-11-03 5:29 ` [RESEND, 19/22] drm/i915/display: Add function to configure event for dc balance Mitul Golani
2025-11-05 6:18 ` Nautiyal, Ankit K
2025-11-03 5:30 ` [RESEND, 20/22] drm/i915/vrr: Enable Adaptive sync counter bit Mitul Golani
2025-11-05 6:02 ` Nautiyal, Ankit K
2025-11-03 5:30 ` [RESEND, 21/22] drm/i915/vrr: Enable DC Balance Mitul Golani
2025-11-03 5:30 ` [RESEND, 22/22] drm/i915/vrr: Add function to check if DC Balance Possible Mitul Golani
2025-11-05 6:04 ` Nautiyal, Ankit K
2025-11-03 5:38 ` ✗ CI.checkpatch: warning for Enable/Disable DC balance along with VRR DSB Patchwork
2025-11-03 5:39 ` ✓ CI.KUnit: success " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=9316274c-2379-4e96-be4a-26b36406a5f0@intel.com \
--to=ankit.k.nautiyal@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=mitulkumar.ajitkumar.golani@intel.com \
--cc=uma.shankar@intel.com \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox