Re: [RESEND, 12/22] drm/i915/vrr: Write DC balance params to hw registers

["Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>]

On 11/3/2025 10:59 AM, Mitul Golani wrote:
> Write DC Balance parameters to hw registers.
>
> --v2:
> - Update commit header.
> - Separate crtc_state params from this patch. (Ankit)
>
> --v3:
> - Write registers at compute config.
> - Update condition for write.
>
> --v4:
> - Address issue with state checker.
>
> --v5:
> - Initialise some more dc balance register while enabling VRR.
>
> --v6:
> - FLIPLINE_CFG need to be configure at last, as it is double buffer
> arming point.
>
> --v7:
> - Initialise and reset live value of vmax and vmin as well.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 53 ++++++++++++++++++++++++
>   1 file changed, 53 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 6168caff9cf0..2d418f45569f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -764,10 +764,43 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	enum pipe pipe = crtc->pipe;
>   	u32 vrr_ctl;
>   
>   	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN);
>   
> +	if (crtc_state->vrr.dc_balance.enable) {
> +		intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),
> +			       VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
> +		intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder),
> +			       VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
> +		intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder),
> +			       VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
> +		intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder),
> +			       VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
> +		intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),
> +			       VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
> +		intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder),
> +			       VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
> +		intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder),
> +			       VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
> +		intel_de_write(display, PIPEDMC_DCB_VMIN(pipe),
> +			       crtc_state->vrr.dc_balance.vmin - 1);
> +		intel_de_write(display, PIPEDMC_DCB_VMAX(pipe),
> +			       crtc_state->vrr.dc_balance.vmax - 1);
> +		intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe),
> +			       crtc_state->vrr.dc_balance.max_increase);
> +		intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe),
> +			       crtc_state->vrr.dc_balance.max_decrease);
> +		intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe),
> +			       crtc_state->vrr.dc_balance.guardband);
> +		intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe),
> +			       crtc_state->vrr.dc_balance.slope);
> +		intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
> +			       crtc_state->vrr.dc_balance.vblank_target);

Can we make a separate function for this something like:

intel_vrr_enable_dc_balancing()

{

if (!crtc_state->vrr.dc_balance.enable)

Return;

…..

…..

}

Similar thing for disable.


Regards,

Ankit


> +	}
> +
>   	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
>   
>   	/*
> @@ -785,6 +818,8 @@ static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(old_crtc_state);
>   	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> +	enum pipe pipe = crtc->pipe;
>   
>   	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
>   		       trans_vrr_ctl(old_crtc_state));
> @@ -795,6 +830,24 @@ static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
>   		drm_err(display->drm, "Timed out waiting for VRR live status to clear\n");
>   
>   	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
> +
> +	if (old_crtc_state->vrr.dc_balance.enable) {
> +		intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
> +		intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
> +		intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0);
> +		intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0);
> +		intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0);
> +		intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0);
> +		intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0);
> +		intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), 0);
> +		intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), 0);
> +		intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), 0);
> +		intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), 0);
> +		intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0);
> +		intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
> +		intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
> +		intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
> +	}
>   }
>   
>   void intel_vrr_enable(const struct intel_crtc_state *crtc_state)