From: "Borah, Chaitanya Kumar" <chaitanya.kumar.borah@intel.com>
To: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>,
<intel-gfx@lists.freedesktop.org>
Cc: <intel-xe@lists.freedesktop.org>, <uma.shankar@intel.com>,
<ankit.k.nautiyal@intel.com>
Subject: Re: [PATCH v6 5/9] drm/i915/display: Move CMRR crtc_state members under VRR
Date: Thu, 23 Jul 2026 21:48:19 +0530 [thread overview]
Message-ID: <7b54f757-68da-4c48-bfb5-aa2448a85e48@intel.com> (raw)
In-Reply-To: <20260722043923.3241977-6-mitulkumar.ajitkumar.golani@intel.com>
On 7/22/2026 10:09 AM, Mitul Golani wrote:
> Move CMRR crtc state members under VRR infrastructure as
> it is enabled during fix refresh rate VRR timing generator
> is enabled.
>
The RB was contintgent on changing the commit message.
"it is enabled when the fixed-refresh-rate VRR timing generator is enabled
"
Please don't ignore the *conditions* in a *conditional* RB.
> --v2:
> - Move cmrr structure under vrr umbrella.
> - Remove dups. (Jani)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 10 +++----
> .../drm/i915/display/intel_display_types.h | 12 ++++----
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> drivers/gpu/drm/i915/display/intel_vrr.c | 30 +++++++++----------
> 6 files changed, 29 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index c8e0f90af910..3c0f5b2fb2e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -326,7 +326,7 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
> XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
>
> /* TODO: The code below may need to be revisited once CMRR is enabled */
> - if (crtc_state->cmrr.enable)
> + if (crtc_state->vrr.cmrr.enable)
> vrr_ctl |= VRR_CTL_CMRR_ENABLE;
>
> intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder), vrr_ctl);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2c55a4818ad7..5baa9602b86e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -950,8 +950,8 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
> static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> - return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
> - old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
> + return old_crtc_state->vrr.cmrr.cmrr_m != new_crtc_state->vrr.cmrr.cmrr_m ||
> + old_crtc_state->vrr.cmrr.cmrr_n != new_crtc_state->vrr.cmrr.cmrr_n;
> }
>
> static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
> @@ -5523,9 +5523,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_I(vrr.flipline);
> PIPE_CONF_CHECK_I(vrr.vsync_start);
> PIPE_CONF_CHECK_I(vrr.vsync_end);
> - PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
> - PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
> - PIPE_CONF_CHECK_BOOL(cmrr.enable);
> + PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_m);
> + PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_n);
> + PIPE_CONF_CHECK_BOOL(vrr.cmrr.enable);
> PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
> PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
> PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 46dd980b315a..20a07ea06b5e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1408,13 +1408,13 @@ struct intel_crtc_state {
> u16 max_increase, max_decrease;
> u16 vblank_target;
> } dc_balance;
> - } vrr;
>
> - /* Content Match Refresh Rate state */
> - struct {
> - bool enable;
> - u64 cmrr_n, cmrr_m;
> - } cmrr;
> + /* Content Match Refresh Rate state */
> + struct {
> + bool enable;
> + u64 cmrr_n, cmrr_m;
> + } cmrr;
> + } vrr;
>
> /* Stream Splitter for eDP MSO */
> struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 23e169d8db7b..51afe519073f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3129,7 +3129,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> as_sdp->revision = 0x2;
> as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
>
> - if (crtc_state->cmrr.enable) {
> + if (crtc_state->vrr.cmrr.enable) {
> as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
> as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 6a90ded5d1fa..e9e47522495d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1587,7 +1587,7 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
> struct intel_dp *intel_dp = intel_attached_dp(connector);
> struct intel_display *display = to_intel_display(intel_dp);
>
> - if (crtc_state->cmrr.enable) {
> + if (crtc_state->vrr.cmrr.enable) {
> drm_dbg_kms(display->drm,
> "Selective update cannot be enabled when CMRR is enabled\n");
> goto unsupported;
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 267c65d9245f..84b1ec7f1616 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -235,12 +235,12 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
> multiplier_n = 1000;
> }
>
> - crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
> - multiplier_n);
> + crtc_state->vrr.cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
> + multiplier_n);
> vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
> - crtc_state->cmrr.cmrr_n);
> + crtc_state->vrr.cmrr.cmrr_n);
> adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
> - crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
> + crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
>
> return vtotal;
> }
> @@ -258,7 +258,7 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
> crtc_state->vrr.vmin = crtc_state->vrr.vmax;
> crtc_state->vrr.flipline = crtc_state->vrr.vmin;
>
> - crtc_state->cmrr.enable = true;
> + crtc_state->vrr.cmrr.enable = true;
> crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> }
>
> @@ -651,15 +651,15 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> return;
> }
>
> - if (crtc_state->cmrr.enable) {
> + if (crtc_state->vrr.cmrr.enable) {
> intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
> - upper_32_bits(crtc_state->cmrr.cmrr_m));
> + upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
> - lower_32_bits(crtc_state->cmrr.cmrr_m));
> + lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
> - upper_32_bits(crtc_state->cmrr.cmrr_n));
> + upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> - lower_32_bits(crtc_state->cmrr.cmrr_n));
> + lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> }
>
> intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
> @@ -980,7 +980,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> intel_vrr_enable_dc_balancing(crtc_state);
>
> if (!intel_vrr_always_use_vrr_tg(display))
> - intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
> + intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
> }
>
> void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> @@ -1077,12 +1077,12 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> TRANS_VRR_CTL(display, cpu_transcoder));
>
> if (intel_vrr_cmrr_possible(crtc_state))
> - crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
> + crtc_state->vrr.cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
>
> - if (crtc_state->cmrr.enable) {
> - crtc_state->cmrr.cmrr_n =
> + if (crtc_state->vrr.cmrr.enable) {
> + crtc_state->vrr.cmrr.cmrr_n =
> intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));
> - crtc_state->cmrr.cmrr_m =
> + crtc_state->vrr.cmrr.cmrr_m =
> intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder));
> }
>
next prev parent reply other threads:[~2026-07-23 16:18 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-22 4:39 [PATCH v6 0/9] Enable CMRR in fixed-RR VRR path Mitul Golani
2026-07-22 4:39 ` [PATCH v6 1/9] drm/i915/vrr: Return from PSR2 compute config in case of CMRR enabled Mitul Golani
2026-07-23 16:15 ` Borah, Chaitanya Kumar
2026-07-24 10:22 ` Golani, Mitulkumar Ajitkumar
2026-07-24 10:33 ` Borah, Chaitanya Kumar
2026-07-22 4:39 ` [PATCH v6 2/9] drm/i915/vrr: Restrict CMRR enable condition to VRR-TG-default platforms Mitul Golani
2026-07-23 16:16 ` Borah, Chaitanya Kumar
2026-07-22 4:39 ` [PATCH v6 3/9] drm/i915/vrr: Add per-CRTC vrr/cmrr debugfs control Mitul Golani
2026-07-23 16:16 ` Borah, Chaitanya Kumar
2026-07-22 4:39 ` [PATCH v6 4/9] drm/i915/vrr: Update AS_SDP target_rr_divider based on CMRR config request Mitul Golani
2026-07-23 16:17 ` Borah, Chaitanya Kumar
2026-07-22 4:39 ` [PATCH v6 5/9] drm/i915/display: Move CMRR crtc_state members under VRR Mitul Golani
2026-07-23 16:18 ` Borah, Chaitanya Kumar [this message]
2026-07-22 4:39 ` [PATCH v6 6/9] drm/i915/vrr: Compute CMRR fractional timings generically Mitul Golani
2026-07-23 16:19 ` Borah, Chaitanya Kumar
2026-07-22 4:39 ` [PATCH v6 7/9] drm/i915/vrr: Dump CMRR state in the crtc state dump Mitul Golani
2026-07-22 4:39 ` [PATCH v6 8/9] drm/i915/vrr: Program CMRR enable/disable from transcoder timings Mitul Golani
2026-07-23 16:21 ` Borah, Chaitanya Kumar
2026-07-28 5:46 ` Golani, Mitulkumar Ajitkumar
2026-07-22 4:39 ` [PATCH v6 9/9] drm/i915/vrr: Enable cmrr Mitul Golani
2026-07-23 16:21 ` Borah, Chaitanya Kumar
2026-07-24 9:50 ` Borah, Chaitanya Kumar
2026-07-28 11:14 ` Golani, Mitulkumar Ajitkumar
2026-07-22 4:58 ` ✓ CI.KUnit: success for Enable CMRR in fixed-RR VRR path (rev5) Patchwork
2026-07-22 5:32 ` ✓ Xe.CI.BAT: " Patchwork
2026-07-22 19:41 ` ✗ Xe.CI.FULL: failure " Patchwork
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