* [PATCH 0/4] Move RTP tables for engine init off the stack
@ 2026-06-16 19:21 Matt Roper
2026-06-16 19:21 ` [PATCH 1/4] drm/xe: Reformat xe_rtp_types.h Matt Roper
` (7 more replies)
0 siblings, 8 replies; 14+ messages in thread
From: Matt Roper @ 2026-06-16 19:21 UTC (permalink / raw)
To: intel-xe; +Cc: Gustavo Sousa, Violet Monti, Matt Roper
There are two RTP tables used during engine initialization that are
currently defined as stack variables inside of functions because they're
not truly constant tables and utilize other values calculated on the
functions' stacks. We'd like to make those tables truly constant and
pull them out of the function bodies. Doing so should make the code
more readable, avoid compiler warnings about stack size as these tables
grow over time, and potentially allow these tables to be tested with
kunit in the future.
Let's add a FIELD_SET_FUNC RTP action that acts similarly to FIELD_SET,
but indicates that the value to write should be determined during RTP
processing by calling the provided function pointer. FIELD_SET_FUNC can
be used with small static functions to calculate the cache control
values at runtime.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
Matt Roper (4):
drm/xe: Reformat xe_rtp_types.h
drm/xe/rtp: Add FIELD_SET_FUNC RTP action
drm/xe: Move engines' LRC programming RTP table off the stack
drm/xe: Move engines' non-LRC programming RTP table off the stack
drivers/gpu/drm/xe/xe_hw_engine.c | 218 ++++++++++++++++++++------------------
drivers/gpu/drm/xe/xe_rtp.c | 10 +-
drivers/gpu/drm/xe/xe_rtp.h | 21 ++++
drivers/gpu/drm/xe/xe_rtp_types.h | 33 ++++--
4 files changed, 169 insertions(+), 113 deletions(-)
---
base-commit: 0984dfdee2a4f9e1922fe919a6b469e115e23360
change-id: 20260615-rtp_with_dynamic_vals-f161965451af
Best regards,
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/4] drm/xe: Reformat xe_rtp_types.h
2026-06-16 19:21 [PATCH 0/4] Move RTP tables for engine init off the stack Matt Roper
@ 2026-06-16 19:21 ` Matt Roper
2026-06-16 22:09 ` Gustavo Sousa
2026-06-16 19:21 ` [PATCH 2/4] drm/xe/rtp: Add FIELD_SET_FUNC RTP action Matt Roper
` (6 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Matt Roper @ 2026-06-16 19:21 UTC (permalink / raw)
To: intel-xe; +Cc: Gustavo Sousa, Violet Monti, Matt Roper
Adjust whitespace / newlines in xe_rtp_types.h to make it easier to read
and more consistent with other files. No functional change.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_rtp_types.h | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
index 58018ae4f8cc..1d7c63d0ae94 100644
--- a/drivers/gpu/drm/xe/xe_rtp_types.h
+++ b/drivers/gpu/drm/xe/xe_rtp_types.h
@@ -22,20 +22,24 @@ struct xe_gt;
*/
struct xe_rtp_action {
/** @reg: Register */
- struct xe_reg reg;
+ struct xe_reg reg;
+
/**
* @clr_bits: bits to clear when updating register. It's always a
* superset of bits being modified
*/
- u32 clr_bits;
+ u32 clr_bits;
+
/** @set_bits: bits to set when updating register */
- u32 set_bits;
+ u32 set_bits;
+
#define XE_RTP_NOCHECK .read_mask = 0
/** @read_mask: mask for bits to consider when reading value back */
- u32 read_mask;
+ u32 read_mask;
+
#define XE_RTP_ACTION_FLAG_ENGINE_BASE BIT(0)
/** @flags: flags to apply on rule evaluation or action */
- u8 flags;
+ u8 flags;
};
enum {
@@ -69,6 +73,7 @@ struct xe_rtp_rule {
u8 platform;
u8 subplatform;
};
+
/*
* MATCH_GRAPHICS_VERSION / XE_RTP_MATCH_GRAPHICS_VERSION_RANGE /
* MATCH_MEDIA_VERSION / XE_RTP_MATCH_MEDIA_VERSION_RANGE
@@ -78,15 +83,18 @@ struct xe_rtp_rule {
#define XE_RTP_END_VERSION_UNDEFINED U32_MAX
u32 ver_end;
};
+
/* MATCH_STEP */
struct {
u8 step_start;
u8 step_end;
};
+
/* MATCH_ENGINE_CLASS / MATCH_NOT_ENGINE_CLASS */
struct {
u8 engine_class;
};
+
/* MATCH_FUNC */
bool (*match_func)(const struct xe_device *xe,
const struct xe_gt *gt,
--
2.54.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/4] drm/xe/rtp: Add FIELD_SET_FUNC RTP action
2026-06-16 19:21 [PATCH 0/4] Move RTP tables for engine init off the stack Matt Roper
2026-06-16 19:21 ` [PATCH 1/4] drm/xe: Reformat xe_rtp_types.h Matt Roper
@ 2026-06-16 19:21 ` Matt Roper
2026-06-16 22:22 ` Gustavo Sousa
2026-06-16 19:21 ` [PATCH 3/4] drm/xe: Move engines' LRC programming RTP table off the stack Matt Roper
` (5 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Matt Roper @ 2026-06-16 19:21 UTC (permalink / raw)
To: intel-xe; +Cc: Gustavo Sousa, Violet Monti, Matt Roper
Most of our RTP programming involves programming constant values into
register fields. However there are a few cases (e.g., RING_CMD_CCTL
programming) that rely on dynamic per-GT or per-engine checks to decide
what value will be programmed. Add a FIELD_SET_FUNC RTP action which
will call the provided function pointer once at RTP processing time to
determine the appropriate value.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_rtp.c | 10 ++++++++--
drivers/gpu/drm/xe/xe_rtp.h | 21 +++++++++++++++++++++
drivers/gpu/drm/xe/xe_rtp_types.h | 17 +++++++++++++++--
3 files changed, 44 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
index 83a40e1f9528..6a8d6ea68f25 100644
--- a/drivers/gpu/drm/xe/xe_rtp.c
+++ b/drivers/gpu/drm/xe/xe_rtp.c
@@ -227,17 +227,23 @@ static bool rule_matches(const struct xe_device *xe,
static void rtp_add_sr_entry(const struct xe_rtp_action *action,
struct xe_gt *gt,
+ struct xe_hw_engine *hwe,
u32 mmio_base,
struct xe_reg_sr *sr)
{
struct xe_reg_sr_entry sr_entry = {
.reg = action->reg,
.clr_bits = action->clr_bits,
- .set_bits = action->set_bits,
.read_mask = action->read_mask,
};
+ if (action->use_func)
+ sr_entry.set_bits = action->set_func(gt, hwe);
+ else
+ sr_entry.set_bits = action->set_bits;
+
sr_entry.reg.addr += mmio_base;
+
xe_reg_sr_add(sr, &sr_entry, gt);
}
@@ -259,7 +265,7 @@ static bool rtp_process_one_sr(const struct xe_rtp_entry_sr *entry,
else
mmio_base = 0;
- rtp_add_sr_entry(action, gt, mmio_base, sr);
+ rtp_add_sr_entry(action, gt, hwe, mmio_base, sr);
}
return true;
diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index 2cc65053cd07..e374b57a066c 100644
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -322,6 +322,27 @@ struct xe_reg_sr;
.clr_bits = (mask_bits_), .set_bits = (val_), \
.read_mask = 0, ##__VA_ARGS__ }
+/**
+ * XE_RTP_ACTION_FIELD_SET_FUNC: Set a bit range to the value returned by a function
+ * @reg_: Register
+ * @mask_bits_: Mask of bits to be changed in the register, forming a field
+ * @func_: Function that returns value to set in the field denoted by @mask_bits_
+ * @...: Additional fields to override in the struct xe_rtp_action entry
+ *
+ * @func_ will only be called a single time, when the RTP table is being
+ * processed. After processing, the value in the reg_sr entry is fixed and
+ * will not be re-evaluated.
+ *
+ * For masked registers this translates to a single write, while for other
+ * registers it's a RMW. The correspondent bspec notation is:
+ *
+ * REGNAME[<end>:<start>] = FUNC(GT, HWE)
+ */
+#define XE_RTP_ACTION_FIELD_SET_FUNC(reg_, mask_bits_, func_, ...) \
+ { .reg = XE_RTP_DROP_CAST(reg_), \
+ .clr_bits = mask_bits_, .set_func = func_, .use_func = 1, \
+ .read_mask = mask_bits_, ##__VA_ARGS__ }
+
/**
* XE_RTP_ACTION_WHITELIST - Add register to userspace whitelist
* @reg_: Register
diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
index 1d7c63d0ae94..b78092fa06e0 100644
--- a/drivers/gpu/drm/xe/xe_rtp_types.h
+++ b/drivers/gpu/drm/xe/xe_rtp_types.h
@@ -30,8 +30,14 @@ struct xe_rtp_action {
*/
u32 clr_bits;
- /** @set_bits: bits to set when updating register */
- u32 set_bits;
+ union {
+ /** @set_bits: bits to set when updating register */
+ u32 set_bits;
+
+ /** @set_func: function to provide bits to set when updating register */
+ u32 (*set_func)(struct xe_gt *gt,
+ struct xe_hw_engine *hwe);
+ };
#define XE_RTP_NOCHECK .read_mask = 0
/** @read_mask: mask for bits to consider when reading value back */
@@ -40,6 +46,13 @@ struct xe_rtp_action {
#define XE_RTP_ACTION_FLAG_ENGINE_BASE BIT(0)
/** @flags: flags to apply on rule evaluation or action */
u8 flags;
+
+ /**
+ * @use_func:
+ * Internal flag indicating @set_func should be called instead of
+ * using @set_bits.
+ */
+ u8 use_func:1;
};
enum {
--
2.54.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/4] drm/xe: Move engines' LRC programming RTP table off the stack
2026-06-16 19:21 [PATCH 0/4] Move RTP tables for engine init off the stack Matt Roper
2026-06-16 19:21 ` [PATCH 1/4] drm/xe: Reformat xe_rtp_types.h Matt Roper
2026-06-16 19:21 ` [PATCH 2/4] drm/xe/rtp: Add FIELD_SET_FUNC RTP action Matt Roper
@ 2026-06-16 19:21 ` Matt Roper
2026-06-16 19:54 ` Matt Roper
2026-06-16 19:21 ` [PATCH 4/4] drm/xe: Move engines' non-LRC " Matt Roper
` (4 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Matt Roper @ 2026-06-16 19:21 UTC (permalink / raw)
To: intel-xe; +Cc: Gustavo Sousa, Violet Monti, Matt Roper
The 'lrc_setup' RTP table was allocated on the stack because it wasn't
truly constant and needed to calculate the proper value for BLIT_CCTL at
runtime based on other stack variables. Using the FIELD_SET_FUNC action
allows us to make the table itself truly constant and move it off the
stack; the BLIT_CCTL value is now calculated during RTP table
processing.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_hw_engine.c | 60 ++++++++++++++++++++-------------------
1 file changed, 31 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 98265293f2dc..0b688b851b71 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -337,39 +337,41 @@ static bool xe_rtp_cfeg_wmtp_disabled(const struct xe_device *xe,
return xe_mmio_read32(&hwe->gt->mmio, XEHP_FUSE4) & CFEG_WMTP_DISABLE;
}
+static u32 blit_cctl_val(struct xe_gt *gt, struct xe_hw_engine *hwe)
+{
+ return REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, gt->mocs.uc_index) |
+ REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, gt->mocs.uc_index);
+}
+
+const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
+ /*
+ * Some blitter commands do not have a field for MOCS, those
+ * commands will use MOCS index pointed by BLIT_CCTL.
+ * BLIT_CCTL registers are needed to be programmed to un-cached.
+ */
+ { XE_RTP_NAME("BLIT_CCTL_default_MOCS"),
+ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
+ ENGINE_CLASS(COPY)),
+ XE_RTP_ACTIONS(FIELD_SET_FUNC(BLIT_CCTL(0),
+ BLIT_CCTL_DST_MOCS_MASK |
+ BLIT_CCTL_SRC_MOCS_MASK,
+ blit_cctl_val,
+ XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+ },
+ /* Disable WMTP if HW doesn't support it */
+ { XE_RTP_NAME("DISABLE_WMTP_ON_UNSUPPORTED_HW"),
+ XE_RTP_RULES(FUNC(xe_rtp_cfeg_wmtp_disabled)),
+ XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0),
+ PREEMPT_GPGPU_LEVEL_MASK,
+ PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
+ XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
+ },
+);
+
static void
hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
{
- struct xe_gt *gt = hwe->gt;
- const u8 mocs_write_idx = gt->mocs.uc_index;
- const u8 mocs_read_idx = gt->mocs.uc_index;
- u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) |
- REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx);
struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
- const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
- /*
- * Some blitter commands do not have a field for MOCS, those
- * commands will use MOCS index pointed by BLIT_CCTL.
- * BLIT_CCTL registers are needed to be programmed to un-cached.
- */
- { XE_RTP_NAME("BLIT_CCTL_default_MOCS"),
- XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
- ENGINE_CLASS(COPY)),
- XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0),
- BLIT_CCTL_DST_MOCS_MASK |
- BLIT_CCTL_SRC_MOCS_MASK,
- blit_cctl_val,
- XE_RTP_ACTION_FLAG(ENGINE_BASE)))
- },
- /* Disable WMTP if HW doesn't support it */
- { XE_RTP_NAME("DISABLE_WMTP_ON_UNSUPPORTED_HW"),
- XE_RTP_RULES(FUNC(xe_rtp_cfeg_wmtp_disabled)),
- XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0),
- PREEMPT_GPGPU_LEVEL_MASK,
- PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
- XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
- },
- );
xe_rtp_process_to_sr(&ctx, &lrc_setup, &hwe->reg_lrc, true);
}
--
2.54.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/4] drm/xe: Move engines' non-LRC programming RTP table off the stack
2026-06-16 19:21 [PATCH 0/4] Move RTP tables for engine init off the stack Matt Roper
` (2 preceding siblings ...)
2026-06-16 19:21 ` [PATCH 3/4] drm/xe: Move engines' LRC programming RTP table off the stack Matt Roper
@ 2026-06-16 19:21 ` Matt Roper
2026-06-16 22:33 ` Gustavo Sousa
2026-06-16 19:28 ` ✗ CI.checkpatch: warning for Move RTP tables for engine init " Patchwork
` (3 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Matt Roper @ 2026-06-16 19:21 UTC (permalink / raw)
To: intel-xe; +Cc: Gustavo Sousa, Violet Monti, Matt Roper
The 'engine_sr' RTP table was allocated on the stack because it wasn't
truly constant and needed to calculate the proper value for
RING_CMD_CCTL at runtime based on other stack variables. Using the
FIELD_SET_FUNC action allows us to make the table itself truly constant
and move it off the stack; the RING_CMD_CCTL value is now calculated
during RTP table processing.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_hw_engine.c | 158 ++++++++++++++++++++------------------
1 file changed, 82 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 0b688b851b71..987cd1a49f03 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -387,86 +387,92 @@ void xe_hw_engine_setup_reg_lrc(struct xe_hw_engine *hwe)
xe_tuning_process_lrc(hwe);
}
+/*
+ * RING_CMD_CCTL specifies the default MOCS entry that will be
+ * used by the command streamer when executing commands that
+ * don't have a way to explicitly specify a MOCS setting.
+ * The default should usually reference whichever MOCS entry
+ * corresponds to uncached behavior, although use of a WB cached
+ * entry is recommended by the spec in certain circumstances on
+ * specific platforms.
+ * Bspec: 72161
+ */
+static u32 ring_cmd_cctl_val(struct xe_gt *gt, struct xe_hw_engine *hwe)
+{
+ struct xe_device *xe = gt_to_xe(gt);
+ u8 mocs_read_idx = gt->mocs.uc_index;
+
+ if (hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) &&
+ (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC))
+ mocs_read_idx = gt->mocs.wb_index;
+
+ return REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, gt->mocs.uc_index) |
+ REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);
+}
+
+const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR(
+ { XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"),
+ XE_RTP_RULES(FUNC(xe_rtp_match_always)),
+ XE_RTP_ACTIONS(FIELD_SET_FUNC(RING_CMD_CCTL(0),
+ CMD_CCTL_WRITE_OVERRIDE_MASK |
+ CMD_CCTL_READ_OVERRIDE_MASK,
+ ring_cmd_cctl_val,
+ XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+ },
+ { XE_RTP_NAME("Disable HW status page updates for interrupts"),
+ XE_RTP_RULES(FUNC(xe_rtp_match_always)),
+ XE_RTP_ACTIONS(SET(RING_HWSTAM(0), ~0x0,
+ XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+ },
+ { XE_RTP_NAME("Disable engine 'legacy' mode"),
+ XE_RTP_RULES(FUNC(xe_rtp_match_always)),
+ XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_DISABLE_LEGACY_MODE,
+ XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+ },
+ /*
+ * To allow the GSC engine to go idle on MTL we need to enable
+ * idle messaging and set the hysteresis value (we use 0xA=5us
+ * as recommended in spec). On platforms after MTL this is
+ * enabled by default.
+ */
+ { XE_RTP_NAME("MTL GSCCS IDLE MSG enable"),
+ XE_RTP_RULES(MEDIA_VERSION(1300), ENGINE_CLASS(OTHER)),
+ XE_RTP_ACTIONS(CLR(RING_PSMI_CTL(0),
+ IDLE_MSG_DISABLE,
+ XE_RTP_ACTION_FLAG(ENGINE_BASE)),
+ FIELD_SET(RING_PWRCTX_MAXCNT(0),
+ IDLE_WAIT_TIME,
+ 0xA,
+ XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+ },
+ /* Enable Priority Mem Read */
+ { XE_RTP_NAME("Priority_Mem_Read"),
+ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+ XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ,
+ XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+ },
+ { XE_RTP_NAME("Enable CCS Engine(s)"),
+ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, XE_RTP_END_VERSION_UNDEFINED),
+ FUNC(xe_rtp_match_first_render_or_compute)),
+ XE_RTP_ACTIONS(SET(RCU_MODE, RCU_MODE_CCS_ENABLE))
+ },
+ /* Use Fixed slice CCS mode */
+ { XE_RTP_NAME("RCU_MODE_FIXED_SLICE_CCS_MODE"),
+ XE_RTP_RULES(FUNC(xe_hw_engine_match_fixed_cslice_mode)),
+ XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE,
+ RCU_MODE_FIXED_SLICE_CCS_MODE))
+ },
+ { XE_RTP_NAME("Enable MSI-X interrupt support"),
+ XE_RTP_RULES(FUNC(xe_rtp_match_has_msix)),
+ XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE,
+ XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+ },
+);
+
static void
hw_engine_setup_default_state(struct xe_hw_engine *hwe)
{
- struct xe_gt *gt = hwe->gt;
- struct xe_device *xe = gt_to_xe(gt);
- /*
- * RING_CMD_CCTL specifies the default MOCS entry that will be
- * used by the command streamer when executing commands that
- * don't have a way to explicitly specify a MOCS setting.
- * The default should usually reference whichever MOCS entry
- * corresponds to uncached behavior, although use of a WB cached
- * entry is recommended by the spec in certain circumstances on
- * specific platforms.
- * Bspec: 72161
- */
- const u8 mocs_write_idx = gt->mocs.uc_index;
- const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) &&
- (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) ?
- gt->mocs.wb_index : gt->mocs.uc_index;
- u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |
- REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);
struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
- const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR(
- { XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"),
- XE_RTP_RULES(FUNC(xe_rtp_match_always)),
- XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0),
- CMD_CCTL_WRITE_OVERRIDE_MASK |
- CMD_CCTL_READ_OVERRIDE_MASK,
- ring_cmd_cctl_val,
- XE_RTP_ACTION_FLAG(ENGINE_BASE)))
- },
- { XE_RTP_NAME("Disable HW status page updates for interrupts"),
- XE_RTP_RULES(FUNC(xe_rtp_match_always)),
- XE_RTP_ACTIONS(SET(RING_HWSTAM(0), ~0x0,
- XE_RTP_ACTION_FLAG(ENGINE_BASE)))
- },
- { XE_RTP_NAME("Disable engine 'legacy' mode"),
- XE_RTP_RULES(FUNC(xe_rtp_match_always)),
- XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_DISABLE_LEGACY_MODE,
- XE_RTP_ACTION_FLAG(ENGINE_BASE)))
- },
- /*
- * To allow the GSC engine to go idle on MTL we need to enable
- * idle messaging and set the hysteresis value (we use 0xA=5us
- * as recommended in spec). On platforms after MTL this is
- * enabled by default.
- */
- { XE_RTP_NAME("MTL GSCCS IDLE MSG enable"),
- XE_RTP_RULES(MEDIA_VERSION(1300), ENGINE_CLASS(OTHER)),
- XE_RTP_ACTIONS(CLR(RING_PSMI_CTL(0),
- IDLE_MSG_DISABLE,
- XE_RTP_ACTION_FLAG(ENGINE_BASE)),
- FIELD_SET(RING_PWRCTX_MAXCNT(0),
- IDLE_WAIT_TIME,
- 0xA,
- XE_RTP_ACTION_FLAG(ENGINE_BASE)))
- },
- /* Enable Priority Mem Read */
- { XE_RTP_NAME("Priority_Mem_Read"),
- XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
- XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ,
- XE_RTP_ACTION_FLAG(ENGINE_BASE)))
- },
- { XE_RTP_NAME("Enable CCS Engine(s)"),
- XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, XE_RTP_END_VERSION_UNDEFINED),
- FUNC(xe_rtp_match_first_render_or_compute)),
- XE_RTP_ACTIONS(SET(RCU_MODE, RCU_MODE_CCS_ENABLE))
- },
- /* Use Fixed slice CCS mode */
- { XE_RTP_NAME("RCU_MODE_FIXED_SLICE_CCS_MODE"),
- XE_RTP_RULES(FUNC(xe_hw_engine_match_fixed_cslice_mode)),
- XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE,
- RCU_MODE_FIXED_SLICE_CCS_MODE))
- },
- { XE_RTP_NAME("Enable MSI-X interrupt support"),
- XE_RTP_RULES(FUNC(xe_rtp_match_has_msix)),
- XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE,
- XE_RTP_ACTION_FLAG(ENGINE_BASE)))
- },
- );
xe_rtp_process_to_sr(&ctx, &engine_sr, &hwe->reg_sr, false);
}
--
2.54.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✗ CI.checkpatch: warning for Move RTP tables for engine init off the stack
2026-06-16 19:21 [PATCH 0/4] Move RTP tables for engine init off the stack Matt Roper
` (3 preceding siblings ...)
2026-06-16 19:21 ` [PATCH 4/4] drm/xe: Move engines' non-LRC " Matt Roper
@ 2026-06-16 19:28 ` Patchwork
2026-06-16 19:29 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-06-16 19:28 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
== Series Details ==
Series: Move RTP tables for engine init off the stack
URL : https://patchwork.freedesktop.org/series/168630/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 18d1c9c0683f6d5df4a3ee17cbf77b324fcc993d
Author: Matt Roper <matthew.d.roper@intel.com>
Date: Tue Jun 16 12:21:54 2026 -0700
drm/xe: Move engines' non-LRC programming RTP table off the stack
The 'engine_sr' RTP table was allocated on the stack because it wasn't
truly constant and needed to calculate the proper value for
RING_CMD_CCTL at runtime based on other stack variables. Using the
FIELD_SET_FUNC action allows us to make the table itself truly constant
and move it off the stack; the RING_CMD_CCTL value is now calculated
during RTP table processing.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
+ /mt/dim checkpatch 5447491819dcc3d10fd362c7bfbf877d343f6526 drm-intel
8a66b5239ac3 drm/xe: Reformat xe_rtp_types.h
048a8175cff2 drm/xe/rtp: Add FIELD_SET_FUNC RTP action
-:77: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask_bits_' - possible side-effects?
#77: FILE: drivers/gpu/drm/xe/xe_rtp.h:341:
+#define XE_RTP_ACTION_FIELD_SET_FUNC(reg_, mask_bits_, func_, ...) \
+ { .reg = XE_RTP_DROP_CAST(reg_), \
+ .clr_bits = mask_bits_, .set_func = func_, .use_func = 1, \
+ .read_mask = mask_bits_, ##__VA_ARGS__ }
total: 0 errors, 0 warnings, 1 checks, 88 lines checked
0935091f0103 drm/xe: Move engines' LRC programming RTP table off the stack
-:29: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#29: FILE: drivers/gpu/drm/xe/xe_hw_engine.c:346:
+const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
total: 0 errors, 0 warnings, 1 checks, 70 lines checked
18d1c9c0683f drm/xe: Move engines' non-LRC programming RTP table off the stack
-:50: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#50: FILE: drivers/gpu/drm/xe/xe_hw_engine.c:413:
+const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR(
total: 0 errors, 0 warnings, 1 checks, 167 lines checked
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ CI.KUnit: success for Move RTP tables for engine init off the stack
2026-06-16 19:21 [PATCH 0/4] Move RTP tables for engine init off the stack Matt Roper
` (4 preceding siblings ...)
2026-06-16 19:28 ` ✗ CI.checkpatch: warning for Move RTP tables for engine init " Patchwork
@ 2026-06-16 19:29 ` Patchwork
2026-06-16 20:19 ` ✓ Xe.CI.BAT: " Patchwork
2026-06-17 0:31 ` ✓ Xe.CI.FULL: " Patchwork
7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-06-16 19:29 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
== Series Details ==
Series: Move RTP tables for engine init off the stack
URL : https://patchwork.freedesktop.org/series/168630/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[19:28:01] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:28:05] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:28:36] Starting KUnit Kernel (1/1)...
[19:28:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:28:36] ================== guc_buf (11 subtests) ===================
[19:28:36] [PASSED] test_smallest
[19:28:36] [PASSED] test_largest
[19:28:36] [PASSED] test_granular
[19:28:36] [PASSED] test_unique
[19:28:36] [PASSED] test_overlap
[19:28:36] [PASSED] test_reusable
[19:28:36] [PASSED] test_too_big
[19:28:36] [PASSED] test_flush
[19:28:36] [PASSED] test_lookup
[19:28:36] [PASSED] test_data
[19:28:36] [PASSED] test_class
[19:28:36] ===================== [PASSED] guc_buf =====================
[19:28:36] =================== guc_dbm (7 subtests) ===================
[19:28:36] [PASSED] test_empty
[19:28:36] [PASSED] test_default
[19:28:36] ======================== test_size ========================
[19:28:36] [PASSED] 4
[19:28:36] [PASSED] 8
[19:28:36] [PASSED] 32
[19:28:36] [PASSED] 256
[19:28:36] ==================== [PASSED] test_size ====================
[19:28:36] ======================= test_reuse ========================
[19:28:36] [PASSED] 4
[19:28:36] [PASSED] 8
[19:28:36] [PASSED] 32
[19:28:36] [PASSED] 256
[19:28:36] =================== [PASSED] test_reuse ====================
[19:28:36] =================== test_range_overlap ====================
[19:28:36] [PASSED] 4
[19:28:36] [PASSED] 8
[19:28:36] [PASSED] 32
[19:28:36] [PASSED] 256
[19:28:36] =============== [PASSED] test_range_overlap ================
[19:28:36] =================== test_range_compact ====================
[19:28:36] [PASSED] 4
[19:28:36] [PASSED] 8
[19:28:36] [PASSED] 32
[19:28:36] [PASSED] 256
[19:28:36] =============== [PASSED] test_range_compact ================
[19:28:36] ==================== test_range_spare =====================
[19:28:36] [PASSED] 4
[19:28:36] [PASSED] 8
[19:28:36] [PASSED] 32
[19:28:36] [PASSED] 256
[19:28:36] ================ [PASSED] test_range_spare =================
[19:28:36] ===================== [PASSED] guc_dbm =====================
[19:28:36] =================== guc_idm (6 subtests) ===================
[19:28:36] [PASSED] bad_init
[19:28:36] [PASSED] no_init
[19:28:36] [PASSED] init_fini
[19:28:36] [PASSED] check_used
[19:28:37] [PASSED] check_quota
[19:28:37] [PASSED] check_all
[19:28:37] ===================== [PASSED] guc_idm =====================
[19:28:37] ================== no_relay (3 subtests) ===================
[19:28:37] [PASSED] xe_drops_guc2pf_if_not_ready
[19:28:37] [PASSED] xe_drops_guc2vf_if_not_ready
[19:28:37] [PASSED] xe_rejects_send_if_not_ready
[19:28:37] ==================== [PASSED] no_relay =====================
[19:28:37] ================== pf_relay (14 subtests) ==================
[19:28:37] [PASSED] pf_rejects_guc2pf_too_short
[19:28:37] [PASSED] pf_rejects_guc2pf_too_long
[19:28:37] [PASSED] pf_rejects_guc2pf_no_payload
[19:28:37] [PASSED] pf_fails_no_payload
[19:28:37] [PASSED] pf_fails_bad_origin
[19:28:37] [PASSED] pf_fails_bad_type
[19:28:37] [PASSED] pf_txn_reports_error
[19:28:37] [PASSED] pf_txn_sends_pf2guc
[19:28:37] [PASSED] pf_sends_pf2guc
[19:28:37] [SKIPPED] pf_loopback_nop
[19:28:37] [SKIPPED] pf_loopback_echo
[19:28:37] [SKIPPED] pf_loopback_fail
[19:28:37] [SKIPPED] pf_loopback_busy
[19:28:37] [SKIPPED] pf_loopback_retry
[19:28:37] ==================== [PASSED] pf_relay =====================
[19:28:37] ================== vf_relay (3 subtests) ===================
[19:28:37] [PASSED] vf_rejects_guc2vf_too_short
[19:28:37] [PASSED] vf_rejects_guc2vf_too_long
[19:28:37] [PASSED] vf_rejects_guc2vf_no_payload
[19:28:37] ==================== [PASSED] vf_relay =====================
[19:28:37] ================ pf_gt_config (9 subtests) =================
[19:28:37] [PASSED] fair_contexts_1vf
[19:28:37] [PASSED] fair_doorbells_1vf
[19:28:37] [PASSED] fair_ggtt_1vf
[19:28:37] ====================== fair_vram_1vf ======================
[19:28:37] [PASSED] 3.50 GiB
[19:28:37] [PASSED] 11.5 GiB
[19:28:37] [PASSED] 15.5 GiB
[19:28:37] [PASSED] 31.5 GiB
[19:28:37] [PASSED] 63.5 GiB
[19:28:37] [PASSED] 1.91 GiB
[19:28:37] ================== [PASSED] fair_vram_1vf ==================
[19:28:37] ================ fair_vram_1vf_admin_only =================
[19:28:37] [PASSED] 3.50 GiB
[19:28:37] [PASSED] 11.5 GiB
[19:28:37] [PASSED] 15.5 GiB
[19:28:37] [PASSED] 31.5 GiB
[19:28:37] [PASSED] 63.5 GiB
[19:28:37] [PASSED] 1.91 GiB
[19:28:37] ============ [PASSED] fair_vram_1vf_admin_only =============
[19:28:37] ====================== fair_contexts ======================
[19:28:37] [PASSED] 1 VF
[19:28:37] [PASSED] 2 VFs
[19:28:37] [PASSED] 3 VFs
[19:28:37] [PASSED] 4 VFs
[19:28:37] [PASSED] 5 VFs
[19:28:37] [PASSED] 6 VFs
[19:28:37] [PASSED] 7 VFs
[19:28:37] [PASSED] 8 VFs
[19:28:37] [PASSED] 9 VFs
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[19:28:37] [PASSED] 12 VFs
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[19:28:37] [PASSED] 15 VFs
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[19:28:37] [PASSED] 35 VFs
[19:28:37] [PASSED] 36 VFs
[19:28:37] [PASSED] 37 VFs
[19:28:37] [PASSED] 38 VFs
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[19:28:37] [PASSED] 44 VFs
[19:28:37] [PASSED] 45 VFs
[19:28:37] [PASSED] 46 VFs
[19:28:37] [PASSED] 47 VFs
[19:28:37] [PASSED] 48 VFs
[19:28:37] [PASSED] 49 VFs
[19:28:37] [PASSED] 50 VFs
[19:28:37] [PASSED] 51 VFs
[19:28:37] [PASSED] 52 VFs
[19:28:37] [PASSED] 53 VFs
[19:28:37] [PASSED] 54 VFs
[19:28:37] [PASSED] 55 VFs
[19:28:37] [PASSED] 56 VFs
[19:28:37] [PASSED] 57 VFs
[19:28:37] [PASSED] 58 VFs
[19:28:37] [PASSED] 59 VFs
[19:28:37] [PASSED] 60 VFs
[19:28:37] [PASSED] 61 VFs
[19:28:37] [PASSED] 62 VFs
[19:28:37] [PASSED] 63 VFs
[19:28:37] ================== [PASSED] fair_contexts ==================
[19:28:37] ===================== fair_doorbells ======================
[19:28:37] [PASSED] 1 VF
[19:28:37] [PASSED] 2 VFs
[19:28:37] [PASSED] 3 VFs
[19:28:37] [PASSED] 4 VFs
[19:28:37] [PASSED] 5 VFs
[19:28:37] [PASSED] 6 VFs
[19:28:37] [PASSED] 7 VFs
[19:28:37] [PASSED] 8 VFs
[19:28:37] [PASSED] 9 VFs
[19:28:37] [PASSED] 10 VFs
[19:28:37] [PASSED] 11 VFs
[19:28:37] [PASSED] 12 VFs
[19:28:37] [PASSED] 13 VFs
[19:28:37] [PASSED] 14 VFs
[19:28:37] [PASSED] 15 VFs
[19:28:37] [PASSED] 16 VFs
[19:28:37] [PASSED] 17 VFs
[19:28:37] [PASSED] 18 VFs
[19:28:37] [PASSED] 19 VFs
[19:28:37] [PASSED] 20 VFs
[19:28:37] [PASSED] 21 VFs
[19:28:37] [PASSED] 22 VFs
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[19:28:37] [PASSED] 24 VFs
[19:28:37] [PASSED] 25 VFs
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[19:28:37] [PASSED] 27 VFs
[19:28:37] [PASSED] 28 VFs
[19:28:37] [PASSED] 29 VFs
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[19:28:37] [PASSED] 33 VFs
[19:28:37] [PASSED] 34 VFs
[19:28:37] [PASSED] 35 VFs
[19:28:37] [PASSED] 36 VFs
[19:28:37] [PASSED] 37 VFs
[19:28:37] [PASSED] 38 VFs
[19:28:37] [PASSED] 39 VFs
[19:28:37] [PASSED] 40 VFs
[19:28:37] [PASSED] 41 VFs
[19:28:37] [PASSED] 42 VFs
[19:28:37] [PASSED] 43 VFs
[19:28:37] [PASSED] 44 VFs
[19:28:37] [PASSED] 45 VFs
[19:28:37] [PASSED] 46 VFs
[19:28:37] [PASSED] 47 VFs
[19:28:37] [PASSED] 48 VFs
[19:28:37] [PASSED] 49 VFs
[19:28:37] [PASSED] 50 VFs
[19:28:37] [PASSED] 51 VFs
[19:28:37] [PASSED] 52 VFs
[19:28:37] [PASSED] 53 VFs
[19:28:37] [PASSED] 54 VFs
[19:28:37] [PASSED] 55 VFs
[19:28:37] [PASSED] 56 VFs
[19:28:37] [PASSED] 57 VFs
[19:28:37] [PASSED] 58 VFs
[19:28:37] [PASSED] 59 VFs
[19:28:37] [PASSED] 60 VFs
[19:28:37] [PASSED] 61 VFs
[19:28:37] [PASSED] 62 VFs
[19:28:37] [PASSED] 63 VFs
[19:28:37] ================= [PASSED] fair_doorbells ==================
[19:28:37] ======================== fair_ggtt ========================
[19:28:37] [PASSED] 1 VF
[19:28:37] [PASSED] 2 VFs
[19:28:37] [PASSED] 3 VFs
[19:28:37] [PASSED] 4 VFs
[19:28:37] [PASSED] 5 VFs
[19:28:37] [PASSED] 6 VFs
[19:28:37] [PASSED] 7 VFs
[19:28:37] [PASSED] 8 VFs
[19:28:37] [PASSED] 9 VFs
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[19:28:37] [PASSED] 11 VFs
[19:28:37] [PASSED] 12 VFs
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[19:28:37] [PASSED] 19 VFs
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[19:28:37] [PASSED] 33 VFs
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[19:28:37] [PASSED] 35 VFs
[19:28:37] [PASSED] 36 VFs
[19:28:37] [PASSED] 37 VFs
[19:28:37] [PASSED] 38 VFs
[19:28:37] [PASSED] 39 VFs
[19:28:37] [PASSED] 40 VFs
[19:28:37] [PASSED] 41 VFs
[19:28:37] [PASSED] 42 VFs
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[19:28:37] [PASSED] 44 VFs
[19:28:37] [PASSED] 45 VFs
[19:28:37] [PASSED] 46 VFs
[19:28:37] [PASSED] 47 VFs
[19:28:37] [PASSED] 48 VFs
[19:28:37] [PASSED] 49 VFs
[19:28:37] [PASSED] 50 VFs
[19:28:37] [PASSED] 51 VFs
[19:28:37] [PASSED] 52 VFs
[19:28:37] [PASSED] 53 VFs
[19:28:37] [PASSED] 54 VFs
[19:28:37] [PASSED] 55 VFs
[19:28:37] [PASSED] 56 VFs
[19:28:37] [PASSED] 57 VFs
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[19:28:37] [PASSED] 59 VFs
[19:28:37] [PASSED] 60 VFs
[19:28:37] [PASSED] 61 VFs
[19:28:37] [PASSED] 62 VFs
[19:28:37] [PASSED] 63 VFs
[19:28:37] ==================== [PASSED] fair_ggtt ====================
[19:28:37] ======================== fair_vram ========================
[19:28:37] [PASSED] 1 VF
[19:28:37] [PASSED] 2 VFs
[19:28:37] [PASSED] 3 VFs
[19:28:37] [PASSED] 4 VFs
[19:28:37] [PASSED] 5 VFs
[19:28:37] [PASSED] 6 VFs
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[19:28:37] [PASSED] 9 VFs
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[19:28:37] [PASSED] 36 VFs
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[19:28:37] [PASSED] 38 VFs
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[19:28:37] [PASSED] 46 VFs
[19:28:37] [PASSED] 47 VFs
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[19:28:37] [PASSED] 49 VFs
[19:28:37] [PASSED] 50 VFs
[19:28:37] [PASSED] 51 VFs
[19:28:37] [PASSED] 52 VFs
[19:28:37] [PASSED] 53 VFs
[19:28:37] [PASSED] 54 VFs
[19:28:37] [PASSED] 55 VFs
[19:28:37] [PASSED] 56 VFs
[19:28:37] [PASSED] 57 VFs
[19:28:37] [PASSED] 58 VFs
[19:28:37] [PASSED] 59 VFs
[19:28:37] [PASSED] 60 VFs
[19:28:37] [PASSED] 61 VFs
[19:28:37] [PASSED] 62 VFs
[19:28:37] [PASSED] 63 VFs
[19:28:37] ==================== [PASSED] fair_vram ====================
[19:28:37] ================== [PASSED] pf_gt_config ===================
[19:28:37] ===================== lmtt (1 subtest) =====================
[19:28:37] ======================== test_ops =========================
[19:28:37] [PASSED] 2-level
[19:28:37] [PASSED] multi-level
[19:28:37] ==================== [PASSED] test_ops =====================
[19:28:37] ====================== [PASSED] lmtt =======================
[19:28:37] ================= pf_service (11 subtests) =================
[19:28:37] [PASSED] pf_negotiate_any
[19:28:37] [PASSED] pf_negotiate_base_match
[19:28:37] [PASSED] pf_negotiate_base_newer
[19:28:37] [PASSED] pf_negotiate_base_next
[19:28:37] [SKIPPED] pf_negotiate_base_older
[19:28:37] [PASSED] pf_negotiate_base_prev
[19:28:37] [PASSED] pf_negotiate_latest_match
[19:28:37] [PASSED] pf_negotiate_latest_newer
[19:28:37] [PASSED] pf_negotiate_latest_next
[19:28:37] [SKIPPED] pf_negotiate_latest_older
[19:28:37] [SKIPPED] pf_negotiate_latest_prev
[19:28:37] =================== [PASSED] pf_service ====================
[19:28:37] ================= xe_guc_g2g (2 subtests) ==================
[19:28:37] ============== xe_live_guc_g2g_kunit_default ==============
[19:28:37] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[19:28:37] ============== xe_live_guc_g2g_kunit_allmem ===============
[19:28:37] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[19:28:37] =================== [SKIPPED] xe_guc_g2g ===================
[19:28:37] =================== xe_mocs (2 subtests) ===================
[19:28:37] ================ xe_live_mocs_kernel_kunit ================
[19:28:37] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[19:28:37] ================ xe_live_mocs_reset_kunit =================
[19:28:37] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[19:28:37] ==================== [SKIPPED] xe_mocs =====================
[19:28:37] ================= xe_migrate (2 subtests) ==================
[19:28:37] ================= xe_migrate_sanity_kunit =================
[19:28:37] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[19:28:37] ================== xe_validate_ccs_kunit ==================
[19:28:37] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[19:28:37] =================== [SKIPPED] xe_migrate ===================
[19:28:37] ================== xe_dma_buf (1 subtest) ==================
[19:28:37] ==================== xe_dma_buf_kunit =====================
[19:28:37] ================ [SKIPPED] xe_dma_buf_kunit ================
[19:28:37] =================== [SKIPPED] xe_dma_buf ===================
[19:28:37] ================= xe_bo_shrink (1 subtest) =================
[19:28:37] =================== xe_bo_shrink_kunit ====================
[19:28:37] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[19:28:37] ================== [SKIPPED] xe_bo_shrink ==================
[19:28:37] ==================== xe_bo (2 subtests) ====================
[19:28:37] ================== xe_ccs_migrate_kunit ===================
[19:28:37] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[19:28:37] ==================== xe_bo_evict_kunit ====================
[19:28:37] =============== [SKIPPED] xe_bo_evict_kunit ================
[19:28:37] ===================== [SKIPPED] xe_bo ======================
[19:28:37] ==================== args (13 subtests) ====================
[19:28:37] [PASSED] count_args_test
[19:28:37] [PASSED] call_args_example
[19:28:37] [PASSED] call_args_test
[19:28:37] [PASSED] drop_first_arg_example
[19:28:37] [PASSED] drop_first_arg_test
[19:28:37] [PASSED] first_arg_example
[19:28:37] [PASSED] first_arg_test
[19:28:37] [PASSED] last_arg_example
[19:28:37] [PASSED] last_arg_test
[19:28:37] [PASSED] pick_arg_example
[19:28:37] [PASSED] if_args_example
[19:28:37] [PASSED] if_args_test
[19:28:37] [PASSED] sep_comma_example
[19:28:37] ====================== [PASSED] args =======================
[19:28:37] =================== xe_pci (3 subtests) ====================
[19:28:37] ==================== check_graphics_ip ====================
[19:28:37] [PASSED] 12.00 Xe_LP
[19:28:37] [PASSED] 12.10 Xe_LP+
[19:28:37] [PASSED] 12.55 Xe_HPG
[19:28:37] [PASSED] 12.60 Xe_HPC
[19:28:37] [PASSED] 12.70 Xe_LPG
[19:28:37] [PASSED] 12.71 Xe_LPG
[19:28:37] [PASSED] 12.74 Xe_LPG+
[19:28:37] [PASSED] 20.01 Xe2_HPG
[19:28:37] [PASSED] 20.02 Xe2_HPG
[19:28:37] [PASSED] 20.04 Xe2_LPG
[19:28:37] [PASSED] 30.00 Xe3_LPG
[19:28:37] [PASSED] 30.01 Xe3_LPG
[19:28:37] [PASSED] 30.03 Xe3_LPG
[19:28:37] [PASSED] 30.04 Xe3_LPG
[19:28:37] [PASSED] 30.05 Xe3_LPG
[19:28:37] [PASSED] 35.10 Xe3p_LPG
[19:28:37] [PASSED] 35.11 Xe3p_XPC
[19:28:37] ================ [PASSED] check_graphics_ip ================
[19:28:37] ===================== check_media_ip ======================
[19:28:37] [PASSED] 12.00 Xe_M
[19:28:37] [PASSED] 12.55 Xe_HPM
[19:28:37] [PASSED] 13.00 Xe_LPM+
[19:28:37] [PASSED] 13.01 Xe2_HPM
[19:28:37] [PASSED] 20.00 Xe2_LPM
[19:28:37] [PASSED] 30.00 Xe3_LPM
[19:28:37] [PASSED] 30.02 Xe3_LPM
[19:28:37] [PASSED] 35.00 Xe3p_LPM
[19:28:37] [PASSED] 35.03 Xe3p_HPM
[19:28:37] ================= [PASSED] check_media_ip ==================
[19:28:37] =================== check_platform_desc ===================
[19:28:37] [PASSED] 0x9A60 (TIGERLAKE)
[19:28:37] [PASSED] 0x9A68 (TIGERLAKE)
[19:28:37] [PASSED] 0x9A70 (TIGERLAKE)
[19:28:37] [PASSED] 0x9A40 (TIGERLAKE)
[19:28:37] [PASSED] 0x9A49 (TIGERLAKE)
[19:28:37] [PASSED] 0x9A59 (TIGERLAKE)
[19:28:37] [PASSED] 0x9A78 (TIGERLAKE)
[19:28:37] [PASSED] 0x9AC0 (TIGERLAKE)
[19:28:37] [PASSED] 0x9AC9 (TIGERLAKE)
[19:28:37] [PASSED] 0x9AD9 (TIGERLAKE)
[19:28:37] [PASSED] 0x9AF8 (TIGERLAKE)
[19:28:37] [PASSED] 0x4C80 (ROCKETLAKE)
[19:28:37] [PASSED] 0x4C8A (ROCKETLAKE)
[19:28:37] [PASSED] 0x4C8B (ROCKETLAKE)
[19:28:37] [PASSED] 0x4C8C (ROCKETLAKE)
[19:28:37] [PASSED] 0x4C90 (ROCKETLAKE)
[19:28:37] [PASSED] 0x4C9A (ROCKETLAKE)
[19:28:37] [PASSED] 0x4680 (ALDERLAKE_S)
[19:28:37] [PASSED] 0x4682 (ALDERLAKE_S)
[19:28:37] [PASSED] 0x4688 (ALDERLAKE_S)
[19:28:37] [PASSED] 0x468A (ALDERLAKE_S)
[19:28:37] [PASSED] 0x468B (ALDERLAKE_S)
[19:28:37] [PASSED] 0x4690 (ALDERLAKE_S)
[19:28:37] [PASSED] 0x4692 (ALDERLAKE_S)
[19:28:37] [PASSED] 0x4693 (ALDERLAKE_S)
[19:28:37] [PASSED] 0x46A0 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x46A1 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x46A2 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x46A3 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x46A6 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x46A8 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x46AA (ALDERLAKE_P)
[19:28:37] [PASSED] 0x462A (ALDERLAKE_P)
[19:28:37] [PASSED] 0x4626 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x4628 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x46B0 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x46B1 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x46B2 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x46B3 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x46C0 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x46C1 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x46C2 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x46C3 (ALDERLAKE_P)
[19:28:37] [PASSED] 0x46D0 (ALDERLAKE_N)
[19:28:37] [PASSED] 0x46D1 (ALDERLAKE_N)
[19:28:37] [PASSED] 0x46D2 (ALDERLAKE_N)
[19:28:37] [PASSED] 0x46D3 (ALDERLAKE_N)
[19:28:37] [PASSED] 0x46D4 (ALDERLAKE_N)
[19:28:37] [PASSED] 0xA721 (ALDERLAKE_P)
[19:28:37] [PASSED] 0xA7A1 (ALDERLAKE_P)
[19:28:37] [PASSED] 0xA7A9 (ALDERLAKE_P)
[19:28:37] [PASSED] 0xA7AC (ALDERLAKE_P)
[19:28:37] [PASSED] 0xA7AD (ALDERLAKE_P)
[19:28:37] [PASSED] 0xA720 (ALDERLAKE_P)
[19:28:37] [PASSED] 0xA7A0 (ALDERLAKE_P)
[19:28:37] [PASSED] 0xA7A8 (ALDERLAKE_P)
[19:28:37] [PASSED] 0xA7AA (ALDERLAKE_P)
[19:28:37] [PASSED] 0xA7AB (ALDERLAKE_P)
[19:28:37] [PASSED] 0xA780 (ALDERLAKE_S)
[19:28:37] [PASSED] 0xA781 (ALDERLAKE_S)
[19:28:37] [PASSED] 0xA782 (ALDERLAKE_S)
[19:28:37] [PASSED] 0xA783 (ALDERLAKE_S)
[19:28:37] [PASSED] 0xA788 (ALDERLAKE_S)
[19:28:37] [PASSED] 0xA789 (ALDERLAKE_S)
[19:28:37] [PASSED] 0xA78A (ALDERLAKE_S)
[19:28:37] [PASSED] 0xA78B (ALDERLAKE_S)
[19:28:37] [PASSED] 0x4905 (DG1)
[19:28:37] [PASSED] 0x4906 (DG1)
[19:28:37] [PASSED] 0x4907 (DG1)
[19:28:37] [PASSED] 0x4908 (DG1)
[19:28:37] [PASSED] 0x4909 (DG1)
[19:28:37] [PASSED] 0x56C0 (DG2)
[19:28:37] [PASSED] 0x56C2 (DG2)
[19:28:37] [PASSED] 0x56C1 (DG2)
[19:28:37] [PASSED] 0x7D51 (METEORLAKE)
[19:28:37] [PASSED] 0x7DD1 (METEORLAKE)
[19:28:37] [PASSED] 0x7D41 (METEORLAKE)
[19:28:37] [PASSED] 0x7D67 (METEORLAKE)
[19:28:37] [PASSED] 0xB640 (METEORLAKE)
[19:28:37] [PASSED] 0x56A0 (DG2)
[19:28:37] [PASSED] 0x56A1 (DG2)
[19:28:37] [PASSED] 0x56A2 (DG2)
[19:28:37] [PASSED] 0x56BE (DG2)
[19:28:37] [PASSED] 0x56BF (DG2)
[19:28:37] [PASSED] 0x5690 (DG2)
[19:28:37] [PASSED] 0x5691 (DG2)
[19:28:37] [PASSED] 0x5692 (DG2)
[19:28:37] [PASSED] 0x56A5 (DG2)
[19:28:37] [PASSED] 0x56A6 (DG2)
[19:28:37] [PASSED] 0x56B0 (DG2)
[19:28:37] [PASSED] 0x56B1 (DG2)
[19:28:37] [PASSED] 0x56BA (DG2)
[19:28:37] [PASSED] 0x56BB (DG2)
[19:28:37] [PASSED] 0x56BC (DG2)
[19:28:37] [PASSED] 0x56BD (DG2)
[19:28:37] [PASSED] 0x5693 (DG2)
[19:28:37] [PASSED] 0x5694 (DG2)
[19:28:37] [PASSED] 0x5695 (DG2)
[19:28:37] [PASSED] 0x56A3 (DG2)
[19:28:37] [PASSED] 0x56A4 (DG2)
[19:28:37] [PASSED] 0x56B2 (DG2)
[19:28:37] [PASSED] 0x56B3 (DG2)
[19:28:37] [PASSED] 0x5696 (DG2)
[19:28:37] [PASSED] 0x5697 (DG2)
[19:28:37] [PASSED] 0xB69 (PVC)
[19:28:37] [PASSED] 0xB6E (PVC)
[19:28:37] [PASSED] 0xBD4 (PVC)
[19:28:37] [PASSED] 0xBD5 (PVC)
[19:28:37] [PASSED] 0xBD6 (PVC)
[19:28:37] [PASSED] 0xBD7 (PVC)
[19:28:37] [PASSED] 0xBD8 (PVC)
[19:28:37] [PASSED] 0xBD9 (PVC)
[19:28:37] [PASSED] 0xBDA (PVC)
[19:28:37] [PASSED] 0xBDB (PVC)
[19:28:37] [PASSED] 0xBE0 (PVC)
[19:28:37] [PASSED] 0xBE1 (PVC)
[19:28:37] [PASSED] 0xBE5 (PVC)
[19:28:37] [PASSED] 0x7D40 (METEORLAKE)
[19:28:37] [PASSED] 0x7D45 (METEORLAKE)
[19:28:37] [PASSED] 0x7D55 (METEORLAKE)
[19:28:37] [PASSED] 0x7D60 (METEORLAKE)
[19:28:37] [PASSED] 0x7DD5 (METEORLAKE)
[19:28:37] [PASSED] 0x6420 (LUNARLAKE)
[19:28:37] [PASSED] 0x64A0 (LUNARLAKE)
[19:28:37] [PASSED] 0x64B0 (LUNARLAKE)
[19:28:37] [PASSED] 0xE202 (BATTLEMAGE)
[19:28:37] [PASSED] 0xE209 (BATTLEMAGE)
[19:28:37] [PASSED] 0xE20B (BATTLEMAGE)
[19:28:37] [PASSED] 0xE20C (BATTLEMAGE)
[19:28:37] [PASSED] 0xE20D (BATTLEMAGE)
[19:28:37] [PASSED] 0xE210 (BATTLEMAGE)
[19:28:37] [PASSED] 0xE211 (BATTLEMAGE)
[19:28:37] [PASSED] 0xE212 (BATTLEMAGE)
[19:28:37] [PASSED] 0xE216 (BATTLEMAGE)
[19:28:37] [PASSED] 0xE220 (BATTLEMAGE)
[19:28:37] [PASSED] 0xE221 (BATTLEMAGE)
[19:28:37] [PASSED] 0xE222 (BATTLEMAGE)
[19:28:37] [PASSED] 0xE223 (BATTLEMAGE)
[19:28:37] [PASSED] 0xB080 (PANTHERLAKE)
[19:28:37] [PASSED] 0xB081 (PANTHERLAKE)
[19:28:37] [PASSED] 0xB082 (PANTHERLAKE)
[19:28:37] [PASSED] 0xB083 (PANTHERLAKE)
[19:28:37] [PASSED] 0xB084 (PANTHERLAKE)
[19:28:37] [PASSED] 0xB085 (PANTHERLAKE)
[19:28:37] [PASSED] 0xB086 (PANTHERLAKE)
[19:28:37] [PASSED] 0xB087 (PANTHERLAKE)
[19:28:37] [PASSED] 0xB08F (PANTHERLAKE)
[19:28:37] [PASSED] 0xB090 (PANTHERLAKE)
[19:28:37] [PASSED] 0xB0A0 (PANTHERLAKE)
[19:28:37] [PASSED] 0xB0B0 (PANTHERLAKE)
[19:28:37] [PASSED] 0xFD80 (PANTHERLAKE)
[19:28:37] [PASSED] 0xFD81 (PANTHERLAKE)
[19:28:37] [PASSED] 0xD740 (NOVALAKE_S)
[19:28:37] [PASSED] 0xD741 (NOVALAKE_S)
[19:28:37] [PASSED] 0xD742 (NOVALAKE_S)
[19:28:37] [PASSED] 0xD743 (NOVALAKE_S)
[19:28:37] [PASSED] 0xD745 (NOVALAKE_S)
[19:28:37] [PASSED] 0xD74A (NOVALAKE_S)
[19:28:37] [PASSED] 0xD74B (NOVALAKE_S)
[19:28:37] [PASSED] 0x674C (CRESCENTISLAND)
[19:28:37] [PASSED] 0x674D (CRESCENTISLAND)
[19:28:37] [PASSED] 0x674E (CRESCENTISLAND)
[19:28:37] [PASSED] 0x674F (CRESCENTISLAND)
[19:28:37] [PASSED] 0x6750 (CRESCENTISLAND)
[19:28:37] [PASSED] 0xD750 (NOVALAKE_P)
[19:28:37] [PASSED] 0xD751 (NOVALAKE_P)
[19:28:37] [PASSED] 0xD752 (NOVALAKE_P)
[19:28:37] [PASSED] 0xD753 (NOVALAKE_P)
[19:28:37] [PASSED] 0xD754 (NOVALAKE_P)
[19:28:37] [PASSED] 0xD755 (NOVALAKE_P)
[19:28:37] [PASSED] 0xD756 (NOVALAKE_P)
[19:28:37] [PASSED] 0xD757 (NOVALAKE_P)
[19:28:37] [PASSED] 0xD75F (NOVALAKE_P)
[19:28:37] =============== [PASSED] check_platform_desc ===============
[19:28:37] ===================== [PASSED] xe_pci ======================
[19:28:37] ============= xe_rtp_tables_test (4 subtests) ==============
[19:28:37] ================== xe_rtp_table_gt_test ===================
[19:28:37] [PASSED] gt_was/14011060649
[19:28:37] [PASSED] gt_was/14011059788
[19:28:37] [PASSED] gt_was/14015795083
[19:28:37] [PASSED] gt_was/16021867713
[19:28:37] [PASSED] gt_was/14019449301
[19:28:37] [PASSED] gt_was/16028005424
[19:28:37] [PASSED] gt_was/14026578760
[19:28:37] [PASSED] gt_was/1409420604
[19:28:37] [PASSED] gt_was/1408615072
[19:28:37] [PASSED] gt_was/22010523718
[19:28:37] [PASSED] gt_was/14011006942
[19:28:37] [PASSED] gt_was/14014830051
[19:28:37] [PASSED] gt_was/18018781329
[19:28:37] [PASSED] gt_was/1509235366
[19:28:37] [PASSED] gt_was/18018781329
[19:28:37] [PASSED] gt_was/16016694945
[19:28:37] [PASSED] gt_was/14018575942
[19:28:37] [PASSED] gt_was/22016670082
[19:28:37] [PASSED] gt_was/22016670082
[19:28:37] [PASSED] gt_was/14017421178
[19:28:37] [PASSED] gt_was/16025250150
[19:28:37] [PASSED] gt_was/14021871409
[19:28:37] [PASSED] gt_was/16021865536
[19:28:37] [PASSED] gt_was/14021486841
[19:28:37] [PASSED] gt_was/14025160223
[19:28:37] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[19:28:37] [PASSED] gt_was/14025635424
[19:28:37] [PASSED] gt_was/16028005424
[19:28:37] ============== [PASSED] xe_rtp_table_gt_test ===============
[19:28:37] ================== xe_rtp_table_gt_test ===================
[19:28:37] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[19:28:37] [PASSED] gt_tunings/Tuning: 32B Access Enable
[19:28:37] [PASSED] gt_tunings/Tuning: L3 cache
[19:28:37] [PASSED] gt_tunings/Tuning: L3 cache - media
[19:28:37] [PASSED] gt_tunings/Tuning: Compression Overfetch
[19:28:37] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[19:28:37] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[19:28:37] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[19:28:37] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[19:28:37] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[19:28:37] [PASSED] gt_tunings/Tuning: Stateless compression control
[19:28:37] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[19:28:37] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[19:28:37] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[19:28:37] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[19:28:37] ============== [PASSED] xe_rtp_table_gt_test ===============
[19:28:37] ================== xe_rtp_table_oob_test ==================
[19:28:37] [PASSED] oob_was/1607983814
[19:28:37] [PASSED] oob_was/16010904313
[19:28:37] [PASSED] oob_was/18022495364
[19:28:37] [PASSED] oob_was/22012773006
[19:28:37] [PASSED] oob_was/14014475959
[19:28:37] [PASSED] oob_was/22011391025
[19:28:37] [PASSED] oob_was/22012727170
[19:28:37] [PASSED] oob_was/22012727685
[19:28:37] [PASSED] oob_was/22016596838
[19:28:37] [PASSED] oob_was/18020744125
[19:28:37] [PASSED] oob_was/1409600907
[19:28:37] [PASSED] oob_was/22014953428
[19:28:37] [PASSED] oob_was/16017236439
[19:28:37] [PASSED] oob_was/14019821291
[19:28:37] [PASSED] oob_was/14015076503
[19:28:37] [PASSED] oob_was/14018913170
[19:28:37] [PASSED] oob_was/14018094691
[19:28:37] [PASSED] oob_was/18024947630
[19:28:37] [PASSED] oob_was/16022287689
[19:28:37] [PASSED] oob_was/13011645652
[19:28:37] [PASSED] oob_was/14022293748
[19:28:37] [PASSED] oob_was/22019794406
[19:28:37] [PASSED] oob_was/22019338487
[19:28:37] [PASSED] oob_was/16023588340
[19:28:37] [PASSED] oob_was/14019789679
[19:28:37] [PASSED] oob_was/14022866841
[19:28:37] [PASSED] oob_was/16021333562
[19:28:37] [PASSED] oob_was/14016712196
[19:28:37] [PASSED] oob_was/14015568240
[19:28:37] [PASSED] oob_was/18013179988
[19:28:37] [PASSED] oob_was/1508761755
[19:28:37] [PASSED] oob_was/16023105232
[19:28:37] [PASSED] oob_was/16026508708
[19:28:37] [PASSED] oob_was/14020001231
[19:28:37] [PASSED] oob_was/16023683509
[19:28:37] [PASSED] oob_was/14025515070
[19:28:37] [PASSED] oob_was/15015404425_disable
[19:28:37] [PASSED] oob_was/16026007364
[19:28:37] [PASSED] oob_was/14020316580
[19:28:37] [PASSED] oob_was/14025883347
[19:28:37] [PASSED] oob_was/16029380221
[19:28:37] ============== [PASSED] xe_rtp_table_oob_test ==============
[19:28:37] ================ xe_rtp_table_dev_oob_test ================
[19:28:37] [PASSED] device_oob_was/22010954014
[19:28:37] [PASSED] device_oob_was/15015404425
[19:28:37] [PASSED] device_oob_was/22019338487_display
[19:28:37] [PASSED] device_oob_was/14022085890
[19:28:37] [PASSED] device_oob_was/14026539277
[19:28:37] [PASSED] device_oob_was/14026633728
[19:28:37] [PASSED] device_oob_was/14026746987
[19:28:37] [PASSED] device_oob_was/14026779378
[19:28:37] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[19:28:37] =============== [PASSED] xe_rtp_tables_test ================
[19:28:37] =================== xe_rtp (3 subtests) ====================
[19:28:37] =================== xe_rtp_rules_tests ====================
[19:28:37] [PASSED] no
[19:28:37] [PASSED] yes
[19:28:37] [PASSED] no-and-no
[19:28:37] [PASSED] no-and-yes
[19:28:37] [PASSED] yes-and-no
[19:28:37] [PASSED] yes-and-yes
[19:28:37] [PASSED] no-or-no
[19:28:37] [PASSED] no-or-yes
[19:28:37] [PASSED] yes-or-no
[19:28:37] [PASSED] yes-or-yes
[19:28:37] [PASSED] no-yes-or-yes-no
[19:28:37] [PASSED] no-yes-or-yes-yes
[19:28:37] [PASSED] yes-yes-or-no-yes
[19:28:37] [PASSED] yes-yes-or-yes-yes
[19:28:37] [PASSED] no-no-or-yes-or-no
[19:28:37] [PASSED] or
[19:28:37] [PASSED] or-yes
[19:28:37] [PASSED] or-no
[19:28:37] [PASSED] yes-or
[19:28:37] [PASSED] no-or
[19:28:37] [PASSED] no-or-or-yes
[19:28:37] [PASSED] yes-or-or-no
[19:28:37] [PASSED] no-or-or-no
[19:28:37] [PASSED] missing-context-engine-class
[19:28:37] [PASSED] missing-context-engine-class-or-yes
[19:28:37] [PASSED] missing-context-engine-class-or-or-yes
[19:28:37] =============== [PASSED] xe_rtp_rules_tests ================
[19:28:37] =============== xe_rtp_process_to_sr_tests ================
[19:28:37] [PASSED] coalesce-same-reg
[19:28:37] [PASSED] no-match-no-add
[19:28:37] [PASSED] two-regs-two-entries
[19:28:37] [PASSED] clr-one-set-other
[19:28:37] [PASSED] set-field
[19:28:37] [PASSED] conflict-duplicate
[19:28:37] [PASSED] conflict-not-disjoint
[19:28:37] [PASSED] conflict-reg-type
[19:28:37] [PASSED] bad-mcr-reg-forced-to-regular
[19:28:37] [PASSED] bad-regular-reg-forced-to-mcr
[19:28:37] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[19:28:37] ================== xe_rtp_process_tests ===================
[19:28:37] [PASSED] active1
[19:28:37] [PASSED] active2
[19:28:37] [PASSED] active-inactive
[19:28:37] [PASSED] inactive-active
[19:28:37] [PASSED] inactive-active-inactive
[19:28:37] [PASSED] inactive-inactive-inactive
[19:28:37] ============== [PASSED] xe_rtp_process_tests ===============
[19:28:37] ===================== [PASSED] xe_rtp ======================
[19:28:37] ==================== xe_wa (1 subtest) =====================
[19:28:37] ======================== xe_wa_gt =========================
[19:28:37] [PASSED] TIGERLAKE B0
[19:28:37] [PASSED] DG1 A0
[19:28:37] [PASSED] DG1 B0
[19:28:37] [PASSED] ALDERLAKE_S A0
[19:28:37] [PASSED] ALDERLAKE_S B0
[19:28:37] [PASSED] ALDERLAKE_S C0
[19:28:37] [PASSED] ALDERLAKE_S D0
[19:28:37] [PASSED] ALDERLAKE_P A0
[19:28:37] [PASSED] ALDERLAKE_P B0
[19:28:37] [PASSED] ALDERLAKE_P C0
[19:28:37] [PASSED] ALDERLAKE_S RPLS D0
[19:28:37] [PASSED] ALDERLAKE_P RPLU E0
[19:28:37] [PASSED] DG2 G10 C0
[19:28:37] [PASSED] DG2 G11 B1
[19:28:37] [PASSED] DG2 G12 A1
[19:28:37] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[19:28:37] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[19:28:37] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[19:28:37] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[19:28:37] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[19:28:37] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[19:28:37] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[19:28:37] ==================== [PASSED] xe_wa_gt =====================
[19:28:37] ====================== [PASSED] xe_wa ======================
[19:28:37] ============================================================
[19:28:37] Testing complete. Ran 717 tests: passed: 699, skipped: 18
[19:28:37] Elapsed time: 36.103s total, 4.300s configuring, 31.137s building, 0.652s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[19:28:37] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:28:39] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:29:03] Starting KUnit Kernel (1/1)...
[19:29:03] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:29:03] ============ drm_test_pick_cmdline (2 subtests) ============
[19:29:03] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[19:29:03] =============== drm_test_pick_cmdline_named ===============
[19:29:03] [PASSED] NTSC
[19:29:03] [PASSED] NTSC-J
[19:29:03] [PASSED] PAL
[19:29:03] [PASSED] PAL-M
[19:29:03] =========== [PASSED] drm_test_pick_cmdline_named ===========
[19:29:03] ============== [PASSED] drm_test_pick_cmdline ==============
[19:29:03] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[19:29:03] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[19:29:03] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[19:29:03] =========== drm_validate_clone_mode (2 subtests) ===========
[19:29:03] ============== drm_test_check_in_clone_mode ===============
[19:29:03] [PASSED] in_clone_mode
[19:29:03] [PASSED] not_in_clone_mode
[19:29:03] ========== [PASSED] drm_test_check_in_clone_mode ===========
[19:29:03] =============== drm_test_check_valid_clones ===============
[19:29:03] [PASSED] not_in_clone_mode
[19:29:03] [PASSED] valid_clone
[19:29:03] [PASSED] invalid_clone
[19:29:03] =========== [PASSED] drm_test_check_valid_clones ===========
[19:29:03] ============= [PASSED] drm_validate_clone_mode =============
[19:29:03] ============= drm_validate_modeset (1 subtest) =============
[19:29:03] [PASSED] drm_test_check_connector_changed_modeset
[19:29:03] ============== [PASSED] drm_validate_modeset ===============
[19:29:03] ====== drm_test_bridge_get_current_state (2 subtests) ======
[19:29:03] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[19:29:03] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[19:29:03] ======== [PASSED] drm_test_bridge_get_current_state ========
[19:29:03] ====== drm_test_bridge_helper_reset_crtc (4 subtests) ======
[19:29:03] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[19:29:03] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[19:29:03] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[19:29:03] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[19:29:03] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[19:29:03] ============== drm_bridge_alloc (2 subtests) ===============
[19:29:03] [PASSED] drm_test_drm_bridge_alloc_basic
[19:29:03] [PASSED] drm_test_drm_bridge_alloc_get_put
[19:29:03] ================ [PASSED] drm_bridge_alloc =================
[19:29:03] ============= drm_bridge_bus_fmt (5 subtests) ==============
[19:29:03] [PASSED] drm_test_bridge_rgb_yuv_rgb
[19:29:03] [PASSED] drm_test_bridge_must_convert_to_yuv444
[19:29:03] [PASSED] drm_test_bridge_hdmi_auto_rgb
[19:29:03] [PASSED] drm_test_bridge_auto_first
[19:29:03] [PASSED] drm_test_bridge_rgb_yuv_no_path
[19:29:03] =============== [PASSED] drm_bridge_bus_fmt ================
[19:29:03] ============= drm_cmdline_parser (40 subtests) =============
[19:29:03] [PASSED] drm_test_cmdline_force_d_only
[19:29:03] [PASSED] drm_test_cmdline_force_D_only_dvi
[19:29:03] [PASSED] drm_test_cmdline_force_D_only_hdmi
[19:29:03] [PASSED] drm_test_cmdline_force_D_only_not_digital
[19:29:03] [PASSED] drm_test_cmdline_force_e_only
[19:29:03] [PASSED] drm_test_cmdline_res
[19:29:03] [PASSED] drm_test_cmdline_res_vesa
[19:29:03] [PASSED] drm_test_cmdline_res_vesa_rblank
[19:29:03] [PASSED] drm_test_cmdline_res_rblank
[19:29:03] [PASSED] drm_test_cmdline_res_bpp
[19:29:03] [PASSED] drm_test_cmdline_res_refresh
[19:29:03] [PASSED] drm_test_cmdline_res_bpp_refresh
[19:29:03] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[19:29:03] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[19:29:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[19:29:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[19:29:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[19:29:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[19:29:03] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[19:29:03] [PASSED] drm_test_cmdline_res_margins_force_on
[19:29:03] [PASSED] drm_test_cmdline_res_vesa_margins
[19:29:03] [PASSED] drm_test_cmdline_name
[19:29:03] [PASSED] drm_test_cmdline_name_bpp
[19:29:03] [PASSED] drm_test_cmdline_name_option
[19:29:03] [PASSED] drm_test_cmdline_name_bpp_option
[19:29:03] [PASSED] drm_test_cmdline_rotate_0
[19:29:03] [PASSED] drm_test_cmdline_rotate_90
[19:29:03] [PASSED] drm_test_cmdline_rotate_180
[19:29:03] [PASSED] drm_test_cmdline_rotate_270
[19:29:03] [PASSED] drm_test_cmdline_hmirror
[19:29:03] [PASSED] drm_test_cmdline_vmirror
[19:29:03] [PASSED] drm_test_cmdline_margin_options
[19:29:03] [PASSED] drm_test_cmdline_multiple_options
[19:29:03] [PASSED] drm_test_cmdline_bpp_extra_and_option
[19:29:03] [PASSED] drm_test_cmdline_extra_and_option
[19:29:03] [PASSED] drm_test_cmdline_freestanding_options
[19:29:03] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[19:29:03] [PASSED] drm_test_cmdline_panel_orientation
[19:29:03] ================ drm_test_cmdline_invalid =================
[19:29:03] [PASSED] margin_only
[19:29:03] [PASSED] interlace_only
[19:29:03] [PASSED] res_missing_x
[19:29:03] [PASSED] res_missing_y
[19:29:03] [PASSED] res_bad_y
[19:29:03] [PASSED] res_missing_y_bpp
[19:29:03] [PASSED] res_bad_bpp
[19:29:03] [PASSED] res_bad_refresh
[19:29:03] [PASSED] res_bpp_refresh_force_on_off
[19:29:03] [PASSED] res_invalid_mode
[19:29:03] [PASSED] res_bpp_wrong_place_mode
[19:29:03] [PASSED] name_bpp_refresh
[19:29:03] [PASSED] name_refresh
[19:29:03] [PASSED] name_refresh_wrong_mode
[19:29:03] [PASSED] name_refresh_invalid_mode
[19:29:03] [PASSED] rotate_multiple
[19:29:03] [PASSED] rotate_invalid_val
[19:29:03] [PASSED] rotate_truncated
[19:29:03] [PASSED] invalid_option
[19:29:03] [PASSED] invalid_tv_option
[19:29:03] [PASSED] truncated_tv_option
[19:29:03] ============ [PASSED] drm_test_cmdline_invalid =============
[19:29:03] =============== drm_test_cmdline_tv_options ===============
[19:29:03] [PASSED] NTSC
[19:29:03] [PASSED] NTSC_443
[19:29:03] [PASSED] NTSC_J
[19:29:03] [PASSED] PAL
[19:29:03] [PASSED] PAL_M
[19:29:03] [PASSED] PAL_N
[19:29:03] [PASSED] SECAM
[19:29:03] [PASSED] MONO_525
[19:29:03] [PASSED] MONO_625
[19:29:03] =========== [PASSED] drm_test_cmdline_tv_options ===========
[19:29:03] =============== [PASSED] drm_cmdline_parser ================
[19:29:03] ========== drmm_connector_hdmi_init (20 subtests) ==========
[19:29:03] [PASSED] drm_test_connector_hdmi_init_valid
[19:29:03] [PASSED] drm_test_connector_hdmi_init_bpc_8
[19:29:03] [PASSED] drm_test_connector_hdmi_init_bpc_10
[19:29:03] [PASSED] drm_test_connector_hdmi_init_bpc_12
[19:29:03] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[19:29:03] [PASSED] drm_test_connector_hdmi_init_bpc_null
[19:29:03] [PASSED] drm_test_connector_hdmi_init_formats_empty
[19:29:03] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[19:29:03] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[19:29:03] [PASSED] supported_formats=0x9 yuv420_allowed=1
[19:29:03] [PASSED] supported_formats=0x9 yuv420_allowed=0
[19:29:03] [PASSED] supported_formats=0x5 yuv420_allowed=1
[19:29:03] [PASSED] supported_formats=0x5 yuv420_allowed=0
[19:29:03] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[19:29:03] [PASSED] drm_test_connector_hdmi_init_null_ddc
[19:29:03] [PASSED] drm_test_connector_hdmi_init_null_product
[19:29:03] [PASSED] drm_test_connector_hdmi_init_null_vendor
[19:29:03] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[19:29:03] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[19:29:03] [PASSED] drm_test_connector_hdmi_init_product_valid
[19:29:03] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[19:29:03] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[19:29:03] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[19:29:03] ========= drm_test_connector_hdmi_init_type_valid =========
[19:29:03] [PASSED] HDMI-A
[19:29:03] [PASSED] HDMI-B
[19:29:03] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[19:29:03] ======== drm_test_connector_hdmi_init_type_invalid ========
[19:29:03] [PASSED] Unknown
[19:29:03] [PASSED] VGA
[19:29:03] [PASSED] DVI-I
[19:29:03] [PASSED] DVI-D
[19:29:03] [PASSED] DVI-A
[19:29:03] [PASSED] Composite
[19:29:03] [PASSED] SVIDEO
[19:29:03] [PASSED] LVDS
[19:29:03] [PASSED] Component
[19:29:03] [PASSED] DIN
[19:29:03] [PASSED] DP
[19:29:03] [PASSED] TV
[19:29:03] [PASSED] eDP
[19:29:03] [PASSED] Virtual
[19:29:03] [PASSED] DSI
[19:29:03] [PASSED] DPI
[19:29:03] [PASSED] Writeback
[19:29:03] [PASSED] SPI
[19:29:03] [PASSED] USB
[19:29:03] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[19:29:03] ============ [PASSED] drmm_connector_hdmi_init =============
[19:29:03] ============= drmm_connector_init (3 subtests) =============
[19:29:03] [PASSED] drm_test_drmm_connector_init
[19:29:03] [PASSED] drm_test_drmm_connector_init_null_ddc
[19:29:03] ========= drm_test_drmm_connector_init_type_valid =========
[19:29:03] [PASSED] Unknown
[19:29:03] [PASSED] VGA
[19:29:03] [PASSED] DVI-I
[19:29:03] [PASSED] DVI-D
[19:29:03] [PASSED] DVI-A
[19:29:03] [PASSED] Composite
[19:29:03] [PASSED] SVIDEO
[19:29:03] [PASSED] LVDS
[19:29:03] [PASSED] Component
[19:29:03] [PASSED] DIN
[19:29:03] [PASSED] DP
[19:29:03] [PASSED] HDMI-A
[19:29:03] [PASSED] HDMI-B
[19:29:03] [PASSED] TV
[19:29:03] [PASSED] eDP
[19:29:03] [PASSED] Virtual
[19:29:03] [PASSED] DSI
[19:29:03] [PASSED] DPI
[19:29:03] [PASSED] Writeback
[19:29:03] [PASSED] SPI
[19:29:03] [PASSED] USB
[19:29:03] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[19:29:03] =============== [PASSED] drmm_connector_init ===============
[19:29:03] ========= drm_connector_dynamic_init (6 subtests) ==========
[19:29:03] [PASSED] drm_test_drm_connector_dynamic_init
[19:29:03] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[19:29:03] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[19:29:03] [PASSED] drm_test_drm_connector_dynamic_init_properties
[19:29:03] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[19:29:03] [PASSED] Unknown
[19:29:03] [PASSED] VGA
[19:29:03] [PASSED] DVI-I
[19:29:03] [PASSED] DVI-D
[19:29:03] [PASSED] DVI-A
[19:29:03] [PASSED] Composite
[19:29:03] [PASSED] SVIDEO
[19:29:03] [PASSED] LVDS
[19:29:03] [PASSED] Component
[19:29:03] [PASSED] DIN
[19:29:03] [PASSED] DP
[19:29:03] [PASSED] HDMI-A
[19:29:03] [PASSED] HDMI-B
[19:29:03] [PASSED] TV
[19:29:03] [PASSED] eDP
[19:29:03] [PASSED] Virtual
[19:29:03] [PASSED] DSI
[19:29:03] [PASSED] DPI
[19:29:03] [PASSED] Writeback
[19:29:03] [PASSED] SPI
[19:29:03] [PASSED] USB
[19:29:03] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[19:29:03] ======== drm_test_drm_connector_dynamic_init_name =========
[19:29:03] [PASSED] Unknown
[19:29:03] [PASSED] VGA
[19:29:03] [PASSED] DVI-I
[19:29:03] [PASSED] DVI-D
[19:29:03] [PASSED] DVI-A
[19:29:03] [PASSED] Composite
[19:29:03] [PASSED] SVIDEO
[19:29:03] [PASSED] LVDS
[19:29:03] [PASSED] Component
[19:29:03] [PASSED] DIN
[19:29:03] [PASSED] DP
[19:29:03] [PASSED] HDMI-A
[19:29:03] [PASSED] HDMI-B
[19:29:03] [PASSED] TV
[19:29:03] [PASSED] eDP
[19:29:03] [PASSED] Virtual
[19:29:03] [PASSED] DSI
[19:29:03] [PASSED] DPI
[19:29:03] [PASSED] Writeback
[19:29:03] [PASSED] SPI
[19:29:03] [PASSED] USB
[19:29:03] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[19:29:03] =========== [PASSED] drm_connector_dynamic_init ============
[19:29:03] ==== drm_connector_dynamic_register_early (4 subtests) =====
[19:29:03] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[19:29:03] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[19:29:03] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[19:29:03] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[19:29:03] ====== [PASSED] drm_connector_dynamic_register_early =======
[19:29:03] ======= drm_connector_dynamic_register (7 subtests) ========
[19:29:03] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[19:29:03] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[19:29:03] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[19:29:03] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[19:29:03] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[19:29:03] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[19:29:03] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[19:29:03] ========= [PASSED] drm_connector_dynamic_register ==========
[19:29:03] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[19:29:03] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[19:29:03] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[19:29:03] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[19:29:03] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[19:29:03] ========== drm_test_get_tv_mode_from_name_valid ===========
[19:29:03] [PASSED] NTSC
[19:29:03] [PASSED] NTSC-443
[19:29:03] [PASSED] NTSC-J
[19:29:03] [PASSED] PAL
[19:29:03] [PASSED] PAL-M
[19:29:03] [PASSED] PAL-N
[19:29:03] [PASSED] SECAM
[19:29:03] [PASSED] Mono
[19:29:03] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[19:29:03] [PASSED] drm_test_get_tv_mode_from_name_truncated
[19:29:03] ============ [PASSED] drm_get_tv_mode_from_name ============
[19:29:03] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[19:29:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[19:29:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[19:29:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[19:29:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[19:29:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[19:29:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[19:29:03] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[19:29:03] [PASSED] VIC 96
[19:29:03] [PASSED] VIC 97
[19:29:03] [PASSED] VIC 101
[19:29:03] [PASSED] VIC 102
[19:29:03] [PASSED] VIC 106
[19:29:03] [PASSED] VIC 107
[19:29:03] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[19:29:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[19:29:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[19:29:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[19:29:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[19:29:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[19:29:03] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[19:29:03] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[19:29:03] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[19:29:03] [PASSED] Automatic
[19:29:03] [PASSED] Full
[19:29:03] [PASSED] Limited 16:235
[19:29:03] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[19:29:03] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[19:29:03] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[19:29:03] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[19:29:03] === drm_test_drm_hdmi_connector_get_output_format_name ====
[19:29:03] [PASSED] RGB
[19:29:03] [PASSED] YUV 4:2:0
[19:29:03] [PASSED] YUV 4:2:2
[19:29:03] [PASSED] YUV 4:4:4
[19:29:03] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[19:29:03] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[19:29:03] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[19:29:03] ============= drm_damage_helper (21 subtests) ==============
[19:29:03] [PASSED] drm_test_damage_iter_no_damage
[19:29:03] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[19:29:03] [PASSED] drm_test_damage_iter_no_damage_src_moved
[19:29:03] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[19:29:03] [PASSED] drm_test_damage_iter_no_damage_not_visible
[19:29:03] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[19:29:03] [PASSED] drm_test_damage_iter_no_damage_no_fb
[19:29:03] [PASSED] drm_test_damage_iter_simple_damage
[19:29:03] [PASSED] drm_test_damage_iter_single_damage
[19:29:03] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[19:29:03] [PASSED] drm_test_damage_iter_single_damage_outside_src
[19:29:03] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[19:29:03] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[19:29:03] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[19:29:03] [PASSED] drm_test_damage_iter_single_damage_src_moved
[19:29:03] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[19:29:03] [PASSED] drm_test_damage_iter_damage
[19:29:03] [PASSED] drm_test_damage_iter_damage_one_intersect
[19:29:03] [PASSED] drm_test_damage_iter_damage_one_outside
[19:29:03] [PASSED] drm_test_damage_iter_damage_src_moved
[19:29:03] [PASSED] drm_test_damage_iter_damage_not_visible
[19:29:03] ================ [PASSED] drm_damage_helper ================
[19:29:03] ============== drm_dp_mst_helper (3 subtests) ==============
[19:29:03] ============== drm_test_dp_mst_calc_pbn_mode ==============
[19:29:03] [PASSED] Clock 154000 BPP 30 DSC disabled
[19:29:03] [PASSED] Clock 234000 BPP 30 DSC disabled
[19:29:03] [PASSED] Clock 297000 BPP 24 DSC disabled
[19:29:03] [PASSED] Clock 332880 BPP 24 DSC enabled
[19:29:03] [PASSED] Clock 324540 BPP 24 DSC enabled
[19:29:03] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[19:29:03] ============== drm_test_dp_mst_calc_pbn_div ===============
[19:29:03] [PASSED] Link rate 2000000 lane count 4
[19:29:03] [PASSED] Link rate 2000000 lane count 2
[19:29:03] [PASSED] Link rate 2000000 lane count 1
[19:29:03] [PASSED] Link rate 1350000 lane count 4
[19:29:03] [PASSED] Link rate 1350000 lane count 2
[19:29:03] [PASSED] Link rate 1350000 lane count 1
[19:29:03] [PASSED] Link rate 1000000 lane count 4
[19:29:03] [PASSED] Link rate 1000000 lane count 2
[19:29:03] [PASSED] Link rate 1000000 lane count 1
[19:29:03] [PASSED] Link rate 810000 lane count 4
[19:29:03] [PASSED] Link rate 810000 lane count 2
[19:29:03] [PASSED] Link rate 810000 lane count 1
[19:29:03] [PASSED] Link rate 540000 lane count 4
[19:29:03] [PASSED] Link rate 540000 lane count 2
[19:29:03] [PASSED] Link rate 540000 lane count 1
[19:29:03] [PASSED] Link rate 270000 lane count 4
[19:29:03] [PASSED] Link rate 270000 lane count 2
[19:29:03] [PASSED] Link rate 270000 lane count 1
[19:29:03] [PASSED] Link rate 162000 lane count 4
[19:29:03] [PASSED] Link rate 162000 lane count 2
[19:29:03] [PASSED] Link rate 162000 lane count 1
[19:29:03] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[19:29:03] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[19:29:03] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[19:29:03] [PASSED] DP_POWER_UP_PHY with port number
[19:29:03] [PASSED] DP_POWER_DOWN_PHY with port number
[19:29:03] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[19:29:03] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[19:29:03] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[19:29:03] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[19:29:03] [PASSED] DP_QUERY_PAYLOAD with port number
[19:29:03] [PASSED] DP_QUERY_PAYLOAD with VCPI
[19:29:03] [PASSED] DP_REMOTE_DPCD_READ with port number
[19:29:03] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[19:29:03] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[19:29:03] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[19:29:03] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[19:29:03] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[19:29:03] [PASSED] DP_REMOTE_I2C_READ with port number
[19:29:03] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[19:29:03] [PASSED] DP_REMOTE_I2C_READ with transactions array
[19:29:03] [PASSED] DP_REMOTE_I2C_WRITE with port number
[19:29:03] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[19:29:03] [PASSED] DP_REMOTE_I2C_WRITE with data array
[19:29:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[19:29:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[19:29:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[19:29:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[19:29:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[19:29:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[19:29:03] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[19:29:03] ================ [PASSED] drm_dp_mst_helper ================
[19:29:03] ================== drm_exec (7 subtests) ===================
[19:29:03] [PASSED] sanitycheck
[19:29:03] [PASSED] test_lock
[19:29:03] [PASSED] test_lock_unlock
[19:29:03] [PASSED] test_duplicates
[19:29:03] [PASSED] test_prepare
[19:29:03] [PASSED] test_prepare_array
[19:29:03] [PASSED] test_multiple_loops
[19:29:03] ==================== [PASSED] drm_exec =====================
[19:29:03] =========== drm_format_helper_test (17 subtests) ===========
[19:29:03] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[19:29:03] [PASSED] single_pixel_source_buffer
[19:29:03] [PASSED] single_pixel_clip_rectangle
[19:29:03] [PASSED] well_known_colors
[19:29:03] [PASSED] destination_pitch
[19:29:03] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[19:29:03] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[19:29:03] [PASSED] single_pixel_source_buffer
[19:29:03] [PASSED] single_pixel_clip_rectangle
[19:29:03] [PASSED] well_known_colors
[19:29:03] [PASSED] destination_pitch
[19:29:03] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[19:29:03] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[19:29:03] [PASSED] single_pixel_source_buffer
[19:29:03] [PASSED] single_pixel_clip_rectangle
[19:29:03] [PASSED] well_known_colors
[19:29:03] [PASSED] destination_pitch
[19:29:03] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[19:29:03] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[19:29:03] [PASSED] single_pixel_source_buffer
[19:29:03] [PASSED] single_pixel_clip_rectangle
[19:29:03] [PASSED] well_known_colors
[19:29:03] [PASSED] destination_pitch
[19:29:03] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[19:29:03] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[19:29:03] [PASSED] single_pixel_source_buffer
[19:29:03] [PASSED] single_pixel_clip_rectangle
[19:29:03] [PASSED] well_known_colors
[19:29:03] [PASSED] destination_pitch
[19:29:03] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[19:29:03] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[19:29:03] [PASSED] single_pixel_source_buffer
[19:29:03] [PASSED] single_pixel_clip_rectangle
[19:29:03] [PASSED] well_known_colors
[19:29:03] [PASSED] destination_pitch
[19:29:03] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[19:29:03] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[19:29:03] [PASSED] single_pixel_source_buffer
[19:29:03] [PASSED] single_pixel_clip_rectangle
[19:29:03] [PASSED] well_known_colors
[19:29:03] [PASSED] destination_pitch
[19:29:03] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[19:29:03] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[19:29:03] [PASSED] single_pixel_source_buffer
[19:29:03] [PASSED] single_pixel_clip_rectangle
[19:29:03] [PASSED] well_known_colors
[19:29:03] [PASSED] destination_pitch
[19:29:03] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[19:29:03] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[19:29:03] [PASSED] single_pixel_source_buffer
[19:29:03] [PASSED] single_pixel_clip_rectangle
[19:29:03] [PASSED] well_known_colors
[19:29:03] [PASSED] destination_pitch
[19:29:03] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[19:29:03] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[19:29:03] [PASSED] single_pixel_source_buffer
[19:29:03] [PASSED] single_pixel_clip_rectangle
[19:29:03] [PASSED] well_known_colors
[19:29:03] [PASSED] destination_pitch
[19:29:03] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[19:29:03] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[19:29:03] [PASSED] single_pixel_source_buffer
[19:29:03] [PASSED] single_pixel_clip_rectangle
[19:29:03] [PASSED] well_known_colors
[19:29:03] [PASSED] destination_pitch
[19:29:03] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[19:29:03] ============== drm_test_fb_xrgb8888_to_mono ===============
[19:29:03] [PASSED] single_pixel_source_buffer
[19:29:03] [PASSED] single_pixel_clip_rectangle
[19:29:03] [PASSED] well_known_colors
[19:29:03] [PASSED] destination_pitch
[19:29:03] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[19:29:03] ==================== drm_test_fb_swab =====================
[19:29:03] [PASSED] single_pixel_source_buffer
[19:29:03] [PASSED] single_pixel_clip_rectangle
[19:29:03] [PASSED] well_known_colors
[19:29:03] [PASSED] destination_pitch
[19:29:03] ================ [PASSED] drm_test_fb_swab =================
[19:29:03] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[19:29:03] [PASSED] single_pixel_source_buffer
[19:29:03] [PASSED] single_pixel_clip_rectangle
[19:29:03] [PASSED] well_known_colors
[19:29:03] [PASSED] destination_pitch
[19:29:03] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[19:29:03] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[19:29:03] [PASSED] single_pixel_source_buffer
[19:29:03] [PASSED] single_pixel_clip_rectangle
[19:29:03] [PASSED] well_known_colors
[19:29:03] [PASSED] destination_pitch
[19:29:03] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[19:29:03] ================= drm_test_fb_clip_offset =================
[19:29:03] [PASSED] pass through
[19:29:03] [PASSED] horizontal offset
[19:29:03] [PASSED] vertical offset
[19:29:03] [PASSED] horizontal and vertical offset
[19:29:03] [PASSED] horizontal offset (custom pitch)
[19:29:03] [PASSED] vertical offset (custom pitch)
[19:29:03] [PASSED] horizontal and vertical offset (custom pitch)
[19:29:03] ============= [PASSED] drm_test_fb_clip_offset =============
[19:29:03] =================== drm_test_fb_memcpy ====================
[19:29:03] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[19:29:03] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[19:29:03] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[19:29:03] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[19:29:03] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[19:29:03] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[19:29:03] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[19:29:03] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[19:29:03] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[19:29:03] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[19:29:03] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[19:29:03] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[19:29:03] =============== [PASSED] drm_test_fb_memcpy ================
[19:29:03] ============= [PASSED] drm_format_helper_test ==============
[19:29:03] ================= drm_format (18 subtests) =================
[19:29:03] [PASSED] drm_test_format_block_width_invalid
[19:29:03] [PASSED] drm_test_format_block_width_one_plane
[19:29:03] [PASSED] drm_test_format_block_width_two_plane
[19:29:03] [PASSED] drm_test_format_block_width_three_plane
[19:29:03] [PASSED] drm_test_format_block_width_tiled
[19:29:03] [PASSED] drm_test_format_block_height_invalid
[19:29:03] [PASSED] drm_test_format_block_height_one_plane
[19:29:03] [PASSED] drm_test_format_block_height_two_plane
[19:29:03] [PASSED] drm_test_format_block_height_three_plane
[19:29:03] [PASSED] drm_test_format_block_height_tiled
[19:29:03] [PASSED] drm_test_format_min_pitch_invalid
[19:29:03] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[19:29:03] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[19:29:03] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[19:29:03] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[19:29:03] [PASSED] drm_test_format_min_pitch_two_plane
[19:29:03] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[19:29:03] [PASSED] drm_test_format_min_pitch_tiled
[19:29:03] =================== [PASSED] drm_format ====================
[19:29:03] ============== drm_framebuffer (10 subtests) ===============
[19:29:03] ========== drm_test_framebuffer_check_src_coords ==========
[19:29:03] [PASSED] Success: source fits into fb
[19:29:03] [PASSED] Fail: overflowing fb with x-axis coordinate
[19:29:03] [PASSED] Fail: overflowing fb with y-axis coordinate
[19:29:03] [PASSED] Fail: overflowing fb with source width
[19:29:03] [PASSED] Fail: overflowing fb with source height
[19:29:03] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[19:29:03] [PASSED] drm_test_framebuffer_cleanup
[19:29:03] =============== drm_test_framebuffer_create ===============
[19:29:03] [PASSED] ABGR8888 normal sizes
[19:29:03] [PASSED] ABGR8888 max sizes
[19:29:03] [PASSED] ABGR8888 pitch greater than min required
[19:29:03] [PASSED] ABGR8888 pitch less than min required
[19:29:03] [PASSED] ABGR8888 Invalid width
[19:29:03] [PASSED] ABGR8888 Invalid buffer handle
[19:29:03] [PASSED] No pixel format
[19:29:03] [PASSED] ABGR8888 Width 0
[19:29:03] [PASSED] ABGR8888 Height 0
[19:29:03] [PASSED] ABGR8888 Out of bound height * pitch combination
[19:29:03] [PASSED] ABGR8888 Large buffer offset
[19:29:03] [PASSED] ABGR8888 Buffer offset for inexistent plane
[19:29:03] [PASSED] ABGR8888 Invalid flag
[19:29:03] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[19:29:03] [PASSED] ABGR8888 Valid buffer modifier
[19:29:03] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[19:29:03] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[19:29:03] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[19:29:03] [PASSED] NV12 Normal sizes
[19:29:03] [PASSED] NV12 Max sizes
[19:29:03] [PASSED] NV12 Invalid pitch
[19:29:03] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[19:29:03] [PASSED] NV12 different modifier per-plane
[19:29:03] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[19:29:03] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[19:29:03] [PASSED] NV12 Modifier for inexistent plane
[19:29:03] [PASSED] NV12 Handle for inexistent plane
[19:29:03] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[19:29:03] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[19:29:03] [PASSED] YVU420 Normal sizes
[19:29:03] [PASSED] YVU420 Max sizes
[19:29:03] [PASSED] YVU420 Invalid pitch
[19:29:03] [PASSED] YVU420 Different pitches
[19:29:03] [PASSED] YVU420 Different buffer offsets/pitches
[19:29:03] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[19:29:03] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[19:29:03] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[19:29:03] [PASSED] YVU420 Valid modifier
[19:29:03] [PASSED] YVU420 Different modifiers per plane
[19:29:03] [PASSED] YVU420 Modifier for inexistent plane
[19:29:03] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[19:29:03] [PASSED] X0L2 Normal sizes
[19:29:03] [PASSED] X0L2 Max sizes
[19:29:03] [PASSED] X0L2 Invalid pitch
[19:29:03] [PASSED] X0L2 Pitch greater than minimum required
[19:29:03] [PASSED] X0L2 Handle for inexistent plane
[19:29:03] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[19:29:03] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[19:29:03] [PASSED] X0L2 Valid modifier
[19:29:03] [PASSED] X0L2 Modifier for inexistent plane
[19:29:03] =========== [PASSED] drm_test_framebuffer_create ===========
[19:29:03] [PASSED] drm_test_framebuffer_free
[19:29:03] [PASSED] drm_test_framebuffer_init
[19:29:03] [PASSED] drm_test_framebuffer_init_bad_format
[19:29:03] [PASSED] drm_test_framebuffer_init_dev_mismatch
[19:29:03] [PASSED] drm_test_framebuffer_lookup
[19:29:03] [PASSED] drm_test_framebuffer_lookup_inexistent
[19:29:03] [PASSED] drm_test_framebuffer_modifiers_not_supported
[19:29:03] ================= [PASSED] drm_framebuffer =================
[19:29:03] ================ drm_gem_shmem (8 subtests) ================
[19:29:03] [PASSED] drm_gem_shmem_test_obj_create
[19:29:03] [PASSED] drm_gem_shmem_test_obj_create_private
[19:29:03] [PASSED] drm_gem_shmem_test_pin_pages
[19:29:03] [PASSED] drm_gem_shmem_test_vmap
[19:29:03] [PASSED] drm_gem_shmem_test_get_sg_table
[19:29:03] [PASSED] drm_gem_shmem_test_get_pages_sgt
[19:29:03] [PASSED] drm_gem_shmem_test_madvise
[19:29:03] [PASSED] drm_gem_shmem_test_purge
[19:29:03] ================== [PASSED] drm_gem_shmem ==================
[19:29:03] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[19:29:03] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[19:29:03] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[19:29:03] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[19:29:03] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[19:29:03] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[19:29:03] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[19:29:03] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[19:29:03] [PASSED] Automatic
[19:29:03] [PASSED] Full
[19:29:03] [PASSED] Limited 16:235
[19:29:03] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[19:29:03] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[19:29:03] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[19:29:03] [PASSED] drm_test_check_disable_connector
[19:29:03] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[19:29:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[19:29:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[19:29:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[19:29:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[19:29:03] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[19:29:03] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[19:29:03] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[19:29:03] [PASSED] drm_test_check_output_bpc_dvi
[19:29:03] [PASSED] drm_test_check_output_bpc_format_vic_1
[19:29:03] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[19:29:03] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[19:29:03] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[19:29:03] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[19:29:03] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[19:29:03] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[19:29:03] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[19:29:03] ============ drm_test_check_hdmi_color_format =============
[19:29:03] [PASSED] AUTO -> RGB
[19:29:03] [PASSED] YCBCR422 -> YUV422
[19:29:03] [PASSED] YCBCR420 -> YUV420
[19:29:03] [PASSED] YCBCR444 -> YUV444
[19:29:03] [PASSED] RGB -> RGB
[19:29:03] ======== [PASSED] drm_test_check_hdmi_color_format =========
[19:29:03] ======== drm_test_check_hdmi_color_format_420_only ========
[19:29:03] [PASSED] RGB should fail
[19:29:03] [PASSED] YUV444 should fail
[19:29:03] [PASSED] YUV422 should fail
[19:29:03] [PASSED] YUV420 should work
[19:29:03] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[19:29:03] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[19:29:03] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[19:29:03] [PASSED] drm_test_check_broadcast_rgb_value
[19:29:03] [PASSED] drm_test_check_bpc_8_value
[19:29:03] [PASSED] drm_test_check_bpc_10_value
[19:29:03] [PASSED] drm_test_check_bpc_12_value
[19:29:03] [PASSED] drm_test_check_format_value
[19:29:03] [PASSED] drm_test_check_tmds_char_value
[19:29:03] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[19:29:03] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[19:29:03] [PASSED] drm_test_check_mode_valid
[19:29:03] [PASSED] drm_test_check_mode_valid_reject
[19:29:03] [PASSED] drm_test_check_mode_valid_reject_rate
[19:29:03] [PASSED] drm_test_check_mode_valid_reject_max_clock
[19:29:03] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[19:29:03] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[19:29:03] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[19:29:03] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[19:29:03] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[19:29:03] [PASSED] drm_test_check_infoframes
[19:29:03] [PASSED] drm_test_check_reject_avi_infoframe
[19:29:03] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[19:29:03] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[19:29:03] [PASSED] drm_test_check_reject_audio_infoframe
[19:29:03] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[19:29:03] ================= drm_managed (2 subtests) =================
[19:29:03] [PASSED] drm_test_managed_release_action
[19:29:03] [PASSED] drm_test_managed_run_action
[19:29:03] =================== [PASSED] drm_managed ===================
[19:29:03] =================== drm_mm (6 subtests) ====================
[19:29:03] [PASSED] drm_test_mm_init
[19:29:03] [PASSED] drm_test_mm_debug
[19:29:03] [PASSED] drm_test_mm_align32
[19:29:03] [PASSED] drm_test_mm_align64
[19:29:03] [PASSED] drm_test_mm_lowest
[19:29:03] [PASSED] drm_test_mm_highest
[19:29:03] ===================== [PASSED] drm_mm ======================
[19:29:03] ============= drm_modes_analog_tv (5 subtests) =============
[19:29:03] [PASSED] drm_test_modes_analog_tv_mono_576i
[19:29:03] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[19:29:03] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[19:29:03] [PASSED] drm_test_modes_analog_tv_pal_576i
[19:29:03] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[19:29:03] =============== [PASSED] drm_modes_analog_tv ===============
[19:29:03] ============== drm_plane_helper (2 subtests) ===============
[19:29:03] =============== drm_test_check_plane_state ================
[19:29:03] [PASSED] clipping_simple
[19:29:03] [PASSED] clipping_rotate_reflect
[19:29:03] [PASSED] positioning_simple
[19:29:03] [PASSED] upscaling
[19:29:03] [PASSED] downscaling
[19:29:03] [PASSED] rounding1
[19:29:03] [PASSED] rounding2
[19:29:03] [PASSED] rounding3
[19:29:03] [PASSED] rounding4
[19:29:03] =========== [PASSED] drm_test_check_plane_state ============
[19:29:03] =========== drm_test_check_invalid_plane_state ============
[19:29:03] [PASSED] positioning_invalid
[19:29:03] [PASSED] upscaling_invalid
[19:29:03] [PASSED] downscaling_invalid
[19:29:03] ======= [PASSED] drm_test_check_invalid_plane_state ========
[19:29:03] ================ [PASSED] drm_plane_helper =================
[19:29:03] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[19:29:03] ====== drm_test_connector_helper_tv_get_modes_check =======
[19:29:03] [PASSED] None
[19:29:03] [PASSED] PAL
[19:29:03] [PASSED] NTSC
[19:29:03] [PASSED] Both, NTSC Default
[19:29:03] [PASSED] Both, PAL Default
[19:29:03] [PASSED] Both, NTSC Default, with PAL on command-line
[19:29:03] [PASSED] Both, PAL Default, with NTSC on command-line
[19:29:03] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[19:29:03] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[19:29:03] ================== drm_rect (9 subtests) ===================
[19:29:03] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[19:29:03] [PASSED] drm_test_rect_clip_scaled_not_clipped
[19:29:03] [PASSED] drm_test_rect_clip_scaled_clipped
[19:29:03] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[19:29:03] ================= drm_test_rect_intersect =================
[19:29:03] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[19:29:03] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[19:29:03] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[19:29:03] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[19:29:03] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[19:29:03] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[19:29:03] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[19:29:03] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[19:29:03] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[19:29:03] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[19:29:03] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[19:29:03] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[19:29:03] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[19:29:03] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[19:29:03] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[19:29:03] ============= [PASSED] drm_test_rect_intersect =============
[19:29:03] ================ drm_test_rect_calc_hscale ================
[19:29:03] [PASSED] normal use
[19:29:03] [PASSED] out of max range
[19:29:03] [PASSED] out of min range
[19:29:03] [PASSED] zero dst
[19:29:03] [PASSED] negative src
[19:29:03] [PASSED] negative dst
[19:29:03] ============ [PASSED] drm_test_rect_calc_hscale ============
[19:29:03] ================ drm_test_rect_calc_vscale ================
[19:29:03] [PASSED] normal use
[19:29:03] [PASSED] out of max range
[19:29:03] [PASSED] out of min range
[19:29:03] [PASSED] zero dst
[19:29:03] [PASSED] negative src
[19:29:03] [PASSED] negative dst
[19:29:03] ============ [PASSED] drm_test_rect_calc_vscale ============
[19:29:03] ================== drm_test_rect_rotate ===================
[19:29:03] [PASSED] reflect-x
[19:29:03] [PASSED] reflect-y
[19:29:03] [PASSED] rotate-0
[19:29:03] [PASSED] rotate-90
[19:29:03] [PASSED] rotate-180
[19:29:03] [PASSED] rotate-270
[19:29:03] ============== [PASSED] drm_test_rect_rotate ===============
[19:29:03] ================ drm_test_rect_rotate_inv =================
[19:29:03] [PASSED] reflect-x
[19:29:03] [PASSED] reflect-y
[19:29:03] [PASSED] rotate-0
[19:29:03] [PASSED] rotate-90
[19:29:03] [PASSED] rotate-180
[19:29:03] [PASSED] rotate-270
[19:29:03] ============ [PASSED] drm_test_rect_rotate_inv =============
[19:29:03] ==================== [PASSED] drm_rect =====================
[19:29:03] ============ drm_sysfb_modeset_test (1 subtest) ============
[19:29:03] ============ drm_test_sysfb_build_fourcc_list =============
[19:29:03] [PASSED] no native formats
[19:29:03] [PASSED] XRGB8888 as native format
[19:29:03] [PASSED] remove duplicates
[19:29:03] [PASSED] convert alpha formats
[19:29:03] [PASSED] random formats
[19:29:03] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[19:29:03] ============= [PASSED] drm_sysfb_modeset_test ==============
[19:29:03] ================== drm_fixp (2 subtests) ===================
[19:29:03] [PASSED] drm_test_int2fixp
[19:29:03] [PASSED] drm_test_sm2fixp
[19:29:03] ==================== [PASSED] drm_fixp =====================
[19:29:03] ============================================================
[19:29:03] Testing complete. Ran 639 tests: passed: 639
[19:29:03] Elapsed time: 25.733s total, 1.761s configuring, 23.808s building, 0.142s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[19:29:03] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:29:05] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:29:14] Starting KUnit Kernel (1/1)...
[19:29:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:29:14] ================= ttm_device (5 subtests) ==================
[19:29:14] [PASSED] ttm_device_init_basic
[19:29:14] [PASSED] ttm_device_init_multiple
[19:29:14] [PASSED] ttm_device_fini_basic
[19:29:14] [PASSED] ttm_device_init_no_vma_man
[19:29:14] ================== ttm_device_init_pools ==================
[19:29:14] [PASSED] No DMA allocations, no DMA32 required
[19:29:14] [PASSED] DMA allocations, DMA32 required
[19:29:14] [PASSED] No DMA allocations, DMA32 required
[19:29:14] [PASSED] DMA allocations, no DMA32 required
[19:29:14] ============== [PASSED] ttm_device_init_pools ==============
[19:29:14] =================== [PASSED] ttm_device ====================
[19:29:14] ================== ttm_pool (8 subtests) ===================
[19:29:14] ================== ttm_pool_alloc_basic ===================
[19:29:14] [PASSED] One page
[19:29:14] [PASSED] More than one page
[19:29:14] [PASSED] Above the allocation limit
[19:29:14] [PASSED] One page, with coherent DMA mappings enabled
[19:29:14] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:29:14] ============== [PASSED] ttm_pool_alloc_basic ===============
[19:29:14] ============== ttm_pool_alloc_basic_dma_addr ==============
[19:29:14] [PASSED] One page
[19:29:14] [PASSED] More than one page
[19:29:14] [PASSED] Above the allocation limit
[19:29:14] [PASSED] One page, with coherent DMA mappings enabled
[19:29:14] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:29:14] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[19:29:14] [PASSED] ttm_pool_alloc_order_caching_match
[19:29:14] [PASSED] ttm_pool_alloc_caching_mismatch
[19:29:14] [PASSED] ttm_pool_alloc_order_mismatch
[19:29:14] [PASSED] ttm_pool_free_dma_alloc
[19:29:14] [PASSED] ttm_pool_free_no_dma_alloc
[19:29:14] [PASSED] ttm_pool_fini_basic
[19:29:14] ==================== [PASSED] ttm_pool =====================
[19:29:14] ================ ttm_resource (8 subtests) =================
[19:29:14] ================= ttm_resource_init_basic =================
[19:29:14] [PASSED] Init resource in TTM_PL_SYSTEM
[19:29:14] [PASSED] Init resource in TTM_PL_VRAM
[19:29:14] [PASSED] Init resource in a private placement
[19:29:14] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[19:29:14] ============= [PASSED] ttm_resource_init_basic =============
[19:29:14] [PASSED] ttm_resource_init_pinned
[19:29:14] [PASSED] ttm_resource_fini_basic
[19:29:14] [PASSED] ttm_resource_manager_init_basic
[19:29:14] [PASSED] ttm_resource_manager_usage_basic
[19:29:14] [PASSED] ttm_resource_manager_set_used_basic
[19:29:14] [PASSED] ttm_sys_man_alloc_basic
[19:29:14] [PASSED] ttm_sys_man_free_basic
[19:29:14] ================== [PASSED] ttm_resource ===================
[19:29:14] =================== ttm_tt (15 subtests) ===================
[19:29:14] ==================== ttm_tt_init_basic ====================
[19:29:14] [PASSED] Page-aligned size
[19:29:14] [PASSED] Extra pages requested
[19:29:14] ================ [PASSED] ttm_tt_init_basic ================
[19:29:14] [PASSED] ttm_tt_init_misaligned
[19:29:14] [PASSED] ttm_tt_fini_basic
[19:29:14] [PASSED] ttm_tt_fini_sg
[19:29:14] [PASSED] ttm_tt_fini_shmem
[19:29:14] [PASSED] ttm_tt_create_basic
[19:29:14] [PASSED] ttm_tt_create_invalid_bo_type
[19:29:14] [PASSED] ttm_tt_create_ttm_exists
[19:29:14] [PASSED] ttm_tt_create_failed
[19:29:14] [PASSED] ttm_tt_destroy_basic
[19:29:14] [PASSED] ttm_tt_populate_null_ttm
[19:29:14] [PASSED] ttm_tt_populate_populated_ttm
[19:29:14] [PASSED] ttm_tt_unpopulate_basic
[19:29:14] [PASSED] ttm_tt_unpopulate_empty_ttm
[19:29:14] [PASSED] ttm_tt_swapin_basic
[19:29:14] ===================== [PASSED] ttm_tt ======================
[19:29:14] =================== ttm_bo (14 subtests) ===================
[19:29:14] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[19:29:14] [PASSED] Cannot be interrupted and sleeps
[19:29:14] [PASSED] Cannot be interrupted, locks straight away
[19:29:14] [PASSED] Can be interrupted, sleeps
[19:29:14] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[19:29:14] [PASSED] ttm_bo_reserve_locked_no_sleep
[19:29:14] [PASSED] ttm_bo_reserve_no_wait_ticket
[19:29:14] [PASSED] ttm_bo_reserve_double_resv
[19:29:14] [PASSED] ttm_bo_reserve_interrupted
[19:29:14] [PASSED] ttm_bo_reserve_deadlock
[19:29:14] [PASSED] ttm_bo_unreserve_basic
[19:29:14] [PASSED] ttm_bo_unreserve_pinned
[19:29:14] [PASSED] ttm_bo_unreserve_bulk
[19:29:14] [PASSED] ttm_bo_fini_basic
[19:29:14] [PASSED] ttm_bo_fini_shared_resv
[19:29:14] [PASSED] ttm_bo_pin_basic
[19:29:14] [PASSED] ttm_bo_pin_unpin_resource
[19:29:14] [PASSED] ttm_bo_multiple_pin_one_unpin
[19:29:14] ===================== [PASSED] ttm_bo ======================
[19:29:14] ============== ttm_bo_validate (22 subtests) ===============
[19:29:14] ============== ttm_bo_init_reserved_sys_man ===============
[19:29:14] [PASSED] Buffer object for userspace
[19:29:14] [PASSED] Kernel buffer object
[19:29:14] [PASSED] Shared buffer object
[19:29:14] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[19:29:14] ============== ttm_bo_init_reserved_mock_man ==============
[19:29:14] [PASSED] Buffer object for userspace
[19:29:14] [PASSED] Kernel buffer object
[19:29:14] [PASSED] Shared buffer object
[19:29:14] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[19:29:14] [PASSED] ttm_bo_init_reserved_resv
[19:29:14] ================== ttm_bo_validate_basic ==================
[19:29:14] [PASSED] Buffer object for userspace
[19:29:14] [PASSED] Kernel buffer object
[19:29:14] [PASSED] Shared buffer object
[19:29:14] ============== [PASSED] ttm_bo_validate_basic ==============
[19:29:14] [PASSED] ttm_bo_validate_invalid_placement
[19:29:14] ============= ttm_bo_validate_same_placement ==============
[19:29:14] [PASSED] System manager
[19:29:14] [PASSED] VRAM manager
[19:29:14] ========= [PASSED] ttm_bo_validate_same_placement ==========
[19:29:14] [PASSED] ttm_bo_validate_failed_alloc
[19:29:14] [PASSED] ttm_bo_validate_pinned
[19:29:14] [PASSED] ttm_bo_validate_busy_placement
[19:29:14] ================ ttm_bo_validate_multihop =================
[19:29:14] [PASSED] Buffer object for userspace
[19:29:14] [PASSED] Kernel buffer object
[19:29:14] [PASSED] Shared buffer object
[19:29:14] ============ [PASSED] ttm_bo_validate_multihop =============
[19:29:14] ========== ttm_bo_validate_no_placement_signaled ==========
[19:29:14] [PASSED] Buffer object in system domain, no page vector
[19:29:14] [PASSED] Buffer object in system domain with an existing page vector
[19:29:14] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[19:29:14] ======== ttm_bo_validate_no_placement_not_signaled ========
[19:29:14] [PASSED] Buffer object for userspace
[19:29:14] [PASSED] Kernel buffer object
[19:29:14] [PASSED] Shared buffer object
[19:29:14] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[19:29:14] [PASSED] ttm_bo_validate_move_fence_signaled
[19:29:14] ========= ttm_bo_validate_move_fence_not_signaled =========
[19:29:14] [PASSED] Waits for GPU
[19:29:14] [PASSED] Tries to lock straight away
[19:29:14] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[19:29:14] [PASSED] ttm_bo_validate_swapout
[19:29:14] [PASSED] ttm_bo_validate_happy_evict
[19:29:14] [PASSED] ttm_bo_validate_all_pinned_evict
[19:29:14] [PASSED] ttm_bo_validate_allowed_only_evict
[19:29:14] [PASSED] ttm_bo_validate_deleted_evict
[19:29:14] [PASSED] ttm_bo_validate_busy_domain_evict
[19:29:14] [PASSED] ttm_bo_validate_evict_gutting
[19:29:14] [PASSED] ttm_bo_validate_recrusive_evict
[19:29:14] ================= [PASSED] ttm_bo_validate =================
[19:29:14] ============================================================
[19:29:14] Testing complete. Ran 102 tests: passed: 102
[19:29:14] Elapsed time: 11.525s total, 1.793s configuring, 9.517s building, 0.178s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/4] drm/xe: Move engines' LRC programming RTP table off the stack
2026-06-16 19:21 ` [PATCH 3/4] drm/xe: Move engines' LRC programming RTP table off the stack Matt Roper
@ 2026-06-16 19:54 ` Matt Roper
2026-06-16 22:26 ` Gustavo Sousa
0 siblings, 1 reply; 14+ messages in thread
From: Matt Roper @ 2026-06-16 19:54 UTC (permalink / raw)
To: intel-xe; +Cc: Gustavo Sousa, Violet Monti
On Tue, Jun 16, 2026 at 12:21:53PM -0700, Matt Roper wrote:
> The 'lrc_setup' RTP table was allocated on the stack because it wasn't
> truly constant and needed to calculate the proper value for BLIT_CCTL at
> runtime based on other stack variables. Using the FIELD_SET_FUNC action
> allows us to make the table itself truly constant and move it off the
> stack; the BLIT_CCTL value is now calculated during RTP table
> processing.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_hw_engine.c | 60 ++++++++++++++++++++-------------------
> 1 file changed, 31 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 98265293f2dc..0b688b851b71 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -337,39 +337,41 @@ static bool xe_rtp_cfeg_wmtp_disabled(const struct xe_device *xe,
> return xe_mmio_read32(&hwe->gt->mmio, XEHP_FUSE4) & CFEG_WMTP_DISABLE;
> }
>
> +static u32 blit_cctl_val(struct xe_gt *gt, struct xe_hw_engine *hwe)
> +{
> + return REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, gt->mocs.uc_index) |
> + REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, gt->mocs.uc_index);
> +}
> +
> +const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
This (and the table in the next patch) should have been 'static.' I
initially had VISIBLE_IF_KUNIT here, but decided to drop that
until/unless we actually have kunit tests that operate on them.
Matt
> + /*
> + * Some blitter commands do not have a field for MOCS, those
> + * commands will use MOCS index pointed by BLIT_CCTL.
> + * BLIT_CCTL registers are needed to be programmed to un-cached.
> + */
> + { XE_RTP_NAME("BLIT_CCTL_default_MOCS"),
> + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
> + ENGINE_CLASS(COPY)),
> + XE_RTP_ACTIONS(FIELD_SET_FUNC(BLIT_CCTL(0),
> + BLIT_CCTL_DST_MOCS_MASK |
> + BLIT_CCTL_SRC_MOCS_MASK,
> + blit_cctl_val,
> + XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> + },
> + /* Disable WMTP if HW doesn't support it */
> + { XE_RTP_NAME("DISABLE_WMTP_ON_UNSUPPORTED_HW"),
> + XE_RTP_RULES(FUNC(xe_rtp_cfeg_wmtp_disabled)),
> + XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0),
> + PREEMPT_GPGPU_LEVEL_MASK,
> + PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
> + XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
> + },
> +);
> +
> static void
> hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
> {
> - struct xe_gt *gt = hwe->gt;
> - const u8 mocs_write_idx = gt->mocs.uc_index;
> - const u8 mocs_read_idx = gt->mocs.uc_index;
> - u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) |
> - REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx);
> struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
> - const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
> - /*
> - * Some blitter commands do not have a field for MOCS, those
> - * commands will use MOCS index pointed by BLIT_CCTL.
> - * BLIT_CCTL registers are needed to be programmed to un-cached.
> - */
> - { XE_RTP_NAME("BLIT_CCTL_default_MOCS"),
> - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
> - ENGINE_CLASS(COPY)),
> - XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0),
> - BLIT_CCTL_DST_MOCS_MASK |
> - BLIT_CCTL_SRC_MOCS_MASK,
> - blit_cctl_val,
> - XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> - },
> - /* Disable WMTP if HW doesn't support it */
> - { XE_RTP_NAME("DISABLE_WMTP_ON_UNSUPPORTED_HW"),
> - XE_RTP_RULES(FUNC(xe_rtp_cfeg_wmtp_disabled)),
> - XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0),
> - PREEMPT_GPGPU_LEVEL_MASK,
> - PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
> - XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
> - },
> - );
>
> xe_rtp_process_to_sr(&ctx, &lrc_setup, &hwe->reg_lrc, true);
> }
>
> --
> 2.54.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Xe.CI.BAT: success for Move RTP tables for engine init off the stack
2026-06-16 19:21 [PATCH 0/4] Move RTP tables for engine init off the stack Matt Roper
` (5 preceding siblings ...)
2026-06-16 19:29 ` ✓ CI.KUnit: success " Patchwork
@ 2026-06-16 20:19 ` Patchwork
2026-06-17 0:31 ` ✓ Xe.CI.FULL: " Patchwork
7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-06-16 20:19 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 959 bytes --]
== Series Details ==
Series: Move RTP tables for engine init off the stack
URL : https://patchwork.freedesktop.org/series/168630/
State : success
== Summary ==
CI Bug Log - changes from xe-5266-25914cd9b1df750ddca1d16601976d329e9823af_BAT -> xe-pw-168630v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-5266-25914cd9b1df750ddca1d16601976d329e9823af -> xe-pw-168630v1
IGT_8966: 9b33225c761bfe8c8c266bc56558d75c700029fb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-5266-25914cd9b1df750ddca1d16601976d329e9823af: 25914cd9b1df750ddca1d16601976d329e9823af
xe-pw-168630v1: 168630v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/index.html
[-- Attachment #2: Type: text/html, Size: 1507 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/4] drm/xe: Reformat xe_rtp_types.h
2026-06-16 19:21 ` [PATCH 1/4] drm/xe: Reformat xe_rtp_types.h Matt Roper
@ 2026-06-16 22:09 ` Gustavo Sousa
0 siblings, 0 replies; 14+ messages in thread
From: Gustavo Sousa @ 2026-06-16 22:09 UTC (permalink / raw)
To: Matt Roper, intel-xe; +Cc: Violet Monti, Matt Roper
Matt Roper <matthew.d.roper@intel.com> writes:
> Adjust whitespace / newlines in xe_rtp_types.h to make it easier to read
> and more consistent with other files. No functional change.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
> drivers/gpu/drm/xe/xe_rtp_types.h | 18 +++++++++++++-----
> 1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
> index 58018ae4f8cc..1d7c63d0ae94 100644
> --- a/drivers/gpu/drm/xe/xe_rtp_types.h
> +++ b/drivers/gpu/drm/xe/xe_rtp_types.h
> @@ -22,20 +22,24 @@ struct xe_gt;
> */
> struct xe_rtp_action {
> /** @reg: Register */
> - struct xe_reg reg;
> + struct xe_reg reg;
> +
> /**
> * @clr_bits: bits to clear when updating register. It's always a
> * superset of bits being modified
> */
> - u32 clr_bits;
> + u32 clr_bits;
> +
> /** @set_bits: bits to set when updating register */
> - u32 set_bits;
> + u32 set_bits;
> +
> #define XE_RTP_NOCHECK .read_mask = 0
> /** @read_mask: mask for bits to consider when reading value back */
> - u32 read_mask;
> + u32 read_mask;
> +
> #define XE_RTP_ACTION_FLAG_ENGINE_BASE BIT(0)
> /** @flags: flags to apply on rule evaluation or action */
> - u8 flags;
> + u8 flags;
> };
>
> enum {
> @@ -69,6 +73,7 @@ struct xe_rtp_rule {
> u8 platform;
> u8 subplatform;
> };
> +
> /*
> * MATCH_GRAPHICS_VERSION / XE_RTP_MATCH_GRAPHICS_VERSION_RANGE /
> * MATCH_MEDIA_VERSION / XE_RTP_MATCH_MEDIA_VERSION_RANGE
> @@ -78,15 +83,18 @@ struct xe_rtp_rule {
> #define XE_RTP_END_VERSION_UNDEFINED U32_MAX
> u32 ver_end;
> };
> +
> /* MATCH_STEP */
> struct {
> u8 step_start;
> u8 step_end;
> };
> +
> /* MATCH_ENGINE_CLASS / MATCH_NOT_ENGINE_CLASS */
> struct {
> u8 engine_class;
> };
> +
> /* MATCH_FUNC */
> bool (*match_func)(const struct xe_device *xe,
> const struct xe_gt *gt,
>
> --
> 2.54.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/4] drm/xe/rtp: Add FIELD_SET_FUNC RTP action
2026-06-16 19:21 ` [PATCH 2/4] drm/xe/rtp: Add FIELD_SET_FUNC RTP action Matt Roper
@ 2026-06-16 22:22 ` Gustavo Sousa
0 siblings, 0 replies; 14+ messages in thread
From: Gustavo Sousa @ 2026-06-16 22:22 UTC (permalink / raw)
To: Matt Roper, intel-xe; +Cc: Violet Monti, Matt Roper
Matt Roper <matthew.d.roper@intel.com> writes:
> Most of our RTP programming involves programming constant values into
> register fields. However there are a few cases (e.g., RING_CMD_CCTL
> programming) that rely on dynamic per-GT or per-engine checks to decide
> what value will be programmed. Add a FIELD_SET_FUNC RTP action which
> will call the provided function pointer once at RTP processing time to
> determine the appropriate value.
That's a great idea! I think it would be nice if we added a test case
for this in rtp_to_sr_cases[], for completeness.
More feedback below...
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_rtp.c | 10 ++++++++--
> drivers/gpu/drm/xe/xe_rtp.h | 21 +++++++++++++++++++++
> drivers/gpu/drm/xe/xe_rtp_types.h | 17 +++++++++++++++--
> 3 files changed, 44 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
> index 83a40e1f9528..6a8d6ea68f25 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.c
> +++ b/drivers/gpu/drm/xe/xe_rtp.c
> @@ -227,17 +227,23 @@ static bool rule_matches(const struct xe_device *xe,
>
> static void rtp_add_sr_entry(const struct xe_rtp_action *action,
> struct xe_gt *gt,
> + struct xe_hw_engine *hwe,
> u32 mmio_base,
> struct xe_reg_sr *sr)
> {
> struct xe_reg_sr_entry sr_entry = {
> .reg = action->reg,
> .clr_bits = action->clr_bits,
> - .set_bits = action->set_bits,
> .read_mask = action->read_mask,
> };
>
> + if (action->use_func)
> + sr_entry.set_bits = action->set_func(gt, hwe);
> + else
> + sr_entry.set_bits = action->set_bits;
> +
> sr_entry.reg.addr += mmio_base;
> +
> xe_reg_sr_add(sr, &sr_entry, gt);
> }
>
> @@ -259,7 +265,7 @@ static bool rtp_process_one_sr(const struct xe_rtp_entry_sr *entry,
> else
> mmio_base = 0;
>
> - rtp_add_sr_entry(action, gt, mmio_base, sr);
> + rtp_add_sr_entry(action, gt, hwe, mmio_base, sr);
> }
>
> return true;
> diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
> index 2cc65053cd07..e374b57a066c 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.h
> +++ b/drivers/gpu/drm/xe/xe_rtp.h
> @@ -322,6 +322,27 @@ struct xe_reg_sr;
> .clr_bits = (mask_bits_), .set_bits = (val_), \
> .read_mask = 0, ##__VA_ARGS__ }
>
> +/**
> + * XE_RTP_ACTION_FIELD_SET_FUNC: Set a bit range to the value returned by a function
> + * @reg_: Register
> + * @mask_bits_: Mask of bits to be changed in the register, forming a field
> + * @func_: Function that returns value to set in the field denoted by @mask_bits_
> + * @...: Additional fields to override in the struct xe_rtp_action entry
> + *
> + * @func_ will only be called a single time, when the RTP table is being
> + * processed. After processing, the value in the reg_sr entry is fixed and
> + * will not be re-evaluated.
> + *
> + * For masked registers this translates to a single write, while for other
> + * registers it's a RMW. The correspondent bspec notation is:
> + *
> + * REGNAME[<end>:<start>] = FUNC(GT, HWE)
I think we could avoid duplicating information in the doc by referring
to XE_RTP_ACTION_FIELD_SET().
So, before "@func_ will only be called (...)", we could add a paragraph
along the lines of:
"This macro works like XE_RTP_ACTION_FIELD_SET(), except that the
field value is evaluated by the time the RTP table is processed."
Then we can skip the last paragraph, which is a copy/paste from
XE_RTP_ACTION_FIELD_SET.
The change itself looks fine to me, so, unconditionally:
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
> + */
> +#define XE_RTP_ACTION_FIELD_SET_FUNC(reg_, mask_bits_, func_, ...) \
> + { .reg = XE_RTP_DROP_CAST(reg_), \
> + .clr_bits = mask_bits_, .set_func = func_, .use_func = 1, \
> + .read_mask = mask_bits_, ##__VA_ARGS__ }
> +
> /**
> * XE_RTP_ACTION_WHITELIST - Add register to userspace whitelist
> * @reg_: Register
> diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
> index 1d7c63d0ae94..b78092fa06e0 100644
> --- a/drivers/gpu/drm/xe/xe_rtp_types.h
> +++ b/drivers/gpu/drm/xe/xe_rtp_types.h
> @@ -30,8 +30,14 @@ struct xe_rtp_action {
> */
> u32 clr_bits;
>
> - /** @set_bits: bits to set when updating register */
> - u32 set_bits;
> + union {
> + /** @set_bits: bits to set when updating register */
> + u32 set_bits;
> +
> + /** @set_func: function to provide bits to set when updating register */
> + u32 (*set_func)(struct xe_gt *gt,
> + struct xe_hw_engine *hwe);
> + };
>
> #define XE_RTP_NOCHECK .read_mask = 0
> /** @read_mask: mask for bits to consider when reading value back */
> @@ -40,6 +46,13 @@ struct xe_rtp_action {
> #define XE_RTP_ACTION_FLAG_ENGINE_BASE BIT(0)
> /** @flags: flags to apply on rule evaluation or action */
> u8 flags;
> +
> + /**
> + * @use_func:
> + * Internal flag indicating @set_func should be called instead of
> + * using @set_bits.
> + */
> + u8 use_func:1;
> };
>
> enum {
>
> --
> 2.54.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/4] drm/xe: Move engines' LRC programming RTP table off the stack
2026-06-16 19:54 ` Matt Roper
@ 2026-06-16 22:26 ` Gustavo Sousa
0 siblings, 0 replies; 14+ messages in thread
From: Gustavo Sousa @ 2026-06-16 22:26 UTC (permalink / raw)
To: Matt Roper, intel-xe; +Cc: Violet Monti
Matt Roper <matthew.d.roper@intel.com> writes:
> On Tue, Jun 16, 2026 at 12:21:53PM -0700, Matt Roper wrote:
>> The 'lrc_setup' RTP table was allocated on the stack because it wasn't
>> truly constant and needed to calculate the proper value for BLIT_CCTL at
>> runtime based on other stack variables. Using the FIELD_SET_FUNC action
>> allows us to make the table itself truly constant and move it off the
>> stack; the BLIT_CCTL value is now calculated during RTP table
>> processing.
>>
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_hw_engine.c | 60 ++++++++++++++++++++-------------------
>> 1 file changed, 31 insertions(+), 29 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
>> index 98265293f2dc..0b688b851b71 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
>> @@ -337,39 +337,41 @@ static bool xe_rtp_cfeg_wmtp_disabled(const struct xe_device *xe,
>> return xe_mmio_read32(&hwe->gt->mmio, XEHP_FUSE4) & CFEG_WMTP_DISABLE;
>> }
>>
>> +static u32 blit_cctl_val(struct xe_gt *gt, struct xe_hw_engine *hwe)
>> +{
>> + return REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, gt->mocs.uc_index) |
>> + REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, gt->mocs.uc_index);
>> +}
>> +
>> +const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
>
> This (and the table in the next patch) should have been 'static.' I
With the addition of the "static" keyword for lrc_setup,
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
> initially had VISIBLE_IF_KUNIT here, but decided to drop that
> until/unless we actually have kunit tests that operate on them.
>
>
> Matt
>
>> + /*
>> + * Some blitter commands do not have a field for MOCS, those
>> + * commands will use MOCS index pointed by BLIT_CCTL.
>> + * BLIT_CCTL registers are needed to be programmed to un-cached.
>> + */
>> + { XE_RTP_NAME("BLIT_CCTL_default_MOCS"),
>> + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
>> + ENGINE_CLASS(COPY)),
>> + XE_RTP_ACTIONS(FIELD_SET_FUNC(BLIT_CCTL(0),
>> + BLIT_CCTL_DST_MOCS_MASK |
>> + BLIT_CCTL_SRC_MOCS_MASK,
>> + blit_cctl_val,
>> + XE_RTP_ACTION_FLAG(ENGINE_BASE)))
>> + },
>> + /* Disable WMTP if HW doesn't support it */
>> + { XE_RTP_NAME("DISABLE_WMTP_ON_UNSUPPORTED_HW"),
>> + XE_RTP_RULES(FUNC(xe_rtp_cfeg_wmtp_disabled)),
>> + XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0),
>> + PREEMPT_GPGPU_LEVEL_MASK,
>> + PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
>> + XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
>> + },
>> +);
>> +
>> static void
>> hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
>> {
>> - struct xe_gt *gt = hwe->gt;
>> - const u8 mocs_write_idx = gt->mocs.uc_index;
>> - const u8 mocs_read_idx = gt->mocs.uc_index;
>> - u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) |
>> - REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx);
>> struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>> - const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
>> - /*
>> - * Some blitter commands do not have a field for MOCS, those
>> - * commands will use MOCS index pointed by BLIT_CCTL.
>> - * BLIT_CCTL registers are needed to be programmed to un-cached.
>> - */
>> - { XE_RTP_NAME("BLIT_CCTL_default_MOCS"),
>> - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
>> - ENGINE_CLASS(COPY)),
>> - XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0),
>> - BLIT_CCTL_DST_MOCS_MASK |
>> - BLIT_CCTL_SRC_MOCS_MASK,
>> - blit_cctl_val,
>> - XE_RTP_ACTION_FLAG(ENGINE_BASE)))
>> - },
>> - /* Disable WMTP if HW doesn't support it */
>> - { XE_RTP_NAME("DISABLE_WMTP_ON_UNSUPPORTED_HW"),
>> - XE_RTP_RULES(FUNC(xe_rtp_cfeg_wmtp_disabled)),
>> - XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0),
>> - PREEMPT_GPGPU_LEVEL_MASK,
>> - PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
>> - XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
>> - },
>> - );
>>
>> xe_rtp_process_to_sr(&ctx, &lrc_setup, &hwe->reg_lrc, true);
>> }
>>
>> --
>> 2.54.0
>>
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 4/4] drm/xe: Move engines' non-LRC programming RTP table off the stack
2026-06-16 19:21 ` [PATCH 4/4] drm/xe: Move engines' non-LRC " Matt Roper
@ 2026-06-16 22:33 ` Gustavo Sousa
0 siblings, 0 replies; 14+ messages in thread
From: Gustavo Sousa @ 2026-06-16 22:33 UTC (permalink / raw)
To: Matt Roper, intel-xe; +Cc: Violet Monti, Matt Roper
Matt Roper <matthew.d.roper@intel.com> writes:
> The 'engine_sr' RTP table was allocated on the stack because it wasn't
> truly constant and needed to calculate the proper value for
> RING_CMD_CCTL at runtime based on other stack variables. Using the
> FIELD_SET_FUNC action allows us to make the table itself truly constant
> and move it off the stack; the RING_CMD_CCTL value is now calculated
> during RTP table processing.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_hw_engine.c | 158 ++++++++++++++++++++------------------
> 1 file changed, 82 insertions(+), 76 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 0b688b851b71..987cd1a49f03 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -387,86 +387,92 @@ void xe_hw_engine_setup_reg_lrc(struct xe_hw_engine *hwe)
> xe_tuning_process_lrc(hwe);
> }
>
> +/*
> + * RING_CMD_CCTL specifies the default MOCS entry that will be
> + * used by the command streamer when executing commands that
> + * don't have a way to explicitly specify a MOCS setting.
> + * The default should usually reference whichever MOCS entry
> + * corresponds to uncached behavior, although use of a WB cached
> + * entry is recommended by the spec in certain circumstances on
> + * specific platforms.
> + * Bspec: 72161
> + */
> +static u32 ring_cmd_cctl_val(struct xe_gt *gt, struct xe_hw_engine *hwe)
> +{
> + struct xe_device *xe = gt_to_xe(gt);
> + u8 mocs_read_idx = gt->mocs.uc_index;
> +
> + if (hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) &&
> + (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC))
> + mocs_read_idx = gt->mocs.wb_index;
> +
> + return REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, gt->mocs.uc_index) |
> + REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);
> +}
> +
> +const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR(
With the addition of the "static" keyword for engine_sr,
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
> + { XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"),
> + XE_RTP_RULES(FUNC(xe_rtp_match_always)),
> + XE_RTP_ACTIONS(FIELD_SET_FUNC(RING_CMD_CCTL(0),
> + CMD_CCTL_WRITE_OVERRIDE_MASK |
> + CMD_CCTL_READ_OVERRIDE_MASK,
> + ring_cmd_cctl_val,
> + XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> + },
> + { XE_RTP_NAME("Disable HW status page updates for interrupts"),
> + XE_RTP_RULES(FUNC(xe_rtp_match_always)),
> + XE_RTP_ACTIONS(SET(RING_HWSTAM(0), ~0x0,
> + XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> + },
> + { XE_RTP_NAME("Disable engine 'legacy' mode"),
> + XE_RTP_RULES(FUNC(xe_rtp_match_always)),
> + XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_DISABLE_LEGACY_MODE,
> + XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> + },
> + /*
> + * To allow the GSC engine to go idle on MTL we need to enable
> + * idle messaging and set the hysteresis value (we use 0xA=5us
> + * as recommended in spec). On platforms after MTL this is
> + * enabled by default.
> + */
> + { XE_RTP_NAME("MTL GSCCS IDLE MSG enable"),
> + XE_RTP_RULES(MEDIA_VERSION(1300), ENGINE_CLASS(OTHER)),
> + XE_RTP_ACTIONS(CLR(RING_PSMI_CTL(0),
> + IDLE_MSG_DISABLE,
> + XE_RTP_ACTION_FLAG(ENGINE_BASE)),
> + FIELD_SET(RING_PWRCTX_MAXCNT(0),
> + IDLE_WAIT_TIME,
> + 0xA,
> + XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> + },
> + /* Enable Priority Mem Read */
> + { XE_RTP_NAME("Priority_Mem_Read"),
> + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
> + XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ,
> + XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> + },
> + { XE_RTP_NAME("Enable CCS Engine(s)"),
> + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, XE_RTP_END_VERSION_UNDEFINED),
> + FUNC(xe_rtp_match_first_render_or_compute)),
> + XE_RTP_ACTIONS(SET(RCU_MODE, RCU_MODE_CCS_ENABLE))
> + },
> + /* Use Fixed slice CCS mode */
> + { XE_RTP_NAME("RCU_MODE_FIXED_SLICE_CCS_MODE"),
> + XE_RTP_RULES(FUNC(xe_hw_engine_match_fixed_cslice_mode)),
> + XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE,
> + RCU_MODE_FIXED_SLICE_CCS_MODE))
> + },
> + { XE_RTP_NAME("Enable MSI-X interrupt support"),
> + XE_RTP_RULES(FUNC(xe_rtp_match_has_msix)),
> + XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE,
> + XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> + },
> +);
> +
> static void
> hw_engine_setup_default_state(struct xe_hw_engine *hwe)
> {
> - struct xe_gt *gt = hwe->gt;
> - struct xe_device *xe = gt_to_xe(gt);
> - /*
> - * RING_CMD_CCTL specifies the default MOCS entry that will be
> - * used by the command streamer when executing commands that
> - * don't have a way to explicitly specify a MOCS setting.
> - * The default should usually reference whichever MOCS entry
> - * corresponds to uncached behavior, although use of a WB cached
> - * entry is recommended by the spec in certain circumstances on
> - * specific platforms.
> - * Bspec: 72161
> - */
> - const u8 mocs_write_idx = gt->mocs.uc_index;
> - const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) &&
> - (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) ?
> - gt->mocs.wb_index : gt->mocs.uc_index;
> - u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |
> - REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);
> struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
> - const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR(
> - { XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"),
> - XE_RTP_RULES(FUNC(xe_rtp_match_always)),
> - XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0),
> - CMD_CCTL_WRITE_OVERRIDE_MASK |
> - CMD_CCTL_READ_OVERRIDE_MASK,
> - ring_cmd_cctl_val,
> - XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> - },
> - { XE_RTP_NAME("Disable HW status page updates for interrupts"),
> - XE_RTP_RULES(FUNC(xe_rtp_match_always)),
> - XE_RTP_ACTIONS(SET(RING_HWSTAM(0), ~0x0,
> - XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> - },
> - { XE_RTP_NAME("Disable engine 'legacy' mode"),
> - XE_RTP_RULES(FUNC(xe_rtp_match_always)),
> - XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_DISABLE_LEGACY_MODE,
> - XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> - },
> - /*
> - * To allow the GSC engine to go idle on MTL we need to enable
> - * idle messaging and set the hysteresis value (we use 0xA=5us
> - * as recommended in spec). On platforms after MTL this is
> - * enabled by default.
> - */
> - { XE_RTP_NAME("MTL GSCCS IDLE MSG enable"),
> - XE_RTP_RULES(MEDIA_VERSION(1300), ENGINE_CLASS(OTHER)),
> - XE_RTP_ACTIONS(CLR(RING_PSMI_CTL(0),
> - IDLE_MSG_DISABLE,
> - XE_RTP_ACTION_FLAG(ENGINE_BASE)),
> - FIELD_SET(RING_PWRCTX_MAXCNT(0),
> - IDLE_WAIT_TIME,
> - 0xA,
> - XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> - },
> - /* Enable Priority Mem Read */
> - { XE_RTP_NAME("Priority_Mem_Read"),
> - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
> - XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ,
> - XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> - },
> - { XE_RTP_NAME("Enable CCS Engine(s)"),
> - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, XE_RTP_END_VERSION_UNDEFINED),
> - FUNC(xe_rtp_match_first_render_or_compute)),
> - XE_RTP_ACTIONS(SET(RCU_MODE, RCU_MODE_CCS_ENABLE))
> - },
> - /* Use Fixed slice CCS mode */
> - { XE_RTP_NAME("RCU_MODE_FIXED_SLICE_CCS_MODE"),
> - XE_RTP_RULES(FUNC(xe_hw_engine_match_fixed_cslice_mode)),
> - XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE,
> - RCU_MODE_FIXED_SLICE_CCS_MODE))
> - },
> - { XE_RTP_NAME("Enable MSI-X interrupt support"),
> - XE_RTP_RULES(FUNC(xe_rtp_match_has_msix)),
> - XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE,
> - XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> - },
> - );
>
> xe_rtp_process_to_sr(&ctx, &engine_sr, &hwe->reg_sr, false);
> }
>
> --
> 2.54.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Xe.CI.FULL: success for Move RTP tables for engine init off the stack
2026-06-16 19:21 [PATCH 0/4] Move RTP tables for engine init off the stack Matt Roper
` (6 preceding siblings ...)
2026-06-16 20:19 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-06-17 0:31 ` Patchwork
7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-06-17 0:31 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 15478 bytes --]
== Series Details ==
Series: Move RTP tables for engine init off the stack
URL : https://patchwork.freedesktop.org/series/168630/
State : success
== Summary ==
CI Bug Log - changes from xe-5266-25914cd9b1df750ddca1d16601976d329e9823af_FULL -> xe-pw-168630v1_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-168630v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_bw@linear-tiling-2-displays-target-3840x2160p:
- shard-bmg: NOTRUN -> [SKIP][1] ([Intel XE#367])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_bw@linear-tiling-2-displays-target-3840x2160p.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][2] ([Intel XE#2887])
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc:
- shard-lnl: NOTRUN -> [SKIP][3] ([Intel XE#2887])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-lnl-3/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][4] ([Intel XE#3432])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_chamelium_hpd@hdmi-hpd-after-hibernate:
- shard-bmg: NOTRUN -> [SKIP][5] ([Intel XE#2252])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_chamelium_hpd@hdmi-hpd-after-hibernate.html
* igt@kms_cursor_crc@cursor-offscreen-256x85:
- shard-lnl: NOTRUN -> [SKIP][6] ([Intel XE#1424])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-lnl-3/igt@kms_cursor_crc@cursor-offscreen-256x85.html
* igt@kms_dsc@dsc-with-formats:
- shard-bmg: NOTRUN -> [SKIP][7] ([Intel XE#8265])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_dsc@dsc-with-formats.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-bmg: NOTRUN -> [SKIP][8] ([Intel XE#6126] / [Intel XE#776])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop:
- shard-lnl: NOTRUN -> [SKIP][9] ([Intel XE#1421]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-lnl-3/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: [PASS][10] -> [FAIL][11] ([Intel XE#301]) +1 other test fail
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5266-25914cd9b1df750ddca1d16601976d329e9823af/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][12] ([Intel XE#4141]) +1 other test skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-tiling-y:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#2352] / [Intel XE#7399])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-move:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#2311]) +3 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#7061] / [Intel XE#7356])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrshdr-argb161616f-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][16] ([Intel XE#7061])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrshdr-argb161616f-draw-blt.html
* igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-pri-indfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][17] ([Intel XE#7905]) +3 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-lnl-3/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2313]) +3 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f:
- shard-bmg: [PASS][19] -> [SKIP][20] ([Intel XE#7915]) +1 other test skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5266-25914cd9b1df750ddca1d16601976d329e9823af/shard-bmg-3/igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-8/igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f.html
* igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#7283])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html
* igt@kms_pm_backlight@fade:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_pm_backlight@fade.html
* igt@kms_psr@fbc-pr-sprite-blt:
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#2234] / [Intel XE#2850])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_psr@fbc-pr-sprite-blt.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-lnl: NOTRUN -> [SKIP][24] ([Intel XE#1127] / [Intel XE#5813])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-lnl-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#3904] / [Intel XE#7342])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-lnl: NOTRUN -> [SKIP][26] ([Intel XE#1499])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-lnl-3/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@xe_eudebug_online@debugger-reopen:
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#7636])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@xe_eudebug_online@debugger-reopen.html
* igt@xe_exec_balancer@many-execqueues-cm-virtual-basic:
- shard-lnl: NOTRUN -> [SKIP][28] ([Intel XE#7482])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-lnl-3/igt@xe_exec_balancer@many-execqueues-cm-virtual-basic.html
* igt@xe_exec_fault_mode@twice-multi-queue-rebind-imm:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#7136])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@xe_exec_fault_mode@twice-multi-queue-rebind-imm.html
* igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind:
- shard-lnl: NOTRUN -> [SKIP][30] ([Intel XE#7136])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-lnl-3/igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind.html
* igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-dyn-priority-smem:
- shard-lnl: NOTRUN -> [SKIP][31] ([Intel XE#6874])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-lnl-3/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-dyn-priority-smem.html
* igt@xe_exec_multi_queue@max-queues-close-fd-smem:
- shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#6874]) +2 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@xe_exec_multi_queue@max-queues-close-fd-smem.html
* igt@xe_exec_reset@cm-multi-queue-cat-error:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#7866])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@xe_exec_reset@cm-multi-queue-cat-error.html
* igt@xe_multigpu_svm@mgpu-atomic-op-conflict:
- shard-bmg: NOTRUN -> [SKIP][34] ([Intel XE#6964])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@xe_multigpu_svm@mgpu-atomic-op-conflict.html
* igt@xe_pm@d3cold-multiple-execs:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#2284] / [Intel XE#7370])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@xe_pm@d3cold-multiple-execs.html
* igt@xe_sriov_vfio@bind-unbind-vfs:
- shard-lnl: NOTRUN -> [SKIP][36] ([Intel XE#7724])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-lnl-3/igt@xe_sriov_vfio@bind-unbind-vfs.html
* igt@xe_wedged@wedged-mode-toggle:
- shard-bmg: [PASS][37] -> [ABORT][38] ([Intel XE#8007])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5266-25914cd9b1df750ddca1d16601976d329e9823af/shard-bmg-1/igt@xe_wedged@wedged-mode-toggle.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-7/igt@xe_wedged@wedged-mode-toggle.html
#### Possible fixes ####
* igt@kms_cursor_edge_walk@64x64-top-edge:
- shard-bmg: [INCOMPLETE][39] -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5266-25914cd9b1df750ddca1d16601976d329e9823af/shard-bmg-5/igt@kms_cursor_edge_walk@64x64-top-edge.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-9/igt@kms_cursor_edge_walk@64x64-top-edge.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-lnl: [FAIL][41] ([Intel XE#301]) -> [PASS][42] +1 other test pass
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5266-25914cd9b1df750ddca1d16601976d329e9823af/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_hdr@static-swap@pipe-a-hdmi-a-3-xrgb2101010:
- shard-bmg: [SKIP][43] ([Intel XE#7915]) -> [PASS][44] +1 other test pass
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5266-25914cd9b1df750ddca1d16601976d329e9823af/shard-bmg-2/igt@kms_hdr@static-swap@pipe-a-hdmi-a-3-xrgb2101010.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-5/igt@kms_hdr@static-swap@pipe-a-hdmi-a-3-xrgb2101010.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-bmg: [INCOMPLETE][45] ([Intel XE#6321]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5266-25914cd9b1df750ddca1d16601976d329e9823af/shard-bmg-8/igt@xe_evict@evict-mixed-many-threads-small.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/shard-bmg-1/igt@xe_evict@evict-mixed-many-threads-small.html
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
[Intel XE#6126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6126
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
[Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
[Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
[Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
[Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
[Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
[Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
[Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
[Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
[Intel XE#7724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7724
[Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
[Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
[Intel XE#7866]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7866
[Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
[Intel XE#7915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7915
[Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
[Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
Build changes
-------------
* Linux: xe-5266-25914cd9b1df750ddca1d16601976d329e9823af -> xe-pw-168630v1
IGT_8966: 9b33225c761bfe8c8c266bc56558d75c700029fb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-5266-25914cd9b1df750ddca1d16601976d329e9823af: 25914cd9b1df750ddca1d16601976d329e9823af
xe-pw-168630v1: 168630v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168630v1/index.html
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Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-06-16 19:21 [PATCH 0/4] Move RTP tables for engine init off the stack Matt Roper
2026-06-16 19:21 ` [PATCH 1/4] drm/xe: Reformat xe_rtp_types.h Matt Roper
2026-06-16 22:09 ` Gustavo Sousa
2026-06-16 19:21 ` [PATCH 2/4] drm/xe/rtp: Add FIELD_SET_FUNC RTP action Matt Roper
2026-06-16 22:22 ` Gustavo Sousa
2026-06-16 19:21 ` [PATCH 3/4] drm/xe: Move engines' LRC programming RTP table off the stack Matt Roper
2026-06-16 19:54 ` Matt Roper
2026-06-16 22:26 ` Gustavo Sousa
2026-06-16 19:21 ` [PATCH 4/4] drm/xe: Move engines' non-LRC " Matt Roper
2026-06-16 22:33 ` Gustavo Sousa
2026-06-16 19:28 ` ✗ CI.checkpatch: warning for Move RTP tables for engine init " Patchwork
2026-06-16 19:29 ` ✓ CI.KUnit: success " Patchwork
2026-06-16 20:19 ` ✓ Xe.CI.BAT: " Patchwork
2026-06-17 0:31 ` ✓ Xe.CI.FULL: " Patchwork
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