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* [PATCH 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
@ 2025-12-08  6:16 Harish Chegondi
  2025-12-08  6:32 ` ✓ CI.KUnit: success for series starting with [1/1] " Patchwork
                   ` (4 more replies)
  0 siblings, 5 replies; 12+ messages in thread
From: Harish Chegondi @ 2025-12-08  6:16 UTC (permalink / raw)
  To: intel-xe; +Cc: Harish Chegondi, Ashutosh Dixit, Umesh Nerlige Ramappa

If a reset (GT or engine) happens during EU stall data sampling, all the
EU stall registers can get reset to 0. This will result in EU stall data
buffers' read and write pointer register values to be out of sync with
the cached values. This can result in read() returning invalid data. To
prevent this, check the value of a EU stall base register. If it is zero,
it indicates a reset may have happened that wiped the register to zero.
If this happens, return EBADFD from read() upon which the user space
should close the fd and open a new fd for a new EU stall data
collection session.

Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
---
 drivers/gpu/drm/xe/xe_eu_stall.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
index 97dfb7945b7a..02c0beb4559f 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.c
+++ b/drivers/gpu/drm/xe/xe_eu_stall.c
@@ -541,9 +541,24 @@ static ssize_t xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *st
 	size_t total_size = 0;
 	u16 group, instance;
 	unsigned int xecore;
+	u32 base_reg_value;
 	int ret = 0;
 
 	mutex_lock(&stream->xecore_buf_lock);
+	/* If a GT or engine reset happens during EU stall data sampling,
+	 * all EU stall registers get reset to 0 and the cached values of
+	 * EU stall data buffers' read and write pointers are out of sync
+	 * with the register values. This can cause invalid data to be
+	 * returned from read(). To prevent this, check the value of a
+	 * EU stall base register. If it is zero, return -EBADFD. The
+	 * user is expected to close the fd and open a new fd.
+	 */
+	base_reg_value = xe_gt_mcr_unicast_read_any(gt, XEHPC_EUSTALL_BASE);
+	if (unlikely(!base_reg_value)) {
+		xe_gt_dbg(gt, "EU stall base register has been reset to 0\n");
+		mutex_unlock(&stream->xecore_buf_lock);
+		return -EBADFD;
+	}
 	if (bitmap_weight(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS)) {
 		if (!stream->data_drop.reported_to_user) {
 			stream->data_drop.reported_to_user = true;
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
@ 2025-10-01  6:38 Harish Chegondi
  0 siblings, 0 replies; 12+ messages in thread
From: Harish Chegondi @ 2025-10-01  6:38 UTC (permalink / raw)
  To: intel-xe; +Cc: Harish Chegondi, Ashutosh Dixit

If a reset (GT or engine) happens during EU stall data sampling, all the
EU stall registers can get reset to 0. This will result in EU stall data
buffers' read and write pointer register values to be out of sync with
the cached values. This can result in read() returning invalid data. To
prevent this, check the value of a EU stall base register. If it is zero,
it indicates a reset may have happened that wiped the register to zero.
If this happens, return EBADFD from read() upon which the user space
should close the fd and open a new fd for a new EU stall data
collection session.

Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
---
 drivers/gpu/drm/xe/xe_eu_stall.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
index f5cfdf29fde3..39d5f2abe73b 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.c
+++ b/drivers/gpu/drm/xe/xe_eu_stall.c
@@ -516,9 +516,24 @@ static ssize_t xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *st
 	size_t total_size = 0;
 	u16 group, instance;
 	unsigned int xecore;
+	u32 base_reg_value;
 	int ret = 0;
 
 	mutex_lock(&stream->xecore_buf_lock);
+	/* If a GT or engine reset happens during EU stall data sampling,
+	 * all EU stall registers get reset to 0 and the cached values of
+	 * EU stall data buffers' read and write pointers are out of sync
+	 * with the register values. This can cause invalid data to be
+	 * returned from read(). To prevent this, check the value of a
+	 * EU stall base register. If it is zero, return -EBADFD. The
+	 * user is expected to close the fd and open a new fd.
+	 */
+	base_reg_value = xe_gt_mcr_unicast_read_any(gt, XEHPC_EUSTALL_BASE);
+	if (unlikely(!base_reg_value)) {
+		xe_gt_dbg(gt, "EU stall base register has been reset to 0\n");
+		mutex_unlock(&stream->xecore_buf_lock);
+		return -EBADFD;
+	}
 	if (bitmap_weight(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS)) {
 		if (!stream->data_drop.reported_to_user) {
 			stream->data_drop.reported_to_user = true;
-- 
2.51.0


^ permalink raw reply related	[flat|nested] 12+ messages in thread
end of thread, other threads:[~2025-12-24  1:48 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-12-08  6:16 [PATCH 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset Harish Chegondi
2025-12-08  6:32 ` ✓ CI.KUnit: success for series starting with [1/1] " Patchwork
2025-12-08  7:56 ` ✓ Xe.CI.BAT: " Patchwork
2025-12-08  8:48 ` ✗ Xe.CI.Full: failure " Patchwork
2025-12-12 21:18 ` [PATCH 1/1] " Dixit, Ashutosh
2025-12-16 23:53   ` Harish Chegondi
2025-12-18 19:53 ` Dixit, Ashutosh
2025-12-22 22:37   ` Harish Chegondi
2025-12-23  5:08     ` Dixit, Ashutosh
2025-12-23 23:39       ` Harish Chegondi
2025-12-24  1:47         ` Dixit, Ashutosh
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2025-10-01  6:38 Harish Chegondi

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