Re: [PATCH 3/3] drm/xe: Mark ROW_CHICKEN5 as a masked register

[Gustavo Sousa <gustavo.sousa@intel.com>]

Matt Roper <matthew.d.roper@intel.com> writes:

> ROW_CHICKEN5 is a masked register (i.e., to adjust the value of any of
> the lower 16 bits, the corresponding bit in the upper 16 bits must also
> be set).  Add the XE_REG_OPTION_MASKED to its definition; failure to do
> so will cause workaround updates of this register to not apply properly.
>
> Bspec: 56853
> Fixes: 835cd6cbb0d0 ("drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10")
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

It appears there was a Bspec update that accidentally dropped the
mask bits from the register description and then later on those were
added back (although the "masked" access tag remained).  Maybe it is
likely that we were in between those those changes when this programming
was added to the driver?

--
Gustavo Sousa

> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index aa267c2f6162..a4472b7acb18 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -584,7 +584,7 @@
>  #define   DISABLE_128B_EVICTION_COMMAND_UDW	REG_BIT(36 - 32)
>  #define   LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE	REG_BIT(35 - 32)
>  
> -#define ROW_CHICKEN5				XE_REG_MCR(0xe7f0)
> +#define ROW_CHICKEN5				XE_REG_MCR(0xe7f0, XE_REG_OPTION_MASKED)
>  #define   CPSS_AWARE_DIS			REG_BIT(3)
>  
>  #define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
>
> -- 
> 2.53.0