* [PATCH 0/8] drm/{i915,xe}: refactor register helpers
@ 2026-02-25 17:57 Jani Nikula
2026-02-25 17:57 ` [PATCH 1/8] drm/i915/reg: make masked field helpers constexpr Jani Nikula
` (12 more replies)
0 siblings, 13 replies; 23+ messages in thread
From: Jani Nikula @ 2026-02-25 17:57 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, rodrigo.vivi
I realized xe_reg_defs.h subtly pulls in i915_reg_defs.h from i915 via
the compat headers, which is ugly and wrong to say the least, and then
xe uses the macros all over the place.
Clean this up by creating two shared headers under include/drm/intel,
with some related cleanups on top.
BR,
Jani.
Jani Nikula (8):
drm/i915/reg: make masked field helpers constexpr
drm/i915/lrc: switch to _MASKED_BIT_ENABLE() and _MASKED_BIT_DISABLE()
drm/{i915,xe}/reg: rename masked field helpers REG_MASKED_FIELD*()
drm/i915/perf: prefer REG_MASKED_FIELD_ENABLE() and
REG_MASKED_FIELD_DISABLE()
drm/xe/oa: prefer REG_MASKED_FIELD_ENABLE() and
REG_MASKED_FIELD_DISABLE()
drm/intel: add reg_bits.h for the various register content helpers
drm/intel: add pick.h for the various "picker" helpers
drm/i915/gt: prefer _PICK_EVEN() over _PICK()
drivers/gpu/drm/i915/display/i9xx_wm.c | 8 +-
.../gpu/drm/i915/display/intel_display_irq.c | 4 +-
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 10 +-
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 6 +-
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 6 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 21 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 22 +--
drivers/gpu/drm/i915/gt/intel_reset.c | 4 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 19 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +-
drivers/gpu/drm/i915/gvt/handlers.c | 10 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
drivers/gpu/drm/i915/gvt/reg.h | 4 +-
drivers/gpu/drm/i915/i915_perf.c | 34 ++--
drivers/gpu/drm/i915/i915_reg_defs.h | 179 +-----------------
drivers/gpu/drm/i915/intel_clock_gating.c | 38 ++--
drivers/gpu/drm/i915/intel_uncore.c | 4 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 4 +-
.../drm/xe/compat-i915-headers/intel_uncore.h | 1 +
drivers/gpu/drm/xe/regs/xe_reg_defs.h | 5 +-
drivers/gpu/drm/xe/xe_eu_stall.c | 20 +-
drivers/gpu/drm/xe/xe_execlist.c | 6 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 8 +-
drivers/gpu/drm/xe/xe_lrc.c | 12 +-
drivers/gpu/drm/xe/xe_oa.c | 42 ++--
drivers/gpu/drm/xe/xe_pxp.c | 4 +-
drivers/gpu/drm/xe/xe_uc_fw.c | 4 +-
include/drm/intel/pick.h | 51 +++++
include/drm/intel/reg_bits.h | 139 ++++++++++++++
34 files changed, 362 insertions(+), 349 deletions(-)
create mode 100644 include/drm/intel/pick.h
create mode 100644 include/drm/intel/reg_bits.h
--
2.47.3
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 1/8] drm/i915/reg: make masked field helpers constexpr 2026-02-25 17:57 [PATCH 0/8] drm/{i915,xe}: refactor register helpers Jani Nikula @ 2026-02-25 17:57 ` Jani Nikula 2026-03-02 20:08 ` Michał Grzelak 2026-02-25 17:57 ` [PATCH 2/8] drm/i915/lrc: switch to _MASKED_BIT_ENABLE() and _MASKED_BIT_DISABLE() Jani Nikula ` (11 subsequent siblings) 12 siblings, 1 reply; 23+ messages in thread From: Jani Nikula @ 2026-02-25 17:57 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula, rodrigo.vivi Make it possible to use _MASKED_FIELD(), _MASKED_BIT_ENABLE() and _MASKED_BIT_DISABLE() in contexts that require integer constant expressions. This increases their usefulness at the small cost of making the warnings from build time checks less helpful. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_reg_defs.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h index e81fac8ab51b..c39b3a5dafe6 100644 --- a/drivers/gpu/drm/i915/i915_reg_defs.h +++ b/drivers/gpu/drm/i915/i915_reg_defs.h @@ -106,17 +106,17 @@ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) -#define _MASKED_FIELD(mask, value) ({ \ - if (__builtin_constant_p(mask)) \ - BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ - if (__builtin_constant_p(value)) \ - BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ - if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ - BUILD_BUG_ON_MSG((value) & ~(mask), \ - "Incorrect value for mask"); \ - __MASKED_FIELD(mask, value); }) -#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) -#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) +#define _MASKED_FIELD(mask, value) \ + (BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \ + __MASKED_FIELD(mask, value)) + +#define _MASKED_BIT_ENABLE(a) \ + (__builtin_choose_expr(__builtin_constant_p(a), _MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }))) + +#define _MASKED_BIT_DISABLE(a) \ + (_MASKED_FIELD((a), 0)) /* * Given the first two numbers __a and __b of arbitrarily many evenly spaced -- 2.47.3 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 1/8] drm/i915/reg: make masked field helpers constexpr 2026-02-25 17:57 ` [PATCH 1/8] drm/i915/reg: make masked field helpers constexpr Jani Nikula @ 2026-03-02 20:08 ` Michał Grzelak 0 siblings, 0 replies; 23+ messages in thread From: Michał Grzelak @ 2026-03-02 20:08 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, intel-xe, rodrigo.vivi [-- Attachment #1: Type: text/plain, Size: 423 bytes --] On Wed, 25 Feb 2026, Jani Nikula wrote: > Make it possible to use _MASKED_FIELD(), _MASKED_BIT_ENABLE() and > _MASKED_BIT_DISABLE() in contexts that require integer constant > expressions. This increases their usefulness at the small cost of making > the warnings from build time checks less helpful. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> BR, Michał ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 2/8] drm/i915/lrc: switch to _MASKED_BIT_ENABLE() and _MASKED_BIT_DISABLE() 2026-02-25 17:57 [PATCH 0/8] drm/{i915,xe}: refactor register helpers Jani Nikula 2026-02-25 17:57 ` [PATCH 1/8] drm/i915/reg: make masked field helpers constexpr Jani Nikula @ 2026-02-25 17:57 ` Jani Nikula 2026-03-02 20:08 ` Michał Grzelak 2026-02-25 17:57 ` [PATCH 3/8] drm/{i915, xe}/reg: rename masked field helpers REG_MASKED_FIELD*() Jani Nikula ` (10 subsequent siblings) 12 siblings, 1 reply; 23+ messages in thread From: Jani Nikula @ 2026-02-25 17:57 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula, rodrigo.vivi Since it's now possible to use _MASKED_BIT_ENABLE() and _MASKED_BIT_DISABLE() in the array initializer, switch to them. This allows us to remove __MASKED_FIELD() macro. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 9 +++------ drivers/gpu/drm/i915/i915_reg_defs.h | 3 +-- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index d36e543e98df..8f7156ba9f8e 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1736,22 +1736,19 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ { COMMON_SLICE_CHICKEN2, - __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE, - 0), + _MASKED_BIT_DISABLE(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE), }, /* BSpec: 11391 */ { FF_SLICE_CHICKEN, - __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX, - FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX), + _MASKED_BIT_ENABLE(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX), }, /* BSpec: 11299 */ { _3D_CHICKEN3, - __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX, - _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX), + _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX), } }; diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h index c39b3a5dafe6..59c661539895 100644 --- a/drivers/gpu/drm/i915/i915_reg_defs.h +++ b/drivers/gpu/drm/i915/i915_reg_defs.h @@ -105,12 +105,11 @@ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) -#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) #define _MASKED_FIELD(mask, value) \ (BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \ - __MASKED_FIELD(mask, value)) + ((mask) << 16 | (value))) #define _MASKED_BIT_ENABLE(a) \ (__builtin_choose_expr(__builtin_constant_p(a), _MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }))) -- 2.47.3 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 2/8] drm/i915/lrc: switch to _MASKED_BIT_ENABLE() and _MASKED_BIT_DISABLE() 2026-02-25 17:57 ` [PATCH 2/8] drm/i915/lrc: switch to _MASKED_BIT_ENABLE() and _MASKED_BIT_DISABLE() Jani Nikula @ 2026-03-02 20:08 ` Michał Grzelak 0 siblings, 0 replies; 23+ messages in thread From: Michał Grzelak @ 2026-03-02 20:08 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, intel-xe, rodrigo.vivi [-- Attachment #1: Type: text/plain, Size: 337 bytes --] On Wed, 25 Feb 2026, Jani Nikula wrote: > Since it's now possible to use _MASKED_BIT_ENABLE() and > _MASKED_BIT_DISABLE() in the array initializer, switch to them. This > allows us to remove __MASKED_FIELD() macro. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> BR, Michał ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 3/8] drm/{i915, xe}/reg: rename masked field helpers REG_MASKED_FIELD*() 2026-02-25 17:57 [PATCH 0/8] drm/{i915,xe}: refactor register helpers Jani Nikula 2026-02-25 17:57 ` [PATCH 1/8] drm/i915/reg: make masked field helpers constexpr Jani Nikula 2026-02-25 17:57 ` [PATCH 2/8] drm/i915/lrc: switch to _MASKED_BIT_ENABLE() and _MASKED_BIT_DISABLE() Jani Nikula @ 2026-02-25 17:57 ` Jani Nikula 2026-03-02 20:08 ` Michał Grzelak 2026-02-25 17:57 ` [PATCH 4/8] drm/i915/perf: prefer REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() Jani Nikula ` (9 subsequent siblings) 12 siblings, 1 reply; 23+ messages in thread From: Jani Nikula @ 2026-02-25 17:57 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula, rodrigo.vivi The underscore prefixed masked field helper names aren't great. Rename them REG_MASKED_FIELD(), REG_MASKED_FIELD_ENABLE(), and REG_MASKED_FIELD_DISABLE(). This is more in line with the existing REG_FIELD_PREP() etc. helpers, and using "field" instead of "bit" is more accurate for the functionality. This is done with: sed -i 's/_MASKED_FIELD/REG_MASKED_FIELD/g' $(git grep -wl _MASKED_FIELD) sed -i 's/_MASKED_BIT_ENABLE/REG_MASKED_FIELD_ENABLE/g' $(git grep -wl _MASKED_BIT_ENABLE) sed -i 's/_MASKED_BIT_DISABLE/REG_MASKED_FIELD_DISABLE/g' $(git grep -wl _MASKED_BIT_DISABLE) with some manual indentation fixes on top. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/i9xx_wm.c | 8 ++-- .../gpu/drm/i915/display/intel_display_irq.c | 4 +- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 10 ++--- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +- .../drm/i915/gt/intel_execlists_submission.c | 6 +-- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 6 +-- drivers/gpu/drm/i915/gt/intel_lrc.c | 18 ++++----- drivers/gpu/drm/i915/gt/intel_rc6.c | 22 +++++------ drivers/gpu/drm/i915/gt/intel_reset.c | 4 +- .../gpu/drm/i915/gt/intel_ring_submission.c | 19 ++++------ drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 ++++++------ .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +- drivers/gpu/drm/i915/gvt/handlers.c | 10 ++--- drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +- drivers/gpu/drm/i915/gvt/reg.h | 4 +- drivers/gpu/drm/i915/i915_perf.c | 34 ++++++++--------- drivers/gpu/drm/i915/i915_reg_defs.h | 10 ++--- drivers/gpu/drm/i915/intel_clock_gating.c | 38 +++++++++---------- drivers/gpu/drm/i915/intel_uncore.c | 4 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 4 +- drivers/gpu/drm/xe/xe_eu_stall.c | 20 +++++----- drivers/gpu/drm/xe/xe_execlist.c | 6 +-- drivers/gpu/drm/xe/xe_hw_engine.c | 8 ++-- drivers/gpu/drm/xe/xe_lrc.c | 12 +++--- drivers/gpu/drm/xe/xe_oa.c | 38 +++++++++---------- drivers/gpu/drm/xe/xe_pxp.c | 4 +- drivers/gpu/drm/xe/xe_uc_fw.c | 4 +- 29 files changed, 164 insertions(+), 167 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index 24f898efa9dd..9e170e79dcf6 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -182,8 +182,8 @@ static bool _intel_set_memory_cxsr(struct intel_display *display, bool enable) intel_de_posting_read(display, DSPFW3(display)); } else if (display->platform.i945g || display->platform.i945gm) { was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN; - val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : - _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); + val = enable ? REG_MASKED_FIELD_ENABLE(FW_BLC_SELF_EN) : + REG_MASKED_FIELD_DISABLE(FW_BLC_SELF_EN); intel_de_write(display, FW_BLC_SELF, val); intel_de_posting_read(display, FW_BLC_SELF); } else if (display->platform.i915gm) { @@ -193,8 +193,8 @@ static bool _intel_set_memory_cxsr(struct intel_display *display, bool enable) * FW_BLC_SELF. What's going on? */ was_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN; - val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : - _MASKED_BIT_DISABLE(INSTPM_SELF_EN); + val = enable ? REG_MASKED_FIELD_ENABLE(INSTPM_SELF_EN) : + REG_MASKED_FIELD_DISABLE(INSTPM_SELF_EN); intel_de_write(display, INSTPM, val); intel_de_posting_read(display, INSTPM); } else { diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index e57e692b3663..70c1bba7c0a8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -1619,7 +1619,7 @@ static void i915gm_irq_cstate_wa_enable(struct intel_display *display) */ if (display->irq.vblank_enabled++ == 0) intel_de_write(display, SCPD0, - _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); + REG_MASKED_FIELD_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); } static void i915gm_irq_cstate_wa_disable(struct intel_display *display) @@ -1628,7 +1628,7 @@ static void i915gm_irq_cstate_wa_disable(struct intel_display *display) if (--display->irq.vblank_enabled == 0) intel_de_write(display, SCPD0, - _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); + REG_MASKED_FIELD_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); } void i915gm_irq_cstate_wa(struct intel_display *display, bool enable) diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c index e8fab45759c3..438cd4724ac4 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c @@ -67,7 +67,7 @@ void gen6_ppgtt_enable(struct intel_gt *gt) if (HAS_PPGTT(uncore->i915)) /* may be disabled for VT-d */ intel_uncore_write(uncore, GFX_MODE, - _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); + REG_MASKED_FIELD_ENABLE(GFX_PPGTT_ENABLE)); } /* PPGTT support for Sandybdrige/Gen6 and later */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 54c9571327e7..c0fd349a4600 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1233,7 +1233,7 @@ static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine) engine->class == VIDEO_ENHANCEMENT_CLASS || engine->class == COMPUTE_CLASS || engine->class == OTHER_CLASS)) - engine->tlb_inv.request = _MASKED_BIT_ENABLE(val); + engine->tlb_inv.request = REG_MASKED_FIELD_ENABLE(val); else engine->tlb_inv.request = val; @@ -1628,7 +1628,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine, const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); int err; - intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + intel_uncore_write_fw(uncore, mode, REG_MASKED_FIELD_ENABLE(STOP_RING)); /* * Wa_22011802037: Prior to doing a reset, ensure CS is @@ -1636,7 +1636,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine, */ if (intel_engine_reset_needs_wa_22011802037(engine->gt)) intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base), - _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE)); + REG_MASKED_FIELD_ENABLE(GEN12_GFX_PREFETCH_DISABLE)); err = __intel_wait_for_register_fw(engine->uncore, mode, MODE_IDLE, MODE_IDLE, @@ -1692,7 +1692,7 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) { ENGINE_TRACE(engine, "\n"); - ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); + ENGINE_WRITE_FW(engine, RING_MI_MODE, REG_MASKED_FIELD_DISABLE(STOP_RING)); } static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine) @@ -2552,7 +2552,7 @@ void xehp_enable_ccs_engines(struct intel_engine_cs *engine) return; intel_uncore_write(engine->uncore, GEN12_RCU_MODE, - _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE)); + REG_MASKED_FIELD_ENABLE(GEN12_RCU_MODE_CCS_ENABLE)); } #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c index fb7bff27b45a..26196a57041e 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c @@ -24,7 +24,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine) if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) { intel_uncore_write(engine->gt->uncore, RC_PSMI_CTRL_GSCCS, - _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE)); + REG_MASKED_FIELD_DISABLE(IDLE_MSG_DISABLE)); /* hysteresis 0xA=5us as recommended in spec*/ intel_uncore_write(engine->gt->uncore, PWRCTX_MAXCNT_GSCCS, diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index cafe0b8e6bdd..1359fc9cb88e 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2934,12 +2934,12 @@ static void enable_execlists(struct intel_engine_cs *engine) intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */ if (GRAPHICS_VER(engine->i915) >= 11) - mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE); + mode = REG_MASKED_FIELD_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE); else - mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE); + mode = REG_MASKED_FIELD_ENABLE(GFX_RUN_LIST_ENABLE); ENGINE_WRITE_FW(engine, RING_MODE_GEN7, mode); - ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); + ENGINE_WRITE_FW(engine, RING_MI_MODE, REG_MASKED_FIELD_DISABLE(STOP_RING)); ENGINE_WRITE_FW(engine, RING_HWS_PGA, diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c index 94d63bbbdaa6..ac9aede82320 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c @@ -916,15 +916,15 @@ void intel_gt_init_swizzling(struct intel_gt *gt) if (GRAPHICS_VER(i915) == 6) intel_uncore_write(uncore, ARB_MODE, - _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); + REG_MASKED_FIELD_ENABLE(ARB_MODE_SWIZZLE_SNB)); else if (GRAPHICS_VER(i915) == 7) intel_uncore_write(uncore, ARB_MODE, - _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); + REG_MASKED_FIELD_ENABLE(ARB_MODE_SWIZZLE_IVB)); else if (GRAPHICS_VER(i915) == 8) intel_uncore_write(uncore, GAMTARBMODE, - _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); + REG_MASKED_FIELD_ENABLE(ARB_MODE_SWIZZLE_BDW)); else MISSING_CASE(GRAPHICS_VER(i915)); } diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 8f7156ba9f8e..147d22907960 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -846,16 +846,16 @@ static void init_common_regs(u32 * const regs, u32 ctl; int loc; - ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH); - ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); + ctl = REG_MASKED_FIELD_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH); + ctl |= REG_MASKED_FIELD_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); if (inhibit) ctl |= CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT; if (GRAPHICS_VER(engine->i915) < 11) - ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT | - CTX_CTRL_RS_CTX_ENABLE); + ctl |= REG_MASKED_FIELD_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT | + CTX_CTRL_RS_CTX_ENABLE); /* Wa_14019159160 - Case 2.*/ if (ctx_needs_runalone(ce)) - ctl |= _MASKED_BIT_ENABLE(GEN12_CTX_CTRL_RUNALONE_MODE); + ctl |= REG_MASKED_FIELD_ENABLE(GEN12_CTX_CTRL_RUNALONE_MODE); regs[CTX_CONTEXT_CONTROL] = ctl; regs[CTX_TIMESTAMP] = ce->stats.runtime.last; @@ -1344,7 +1344,7 @@ gen12_invalidate_state_cache(u32 *cs) { *cs++ = MI_LOAD_REGISTER_IMM(1); *cs++ = i915_mmio_reg_offset(GEN12_CS_DEBUG_MODE2); - *cs++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE); + *cs++ = REG_MASKED_FIELD_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE); return cs; } @@ -1736,19 +1736,19 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ { COMMON_SLICE_CHICKEN2, - _MASKED_BIT_DISABLE(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE), + REG_MASKED_FIELD_DISABLE(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE), }, /* BSpec: 11391 */ { FF_SLICE_CHICKEN, - _MASKED_BIT_ENABLE(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX), + REG_MASKED_FIELD_ENABLE(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX), }, /* BSpec: 11299 */ { _3D_CHICKEN3, - _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX), + REG_MASKED_FIELD_ENABLE(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX), } }; diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 5c316f734c4a..e91e5cdca26c 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -378,9 +378,9 @@ static void chv_rc6_enable(struct intel_rc6 *rc6) /* Allows RC6 residency counter to work */ intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL, - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | - VLV_MEDIA_RC6_COUNT_EN | - VLV_RENDER_RC6_COUNT_EN)); + REG_MASKED_FIELD_ENABLE(VLV_COUNT_RANGE_HIGH | + VLV_MEDIA_RC6_COUNT_EN | + VLV_RENDER_RC6_COUNT_EN)); /* 3: Enable RC6 */ rc6->ctl_enable = GEN7_RC_CTL_TO_MODE; @@ -403,11 +403,11 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6) /* Allows RC6 residency counter to work */ intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL, - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | - VLV_MEDIA_RC0_COUNT_EN | - VLV_RENDER_RC0_COUNT_EN | - VLV_MEDIA_RC6_COUNT_EN | - VLV_RENDER_RC6_COUNT_EN)); + REG_MASKED_FIELD_ENABLE(VLV_COUNT_RANGE_HIGH | + VLV_MEDIA_RC0_COUNT_EN | + VLV_RENDER_RC0_COUNT_EN | + VLV_MEDIA_RC6_COUNT_EN | + VLV_RENDER_RC6_COUNT_EN)); rc6->ctl_enable = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; @@ -763,17 +763,17 @@ static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg) * set the high bit to be safe. */ intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL, - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); + REG_MASKED_FIELD_ENABLE(VLV_COUNT_RANGE_HIGH)); upper = intel_uncore_read_fw(uncore, reg); do { tmp = upper; intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL, - _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH)); + REG_MASKED_FIELD_DISABLE(VLV_COUNT_RANGE_HIGH)); lower = intel_uncore_read_fw(uncore, reg); intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL, - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); + REG_MASKED_FIELD_ENABLE(VLV_COUNT_RANGE_HIGH)); upper = intel_uncore_read_fw(uncore, reg); } while (upper != tmp && --loop); diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 41b5036dc538..984d0056c01c 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -586,7 +586,7 @@ static int gen8_engine_reset_prepare(struct intel_engine_cs *engine) return 0; } - intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request)); + intel_uncore_write_fw(uncore, reg, REG_MASKED_FIELD_ENABLE(request)); ret = __intel_wait_for_register_fw(uncore, reg, mask, ack, 700, 0, NULL); if (ret) @@ -602,7 +602,7 @@ static void gen8_engine_reset_cancel(struct intel_engine_cs *engine) { intel_uncore_write_fw(engine->uncore, RING_RESET_CTL(engine->mmio_base), - _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)); + REG_MASKED_FIELD_DISABLE(RESET_CTL_REQUEST_RESET)); } static int gen8_reset_engines(struct intel_gt *gt, diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 099453dd9cd5..064e7cce412f 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -128,8 +128,7 @@ static void flush_cs_tlb(struct intel_engine_cs *engine) engine->name); ENGINE_WRITE_FW(engine, RING_INSTPM, - _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | - INSTPM_SYNC_FLUSH)); + REG_MASKED_FIELD_ENABLE(INSTPM_TLB_INVALIDATE | INSTPM_SYNC_FLUSH)); if (__intel_wait_for_register_fw(engine->uncore, RING_INSTPM(engine->mmio_base), INSTPM_SYNC_FLUSH, 0, @@ -172,7 +171,7 @@ static void set_pp_dir(struct intel_engine_cs *engine) if (GRAPHICS_VER(engine->i915) >= 7) { ENGINE_WRITE_FW(engine, RING_MODE_GEN7, - _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); + REG_MASKED_FIELD_ENABLE(GFX_PPGTT_ENABLE)); } } @@ -276,7 +275,7 @@ static int xcs_resume(struct intel_engine_cs *engine) if (GRAPHICS_VER(engine->i915) > 2) { ENGINE_WRITE_FW(engine, - RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); + RING_MI_MODE, REG_MASKED_FIELD_DISABLE(STOP_RING)); ENGINE_POSTING_READ(engine, RING_MI_MODE); } @@ -719,7 +718,7 @@ static int load_pd_dir(struct i915_request *rq, *cs++ = MI_LOAD_REGISTER_IMM(1); *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); - *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); + *cs++ = REG_MASKED_FIELD_ENABLE(INSTPM_TLB_INVALIDATE); intel_ring_advance(rq, cs); @@ -768,8 +767,7 @@ static int mi_set_context(struct i915_request *rq, *cs++ = i915_mmio_reg_offset( RING_PSMI_CTL(signaller->mmio_base)); - *cs++ = _MASKED_BIT_ENABLE( - GEN6_PSMI_SLEEP_MSG_DISABLE); + *cs++ = REG_MASKED_FIELD_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE); } } } else if (GRAPHICS_VER(i915) == 5) { @@ -822,8 +820,7 @@ static int mi_set_context(struct i915_request *rq, last_reg = RING_PSMI_CTL(signaller->mmio_base); *cs++ = i915_mmio_reg_offset(last_reg); - *cs++ = _MASKED_BIT_DISABLE( - GEN6_PSMI_SLEEP_MSG_DISABLE); + *cs++ = REG_MASKED_FIELD_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE); } /* Insert a delay before the next switch! */ @@ -1055,7 +1052,7 @@ static void gen6_bsd_submit_request(struct i915_request *request) * will then assume that it is busy and bring it out of rc6. */ intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE), - _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); + REG_MASKED_FIELD_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); /* Clear the context id. Here be magic! */ intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0); @@ -1076,7 +1073,7 @@ static void gen6_bsd_submit_request(struct i915_request *request) * and so let it sleep to conserve power when idle. */ intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE), - _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); + REG_MASKED_FIELD_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); } diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index f78d991ad7bf..24ea5d8d529c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -300,39 +300,39 @@ wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr) static void wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) { - wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); + wa_add(wal, reg, 0, REG_MASKED_FIELD_ENABLE(val), val, true); } static void wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) { - wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); + wa_mcr_add(wal, reg, 0, REG_MASKED_FIELD_ENABLE(val), val, true); } static void wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) { - wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); + wa_add(wal, reg, 0, REG_MASKED_FIELD_DISABLE(val), val, true); } static void wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) { - wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); + wa_mcr_add(wal, reg, 0, REG_MASKED_FIELD_DISABLE(val), val, true); } static void wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val) { - wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); + wa_add(wal, reg, 0, REG_MASKED_FIELD(mask, val), mask, true); } static void wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 mask, u32 val) { - wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); + wa_mcr_add(wal, reg, 0, REG_MASKED_FIELD(mask, val), mask, true); } static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, @@ -666,7 +666,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, /* WaEnableFloatBlendOptimization:icl */ wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, - _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), + REG_MASKED_FIELD_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 0 /* write-only, so skip validation */, true); @@ -1131,7 +1131,7 @@ hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) wa_add(wal, HSW_ROW_CHICKEN3, 0, - _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), + REG_MASKED_FIELD_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 0 /* XXX does this reg exist? */, true); /* WaVSRefCountFullforceMissDisable:hsw */ @@ -2272,7 +2272,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) IS_DG2(i915)) { /* Wa_14015150844 */ wa_mcr_add(wal, XEHP_HDC_CHICKEN0, 0, - _MASKED_BIT_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES), + REG_MASKED_FIELD_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES), 0, true); } @@ -2663,7 +2663,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) if (IS_GRAPHICS_VER(i915, 4, 6)) /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), - 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), + 0, REG_MASKED_FIELD_ENABLE(VS_TIMER_DISPATCH), /* XXX bit doesn't stick on Broadwater */ IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); @@ -2679,7 +2679,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * enabled. */ wa_add(wal, ECOSKPD(RENDER_RING_BASE), - 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), + 0, REG_MASKED_FIELD_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 0 /* XXX bit doesn't stick on Broadwater */, true); } @@ -2879,7 +2879,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li * we need to explicitly skip the readback. */ wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, - _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), + REG_MASKED_FIELD_ENABLE(ENABLE_PREFETCH_INTO_IC), 0 /* write-only, so skip validation */, true); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 142183d3f7fb..13650ce1c7a6 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -4414,9 +4414,9 @@ static void start_engine(struct intel_engine_cs *engine) { ENGINE_WRITE_FW(engine, RING_MODE_GEN7, - _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); + REG_MASKED_FIELD_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); - ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); + ENGINE_WRITE_FW(engine, RING_MI_MODE, REG_MASKED_FIELD_DISABLE(STOP_RING)); ENGINE_POSTING_READ(engine, RING_MI_MODE); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 5a9f7749acff..7fac97fe30a6 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -1065,7 +1065,7 @@ static int uc_fw_xfer(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags) /* Start the DMA */ intel_uncore_write_fw(uncore, DMA_CTRL, - _MASKED_BIT_ENABLE(dma_flags | START_DMA)); + REG_MASKED_FIELD_ENABLE(dma_flags | START_DMA)); /* Wait for DMA to finish */ ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100, NULL); @@ -1075,7 +1075,7 @@ static int uc_fw_xfer(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags) intel_uncore_read_fw(uncore, DMA_CTRL)); /* Disable the bits once DMA is over */ - intel_uncore_write_fw(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags)); + intel_uncore_write_fw(uncore, DMA_CTRL, REG_MASKED_FIELD_DISABLE(dma_flags)); intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 56b855899609..a34f56630af9 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -2047,10 +2047,10 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, bool enable_execlist; int ret; - (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); + (*(u32 *)p_data) &= ~REG_MASKED_FIELD_ENABLE(1); if (IS_COFFEELAKE(vgpu->gvt->gt->i915) || IS_COMETLAKE(vgpu->gvt->gt->i915)) - (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); + (*(u32 *)p_data) &= ~REG_MASKED_FIELD_ENABLE(2); write_vreg(vgpu, offset, p_data, bytes); if (IS_MASKED_BITS_ENABLED(data, 1)) { @@ -2139,7 +2139,7 @@ static int ring_reset_ctl_write(struct intel_vgpu *vgpu, if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET)) data |= RESET_CTL_READY_TO_RESET; - else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) + else if (data & REG_MASKED_FIELD_DISABLE(RESET_CTL_REQUEST_RESET)) data &= ~RESET_CTL_READY_TO_RESET; vgpu_vreg(vgpu, offset) = data; @@ -2152,7 +2152,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, { u32 data = *(u32 *)p_data; - (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); + (*(u32 *)p_data) &= ~REG_MASKED_FIELD_ENABLE(0x18); write_vreg(vgpu, offset, p_data, bytes); if (IS_MASKED_BITS_ENABLED(data, 0x10) || @@ -2534,7 +2534,7 @@ static int init_bdw_mmio_info(struct intel_gvt *gvt) #define RING_REG(base) _MMIO((base) + 0xd0) MMIO_RING_F(RING_REG, 4, F_RO, 0, - ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, + ~REG_MASKED_FIELD_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, ring_reset_ctl_write); #undef RING_REG diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index 3eb442acdf8d..a93999ba8092 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -476,7 +476,7 @@ bool is_inhibit_context(struct intel_context *ce) { const u32 *reg_state = ce->lrc_reg_state; u32 inhibit_mask = - _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); + REG_MASKED_FIELD_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); return inhibit_mask == (reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask); diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h index 90d8eb1761a3..a4cf15e43990 100644 --- a/drivers/gpu/drm/i915/gvt/reg.h +++ b/drivers/gpu/drm/i915/gvt/reg.h @@ -91,9 +91,9 @@ ((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16)))) #define IS_MASKED_BITS_ENABLED(_val, _b) \ - (((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b)) + (((_val) & REG_MASKED_FIELD_ENABLE(_b)) == REG_MASKED_FIELD_ENABLE(_b)) #define IS_MASKED_BITS_DISABLED(_val, _b) \ - ((_val) & _MASKED_BIT_DISABLE(_b)) + ((_val) & REG_MASKED_FIELD_DISABLE(_b)) #define FORCEWAKE_RENDER_GEN9_REG 0xa278 #define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84 diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 2820e8f0f765..9ad4383404ff 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -2635,10 +2635,10 @@ static int gen12_configure_oar_context(struct i915_perf_stream *stream, { RING_CONTEXT_CONTROL(ce->engine->mmio_base), CTX_CONTEXT_CONTROL, - _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE, - active ? - GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE : - 0) + REG_MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE, + active ? + GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE : + 0) }, }; @@ -2827,8 +2827,8 @@ gen8_enable_metric_set(struct i915_perf_stream *stream, */ if (IS_GRAPHICS_VER(stream->perf->i915, 9, 11)) { intel_uncore_write(uncore, GEN8_OA_DEBUG, - _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | - GEN9_OA_DEBUG_INCLUDE_CLK_RATIO)); + REG_MASKED_FIELD_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | + GEN9_OA_DEBUG_INCLUDE_CLK_RATIO)); } /* @@ -2847,9 +2847,9 @@ gen8_enable_metric_set(struct i915_perf_stream *stream, static u32 oag_report_ctx_switches(const struct i915_perf_stream *stream) { - return _MASKED_FIELD(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS, - (stream->sample_flags & SAMPLE_OA_REPORT) ? - 0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS); + return REG_MASKED_FIELD(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS, + (stream->sample_flags & SAMPLE_OA_REPORT) ? + 0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS); } static int @@ -2870,15 +2870,15 @@ gen12_enable_metric_set(struct i915_perf_stream *stream, */ if (IS_DG2(i915)) { intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN, - _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); + REG_MASKED_FIELD_ENABLE(STALL_DOP_GATING_DISABLE)); intel_uncore_write(uncore, GEN7_ROW_CHICKEN2, - _MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING)); + REG_MASKED_FIELD_ENABLE(GEN12_DISABLE_DOP_GATING)); } intel_uncore_write(uncore, __oa_regs(stream)->oa_debug, /* Disable clk ratio reports, like previous Gens. */ - _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | - GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO) | + REG_MASKED_FIELD_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | + GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO) | /* * If the user didn't require OA reports, instruct * the hardware not to emit ctx switch reports. @@ -2949,9 +2949,9 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream) */ if (IS_DG2(i915)) { intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN, - _MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE)); + REG_MASKED_FIELD_DISABLE(STALL_DOP_GATING_DISABLE)); intel_uncore_write(uncore, GEN7_ROW_CHICKEN2, - _MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING)); + REG_MASKED_FIELD_DISABLE(GEN12_DISABLE_DOP_GATING)); } /* disable the context save/restore or OAR counters */ @@ -4475,7 +4475,7 @@ static u32 mask_reg_value(u32 reg, u32 val) * programmed by userspace doesn't change this. */ if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2)) - val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE); + val = val & ~REG_MASKED_FIELD_ENABLE(GEN8_ST_PO_DISABLE); /* * WAIT_FOR_RC6_EXIT has only one bit fulfilling the function @@ -4483,7 +4483,7 @@ static u32 mask_reg_value(u32 reg, u32 val) * configs. */ if (REG_EQUAL(reg, WAIT_FOR_RC6_EXIT)) - val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE); + val = val & ~REG_MASKED_FIELD_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE); return val; } diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h index 59c661539895..9d72f6fae4ae 100644 --- a/drivers/gpu/drm/i915/i915_reg_defs.h +++ b/drivers/gpu/drm/i915/i915_reg_defs.h @@ -105,17 +105,17 @@ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) -#define _MASKED_FIELD(mask, value) \ +#define REG_MASKED_FIELD(mask, value) \ (BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \ ((mask) << 16 | (value))) -#define _MASKED_BIT_ENABLE(a) \ - (__builtin_choose_expr(__builtin_constant_p(a), _MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }))) +#define REG_MASKED_FIELD_ENABLE(a) \ + (__builtin_choose_expr(__builtin_constant_p(a), REG_MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); REG_MASKED_FIELD(_a, _a); }))) -#define _MASKED_BIT_DISABLE(a) \ - (_MASKED_FIELD((a), 0)) +#define REG_MASKED_FIELD_DISABLE(a) \ + (REG_MASKED_FIELD((a), 0)) /* * Given the first two numbers __a and __b of arbitrarily many evenly spaced diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index d0400ea2ffc7..68a6f94f2a37 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -454,7 +454,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *i915) GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0); intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), - _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); + REG_MASKED_FIELD_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); /* WaDisableSDEUnitClockGating:bdw */ intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); @@ -519,13 +519,13 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915) if (INTEL_INFO(i915)->gt == 1) intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); + REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE)); else { /* must write both registers */ intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); + REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE)); intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2_GT2, - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); + REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE)); } /* @@ -559,7 +559,7 @@ static void vlv_init_clock_gating(struct drm_i915_private *i915) /* WaDisableDopClockGating:vlv */ intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); + REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE)); /* This is required by WaCatErrorRejectionIssue:vlv */ intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, @@ -594,7 +594,7 @@ static void chv_init_clock_gating(struct drm_i915_private *i915) /* WaDisableSemaphoreAndSyncFlipWait:chv */ intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), - _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); + REG_MASKED_FIELD_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); /* WaDisableCSUnitClockGating:chv */ intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE); @@ -640,7 +640,7 @@ static void i965gm_init_clock_gating(struct drm_i915_private *i915) intel_uncore_write16(uncore, DEUC, 0); intel_uncore_write(uncore, MI_ARB_STATE, - _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); + REG_MASKED_FIELD_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); } static void i965g_init_clock_gating(struct drm_i915_private *i915) @@ -652,7 +652,7 @@ static void i965g_init_clock_gating(struct drm_i915_private *i915) I965_FBC_CLOCK_GATE_DISABLE); intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, 0); intel_uncore_write(&i915->uncore, MI_ARB_STATE, - _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); + REG_MASKED_FIELD_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); } static void gen3_init_clock_gating(struct drm_i915_private *i915) @@ -665,21 +665,21 @@ static void gen3_init_clock_gating(struct drm_i915_private *i915) if (IS_PINEVIEW(i915)) intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), - _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); + REG_MASKED_FIELD_ENABLE(ECO_GATING_CX_ONLY)); /* IIR "flip pending" means done if this bit is set */ intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), - _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); + REG_MASKED_FIELD_DISABLE(ECO_FLIP_DONE)); /* interrupts should cause a wake up from C3 */ - intel_uncore_write(&i915->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); + intel_uncore_write(&i915->uncore, INSTPM, REG_MASKED_FIELD_ENABLE(INSTPM_AGPBUSY_INT_EN)); /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ intel_uncore_write(&i915->uncore, MI_ARB_STATE, - _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); + REG_MASKED_FIELD_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); intel_uncore_write(&i915->uncore, MI_ARB_STATE, - _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); + REG_MASKED_FIELD_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); } static void i85x_init_clock_gating(struct drm_i915_private *i915) @@ -687,11 +687,11 @@ static void i85x_init_clock_gating(struct drm_i915_private *i915) intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); /* interrupts should cause a wake up from C3 */ - intel_uncore_write(&i915->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | - _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); + intel_uncore_write(&i915->uncore, MI_STATE, REG_MASKED_FIELD_ENABLE(MI_AGPBUSY_INT_EN) | + REG_MASKED_FIELD_DISABLE(MI_AGPBUSY_830_MODE)); intel_uncore_write(&i915->uncore, MEM_MODE, - _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); + REG_MASKED_FIELD_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); /* * Have FBC ignore 3D activity since we use software @@ -701,14 +701,14 @@ static void i85x_init_clock_gating(struct drm_i915_private *i915) * until a 2D blit occurs. */ intel_uncore_write(&i915->uncore, SCPD0, - _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D)); + REG_MASKED_FIELD_ENABLE(SCPD_FBC_IGNORE_3D)); } static void i830_init_clock_gating(struct drm_i915_private *i915) { intel_uncore_write(&i915->uncore, MEM_MODE, - _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | - _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); + REG_MASKED_FIELD_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | + REG_MASKED_FIELD_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); } void intel_clock_gating_init(struct drm_device *drm) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index bccedd59a114..5b698d4d7a7f 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -132,8 +132,8 @@ intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) } #define fw_ack(d) readl((d)->reg_ack) -#define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set) -#define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set) +#define fw_set(d, val) writel(REG_MASKED_FIELD_ENABLE((val)), (d)->reg_set) +#define fw_clear(d, val) writel(REG_MASKED_FIELD_DISABLE((val)), (d)->reg_set) static inline void fw_domain_reset(const struct intel_uncore_forcewake_domain *d) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index f7ed4e18a3ab..2b63fb2cffd6 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -66,8 +66,8 @@ bool intel_pxp_is_active(const struct intel_pxp *pxp) static void kcr_pxp_set_status(const struct intel_pxp *pxp, bool enable) { - u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) : - _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES); + u32 val = enable ? REG_MASKED_FIELD_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) : + REG_MASKED_FIELD_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES); intel_uncore_write(pxp->ctrl_gt->uncore, KCR_INIT(pxp->kcr_base), val); } diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c index 39723928a019..c34408cfd292 100644 --- a/drivers/gpu/drm/xe/xe_eu_stall.c +++ b/drivers/gpu/drm/xe/xe_eu_stall.c @@ -442,9 +442,9 @@ static void clear_dropped_eviction_line_bit(struct xe_gt *gt, u16 group, u16 ins * On Xe2 and later GPUs, the bit has to be cleared by writing 0 to it. */ if (GRAPHICS_VER(xe) >= 20) - write_ptr_reg = _MASKED_BIT_DISABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP); + write_ptr_reg = REG_MASKED_FIELD_DISABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP); else - write_ptr_reg = _MASKED_BIT_ENABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP); + write_ptr_reg = REG_MASKED_FIELD_ENABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP); xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT, write_ptr_reg, group, instance); } @@ -504,7 +504,7 @@ static int xe_eu_stall_data_buf_read(struct xe_eu_stall_data_stream *stream, /* Read pointer can overflow into one additional bit */ read_ptr &= (buf_size << 1) - 1; read_ptr_reg = REG_FIELD_PREP(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, (read_ptr >> 6)); - read_ptr_reg = _MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg); + read_ptr_reg = REG_MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg); xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT1, read_ptr_reg, group, instance); xecore_buf->read = read_ptr; trace_xe_eu_stall_data_read(group, instance, read_ptr, write_ptr, @@ -674,7 +674,7 @@ static int xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream) if (XE_GT_WA(gt, 22016596838)) xe_gt_mcr_multicast_write(gt, ROW_CHICKEN2, - _MASKED_BIT_ENABLE(DISABLE_DOP_GATING)); + REG_MASKED_FIELD_ENABLE(DISABLE_DOP_GATING)); for_each_dss_steering(xecore, gt, group, instance) { write_ptr_reg = xe_gt_mcr_unicast_read(gt, XEHPC_EUSTALL_REPORT, group, instance); @@ -683,7 +683,7 @@ static int xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream) clear_dropped_eviction_line_bit(gt, group, instance); write_ptr = REG_FIELD_GET(XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK, write_ptr_reg); read_ptr_reg = REG_FIELD_PREP(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, write_ptr); - read_ptr_reg = _MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg); + read_ptr_reg = REG_MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg); /* Initialize the read pointer to the write pointer */ xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT1, read_ptr_reg, group, instance); write_ptr <<= 6; @@ -695,10 +695,10 @@ static int xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream) stream->data_drop.reported_to_user = false; bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS); - reg_value = _MASKED_FIELD(EUSTALL_MOCS | EUSTALL_SAMPLE_RATE, - REG_FIELD_PREP(EUSTALL_MOCS, gt->mocs.uc_index << 1) | - REG_FIELD_PREP(EUSTALL_SAMPLE_RATE, - stream->sampling_rate_mult)); + reg_value = REG_MASKED_FIELD(EUSTALL_MOCS | EUSTALL_SAMPLE_RATE, + REG_FIELD_PREP(EUSTALL_MOCS, gt->mocs.uc_index << 1) | + REG_FIELD_PREP(EUSTALL_SAMPLE_RATE, + stream->sampling_rate_mult)); xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_CTRL, reg_value); /* GGTT addresses can never be > 32 bits */ xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE_UPPER, 0); @@ -830,7 +830,7 @@ static int xe_eu_stall_disable_locked(struct xe_eu_stall_data_stream *stream) if (XE_GT_WA(gt, 22016596838)) xe_gt_mcr_multicast_write(gt, ROW_CHICKEN2, - _MASKED_BIT_DISABLE(DISABLE_DOP_GATING)); + REG_MASKED_FIELD_DISABLE(DISABLE_DOP_GATING)); xe_force_wake_put(gt_to_fw(gt), stream->fw_ref); xe_pm_runtime_put(gt_to_xe(gt)); diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c index 7e8a3a7db741..755a2bff5d7b 100644 --- a/drivers/gpu/drm/xe/xe_execlist.c +++ b/drivers/gpu/drm/xe/xe_execlist.c @@ -47,7 +47,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc, struct xe_mmio *mmio = >->mmio; struct xe_device *xe = gt_to_xe(gt); u64 lrc_desc; - u32 ring_mode = _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE); + u32 ring_mode = REG_MASKED_FIELD_ENABLE(GFX_DISABLE_LEGACY_MODE); lrc_desc = xe_lrc_descriptor(lrc); @@ -61,7 +61,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc, if (hwe->class == XE_ENGINE_CLASS_COMPUTE) xe_mmio_write32(mmio, RCU_MODE, - _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE)); + REG_MASKED_FIELD_ENABLE(RCU_MODE_CCS_ENABLE)); xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail); lrc->ring.old_tail = lrc->ring.tail; @@ -83,7 +83,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc, xe_mmio_read32(mmio, RING_HWS_PGA(hwe->mmio_base)); if (xe_device_has_msix(gt_to_xe(hwe->gt))) - ring_mode |= _MASKED_BIT_ENABLE(GFX_MSIX_INTERRUPT_ENABLE); + ring_mode |= REG_MASKED_FIELD_ENABLE(GFX_MSIX_INTERRUPT_ENABLE); xe_mmio_write32(mmio, RING_MODE(hwe->mmio_base), ring_mode); xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base), diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c index ea3ad600d7c7..337baf0a6e87 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.c +++ b/drivers/gpu/drm/xe/xe_hw_engine.c @@ -327,21 +327,21 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe) { u32 ccs_mask = xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE); - u32 ring_mode = _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE); + u32 ring_mode = REG_MASKED_FIELD_ENABLE(GFX_DISABLE_LEGACY_MODE); if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask) xe_mmio_write32(&hwe->gt->mmio, RCU_MODE, - _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE)); + REG_MASKED_FIELD_ENABLE(RCU_MODE_CCS_ENABLE)); xe_hw_engine_mmio_write32(hwe, RING_HWSTAM(0), ~0x0); xe_hw_engine_mmio_write32(hwe, RING_HWS_PGA(0), xe_bo_ggtt_addr(hwe->hwsp)); if (xe_device_has_msix(gt_to_xe(hwe->gt))) - ring_mode |= _MASKED_BIT_ENABLE(GFX_MSIX_INTERRUPT_ENABLE); + ring_mode |= REG_MASKED_FIELD_ENABLE(GFX_MSIX_INTERRUPT_ENABLE); xe_hw_engine_mmio_write32(hwe, RING_MODE(0), ring_mode); xe_hw_engine_mmio_write32(hwe, RING_MI_MODE(0), - _MASKED_BIT_DISABLE(STOP_RING)); + REG_MASKED_FIELD_DISABLE(STOP_RING)); xe_hw_engine_mmio_read32(hwe, RING_MI_MODE(0)); } diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c index 9590b4605952..9dc22f1dc279 100644 --- a/drivers/gpu/drm/xe/xe_lrc.c +++ b/drivers/gpu/drm/xe/xe_lrc.c @@ -641,12 +641,12 @@ static const u8 *reg_offsets(struct xe_device *xe, enum xe_engine_class class) static void set_context_control(u32 *regs, struct xe_hw_engine *hwe) { - regs[CTX_CONTEXT_CONTROL] = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | - CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); + regs[CTX_CONTEXT_CONTROL] = REG_MASKED_FIELD_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | + CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); if (xe_gt_has_indirect_ring_state(hwe->gt)) regs[CTX_CONTEXT_CONTROL] |= - _MASKED_BIT_ENABLE(CTX_CTRL_INDIRECT_RING_STATE_ENABLE); + REG_MASKED_FIELD_ENABLE(CTX_CTRL_INDIRECT_RING_STATE_ENABLE); } static void set_memory_based_intr(u32 *regs, struct xe_hw_engine *hwe) @@ -1208,7 +1208,7 @@ static ssize_t setup_invalidate_state_cache_wa(struct xe_lrc *lrc, *cmd++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1); *cmd++ = CS_DEBUG_MODE2(0).addr; - *cmd++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE); + *cmd++ = REG_MASKED_FIELD_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE); return cmd - batch; } @@ -1546,12 +1546,12 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, if (init_flags & XE_LRC_CREATE_RUNALONE) xe_lrc_write_ctx_reg(lrc, CTX_CONTEXT_CONTROL, xe_lrc_read_ctx_reg(lrc, CTX_CONTEXT_CONTROL) | - _MASKED_BIT_ENABLE(CTX_CTRL_RUN_ALONE)); + REG_MASKED_FIELD_ENABLE(CTX_CTRL_RUN_ALONE)); if (init_flags & XE_LRC_CREATE_PXP) xe_lrc_write_ctx_reg(lrc, CTX_CONTEXT_CONTROL, xe_lrc_read_ctx_reg(lrc, CTX_CONTEXT_CONTROL) | - _MASKED_BIT_ENABLE(CTX_CTRL_PXP_ENABLE)); + REG_MASKED_FIELD_ENABLE(CTX_CTRL_PXP_ENABLE)); lrc->ctx_timestamp = 0; xe_lrc_write_ctx_reg(lrc, CTX_TIMESTAMP, 0); diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c index dcd393b0931a..9266a6ef9b1a 100644 --- a/drivers/gpu/drm/xe/xe_oa.c +++ b/drivers/gpu/drm/xe/xe_oa.c @@ -758,8 +758,8 @@ static int xe_oa_configure_oar_context(struct xe_oa_stream *stream, bool enable) }, { RING_CONTEXT_CONTROL(stream->hwe->mmio_base), - _MASKED_FIELD(CTX_CTRL_OAC_CONTEXT_ENABLE, - enable ? CTX_CTRL_OAC_CONTEXT_ENABLE : 0) + REG_MASKED_FIELD(CTX_CTRL_OAC_CONTEXT_ENABLE, + enable ? CTX_CTRL_OAC_CONTEXT_ENABLE : 0) }, }; @@ -782,9 +782,9 @@ static int xe_oa_configure_oac_context(struct xe_oa_stream *stream, bool enable) }, { RING_CONTEXT_CONTROL(stream->hwe->mmio_base), - _MASKED_FIELD(CTX_CTRL_OAC_CONTEXT_ENABLE, - enable ? CTX_CTRL_OAC_CONTEXT_ENABLE : 0) | - _MASKED_FIELD(CTX_CTRL_RUN_ALONE, enable ? CTX_CTRL_RUN_ALONE : 0), + REG_MASKED_FIELD(CTX_CTRL_OAC_CONTEXT_ENABLE, + enable ? CTX_CTRL_OAC_CONTEXT_ENABLE : 0) | + REG_MASKED_FIELD(CTX_CTRL_RUN_ALONE, enable ? CTX_CTRL_RUN_ALONE : 0), }, }; @@ -812,9 +812,9 @@ static int xe_oa_configure_oa_context(struct xe_oa_stream *stream, bool enable) static u32 oag_configure_mmio_trigger(const struct xe_oa_stream *stream, bool enable) { - return _MASKED_FIELD(OAG_OA_DEBUG_DISABLE_MMIO_TRG, - enable && stream && stream->sample ? - 0 : OAG_OA_DEBUG_DISABLE_MMIO_TRG); + return REG_MASKED_FIELD(OAG_OA_DEBUG_DISABLE_MMIO_TRG, + enable && stream && stream->sample ? + 0 : OAG_OA_DEBUG_DISABLE_MMIO_TRG); } static void xe_oa_disable_metric_set(struct xe_oa_stream *stream) @@ -825,9 +825,9 @@ static void xe_oa_disable_metric_set(struct xe_oa_stream *stream) /* Enable thread stall DOP gating and EU DOP gating. */ if (XE_GT_WA(stream->gt, 1508761755)) { xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN, - _MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE)); + REG_MASKED_FIELD_DISABLE(STALL_DOP_GATING_DISABLE)); xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN2, - _MASKED_BIT_DISABLE(DISABLE_DOP_GATING)); + REG_MASKED_FIELD_DISABLE(DISABLE_DOP_GATING)); } xe_mmio_write32(mmio, __oa_regs(stream)->oa_debug, @@ -1055,16 +1055,16 @@ static int xe_oa_emit_oa_config(struct xe_oa_stream *stream, struct xe_oa_config static u32 oag_report_ctx_switches(const struct xe_oa_stream *stream) { /* If user didn't require OA reports, ask HW not to emit ctx switch reports */ - return _MASKED_FIELD(OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS, - stream->sample ? - 0 : OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS); + return REG_MASKED_FIELD(OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS, + stream->sample ? + 0 : OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS); } static u32 oag_buf_size_select(const struct xe_oa_stream *stream) { - return _MASKED_FIELD(OAG_OA_DEBUG_BUF_SIZE_SELECT, - xe_bo_size(stream->oa_buffer.bo) > SZ_16M ? - OAG_OA_DEBUG_BUF_SIZE_SELECT : 0); + return REG_MASKED_FIELD(OAG_OA_DEBUG_BUF_SIZE_SELECT, + xe_bo_size(stream->oa_buffer.bo) > SZ_16M ? + OAG_OA_DEBUG_BUF_SIZE_SELECT : 0); } static int xe_oa_enable_metric_set(struct xe_oa_stream *stream) @@ -1079,9 +1079,9 @@ static int xe_oa_enable_metric_set(struct xe_oa_stream *stream) */ if (XE_GT_WA(stream->gt, 1508761755)) { xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN, - _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); + REG_MASKED_FIELD_ENABLE(STALL_DOP_GATING_DISABLE)); xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN2, - _MASKED_BIT_ENABLE(DISABLE_DOP_GATING)); + REG_MASKED_FIELD_ENABLE(DISABLE_DOP_GATING)); } /* Disable clk ratio reports */ @@ -1096,7 +1096,7 @@ static int xe_oa_enable_metric_set(struct xe_oa_stream *stream) OAG_OA_DEBUG_DISABLE_START_TRG_1_COUNT_QUAL; xe_mmio_write32(mmio, __oa_regs(stream)->oa_debug, - _MASKED_BIT_ENABLE(oa_debug) | + REG_MASKED_FIELD_ENABLE(oa_debug) | oag_report_ctx_switches(stream) | oag_buf_size_select(stream) | oag_configure_mmio_trigger(stream, true)); diff --git a/drivers/gpu/drm/xe/xe_pxp.c b/drivers/gpu/drm/xe/xe_pxp.c index d61446bf9c19..e2978e48f660 100644 --- a/drivers/gpu/drm/xe/xe_pxp.c +++ b/drivers/gpu/drm/xe/xe_pxp.c @@ -312,8 +312,8 @@ void xe_pxp_irq_handler(struct xe_device *xe, u16 iir) static int kcr_pxp_set_status(const struct xe_pxp *pxp, bool enable) { - u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) : - _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES); + u32 val = enable ? REG_MASKED_FIELD_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) : + REG_MASKED_FIELD_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES); CLASS(xe_force_wake, fw_ref)(gt_to_fw(pxp->gt), XE_FW_GT); if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FW_GT)) diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c index 60c82b920f47..684a6064b4c1 100644 --- a/drivers/gpu/drm/xe/xe_uc_fw.c +++ b/drivers/gpu/drm/xe/xe_uc_fw.c @@ -885,7 +885,7 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags) /* Start the DMA */ xe_mmio_write32(mmio, DMA_CTRL, - _MASKED_BIT_ENABLE(dma_flags | START_DMA)); + REG_MASKED_FIELD_ENABLE(dma_flags | START_DMA)); /* Wait for DMA to finish */ ret = xe_mmio_wait32(mmio, DMA_CTRL, START_DMA, 0, 100000, &dma_ctrl, @@ -895,7 +895,7 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags) xe_uc_fw_type_repr(uc_fw->type), dma_ctrl); /* Disable the bits once DMA is over */ - xe_mmio_write32(mmio, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags)); + xe_mmio_write32(mmio, DMA_CTRL, REG_MASKED_FIELD_DISABLE(dma_flags)); return ret; } -- 2.47.3 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 3/8] drm/{i915, xe}/reg: rename masked field helpers REG_MASKED_FIELD*() 2026-02-25 17:57 ` [PATCH 3/8] drm/{i915, xe}/reg: rename masked field helpers REG_MASKED_FIELD*() Jani Nikula @ 2026-03-02 20:08 ` Michał Grzelak 0 siblings, 0 replies; 23+ messages in thread From: Michał Grzelak @ 2026-03-02 20:08 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, intel-xe, rodrigo.vivi [-- Attachment #1: Type: text/plain, Size: 809 bytes --] On Wed, 25 Feb 2026, Jani Nikula wrote: > The underscore prefixed masked field helper names aren't great. Rename > them REG_MASKED_FIELD(), REG_MASKED_FIELD_ENABLE(), and > REG_MASKED_FIELD_DISABLE(). This is more in line with the existing > REG_FIELD_PREP() etc. helpers, and using "field" instead of "bit" is > more accurate for the functionality. > > This is done with: > > sed -i 's/_MASKED_FIELD/REG_MASKED_FIELD/g' $(git grep -wl _MASKED_FIELD) > sed -i 's/_MASKED_BIT_ENABLE/REG_MASKED_FIELD_ENABLE/g' $(git grep -wl _MASKED_BIT_ENABLE) > sed -i 's/_MASKED_BIT_DISABLE/REG_MASKED_FIELD_DISABLE/g' $(git grep -wl _MASKED_BIT_DISABLE) > > with some manual indentation fixes on top. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> BR, Michał ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 4/8] drm/i915/perf: prefer REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() 2026-02-25 17:57 [PATCH 0/8] drm/{i915,xe}: refactor register helpers Jani Nikula ` (2 preceding siblings ...) 2026-02-25 17:57 ` [PATCH 3/8] drm/{i915, xe}/reg: rename masked field helpers REG_MASKED_FIELD*() Jani Nikula @ 2026-02-25 17:57 ` Jani Nikula 2026-03-02 20:08 ` Michał Grzelak 2026-02-25 17:57 ` [PATCH 5/8] drm/xe/oa: " Jani Nikula ` (8 subsequent siblings) 12 siblings, 1 reply; 23+ messages in thread From: Jani Nikula @ 2026-02-25 17:57 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula, rodrigo.vivi Using REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() is more obvious to the reader than having the ternary expression inside REG_MASKED_FIELD(). Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_perf.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 9ad4383404ff..19b82427aa41 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -2635,10 +2635,9 @@ static int gen12_configure_oar_context(struct i915_perf_stream *stream, { RING_CONTEXT_CONTROL(ce->engine->mmio_base), CTX_CONTEXT_CONTROL, - REG_MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE, - active ? - GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE : - 0) + active ? + REG_MASKED_FIELD_ENABLE(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE) : + REG_MASKED_FIELD_DISABLE(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE), }, }; @@ -2847,9 +2846,10 @@ gen8_enable_metric_set(struct i915_perf_stream *stream, static u32 oag_report_ctx_switches(const struct i915_perf_stream *stream) { - return REG_MASKED_FIELD(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS, - (stream->sample_flags & SAMPLE_OA_REPORT) ? - 0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS); + if (stream->sample_flags & SAMPLE_OA_REPORT) + return REG_MASKED_FIELD_DISABLE(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS); + else + return REG_MASKED_FIELD_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS); } static int -- 2.47.3 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 4/8] drm/i915/perf: prefer REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() 2026-02-25 17:57 ` [PATCH 4/8] drm/i915/perf: prefer REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() Jani Nikula @ 2026-03-02 20:08 ` Michał Grzelak 0 siblings, 0 replies; 23+ messages in thread From: Michał Grzelak @ 2026-03-02 20:08 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, intel-xe, rodrigo.vivi [-- Attachment #1: Type: text/plain, Size: 323 bytes --] On Wed, 25 Feb 2026, Jani Nikula wrote: > Using REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() is more > obvious to the reader than having the ternary expression inside > REG_MASKED_FIELD(). > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> BR, Michał ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 5/8] drm/xe/oa: prefer REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() 2026-02-25 17:57 [PATCH 0/8] drm/{i915,xe}: refactor register helpers Jani Nikula ` (3 preceding siblings ...) 2026-02-25 17:57 ` [PATCH 4/8] drm/i915/perf: prefer REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() Jani Nikula @ 2026-02-25 17:57 ` Jani Nikula 2026-03-02 20:11 ` Michał Grzelak 2026-02-25 17:57 ` [PATCH 6/8] drm/intel: add reg_bits.h for the various register content helpers Jani Nikula ` (7 subsequent siblings) 12 siblings, 1 reply; 23+ messages in thread From: Jani Nikula @ 2026-02-25 17:57 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula, rodrigo.vivi Using REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() is more obvious to the reader than having the ternary expression inside REG_MASKED_FIELD(). Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/xe/xe_oa.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c index 9266a6ef9b1a..c176a61febb2 100644 --- a/drivers/gpu/drm/xe/xe_oa.c +++ b/drivers/gpu/drm/xe/xe_oa.c @@ -758,8 +758,9 @@ static int xe_oa_configure_oar_context(struct xe_oa_stream *stream, bool enable) }, { RING_CONTEXT_CONTROL(stream->hwe->mmio_base), - REG_MASKED_FIELD(CTX_CTRL_OAC_CONTEXT_ENABLE, - enable ? CTX_CTRL_OAC_CONTEXT_ENABLE : 0) + enable ? + REG_MASKED_FIELD_ENABLE(CTX_CTRL_OAC_CONTEXT_ENABLE) : + REG_MASKED_FIELD_DISABLE(CTX_CTRL_OAC_CONTEXT_ENABLE) }, }; @@ -782,9 +783,9 @@ static int xe_oa_configure_oac_context(struct xe_oa_stream *stream, bool enable) }, { RING_CONTEXT_CONTROL(stream->hwe->mmio_base), - REG_MASKED_FIELD(CTX_CTRL_OAC_CONTEXT_ENABLE, - enable ? CTX_CTRL_OAC_CONTEXT_ENABLE : 0) | - REG_MASKED_FIELD(CTX_CTRL_RUN_ALONE, enable ? CTX_CTRL_RUN_ALONE : 0), + enable ? + REG_MASKED_FIELD_ENABLE(CTX_CTRL_OAC_CONTEXT_ENABLE | CTX_CTRL_RUN_ALONE) : + REG_MASKED_FIELD_DISABLE(CTX_CTRL_OAC_CONTEXT_ENABLE | CTX_CTRL_RUN_ALONE), }, }; @@ -812,9 +813,10 @@ static int xe_oa_configure_oa_context(struct xe_oa_stream *stream, bool enable) static u32 oag_configure_mmio_trigger(const struct xe_oa_stream *stream, bool enable) { - return REG_MASKED_FIELD(OAG_OA_DEBUG_DISABLE_MMIO_TRG, - enable && stream && stream->sample ? - 0 : OAG_OA_DEBUG_DISABLE_MMIO_TRG); + if (enable && stream && stream->sample) + return REG_MASKED_FIELD_DISABLE(OAG_OA_DEBUG_DISABLE_MMIO_TRG); + else + return REG_MASKED_FIELD_ENABLE(OAG_OA_DEBUG_DISABLE_MMIO_TRG); } static void xe_oa_disable_metric_set(struct xe_oa_stream *stream) @@ -1055,16 +1057,18 @@ static int xe_oa_emit_oa_config(struct xe_oa_stream *stream, struct xe_oa_config static u32 oag_report_ctx_switches(const struct xe_oa_stream *stream) { /* If user didn't require OA reports, ask HW not to emit ctx switch reports */ - return REG_MASKED_FIELD(OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS, - stream->sample ? - 0 : OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS); + if (stream->sample) + return REG_MASKED_FIELD_DISABLE(OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS); + else + return REG_MASKED_FIELD_ENABLE(OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS); } static u32 oag_buf_size_select(const struct xe_oa_stream *stream) { - return REG_MASKED_FIELD(OAG_OA_DEBUG_BUF_SIZE_SELECT, - xe_bo_size(stream->oa_buffer.bo) > SZ_16M ? - OAG_OA_DEBUG_BUF_SIZE_SELECT : 0); + if (xe_bo_size(stream->oa_buffer.bo) > SZ_16M) + return REG_MASKED_FIELD_ENABLE(OAG_OA_DEBUG_BUF_SIZE_SELECT); + else + return REG_MASKED_FIELD_DISABLE(OAG_OA_DEBUG_BUF_SIZE_SELECT); } static int xe_oa_enable_metric_set(struct xe_oa_stream *stream) -- 2.47.3 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 5/8] drm/xe/oa: prefer REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() 2026-02-25 17:57 ` [PATCH 5/8] drm/xe/oa: " Jani Nikula @ 2026-03-02 20:11 ` Michał Grzelak 0 siblings, 0 replies; 23+ messages in thread From: Michał Grzelak @ 2026-03-02 20:11 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, intel-xe, rodrigo.vivi [-- Attachment #1: Type: text/plain, Size: 686 bytes --] On Wed, 25 Feb 2026, Jani Nikula wrote: > Using REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() is more > obvious to the reader than having the ternary expression inside > REG_MASKED_FIELD(). > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Not relevant to the code but this patch instead of subject is shown with quotation mark when going on lore [1] to thread overview from any patch from the series. And it cannot be an abbreviation of too long subject since previous patch has it longer and is still shown properly. Weird. [1] https://lore.kernel.org/all/cover.1772042022.git.jani.nikula@intel.com BR, Michał ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 6/8] drm/intel: add reg_bits.h for the various register content helpers 2026-02-25 17:57 [PATCH 0/8] drm/{i915,xe}: refactor register helpers Jani Nikula ` (4 preceding siblings ...) 2026-02-25 17:57 ` [PATCH 5/8] drm/xe/oa: " Jani Nikula @ 2026-02-25 17:57 ` Jani Nikula 2026-03-02 20:11 ` Michał Grzelak 2026-02-25 17:57 ` [PATCH 7/8] drm/intel: add pick.h for the various "picker" helpers Jani Nikula ` (6 subsequent siblings) 12 siblings, 1 reply; 23+ messages in thread From: Jani Nikula @ 2026-02-25 17:57 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula, rodrigo.vivi Add a shared header that's used by i915, xe, and i915 display. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_reg_defs.h | 133 +------------------------ include/drm/intel/reg_bits.h | 139 +++++++++++++++++++++++++++ 2 files changed, 140 insertions(+), 132 deletions(-) create mode 100644 include/drm/intel/reg_bits.h diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h index 9d72f6fae4ae..a1dc7ff2bef7 100644 --- a/drivers/gpu/drm/i915/i915_reg_defs.h +++ b/drivers/gpu/drm/i915/i915_reg_defs.h @@ -6,116 +6,7 @@ #ifndef __I915_REG_DEFS__ #define __I915_REG_DEFS__ -#include <linux/bitfield.h> -#include <linux/bits.h> - -/* - * Wrappers over the generic fixed width BIT_U*() and GENMASK_U*() - * implementations, for compatibility reasons with previous implementation. - */ -#define REG_GENMASK(high, low) GENMASK_U32(high, low) -#define REG_GENMASK64(high, low) GENMASK_U64(high, low) -#define REG_GENMASK16(high, low) GENMASK_U16(high, low) -#define REG_GENMASK8(high, low) GENMASK_U8(high, low) - -#define REG_BIT(n) BIT_U32(n) -#define REG_BIT64(n) BIT_U64(n) -#define REG_BIT16(n) BIT_U16(n) -#define REG_BIT8(n) BIT_U8(n) - -/* - * Local integer constant expression version of is_power_of_2(). - */ -#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0)) - -/** - * REG_FIELD_PREP() - Prepare a u32 bitfield value - * @__mask: shifted mask defining the field's length and position - * @__val: value to put in the field - * - * Local copy of FIELD_PREP() to generate an integer constant expression, force - * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK(). - * - * @return: @__val masked and shifted into the field defined by @__mask. - */ -#define REG_FIELD_PREP(__mask, __val) \ - ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ - BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ - BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ - BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ - BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) - -/** - * REG_FIELD_PREP8() - Prepare a u8 bitfield value - * @__mask: shifted mask defining the field's length and position - * @__val: value to put in the field - * - * Local copy of FIELD_PREP() to generate an integer constant expression, force - * u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and REG_GENMASK8(). - * - * @return: @__val masked and shifted into the field defined by @__mask. - */ -#define REG_FIELD_PREP8(__mask, __val) \ - ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ - BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ - BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \ - BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ - BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) - -/** - * REG_FIELD_GET() - Extract a u32 bitfield value - * @__mask: shifted mask defining the field's length and position - * @__val: value to extract the bitfield value from - * - * Local wrapper for FIELD_GET() to force u32 and for consistency with - * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK(). - * - * @return: Masked and shifted value of the field defined by @__mask in @__val. - */ -#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) - -/** - * REG_FIELD_GET64() - Extract a u64 bitfield value - * @__mask: shifted mask defining the field's length and position - * @__val: value to extract the bitfield value from - * - * Local wrapper for FIELD_GET() to force u64 and for consistency with - * REG_GENMASK64(). - * - * @return: Masked and shifted value of the field defined by @__mask in @__val. - */ -#define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val)) - - -/** - * REG_FIELD_PREP16() - Prepare a u16 bitfield value - * @__mask: shifted mask defining the field's length and position - * @__val: value to put in the field - * - * Local copy of FIELD_PREP16() to generate an integer constant - * expression, force u8 and for consistency with - * REG_FIELD_GET16(), REG_BIT16() and REG_GENMASK16(). - * - * @return: @__val masked and shifted into the field defined by @__mask. - */ -#define REG_FIELD_PREP16(__mask, __val) \ - ((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ - BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ - BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) + \ - BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ - BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) - -#define REG_MASKED_FIELD(mask, value) \ - (BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \ - BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \ - BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \ - ((mask) << 16 | (value))) - -#define REG_MASKED_FIELD_ENABLE(a) \ - (__builtin_choose_expr(__builtin_constant_p(a), REG_MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); REG_MASKED_FIELD(_a, _a); }))) - -#define REG_MASKED_FIELD_DISABLE(a) \ - (REG_MASKED_FIELD((a), 0)) +#include <drm/intel/reg_bits.h> /* * Given the first two numbers __a and __b of arbitrarily many evenly spaced @@ -161,28 +52,6 @@ */ #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) -/** - * REG_FIELD_GET8() - Extract a u8 bitfield value - * @__mask: shifted mask defining the field's length and position - * @__val: value to extract the bitfield value from - * - * Local wrapper for FIELD_GET() to force u8 and for consistency with - * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK(). - * - * @return: Masked and shifted value of the field defined by @__mask in @__val. - */ -#define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val)) - -/** - * REG_FIELD_MAX() - produce the maximum value representable by a field - * @__mask: shifted mask defining the field's length and position - * - * Local wrapper for FIELD_MAX() to return the maximum bit value that can - * be held in the field specified by @_mask, cast to u32 for consistency - * with other macros. - */ -#define REG_FIELD_MAX(__mask) ((u32)FIELD_MAX(__mask)) - typedef struct { u32 reg; } i915_reg_t; diff --git a/include/drm/intel/reg_bits.h b/include/drm/intel/reg_bits.h new file mode 100644 index 000000000000..2a9066e1d808 --- /dev/null +++ b/include/drm/intel/reg_bits.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2026 Intel Corporation */ + +#ifndef _REG_BITS_H_ +#define _REG_BITS_H_ + +#include <linux/bitfield.h> +#include <linux/bits.h> + +/* + * Wrappers over the generic fixed width BIT_U*() and GENMASK_U*() + * implementations, for compatibility reasons with previous implementation. + */ +#define REG_GENMASK(high, low) GENMASK_U32(high, low) +#define REG_GENMASK64(high, low) GENMASK_U64(high, low) +#define REG_GENMASK16(high, low) GENMASK_U16(high, low) +#define REG_GENMASK8(high, low) GENMASK_U8(high, low) + +#define REG_BIT(n) BIT_U32(n) +#define REG_BIT64(n) BIT_U64(n) +#define REG_BIT16(n) BIT_U16(n) +#define REG_BIT8(n) BIT_U8(n) + +/* + * Local integer constant expression version of is_power_of_2(). + */ +#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0)) + +/** + * REG_FIELD_PREP8() - Prepare a u8 bitfield value + * @__mask: shifted mask defining the field's length and position + * @__val: value to put in the field + * + * Local copy of FIELD_PREP() to generate an integer constant expression, force + * u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and REG_GENMASK8(). + * + * @return: @__val masked and shifted into the field defined by @__mask. + */ +#define REG_FIELD_PREP8(__mask, __val) \ + ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \ + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) + +/** + * REG_FIELD_PREP16() - Prepare a u16 bitfield value + * @__mask: shifted mask defining the field's length and position + * @__val: value to put in the field + * + * Local copy of FIELD_PREP16() to generate an integer constant + * expression, force u8 and for consistency with + * REG_FIELD_GET16(), REG_BIT16() and REG_GENMASK16(). + * + * @return: @__val masked and shifted into the field defined by @__mask. + */ +#define REG_FIELD_PREP16(__mask, __val) \ + ((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) + \ + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) + +/** + * REG_FIELD_PREP() - Prepare a u32 bitfield value + * @__mask: shifted mask defining the field's length and position + * @__val: value to put in the field + * + * Local copy of FIELD_PREP() to generate an integer constant expression, force + * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK(). + * + * @return: @__val masked and shifted into the field defined by @__mask. + */ +#define REG_FIELD_PREP(__mask, __val) \ + ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) + +/** + * REG_FIELD_GET8() - Extract a u8 bitfield value + * @__mask: shifted mask defining the field's length and position + * @__val: value to extract the bitfield value from + * + * Local wrapper for FIELD_GET() to force u8 and for consistency with + * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK(). + * + * @return: Masked and shifted value of the field defined by @__mask in @__val. + */ +#define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val)) + +/** + * REG_FIELD_GET() - Extract a u32 bitfield value + * @__mask: shifted mask defining the field's length and position + * @__val: value to extract the bitfield value from + * + * Local wrapper for FIELD_GET() to force u32 and for consistency with + * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK(). + * + * @return: Masked and shifted value of the field defined by @__mask in @__val. + */ +#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) + +/** + * REG_FIELD_GET64() - Extract a u64 bitfield value + * @__mask: shifted mask defining the field's length and position + * @__val: value to extract the bitfield value from + * + * Local wrapper for FIELD_GET() to force u64 and for consistency with + * REG_GENMASK64(). + * + * @return: Masked and shifted value of the field defined by @__mask in @__val. + */ +#define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val)) + +/** + * REG_FIELD_MAX() - produce the maximum value representable by a field + * @__mask: shifted mask defining the field's length and position + * + * Local wrapper for FIELD_MAX() to return the maximum bit value that can + * be held in the field specified by @_mask, cast to u32 for consistency + * with other macros. + */ +#define REG_FIELD_MAX(__mask) ((u32)FIELD_MAX(__mask)) + +#define REG_MASKED_FIELD(mask, value) \ + (BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \ + ((mask) << 16 | (value))) + +#define REG_MASKED_FIELD_ENABLE(a) \ + (__builtin_choose_expr(__builtin_constant_p(a), REG_MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); REG_MASKED_FIELD(_a, _a); }))) + +#define REG_MASKED_FIELD_DISABLE(a) \ + (REG_MASKED_FIELD((a), 0)) + +#endif -- 2.47.3 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 6/8] drm/intel: add reg_bits.h for the various register content helpers 2026-02-25 17:57 ` [PATCH 6/8] drm/intel: add reg_bits.h for the various register content helpers Jani Nikula @ 2026-03-02 20:11 ` Michał Grzelak 0 siblings, 0 replies; 23+ messages in thread From: Michał Grzelak @ 2026-03-02 20:11 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, intel-xe, rodrigo.vivi [-- Attachment #1: Type: text/plain, Size: 227 bytes --] On Wed, 25 Feb 2026, Jani Nikula wrote: > Add a shared header that's used by i915, xe, and i915 display. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> BR, Michał ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 7/8] drm/intel: add pick.h for the various "picker" helpers 2026-02-25 17:57 [PATCH 0/8] drm/{i915,xe}: refactor register helpers Jani Nikula ` (5 preceding siblings ...) 2026-02-25 17:57 ` [PATCH 6/8] drm/intel: add reg_bits.h for the various register content helpers Jani Nikula @ 2026-02-25 17:57 ` Jani Nikula 2026-03-02 20:11 ` Michał Grzelak 2026-02-25 17:57 ` [PATCH 8/8] drm/i915/gt: prefer _PICK_EVEN() over _PICK() Jani Nikula ` (5 subsequent siblings) 12 siblings, 1 reply; 23+ messages in thread From: Jani Nikula @ 2026-02-25 17:57 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula, rodrigo.vivi Add a shared header that's used by i915, xe, and i915 display. This allows us to drop the compat-i915-headers/i915_reg_defs.h include from xe_reg_defs.h. All the register macro helpers were subtly pulled in from i915 to all of xe through this. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_reg_defs.h | 45 +--------------- .../drm/xe/compat-i915-headers/intel_uncore.h | 1 + drivers/gpu/drm/xe/regs/xe_reg_defs.h | 5 +- include/drm/intel/pick.h | 51 +++++++++++++++++++ 4 files changed, 56 insertions(+), 46 deletions(-) create mode 100644 include/drm/intel/pick.h diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h index a1dc7ff2bef7..e897d3ccbf9e 100644 --- a/drivers/gpu/drm/i915/i915_reg_defs.h +++ b/drivers/gpu/drm/i915/i915_reg_defs.h @@ -6,52 +6,9 @@ #ifndef __I915_REG_DEFS__ #define __I915_REG_DEFS__ +#include <drm/intel/pick.h> #include <drm/intel/reg_bits.h> -/* - * Given the first two numbers __a and __b of arbitrarily many evenly spaced - * numbers, pick the 0-based __index'th value. - * - * Always prefer this over _PICK() if the numbers are evenly spaced. - */ -#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) - -/* - * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets. - * @__c_index corresponds to the index in which the second range starts to be - * used. Using math interval notation, the first range is used for indexes [ 0, - * @__c_index), while the second range is used for [ @__c_index, ... ). Example: - * - * #define _FOO_A 0xf000 - * #define _FOO_B 0xf004 - * #define _FOO_C 0xf008 - * #define _SUPER_FOO_A 0xa000 - * #define _SUPER_FOO_B 0xa100 - * #define FOO(x) _MMIO(_PICK_EVEN_2RANGES(x, 3, \ - * _FOO_A, _FOO_B, \ - * _SUPER_FOO_A, _SUPER_FOO_B)) - * - * This expands to: - * 0: 0xf000, - * 1: 0xf004, - * 2: 0xf008, - * 3: 0xa000, - * 4: 0xa100, - * 5: 0xa200, - * ... - */ -#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d) \ - (BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) + \ - ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) : \ - _PICK_EVEN((__index) - (__c_index), __c, __d))) - -/* - * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. - * - * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. - */ -#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) - typedef struct { u32 reg; } i915_reg_t; diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h index c5e198ace7bc..a8cfd65119e0 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h @@ -6,6 +6,7 @@ #ifndef __INTEL_UNCORE_H__ #define __INTEL_UNCORE_H__ +#include "i915_reg_defs.h" #include "xe_device.h" #include "xe_device_types.h" #include "xe_mmio.h" diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h index c39aab843e35..27ac0bf1f6cd 100644 --- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h +++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h @@ -6,12 +6,13 @@ #ifndef _XE_REG_DEFS_H_ #define _XE_REG_DEFS_H_ +#include <drm/intel/pick.h> +#include <drm/intel/reg_bits.h> + #include <linux/build_bug.h> #include <linux/log2.h> #include <linux/sizes.h> -#include "compat-i915-headers/i915_reg_defs.h" - /** * XE_REG_ADDR_MAX - The upper limit on MMIO register address * diff --git a/include/drm/intel/pick.h b/include/drm/intel/pick.h new file mode 100644 index 000000000000..d976fab8f270 --- /dev/null +++ b/include/drm/intel/pick.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2026 Intel Corporation */ + +#ifndef _PICK_H_ +#define _PICK_H_ + +/* + * Given the first two numbers __a and __b of arbitrarily many evenly spaced + * numbers, pick the 0-based __index'th value. + * + * Always prefer this over _PICK() if the numbers are evenly spaced. + */ +#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) + +/* + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets. + * @__c_index corresponds to the index in which the second range starts to be + * used. Using math interval notation, the first range is used for indexes [ 0, + * @__c_index), while the second range is used for [ @__c_index, ... ). Example: + * + * #define _FOO_A 0xf000 + * #define _FOO_B 0xf004 + * #define _FOO_C 0xf008 + * #define _SUPER_FOO_A 0xa000 + * #define _SUPER_FOO_B 0xa100 + * #define FOO(x) _MMIO(_PICK_EVEN_2RANGES(x, 3, \ + * _FOO_A, _FOO_B, \ + * _SUPER_FOO_A, _SUPER_FOO_B)) + * + * This expands to: + * 0: 0xf000, + * 1: 0xf004, + * 2: 0xf008, + * 3: 0xa000, + * 4: 0xa100, + * 5: 0xa200, + * ... + */ +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d) \ + (BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) + \ + ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) : \ + _PICK_EVEN((__index) - (__c_index), __c, __d))) + +/* + * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. + * + * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. + */ +#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) + +#endif -- 2.47.3 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 7/8] drm/intel: add pick.h for the various "picker" helpers 2026-02-25 17:57 ` [PATCH 7/8] drm/intel: add pick.h for the various "picker" helpers Jani Nikula @ 2026-03-02 20:11 ` Michał Grzelak 0 siblings, 0 replies; 23+ messages in thread From: Michał Grzelak @ 2026-03-02 20:11 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, intel-xe, rodrigo.vivi [-- Attachment #1: Type: text/plain, Size: 416 bytes --] On Wed, 25 Feb 2026, Jani Nikula wrote: > Add a shared header that's used by i915, xe, and i915 display. > > This allows us to drop the compat-i915-headers/i915_reg_defs.h include > from xe_reg_defs.h. All the register macro helpers were subtly pulled in > from i915 to all of xe through this. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> BR, Michał ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 8/8] drm/i915/gt: prefer _PICK_EVEN() over _PICK() 2026-02-25 17:57 [PATCH 0/8] drm/{i915,xe}: refactor register helpers Jani Nikula ` (6 preceding siblings ...) 2026-02-25 17:57 ` [PATCH 7/8] drm/intel: add pick.h for the various "picker" helpers Jani Nikula @ 2026-02-25 17:57 ` Jani Nikula 2026-03-02 20:12 ` Michał Grzelak 2026-02-25 19:02 ` ✗ CI.checkpatch: warning for drm/{i915,xe}: refactor register helpers Patchwork ` (4 subsequent siblings) 12 siblings, 1 reply; 23+ messages in thread From: Jani Nikula @ 2026-02-25 17:57 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula, rodrigo.vivi There's no need to use _PICK() here. Use the simpler one instead. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 14d31882e9e7..3ba9b2206b79 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -321,11 +321,9 @@ #define _RING_FAULT_REG_VCS 0x4194 #define _RING_FAULT_REG_BCS 0x4294 #define _RING_FAULT_REG_VECS 0x4394 -#define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \ - _RING_FAULT_REG_RCS, \ - _RING_FAULT_REG_VCS, \ - _RING_FAULT_REG_VECS, \ - _RING_FAULT_REG_BCS)) +#define RING_FAULT_REG(engine) _MMIO(_PICK_EVEN((engine)->class, \ + _RING_FAULT_REG_RCS, \ + _RING_FAULT_REG_VCS)) #define RING_FAULT_VADDR_MASK REG_GENMASK(31, 12) /* pre-bdw */ #define RING_FAULT_ENGINE_ID_MASK REG_GENMASK(16, 12) /* bdw+ */ #define RING_FAULT_GTTSEL_MASK REG_BIT(11) /* pre-bdw */ -- 2.47.3 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 8/8] drm/i915/gt: prefer _PICK_EVEN() over _PICK() 2026-02-25 17:57 ` [PATCH 8/8] drm/i915/gt: prefer _PICK_EVEN() over _PICK() Jani Nikula @ 2026-03-02 20:12 ` Michał Grzelak 0 siblings, 0 replies; 23+ messages in thread From: Michał Grzelak @ 2026-03-02 20:12 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, intel-xe, rodrigo.vivi [-- Attachment #1: Type: text/plain, Size: 230 bytes --] On Wed, 25 Feb 2026, Jani Nikula wrote: > There's no need to use _PICK() here. Use the simpler one instead. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> BR, Michał ^ permalink raw reply [flat|nested] 23+ messages in thread
* ✗ CI.checkpatch: warning for drm/{i915,xe}: refactor register helpers 2026-02-25 17:57 [PATCH 0/8] drm/{i915,xe}: refactor register helpers Jani Nikula ` (7 preceding siblings ...) 2026-02-25 17:57 ` [PATCH 8/8] drm/i915/gt: prefer _PICK_EVEN() over _PICK() Jani Nikula @ 2026-02-25 19:02 ` Patchwork 2026-02-25 19:03 ` ✓ CI.KUnit: success " Patchwork ` (3 subsequent siblings) 12 siblings, 0 replies; 23+ messages in thread From: Patchwork @ 2026-02-25 19:02 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-xe == Series Details == Series: drm/{i915,xe}: refactor register helpers URL : https://patchwork.freedesktop.org/series/162163/ State : warning == Summary == + KERNEL=/kernel + git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt Cloning into 'mt'... warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/ + git -C mt rev-list -n1 origin/master 1f57ba1afceae32108bd24770069f764d940a0e4 + cd /kernel + git config --global --add safe.directory /kernel + git log -n1 commit 26b374c51d1ed04384213b4e862b18f1fc778228 Author: Jani Nikula <jani.nikula@intel.com> Date: Wed Feb 25 19:57:10 2026 +0200 drm/i915/gt: prefer _PICK_EVEN() over _PICK() There's no need to use _PICK() here. Use the simpler one instead. Signed-off-by: Jani Nikula <jani.nikula@intel.com> + /mt/dim checkpatch 940d2c5064ed09bca924fd8aa017be99cc745b31 drm-intel 72ce93d5668f drm/i915/reg: make masked field helpers constexpr -:32: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask' - possible side-effects? #32: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:109: +#define _MASKED_FIELD(mask, value) \ + (BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \ + __MASKED_FIELD(mask, value)) -:32: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'value' - possible side-effects? #32: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:109: +#define _MASKED_FIELD(mask, value) \ + (BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \ + __MASKED_FIELD(mask, value)) -:33: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #33: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:110: + (BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \ -:34: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #34: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:111: + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \ -:35: WARNING:LONG_LINE: line length of 134 exceeds 100 columns #35: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:112: + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \ -:38: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'a' - possible side-effects? #38: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:115: +#define _MASKED_BIT_ENABLE(a) \ + (__builtin_choose_expr(__builtin_constant_p(a), _MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }))) -:39: WARNING:LONG_LINE: line length of 131 exceeds 100 columns #39: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:116: + (__builtin_choose_expr(__builtin_constant_p(a), _MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }))) total: 0 errors, 4 warnings, 3 checks, 28 lines checked 6ea5f612e6dd drm/i915/lrc: switch to _MASKED_BIT_ENABLE() and _MASKED_BIT_DISABLE() 169a1233ffee drm/{i915, xe}/reg: rename masked field helpers REG_MASKED_FIELD*() -:16: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?) #16: sed -i 's/_MASKED_BIT_ENABLE/REG_MASKED_FIELD_ENABLE/g' $(git grep -wl _MASKED_BIT_ENABLE) -:720: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask' - possible side-effects? #720: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:108: +#define REG_MASKED_FIELD(mask, value) \ (BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \ ((mask) << 16 | (value))) -:720: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'value' - possible side-effects? #720: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:108: +#define REG_MASKED_FIELD(mask, value) \ (BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \ ((mask) << 16 | (value))) -:728: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'a' - possible side-effects? #728: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:114: +#define REG_MASKED_FIELD_ENABLE(a) \ + (__builtin_choose_expr(__builtin_constant_p(a), REG_MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); REG_MASKED_FIELD(_a, _a); }))) -:729: WARNING:LONG_LINE: line length of 137 exceeds 100 columns #729: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:115: + (__builtin_choose_expr(__builtin_constant_p(a), REG_MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); REG_MASKED_FIELD(_a, _a); }))) total: 0 errors, 2 warnings, 3 checks, 974 lines checked e1e1e47e0322 drm/i915/perf: prefer REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() 41419f35d16d drm/xe/oa: prefer REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() ebaf64b56930 drm/intel: add reg_bits.h for the various register content helpers -:163: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #163: new file mode 100644 -:194: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__x' - possible side-effects? #194: FILE: include/drm/intel/reg_bits.h:27: +#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0)) -:206: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__mask' - possible side-effects? #206: FILE: include/drm/intel/reg_bits.h:39: +#define REG_FIELD_PREP8(__mask, __val) \ + ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \ + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) -:206: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__val' - possible side-effects? #206: FILE: include/drm/intel/reg_bits.h:39: +#define REG_FIELD_PREP8(__mask, __val) \ + ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \ + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) -:211: WARNING:LONG_LINE: line length of 128 exceeds 100 columns #211: FILE: include/drm/intel/reg_bits.h:44: + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) -:224: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__mask' - possible side-effects? #224: FILE: include/drm/intel/reg_bits.h:57: +#define REG_FIELD_PREP16(__mask, __val) \ + ((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) + \ + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) -:224: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__val' - possible side-effects? #224: FILE: include/drm/intel/reg_bits.h:57: +#define REG_FIELD_PREP16(__mask, __val) \ + ((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) + \ + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) -:229: WARNING:LONG_LINE: line length of 128 exceeds 100 columns #229: FILE: include/drm/intel/reg_bits.h:62: + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) -:241: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__mask' - possible side-effects? #241: FILE: include/drm/intel/reg_bits.h:74: +#define REG_FIELD_PREP(__mask, __val) \ + ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) -:241: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__val' - possible side-effects? #241: FILE: include/drm/intel/reg_bits.h:74: +#define REG_FIELD_PREP(__mask, __val) \ + ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) -:246: WARNING:LONG_LINE: line length of 128 exceeds 100 columns #246: FILE: include/drm/intel/reg_bits.h:79: + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) -:294: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask' - possible side-effects? #294: FILE: include/drm/intel/reg_bits.h:127: +#define REG_MASKED_FIELD(mask, value) \ + (BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \ + ((mask) << 16 | (value))) -:294: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'value' - possible side-effects? #294: FILE: include/drm/intel/reg_bits.h:127: +#define REG_MASKED_FIELD(mask, value) \ + (BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \ + ((mask) << 16 | (value))) -:295: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #295: FILE: include/drm/intel/reg_bits.h:128: + (BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \ -:296: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #296: FILE: include/drm/intel/reg_bits.h:129: + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \ -:297: WARNING:LONG_LINE: line length of 134 exceeds 100 columns #297: FILE: include/drm/intel/reg_bits.h:130: + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \ -:300: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'a' - possible side-effects? #300: FILE: include/drm/intel/reg_bits.h:133: +#define REG_MASKED_FIELD_ENABLE(a) \ + (__builtin_choose_expr(__builtin_constant_p(a), REG_MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); REG_MASKED_FIELD(_a, _a); }))) -:301: WARNING:LONG_LINE: line length of 137 exceeds 100 columns #301: FILE: include/drm/intel/reg_bits.h:134: + (__builtin_choose_expr(__builtin_constant_p(a), REG_MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); REG_MASKED_FIELD(_a, _a); }))) total: 0 errors, 8 warnings, 10 checks, 284 lines checked 9a7a4d050343 drm/intel: add pick.h for the various "picker" helpers -:105: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #105: new file mode 100644 -:122: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__a' - possible side-effects? #122: FILE: include/drm/intel/pick.h:13: +#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) -:148: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__index' - possible side-effects? #148: FILE: include/drm/intel/pick.h:39: +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d) \ + (BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) + \ + ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) : \ + _PICK_EVEN((__index) - (__c_index), __c, __d))) -:148: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__c_index' - possible side-effects? #148: FILE: include/drm/intel/pick.h:39: +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d) \ + (BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) + \ + ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) : \ + _PICK_EVEN((__index) - (__c_index), __c, __d))) total: 0 errors, 1 warnings, 3 checks, 126 lines checked 26b374c51d1e drm/i915/gt: prefer _PICK_EVEN() over _PICK() ^ permalink raw reply [flat|nested] 23+ messages in thread
* ✓ CI.KUnit: success for drm/{i915,xe}: refactor register helpers 2026-02-25 17:57 [PATCH 0/8] drm/{i915,xe}: refactor register helpers Jani Nikula ` (8 preceding siblings ...) 2026-02-25 19:02 ` ✗ CI.checkpatch: warning for drm/{i915,xe}: refactor register helpers Patchwork @ 2026-02-25 19:03 ` Patchwork 2026-02-25 19:39 ` ✗ Xe.CI.BAT: failure " Patchwork ` (2 subsequent siblings) 12 siblings, 0 replies; 23+ messages in thread From: Patchwork @ 2026-02-25 19:03 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-xe == Series Details == Series: drm/{i915,xe}: refactor register helpers URL : https://patchwork.freedesktop.org/series/162163/ State : success == Summary == + trap cleanup EXIT + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig [19:02:03] Configuring KUnit Kernel ... Generating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [19:02:08] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48 [19:02:38] Starting KUnit Kernel (1/1)... [19:02:38] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [19:02:38] ================== guc_buf (11 subtests) =================== [19:02:38] [PASSED] test_smallest [19:02:38] [PASSED] test_largest [19:02:38] [PASSED] test_granular [19:02:38] [PASSED] test_unique [19:02:38] [PASSED] test_overlap [19:02:38] [PASSED] test_reusable [19:02:38] [PASSED] test_too_big [19:02:38] [PASSED] test_flush [19:02:38] [PASSED] test_lookup [19:02:38] [PASSED] test_data [19:02:38] [PASSED] test_class [19:02:38] ===================== [PASSED] guc_buf ===================== [19:02:38] =================== guc_dbm (7 subtests) =================== [19:02:38] [PASSED] test_empty [19:02:38] [PASSED] test_default [19:02:38] ======================== test_size ======================== [19:02:38] [PASSED] 4 [19:02:38] [PASSED] 8 [19:02:38] [PASSED] 32 [19:02:38] [PASSED] 256 [19:02:38] ==================== [PASSED] test_size ==================== [19:02:38] ======================= test_reuse ======================== [19:02:38] [PASSED] 4 [19:02:38] [PASSED] 8 [19:02:38] [PASSED] 32 [19:02:38] [PASSED] 256 [19:02:38] =================== [PASSED] test_reuse ==================== [19:02:38] =================== test_range_overlap ==================== [19:02:38] [PASSED] 4 [19:02:38] [PASSED] 8 [19:02:38] [PASSED] 32 [19:02:38] [PASSED] 256 [19:02:38] =============== [PASSED] test_range_overlap ================ [19:02:38] =================== test_range_compact ==================== [19:02:38] [PASSED] 4 [19:02:38] [PASSED] 8 [19:02:38] [PASSED] 32 [19:02:38] [PASSED] 256 [19:02:38] =============== [PASSED] test_range_compact ================ [19:02:38] ==================== test_range_spare ===================== [19:02:38] [PASSED] 4 [19:02:38] [PASSED] 8 [19:02:38] [PASSED] 32 [19:02:38] [PASSED] 256 [19:02:38] ================ [PASSED] test_range_spare ================= [19:02:38] ===================== [PASSED] guc_dbm ===================== [19:02:38] =================== guc_idm (6 subtests) =================== [19:02:38] [PASSED] bad_init [19:02:38] [PASSED] no_init [19:02:38] [PASSED] init_fini [19:02:38] [PASSED] check_used [19:02:38] [PASSED] check_quota [19:02:38] [PASSED] check_all [19:02:38] ===================== [PASSED] guc_idm ===================== [19:02:38] ================== no_relay (3 subtests) =================== [19:02:38] [PASSED] xe_drops_guc2pf_if_not_ready [19:02:38] [PASSED] xe_drops_guc2vf_if_not_ready [19:02:38] [PASSED] xe_rejects_send_if_not_ready [19:02:38] ==================== [PASSED] no_relay ===================== [19:02:38] ================== pf_relay (14 subtests) ================== [19:02:38] [PASSED] pf_rejects_guc2pf_too_short [19:02:38] [PASSED] pf_rejects_guc2pf_too_long [19:02:38] [PASSED] pf_rejects_guc2pf_no_payload [19:02:38] [PASSED] pf_fails_no_payload [19:02:38] [PASSED] pf_fails_bad_origin [19:02:38] [PASSED] pf_fails_bad_type [19:02:38] [PASSED] pf_txn_reports_error [19:02:38] [PASSED] pf_txn_sends_pf2guc [19:02:38] [PASSED] pf_sends_pf2guc [19:02:38] [SKIPPED] pf_loopback_nop [19:02:38] [SKIPPED] pf_loopback_echo [19:02:38] [SKIPPED] pf_loopback_fail [19:02:38] [SKIPPED] pf_loopback_busy [19:02:38] [SKIPPED] pf_loopback_retry [19:02:38] ==================== [PASSED] pf_relay ===================== [19:02:38] ================== vf_relay (3 subtests) =================== [19:02:38] [PASSED] vf_rejects_guc2vf_too_short [19:02:38] [PASSED] vf_rejects_guc2vf_too_long [19:02:38] [PASSED] vf_rejects_guc2vf_no_payload [19:02:38] ==================== [PASSED] vf_relay ===================== [19:02:38] ================ pf_gt_config (9 subtests) ================= [19:02:38] [PASSED] fair_contexts_1vf [19:02:38] [PASSED] fair_doorbells_1vf [19:02:38] [PASSED] fair_ggtt_1vf [19:02:38] ====================== fair_vram_1vf ====================== [19:02:38] [PASSED] 3.50 GiB [19:02:38] [PASSED] 11.5 GiB [19:02:38] [PASSED] 15.5 GiB [19:02:38] [PASSED] 31.5 GiB [19:02:38] [PASSED] 63.5 GiB [19:02:38] [PASSED] 13.9 GiB [19:02:38] ================== [PASSED] fair_vram_1vf ================== [19:02:38] ================ fair_vram_1vf_admin_only ================= [19:02:38] [PASSED] 3.50 GiB [19:02:38] [PASSED] 11.5 GiB [19:02:38] [PASSED] 15.5 GiB [19:02:38] [PASSED] 31.5 GiB [19:02:38] [PASSED] 63.5 GiB [19:02:38] [PASSED] 13.9 GiB [19:02:38] ============ [PASSED] fair_vram_1vf_admin_only ============= [19:02:38] ====================== fair_contexts ====================== [19:02:38] [PASSED] 1 VF [19:02:38] [PASSED] 2 VFs [19:02:38] [PASSED] 3 VFs [19:02:38] [PASSED] 4 VFs [19:02:38] [PASSED] 5 VFs [19:02:38] [PASSED] 6 VFs [19:02:38] [PASSED] 7 VFs [19:02:38] [PASSED] 8 VFs [19:02:38] [PASSED] 9 VFs [19:02:38] [PASSED] 10 VFs [19:02:38] [PASSED] 11 VFs [19:02:38] [PASSED] 12 VFs [19:02:38] [PASSED] 13 VFs [19:02:38] [PASSED] 14 VFs [19:02:38] [PASSED] 15 VFs [19:02:38] [PASSED] 16 VFs [19:02:38] [PASSED] 17 VFs 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======================== fair_vram ======================== [19:02:38] [PASSED] 1 VF [19:02:38] [PASSED] 2 VFs [19:02:38] [PASSED] 3 VFs [19:02:38] [PASSED] 4 VFs [19:02:38] [PASSED] 5 VFs [19:02:38] [PASSED] 6 VFs [19:02:38] [PASSED] 7 VFs [19:02:38] [PASSED] 8 VFs [19:02:38] [PASSED] 9 VFs [19:02:38] [PASSED] 10 VFs [19:02:38] [PASSED] 11 VFs [19:02:38] [PASSED] 12 VFs [19:02:38] [PASSED] 13 VFs [19:02:38] [PASSED] 14 VFs [19:02:38] [PASSED] 15 VFs [19:02:38] [PASSED] 16 VFs [19:02:38] [PASSED] 17 VFs [19:02:38] [PASSED] 18 VFs [19:02:38] [PASSED] 19 VFs [19:02:38] [PASSED] 20 VFs [19:02:38] [PASSED] 21 VFs [19:02:38] [PASSED] 22 VFs [19:02:38] [PASSED] 23 VFs [19:02:38] [PASSED] 24 VFs [19:02:38] [PASSED] 25 VFs [19:02:38] [PASSED] 26 VFs [19:02:38] [PASSED] 27 VFs [19:02:38] [PASSED] 28 VFs [19:02:38] [PASSED] 29 VFs [19:02:38] [PASSED] 30 VFs [19:02:38] [PASSED] 31 VFs [19:02:38] [PASSED] 32 VFs [19:02:38] [PASSED] 33 VFs [19:02:38] [PASSED] 34 VFs [19:02:38] [PASSED] 35 VFs [19:02:38] [PASSED] 36 VFs [19:02:38] [PASSED] 37 VFs [19:02:38] [PASSED] 38 VFs [19:02:38] [PASSED] 39 VFs [19:02:38] [PASSED] 40 VFs [19:02:38] [PASSED] 41 VFs [19:02:38] [PASSED] 42 VFs [19:02:38] [PASSED] 43 VFs [19:02:38] [PASSED] 44 VFs [19:02:38] [PASSED] 45 VFs [19:02:38] [PASSED] 46 VFs [19:02:38] [PASSED] 47 VFs [19:02:38] [PASSED] 48 VFs [19:02:38] [PASSED] 49 VFs [19:02:38] [PASSED] 50 VFs [19:02:38] [PASSED] 51 VFs [19:02:38] [PASSED] 52 VFs [19:02:38] [PASSED] 53 VFs [19:02:38] [PASSED] 54 VFs [19:02:38] [PASSED] 55 VFs [19:02:38] [PASSED] 56 VFs [19:02:38] [PASSED] 57 VFs [19:02:38] [PASSED] 58 VFs [19:02:38] [PASSED] 59 VFs [19:02:38] [PASSED] 60 VFs [19:02:38] [PASSED] 61 VFs [19:02:38] [PASSED] 62 VFs [19:02:38] [PASSED] 63 VFs [19:02:38] ==================== [PASSED] fair_vram ==================== [19:02:38] ================== [PASSED] pf_gt_config =================== [19:02:38] ===================== lmtt (1 subtest) ===================== [19:02:38] ======================== test_ops ========================= [19:02:38] [PASSED] 2-level [19:02:38] [PASSED] multi-level [19:02:38] ==================== [PASSED] test_ops ===================== [19:02:38] ====================== [PASSED] lmtt ======================= [19:02:38] ================= pf_service (11 subtests) ================= [19:02:38] [PASSED] pf_negotiate_any [19:02:38] [PASSED] pf_negotiate_base_match [19:02:38] [PASSED] pf_negotiate_base_newer [19:02:38] [PASSED] pf_negotiate_base_next [19:02:38] [SKIPPED] pf_negotiate_base_older [19:02:38] [PASSED] pf_negotiate_base_prev [19:02:38] [PASSED] pf_negotiate_latest_match [19:02:38] [PASSED] pf_negotiate_latest_newer [19:02:38] [PASSED] pf_negotiate_latest_next [19:02:38] [SKIPPED] pf_negotiate_latest_older [19:02:38] [SKIPPED] pf_negotiate_latest_prev [19:02:38] =================== [PASSED] pf_service ==================== [19:02:38] ================= xe_guc_g2g (2 subtests) ================== [19:02:38] ============== xe_live_guc_g2g_kunit_default ============== [19:02:38] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ========== [19:02:38] ============== xe_live_guc_g2g_kunit_allmem =============== [19:02:38] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ========== [19:02:38] =================== [SKIPPED] xe_guc_g2g =================== [19:02:38] =================== xe_mocs (2 subtests) =================== [19:02:38] ================ xe_live_mocs_kernel_kunit ================ [19:02:38] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============ [19:02:38] ================ xe_live_mocs_reset_kunit ================= [19:02:38] ============ [SKIPPED] xe_live_mocs_reset_kunit ============ [19:02:38] ==================== [SKIPPED] xe_mocs ===================== [19:02:38] ================= xe_migrate (2 subtests) ================== [19:02:38] ================= xe_migrate_sanity_kunit ================= [19:02:38] ============ [SKIPPED] xe_migrate_sanity_kunit ============= [19:02:38] ================== xe_validate_ccs_kunit ================== [19:02:38] ============= [SKIPPED] xe_validate_ccs_kunit ============== [19:02:38] =================== [SKIPPED] xe_migrate =================== [19:02:38] ================== xe_dma_buf (1 subtest) ================== [19:02:38] ==================== xe_dma_buf_kunit ===================== [19:02:38] ================ [SKIPPED] xe_dma_buf_kunit ================ [19:02:38] =================== [SKIPPED] xe_dma_buf =================== [19:02:38] ================= xe_bo_shrink (1 subtest) ================= [19:02:38] =================== xe_bo_shrink_kunit ==================== [19:02:38] =============== [SKIPPED] xe_bo_shrink_kunit =============== [19:02:38] ================== [SKIPPED] xe_bo_shrink ================== [19:02:38] ==================== xe_bo (2 subtests) ==================== [19:02:38] ================== xe_ccs_migrate_kunit =================== [19:02:38] ============== [SKIPPED] xe_ccs_migrate_kunit ============== [19:02:38] ==================== xe_bo_evict_kunit ==================== [19:02:38] =============== [SKIPPED] xe_bo_evict_kunit ================ [19:02:38] ===================== [SKIPPED] xe_bo ====================== [19:02:38] ==================== args (13 subtests) ==================== [19:02:38] [PASSED] count_args_test [19:02:38] [PASSED] call_args_example [19:02:38] [PASSED] call_args_test [19:02:38] [PASSED] drop_first_arg_example [19:02:38] [PASSED] drop_first_arg_test [19:02:38] [PASSED] first_arg_example [19:02:38] [PASSED] first_arg_test [19:02:38] [PASSED] last_arg_example [19:02:38] [PASSED] last_arg_test [19:02:38] [PASSED] pick_arg_example [19:02:38] [PASSED] if_args_example [19:02:38] [PASSED] if_args_test [19:02:38] [PASSED] sep_comma_example [19:02:38] ====================== [PASSED] args ======================= [19:02:38] =================== xe_pci (3 subtests) ==================== [19:02:38] ==================== check_graphics_ip ==================== [19:02:38] [PASSED] 12.00 Xe_LP [19:02:38] [PASSED] 12.10 Xe_LP+ [19:02:38] [PASSED] 12.55 Xe_HPG [19:02:38] [PASSED] 12.60 Xe_HPC [19:02:38] [PASSED] 12.70 Xe_LPG [19:02:38] [PASSED] 12.71 Xe_LPG [19:02:38] [PASSED] 12.74 Xe_LPG+ [19:02:38] [PASSED] 20.01 Xe2_HPG [19:02:38] [PASSED] 20.02 Xe2_HPG [19:02:38] [PASSED] 20.04 Xe2_LPG [19:02:38] [PASSED] 30.00 Xe3_LPG [19:02:38] [PASSED] 30.01 Xe3_LPG [19:02:38] [PASSED] 30.03 Xe3_LPG [19:02:38] [PASSED] 30.04 Xe3_LPG [19:02:38] [PASSED] 30.05 Xe3_LPG [19:02:38] [PASSED] 35.10 Xe3p_LPG [19:02:38] [PASSED] 35.11 Xe3p_XPC [19:02:38] ================ [PASSED] check_graphics_ip ================ [19:02:38] ===================== check_media_ip ====================== [19:02:38] [PASSED] 12.00 Xe_M [19:02:38] [PASSED] 12.55 Xe_HPM [19:02:38] [PASSED] 13.00 Xe_LPM+ [19:02:38] [PASSED] 13.01 Xe2_HPM [19:02:38] [PASSED] 20.00 Xe2_LPM [19:02:38] [PASSED] 30.00 Xe3_LPM [19:02:38] [PASSED] 30.02 Xe3_LPM [19:02:38] [PASSED] 35.00 Xe3p_LPM [19:02:38] [PASSED] 35.03 Xe3p_HPM [19:02:38] ================= [PASSED] check_media_ip ================== [19:02:38] =================== check_platform_desc =================== [19:02:38] [PASSED] 0x9A60 (TIGERLAKE) [19:02:38] [PASSED] 0x9A68 (TIGERLAKE) [19:02:38] [PASSED] 0x9A70 (TIGERLAKE) [19:02:38] [PASSED] 0x9A40 (TIGERLAKE) [19:02:38] [PASSED] 0x9A49 (TIGERLAKE) [19:02:38] [PASSED] 0x9A59 (TIGERLAKE) [19:02:38] [PASSED] 0x9A78 (TIGERLAKE) [19:02:38] [PASSED] 0x9AC0 (TIGERLAKE) [19:02:38] [PASSED] 0x9AC9 (TIGERLAKE) [19:02:38] [PASSED] 0x9AD9 (TIGERLAKE) [19:02:38] [PASSED] 0x9AF8 (TIGERLAKE) [19:02:38] [PASSED] 0x4C80 (ROCKETLAKE) [19:02:38] [PASSED] 0x4C8A (ROCKETLAKE) [19:02:38] [PASSED] 0x4C8B (ROCKETLAKE) [19:02:38] [PASSED] 0x4C8C (ROCKETLAKE) [19:02:38] [PASSED] 0x4C90 (ROCKETLAKE) [19:02:38] [PASSED] 0x4C9A (ROCKETLAKE) [19:02:38] [PASSED] 0x4680 (ALDERLAKE_S) [19:02:38] [PASSED] 0x4682 (ALDERLAKE_S) [19:02:38] [PASSED] 0x4688 (ALDERLAKE_S) [19:02:38] [PASSED] 0x468A (ALDERLAKE_S) [19:02:38] [PASSED] 0x468B (ALDERLAKE_S) [19:02:38] [PASSED] 0x4690 (ALDERLAKE_S) [19:02:38] [PASSED] 0x4692 (ALDERLAKE_S) [19:02:38] [PASSED] 0x4693 (ALDERLAKE_S) [19:02:38] [PASSED] 0x46A0 (ALDERLAKE_P) [19:02:38] [PASSED] 0x46A1 (ALDERLAKE_P) [19:02:38] [PASSED] 0x46A2 (ALDERLAKE_P) [19:02:38] [PASSED] 0x46A3 (ALDERLAKE_P) [19:02:38] [PASSED] 0x46A6 (ALDERLAKE_P) [19:02:38] [PASSED] 0x46A8 (ALDERLAKE_P) [19:02:38] [PASSED] 0x46AA (ALDERLAKE_P) [19:02:38] [PASSED] 0x462A (ALDERLAKE_P) [19:02:38] [PASSED] 0x4626 (ALDERLAKE_P) [19:02:38] [PASSED] 0x4628 (ALDERLAKE_P) [19:02:38] [PASSED] 0x46B0 (ALDERLAKE_P) [19:02:38] [PASSED] 0x46B1 (ALDERLAKE_P) [19:02:38] [PASSED] 0x46B2 (ALDERLAKE_P) [19:02:38] [PASSED] 0x46B3 (ALDERLAKE_P) [19:02:38] [PASSED] 0x46C0 (ALDERLAKE_P) [19:02:38] [PASSED] 0x46C1 (ALDERLAKE_P) [19:02:38] [PASSED] 0x46C2 (ALDERLAKE_P) [19:02:38] [PASSED] 0x46C3 (ALDERLAKE_P) [19:02:38] [PASSED] 0x46D0 (ALDERLAKE_N) [19:02:38] [PASSED] 0x46D1 (ALDERLAKE_N) [19:02:38] [PASSED] 0x46D2 (ALDERLAKE_N) [19:02:38] [PASSED] 0x46D3 (ALDERLAKE_N) [19:02:38] [PASSED] 0x46D4 (ALDERLAKE_N) [19:02:38] [PASSED] 0xA721 (ALDERLAKE_P) [19:02:38] [PASSED] 0xA7A1 (ALDERLAKE_P) [19:02:38] [PASSED] 0xA7A9 (ALDERLAKE_P) [19:02:38] [PASSED] 0xA7AC (ALDERLAKE_P) [19:02:38] [PASSED] 0xA7AD (ALDERLAKE_P) [19:02:38] [PASSED] 0xA720 (ALDERLAKE_P) [19:02:38] [PASSED] 0xA7A0 (ALDERLAKE_P) [19:02:38] [PASSED] 0xA7A8 (ALDERLAKE_P) [19:02:38] [PASSED] 0xA7AA (ALDERLAKE_P) [19:02:38] [PASSED] 0xA7AB (ALDERLAKE_P) [19:02:38] [PASSED] 0xA780 (ALDERLAKE_S) [19:02:38] [PASSED] 0xA781 (ALDERLAKE_S) [19:02:38] [PASSED] 0xA782 (ALDERLAKE_S) [19:02:38] [PASSED] 0xA783 (ALDERLAKE_S) [19:02:38] [PASSED] 0xA788 (ALDERLAKE_S) [19:02:38] [PASSED] 0xA789 (ALDERLAKE_S) [19:02:38] [PASSED] 0xA78A (ALDERLAKE_S) [19:02:38] [PASSED] 0xA78B (ALDERLAKE_S) [19:02:38] [PASSED] 0x4905 (DG1) [19:02:38] [PASSED] 0x4906 (DG1) [19:02:38] [PASSED] 0x4907 (DG1) [19:02:38] [PASSED] 0x4908 (DG1) [19:02:38] [PASSED] 0x4909 (DG1) [19:02:38] [PASSED] 0x56C0 (DG2) [19:02:38] [PASSED] 0x56C2 (DG2) [19:02:38] [PASSED] 0x56C1 (DG2) [19:02:38] [PASSED] 0x7D51 (METEORLAKE) [19:02:38] [PASSED] 0x7DD1 (METEORLAKE) [19:02:38] [PASSED] 0x7D41 (METEORLAKE) [19:02:38] [PASSED] 0x7D67 (METEORLAKE) [19:02:38] [PASSED] 0xB640 (METEORLAKE) [19:02:38] [PASSED] 0x56A0 (DG2) [19:02:38] [PASSED] 0x56A1 (DG2) [19:02:38] [PASSED] 0x56A2 (DG2) [19:02:38] [PASSED] 0x56BE (DG2) [19:02:38] [PASSED] 0x56BF (DG2) [19:02:38] [PASSED] 0x5690 (DG2) [19:02:38] [PASSED] 0x5691 (DG2) [19:02:38] [PASSED] 0x5692 (DG2) [19:02:38] [PASSED] 0x56A5 (DG2) [19:02:38] [PASSED] 0x56A6 (DG2) [19:02:38] [PASSED] 0x56B0 (DG2) [19:02:38] [PASSED] 0x56B1 (DG2) [19:02:38] [PASSED] 0x56BA (DG2) [19:02:38] [PASSED] 0x56BB (DG2) [19:02:38] [PASSED] 0x56BC (DG2) [19:02:38] [PASSED] 0x56BD (DG2) [19:02:38] [PASSED] 0x5693 (DG2) [19:02:38] [PASSED] 0x5694 (DG2) [19:02:38] [PASSED] 0x5695 (DG2) [19:02:38] [PASSED] 0x56A3 (DG2) [19:02:38] [PASSED] 0x56A4 (DG2) [19:02:38] [PASSED] 0x56B2 (DG2) [19:02:38] [PASSED] 0x56B3 (DG2) [19:02:38] [PASSED] 0x5696 (DG2) [19:02:38] [PASSED] 0x5697 (DG2) [19:02:38] [PASSED] 0xB69 (PVC) [19:02:38] [PASSED] 0xB6E (PVC) [19:02:38] [PASSED] 0xBD4 (PVC) [19:02:38] [PASSED] 0xBD5 (PVC) [19:02:38] [PASSED] 0xBD6 (PVC) [19:02:38] [PASSED] 0xBD7 (PVC) [19:02:38] [PASSED] 0xBD8 (PVC) [19:02:38] [PASSED] 0xBD9 (PVC) [19:02:38] [PASSED] 0xBDA (PVC) [19:02:38] [PASSED] 0xBDB (PVC) [19:02:38] [PASSED] 0xBE0 (PVC) [19:02:38] [PASSED] 0xBE1 (PVC) [19:02:38] [PASSED] 0xBE5 (PVC) [19:02:38] [PASSED] 0x7D40 (METEORLAKE) [19:02:38] [PASSED] 0x7D45 (METEORLAKE) [19:02:38] [PASSED] 0x7D55 (METEORLAKE) [19:02:38] [PASSED] 0x7D60 (METEORLAKE) [19:02:38] [PASSED] 0x7DD5 (METEORLAKE) [19:02:38] [PASSED] 0x6420 (LUNARLAKE) [19:02:38] [PASSED] 0x64A0 (LUNARLAKE) [19:02:38] [PASSED] 0x64B0 (LUNARLAKE) [19:02:38] [PASSED] 0xE202 (BATTLEMAGE) [19:02:38] [PASSED] 0xE209 (BATTLEMAGE) [19:02:38] [PASSED] 0xE20B (BATTLEMAGE) [19:02:38] [PASSED] 0xE20C (BATTLEMAGE) [19:02:38] [PASSED] 0xE20D (BATTLEMAGE) [19:02:38] [PASSED] 0xE210 (BATTLEMAGE) [19:02:38] [PASSED] 0xE211 (BATTLEMAGE) [19:02:38] [PASSED] 0xE212 (BATTLEMAGE) [19:02:38] [PASSED] 0xE216 (BATTLEMAGE) [19:02:38] [PASSED] 0xE220 (BATTLEMAGE) [19:02:38] [PASSED] 0xE221 (BATTLEMAGE) [19:02:38] [PASSED] 0xE222 (BATTLEMAGE) [19:02:38] [PASSED] 0xE223 (BATTLEMAGE) [19:02:38] [PASSED] 0xB080 (PANTHERLAKE) [19:02:38] [PASSED] 0xB081 (PANTHERLAKE) [19:02:38] [PASSED] 0xB082 (PANTHERLAKE) [19:02:38] [PASSED] 0xB083 (PANTHERLAKE) [19:02:38] [PASSED] 0xB084 (PANTHERLAKE) [19:02:38] [PASSED] 0xB085 (PANTHERLAKE) [19:02:38] [PASSED] 0xB086 (PANTHERLAKE) [19:02:38] [PASSED] 0xB087 (PANTHERLAKE) [19:02:38] [PASSED] 0xB08F (PANTHERLAKE) [19:02:38] [PASSED] 0xB090 (PANTHERLAKE) [19:02:38] [PASSED] 0xB0A0 (PANTHERLAKE) [19:02:38] [PASSED] 0xB0B0 (PANTHERLAKE) [19:02:38] [PASSED] 0xFD80 (PANTHERLAKE) [19:02:38] [PASSED] 0xFD81 (PANTHERLAKE) [19:02:38] [PASSED] 0xD740 (NOVALAKE_S) [19:02:38] [PASSED] 0xD741 (NOVALAKE_S) [19:02:38] [PASSED] 0xD742 (NOVALAKE_S) [19:02:38] [PASSED] 0xD743 (NOVALAKE_S) [19:02:38] [PASSED] 0xD744 (NOVALAKE_S) [19:02:38] [PASSED] 0xD745 (NOVALAKE_S) [19:02:38] [PASSED] 0x674C (CRESCENTISLAND) [19:02:38] [PASSED] 0xD750 (NOVALAKE_P) [19:02:38] [PASSED] 0xD751 (NOVALAKE_P) [19:02:38] [PASSED] 0xD752 (NOVALAKE_P) [19:02:38] [PASSED] 0xD753 (NOVALAKE_P) [19:02:38] [PASSED] 0xD754 (NOVALAKE_P) [19:02:38] [PASSED] 0xD755 (NOVALAKE_P) [19:02:38] [PASSED] 0xD756 (NOVALAKE_P) [19:02:38] [PASSED] 0xD757 (NOVALAKE_P) [19:02:38] [PASSED] 0xD75F (NOVALAKE_P) [19:02:38] =============== [PASSED] check_platform_desc =============== [19:02:38] ===================== [PASSED] xe_pci ====================== [19:02:38] =================== xe_rtp (2 subtests) ==================== [19:02:39] =============== xe_rtp_process_to_sr_tests ================ [19:02:39] [PASSED] coalesce-same-reg [19:02:39] [PASSED] no-match-no-add [19:02:39] [PASSED] match-or [19:02:39] [PASSED] match-or-xfail [19:02:39] [PASSED] no-match-no-add-multiple-rules [19:02:39] [PASSED] two-regs-two-entries [19:02:39] [PASSED] clr-one-set-other [19:02:39] [PASSED] set-field [19:02:39] [PASSED] conflict-duplicate stty: 'standard input': Inappropriate ioctl for device [19:02:39] [PASSED] conflict-not-disjoint [19:02:39] [PASSED] conflict-reg-type [19:02:39] =========== [PASSED] xe_rtp_process_to_sr_tests ============ [19:02:39] ================== xe_rtp_process_tests =================== [19:02:39] [PASSED] active1 [19:02:39] [PASSED] active2 [19:02:39] [PASSED] active-inactive [19:02:39] [PASSED] inactive-active [19:02:39] [PASSED] inactive-1st_or_active-inactive [19:02:39] [PASSED] inactive-2nd_or_active-inactive [19:02:39] [PASSED] inactive-last_or_active-inactive [19:02:39] [PASSED] inactive-no_or_active-inactive [19:02:39] ============== [PASSED] xe_rtp_process_tests =============== [19:02:39] ===================== [PASSED] xe_rtp ====================== [19:02:39] ==================== xe_wa (1 subtest) ===================== [19:02:39] ======================== xe_wa_gt ========================= [19:02:39] [PASSED] TIGERLAKE B0 [19:02:39] [PASSED] DG1 A0 [19:02:39] [PASSED] DG1 B0 [19:02:39] [PASSED] ALDERLAKE_S A0 [19:02:39] [PASSED] ALDERLAKE_S B0 [19:02:39] [PASSED] ALDERLAKE_S C0 [19:02:39] [PASSED] ALDERLAKE_S D0 [19:02:39] [PASSED] ALDERLAKE_P A0 [19:02:39] [PASSED] ALDERLAKE_P B0 [19:02:39] [PASSED] ALDERLAKE_P C0 [19:02:39] [PASSED] ALDERLAKE_S RPLS D0 [19:02:39] [PASSED] ALDERLAKE_P RPLU E0 [19:02:39] [PASSED] DG2 G10 C0 [19:02:39] [PASSED] DG2 G11 B1 [19:02:39] [PASSED] DG2 G12 A1 [19:02:39] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0 [19:02:39] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0 [19:02:39] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0 [19:02:39] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0 [19:02:39] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0 [19:02:39] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1 [19:02:39] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0 [19:02:39] ==================== [PASSED] xe_wa_gt ===================== [19:02:39] ====================== [PASSED] xe_wa ====================== [19:02:39] ============================================================ [19:02:39] Testing complete. Ran 597 tests: passed: 579, skipped: 18 [19:02:39] Elapsed time: 35.316s total, 4.265s configuring, 30.383s building, 0.620s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig [19:02:39] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [19:02:40] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48 [19:03:04] Starting KUnit Kernel (1/1)... [19:03:04] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [19:03:05] ============ drm_test_pick_cmdline (2 subtests) ============ [19:03:05] [PASSED] drm_test_pick_cmdline_res_1920_1080_60 [19:03:05] =============== drm_test_pick_cmdline_named =============== [19:03:05] [PASSED] NTSC [19:03:05] [PASSED] NTSC-J [19:03:05] [PASSED] PAL [19:03:05] [PASSED] PAL-M [19:03:05] =========== [PASSED] drm_test_pick_cmdline_named =========== [19:03:05] ============== [PASSED] drm_test_pick_cmdline ============== [19:03:05] == drm_test_atomic_get_connector_for_encoder (1 subtest) === [19:03:05] [PASSED] drm_test_drm_atomic_get_connector_for_encoder [19:03:05] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ==== [19:03:05] =========== drm_validate_clone_mode (2 subtests) =========== [19:03:05] ============== drm_test_check_in_clone_mode =============== [19:03:05] [PASSED] in_clone_mode [19:03:05] [PASSED] not_in_clone_mode [19:03:05] ========== [PASSED] drm_test_check_in_clone_mode =========== [19:03:05] =============== drm_test_check_valid_clones =============== [19:03:05] [PASSED] not_in_clone_mode [19:03:05] [PASSED] valid_clone [19:03:05] [PASSED] invalid_clone [19:03:05] =========== [PASSED] drm_test_check_valid_clones =========== [19:03:05] ============= [PASSED] drm_validate_clone_mode ============= [19:03:05] ============= drm_validate_modeset (1 subtest) ============= [19:03:05] [PASSED] drm_test_check_connector_changed_modeset [19:03:05] ============== [PASSED] drm_validate_modeset =============== [19:03:05] ====== drm_test_bridge_get_current_state (2 subtests) ====== [19:03:05] [PASSED] drm_test_drm_bridge_get_current_state_atomic [19:03:05] [PASSED] drm_test_drm_bridge_get_current_state_legacy [19:03:05] ======== [PASSED] drm_test_bridge_get_current_state ======== [19:03:05] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ====== [19:03:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic [19:03:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled [19:03:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy [19:03:05] ======== [PASSED] drm_test_bridge_helper_reset_crtc ======== [19:03:05] ============== drm_bridge_alloc (2 subtests) =============== [19:03:05] [PASSED] drm_test_drm_bridge_alloc_basic [19:03:05] [PASSED] drm_test_drm_bridge_alloc_get_put [19:03:05] ================ [PASSED] drm_bridge_alloc ================= [19:03:05] ============= drm_cmdline_parser (40 subtests) ============= [19:03:05] [PASSED] drm_test_cmdline_force_d_only [19:03:05] [PASSED] drm_test_cmdline_force_D_only_dvi [19:03:05] [PASSED] drm_test_cmdline_force_D_only_hdmi [19:03:05] [PASSED] drm_test_cmdline_force_D_only_not_digital [19:03:05] [PASSED] drm_test_cmdline_force_e_only [19:03:05] [PASSED] drm_test_cmdline_res [19:03:05] [PASSED] drm_test_cmdline_res_vesa [19:03:05] [PASSED] drm_test_cmdline_res_vesa_rblank [19:03:05] [PASSED] drm_test_cmdline_res_rblank [19:03:05] [PASSED] drm_test_cmdline_res_bpp [19:03:05] [PASSED] drm_test_cmdline_res_refresh [19:03:05] [PASSED] drm_test_cmdline_res_bpp_refresh [19:03:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced [19:03:05] [PASSED] drm_test_cmdline_res_bpp_refresh_margins [19:03:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off [19:03:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on [19:03:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog [19:03:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital [19:03:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on [19:03:05] [PASSED] drm_test_cmdline_res_margins_force_on [19:03:05] [PASSED] drm_test_cmdline_res_vesa_margins [19:03:05] [PASSED] drm_test_cmdline_name [19:03:05] [PASSED] drm_test_cmdline_name_bpp [19:03:05] [PASSED] drm_test_cmdline_name_option [19:03:05] [PASSED] drm_test_cmdline_name_bpp_option [19:03:05] [PASSED] drm_test_cmdline_rotate_0 [19:03:05] [PASSED] drm_test_cmdline_rotate_90 [19:03:05] [PASSED] drm_test_cmdline_rotate_180 [19:03:05] [PASSED] drm_test_cmdline_rotate_270 [19:03:05] [PASSED] drm_test_cmdline_hmirror [19:03:05] [PASSED] drm_test_cmdline_vmirror [19:03:05] [PASSED] drm_test_cmdline_margin_options [19:03:05] [PASSED] drm_test_cmdline_multiple_options [19:03:05] [PASSED] drm_test_cmdline_bpp_extra_and_option [19:03:05] [PASSED] drm_test_cmdline_extra_and_option [19:03:05] [PASSED] drm_test_cmdline_freestanding_options [19:03:05] [PASSED] drm_test_cmdline_freestanding_force_e_and_options [19:03:05] [PASSED] drm_test_cmdline_panel_orientation [19:03:05] ================ drm_test_cmdline_invalid ================= [19:03:05] [PASSED] margin_only [19:03:05] [PASSED] interlace_only [19:03:05] [PASSED] res_missing_x [19:03:05] [PASSED] res_missing_y [19:03:05] [PASSED] res_bad_y [19:03:05] [PASSED] res_missing_y_bpp [19:03:05] [PASSED] res_bad_bpp [19:03:05] [PASSED] res_bad_refresh [19:03:05] [PASSED] res_bpp_refresh_force_on_off [19:03:05] [PASSED] res_invalid_mode [19:03:05] [PASSED] res_bpp_wrong_place_mode [19:03:05] [PASSED] name_bpp_refresh [19:03:05] [PASSED] name_refresh [19:03:05] [PASSED] name_refresh_wrong_mode [19:03:05] [PASSED] name_refresh_invalid_mode [19:03:05] [PASSED] rotate_multiple [19:03:05] [PASSED] rotate_invalid_val [19:03:05] [PASSED] rotate_truncated [19:03:05] [PASSED] invalid_option [19:03:05] [PASSED] invalid_tv_option [19:03:05] [PASSED] truncated_tv_option [19:03:05] ============ [PASSED] drm_test_cmdline_invalid ============= [19:03:05] =============== drm_test_cmdline_tv_options =============== [19:03:05] [PASSED] NTSC [19:03:05] [PASSED] NTSC_443 [19:03:05] [PASSED] NTSC_J [19:03:05] [PASSED] PAL [19:03:05] [PASSED] PAL_M [19:03:05] [PASSED] PAL_N [19:03:05] [PASSED] SECAM [19:03:05] [PASSED] MONO_525 [19:03:05] [PASSED] MONO_625 [19:03:05] =========== [PASSED] drm_test_cmdline_tv_options =========== [19:03:05] =============== [PASSED] drm_cmdline_parser ================ [19:03:05] ========== drmm_connector_hdmi_init (20 subtests) ========== [19:03:05] [PASSED] drm_test_connector_hdmi_init_valid [19:03:05] [PASSED] drm_test_connector_hdmi_init_bpc_8 [19:03:05] [PASSED] drm_test_connector_hdmi_init_bpc_10 [19:03:05] [PASSED] drm_test_connector_hdmi_init_bpc_12 [19:03:05] [PASSED] drm_test_connector_hdmi_init_bpc_invalid [19:03:05] [PASSED] drm_test_connector_hdmi_init_bpc_null [19:03:05] [PASSED] drm_test_connector_hdmi_init_formats_empty [19:03:05] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb [19:03:05] === drm_test_connector_hdmi_init_formats_yuv420_allowed === [19:03:05] [PASSED] supported_formats=0x9 yuv420_allowed=1 [19:03:05] [PASSED] supported_formats=0x9 yuv420_allowed=0 [19:03:05] [PASSED] supported_formats=0x3 yuv420_allowed=1 [19:03:05] [PASSED] supported_formats=0x3 yuv420_allowed=0 [19:03:05] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed === [19:03:05] [PASSED] drm_test_connector_hdmi_init_null_ddc [19:03:05] [PASSED] drm_test_connector_hdmi_init_null_product [19:03:05] [PASSED] drm_test_connector_hdmi_init_null_vendor [19:03:05] [PASSED] drm_test_connector_hdmi_init_product_length_exact [19:03:05] [PASSED] drm_test_connector_hdmi_init_product_length_too_long [19:03:05] [PASSED] drm_test_connector_hdmi_init_product_valid [19:03:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact [19:03:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long [19:03:05] [PASSED] drm_test_connector_hdmi_init_vendor_valid [19:03:05] ========= drm_test_connector_hdmi_init_type_valid ========= [19:03:05] [PASSED] HDMI-A [19:03:05] [PASSED] HDMI-B [19:03:05] ===== [PASSED] drm_test_connector_hdmi_init_type_valid ===== [19:03:05] ======== drm_test_connector_hdmi_init_type_invalid ======== [19:03:05] [PASSED] Unknown [19:03:05] [PASSED] VGA [19:03:05] [PASSED] DVI-I [19:03:05] [PASSED] DVI-D [19:03:05] [PASSED] DVI-A [19:03:05] [PASSED] Composite [19:03:05] [PASSED] SVIDEO [19:03:05] [PASSED] LVDS [19:03:05] [PASSED] Component [19:03:05] [PASSED] DIN [19:03:05] [PASSED] DP [19:03:05] [PASSED] TV [19:03:05] [PASSED] eDP [19:03:05] [PASSED] Virtual [19:03:05] [PASSED] DSI [19:03:05] [PASSED] DPI [19:03:05] [PASSED] Writeback [19:03:05] [PASSED] SPI [19:03:05] [PASSED] USB [19:03:05] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ==== [19:03:05] ============ [PASSED] drmm_connector_hdmi_init ============= [19:03:05] ============= drmm_connector_init (3 subtests) ============= [19:03:05] [PASSED] drm_test_drmm_connector_init [19:03:05] [PASSED] drm_test_drmm_connector_init_null_ddc [19:03:05] ========= drm_test_drmm_connector_init_type_valid ========= [19:03:05] [PASSED] Unknown [19:03:05] [PASSED] VGA [19:03:05] [PASSED] DVI-I [19:03:05] [PASSED] DVI-D [19:03:05] [PASSED] DVI-A [19:03:05] [PASSED] Composite [19:03:05] [PASSED] SVIDEO [19:03:05] [PASSED] LVDS [19:03:05] [PASSED] Component [19:03:05] [PASSED] DIN [19:03:05] [PASSED] DP [19:03:05] [PASSED] HDMI-A [19:03:05] [PASSED] HDMI-B [19:03:05] [PASSED] TV [19:03:05] [PASSED] eDP [19:03:05] [PASSED] Virtual [19:03:05] [PASSED] DSI [19:03:05] [PASSED] DPI [19:03:05] [PASSED] Writeback [19:03:05] [PASSED] SPI [19:03:05] [PASSED] USB [19:03:05] ===== [PASSED] drm_test_drmm_connector_init_type_valid ===== [19:03:05] =============== [PASSED] drmm_connector_init =============== [19:03:05] ========= drm_connector_dynamic_init (6 subtests) ========== [19:03:05] [PASSED] drm_test_drm_connector_dynamic_init [19:03:05] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc [19:03:05] [PASSED] drm_test_drm_connector_dynamic_init_not_added [19:03:05] [PASSED] drm_test_drm_connector_dynamic_init_properties [19:03:05] ===== drm_test_drm_connector_dynamic_init_type_valid ====== [19:03:05] [PASSED] Unknown [19:03:05] [PASSED] VGA [19:03:05] [PASSED] DVI-I [19:03:05] [PASSED] DVI-D [19:03:05] [PASSED] DVI-A [19:03:05] [PASSED] Composite [19:03:05] [PASSED] SVIDEO [19:03:05] [PASSED] LVDS [19:03:05] [PASSED] Component [19:03:05] [PASSED] DIN [19:03:05] [PASSED] DP [19:03:05] [PASSED] HDMI-A [19:03:05] [PASSED] HDMI-B [19:03:05] [PASSED] TV [19:03:05] [PASSED] eDP [19:03:05] [PASSED] Virtual [19:03:05] [PASSED] DSI [19:03:05] [PASSED] DPI [19:03:05] [PASSED] Writeback [19:03:05] [PASSED] SPI [19:03:05] [PASSED] USB [19:03:05] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid == [19:03:05] ======== drm_test_drm_connector_dynamic_init_name ========= [19:03:05] [PASSED] Unknown [19:03:05] [PASSED] VGA [19:03:05] [PASSED] DVI-I [19:03:05] [PASSED] DVI-D [19:03:05] [PASSED] DVI-A [19:03:05] [PASSED] Composite [19:03:05] [PASSED] SVIDEO [19:03:05] [PASSED] LVDS [19:03:05] [PASSED] Component [19:03:05] [PASSED] DIN [19:03:05] [PASSED] DP [19:03:05] [PASSED] HDMI-A [19:03:05] [PASSED] HDMI-B [19:03:05] [PASSED] TV [19:03:05] [PASSED] eDP [19:03:05] [PASSED] Virtual [19:03:05] [PASSED] DSI [19:03:05] [PASSED] DPI [19:03:05] [PASSED] Writeback [19:03:05] [PASSED] SPI [19:03:05] [PASSED] USB [19:03:05] ==== [PASSED] drm_test_drm_connector_dynamic_init_name ===== [19:03:05] =========== [PASSED] drm_connector_dynamic_init ============ [19:03:05] ==== drm_connector_dynamic_register_early (4 subtests) ===== [19:03:05] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list [19:03:05] [PASSED] drm_test_drm_connector_dynamic_register_early_defer [19:03:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init [19:03:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object [19:03:05] ====== [PASSED] drm_connector_dynamic_register_early ======= [19:03:05] ======= drm_connector_dynamic_register (7 subtests) ======== [19:03:05] [PASSED] drm_test_drm_connector_dynamic_register_on_list [19:03:05] [PASSED] drm_test_drm_connector_dynamic_register_no_defer [19:03:05] [PASSED] drm_test_drm_connector_dynamic_register_no_init [19:03:05] [PASSED] drm_test_drm_connector_dynamic_register_mode_object [19:03:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs [19:03:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name [19:03:05] [PASSED] drm_test_drm_connector_dynamic_register_debugfs [19:03:05] ========= [PASSED] drm_connector_dynamic_register ========== [19:03:05] = drm_connector_attach_broadcast_rgb_property (2 subtests) = [19:03:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property [19:03:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector [19:03:05] === [PASSED] drm_connector_attach_broadcast_rgb_property === [19:03:05] ========== drm_get_tv_mode_from_name (2 subtests) ========== [19:03:05] ========== drm_test_get_tv_mode_from_name_valid =========== [19:03:05] [PASSED] NTSC [19:03:05] [PASSED] NTSC-443 [19:03:05] [PASSED] NTSC-J [19:03:05] [PASSED] PAL [19:03:05] [PASSED] PAL-M [19:03:05] [PASSED] PAL-N [19:03:05] [PASSED] SECAM [19:03:05] [PASSED] Mono [19:03:05] ====== [PASSED] drm_test_get_tv_mode_from_name_valid ======= [19:03:05] [PASSED] drm_test_get_tv_mode_from_name_truncated [19:03:05] ============ [PASSED] drm_get_tv_mode_from_name ============ [19:03:05] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) = [19:03:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb [19:03:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc [19:03:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1 [19:03:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc [19:03:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1 [19:03:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double [19:03:05] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid = [19:03:05] [PASSED] VIC 96 [19:03:05] [PASSED] VIC 97 [19:03:05] [PASSED] VIC 101 [19:03:05] [PASSED] VIC 102 [19:03:05] [PASSED] VIC 106 [19:03:05] [PASSED] VIC 107 [19:03:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid === [19:03:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc [19:03:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc [19:03:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc [19:03:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc [19:03:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc [19:03:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ==== [19:03:05] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) == [19:03:05] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ==== [19:03:05] [PASSED] Automatic [19:03:05] [PASSED] Full [19:03:05] [PASSED] Limited 16:235 [19:03:05] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name === [19:03:05] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid [19:03:05] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ==== [19:03:05] == drm_hdmi_connector_get_output_format_name (2 subtests) == [19:03:05] === drm_test_drm_hdmi_connector_get_output_format_name ==== [19:03:05] [PASSED] RGB [19:03:05] [PASSED] YUV 4:2:0 [19:03:05] [PASSED] YUV 4:2:2 [19:03:05] [PASSED] YUV 4:4:4 [19:03:05] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name === [19:03:05] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid [19:03:05] ==== [PASSED] drm_hdmi_connector_get_output_format_name ==== [19:03:05] ============= drm_damage_helper (21 subtests) ============== [19:03:05] [PASSED] drm_test_damage_iter_no_damage [19:03:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src [19:03:05] [PASSED] drm_test_damage_iter_no_damage_src_moved [19:03:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved [19:03:05] [PASSED] drm_test_damage_iter_no_damage_not_visible [19:03:05] [PASSED] drm_test_damage_iter_no_damage_no_crtc [19:03:05] [PASSED] drm_test_damage_iter_no_damage_no_fb [19:03:05] [PASSED] drm_test_damage_iter_simple_damage [19:03:05] [PASSED] drm_test_damage_iter_single_damage [19:03:05] [PASSED] drm_test_damage_iter_single_damage_intersect_src [19:03:05] [PASSED] drm_test_damage_iter_single_damage_outside_src [19:03:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src [19:03:05] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src [19:03:05] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src [19:03:05] [PASSED] drm_test_damage_iter_single_damage_src_moved [19:03:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved [19:03:05] [PASSED] drm_test_damage_iter_damage [19:03:05] [PASSED] drm_test_damage_iter_damage_one_intersect [19:03:05] [PASSED] drm_test_damage_iter_damage_one_outside [19:03:05] [PASSED] drm_test_damage_iter_damage_src_moved [19:03:05] [PASSED] drm_test_damage_iter_damage_not_visible [19:03:05] ================ [PASSED] drm_damage_helper ================ [19:03:05] ============== drm_dp_mst_helper (3 subtests) ============== [19:03:05] ============== drm_test_dp_mst_calc_pbn_mode ============== [19:03:05] [PASSED] Clock 154000 BPP 30 DSC disabled [19:03:05] [PASSED] Clock 234000 BPP 30 DSC disabled [19:03:05] [PASSED] Clock 297000 BPP 24 DSC disabled [19:03:05] [PASSED] Clock 332880 BPP 24 DSC enabled [19:03:05] [PASSED] Clock 324540 BPP 24 DSC enabled [19:03:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ========== [19:03:05] ============== drm_test_dp_mst_calc_pbn_div =============== [19:03:05] [PASSED] Link rate 2000000 lane count 4 [19:03:05] [PASSED] Link rate 2000000 lane count 2 [19:03:05] [PASSED] Link rate 2000000 lane count 1 [19:03:05] [PASSED] Link rate 1350000 lane count 4 [19:03:05] [PASSED] Link rate 1350000 lane count 2 [19:03:05] [PASSED] Link rate 1350000 lane count 1 [19:03:05] [PASSED] Link rate 1000000 lane count 4 [19:03:05] [PASSED] Link rate 1000000 lane count 2 [19:03:05] [PASSED] Link rate 1000000 lane count 1 [19:03:05] [PASSED] Link rate 810000 lane count 4 [19:03:05] [PASSED] Link rate 810000 lane count 2 [19:03:05] [PASSED] Link rate 810000 lane count 1 [19:03:05] [PASSED] Link rate 540000 lane count 4 [19:03:05] [PASSED] Link rate 540000 lane count 2 [19:03:05] [PASSED] Link rate 540000 lane count 1 [19:03:05] [PASSED] Link rate 270000 lane count 4 [19:03:05] [PASSED] Link rate 270000 lane count 2 [19:03:05] [PASSED] Link rate 270000 lane count 1 [19:03:05] [PASSED] Link rate 162000 lane count 4 [19:03:05] [PASSED] Link rate 162000 lane count 2 [19:03:05] [PASSED] Link rate 162000 lane count 1 [19:03:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_div =========== [19:03:05] ========= drm_test_dp_mst_sideband_msg_req_decode ========= [19:03:05] [PASSED] DP_ENUM_PATH_RESOURCES with port number [19:03:05] [PASSED] DP_POWER_UP_PHY with port number [19:03:05] [PASSED] DP_POWER_DOWN_PHY with port number [19:03:05] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks [19:03:05] [PASSED] DP_ALLOCATE_PAYLOAD with port number [19:03:05] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI [19:03:05] [PASSED] DP_ALLOCATE_PAYLOAD with PBN [19:03:05] [PASSED] DP_QUERY_PAYLOAD with port number [19:03:05] [PASSED] DP_QUERY_PAYLOAD with VCPI [19:03:05] [PASSED] DP_REMOTE_DPCD_READ with port number [19:03:05] [PASSED] DP_REMOTE_DPCD_READ with DPCD address [19:03:05] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes [19:03:05] [PASSED] DP_REMOTE_DPCD_WRITE with port number [19:03:05] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address [19:03:05] [PASSED] DP_REMOTE_DPCD_WRITE with data array [19:03:05] [PASSED] DP_REMOTE_I2C_READ with port number [19:03:05] [PASSED] DP_REMOTE_I2C_READ with I2C device ID [19:03:05] [PASSED] DP_REMOTE_I2C_READ with transactions array [19:03:05] [PASSED] DP_REMOTE_I2C_WRITE with port number [19:03:05] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID [19:03:05] [PASSED] DP_REMOTE_I2C_WRITE with data array [19:03:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID [19:03:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID [19:03:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event [19:03:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event [19:03:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior [19:03:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior [19:03:05] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode ===== [19:03:05] ================ [PASSED] drm_dp_mst_helper ================ [19:03:05] ================== drm_exec (7 subtests) =================== [19:03:05] [PASSED] sanitycheck [19:03:05] [PASSED] test_lock [19:03:05] [PASSED] test_lock_unlock [19:03:05] [PASSED] test_duplicates [19:03:05] [PASSED] test_prepare [19:03:05] [PASSED] test_prepare_array [19:03:05] [PASSED] test_multiple_loops [19:03:05] ==================== [PASSED] drm_exec ===================== [19:03:05] =========== drm_format_helper_test (17 subtests) =========== [19:03:05] ============== drm_test_fb_xrgb8888_to_gray8 ============== [19:03:05] [PASSED] single_pixel_source_buffer [19:03:05] [PASSED] single_pixel_clip_rectangle [19:03:05] [PASSED] well_known_colors [19:03:05] [PASSED] destination_pitch [19:03:05] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ========== [19:03:05] ============= drm_test_fb_xrgb8888_to_rgb332 ============== [19:03:05] [PASSED] single_pixel_source_buffer [19:03:05] [PASSED] single_pixel_clip_rectangle [19:03:05] [PASSED] well_known_colors [19:03:05] [PASSED] destination_pitch [19:03:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ========== [19:03:05] ============= drm_test_fb_xrgb8888_to_rgb565 ============== [19:03:05] [PASSED] single_pixel_source_buffer [19:03:05] [PASSED] single_pixel_clip_rectangle [19:03:05] [PASSED] well_known_colors [19:03:05] [PASSED] destination_pitch [19:03:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ========== [19:03:05] ============ drm_test_fb_xrgb8888_to_xrgb1555 ============= [19:03:05] [PASSED] single_pixel_source_buffer [19:03:05] [PASSED] single_pixel_clip_rectangle [19:03:05] [PASSED] well_known_colors [19:03:05] [PASSED] destination_pitch [19:03:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 ========= [19:03:05] ============ drm_test_fb_xrgb8888_to_argb1555 ============= [19:03:05] [PASSED] single_pixel_source_buffer [19:03:05] [PASSED] single_pixel_clip_rectangle [19:03:05] [PASSED] well_known_colors [19:03:05] [PASSED] destination_pitch [19:03:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 ========= [19:03:05] ============ drm_test_fb_xrgb8888_to_rgba5551 ============= [19:03:05] [PASSED] single_pixel_source_buffer [19:03:05] [PASSED] single_pixel_clip_rectangle [19:03:05] [PASSED] well_known_colors [19:03:05] [PASSED] destination_pitch [19:03:05] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 ========= [19:03:05] ============= drm_test_fb_xrgb8888_to_rgb888 ============== [19:03:05] [PASSED] single_pixel_source_buffer [19:03:05] [PASSED] single_pixel_clip_rectangle [19:03:05] [PASSED] well_known_colors [19:03:05] [PASSED] destination_pitch [19:03:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ========== [19:03:05] ============= drm_test_fb_xrgb8888_to_bgr888 ============== [19:03:05] [PASSED] single_pixel_source_buffer [19:03:05] [PASSED] single_pixel_clip_rectangle [19:03:05] [PASSED] well_known_colors [19:03:05] [PASSED] destination_pitch [19:03:05] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ========== [19:03:05] ============ drm_test_fb_xrgb8888_to_argb8888 ============= [19:03:05] [PASSED] single_pixel_source_buffer [19:03:05] [PASSED] single_pixel_clip_rectangle [19:03:05] [PASSED] well_known_colors [19:03:05] [PASSED] destination_pitch [19:03:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 ========= [19:03:05] =========== drm_test_fb_xrgb8888_to_xrgb2101010 =========== [19:03:05] [PASSED] single_pixel_source_buffer [19:03:05] [PASSED] single_pixel_clip_rectangle [19:03:05] [PASSED] well_known_colors [19:03:05] [PASSED] destination_pitch [19:03:05] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 ======= [19:03:05] =========== drm_test_fb_xrgb8888_to_argb2101010 =========== [19:03:05] [PASSED] single_pixel_source_buffer [19:03:05] [PASSED] single_pixel_clip_rectangle [19:03:05] [PASSED] well_known_colors [19:03:05] [PASSED] destination_pitch [19:03:05] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 ======= [19:03:05] ============== drm_test_fb_xrgb8888_to_mono =============== [19:03:05] [PASSED] single_pixel_source_buffer [19:03:05] [PASSED] single_pixel_clip_rectangle [19:03:05] [PASSED] well_known_colors [19:03:05] [PASSED] destination_pitch [19:03:05] ========== [PASSED] drm_test_fb_xrgb8888_to_mono =========== [19:03:05] ==================== drm_test_fb_swab ===================== [19:03:05] [PASSED] single_pixel_source_buffer [19:03:05] [PASSED] single_pixel_clip_rectangle [19:03:05] [PASSED] well_known_colors [19:03:05] [PASSED] destination_pitch [19:03:05] ================ [PASSED] drm_test_fb_swab ================= [19:03:05] ============ drm_test_fb_xrgb8888_to_xbgr8888 ============= [19:03:05] [PASSED] single_pixel_source_buffer [19:03:05] [PASSED] single_pixel_clip_rectangle [19:03:05] [PASSED] well_known_colors [19:03:05] [PASSED] destination_pitch [19:03:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 ========= [19:03:05] ============ drm_test_fb_xrgb8888_to_abgr8888 ============= [19:03:05] [PASSED] single_pixel_source_buffer [19:03:05] [PASSED] single_pixel_clip_rectangle [19:03:05] [PASSED] well_known_colors [19:03:05] [PASSED] destination_pitch [19:03:05] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 ========= [19:03:05] ================= drm_test_fb_clip_offset ================= [19:03:05] [PASSED] pass through [19:03:05] [PASSED] horizontal offset [19:03:05] [PASSED] vertical offset [19:03:05] [PASSED] horizontal and vertical offset [19:03:05] [PASSED] horizontal offset (custom pitch) [19:03:05] [PASSED] vertical offset (custom pitch) [19:03:05] [PASSED] horizontal and vertical offset (custom pitch) [19:03:05] ============= [PASSED] drm_test_fb_clip_offset ============= [19:03:05] =================== drm_test_fb_memcpy ==================== [19:03:05] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258) [19:03:05] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258) [19:03:05] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559) [19:03:05] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258) [19:03:05] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258) [19:03:05] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559) [19:03:05] [PASSED] well_known_colors: XB24 little-endian (0x34324258) [19:03:05] [PASSED] well_known_colors: XRA8 little-endian (0x38415258) [19:03:05] [PASSED] well_known_colors: YU24 little-endian (0x34325559) [19:03:05] [PASSED] destination_pitch: XB24 little-endian (0x34324258) [19:03:05] [PASSED] destination_pitch: XRA8 little-endian (0x38415258) [19:03:05] [PASSED] destination_pitch: YU24 little-endian (0x34325559) [19:03:05] =============== [PASSED] drm_test_fb_memcpy ================ [19:03:05] ============= [PASSED] drm_format_helper_test ============== [19:03:05] ================= drm_format (18 subtests) ================= [19:03:05] [PASSED] drm_test_format_block_width_invalid [19:03:05] [PASSED] drm_test_format_block_width_one_plane [19:03:05] [PASSED] drm_test_format_block_width_two_plane [19:03:05] [PASSED] drm_test_format_block_width_three_plane [19:03:05] [PASSED] drm_test_format_block_width_tiled [19:03:05] [PASSED] drm_test_format_block_height_invalid [19:03:05] [PASSED] drm_test_format_block_height_one_plane [19:03:05] [PASSED] drm_test_format_block_height_two_plane [19:03:05] [PASSED] drm_test_format_block_height_three_plane [19:03:05] [PASSED] drm_test_format_block_height_tiled [19:03:05] [PASSED] drm_test_format_min_pitch_invalid [19:03:05] [PASSED] drm_test_format_min_pitch_one_plane_8bpp [19:03:05] [PASSED] drm_test_format_min_pitch_one_plane_16bpp [19:03:05] [PASSED] drm_test_format_min_pitch_one_plane_24bpp [19:03:05] [PASSED] drm_test_format_min_pitch_one_plane_32bpp [19:03:05] [PASSED] drm_test_format_min_pitch_two_plane [19:03:05] [PASSED] drm_test_format_min_pitch_three_plane_8bpp [19:03:05] [PASSED] drm_test_format_min_pitch_tiled [19:03:05] =================== [PASSED] drm_format ==================== [19:03:05] ============== drm_framebuffer (10 subtests) =============== [19:03:05] ========== drm_test_framebuffer_check_src_coords ========== [19:03:05] [PASSED] Success: source fits into fb [19:03:05] [PASSED] Fail: overflowing fb with x-axis coordinate [19:03:05] [PASSED] Fail: overflowing fb with y-axis coordinate [19:03:05] [PASSED] Fail: overflowing fb with source width [19:03:05] [PASSED] Fail: overflowing fb with source height [19:03:05] ====== [PASSED] drm_test_framebuffer_check_src_coords ====== [19:03:05] [PASSED] drm_test_framebuffer_cleanup [19:03:05] =============== drm_test_framebuffer_create =============== [19:03:05] [PASSED] ABGR8888 normal sizes [19:03:05] [PASSED] ABGR8888 max sizes [19:03:05] [PASSED] ABGR8888 pitch greater than min required [19:03:05] [PASSED] ABGR8888 pitch less than min required [19:03:05] [PASSED] ABGR8888 Invalid width [19:03:05] [PASSED] ABGR8888 Invalid buffer handle [19:03:05] [PASSED] No pixel format [19:03:05] [PASSED] ABGR8888 Width 0 [19:03:05] [PASSED] ABGR8888 Height 0 [19:03:05] [PASSED] ABGR8888 Out of bound height * pitch combination [19:03:05] [PASSED] ABGR8888 Large buffer offset [19:03:05] [PASSED] ABGR8888 Buffer offset for inexistent plane [19:03:05] [PASSED] ABGR8888 Invalid flag [19:03:05] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers [19:03:05] [PASSED] ABGR8888 Valid buffer modifier [19:03:05] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE) [19:03:05] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS [19:03:05] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS [19:03:05] [PASSED] NV12 Normal sizes [19:03:05] [PASSED] NV12 Max sizes [19:03:05] [PASSED] NV12 Invalid pitch [19:03:05] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag [19:03:05] [PASSED] NV12 different modifier per-plane [19:03:05] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE [19:03:05] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS [19:03:05] [PASSED] NV12 Modifier for inexistent plane [19:03:05] [PASSED] NV12 Handle for inexistent plane [19:03:05] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS [19:03:05] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier [19:03:05] [PASSED] YVU420 Normal sizes [19:03:05] [PASSED] YVU420 Max sizes [19:03:05] [PASSED] YVU420 Invalid pitch [19:03:05] [PASSED] YVU420 Different pitches [19:03:05] [PASSED] YVU420 Different buffer offsets/pitches [19:03:05] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS [19:03:05] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS [19:03:05] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS [19:03:05] [PASSED] YVU420 Valid modifier [19:03:05] [PASSED] YVU420 Different modifiers per plane [19:03:05] [PASSED] YVU420 Modifier for inexistent plane [19:03:05] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR) [19:03:05] [PASSED] X0L2 Normal sizes [19:03:05] [PASSED] X0L2 Max sizes [19:03:05] [PASSED] X0L2 Invalid pitch [19:03:05] [PASSED] X0L2 Pitch greater than minimum required [19:03:05] [PASSED] X0L2 Handle for inexistent plane [19:03:05] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set [19:03:05] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set [19:03:05] [PASSED] X0L2 Valid modifier [19:03:05] [PASSED] X0L2 Modifier for inexistent plane [19:03:05] =========== [PASSED] drm_test_framebuffer_create =========== [19:03:05] [PASSED] drm_test_framebuffer_free [19:03:05] [PASSED] drm_test_framebuffer_init [19:03:05] [PASSED] drm_test_framebuffer_init_bad_format [19:03:05] [PASSED] drm_test_framebuffer_init_dev_mismatch [19:03:05] [PASSED] drm_test_framebuffer_lookup [19:03:05] [PASSED] drm_test_framebuffer_lookup_inexistent [19:03:05] [PASSED] drm_test_framebuffer_modifiers_not_supported [19:03:05] ================= [PASSED] drm_framebuffer ================= [19:03:05] ================ drm_gem_shmem (8 subtests) ================ [19:03:05] [PASSED] drm_gem_shmem_test_obj_create [19:03:05] [PASSED] drm_gem_shmem_test_obj_create_private [19:03:05] [PASSED] drm_gem_shmem_test_pin_pages [19:03:05] [PASSED] drm_gem_shmem_test_vmap [19:03:05] [PASSED] drm_gem_shmem_test_get_sg_table [19:03:05] [PASSED] drm_gem_shmem_test_get_pages_sgt [19:03:05] [PASSED] drm_gem_shmem_test_madvise [19:03:05] [PASSED] drm_gem_shmem_test_purge [19:03:05] ================== [PASSED] drm_gem_shmem ================== [19:03:05] === drm_atomic_helper_connector_hdmi_check (27 subtests) === [19:03:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode [19:03:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1 [19:03:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode [19:03:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1 [19:03:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode [19:03:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1 [19:03:05] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 ======= [19:03:05] [PASSED] Automatic [19:03:05] [PASSED] Full [19:03:05] [PASSED] Limited 16:235 [19:03:05] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 === [19:03:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed [19:03:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed [19:03:05] [PASSED] drm_test_check_disable_connector [19:03:05] [PASSED] drm_test_check_hdmi_funcs_reject_rate [19:03:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb [19:03:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420 [19:03:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422 [19:03:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420 [19:03:05] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420 [19:03:05] [PASSED] drm_test_check_output_bpc_crtc_mode_changed [19:03:05] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed [19:03:05] [PASSED] drm_test_check_output_bpc_dvi [19:03:05] [PASSED] drm_test_check_output_bpc_format_vic_1 [19:03:05] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only [19:03:05] [PASSED] drm_test_check_output_bpc_format_display_rgb_only [19:03:05] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only [19:03:05] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only [19:03:05] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc [19:03:05] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc [19:03:05] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc [19:03:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ====== [19:03:05] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ==== [19:03:05] [PASSED] drm_test_check_broadcast_rgb_value [19:03:05] [PASSED] drm_test_check_bpc_8_value [19:03:05] [PASSED] drm_test_check_bpc_10_value [19:03:05] [PASSED] drm_test_check_bpc_12_value [19:03:05] [PASSED] drm_test_check_format_value [19:03:05] [PASSED] drm_test_check_tmds_char_value [19:03:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ====== [19:03:05] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) = [19:03:05] [PASSED] drm_test_check_mode_valid [19:03:05] [PASSED] drm_test_check_mode_valid_reject [19:03:05] [PASSED] drm_test_check_mode_valid_reject_rate [19:03:05] [PASSED] drm_test_check_mode_valid_reject_max_clock [19:03:05] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid === [19:03:05] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) = [19:03:05] [PASSED] drm_test_check_infoframes [19:03:05] [PASSED] drm_test_check_reject_avi_infoframe [19:03:05] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8 [19:03:05] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10 [19:03:05] [PASSED] drm_test_check_reject_audio_infoframe [19:03:05] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes === [19:03:05] ================= drm_managed (2 subtests) ================= [19:03:05] [PASSED] drm_test_managed_release_action [19:03:05] [PASSED] drm_test_managed_run_action [19:03:05] =================== [PASSED] drm_managed =================== [19:03:05] =================== drm_mm (6 subtests) ==================== [19:03:05] [PASSED] drm_test_mm_init [19:03:05] [PASSED] drm_test_mm_debug [19:03:05] [PASSED] drm_test_mm_align32 [19:03:05] [PASSED] drm_test_mm_align64 [19:03:05] [PASSED] drm_test_mm_lowest [19:03:05] [PASSED] drm_test_mm_highest [19:03:05] ===================== [PASSED] drm_mm ====================== [19:03:05] ============= drm_modes_analog_tv (5 subtests) ============= [19:03:05] [PASSED] drm_test_modes_analog_tv_mono_576i [19:03:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i [19:03:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined [19:03:05] [PASSED] drm_test_modes_analog_tv_pal_576i [19:03:05] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined [19:03:05] =============== [PASSED] drm_modes_analog_tv =============== [19:03:05] ============== drm_plane_helper (2 subtests) =============== [19:03:05] =============== drm_test_check_plane_state ================ [19:03:05] [PASSED] clipping_simple [19:03:05] [PASSED] clipping_rotate_reflect [19:03:05] [PASSED] positioning_simple [19:03:05] [PASSED] upscaling [19:03:05] [PASSED] downscaling [19:03:05] [PASSED] rounding1 [19:03:05] [PASSED] rounding2 [19:03:05] [PASSED] rounding3 [19:03:05] [PASSED] rounding4 [19:03:05] =========== [PASSED] drm_test_check_plane_state ============ [19:03:05] =========== drm_test_check_invalid_plane_state ============ [19:03:05] [PASSED] positioning_invalid [19:03:05] [PASSED] upscaling_invalid [19:03:05] [PASSED] downscaling_invalid [19:03:05] ======= [PASSED] drm_test_check_invalid_plane_state ======== [19:03:05] ================ [PASSED] drm_plane_helper ================= [19:03:05] ====== drm_connector_helper_tv_get_modes (1 subtest) ======= [19:03:05] ====== drm_test_connector_helper_tv_get_modes_check ======= [19:03:05] [PASSED] None [19:03:05] [PASSED] PAL [19:03:05] [PASSED] NTSC [19:03:05] [PASSED] Both, NTSC Default [19:03:05] [PASSED] Both, PAL Default [19:03:05] [PASSED] Both, NTSC Default, with PAL on command-line [19:03:05] [PASSED] Both, PAL Default, with NTSC on command-line [19:03:05] == [PASSED] drm_test_connector_helper_tv_get_modes_check === [19:03:05] ======== [PASSED] drm_connector_helper_tv_get_modes ======== [19:03:05] ================== drm_rect (9 subtests) =================== [19:03:05] [PASSED] drm_test_rect_clip_scaled_div_by_zero [19:03:05] [PASSED] drm_test_rect_clip_scaled_not_clipped [19:03:05] [PASSED] drm_test_rect_clip_scaled_clipped [19:03:05] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned [19:03:05] ================= drm_test_rect_intersect ================= [19:03:05] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0 [19:03:05] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1 [19:03:05] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0 [19:03:05] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1 [19:03:05] [PASSED] right x left: 2x1+0+0 x 3x1+1+0 [19:03:05] [PASSED] left x right: 3x1+1+0 x 2x1+0+0 [19:03:05] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1 [19:03:05] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0 [19:03:05] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1 [19:03:05] [PASSED] touching side: 1x1+0+0 x 1x1+1+0 [19:03:05] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0 [19:03:05] [PASSED] inside another: 2x2+0+0 x 1x1+1+1 [19:03:05] [PASSED] far away: 1x1+0+0 x 1x1+3+6 [19:03:05] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10 [19:03:05] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10 [19:03:05] ============= [PASSED] drm_test_rect_intersect ============= [19:03:05] ================ drm_test_rect_calc_hscale ================ [19:03:05] [PASSED] normal use [19:03:05] [PASSED] out of max range [19:03:05] [PASSED] out of min range [19:03:05] [PASSED] zero dst [19:03:05] [PASSED] negative src [19:03:05] [PASSED] negative dst [19:03:05] ============ [PASSED] drm_test_rect_calc_hscale ============ [19:03:05] ================ drm_test_rect_calc_vscale ================ [19:03:05] [PASSED] normal use [19:03:05] [PASSED] out of max range [19:03:05] [PASSED] out of min range [19:03:05] [PASSED] zero dst [19:03:05] [PASSED] negative src [19:03:05] [PASSED] negative dst stty: 'standard input': Inappropriate ioctl for device [19:03:05] ============ [PASSED] drm_test_rect_calc_vscale ============ [19:03:05] ================== drm_test_rect_rotate =================== [19:03:05] [PASSED] reflect-x [19:03:05] [PASSED] reflect-y [19:03:05] [PASSED] rotate-0 [19:03:05] [PASSED] rotate-90 [19:03:05] [PASSED] rotate-180 [19:03:05] [PASSED] rotate-270 [19:03:05] ============== [PASSED] drm_test_rect_rotate =============== [19:03:05] ================ drm_test_rect_rotate_inv ================= [19:03:05] [PASSED] reflect-x [19:03:05] [PASSED] reflect-y [19:03:05] [PASSED] rotate-0 [19:03:05] [PASSED] rotate-90 [19:03:05] [PASSED] rotate-180 [19:03:05] [PASSED] rotate-270 [19:03:05] ============ [PASSED] drm_test_rect_rotate_inv ============= [19:03:05] ==================== [PASSED] drm_rect ===================== [19:03:05] ============ drm_sysfb_modeset_test (1 subtest) ============ [19:03:05] ============ drm_test_sysfb_build_fourcc_list ============= [19:03:05] [PASSED] no native formats [19:03:05] [PASSED] XRGB8888 as native format [19:03:05] [PASSED] remove duplicates [19:03:05] [PASSED] convert alpha formats [19:03:05] [PASSED] random formats [19:03:05] ======== [PASSED] drm_test_sysfb_build_fourcc_list ========= [19:03:05] ============= [PASSED] drm_sysfb_modeset_test ============== [19:03:05] ================== drm_fixp (2 subtests) =================== [19:03:05] [PASSED] drm_test_int2fixp [19:03:05] [PASSED] drm_test_sm2fixp [19:03:05] ==================== [PASSED] drm_fixp ===================== [19:03:05] ============================================================ [19:03:05] Testing complete. Ran 621 tests: passed: 621 [19:03:05] Elapsed time: 25.969s total, 1.685s configuring, 24.118s building, 0.123s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig [19:03:05] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [19:03:06] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48 [19:03:16] Starting KUnit Kernel (1/1)... [19:03:16] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [19:03:16] ================= ttm_device (5 subtests) ================== [19:03:16] [PASSED] ttm_device_init_basic [19:03:16] [PASSED] ttm_device_init_multiple [19:03:16] [PASSED] ttm_device_fini_basic [19:03:16] [PASSED] ttm_device_init_no_vma_man [19:03:16] ================== ttm_device_init_pools ================== [19:03:16] [PASSED] No DMA allocations, no DMA32 required [19:03:16] [PASSED] DMA allocations, DMA32 required [19:03:16] [PASSED] No DMA allocations, DMA32 required [19:03:16] [PASSED] DMA allocations, no DMA32 required [19:03:16] ============== [PASSED] ttm_device_init_pools ============== [19:03:16] =================== [PASSED] ttm_device ==================== [19:03:16] ================== ttm_pool (8 subtests) =================== [19:03:16] ================== ttm_pool_alloc_basic =================== [19:03:16] [PASSED] One page [19:03:16] [PASSED] More than one page [19:03:16] [PASSED] Above the allocation limit [19:03:16] [PASSED] One page, with coherent DMA mappings enabled [19:03:16] [PASSED] Above the allocation limit, with coherent DMA mappings enabled [19:03:16] ============== [PASSED] ttm_pool_alloc_basic =============== [19:03:16] ============== ttm_pool_alloc_basic_dma_addr ============== [19:03:16] [PASSED] One page [19:03:16] [PASSED] More than one page [19:03:16] [PASSED] Above the allocation limit [19:03:16] [PASSED] One page, with coherent DMA mappings enabled [19:03:16] [PASSED] Above the allocation limit, with coherent DMA mappings enabled [19:03:16] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ========== [19:03:16] [PASSED] ttm_pool_alloc_order_caching_match [19:03:16] [PASSED] ttm_pool_alloc_caching_mismatch [19:03:16] [PASSED] ttm_pool_alloc_order_mismatch [19:03:16] [PASSED] ttm_pool_free_dma_alloc [19:03:16] [PASSED] ttm_pool_free_no_dma_alloc [19:03:16] [PASSED] ttm_pool_fini_basic [19:03:16] ==================== [PASSED] ttm_pool ===================== [19:03:16] ================ ttm_resource (8 subtests) ================= [19:03:16] ================= ttm_resource_init_basic ================= [19:03:16] [PASSED] Init resource in TTM_PL_SYSTEM [19:03:16] [PASSED] Init resource in TTM_PL_VRAM [19:03:16] [PASSED] Init resource in a private placement [19:03:16] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags [19:03:16] ============= [PASSED] ttm_resource_init_basic ============= [19:03:16] [PASSED] ttm_resource_init_pinned [19:03:16] [PASSED] ttm_resource_fini_basic [19:03:16] [PASSED] ttm_resource_manager_init_basic [19:03:16] [PASSED] ttm_resource_manager_usage_basic [19:03:16] [PASSED] ttm_resource_manager_set_used_basic [19:03:16] [PASSED] ttm_sys_man_alloc_basic [19:03:16] [PASSED] ttm_sys_man_free_basic [19:03:16] ================== [PASSED] ttm_resource =================== [19:03:16] =================== ttm_tt (15 subtests) =================== [19:03:16] ==================== ttm_tt_init_basic ==================== [19:03:16] [PASSED] Page-aligned size [19:03:16] [PASSED] Extra pages requested [19:03:16] ================ [PASSED] ttm_tt_init_basic ================ [19:03:16] [PASSED] ttm_tt_init_misaligned [19:03:16] [PASSED] ttm_tt_fini_basic [19:03:16] [PASSED] ttm_tt_fini_sg [19:03:16] [PASSED] ttm_tt_fini_shmem [19:03:16] [PASSED] ttm_tt_create_basic [19:03:16] [PASSED] ttm_tt_create_invalid_bo_type [19:03:16] [PASSED] ttm_tt_create_ttm_exists [19:03:16] [PASSED] ttm_tt_create_failed [19:03:16] [PASSED] ttm_tt_destroy_basic [19:03:16] [PASSED] ttm_tt_populate_null_ttm [19:03:16] [PASSED] ttm_tt_populate_populated_ttm [19:03:16] [PASSED] ttm_tt_unpopulate_basic [19:03:16] [PASSED] ttm_tt_unpopulate_empty_ttm [19:03:16] [PASSED] ttm_tt_swapin_basic [19:03:16] ===================== [PASSED] ttm_tt ====================== [19:03:16] =================== ttm_bo (14 subtests) =================== [19:03:16] =========== ttm_bo_reserve_optimistic_no_ticket =========== [19:03:16] [PASSED] Cannot be interrupted and sleeps [19:03:16] [PASSED] Cannot be interrupted, locks straight away [19:03:16] [PASSED] Can be interrupted, sleeps [19:03:16] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket ======= [19:03:16] [PASSED] ttm_bo_reserve_locked_no_sleep [19:03:16] [PASSED] ttm_bo_reserve_no_wait_ticket [19:03:16] [PASSED] ttm_bo_reserve_double_resv [19:03:16] [PASSED] ttm_bo_reserve_interrupted [19:03:16] [PASSED] ttm_bo_reserve_deadlock [19:03:16] [PASSED] ttm_bo_unreserve_basic [19:03:16] [PASSED] ttm_bo_unreserve_pinned [19:03:16] [PASSED] ttm_bo_unreserve_bulk [19:03:16] [PASSED] ttm_bo_fini_basic [19:03:16] [PASSED] ttm_bo_fini_shared_resv [19:03:16] [PASSED] ttm_bo_pin_basic [19:03:16] [PASSED] ttm_bo_pin_unpin_resource [19:03:16] [PASSED] ttm_bo_multiple_pin_one_unpin [19:03:16] ===================== [PASSED] ttm_bo ====================== [19:03:16] ============== ttm_bo_validate (21 subtests) =============== [19:03:16] ============== ttm_bo_init_reserved_sys_man =============== [19:03:16] [PASSED] Buffer object for userspace [19:03:16] [PASSED] Kernel buffer object [19:03:16] [PASSED] Shared buffer object [19:03:16] ========== [PASSED] ttm_bo_init_reserved_sys_man =========== [19:03:16] ============== ttm_bo_init_reserved_mock_man ============== [19:03:16] [PASSED] Buffer object for userspace [19:03:16] [PASSED] Kernel buffer object [19:03:16] [PASSED] Shared buffer object [19:03:16] ========== [PASSED] ttm_bo_init_reserved_mock_man ========== [19:03:16] [PASSED] ttm_bo_init_reserved_resv [19:03:16] ================== ttm_bo_validate_basic ================== [19:03:16] [PASSED] Buffer object for userspace [19:03:16] [PASSED] Kernel buffer object [19:03:16] [PASSED] Shared buffer object [19:03:16] ============== [PASSED] ttm_bo_validate_basic ============== [19:03:16] [PASSED] ttm_bo_validate_invalid_placement [19:03:16] ============= ttm_bo_validate_same_placement ============== [19:03:16] [PASSED] System manager [19:03:16] [PASSED] VRAM manager [19:03:16] ========= [PASSED] ttm_bo_validate_same_placement ========== [19:03:16] [PASSED] ttm_bo_validate_failed_alloc [19:03:16] [PASSED] ttm_bo_validate_pinned [19:03:16] [PASSED] ttm_bo_validate_busy_placement [19:03:16] ================ ttm_bo_validate_multihop ================= [19:03:16] [PASSED] Buffer object for userspace [19:03:16] [PASSED] Kernel buffer object [19:03:16] [PASSED] Shared buffer object [19:03:16] ============ [PASSED] ttm_bo_validate_multihop ============= [19:03:16] ========== ttm_bo_validate_no_placement_signaled ========== [19:03:16] [PASSED] Buffer object in system domain, no page vector [19:03:16] [PASSED] Buffer object in system domain with an existing page vector [19:03:16] ====== [PASSED] ttm_bo_validate_no_placement_signaled ====== [19:03:16] ======== ttm_bo_validate_no_placement_not_signaled ======== [19:03:16] [PASSED] Buffer object for userspace [19:03:16] [PASSED] Kernel buffer object [19:03:16] [PASSED] Shared buffer object [19:03:16] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ==== [19:03:16] [PASSED] ttm_bo_validate_move_fence_signaled [19:03:16] ========= ttm_bo_validate_move_fence_not_signaled ========= [19:03:16] [PASSED] Waits for GPU [19:03:16] [PASSED] Tries to lock straight away [19:03:16] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled ===== [19:03:16] [PASSED] ttm_bo_validate_happy_evict [19:03:16] [PASSED] ttm_bo_validate_all_pinned_evict [19:03:16] [PASSED] ttm_bo_validate_allowed_only_evict [19:03:16] [PASSED] ttm_bo_validate_deleted_evict [19:03:16] [PASSED] ttm_bo_validate_busy_domain_evict [19:03:16] [PASSED] ttm_bo_validate_evict_gutting [19:03:16] [PASSED] ttm_bo_validate_recrusive_evict stty: 'standard input': Inappropriate ioctl for device [19:03:16] ================= [PASSED] ttm_bo_validate ================= [19:03:16] ============================================================ [19:03:16] Testing complete. Ran 101 tests: passed: 101 [19:03:16] Elapsed time: 11.292s total, 1.645s configuring, 9.431s building, 0.185s running + cleanup ++ stat -c %u:%g /kernel + chown -R 1003:1003 /kernel ^ permalink raw reply [flat|nested] 23+ messages in thread
* ✗ Xe.CI.BAT: failure for drm/{i915,xe}: refactor register helpers 2026-02-25 17:57 [PATCH 0/8] drm/{i915,xe}: refactor register helpers Jani Nikula ` (9 preceding siblings ...) 2026-02-25 19:03 ` ✓ CI.KUnit: success " Patchwork @ 2026-02-25 19:39 ` Patchwork 2026-02-25 22:15 ` ✗ Xe.CI.FULL: " Patchwork 2026-03-03 15:12 ` [PATCH 0/8] " Rodrigo Vivi 12 siblings, 0 replies; 23+ messages in thread From: Patchwork @ 2026-02-25 19:39 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-xe [-- Attachment #1: Type: text/plain, Size: 2289 bytes --] == Series Details == Series: drm/{i915,xe}: refactor register helpers URL : https://patchwork.freedesktop.org/series/162163/ State : failure == Summary == CI Bug Log - changes from xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86_BAT -> xe-pw-162163v1_BAT ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with xe-pw-162163v1_BAT absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in xe-pw-162163v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (14 -> 14) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in xe-pw-162163v1_BAT: ### IGT changes ### #### Possible regressions #### * igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1: - bat-adlp-7: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html Known issues ------------ Here are the changes found in xe-pw-162163v1_BAT that come from known issues: ### IGT changes ### #### Possible fixes #### * igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1: - bat-adlp-7: [DMESG-WARN][3] -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html Build changes ------------- * Linux: xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86 -> xe-pw-162163v1 IGT_8771: 8771 xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86: 3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86 xe-pw-162163v1: 162163v1 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/index.html [-- Attachment #2: Type: text/html, Size: 2902 bytes --] ^ permalink raw reply [flat|nested] 23+ messages in thread
* ✗ Xe.CI.FULL: failure for drm/{i915,xe}: refactor register helpers 2026-02-25 17:57 [PATCH 0/8] drm/{i915,xe}: refactor register helpers Jani Nikula ` (10 preceding siblings ...) 2026-02-25 19:39 ` ✗ Xe.CI.BAT: failure " Patchwork @ 2026-02-25 22:15 ` Patchwork 2026-03-03 15:12 ` [PATCH 0/8] " Rodrigo Vivi 12 siblings, 0 replies; 23+ messages in thread From: Patchwork @ 2026-02-25 22:15 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-xe [-- Attachment #1: Type: text/plain, Size: 13382 bytes --] == Series Details == Series: drm/{i915,xe}: refactor register helpers URL : https://patchwork.freedesktop.org/series/162163/ State : failure == Summary == CI Bug Log - changes from xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86_FULL -> xe-pw-162163v1_FULL ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with xe-pw-162163v1_FULL absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in xe-pw-162163v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (2 -> 2) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in xe-pw-162163v1_FULL: ### IGT changes ### #### Possible regressions #### * igt@kms_plane@pixel-format-linear-modifier@pipe-b-plane-0: - shard-lnl: [PASS][1] -> [FAIL][2] +1 other test fail [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86/shard-lnl-2/igt@kms_plane@pixel-format-linear-modifier@pipe-b-plane-0.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-lnl-3/igt@kms_plane@pixel-format-linear-modifier@pipe-b-plane-0.html Known issues ------------ Here are the changes found in xe-pw-162163v1_FULL that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_big_fb@4-tiled-32bpp-rotate-90: - shard-bmg: NOTRUN -> [SKIP][3] ([Intel XE#2327]) [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-1/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-bmg: NOTRUN -> [SKIP][4] ([Intel XE#1124]) [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_bw@linear-tiling-1-displays-2160x1440p: - shard-bmg: [PASS][5] -> [SKIP][6] ([Intel XE#367]) [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86/shard-bmg-5/igt@kms_bw@linear-tiling-1-displays-2160x1440p.html [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-7/igt@kms_bw@linear-tiling-1-displays-2160x1440p.html * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs: - shard-bmg: NOTRUN -> [SKIP][7] ([Intel XE#2887]) +2 other tests skip [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-5/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs.html * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs: - shard-bmg: [PASS][8] -> [INCOMPLETE][9] ([Intel XE#7084]) +1 other test incomplete [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-a-hdmi-a-3: - shard-bmg: NOTRUN -> [SKIP][10] ([Intel XE#2652]) +20 other tests skip [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-a-hdmi-a-3.html * igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-1: - shard-bmg: NOTRUN -> [FAIL][11] ([Intel XE#3304]) +1 other test fail [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-5/igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-1.html * igt@kms_content_protection@atomic-hdcp14@pipe-a-dp-2: - shard-bmg: NOTRUN -> [FAIL][12] ([Intel XE#1178] / [Intel XE#3304]) [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-9/igt@kms_content_protection@atomic-hdcp14@pipe-a-dp-2.html * igt@kms_content_protection@uevent@pipe-a-dp-1: - shard-bmg: NOTRUN -> [FAIL][13] ([Intel XE#6707]) [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-5/igt@kms_content_protection@uevent@pipe-a-dp-1.html * igt@kms_flip@flip-vs-suspend@c-hdmi-a3: - shard-bmg: [PASS][14] -> [INCOMPLETE][15] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86/shard-bmg-3/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-7/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling: - shard-bmg: NOTRUN -> [SKIP][16] ([Intel XE#7178]) +1 other test skip [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt: - shard-bmg: NOTRUN -> [SKIP][17] ([Intel XE#2311]) +2 other tests skip [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-mmap-wc: - shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#7061]) [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen: - shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#4141]) +1 other test skip [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff: - shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#2313]) +1 other test skip [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html * igt@kms_hdr@invalid-hdr: - shard-bmg: [PASS][21] -> [SKIP][22] ([Intel XE#1503]) [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86/shard-bmg-7/igt@kms_hdr@invalid-hdr.html [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-2/igt@kms_hdr@invalid-hdr.html * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area: - shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#1406] / [Intel XE#1489]) [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-7/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html * igt@kms_psr@psr-sprite-plane-move: - shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-1/igt@kms_psr@psr-sprite-plane-move.html * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1: - shard-lnl: [PASS][25] -> [FAIL][26] ([Intel XE#2142]) +1 other test fail [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86/shard-lnl-1/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-lnl-4/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html * igt@xe_evict@evict-beng-mixed-many-threads-small: - shard-bmg: [PASS][27] -> [INCOMPLETE][28] ([Intel XE#6321]) [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86/shard-bmg-8/igt@xe_evict@evict-beng-mixed-many-threads-small.html [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-6/igt@xe_evict@evict-beng-mixed-many-threads-small.html * igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm: - shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#7136]) +1 other test skip [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-1/igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm.html * igt@xe_exec_multi_queue@max-queues-basic: - shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#6874]) +1 other test skip [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-1/igt@xe_exec_multi_queue@max-queues-basic.html * igt@xe_pm_residency@aspm_link_residency: - shard-bmg: [PASS][31] -> [SKIP][32] ([Intel XE#7258]) [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86/shard-bmg-1/igt@xe_pm_residency@aspm_link_residency.html [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-6/igt@xe_pm_residency@aspm_link_residency.html #### Possible fixes #### * igt@kms_cursor_legacy@flip-vs-cursor-atomic: - shard-bmg: [FAIL][33] ([Intel XE#7480]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86/shard-bmg-9/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-bmg: [INCOMPLETE][35] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][36] +1 other test pass [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86/shard-bmg-7/igt@kms_flip@flip-vs-suspend-interruptible.html [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-1/igt@kms_flip@flip-vs-suspend-interruptible.html * igt@kms_plane_cursor@overlay@pipe-b-hdmi-a-3-size-128: - shard-bmg: [FAIL][37] ([Intel XE#7299]) -> [PASS][38] +1 other test pass [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86/shard-bmg-2/igt@kms_plane_cursor@overlay@pipe-b-hdmi-a-3-size-128.html [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-7/igt@kms_plane_cursor@overlay@pipe-b-hdmi-a-3-size-128.html #### Warnings #### * igt@kms_tiled_display@basic-test-pattern: - shard-bmg: [SKIP][39] ([Intel XE#2426]) -> [FAIL][40] ([Intel XE#1729]) [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124 [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178 [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406 [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489 [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503 [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729 [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049 [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142 [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234 [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311 [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313 [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327 [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426 [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597 [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652 [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850 [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887 [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304 [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367 [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141 [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321 [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707 [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874 [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061 [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084 [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136 [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178 [Intel XE#7258]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7258 [Intel XE#7299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7299 [Intel XE#7480]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7480 Build changes ------------- * Linux: xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86 -> xe-pw-162163v1 IGT_8771: 8771 xe-4617-3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86: 3b1923ab37ecd72e1405c7b8d3b1d9e1f3e59f86 xe-pw-162163v1: 162163v1 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162163v1/index.html [-- Attachment #2: Type: text/html, Size: 14828 bytes --] ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 0/8] drm/{i915,xe}: refactor register helpers 2026-02-25 17:57 [PATCH 0/8] drm/{i915,xe}: refactor register helpers Jani Nikula ` (11 preceding siblings ...) 2026-02-25 22:15 ` ✗ Xe.CI.FULL: " Patchwork @ 2026-03-03 15:12 ` Rodrigo Vivi 2026-03-04 11:56 ` Jani Nikula 12 siblings, 1 reply; 23+ messages in thread From: Rodrigo Vivi @ 2026-03-03 15:12 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, intel-xe On Wed, Feb 25, 2026 at 07:57:02PM +0200, Jani Nikula wrote: > I realized xe_reg_defs.h subtly pulls in i915_reg_defs.h from i915 via > the compat headers, which is ugly and wrong to say the least, and then > xe uses the macros all over the place. I also hadn't realized we had this mess o.O > > Clean this up by creating two shared headers under include/drm/intel, > with some related cleanups on top. Nice idea on the common header and nice clean up. Either way is good but probably drm-intel-next is easier: Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > BR, > Jani. > > > Jani Nikula (8): > drm/i915/reg: make masked field helpers constexpr > drm/i915/lrc: switch to _MASKED_BIT_ENABLE() and _MASKED_BIT_DISABLE() > drm/{i915,xe}/reg: rename masked field helpers REG_MASKED_FIELD*() > drm/i915/perf: prefer REG_MASKED_FIELD_ENABLE() and > REG_MASKED_FIELD_DISABLE() > drm/xe/oa: prefer REG_MASKED_FIELD_ENABLE() and > REG_MASKED_FIELD_DISABLE() > drm/intel: add reg_bits.h for the various register content helpers > drm/intel: add pick.h for the various "picker" helpers > drm/i915/gt: prefer _PICK_EVEN() over _PICK() > > drivers/gpu/drm/i915/display/i9xx_wm.c | 8 +- > .../gpu/drm/i915/display/intel_display_irq.c | 4 +- > drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 10 +- > drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +- > .../drm/i915/gt/intel_execlists_submission.c | 6 +- > drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 6 +- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +- > drivers/gpu/drm/i915/gt/intel_lrc.c | 21 +- > drivers/gpu/drm/i915/gt/intel_rc6.c | 22 +-- > drivers/gpu/drm/i915/gt/intel_reset.c | 4 +- > .../gpu/drm/i915/gt/intel_ring_submission.c | 19 +- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-- > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +- > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +- > drivers/gpu/drm/i915/gvt/handlers.c | 10 +- > drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +- > drivers/gpu/drm/i915/gvt/reg.h | 4 +- > drivers/gpu/drm/i915/i915_perf.c | 34 ++-- > drivers/gpu/drm/i915/i915_reg_defs.h | 179 +----------------- > drivers/gpu/drm/i915/intel_clock_gating.c | 38 ++-- > drivers/gpu/drm/i915/intel_uncore.c | 4 +- > drivers/gpu/drm/i915/pxp/intel_pxp.c | 4 +- > .../drm/xe/compat-i915-headers/intel_uncore.h | 1 + > drivers/gpu/drm/xe/regs/xe_reg_defs.h | 5 +- > drivers/gpu/drm/xe/xe_eu_stall.c | 20 +- > drivers/gpu/drm/xe/xe_execlist.c | 6 +- > drivers/gpu/drm/xe/xe_hw_engine.c | 8 +- > drivers/gpu/drm/xe/xe_lrc.c | 12 +- > drivers/gpu/drm/xe/xe_oa.c | 42 ++-- > drivers/gpu/drm/xe/xe_pxp.c | 4 +- > drivers/gpu/drm/xe/xe_uc_fw.c | 4 +- > include/drm/intel/pick.h | 51 +++++ > include/drm/intel/reg_bits.h | 139 ++++++++++++++ > 34 files changed, 362 insertions(+), 349 deletions(-) > create mode 100644 include/drm/intel/pick.h > create mode 100644 include/drm/intel/reg_bits.h > > -- > 2.47.3 > ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 0/8] drm/{i915,xe}: refactor register helpers 2026-03-03 15:12 ` [PATCH 0/8] " Rodrigo Vivi @ 2026-03-04 11:56 ` Jani Nikula 0 siblings, 0 replies; 23+ messages in thread From: Jani Nikula @ 2026-03-04 11:56 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx, intel-xe On Tue, 03 Mar 2026, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > On Wed, Feb 25, 2026 at 07:57:02PM +0200, Jani Nikula wrote: >> I realized xe_reg_defs.h subtly pulls in i915_reg_defs.h from i915 via >> the compat headers, which is ugly and wrong to say the least, and then >> xe uses the macros all over the place. > > I also hadn't realized we had this mess o.O > >> >> Clean this up by creating two shared headers under include/drm/intel, >> with some related cleanups on top. > > Nice idea on the common header and nice clean up. > > Either way is good but probably drm-intel-next is easier: > > Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Thanks, pushed the lot to drm-intel-next. BR, Jani. -- Jani Nikula, Intel ^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2026-03-04 11:56 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-02-25 17:57 [PATCH 0/8] drm/{i915,xe}: refactor register helpers Jani Nikula
2026-02-25 17:57 ` [PATCH 1/8] drm/i915/reg: make masked field helpers constexpr Jani Nikula
2026-03-02 20:08 ` Michał Grzelak
2026-02-25 17:57 ` [PATCH 2/8] drm/i915/lrc: switch to _MASKED_BIT_ENABLE() and _MASKED_BIT_DISABLE() Jani Nikula
2026-03-02 20:08 ` Michał Grzelak
2026-02-25 17:57 ` [PATCH 3/8] drm/{i915, xe}/reg: rename masked field helpers REG_MASKED_FIELD*() Jani Nikula
2026-03-02 20:08 ` Michał Grzelak
2026-02-25 17:57 ` [PATCH 4/8] drm/i915/perf: prefer REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() Jani Nikula
2026-03-02 20:08 ` Michał Grzelak
2026-02-25 17:57 ` [PATCH 5/8] drm/xe/oa: " Jani Nikula
2026-03-02 20:11 ` Michał Grzelak
2026-02-25 17:57 ` [PATCH 6/8] drm/intel: add reg_bits.h for the various register content helpers Jani Nikula
2026-03-02 20:11 ` Michał Grzelak
2026-02-25 17:57 ` [PATCH 7/8] drm/intel: add pick.h for the various "picker" helpers Jani Nikula
2026-03-02 20:11 ` Michał Grzelak
2026-02-25 17:57 ` [PATCH 8/8] drm/i915/gt: prefer _PICK_EVEN() over _PICK() Jani Nikula
2026-03-02 20:12 ` Michał Grzelak
2026-02-25 19:02 ` ✗ CI.checkpatch: warning for drm/{i915,xe}: refactor register helpers Patchwork
2026-02-25 19:03 ` ✓ CI.KUnit: success " Patchwork
2026-02-25 19:39 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-02-25 22:15 ` ✗ Xe.CI.FULL: " Patchwork
2026-03-03 15:12 ` [PATCH 0/8] " Rodrigo Vivi
2026-03-04 11:56 ` Jani Nikula
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