From: Andi Shyti <andi.shyti@linux.intel.com>
To: Badal Nilawar <badal.nilawar@intel.com>
Cc: linux-hwmon@vger.kernel.org, rodrigo.vivi@intel.com,
intel-xe@lists.freedesktop.org, linux@roeck-us.net
Subject: Re: [Intel-xe] [PATCH v6 5/5] drm/xe/hwmon: Expose power1_max_interval
Date: Mon, 25 Sep 2023 13:56:47 +0200 [thread overview]
Message-ID: <ZRF1f2OsC1pr5hFd@ashyti-mobl2.lan> (raw)
In-Reply-To: <20230925081842.3566834-6-badal.nilawar@intel.com>
Hi Badal,
[...]
> +static ssize_t
> +xe_hwmon_power1_max_interval_store(struct device *dev, struct device_attribute *attr,
> + const char *buf, size_t count)
> +{
> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> + u32 x, y, rxy, x_w = 2; /* 2 bits */
> + u64 tau4, r, max_win;
> + unsigned long val;
> + int ret;
> +
> + ret = kstrtoul(buf, 0, &val);
> + if (ret)
> + return ret;
> +
> + /*
> + * Max HW supported tau in '1.x * power(2,y)' format, x = 0, y = 0x12
> + * The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds
> + */
> +#define PKG_MAX_WIN_DEFAULT 0x12ull
> +
> + /*
> + * val must be < max in hwmon interface units. The steps below are
> + * explained in xe_hwmon_power1_max_interval_show()
> + */
> + r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
> + x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
> + y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
> + tau4 = ((1 << x_w) | x) << y;
> + max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
> +
> + if (val > max_win)
> + return -EINVAL;
> +
> + /* val in hw units */
> + val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
> + /* Convert to 1.x * power(2,y) */
> + if (!val) {
> + /* Avoid ilog2(0) */
> + y = 0;
> + x = 0;
> + } else {
> + y = ilog2(val);
> + /* x = (val - (1 << y)) >> (y - 2); */
this is some spurious development comment, can you please remove
it?
> + x = (val - (1ul << y)) << x_w >> y;
> + }
> +
> + rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + mutex_lock(&hwmon->hwmon_lock);
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, (u32 *)&r,
> + PKG_PWR_LIM_1_TIME, rxy);
> +
> + mutex_unlock(&hwmon->hwmon_lock);
why are we locking here?
Andi
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return count;
> +}
next prev parent reply other threads:[~2023-09-25 11:57 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-25 8:18 [Intel-xe] [PATCH v6 0/5] Add HWMON support for DGFX Badal Nilawar
2023-09-25 8:18 ` [Intel-xe] [PATCH v6 1/5] drm/xe/hwmon: Expose power attributes Badal Nilawar
2023-09-25 8:58 ` Andi Shyti
2023-09-27 4:45 ` Dixit, Ashutosh
2023-09-27 10:28 ` Nilawar, Badal
2023-09-28 4:54 ` Dixit, Ashutosh
2023-09-27 4:53 ` Dixit, Ashutosh
2023-09-27 8:39 ` Nilawar, Badal
2023-09-28 4:55 ` Dixit, Ashutosh
2023-09-29 6:37 ` Nilawar, Badal
2023-09-29 16:48 ` Dixit, Ashutosh
2023-09-29 21:41 ` Dixit, Ashutosh
2023-10-04 0:52 ` Dixit, Ashutosh
2023-10-04 6:43 ` Nilawar, Badal
2023-10-04 15:56 ` Rodrigo Vivi
2023-10-04 16:11 ` Rodrigo Vivi
2023-10-04 10:18 ` Nilawar, Badal
2023-09-28 4:55 ` Dixit, Ashutosh
2023-09-25 8:18 ` [Intel-xe] [PATCH v6 2/5] drm/xe/hwmon: Expose card reactive critical power Badal Nilawar
2023-09-25 9:03 ` Andi Shyti
2023-09-25 8:18 ` [Intel-xe] [PATCH v6 3/5] drm/xe/hwmon: Expose input voltage attribute Badal Nilawar
2023-09-25 9:04 ` Andi Shyti
2023-09-25 8:18 ` [Intel-xe] [PATCH v6 4/5] drm/xe/hwmon: Expose hwmon energy attribute Badal Nilawar
2023-09-25 11:49 ` Andi Shyti
2023-09-25 8:18 ` [Intel-xe] [PATCH v6 5/5] drm/xe/hwmon: Expose power1_max_interval Badal Nilawar
2023-09-25 11:56 ` Andi Shyti [this message]
[not found] ` <e5801f36-2f9a-6d24-7af2-1e7174f2e0b4@intel.com>
2023-09-26 8:01 ` Andi Shyti
2023-09-26 9:00 ` Nilawar, Badal
2023-09-26 21:01 ` Andi Shyti
2023-09-27 3:32 ` Dixit, Ashutosh
2023-09-27 9:04 ` Nilawar, Badal
2023-09-27 9:31 ` Gupta, Anshuman
2023-09-25 8:20 ` [Intel-xe] ✓ CI.Patch_applied: success for Add HWMON support for DGFX (rev6) Patchwork
2023-09-25 8:20 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-09-25 8:21 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-09-25 8:28 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-09-25 8:28 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork
2023-09-25 8:30 ` [Intel-xe] ✓ CI.checksparse: success " Patchwork
2023-09-25 9:04 ` [Intel-xe] ✗ CI.BAT: failure " Patchwork
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