From: "Nilawar, Badal" <badal.nilawar@intel.com>
To: Andi Shyti <andi.shyti@linux.intel.com>
Cc: linux-hwmon@vger.kernel.org, linux@roeck-us.net,
rodrigo.vivi@intel.com, intel-xe@lists.freedesktop.org
Subject: Re: [Intel-xe] [PATCH v6 5/5] drm/xe/hwmon: Expose power1_max_interval
Date: Tue, 26 Sep 2023 14:30:45 +0530 [thread overview]
Message-ID: <ec2a4e33-0b34-fb00-5470-f2d39edc6eb1@intel.com> (raw)
In-Reply-To: <ZRKP2UIGUWTXnZN6@ashyti-mobl2.lan>
Hi Andi,
On 26-09-2023 13:31, Andi Shyti wrote:
> Hi Badal,
>
>>>> + /* val in hw units */
>>>> + val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
>>>> + /* Convert to 1.x * power(2,y) */
>>>> + if (!val) {
>>>> + /* Avoid ilog2(0) */
>>>> + y = 0;
>>>> + x = 0;
>>>> + } else {
>>>> + y = ilog2(val);
>>>> + /* x = (val - (1 << y)) >> (y - 2); */
>>>
>>> this is some spurious development comment, can you please remove
>>> it?
>>
>> This is kept intentionally to help to understand the calculations.
>
> then this is confusing... Can you please expand the concept?
> As it is it's not understandable and I would expect someone
> sending a patch with title:
>
> [PATCH] drm/xe/hwmon: Remove spurious comment
>
> Because it just looks forgotten from previous development.
I will add this comment inside the comment at the top of if. So it will
look like.
/*
* Convert to 1.x * power(2,y)
* y = ilog(val);
* x = (val - (1 << y)) >> (y-2);
*/
>
>>>> + x = (val - (1ul << y)) << x_w >> y;
>>>> + }
>>>> +
>>>> + rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
>>>> +
>>>> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
>>>> +
>>>> + mutex_lock(&hwmon->hwmon_lock);
>>>> +
>>>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, (u32 *)&r,
>>>> + PKG_PWR_LIM_1_TIME, rxy);
>>>> +
>>>> + mutex_unlock(&hwmon->hwmon_lock);
>>>
>>> why are we locking here?
>>
>> Since it is rmw operation we are using lock here.
>
> OK... so what you are trying to protect here is the
>
> read -> update -> write
>
> and it makes sense. The problem is that if this is a generic
> rule, which means that everyone who will do a rmw operation has
> to take the lock, why not take the lock directly in
> xe_hwmon_process_reg()?
>
> But also this can be a bit confusing, because a function is
> either locked or unlocked and purists might complain.
>
> A suggestion would be to do something like:
>
> static int xe_hwmon_process_reg(..., enum xe_hwmon_reg_operation operation)
> {
> ...
> }
>
> static int xe_hwmon_reg_read(...);
> {
> return xe_hwmon_process_reg(..., REG_READ);
> }
>
> static int xe_hwmon_reg_write(...);
> {
> return xe_hwmon_process_reg(..., REG_WRITE);
> }
>
> static int xe_hwmon_reg_rmw(...);
> {
> int ret;
>
> /*
> * Optional: you can check that the lock is not taken
> * to shout loud if potential deadlocks arise.
> */
>
> /*
> * We want to protect the register update with the
> * lock blah blah blah... explanatory comment.
> */
> mutex_lock(&hwmon->hwmon_lock);
> ret = xe_hwmon_process_reg(..., REG_RMW);
> mutex_unlock(&hwmon->hwmon_lock);
>
> return ret;
> }
>
> What do you think? It looks much clearer to me.
REG_PKG_RAPL_LIMIT register is being written in xe_hwmon_power_max_write
also, that's why lock is taken. But some how while cleaning up I forgot
to take it in xe_hwmon_power_max_write(), thanks for catching it up. I
will update xe_hwmon_power_max_write() and resend series.
Thanks,
Badal
>
> Andi
next prev parent reply other threads:[~2023-09-26 9:01 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-25 8:18 [Intel-xe] [PATCH v6 0/5] Add HWMON support for DGFX Badal Nilawar
2023-09-25 8:18 ` [Intel-xe] [PATCH v6 1/5] drm/xe/hwmon: Expose power attributes Badal Nilawar
2023-09-25 8:58 ` Andi Shyti
2023-09-27 4:45 ` Dixit, Ashutosh
2023-09-27 10:28 ` Nilawar, Badal
2023-09-28 4:54 ` Dixit, Ashutosh
2023-09-27 4:53 ` Dixit, Ashutosh
2023-09-27 8:39 ` Nilawar, Badal
2023-09-28 4:55 ` Dixit, Ashutosh
2023-09-29 6:37 ` Nilawar, Badal
2023-09-29 16:48 ` Dixit, Ashutosh
2023-09-29 21:41 ` Dixit, Ashutosh
2023-10-04 0:52 ` Dixit, Ashutosh
2023-10-04 6:43 ` Nilawar, Badal
2023-10-04 15:56 ` Rodrigo Vivi
2023-10-04 16:11 ` Rodrigo Vivi
2023-10-04 10:18 ` Nilawar, Badal
2023-09-28 4:55 ` Dixit, Ashutosh
2023-09-25 8:18 ` [Intel-xe] [PATCH v6 2/5] drm/xe/hwmon: Expose card reactive critical power Badal Nilawar
2023-09-25 9:03 ` Andi Shyti
2023-09-25 8:18 ` [Intel-xe] [PATCH v6 3/5] drm/xe/hwmon: Expose input voltage attribute Badal Nilawar
2023-09-25 9:04 ` Andi Shyti
2023-09-25 8:18 ` [Intel-xe] [PATCH v6 4/5] drm/xe/hwmon: Expose hwmon energy attribute Badal Nilawar
2023-09-25 11:49 ` Andi Shyti
2023-09-25 8:18 ` [Intel-xe] [PATCH v6 5/5] drm/xe/hwmon: Expose power1_max_interval Badal Nilawar
2023-09-25 11:56 ` Andi Shyti
[not found] ` <e5801f36-2f9a-6d24-7af2-1e7174f2e0b4@intel.com>
2023-09-26 8:01 ` Andi Shyti
2023-09-26 9:00 ` Nilawar, Badal [this message]
2023-09-26 21:01 ` Andi Shyti
2023-09-27 3:32 ` Dixit, Ashutosh
2023-09-27 9:04 ` Nilawar, Badal
2023-09-27 9:31 ` Gupta, Anshuman
2023-09-25 8:20 ` [Intel-xe] ✓ CI.Patch_applied: success for Add HWMON support for DGFX (rev6) Patchwork
2023-09-25 8:20 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-09-25 8:21 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-09-25 8:28 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-09-25 8:28 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork
2023-09-25 8:30 ` [Intel-xe] ✓ CI.checksparse: success " Patchwork
2023-09-25 9:04 ` [Intel-xe] ✗ CI.BAT: failure " Patchwork
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