Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Andi Shyti <andi.shyti@linux.intel.com>
To: Badal Nilawar <badal.nilawar@intel.com>
Cc: linux-hwmon@vger.kernel.org, rodrigo.vivi@intel.com,
	intel-xe@lists.freedesktop.org, linux@roeck-us.net
Subject: Re: [Intel-xe] [PATCH v6 4/5] drm/xe/hwmon: Expose hwmon energy attribute
Date: Mon, 25 Sep 2023 13:49:23 +0200	[thread overview]
Message-ID: <ZRFzw4BJNhb0v5mu@ashyti-mobl2.lan> (raw)
In-Reply-To: <20230925081842.3566834-5-badal.nilawar@intel.com>

Hi Badal,

[...]

> +/*
> + * xe_hwmon_energy_get - Obtain energy value
> + *
> + * The underlying energy hardware register is 32-bits and is subject to
> + * overflow. How long before overflow? For example, with an example
> + * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and
> + * a power draw of 1000 watts, the 32-bit counter will overflow in
> + * approximately 4.36 minutes.
> + *
> + * Examples:
> + *    1 watt:  (2^32 >> 14) /    1 W / (60 * 60 * 24) secs/day -> 3 days
> + * 1000 watts: (2^32 >> 14) / 1000 W / 60             secs/min -> 4.36 minutes
> + *
> + * The function significantly increases overflow duration (from 4.36
> + * minutes) by accumulating the energy register into a 'long' as allowed by
> + * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()),
> + * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and
> + * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before
> + * energy1_input overflows. This at 1000 W is an overflow duration of 278 years.
> + */
> +static void
> +xe_hwmon_energy_get(struct xe_hwmon *hwmon, long *energy)

can we call it rather xe_hwmon_energy_update() as this is not
sending anything, but just updating the energy values.

Anyway...

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> 

Andi

  reply	other threads:[~2023-09-25 11:49 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-25  8:18 [Intel-xe] [PATCH v6 0/5] Add HWMON support for DGFX Badal Nilawar
2023-09-25  8:18 ` [Intel-xe] [PATCH v6 1/5] drm/xe/hwmon: Expose power attributes Badal Nilawar
2023-09-25  8:58   ` Andi Shyti
2023-09-27  4:45   ` Dixit, Ashutosh
2023-09-27 10:28     ` Nilawar, Badal
2023-09-28  4:54       ` Dixit, Ashutosh
2023-09-27  4:53   ` Dixit, Ashutosh
2023-09-27  8:39     ` Nilawar, Badal
2023-09-28  4:55       ` Dixit, Ashutosh
2023-09-29  6:37         ` Nilawar, Badal
2023-09-29 16:48           ` Dixit, Ashutosh
2023-09-29 21:41             ` Dixit, Ashutosh
2023-10-04  0:52               ` Dixit, Ashutosh
2023-10-04  6:43                 ` Nilawar, Badal
2023-10-04 15:56                   ` Rodrigo Vivi
2023-10-04 16:11                     ` Rodrigo Vivi
2023-10-04 10:18               ` Nilawar, Badal
2023-09-28  4:55   ` Dixit, Ashutosh
2023-09-25  8:18 ` [Intel-xe] [PATCH v6 2/5] drm/xe/hwmon: Expose card reactive critical power Badal Nilawar
2023-09-25  9:03   ` Andi Shyti
2023-09-25  8:18 ` [Intel-xe] [PATCH v6 3/5] drm/xe/hwmon: Expose input voltage attribute Badal Nilawar
2023-09-25  9:04   ` Andi Shyti
2023-09-25  8:18 ` [Intel-xe] [PATCH v6 4/5] drm/xe/hwmon: Expose hwmon energy attribute Badal Nilawar
2023-09-25 11:49   ` Andi Shyti [this message]
2023-09-25  8:18 ` [Intel-xe] [PATCH v6 5/5] drm/xe/hwmon: Expose power1_max_interval Badal Nilawar
2023-09-25 11:56   ` Andi Shyti
     [not found]     ` <e5801f36-2f9a-6d24-7af2-1e7174f2e0b4@intel.com>
2023-09-26  8:01       ` Andi Shyti
2023-09-26  9:00         ` Nilawar, Badal
2023-09-26 21:01           ` Andi Shyti
2023-09-27  3:32             ` Dixit, Ashutosh
2023-09-27  9:04               ` Nilawar, Badal
2023-09-27  9:31                 ` Gupta, Anshuman
2023-09-25  8:20 ` [Intel-xe] ✓ CI.Patch_applied: success for Add HWMON support for DGFX (rev6) Patchwork
2023-09-25  8:20 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-09-25  8:21 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-09-25  8:28 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-09-25  8:28 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork
2023-09-25  8:30 ` [Intel-xe] ✓ CI.checksparse: success " Patchwork
2023-09-25  9:04 ` [Intel-xe] ✗ CI.BAT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ZRFzw4BJNhb0v5mu@ashyti-mobl2.lan \
    --to=andi.shyti@linux.intel.com \
    --cc=badal.nilawar@intel.com \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=linux-hwmon@vger.kernel.org \
    --cc=linux@roeck-us.net \
    --cc=rodrigo.vivi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox