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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	uma.shankar@intel.com, animesh.manna@intel.com
Subject: Re: [PATCH 05/11] drm/i915/dsb: add intel_dsb_gosub_finish()
Date: Mon, 7 Apr 2025 19:19:25 +0300	[thread overview]
Message-ID: <Z_P7Da3un_pvEfqj@intel.com> (raw)
In-Reply-To: <20250407142359.1398410-6-chaitanya.kumar.borah@intel.com>

On Mon, Apr 07, 2025 at 07:53:53PM +0530, Chaitanya Kumar Borah wrote:
> A DSB buffer which will be used for GOSUB execution does not need
> the DEWAKE mechanism but still need to be 64 bit aligned. Add helper
> to finish preparation of a dsb buffer to be executed with GOSUB
> instruction.
> 
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c | 7 +++++++
>  drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 2cda6fc7857b..bffa02a0442c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -585,6 +585,13 @@ void intel_dsb_gosub(struct intel_dsb *dsb,
>  	intel_dsb_align_tail(dsb);
>  }
>  
> +void intel_dsb_gosub_finish(struct intel_dsb *dsb)
> +{
> +	intel_dsb_align_tail(dsb);

There is one more w/a listd that may require us to do something like::

/* "All subroutines called by the GOSUB instruction must end with a cacheline of NOPs" */
intel_dsb_noop(8);

> +
> +	intel_dsb_buffer_flush_map(&dsb->dsb_buf);
> +}
> +
>  void intel_dsb_finish(struct intel_dsb *dsb)
>  {
>  	struct intel_crtc *crtc = dsb->crtc;
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
> index 8b2cf0a7b7e6..6900acd603b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -31,6 +31,7 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state,
>  				    enum intel_dsb_id dsb_id,
>  				    unsigned int max_cmds);
>  void intel_dsb_finish(struct intel_dsb *dsb);
> +void intel_dsb_gosub_finish(struct intel_dsb *dsb);
>  void intel_dsb_cleanup(struct intel_dsb *dsb);
>  void intel_dsb_reg_write(struct intel_dsb *dsb,
>  			 i915_reg_t reg, u32 val);
> -- 
> 2.25.1

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2025-04-07 16:19 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-07 14:23 [PATCH 00/11] drm/xe/display: Program double buffered LUT registers Chaitanya Kumar Borah
2025-04-07 14:23 ` [PATCH 01/11] drm/i915/dsb: Extract intel_dsb_ins_align() Chaitanya Kumar Borah
2025-05-14  8:01   ` Shankar, Uma
2025-05-14 11:16   ` Jani Nikula
2025-05-14 11:58     ` Borah, Chaitanya Kumar
2025-04-07 14:23 ` [PATCH 02/11] drm/i915/dsb: Extract assert_dsb_tail_is_aligned() Chaitanya Kumar Borah
2025-04-07 14:23 ` [PATCH 03/11] drm/i915/dsb: Extract intel_dsb_{head,tail}() Chaitanya Kumar Borah
2025-04-07 14:23 ` [PATCH 04/11] drm/i915/dsb: Implement intel_dsb_gosub() Chaitanya Kumar Borah
2025-05-14  9:18   ` Shankar, Uma
2025-04-07 14:23 ` [PATCH 05/11] drm/i915/dsb: add intel_dsb_gosub_finish() Chaitanya Kumar Borah
2025-04-07 16:19   ` Ville Syrjälä [this message]
2025-04-07 14:23 ` [PATCH 06/11] drm/i915/dsb: Add support for GOSUB interrupt Chaitanya Kumar Borah
2025-04-07 16:30   ` Ville Syrjälä
2025-04-07 14:23 ` [PATCH 07/11] drm/i915: s/dsb_color_vblank/dsb_color Chaitanya Kumar Borah
2025-04-07 16:39   ` Ville Syrjälä
2025-04-07 14:23 ` [PATCH 08/11] drm/i915: use GOSUB to program doubled buffered LUT registers Chaitanya Kumar Borah
2025-04-07 16:51   ` Ville Syrjälä
2025-04-07 14:23 ` [PATCH 09/11] drm/i915: Program DB LUT registers before vblank Chaitanya Kumar Borah
2025-04-07 16:54   ` Ville Syrjälä
2025-04-07 14:23 ` [PATCH 10/11] drm/i915/color: Do not pre-load LUTs with DB registers Chaitanya Kumar Borah
2025-04-07 14:23 ` [PATCH 11/11] drm/i915: Disable updating of LUT values during vblank Chaitanya Kumar Borah
2025-04-07 14:49 ` ✓ CI.Patch_applied: success for drm/xe/display: Program double buffered LUT registers (rev5) Patchwork
2025-04-07 14:49 ` ✓ CI.checkpatch: " Patchwork
2025-04-07 14:50 ` ✓ CI.KUnit: " Patchwork
2025-04-07 14:54 ` ✗ CI.Build: failure " Patchwork

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