[PATCH 02/19] drm/i915/dss_regs: Use REG_* macros for the DSS ctl bits

[PATCH 02/19] drm/i915/dss_regs: Use REG_* macros for the DSS ctl bits

[Ankit Nautiyal]

Cleanup register definitions for DSS CLT reg bits.
Replace the hand rolled (1<<n) with the modern REG_BIT().
Use REG_GENMASK and REG_FIELD_PREP for the bit fields.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dss_regs.h | 34 ++++++++++---------
 1 file changed, 18 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dss_regs.h b/drivers/gpu/drm/i915/display/intel_dss_regs.h
index b1e24ea027c3..cfc8ef451917 100644
--- a/drivers/gpu/drm/i915/display/intel_dss_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dss_regs.h
@@ -10,35 +10,37 @@
 
 /* Display Stream Splitter Control */
 #define DSS_CTL1				_MMIO(0x67400)
-#define  SPLITTER_ENABLE			(1 << 31)
-#define  JOINER_ENABLE				(1 << 30)
-#define  DUAL_LINK_MODE_INTERLEAVE		(1 << 24)
+#define  SPLITTER_ENABLE			REG_BIT(31)
+#define  JOINER_ENABLE				REG_BIT(30)
+#define  DUAL_LINK_MODE_INTERLEAVE		REG_BIT(24)
 #define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)
-#define  OVERLAP_PIXELS_MASK			(0xf << 16)
-#define  OVERLAP_PIXELS(pixels)			((pixels) << 16)
-#define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
-#define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
+#define  OVERLAP_PIXELS_MASK			REG_GENMASK(19, 16)
+#define  OVERLAP_PIXELS(pixels)			REG_FIELD_PREP(OVERLAP_PIXELS_MASK, pixels)
+#define  LEFT_DL_BUF_TARGET_DEPTH_MASK		REG_GENMASK(11, 0)
+#define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	REG_FIELD_PREP(LEFT_DL_BUF_TARGET_DEPTH_MASK, \
+							       pixels)
 #define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0
 
 #define DSS_CTL2				_MMIO(0x67404)
-#define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
-#define  RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
-#define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
-#define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
+#define  LEFT_BRANCH_VDSC_ENABLE		REG_BIT(31)
+#define  RIGHT_BRANCH_VDSC_ENABLE		REG_BIT(15)
+#define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		REG_GENMASK(11, 0)
+#define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	REG_FIELD_PREP(RIGHT_DL_BUF_TARGET_DEPTH_MASK,\
+							       pixels)
 
 #define _ICL_PIPE_DSS_CTL1_PB			0x78200
 #define _ICL_PIPE_DSS_CTL1_PC			0x78400
 #define ICL_PIPE_DSS_CTL1(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_PIPE_DSS_CTL1_PB, \
 							   _ICL_PIPE_DSS_CTL1_PC)
-#define  BIG_JOINER_ENABLE			(1 << 29)
-#define  PRIMARY_BIG_JOINER_ENABLE		(1 << 28)
-#define  VGA_CENTERING_ENABLE			(1 << 27)
+#define  BIG_JOINER_ENABLE			REG_BIT(29)
+#define  PRIMARY_BIG_JOINER_ENABLE		REG_BIT(28)
+#define  VGA_CENTERING_ENABLE			REG_BIT(27)
 #define  SPLITTER_CONFIGURATION_MASK		REG_GENMASK(26, 25)
 #define  SPLITTER_CONFIGURATION_2_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
 #define  SPLITTER_CONFIGURATION_4_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
-#define  UNCOMPRESSED_JOINER_PRIMARY		(1 << 21)
-#define  UNCOMPRESSED_JOINER_SECONDARY		(1 << 20)
+#define  UNCOMPRESSED_JOINER_PRIMARY		REG_BIT(21)
+#define  UNCOMPRESSED_JOINER_SECONDARY		REG_BIT(20)
 
 #define _ICL_PIPE_DSS_CTL2_PB			0x78204
 #define _ICL_PIPE_DSS_CTL2_PC			0x78404
-- 
2.45.2

[PATCH 00/19] Consolidation of DSS Control in Separate Files

[Ankit Nautiyal]

Currently, DSS control is configured from various files; this change aims
to consolidate all DSS-related functionalities, such as display stream
splitting, joining, MSO configuration, and joining configuration,
into one place.

A new file, intel_dss_regs.h, will store register information, while the
helpers to configure DSS and related stuff will be moved to intel_dss.c
with its corresponding header file intel_dss.h.
Along with this, the helpers related to retrieve information about the
pipe joiners are also moved from intel_display.c to intel_joiner.

Additionally, wherever possible, the drm_i915_private structure is
replaced with the new intel_display structure as part of ongoing efforts
to phase out the old structure.

Rev2:
-Addressed review comments from Jani.
-Moved all joiner stuff into a separate file.

Rev3:
-Rebase

Ankit Nautiyal (19):
  drm/i915/display: Move all DSS control registers to a new file
  drm/i915/dss_regs: Use REG_* macros for the DSS ctl bits
  drm/i915/ddi: Move all mso related helpers to a new file
  drm/i915/dss: Move to struct intel_display
  drm/i915/icl_dsi: Avoid using intel_dsi in configure_dual_link_mode
  drm/i915/icl_dsi: Use intel_display in configure_dual_link_mode
  drm/i915/icl_dsi: Move helpers to configure dsi dual link to intel_dss
  drm/i915/vdsc: Rename helper to check if the pipe supports dsc
  drm/i915/vdsc: Move all dss stuff in dss files
  drm/i915/dss: Use struct intel_display in dss dsc helpers
  drm/i915/display: Move dss stuff in intel_dss files
  drm/i915/display: Rename static functions that use joiner
  drm/i915/display: Separate out joiner stuff in a new file
  drm/i915/display: Move intel_crtc_joined_pipe_mask to intel_joiner
  drm/i915/display: Move helpers for primary joiner to intel_joiner
  drm/i915/display: Move intel_crtc_is_joiner_secondary to intel_joiner
  drm/i915/display: Move intel_crtc_joiner_secondary_pipes to
    intel_joiner
  drm/i915/joiner: Use struct intel_display in
    intel_joiner_enabled_pipes
  drm/i915/joiner: Use struct intel_display in
    intel_joiner_supported_pipes

 drivers/gpu/drm/i915/Makefile                 |   2 +
 drivers/gpu/drm/i915/display/icl_dsi.c        |  55 +--
 .../gpu/drm/i915/display/intel_atomic_plane.c |   3 +-
 .../drm/i915/display/intel_crtc_state_dump.c  |   5 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  95 +----
 drivers/gpu/drm/i915/display/intel_display.c  | 359 +++---------------
 drivers/gpu/drm/i915/display/intel_display.h  |   9 +-
 .../drm/i915/display/intel_display_debugfs.c  |   3 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   7 +-
 drivers/gpu/drm/i915/display/intel_drrs.c     |   5 +-
 drivers/gpu/drm/i915/display/intel_dss.c      | 268 +++++++++++++
 drivers/gpu/drm/i915/display/intel_dss.h      |  35 ++
 drivers/gpu/drm/i915/display/intel_dss_regs.h |  51 +++
 drivers/gpu/drm/i915/display/intel_joiner.c   | 265 +++++++++++++
 drivers/gpu/drm/i915/display/intel_joiner.h   |  36 ++
 .../drm/i915/display/intel_modeset_setup.c    |  15 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  74 +---
 drivers/gpu/drm/i915/display/intel_vdsc.h     |   2 +-
 .../gpu/drm/i915/display/intel_vdsc_regs.h    |  38 --
 drivers/gpu/drm/xe/Makefile                   |   2 +
 20 files changed, 757 insertions(+), 572 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dss.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_dss.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_dss_regs.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_joiner.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_joiner.h

-- 
2.45.2

[PATCH 01/19] drm/i915/display: Move all DSS control registers to a new file

[Ankit Nautiyal]

Move all registers and bits related to dss ctl to a new file.

v2: Move modification to use REG_* macros to a new patch. (Jani)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        |  2 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_dss_regs.h | 49 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  1 +
 .../gpu/drm/i915/display/intel_vdsc_regs.h    | 38 --------------
 6 files changed, 53 insertions(+), 41 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dss_regs.h

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 293efc1f841d..5ad5011e1fee 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -44,9 +44,9 @@
 #include "intel_de.h"
 #include "intel_dsi.h"
 #include "intel_dsi_vbt.h"
+#include "intel_dss_regs.h"
 #include "intel_panel.h"
 #include "intel_vdsc.h"
-#include "intel_vdsc_regs.h"
 #include "skl_scaler.h"
 #include "skl_universal_plane.h"
 
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 25ff3ff0ab95..4566a60c981c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -57,6 +57,7 @@
 #include "intel_dp_tunnel.h"
 #include "intel_dpio_phy.h"
 #include "intel_dsi.h"
+#include "intel_dss_regs.h"
 #include "intel_encoder.h"
 #include "intel_fdi.h"
 #include "intel_fifo_underrun.h"
@@ -74,7 +75,6 @@
 #include "intel_snps_phy.h"
 #include "intel_tc.h"
 #include "intel_vdsc.h"
-#include "intel_vdsc_regs.h"
 #include "skl_scaler.h"
 #include "skl_universal_plane.h"
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 78ce402a5cd0..3cb960ca6eda 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -87,6 +87,7 @@
 #include "intel_drrs.h"
 #include "intel_dsb.h"
 #include "intel_dsi.h"
+#include "intel_dss_regs.h"
 #include "intel_dvo.h"
 #include "intel_fb.h"
 #include "intel_fbc.h"
@@ -118,7 +119,6 @@
 #include "intel_tv.h"
 #include "intel_vblank.h"
 #include "intel_vdsc.h"
-#include "intel_vdsc_regs.h"
 #include "intel_vga.h"
 #include "intel_vrr.h"
 #include "intel_wm.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dss_regs.h b/drivers/gpu/drm/i915/display/intel_dss_regs.h
new file mode 100644
index 000000000000..b1e24ea027c3
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dss_regs.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_DSS_REGS_H__
+#define __INTEL_DSS_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+/* Display Stream Splitter Control */
+#define DSS_CTL1				_MMIO(0x67400)
+#define  SPLITTER_ENABLE			(1 << 31)
+#define  JOINER_ENABLE				(1 << 30)
+#define  DUAL_LINK_MODE_INTERLEAVE		(1 << 24)
+#define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)
+#define  OVERLAP_PIXELS_MASK			(0xf << 16)
+#define  OVERLAP_PIXELS(pixels)			((pixels) << 16)
+#define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
+#define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
+#define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0
+
+#define DSS_CTL2				_MMIO(0x67404)
+#define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
+#define  RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
+#define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
+#define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
+
+#define _ICL_PIPE_DSS_CTL1_PB			0x78200
+#define _ICL_PIPE_DSS_CTL1_PC			0x78400
+#define ICL_PIPE_DSS_CTL1(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
+							   _ICL_PIPE_DSS_CTL1_PB, \
+							   _ICL_PIPE_DSS_CTL1_PC)
+#define  BIG_JOINER_ENABLE			(1 << 29)
+#define  PRIMARY_BIG_JOINER_ENABLE		(1 << 28)
+#define  VGA_CENTERING_ENABLE			(1 << 27)
+#define  SPLITTER_CONFIGURATION_MASK		REG_GENMASK(26, 25)
+#define  SPLITTER_CONFIGURATION_2_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
+#define  SPLITTER_CONFIGURATION_4_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
+#define  UNCOMPRESSED_JOINER_PRIMARY		(1 << 21)
+#define  UNCOMPRESSED_JOINER_SECONDARY		(1 << 20)
+
+#define _ICL_PIPE_DSS_CTL2_PB			0x78204
+#define _ICL_PIPE_DSS_CTL2_PC			0x78404
+#define ICL_PIPE_DSS_CTL2(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
+							   _ICL_PIPE_DSS_CTL2_PB, \
+							   _ICL_PIPE_DSS_CTL2_PC)
+
+#endif /* __INTEL_DSS_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 2e849b015e74..891346f1f09a 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -15,6 +15,7 @@
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_dsi.h"
+#include "intel_dss_regs.h"
 #include "intel_qp_tables.h"
 #include "intel_vdsc.h"
 #include "intel_vdsc_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index f921ad67b587..27c696e266af 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -8,44 +8,6 @@
 
 #include "intel_display_reg_defs.h"
 
-/* Display Stream Splitter Control */
-#define DSS_CTL1				_MMIO(0x67400)
-#define  SPLITTER_ENABLE			(1 << 31)
-#define  JOINER_ENABLE				(1 << 30)
-#define  DUAL_LINK_MODE_INTERLEAVE		(1 << 24)
-#define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)
-#define  OVERLAP_PIXELS_MASK			(0xf << 16)
-#define  OVERLAP_PIXELS(pixels)			((pixels) << 16)
-#define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
-#define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
-#define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0
-
-#define DSS_CTL2				_MMIO(0x67404)
-#define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
-#define  RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
-#define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
-#define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
-
-#define _ICL_PIPE_DSS_CTL1_PB			0x78200
-#define _ICL_PIPE_DSS_CTL1_PC			0x78400
-#define ICL_PIPE_DSS_CTL1(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_PIPE_DSS_CTL1_PB, \
-							   _ICL_PIPE_DSS_CTL1_PC)
-#define  BIG_JOINER_ENABLE			(1 << 29)
-#define  PRIMARY_BIG_JOINER_ENABLE		(1 << 28)
-#define  VGA_CENTERING_ENABLE			(1 << 27)
-#define  SPLITTER_CONFIGURATION_MASK		REG_GENMASK(26, 25)
-#define  SPLITTER_CONFIGURATION_2_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
-#define  SPLITTER_CONFIGURATION_4_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
-#define  UNCOMPRESSED_JOINER_PRIMARY		(1 << 21)
-#define  UNCOMPRESSED_JOINER_SECONDARY		(1 << 20)
-
-#define _ICL_PIPE_DSS_CTL2_PB			0x78204
-#define _ICL_PIPE_DSS_CTL2_PC			0x78404
-#define ICL_PIPE_DSS_CTL2(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_PIPE_DSS_CTL2_PB, \
-							   _ICL_PIPE_DSS_CTL2_PC)
-
 /* Icelake Display Stream Compression Registers */
 #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
 #define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
-- 
2.45.2

[PATCH 02/19] drm/i915/dss_regs: Use REG_* macros for the DSS ctl bits

[Ankit Nautiyal]

Cleanup register definitions for DSS CLT reg bits.
Replace the hand rolled (1<<n) with the modern REG_BIT().
Use REG_GENMASK and REG_FIELD_PREP for the bit fields.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dss_regs.h | 34 ++++++++++---------
 1 file changed, 18 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dss_regs.h b/drivers/gpu/drm/i915/display/intel_dss_regs.h
index b1e24ea027c3..cfc8ef451917 100644
--- a/drivers/gpu/drm/i915/display/intel_dss_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dss_regs.h
@@ -10,35 +10,37 @@
 
 /* Display Stream Splitter Control */
 #define DSS_CTL1				_MMIO(0x67400)
-#define  SPLITTER_ENABLE			(1 << 31)
-#define  JOINER_ENABLE				(1 << 30)
-#define  DUAL_LINK_MODE_INTERLEAVE		(1 << 24)
+#define  SPLITTER_ENABLE			REG_BIT(31)
+#define  JOINER_ENABLE				REG_BIT(30)
+#define  DUAL_LINK_MODE_INTERLEAVE		REG_BIT(24)
 #define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)
-#define  OVERLAP_PIXELS_MASK			(0xf << 16)
-#define  OVERLAP_PIXELS(pixels)			((pixels) << 16)
-#define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
-#define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
+#define  OVERLAP_PIXELS_MASK			REG_GENMASK(19, 16)
+#define  OVERLAP_PIXELS(pixels)			REG_FIELD_PREP(OVERLAP_PIXELS_MASK, pixels)
+#define  LEFT_DL_BUF_TARGET_DEPTH_MASK		REG_GENMASK(11, 0)
+#define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	REG_FIELD_PREP(LEFT_DL_BUF_TARGET_DEPTH_MASK, \
+							       pixels)
 #define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0
 
 #define DSS_CTL2				_MMIO(0x67404)
-#define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
-#define  RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
-#define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
-#define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
+#define  LEFT_BRANCH_VDSC_ENABLE		REG_BIT(31)
+#define  RIGHT_BRANCH_VDSC_ENABLE		REG_BIT(15)
+#define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		REG_GENMASK(11, 0)
+#define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	REG_FIELD_PREP(RIGHT_DL_BUF_TARGET_DEPTH_MASK,\
+							       pixels)
 
 #define _ICL_PIPE_DSS_CTL1_PB			0x78200
 #define _ICL_PIPE_DSS_CTL1_PC			0x78400
 #define ICL_PIPE_DSS_CTL1(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_PIPE_DSS_CTL1_PB, \
 							   _ICL_PIPE_DSS_CTL1_PC)
-#define  BIG_JOINER_ENABLE			(1 << 29)
-#define  PRIMARY_BIG_JOINER_ENABLE		(1 << 28)
-#define  VGA_CENTERING_ENABLE			(1 << 27)
+#define  BIG_JOINER_ENABLE			REG_BIT(29)
+#define  PRIMARY_BIG_JOINER_ENABLE		REG_BIT(28)
+#define  VGA_CENTERING_ENABLE			REG_BIT(27)
 #define  SPLITTER_CONFIGURATION_MASK		REG_GENMASK(26, 25)
 #define  SPLITTER_CONFIGURATION_2_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
 #define  SPLITTER_CONFIGURATION_4_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
-#define  UNCOMPRESSED_JOINER_PRIMARY		(1 << 21)
-#define  UNCOMPRESSED_JOINER_SECONDARY		(1 << 20)
+#define  UNCOMPRESSED_JOINER_PRIMARY		REG_BIT(21)
+#define  UNCOMPRESSED_JOINER_SECONDARY		REG_BIT(20)
 
 #define _ICL_PIPE_DSS_CTL2_PB			0x78204
 #define _ICL_PIPE_DSS_CTL2_PC			0x78404
-- 
2.45.2

[PATCH 03/19] drm/i915/ddi: Move all mso related helpers to a new file

[Ankit Nautiyal]

Move the MSO related helper functions from intel_ddi.c to a new file
intel_dss.c to improve code modularity and maintainability.
The corresponding headers are also moved to intel_dss.h.

v2: Retain the old naming scheme for the functions and only add dss
prefix. (Jani)

v3: Remove extra line at the end of header file.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/Makefile            |  1 +
 drivers/gpu/drm/i915/display/intel_ddi.c | 86 ++---------------------
 drivers/gpu/drm/i915/display/intel_dss.c | 87 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dss.h | 20 ++++++
 drivers/gpu/drm/xe/Makefile              |  1 +
 5 files changed, 114 insertions(+), 81 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dss.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_dss.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c63fa2133ccb..e55ce8ba123c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -328,6 +328,7 @@ i915-y += \
 	display/intel_dsi.o \
 	display/intel_dsi_dcs_backlight.o \
 	display/intel_dsi_vbt.o \
+	display/intel_dss.o \
 	display/intel_dvo.o \
 	display/intel_encoder.o \
 	display/intel_gmbus.o \
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4566a60c981c..7cc766043a5b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -57,7 +57,7 @@
 #include "intel_dp_tunnel.h"
 #include "intel_dpio_phy.h"
 #include "intel_dsi.h"
-#include "intel_dss_regs.h"
+#include "intel_dss.h"
 #include "intel_encoder.h"
 #include "intel_fdi.h"
 #include "intel_fifo_underrun.h"
@@ -2349,82 +2349,6 @@ static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
 	}
 }
 
-/*
- * Splitter enable for eDP MSO is limited to certain pipes, on certain
- * platforms.
- */
-static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
-{
-	if (DISPLAY_VER(i915) > 20)
-		return ~0;
-	else if (IS_ALDERLAKE_P(i915))
-		return BIT(PIPE_A) | BIT(PIPE_B);
-	else
-		return BIT(PIPE_A);
-}
-
-static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
-				     struct intel_crtc_state *pipe_config)
-{
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	enum pipe pipe = crtc->pipe;
-	u32 dss1;
-
-	if (!HAS_MSO(i915))
-		return;
-
-	dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
-
-	pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
-	if (!pipe_config->splitter.enable)
-		return;
-
-	if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {
-		pipe_config->splitter.enable = false;
-		return;
-	}
-
-	switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
-	default:
-		drm_WARN(&i915->drm, true,
-			 "Invalid splitter configuration, dss1=0x%08x\n", dss1);
-		fallthrough;
-	case SPLITTER_CONFIGURATION_2_SEGMENT:
-		pipe_config->splitter.link_count = 2;
-		break;
-	case SPLITTER_CONFIGURATION_4_SEGMENT:
-		pipe_config->splitter.link_count = 4;
-		break;
-	}
-
-	pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
-}
-
-static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	enum pipe pipe = crtc->pipe;
-	u32 dss1 = 0;
-
-	if (!HAS_MSO(i915))
-		return;
-
-	if (crtc_state->splitter.enable) {
-		dss1 |= SPLITTER_ENABLE;
-		dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
-		if (crtc_state->splitter.link_count == 2)
-			dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
-		else
-			dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
-	}
-
-	intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
-		     SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
-		     OVERLAP_PIXELS_MASK, dss1);
-}
-
 static u8 mtl_get_port_width(u8 lane_count)
 {
 	switch (lane_count) {
@@ -2559,7 +2483,7 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	/*
 	 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected.
 	 */
-	intel_ddi_mso_configure(crtc_state);
+	intel_dss_mso_configure(crtc_state);
 
 	if (!is_mst)
 		intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
@@ -2714,7 +2638,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	/*
 	 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
 	 */
-	intel_ddi_mso_configure(crtc_state);
+	intel_dss_mso_configure(crtc_state);
 
 	if (!is_mst)
 		intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
@@ -3959,7 +3883,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
 
 	intel_ddi_read_func_ctl(encoder, pipe_config);
 
-	intel_ddi_mso_get_config(encoder, pipe_config);
+	intel_dss_mso_get_config(encoder, pipe_config);
 
 	pipe_config->has_audio =
 		intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
@@ -5191,7 +5115,7 @@ void intel_ddi_init(struct intel_display *display,
 		dig_port->hpd_pulse = intel_dp_hpd_pulse;
 
 		if (dig_port->dp.mso_link_count)
-			encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);
+			encoder->pipe_mask = intel_dss_mso_pipe_mask(dev_priv);
 	}
 
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c
new file mode 100644
index 000000000000..e774f55f7008
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dss.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "i915_reg_defs.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+#include "intel_dss.h"
+#include "intel_dss_regs.h"
+
+/*
+ * Splitter enable for eDP MSO is limited to certain pipes, on certain
+ * platforms.
+ */
+u8 intel_dss_mso_pipe_mask(struct drm_i915_private *i915)
+{
+	if (DISPLAY_VER(i915) > 20)
+		return ~0;
+	else if (IS_ALDERLAKE_P(i915))
+		return BIT(PIPE_A) | BIT(PIPE_B);
+	else
+		return BIT(PIPE_A);
+}
+
+void intel_dss_mso_get_config(struct intel_encoder *encoder,
+			      struct intel_crtc_state *pipe_config)
+{
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	u32 dss1;
+
+	if (!HAS_MSO(i915))
+		return;
+
+	dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
+
+	pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
+	if (!pipe_config->splitter.enable)
+		return;
+
+	if (drm_WARN_ON(&i915->drm, !(intel_dss_mso_pipe_mask(i915) & BIT(pipe)))) {
+		pipe_config->splitter.enable = false;
+		return;
+	}
+
+	switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
+	default:
+		drm_WARN(&i915->drm, true,
+			 "Invalid splitter configuration, dss1=0x%08x\n", dss1);
+		fallthrough;
+	case SPLITTER_CONFIGURATION_2_SEGMENT:
+		pipe_config->splitter.link_count = 2;
+		break;
+	case SPLITTER_CONFIGURATION_4_SEGMENT:
+		pipe_config->splitter.link_count = 4;
+		break;
+	}
+
+	pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
+}
+
+void intel_dss_mso_configure(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	u32 dss1 = 0;
+
+	if (!HAS_MSO(i915))
+		return;
+
+	if (crtc_state->splitter.enable) {
+		dss1 |= SPLITTER_ENABLE;
+		dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
+		if (crtc_state->splitter.link_count == 2)
+			dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
+		else
+			dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
+	}
+
+	intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
+		     SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
+		     OVERLAP_PIXELS_MASK, dss1);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h
new file mode 100644
index 000000000000..95302d061205
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dss.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_DSS_H__
+#define __INTEL_DSS_H__
+
+#include "linux/types.h"
+
+struct drm_i915_private;
+struct intel_crtc_state;
+struct intel_encoder;
+
+u8 intel_dss_mso_pipe_mask(struct drm_i915_private *i915);
+void intel_dss_mso_get_config(struct intel_encoder *encoder,
+			      struct intel_crtc_state *pipe_config);
+void intel_dss_mso_configure(const struct intel_crtc_state *crtc_state);
+
+#endif /* __INTEL_DSS_H__ */
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index edfd812e0f41..ff1c0ce6da86 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -228,6 +228,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_dsi.o \
 	i915-display/intel_dsi_dcs_backlight.o \
 	i915-display/intel_dsi_vbt.o \
+	i915-display/intel_dss.o \
 	i915-display/intel_encoder.o \
 	i915-display/intel_fb.o \
 	i915-display/intel_fbc.o \
-- 
2.45.2

[PATCH 04/19] drm/i915/dss: Move to struct intel_display

[Ankit Nautiyal]

Use struct intel_display instead of struct drm_i915_private.

v2: Use struct intel_display for drm Warns. (Jani)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  2 +-
 drivers/gpu/drm/i915/display/intel_dss.c | 22 ++++++++++++----------
 drivers/gpu/drm/i915/display/intel_dss.h |  4 ++--
 3 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7cc766043a5b..aa176f4d42c4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5115,7 +5115,7 @@ void intel_ddi_init(struct intel_display *display,
 		dig_port->hpd_pulse = intel_dp_hpd_pulse;
 
 		if (dig_port->dp.mso_link_count)
-			encoder->pipe_mask = intel_dss_mso_pipe_mask(dev_priv);
+			encoder->pipe_mask = intel_dss_mso_pipe_mask(display);
 	}
 
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c
index e774f55f7008..3f7f416eb3fa 100644
--- a/drivers/gpu/drm/i915/display/intel_dss.c
+++ b/drivers/gpu/drm/i915/display/intel_dss.c
@@ -14,9 +14,11 @@
  * Splitter enable for eDP MSO is limited to certain pipes, on certain
  * platforms.
  */
-u8 intel_dss_mso_pipe_mask(struct drm_i915_private *i915)
+u8 intel_dss_mso_pipe_mask(struct intel_display *display)
 {
-	if (DISPLAY_VER(i915) > 20)
+	struct drm_i915_private *i915 = to_i915(display->drm);
+
+	if (DISPLAY_VER(display) > 20)
 		return ~0;
 	else if (IS_ALDERLAKE_P(i915))
 		return BIT(PIPE_A) | BIT(PIPE_B);
@@ -27,28 +29,28 @@ u8 intel_dss_mso_pipe_mask(struct drm_i915_private *i915)
 void intel_dss_mso_get_config(struct intel_encoder *encoder,
 			      struct intel_crtc_state *pipe_config)
 {
+	struct intel_display *display = to_intel_display(pipe_config);
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	u32 dss1;
 
-	if (!HAS_MSO(i915))
+	if (!HAS_MSO(display))
 		return;
 
-	dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
+	dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
 
 	pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
 	if (!pipe_config->splitter.enable)
 		return;
 
-	if (drm_WARN_ON(&i915->drm, !(intel_dss_mso_pipe_mask(i915) & BIT(pipe)))) {
+	if (drm_WARN_ON(display->drm, !(intel_dss_mso_pipe_mask(display) & BIT(pipe)))) {
 		pipe_config->splitter.enable = false;
 		return;
 	}
 
 	switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
 	default:
-		drm_WARN(&i915->drm, true,
+		drm_WARN(display->drm, true,
 			 "Invalid splitter configuration, dss1=0x%08x\n", dss1);
 		fallthrough;
 	case SPLITTER_CONFIGURATION_2_SEGMENT:
@@ -64,12 +66,12 @@ void intel_dss_mso_get_config(struct intel_encoder *encoder,
 
 void intel_dss_mso_configure(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	u32 dss1 = 0;
 
-	if (!HAS_MSO(i915))
+	if (!HAS_MSO(display))
 		return;
 
 	if (crtc_state->splitter.enable) {
@@ -81,7 +83,7 @@ void intel_dss_mso_configure(const struct intel_crtc_state *crtc_state)
 			dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
 	}
 
-	intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
+	intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe),
 		     SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
 		     OVERLAP_PIXELS_MASK, dss1);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h
index 95302d061205..d4629052979a 100644
--- a/drivers/gpu/drm/i915/display/intel_dss.h
+++ b/drivers/gpu/drm/i915/display/intel_dss.h
@@ -8,11 +8,11 @@
 
 #include "linux/types.h"
 
-struct drm_i915_private;
 struct intel_crtc_state;
+struct intel_display;
 struct intel_encoder;
 
-u8 intel_dss_mso_pipe_mask(struct drm_i915_private *i915);
+u8 intel_dss_mso_pipe_mask(struct intel_display *display);
 void intel_dss_mso_get_config(struct intel_encoder *encoder,
 			      struct intel_crtc_state *pipe_config);
 void intel_dss_mso_configure(const struct intel_crtc_state *crtc_state);
-- 
2.45.2

[PATCH 05/19] drm/i915/icl_dsi: Avoid using intel_dsi in configure_dual_link_mode

[Ankit Nautiyal]

DSS control regs have bits to configure dual_link_mode.
Pass dual_link, and pixel_overlap to the configure_dual_link_mode()
instead of deriving from intel_dsi. This will make the movement of
the function to intel_dss files easier and avoid need of intel_dsi in
intel_dss files.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 5ad5011e1fee..2f94644f51f3 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -275,10 +275,10 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 }
 
 static void configure_dual_link_mode(struct intel_encoder *encoder,
-				     const struct intel_crtc_state *pipe_config)
+				     const struct intel_crtc_state *pipe_config,
+				     u8 dual_link, u8 pixel_overlap)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
 	u32 dss_ctl1;
 
@@ -296,16 +296,16 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
 	dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
 	dss_ctl1 |= SPLITTER_ENABLE;
 	dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
-	dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
+	dss_ctl1 |= OVERLAP_PIXELS(pixel_overlap);
 
-	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+	if (dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 		const struct drm_display_mode *adjusted_mode =
 					&pipe_config->hw.adjusted_mode;
 		u16 hactive = adjusted_mode->crtc_hdisplay;
 		u16 dl_buffer_depth;
 
 		dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
-		dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
+		dl_buffer_depth = hactive / 2 + pixel_overlap;
 
 		if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
 			drm_err(&dev_priv->drm,
@@ -791,7 +791,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 		}
 
 		/* configure stream splitting */
-		configure_dual_link_mode(encoder, pipe_config);
+		configure_dual_link_mode(encoder, pipe_config,
+					 intel_dsi->dual_link,
+					 intel_dsi->pixel_overlap);
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-- 
2.45.2

[PATCH 06/19] drm/i915/icl_dsi: Use intel_display in configure_dual_link_mode

[Ankit Nautiyal]

Replace struct drm_i915_private with struct intel_display in
configure_dual_link_mode.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 2f94644f51f3..79e149d51cb2 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -278,12 +278,12 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
 				     const struct intel_crtc_state *pipe_config,
 				     u8 dual_link, u8 pixel_overlap)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
 	u32 dss_ctl1;
 
 	/* FIXME: Move all DSS handling to intel_vdsc.c */
-	if (DISPLAY_VER(dev_priv) >= 12) {
+	if (DISPLAY_VER(display) >= 12) {
 		struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 
 		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
@@ -293,7 +293,7 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
 		dss_ctl2_reg = DSS_CTL2;
 	}
 
-	dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
+	dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
 	dss_ctl1 |= SPLITTER_ENABLE;
 	dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
 	dss_ctl1 |= OVERLAP_PIXELS(pixel_overlap);
@@ -308,19 +308,19 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
 		dl_buffer_depth = hactive / 2 + pixel_overlap;
 
 		if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
-			drm_err(&dev_priv->drm,
+			drm_err(display->drm,
 				"DL buffer depth exceed max value\n");
 
 		dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
 		dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
-		intel_de_rmw(dev_priv, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
+		intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
 			     RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
 	} else {
 		/* Interleave */
 		dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
 	}
 
-	intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1);
+	intel_de_write(display, dss_ctl1_reg, dss_ctl1);
 }
 
 /* aka DSI 8X clock */
-- 
2.45.2

[PATCH 07/19] drm/i915/icl_dsi: Move helpers to configure dsi dual link to intel_dss

[Ankit Nautiyal]

Move the function to configure dss_ctl for dual_link dsi to intel_dss
files. While at it, use struct intel_display wherever possible.

v2: Avoid modifying the code while movement. (Jani)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c   | 57 ++----------------------
 drivers/gpu/drm/i915/display/intel_dss.c | 50 +++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dss.h |  3 ++
 3 files changed, 57 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 79e149d51cb2..ec880d1cbbee 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -44,7 +44,7 @@
 #include "intel_de.h"
 #include "intel_dsi.h"
 #include "intel_dsi_vbt.h"
-#include "intel_dss_regs.h"
+#include "intel_dss.h"
 #include "intel_panel.h"
 #include "intel_vdsc.h"
 #include "skl_scaler.h"
@@ -274,55 +274,6 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 	}
 }
 
-static void configure_dual_link_mode(struct intel_encoder *encoder,
-				     const struct intel_crtc_state *pipe_config,
-				     u8 dual_link, u8 pixel_overlap)
-{
-	struct intel_display *display = to_intel_display(encoder);
-	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
-	u32 dss_ctl1;
-
-	/* FIXME: Move all DSS handling to intel_vdsc.c */
-	if (DISPLAY_VER(display) >= 12) {
-		struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
-
-		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
-		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
-	} else {
-		dss_ctl1_reg = DSS_CTL1;
-		dss_ctl2_reg = DSS_CTL2;
-	}
-
-	dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
-	dss_ctl1 |= SPLITTER_ENABLE;
-	dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
-	dss_ctl1 |= OVERLAP_PIXELS(pixel_overlap);
-
-	if (dual_link == DSI_DUAL_LINK_FRONT_BACK) {
-		const struct drm_display_mode *adjusted_mode =
-					&pipe_config->hw.adjusted_mode;
-		u16 hactive = adjusted_mode->crtc_hdisplay;
-		u16 dl_buffer_depth;
-
-		dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
-		dl_buffer_depth = hactive / 2 + pixel_overlap;
-
-		if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
-			drm_err(display->drm,
-				"DL buffer depth exceed max value\n");
-
-		dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
-		dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
-		intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
-			     RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
-	} else {
-		/* Interleave */
-		dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
-	}
-
-	intel_de_write(display, dss_ctl1_reg, dss_ctl1);
-}
-
 /* aka DSI 8X clock */
 static int afe_clk(struct intel_encoder *encoder,
 		   const struct intel_crtc_state *crtc_state)
@@ -791,9 +742,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 		}
 
 		/* configure stream splitting */
-		configure_dual_link_mode(encoder, pipe_config,
-					 intel_dsi->dual_link,
-					 intel_dsi->pixel_overlap);
+		intel_dss_dsi_dual_link_mode_configure(encoder, pipe_config,
+						       intel_dsi->dual_link,
+						       intel_dsi->pixel_overlap);
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c
index 3f7f416eb3fa..969e32143983 100644
--- a/drivers/gpu/drm/i915/display/intel_dss.c
+++ b/drivers/gpu/drm/i915/display/intel_dss.c
@@ -7,6 +7,7 @@
 #include "i915_reg_defs.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
+#include "intel_dsi.h"
 #include "intel_dss.h"
 #include "intel_dss_regs.h"
 
@@ -87,3 +88,52 @@ void intel_dss_mso_configure(const struct intel_crtc_state *crtc_state)
 		     SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
 		     OVERLAP_PIXELS_MASK, dss1);
 }
+
+void intel_dss_dsi_dual_link_mode_configure(struct intel_encoder *encoder,
+					    const struct intel_crtc_state *pipe_config,
+					    u8 dual_link,
+					    u8 pixel_overlap)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+	u32 dss_ctl1;
+
+	if (DISPLAY_VER(display) >= 12) {
+		struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+
+		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
+		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
+	} else {
+		dss_ctl1_reg = DSS_CTL1;
+		dss_ctl2_reg = DSS_CTL2;
+	}
+
+	dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
+	dss_ctl1 |= SPLITTER_ENABLE;
+	dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
+	dss_ctl1 |= OVERLAP_PIXELS(pixel_overlap);
+
+	if (dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+		const struct drm_display_mode *adjusted_mode =
+					&pipe_config->hw.adjusted_mode;
+		u16 hactive = adjusted_mode->crtc_hdisplay;
+		u16 dl_buffer_depth;
+
+		dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
+		dl_buffer_depth = hactive / 2 + pixel_overlap;
+
+		if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
+			drm_err(display->drm,
+				"DL buffer depth exceed max value\n");
+
+		dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
+		dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
+		intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
+			     RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
+	} else {
+		/* Interleave */
+		dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
+	}
+
+	intel_de_write(display, dss_ctl1_reg, dss_ctl1);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h
index d4629052979a..aa8c67c15855 100644
--- a/drivers/gpu/drm/i915/display/intel_dss.h
+++ b/drivers/gpu/drm/i915/display/intel_dss.h
@@ -16,5 +16,8 @@ u8 intel_dss_mso_pipe_mask(struct intel_display *display);
 void intel_dss_mso_get_config(struct intel_encoder *encoder,
 			      struct intel_crtc_state *pipe_config);
 void intel_dss_mso_configure(const struct intel_crtc_state *crtc_state);
+void intel_dss_dsi_dual_link_mode_configure(struct intel_encoder *encoder,
+					    const struct intel_crtc_state *pipe_config,
+					    u8 dual_link, u8 pixel_overlap);
 
 #endif /* __INTEL_DSS_H__ */
-- 
2.45.2

[PATCH 08/19] drm/i915/vdsc: Rename helper to check if the pipe supports dsc

[Ankit Nautiyal]

Rename the helper is_pipe_dsc to intel_dsc_is_pipe_dsc to prepare for its
future use across multiple files. This change is a preliminary step towards
making the function non-static, enhancing its accessibility and
reusability.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 891346f1f09a..6d60b72a9dfb 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -35,7 +35,7 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
 	return true;
 }
 
-static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
+static bool intel_dsc_is_dsc_pipe(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 {
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
@@ -366,7 +366,7 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 	 */
 	if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
 		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
-	else if (is_pipe_dsc(crtc, cpu_transcoder))
+	else if (intel_dsc_is_dsc_pipe(crtc, cpu_transcoder))
 		return POWER_DOMAIN_PIPE(pipe);
 	else
 		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
@@ -395,7 +395,7 @@ static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int
 	enum pipe pipe = crtc->pipe;
 	bool pipe_dsc;
 
-	pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
+	pipe_dsc = intel_dsc_is_dsc_pipe(crtc, cpu_transcoder);
 
 	if (dsc_reg_num >= 3)
 		MISSING_CASE(dsc_reg_num);
@@ -538,7 +538,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		rc_buf_thresh_dword[i / 4] |=
 			(u32)(vdsc_cfg->rc_buf_thresh[i] <<
 			      BITS_PER_BYTE * (i % 4));
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+	if (!intel_dsc_is_dsc_pipe(crtc, cpu_transcoder)) {
 		intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
 			       rc_buf_thresh_dword[0]);
 		intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
@@ -592,7 +592,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 				RC_MAX_QP_SHIFT) |
 			       (vdsc_cfg->rc_range_params[i].range_min_qp <<
 				RC_MIN_QP_SHIFT)) << 16 * (i % 2));
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+	if (!intel_dsc_is_dsc_pipe(crtc, cpu_transcoder)) {
 		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
 			       rc_range_params_dword[0]);
 		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,
@@ -726,13 +726,13 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
 
 static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 {
-	return is_pipe_dsc(crtc, cpu_transcoder) ?
+	return intel_dsc_is_dsc_pipe(crtc, cpu_transcoder) ?
 		ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1;
 }
 
 static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 {
-	return is_pipe_dsc(crtc, cpu_transcoder) ?
+	return intel_dsc_is_dsc_pipe(crtc, cpu_transcoder) ?
 		ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2;
 }
 
-- 
2.45.2

[PATCH 09/19] drm/i915/vdsc: Move all dss stuff in dss files

[Ankit Nautiyal]

Move helpers to configure dss for compressed and uncompressed joiner to
intel_dss files. While at it, replace struct drm_i915_private to struct
intel_display wherever possible.

v2:
-Move modification to use struct intel_display to another patch. (Jani)
-Tweak the name for helper to get_config helper. (Jani)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  3 +-
 drivers/gpu/drm/i915/display/intel_dss.c     | 80 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dss.h     |  5 ++
 drivers/gpu/drm/i915/display/intel_vdsc.c    | 67 ++--------------
 drivers/gpu/drm/i915/display/intel_vdsc.h    |  2 +-
 5 files changed, 94 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3cb960ca6eda..9bcbb9c923a9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -87,6 +87,7 @@
 #include "intel_drrs.h"
 #include "intel_dsb.h"
 #include "intel_dsi.h"
+#include "intel_dss.h"
 #include "intel_dss_regs.h"
 #include "intel_dvo.h"
 #include "intel_fb.h"
@@ -1711,7 +1712,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
 		intel_dsc_enable(pipe_crtc_state);
 
 		if (DISPLAY_VER(dev_priv) >= 13)
-			intel_uncompressed_joiner_enable(pipe_crtc_state);
+			intel_dss_enable_uncompressed_joiner(pipe_crtc_state);
 
 		intel_set_pipe_src_size(pipe_crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c
index 969e32143983..b37e9112ab77 100644
--- a/drivers/gpu/drm/i915/display/intel_dss.c
+++ b/drivers/gpu/drm/i915/display/intel_dss.c
@@ -6,10 +6,12 @@
 #include "i915_drv.h"
 #include "i915_reg_defs.h"
 #include "intel_de.h"
+#include "intel_display_limits.h"
 #include "intel_display_types.h"
 #include "intel_dsi.h"
 #include "intel_dss.h"
 #include "intel_dss_regs.h"
+#include "intel_vdsc.h"
 
 /*
  * Splitter enable for eDP MSO is limited to certain pipes, on certain
@@ -137,3 +139,81 @@ void intel_dss_dsi_dual_link_mode_configure(struct intel_encoder *encoder,
 
 	intel_de_write(display, dss_ctl1_reg, dss_ctl1);
 }
+
+static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
+{
+	return intel_dsc_is_dsc_pipe(crtc, cpu_transcoder) ?
+		ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1;
+}
+
+static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
+{
+	return intel_dsc_is_dsc_pipe(crtc, cpu_transcoder) ?
+		ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2;
+}
+
+void intel_dss_reset(const struct intel_crtc_state *old_crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+	intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
+	intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
+}
+
+void intel_dss_enable_uncompressed_joiner(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	u32 dss_ctl1_val = 0;
+
+	if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {
+		if (intel_crtc_is_joiner_secondary(crtc_state))
+			dss_ctl1_val |= UNCOMPRESSED_JOINER_SECONDARY;
+		else
+			dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
+
+		intel_de_write(dev_priv,
+			       dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),
+			       dss_ctl1_val);
+	}
+}
+
+void intel_dss_enable_compressed_joiner(const struct intel_crtc_state *crtc_state,
+					int vdsc_instances_per_pipe)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	u32 dss_ctl1_val = 0;
+	u32 dss_ctl2_val = 0;
+
+	dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
+	if (vdsc_instances_per_pipe > 1) {
+		dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
+		dss_ctl1_val |= JOINER_ENABLE;
+	}
+	if (crtc_state->joiner_pipes) {
+		dss_ctl1_val |= BIG_JOINER_ENABLE;
+		if (!intel_crtc_is_joiner_secondary(crtc_state))
+			dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
+	}
+	intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
+	intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
+}
+
+void intel_dss_dsc_get_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	u32 dss_ctl1, dss_ctl2;
+
+	dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder));
+	dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder));
+
+	crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
+	if (!crtc_state->dsc.compression_enable)
+		return;
+
+	crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
+				    (dss_ctl1 & JOINER_ENABLE);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h
index aa8c67c15855..2d06bbe52687 100644
--- a/drivers/gpu/drm/i915/display/intel_dss.h
+++ b/drivers/gpu/drm/i915/display/intel_dss.h
@@ -19,5 +19,10 @@ void intel_dss_mso_configure(const struct intel_crtc_state *crtc_state);
 void intel_dss_dsi_dual_link_mode_configure(struct intel_encoder *encoder,
 					    const struct intel_crtc_state *pipe_config,
 					    u8 dual_link, u8 pixel_overlap);
+void intel_dss_reset(const struct intel_crtc_state *old_crtc_state);
+void intel_dss_enable_uncompressed_joiner(const struct intel_crtc_state *crtc_state);
+void intel_dss_enable_compressed_joiner(const struct intel_crtc_state *crtc_state,
+					int vdsc_instances_per_pipe);
+void intel_dss_dsc_get_config(struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_DSS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 6d60b72a9dfb..7e7c7694e56f 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -15,7 +15,7 @@
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_dsi.h"
-#include "intel_dss_regs.h"
+#include "intel_dss.h"
 #include "intel_qp_tables.h"
 #include "intel_vdsc.h"
 #include "intel_vdsc_regs.h"
@@ -35,7 +35,7 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
 	return true;
 }
 
-static bool intel_dsc_is_dsc_pipe(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
+bool intel_dsc_is_dsc_pipe(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 {
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
@@ -724,72 +724,23 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
 				  sizeof(dp_dsc_pps_sdp));
 }
 
-static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
-{
-	return intel_dsc_is_dsc_pipe(crtc, cpu_transcoder) ?
-		ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1;
-}
-
-static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
-{
-	return intel_dsc_is_dsc_pipe(crtc, cpu_transcoder) ?
-		ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2;
-}
-
-void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 dss_ctl1_val = 0;
-
-	if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {
-		if (intel_crtc_is_joiner_secondary(crtc_state))
-			dss_ctl1_val |= UNCOMPRESSED_JOINER_SECONDARY;
-		else
-			dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
-
-		intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
-	}
-}
-
 void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 dss_ctl1_val = 0;
-	u32 dss_ctl2_val = 0;
 	int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
 
 	if (!crtc_state->dsc.compression_enable)
 		return;
 
 	intel_dsc_pps_configure(crtc_state);
-
-	dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
-	if (vdsc_instances_per_pipe > 1) {
-		dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
-		dss_ctl1_val |= JOINER_ENABLE;
-	}
-	if (crtc_state->joiner_pipes) {
-		dss_ctl1_val |= BIG_JOINER_ENABLE;
-		if (!intel_crtc_is_joiner_secondary(crtc_state))
-			dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
-	}
-	intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
-	intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
+	intel_dss_enable_compressed_joiner(crtc_state, vdsc_instances_per_pipe);
 }
 
 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-
 	/* Disable only if either of them is enabled */
 	if (old_crtc_state->dsc.compression_enable ||
-	    old_crtc_state->joiner_pipes) {
-		intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
-		intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
-	}
+	    old_crtc_state->joiner_pipes)
+		intel_dss_reset(old_crtc_state);
 }
 
 static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
@@ -946,7 +897,6 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	enum intel_display_power_domain power_domain;
 	intel_wakeref_t wakeref;
-	u32 dss_ctl1, dss_ctl2;
 
 	if (!intel_dsc_source_support(crtc_state))
 		return;
@@ -957,16 +907,11 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	if (!wakeref)
 		return;
 
-	dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
-	dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));
+	intel_dss_dsc_get_config(crtc_state);
 
-	crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
 	if (!crtc_state->dsc.compression_enable)
 		goto out;
 
-	crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
-		(dss_ctl1 & JOINER_ENABLE);
-
 	intel_dsc_get_pps_config(crtc_state);
 out:
 	intel_display_power_put(dev_priv, power_domain, wakeref);
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 290b2e9b3482..345956d0c77e 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -16,7 +16,6 @@ struct intel_crtc_state;
 struct intel_encoder;
 
 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
-void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state);
 void intel_dsc_enable(const struct intel_crtc_state *crtc_state);
 void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config);
@@ -31,5 +30,6 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
 			    const struct intel_crtc_state *crtc_state);
 void intel_vdsc_state_dump(struct drm_printer *p, int indent,
 			   const struct intel_crtc_state *crtc_state);
+bool intel_dsc_is_dsc_pipe(struct intel_crtc *crtc, enum transcoder cpu_transcoder);
 
 #endif /* __INTEL_VDSC_H__ */
-- 
2.45.2

[PATCH 10/19] drm/i915/dss: Use struct intel_display in dss dsc helpers

[Ankit Nautiyal]

Replace struct drm_i915_private with intel_display in the dss dsc
helpers.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dss.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c
index b37e9112ab77..fe55f4b1a9bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dss.c
+++ b/drivers/gpu/drm/i915/display/intel_dss.c
@@ -154,17 +154,17 @@ static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_tran
 
 void intel_dss_reset(const struct intel_crtc_state *old_crtc_state)
 {
+	struct intel_display *display = to_intel_display(old_crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
-	intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
+	intel_de_write(display, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
+	intel_de_write(display, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
 }
 
 void intel_dss_enable_uncompressed_joiner(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 dss_ctl1_val = 0;
 
 	if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {
@@ -173,7 +173,7 @@ void intel_dss_enable_uncompressed_joiner(const struct intel_crtc_state *crtc_st
 		else
 			dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
 
-		intel_de_write(dev_priv,
+		intel_de_write(display,
 			       dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),
 			       dss_ctl1_val);
 	}
@@ -182,8 +182,8 @@ void intel_dss_enable_uncompressed_joiner(const struct intel_crtc_state *crtc_st
 void intel_dss_enable_compressed_joiner(const struct intel_crtc_state *crtc_state,
 					int vdsc_instances_per_pipe)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 dss_ctl1_val = 0;
 	u32 dss_ctl2_val = 0;
 
@@ -197,18 +197,18 @@ void intel_dss_enable_compressed_joiner(const struct intel_crtc_state *crtc_stat
 		if (!intel_crtc_is_joiner_secondary(crtc_state))
 			dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
 	}
-	intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
-	intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
+	intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
+	intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
 }
 
 void intel_dss_dsc_get_config(struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 dss_ctl1, dss_ctl2;
 
-	dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder));
-	dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder));
+	dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder));
+	dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder));
 
 	crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
 	if (!crtc_state->dsc.compression_enable)
-- 
2.45.2

[PATCH 11/19] drm/i915/display: Move dss stuff in intel_dss files

[Ankit Nautiyal]

Move helper to retrieve the compressed and uncompressed joiner pipes from
dss ctl to intel_dss files.

v2: Derive intel_display from crtc. (Jani)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 34 +++-----------
 drivers/gpu/drm/i915/display/intel_dss.c     | 48 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dss.h     |  7 +++
 3 files changed, 61 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9bcbb9c923a9..7b407ebccd54 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3545,35 +3545,13 @@ static void enabled_joiner_pipes(struct drm_i915_private *dev_priv,
 
 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
 					 joiner_pipes(dev_priv)) {
-		enum intel_display_power_domain power_domain;
-		enum pipe pipe = crtc->pipe;
-		intel_wakeref_t wakeref;
-
-		power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);
-		with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
-			u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
+		intel_dss_get_compressed_joiner_pipes(crtc,
+						      primary_pipes,
+						      secondary_pipes);
 
-			if (!(tmp & BIG_JOINER_ENABLE))
-				continue;
-
-			if (tmp & PRIMARY_BIG_JOINER_ENABLE)
-				*primary_pipes |= BIT(pipe);
-			else
-				*secondary_pipes |= BIT(pipe);
-		}
-
-		if (DISPLAY_VER(dev_priv) < 13)
-			continue;
-
-		power_domain = POWER_DOMAIN_PIPE(pipe);
-		with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
-			u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
-
-			if (tmp & UNCOMPRESSED_JOINER_PRIMARY)
-				*primary_pipes |= BIT(pipe);
-			if (tmp & UNCOMPRESSED_JOINER_SECONDARY)
-				*secondary_pipes |= BIT(pipe);
-		}
+		intel_dss_get_uncompressed_joiner_pipes(crtc,
+							primary_pipes,
+							secondary_pipes);
 	}
 
 	/* Joiner pipes should always be consecutive primary and secondary */
diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c
index fe55f4b1a9bf..01303feadcef 100644
--- a/drivers/gpu/drm/i915/display/intel_dss.c
+++ b/drivers/gpu/drm/i915/display/intel_dss.c
@@ -217,3 +217,51 @@ void intel_dss_dsc_get_config(struct intel_crtc_state *crtc_state)
 	crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
 				    (dss_ctl1 & JOINER_ENABLE);
 }
+
+void intel_dss_get_compressed_joiner_pipes(struct intel_crtc *crtc,
+					   u8 *primary_pipes,
+					   u8 *secondary_pipes)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct drm_i915_private *i915 = to_i915(display->drm);
+	enum intel_display_power_domain power_domain;
+	enum pipe pipe = crtc->pipe;
+	intel_wakeref_t wakeref;
+
+	power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);
+	with_intel_display_power_if_enabled(i915, power_domain, wakeref) {
+		u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
+
+		if (!(tmp & BIG_JOINER_ENABLE))
+			continue;
+
+		if (tmp & PRIMARY_BIG_JOINER_ENABLE)
+			*primary_pipes |= BIT(pipe);
+		else
+			*secondary_pipes |= BIT(pipe);
+	}
+}
+
+void intel_dss_get_uncompressed_joiner_pipes(struct intel_crtc *crtc,
+					     u8 *primary_pipes,
+					     u8 *secondary_pipes)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct drm_i915_private *i915 = to_i915(display->drm);
+	enum intel_display_power_domain power_domain;
+	enum pipe pipe = crtc->pipe;
+	intel_wakeref_t wakeref;
+
+	if (DISPLAY_VER(display) < 13)
+		return;
+
+	power_domain = POWER_DOMAIN_PIPE(pipe);
+	with_intel_display_power_if_enabled(i915, power_domain, wakeref) {
+		u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
+
+		if (tmp & UNCOMPRESSED_JOINER_PRIMARY)
+			*primary_pipes |= BIT(pipe);
+		if (tmp & UNCOMPRESSED_JOINER_SECONDARY)
+			*secondary_pipes |= BIT(pipe);
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h
index 2d06bbe52687..9a63e18cce2e 100644
--- a/drivers/gpu/drm/i915/display/intel_dss.h
+++ b/drivers/gpu/drm/i915/display/intel_dss.h
@@ -11,6 +11,7 @@
 struct intel_crtc_state;
 struct intel_display;
 struct intel_encoder;
+struct intel_crtc;
 
 u8 intel_dss_mso_pipe_mask(struct intel_display *display);
 void intel_dss_mso_get_config(struct intel_encoder *encoder,
@@ -24,5 +25,11 @@ void intel_dss_enable_uncompressed_joiner(const struct intel_crtc_state *crtc_st
 void intel_dss_enable_compressed_joiner(const struct intel_crtc_state *crtc_state,
 					int vdsc_instances_per_pipe);
 void intel_dss_dsc_get_config(struct intel_crtc_state *crtc_state);
+void intel_dss_get_compressed_joiner_pipes(struct intel_crtc *crtc,
+					   u8 *primary_pipes,
+					   u8 *secondary_pipes);
+void intel_dss_get_uncompressed_joiner_pipes(struct intel_crtc *crtc,
+					     u8 *primary_pipes,
+					     u8 *secondary_pipes);
 
 #endif /* __INTEL_DSS_H__ */
-- 
2.45.2

[PATCH 12/19] drm/i915/display: Rename static functions that use joiner

[Ankit Nautiyal]

At the moment, many functions that are concerned with joiner have
different prefixes. Rename the static functions, to have a prefix
'intel_joiner'. This will make the movement of these helpers to a
separate file for pipe joiner.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 56 +++++++++++---------
 1 file changed, 30 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7b407ebccd54..ad72691b47b2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -249,7 +249,7 @@ is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 		is_trans_port_sync_slave(crtc_state);
 }
 
-static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state)
+static enum pipe intel_joiner_get_primary_pipe(const struct intel_crtc_state *crtc_state)
 {
 	return ffs(crtc_state->joiner_pipes) - 1;
 }
@@ -257,7 +257,7 @@ static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state)
 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
 {
 	if (crtc_state->joiner_pipes)
-		return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state));
+		return crtc_state->joiner_pipes & ~BIT(intel_joiner_get_primary_pipe(crtc_state));
 	else
 		return 0;
 }
@@ -267,7 +267,7 @@ bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	return crtc_state->joiner_pipes &&
-		crtc->pipe != joiner_primary_pipe(crtc_state);
+		crtc->pipe != intel_joiner_get_primary_pipe(crtc_state);
 }
 
 bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)
@@ -275,10 +275,10 @@ bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	return crtc_state->joiner_pipes &&
-		crtc->pipe == joiner_primary_pipe(crtc_state);
+		crtc->pipe == intel_joiner_get_primary_pipe(crtc_state);
 }
 
-static int intel_joiner_num_pipes(const struct intel_crtc_state *crtc_state)
+static int intel_joiner_get_num_pipes(const struct intel_crtc_state *crtc_state)
 {
 	return hweight8(crtc_state->joiner_pipes);
 }
@@ -295,7 +295,7 @@ struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
 	if (intel_crtc_is_joiner_secondary(crtc_state))
-		return intel_crtc_for_pipe(i915, joiner_primary_pipe(crtc_state));
+		return intel_crtc_for_pipe(i915, intel_joiner_get_primary_pipe(crtc_state));
 	else
 		return to_intel_crtc(crtc_state->uapi.crtc);
 }
@@ -2344,7 +2344,7 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
 static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,
 					struct drm_display_mode *mode)
 {
-	int num_pipes = intel_joiner_num_pipes(crtc_state);
+	int num_pipes = intel_joiner_get_num_pipes(crtc_state);
 
 	if (num_pipes < 2)
 		return;
@@ -2408,7 +2408,7 @@ static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state
 	drm_mode_copy(mode, pipe_mode);
 	intel_mode_from_crtc_timings(mode, mode);
 	mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
-		(intel_joiner_num_pipes(crtc_state) ?: 1);
+		(intel_joiner_get_num_pipes(crtc_state) ?: 1);
 	mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
 
 	/* Derive per-pipe timings in case joiner is used */
@@ -2428,7 +2428,7 @@ void intel_encoder_get_config(struct intel_encoder *encoder,
 
 static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
 {
-	int num_pipes = intel_joiner_num_pipes(crtc_state);
+	int num_pipes = intel_joiner_get_num_pipes(crtc_state);
 	int width, height;
 
 	if (num_pipes < 2)
@@ -2888,14 +2888,14 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	int num_pipes = intel_joiner_num_pipes(crtc_state);
+	int num_pipes = intel_joiner_get_num_pipes(crtc_state);
 	enum pipe primary_pipe, pipe = crtc->pipe;
 	int width;
 
 	if (num_pipes < 2)
 		return;
 
-	primary_pipe = joiner_primary_pipe(crtc_state);
+	primary_pipe = intel_joiner_get_primary_pipe(crtc_state);
 	width = drm_rect_width(&crtc_state->pipe_src);
 
 	drm_rect_translate_to(&crtc_state->pipe_src,
@@ -3505,7 +3505,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
 	return ret;
 }
 
-static u8 joiner_pipes(struct drm_i915_private *i915)
+static u8 intel_joiner_supported_pipes(struct drm_i915_private *i915)
 {
 	u8 pipes;
 
@@ -3535,8 +3535,8 @@ static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
 	return tmp & TRANS_DDI_FUNC_ENABLE;
 }
 
-static void enabled_joiner_pipes(struct drm_i915_private *dev_priv,
-				 u8 *primary_pipes, u8 *secondary_pipes)
+static void intel_joiner_enabled_pipes(struct drm_i915_private *dev_priv,
+				       u8 *primary_pipes, u8 *secondary_pipes)
 {
 	struct intel_crtc *crtc;
 
@@ -3544,7 +3544,7 @@ static void enabled_joiner_pipes(struct drm_i915_private *dev_priv,
 	*secondary_pipes = 0;
 
 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
-					 joiner_pipes(dev_priv)) {
+					 intel_joiner_supported_pipes(dev_priv)) {
 		intel_dss_get_compressed_joiner_pipes(crtc,
 						      primary_pipes,
 						      secondary_pipes);
@@ -3560,7 +3560,9 @@ static void enabled_joiner_pipes(struct drm_i915_private *dev_priv,
 		 *primary_pipes, *secondary_pipes);
 }
 
-static enum pipe get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes)
+static enum pipe intel_joiner_find_primary_pipe(enum pipe pipe,
+						u8 primary_pipes,
+						u8 secondary_pipes)
 {
 	if ((secondary_pipes & BIT(pipe)) == 0)
 		return pipe;
@@ -3572,11 +3574,13 @@ static enum pipe get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes, u8 se
 	return fls(primary_pipes) - 1;
 }
 
-static u8 get_joiner_secondary_pipes(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes)
+static u8 intel_joiner_find_secondary_pipes(enum pipe pipe,
+					    u8 primary_pipes,
+					    u8 secondary_pipes)
 {
 	enum pipe primary_pipe, next_primary_pipe;
 
-	primary_pipe = get_joiner_primary_pipe(pipe, primary_pipes, secondary_pipes);
+	primary_pipe = intel_joiner_find_primary_pipe(pipe, primary_pipes, secondary_pipes);
 
 	if ((primary_pipes & BIT(primary_pipe)) == 0)
 		return 0;
@@ -3660,10 +3664,10 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
 		enabled_transcoders |= BIT(cpu_transcoder);
 
 	/* joiner secondary -> consider the primary pipe's transcoder as well */
-	enabled_joiner_pipes(dev_priv, &primary_pipes, &secondary_pipes);
+	intel_joiner_enabled_pipes(dev_priv, &primary_pipes, &secondary_pipes);
 	if (secondary_pipes & BIT(crtc->pipe)) {
 		cpu_transcoder = (enum transcoder)
-			get_joiner_primary_pipe(crtc->pipe, primary_pipes, secondary_pipes);
+			intel_joiner_find_primary_pipe(crtc->pipe, primary_pipes, secondary_pipes);
 		if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
 			enabled_transcoders |= BIT(cpu_transcoder);
 	}
@@ -3797,14 +3801,14 @@ static void intel_joiner_get_config(struct intel_crtc_state *crtc_state)
 	u8 primary_pipes, secondary_pipes;
 	enum pipe pipe = crtc->pipe;
 
-	enabled_joiner_pipes(i915, &primary_pipes, &secondary_pipes);
+	intel_joiner_enabled_pipes(i915, &primary_pipes, &secondary_pipes);
 
 	if (((primary_pipes | secondary_pipes) & BIT(pipe)) == 0)
 		return;
 
 	crtc_state->joiner_pipes =
-		BIT(get_joiner_primary_pipe(pipe, primary_pipes, secondary_pipes)) |
-		get_joiner_secondary_pipes(pipe, primary_pipes, secondary_pipes);
+		BIT(intel_joiner_find_primary_pipe(pipe, primary_pipes, secondary_pipes)) |
+		intel_joiner_find_secondary_pipes(pipe, primary_pipes, secondary_pipes);
 }
 
 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
@@ -5987,15 +5991,15 @@ static int intel_atomic_check_joiner(struct intel_atomic_state *state,
 
 	/* sanity check */
 	if (drm_WARN_ON(&i915->drm,
-			primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state)))
+			primary_crtc->pipe != intel_joiner_get_primary_pipe(primary_crtc_state)))
 		return -EINVAL;
 
-	if (primary_crtc_state->joiner_pipes & ~joiner_pipes(i915)) {
+	if (primary_crtc_state->joiner_pipes & ~intel_joiner_supported_pipes(i915)) {
 		drm_dbg_kms(&i915->drm,
 			    "[CRTC:%d:%s] Cannot act as joiner primary "
 			    "(need 0x%x as pipes, only 0x%x possible)\n",
 			    primary_crtc->base.base.id, primary_crtc->base.name,
-			    primary_crtc_state->joiner_pipes, joiner_pipes(i915));
+			    primary_crtc_state->joiner_pipes, intel_joiner_supported_pipes(i915));
 		return -EINVAL;
 	}
 
-- 
2.45.2

[PATCH 13/19] drm/i915/display: Separate out joiner stuff in a new file

[Ankit Nautiyal]

Move all the static functions intel_joiner* to the new file
intel_joiner.c.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/Makefile                |   1 +
 drivers/gpu/drm/i915/display/intel_display.c | 234 +------------------
 drivers/gpu/drm/i915/display/intel_display.h |   5 +
 drivers/gpu/drm/i915/display/intel_joiner.c  | 233 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_joiner.h  |  32 +++
 drivers/gpu/drm/xe/Makefile                  |   1 +
 6 files changed, 278 insertions(+), 228 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_joiner.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_joiner.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e55ce8ba123c..c337385bbe7d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -333,6 +333,7 @@ i915-y += \
 	display/intel_encoder.o \
 	display/intel_gmbus.o \
 	display/intel_hdmi.o \
+	display/intel_joiner.o \
 	display/intel_lspcon.o \
 	display/intel_lvds.o \
 	display/intel_panel.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ad72691b47b2..9af3ea6c7642 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -97,6 +97,7 @@
 #include "intel_frontbuffer.h"
 #include "intel_hdmi.h"
 #include "intel_hotplug.h"
+#include "intel_joiner.h"
 #include "intel_link_bw.h"
 #include "intel_lvds.h"
 #include "intel_lvds_regs.h"
@@ -249,11 +250,6 @@ is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 		is_trans_port_sync_slave(crtc_state);
 }
 
-static enum pipe intel_joiner_get_primary_pipe(const struct intel_crtc_state *crtc_state)
-{
-	return ffs(crtc_state->joiner_pipes) - 1;
-}
-
 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
 {
 	if (crtc_state->joiner_pipes)
@@ -278,11 +274,6 @@ bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)
 		crtc->pipe == intel_joiner_get_primary_pipe(crtc_state);
 }
 
-static int intel_joiner_get_num_pipes(const struct intel_crtc_state *crtc_state)
-{
-	return hweight8(crtc_state->joiner_pipes);
-}
-
 u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -2341,23 +2332,6 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
 			ilk_pipe_pixel_rate(crtc_state);
 }
 
-static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,
-					struct drm_display_mode *mode)
-{
-	int num_pipes = intel_joiner_get_num_pipes(crtc_state);
-
-	if (num_pipes < 2)
-		return;
-
-	mode->crtc_clock /= num_pipes;
-	mode->crtc_hdisplay /= num_pipes;
-	mode->crtc_hblank_start /= num_pipes;
-	mode->crtc_hblank_end /= num_pipes;
-	mode->crtc_hsync_start /= num_pipes;
-	mode->crtc_hsync_end /= num_pipes;
-	mode->crtc_htotal /= num_pipes;
-}
-
 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
 					  struct drm_display_mode *mode)
 {
@@ -2426,21 +2400,6 @@ void intel_encoder_get_config(struct intel_encoder *encoder,
 	intel_crtc_readout_derived_state(crtc_state);
 }
 
-static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
-{
-	int num_pipes = intel_joiner_get_num_pipes(crtc_state);
-	int width, height;
-
-	if (num_pipes < 2)
-		return;
-
-	width = drm_rect_width(&crtc_state->pipe_src);
-	height = drm_rect_height(&crtc_state->pipe_src);
-
-	drm_rect_init(&crtc_state->pipe_src, 0, 0,
-		      width / num_pipes, height);
-}
-
 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -2885,23 +2844,6 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 				      TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder));
 }
 
-static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	int num_pipes = intel_joiner_get_num_pipes(crtc_state);
-	enum pipe primary_pipe, pipe = crtc->pipe;
-	int width;
-
-	if (num_pipes < 2)
-		return;
-
-	primary_pipe = intel_joiner_get_primary_pipe(crtc_state);
-	width = drm_rect_width(&crtc_state->pipe_src);
-
-	drm_rect_translate_to(&crtc_state->pipe_src,
-			      (pipe - primary_pipe) * width, 0);
-}
-
 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
 				    struct intel_crtc_state *pipe_config)
 {
@@ -3505,20 +3447,6 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
 	return ret;
 }
 
-static u8 intel_joiner_supported_pipes(struct drm_i915_private *i915)
-{
-	u8 pipes;
-
-	if (DISPLAY_VER(i915) >= 12)
-		pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
-	else if (DISPLAY_VER(i915) >= 11)
-		pipes = BIT(PIPE_B) | BIT(PIPE_C);
-	else
-		pipes = 0;
-
-	return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
-}
-
 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
 					   enum transcoder cpu_transcoder)
 {
@@ -3535,66 +3463,6 @@ static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
 	return tmp & TRANS_DDI_FUNC_ENABLE;
 }
 
-static void intel_joiner_enabled_pipes(struct drm_i915_private *dev_priv,
-				       u8 *primary_pipes, u8 *secondary_pipes)
-{
-	struct intel_crtc *crtc;
-
-	*primary_pipes = 0;
-	*secondary_pipes = 0;
-
-	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
-					 intel_joiner_supported_pipes(dev_priv)) {
-		intel_dss_get_compressed_joiner_pipes(crtc,
-						      primary_pipes,
-						      secondary_pipes);
-
-		intel_dss_get_uncompressed_joiner_pipes(crtc,
-							primary_pipes,
-							secondary_pipes);
-	}
-
-	/* Joiner pipes should always be consecutive primary and secondary */
-	drm_WARN(&dev_priv->drm, *secondary_pipes != *primary_pipes << 1,
-		 "Joiner misconfigured (primary pipes 0x%x, secondary pipes 0x%x)\n",
-		 *primary_pipes, *secondary_pipes);
-}
-
-static enum pipe intel_joiner_find_primary_pipe(enum pipe pipe,
-						u8 primary_pipes,
-						u8 secondary_pipes)
-{
-	if ((secondary_pipes & BIT(pipe)) == 0)
-		return pipe;
-
-	/* ignore everything above our pipe */
-	primary_pipes &= ~GENMASK(7, pipe);
-
-	/* highest remaining bit should be our primary pipe */
-	return fls(primary_pipes) - 1;
-}
-
-static u8 intel_joiner_find_secondary_pipes(enum pipe pipe,
-					    u8 primary_pipes,
-					    u8 secondary_pipes)
-{
-	enum pipe primary_pipe, next_primary_pipe;
-
-	primary_pipe = intel_joiner_find_primary_pipe(pipe, primary_pipes, secondary_pipes);
-
-	if ((primary_pipes & BIT(primary_pipe)) == 0)
-		return 0;
-
-	/* ignore our primary pipe and everything below it */
-	primary_pipes &= ~GENMASK(primary_pipe, 0);
-	/* make sure a high bit is set for the ffs() */
-	primary_pipes |= BIT(7);
-	/* lowest remaining bit should be the next primary pipe */
-	next_primary_pipe = ffs(primary_pipes) - 1;
-
-	return secondary_pipes & GENMASK(next_primary_pipe - 1, primary_pipe);
-}
-
 static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
 {
 	u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
@@ -3794,23 +3662,6 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
 	return transcoder_is_dsi(pipe_config->cpu_transcoder);
 }
 
-static void intel_joiner_get_config(struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	u8 primary_pipes, secondary_pipes;
-	enum pipe pipe = crtc->pipe;
-
-	intel_joiner_enabled_pipes(i915, &primary_pipes, &secondary_pipes);
-
-	if (((primary_pipes | secondary_pipes) & BIT(pipe)) == 0)
-		return;
-
-	crtc_state->joiner_pipes =
-		BIT(intel_joiner_find_primary_pipe(pipe, primary_pipes, secondary_pipes)) |
-		intel_joiner_find_secondary_pipes(pipe, primary_pipes, secondary_pipes);
-}
-
 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
 				struct intel_crtc_state *pipe_config)
 {
@@ -5822,9 +5673,9 @@ static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
 		IS_IVYBRIDGE(dev_priv);
 }
 
-static int intel_crtc_add_joiner_planes(struct intel_atomic_state *state,
-					struct intel_crtc *crtc,
-					struct intel_crtc *other)
+int intel_crtc_add_joiner_planes(struct intel_atomic_state *state,
+				 struct intel_crtc *crtc,
+				 struct intel_crtc *other)
 {
 	const struct intel_plane_state __maybe_unused *plane_state;
 	struct intel_plane *plane;
@@ -5839,32 +5690,6 @@ static int intel_crtc_add_joiner_planes(struct intel_atomic_state *state,
 	return intel_crtc_add_planes_to_state(state, other, plane_ids);
 }
 
-static int intel_joiner_add_affected_planes(struct intel_atomic_state *state)
-{
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
-	const struct intel_crtc_state *crtc_state;
-	struct intel_crtc *crtc;
-	int i;
-
-	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
-		struct intel_crtc *other;
-
-		for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
-						 crtc_state->joiner_pipes) {
-			int ret;
-
-			if (crtc == other)
-				continue;
-
-			ret = intel_crtc_add_joiner_planes(state, crtc, other);
-			if (ret)
-				return ret;
-		}
-	}
-
-	return 0;
-}
-
 static int intel_atomic_check_planes(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -6049,8 +5874,8 @@ static int intel_atomic_check_joiner(struct intel_atomic_state *state,
 	return 0;
 }
 
-static void kill_joiner_secondaries(struct intel_atomic_state *state,
-				    struct intel_crtc *primary_crtc)
+void intel_crtc_kill_joiner_secondaries(struct intel_atomic_state *state,
+					struct intel_crtc *primary_crtc)
 {
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	struct intel_crtc_state *primary_crtc_state =
@@ -6349,53 +6174,6 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in
 	return 0;
 }
 
-static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
-{
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
-	struct intel_crtc_state *crtc_state;
-	struct intel_crtc *crtc;
-	u8 affected_pipes = 0;
-	u8 modeset_pipes = 0;
-	int i;
-
-	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
-		affected_pipes |= crtc_state->joiner_pipes;
-		if (intel_crtc_needs_modeset(crtc_state))
-			modeset_pipes |= crtc_state->joiner_pipes;
-	}
-
-	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
-		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
-		if (IS_ERR(crtc_state))
-			return PTR_ERR(crtc_state);
-	}
-
-	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
-		int ret;
-
-		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
-
-		crtc_state->uapi.mode_changed = true;
-
-		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
-		if (ret)
-			return ret;
-
-		ret = intel_atomic_add_affected_planes(state, crtc);
-		if (ret)
-			return ret;
-	}
-
-	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
-		/* Kill old joiner link, we may re-establish afterwards */
-		if (intel_crtc_needs_modeset(crtc_state) &&
-		    intel_crtc_is_joiner_primary(crtc_state))
-			kill_joiner_secondaries(state, crtc);
-	}
-
-	return 0;
-}
-
 static int intel_atomic_check_config(struct intel_atomic_state *state,
 				     struct intel_link_bw_limits *limits,
 				     enum pipe *failed_pipe)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index b21d9578d5db..6bf423e36bc9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -586,5 +586,10 @@ bool assert_port_valid(struct drm_i915_private *i915, enum port port);
 })
 
 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915);
+int intel_crtc_add_joiner_planes(struct intel_atomic_state *state,
+				 struct intel_crtc *crtc,
+				 struct intel_crtc *other);
+void intel_crtc_kill_joiner_secondaries(struct intel_atomic_state *state,
+					struct intel_crtc *primary_crtc);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.c b/drivers/gpu/drm/i915/display/intel_joiner.c
new file mode 100644
index 000000000000..b24dfdbc9840
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_joiner.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#include <drm/drm_rect.h>
+
+#include "i915_drv.h"
+#include "intel_atomic.h"
+#include "intel_display.h"
+#include "intel_display_device.h"
+#include "intel_display_types.h"
+#include "intel_dss.h"
+#include "intel_joiner.h"
+
+enum pipe intel_joiner_get_primary_pipe(const struct intel_crtc_state *crtc_state)
+{
+	return ffs(crtc_state->joiner_pipes) - 1;
+}
+
+int intel_joiner_get_num_pipes(const struct intel_crtc_state *crtc_state)
+{
+	return hweight8(crtc_state->joiner_pipes);
+}
+
+void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,
+				 struct drm_display_mode *mode)
+{
+	int num_pipes = intel_joiner_get_num_pipes(crtc_state);
+
+	if (num_pipes < 2)
+		return;
+
+	mode->crtc_clock /= num_pipes;
+	mode->crtc_hdisplay /= num_pipes;
+	mode->crtc_hblank_start /= num_pipes;
+	mode->crtc_hblank_end /= num_pipes;
+	mode->crtc_hsync_start /= num_pipes;
+	mode->crtc_hsync_end /= num_pipes;
+	mode->crtc_htotal /= num_pipes;
+}
+
+void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
+{
+	int num_pipes = intel_joiner_get_num_pipes(crtc_state);
+	int width, height;
+
+	if (num_pipes < 2)
+		return;
+
+	width = drm_rect_width(&crtc_state->pipe_src);
+	height = drm_rect_height(&crtc_state->pipe_src);
+
+	drm_rect_init(&crtc_state->pipe_src, 0, 0,
+		      width / num_pipes, height);
+}
+
+void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	int num_pipes = intel_joiner_get_num_pipes(crtc_state);
+	enum pipe primary_pipe, pipe = crtc->pipe;
+	int width;
+
+	if (num_pipes < 2)
+		return;
+
+	primary_pipe = intel_joiner_get_primary_pipe(crtc_state);
+	width = drm_rect_width(&crtc_state->pipe_src);
+
+	drm_rect_translate_to(&crtc_state->pipe_src,
+			      (pipe - primary_pipe) * width, 0);
+}
+
+u8 intel_joiner_supported_pipes(struct drm_i915_private *i915)
+{
+	u8 pipes;
+
+	if (DISPLAY_VER(i915) >= 12)
+		pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
+	else if (DISPLAY_VER(i915) >= 11)
+		pipes = BIT(PIPE_B) | BIT(PIPE_C);
+	else
+		pipes = 0;
+
+	return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
+}
+
+void intel_joiner_enabled_pipes(struct drm_i915_private *dev_priv,
+				u8 *primary_pipes, u8 *secondary_pipes)
+{
+	struct intel_crtc *crtc;
+
+	*primary_pipes = 0;
+	*secondary_pipes = 0;
+
+	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
+					 intel_joiner_supported_pipes(dev_priv)) {
+		intel_dss_get_compressed_joiner_pipes(crtc,
+						      primary_pipes,
+						      secondary_pipes);
+
+		intel_dss_get_uncompressed_joiner_pipes(crtc,
+							primary_pipes,
+							secondary_pipes);
+	}
+
+	/* Joiner pipes should always be consecutive primary and secondary */
+	drm_WARN(&dev_priv->drm, *secondary_pipes != *primary_pipes << 1,
+		 "Joiner misconfigured (primary pipes 0x%x, secondary pipes 0x%x)\n",
+		 *primary_pipes, *secondary_pipes);
+}
+
+enum pipe intel_joiner_find_primary_pipe(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes)
+{
+	if ((secondary_pipes & BIT(pipe)) == 0)
+		return pipe;
+
+	/* ignore everything above our pipe */
+	primary_pipes &= ~GENMASK(7, pipe);
+
+	/* highest remaining bit should be our primary pipe */
+	return fls(primary_pipes) - 1;
+}
+
+u8 intel_joiner_find_secondary_pipes(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes)
+{
+	enum pipe primary_pipe, next_primary_pipe;
+
+	primary_pipe = intel_joiner_find_primary_pipe(pipe, primary_pipes, secondary_pipes);
+
+	if ((primary_pipes & BIT(primary_pipe)) == 0)
+		return 0;
+
+	/* ignore our primary pipe and everything below it */
+	primary_pipes &= ~GENMASK(primary_pipe, 0);
+	/* make sure a high bit is set for the ffs() */
+	primary_pipes |= BIT(7);
+	/* lowest remaining bit should be the next primary pipe */
+	next_primary_pipe = ffs(primary_pipes) - 1;
+
+	return secondary_pipes & GENMASK(next_primary_pipe - 1, primary_pipe);
+}
+
+void intel_joiner_get_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	u8 primary_pipes, secondary_pipes;
+	enum pipe pipe = crtc->pipe;
+
+	intel_joiner_enabled_pipes(i915, &primary_pipes, &secondary_pipes);
+
+	if (((primary_pipes | secondary_pipes) & BIT(pipe)) == 0)
+		return;
+
+	crtc_state->joiner_pipes =
+		BIT(intel_joiner_find_primary_pipe(pipe, primary_pipes, secondary_pipes)) |
+		intel_joiner_find_secondary_pipes(pipe, primary_pipes, secondary_pipes);
+}
+
+int intel_joiner_add_affected_planes(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	const struct intel_crtc_state *crtc_state;
+	struct intel_crtc *crtc;
+	int i;
+
+	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+		struct intel_crtc *other;
+
+		for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
+						 crtc_state->joiner_pipes) {
+			int ret;
+
+			if (crtc == other)
+				continue;
+
+			ret = intel_crtc_add_joiner_planes(state, crtc, other);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
+int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_crtc_state *crtc_state;
+	struct intel_crtc *crtc;
+	u8 affected_pipes = 0;
+	u8 modeset_pipes = 0;
+	int i;
+
+	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+		affected_pipes |= crtc_state->joiner_pipes;
+		if (intel_crtc_needs_modeset(crtc_state))
+			modeset_pipes |= crtc_state->joiner_pipes;
+	}
+
+	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
+		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
+		if (IS_ERR(crtc_state))
+			return PTR_ERR(crtc_state);
+	}
+
+	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
+		int ret;
+
+		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+
+		crtc_state->uapi.mode_changed = true;
+
+		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
+		if (ret)
+			return ret;
+
+		ret = intel_atomic_add_affected_planes(state, crtc);
+		if (ret)
+			return ret;
+	}
+
+	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+		/* Kill old joiner link, we may re-establish afterwards */
+		if (intel_crtc_needs_modeset(crtc_state) &&
+		    intel_crtc_is_joiner_primary(crtc_state))
+			intel_crtc_kill_joiner_secondaries(state, crtc);
+	}
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.h b/drivers/gpu/drm/i915/display/intel_joiner.h
new file mode 100644
index 000000000000..3417274de4a2
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_joiner.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_JOINER_H__
+#define __INTEL_JOINER_H__
+
+#include "linux/types.h"
+
+enum pipe;
+struct drm_display_mode;
+struct drm_i915_private;
+struct intel_atomic_state;
+struct intel_crtc_state;
+
+enum pipe intel_joiner_get_primary_pipe(const struct intel_crtc_state *crtc_state);
+int intel_joiner_get_num_pipes(const struct intel_crtc_state *crtc_state);
+void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,
+				 struct drm_display_mode *mode);
+void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state);
+void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state);
+u8 intel_joiner_supported_pipes(struct drm_i915_private *i915);
+void intel_joiner_enabled_pipes(struct drm_i915_private *dev_priv,
+				u8 *primary_pipes, u8 *secondary_pipes);
+enum pipe intel_joiner_find_primary_pipe(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes);
+u8 intel_joiner_find_secondary_pipes(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes);
+void intel_joiner_get_config(struct intel_crtc_state *crtc_state);
+int intel_joiner_add_affected_planes(struct intel_atomic_state *state);
+int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state);
+
+#endif/* __INTEL_JOINER_H__ */
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index ff1c0ce6da86..995accd939f9 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -243,6 +243,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_hotplug.o \
 	i915-display/intel_hotplug_irq.o \
 	i915-display/intel_hti.o \
+	i915-display/intel_joiner.o \
 	i915-display/intel_link_bw.o \
 	i915-display/intel_lspcon.o \
 	i915-display/intel_modeset_lock.o \
-- 
2.45.2

[PATCH 14/19] drm/i915/display: Move intel_crtc_joined_pipe_mask to intel_joiner

[Ankit Nautiyal]

Move the helper to get joined pipe mask to intel_joiner.c

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     |  9 ++---
 drivers/gpu/drm/i915/display/intel_display.c | 35 ++++++++------------
 drivers/gpu/drm/i915/display/intel_display.h |  1 -
 drivers/gpu/drm/i915/display/intel_dp_mst.c  |  7 ++--
 drivers/gpu/drm/i915/display/intel_joiner.c  |  7 ++++
 drivers/gpu/drm/i915/display/intel_joiner.h  |  1 +
 6 files changed, 31 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index aa176f4d42c4..87dbb7733eda 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -66,6 +66,7 @@
 #include "intel_hdmi.h"
 #include "intel_hotplug.h"
 #include "intel_hti.h"
+#include "intel_joiner.h"
 #include "intel_lspcon.h"
 #include "intel_mg_phy_regs.h"
 #include "intel_modeset_lock.h"
@@ -3043,7 +3044,7 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state,
 	struct intel_crtc *pipe_crtc;
 
 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
-					 intel_crtc_joined_pipe_mask(old_crtc_state)) {
+					 intel_joiner_crtc_joined_pipe_mask(old_crtc_state)) {
 		const struct intel_crtc_state *old_pipe_crtc_state =
 			intel_atomic_get_old_crtc_state(state, pipe_crtc);
 
@@ -3055,7 +3056,7 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state,
 	intel_ddi_disable_transcoder_func(old_crtc_state);
 
 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
-					 intel_crtc_joined_pipe_mask(old_crtc_state)) {
+					 intel_joiner_crtc_joined_pipe_mask(old_crtc_state)) {
 		const struct intel_crtc_state *old_pipe_crtc_state =
 			intel_atomic_get_old_crtc_state(state, pipe_crtc);
 
@@ -3319,7 +3320,7 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
 	intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
 
 	for_each_intel_crtc_in_pipe_mask_reverse(&i915->drm, pipe_crtc,
-						 intel_crtc_joined_pipe_mask(crtc_state)) {
+						 intel_joiner_crtc_joined_pipe_mask(crtc_state)) {
 		const struct intel_crtc_state *pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
 
@@ -3429,7 +3430,7 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
 		return;
 
 	for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc,
-					 intel_crtc_joined_pipe_mask(crtc_state))
+					 intel_joiner_crtc_joined_pipe_mask(crtc_state))
 		intel_update_active_dpll(state, pipe_crtc, encoder);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9af3ea6c7642..97f01a02efe3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -274,13 +274,6 @@ bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)
 		crtc->pipe == intel_joiner_get_primary_pipe(crtc_state);
 }
 
-u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-
-	return BIT(crtc->pipe) | crtc_state->joiner_pipes;
-}
-
 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
@@ -1679,13 +1672,13 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
 		return;
 
 	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
-						 intel_crtc_joined_pipe_mask(new_crtc_state))
+						 intel_joiner_crtc_joined_pipe_mask(new_crtc_state))
 		intel_dmc_enable_pipe(dev_priv, pipe_crtc->pipe);
 
 	intel_encoders_pre_pll_enable(state, crtc);
 
 	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
-						 intel_crtc_joined_pipe_mask(new_crtc_state)) {
+						 intel_joiner_crtc_joined_pipe_mask(new_crtc_state)) {
 		const struct intel_crtc_state *pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
 
@@ -1696,7 +1689,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
 	intel_encoders_pre_enable(state, crtc);
 
 	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
-						 intel_crtc_joined_pipe_mask(new_crtc_state)) {
+						 intel_joiner_crtc_joined_pipe_mask(new_crtc_state)) {
 		const struct intel_crtc_state *pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
 
@@ -1715,7 +1708,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
 		hsw_configure_cpu_transcoder(new_crtc_state);
 
 	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
-						 intel_crtc_joined_pipe_mask(new_crtc_state)) {
+						 intel_joiner_crtc_joined_pipe_mask(new_crtc_state)) {
 		const struct intel_crtc_state *pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
 
@@ -1751,7 +1744,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
 	intel_encoders_enable(state, crtc);
 
 	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
-						 intel_crtc_joined_pipe_mask(new_crtc_state)) {
+						 intel_joiner_crtc_joined_pipe_mask(new_crtc_state)) {
 		const struct intel_crtc_state *pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
 		enum pipe hsw_workaround_pipe;
@@ -1846,7 +1839,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
 	intel_encoders_post_disable(state, crtc);
 
 	for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc,
-					 intel_crtc_joined_pipe_mask(old_crtc_state)) {
+					 intel_joiner_crtc_joined_pipe_mask(old_crtc_state)) {
 		const struct intel_crtc_state *old_pipe_crtc_state =
 			intel_atomic_get_old_crtc_state(state, pipe_crtc);
 
@@ -1856,7 +1849,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
 	intel_encoders_post_pll_disable(state, crtc);
 
 	for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc,
-					 intel_crtc_joined_pipe_mask(old_crtc_state))
+					 intel_joiner_crtc_joined_pipe_mask(old_crtc_state))
 		intel_dmc_disable_pipe(i915, pipe_crtc->pipe);
 }
 
@@ -6632,7 +6625,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
 		return;
 
 	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
-						 intel_crtc_joined_pipe_mask(new_crtc_state)) {
+						 intel_joiner_crtc_joined_pipe_mask(new_crtc_state)) {
 		const struct intel_crtc_state *pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
 
@@ -6745,13 +6738,13 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
 	 * or we race against vblank off.
 	 */
 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
-					 intel_crtc_joined_pipe_mask(old_crtc_state))
+					 intel_joiner_crtc_joined_pipe_mask(old_crtc_state))
 		intel_crtc_disable_pipe_crc(pipe_crtc);
 
 	dev_priv->display.funcs.display->crtc_disable(state, crtc);
 
 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
-					 intel_crtc_joined_pipe_mask(old_crtc_state)) {
+					 intel_joiner_crtc_joined_pipe_mask(old_crtc_state)) {
 		const struct intel_crtc_state *new_pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
 
@@ -6816,7 +6809,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 
 		intel_old_crtc_state_disables(state, crtc);
 
-		disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state);
+		disable_pipes &= ~intel_joiner_crtc_joined_pipe_mask(old_crtc_state);
 	}
 
 	/* Disable everything else left on */
@@ -6829,7 +6822,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 
 		intel_old_crtc_state_disables(state, crtc);
 
-		disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state);
+		disable_pipes &= ~intel_joiner_crtc_joined_pipe_mask(old_crtc_state);
 	}
 
 	drm_WARN_ON(&i915->drm, disable_pipes);
@@ -6956,7 +6949,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
 		    is_trans_port_sync_master(new_crtc_state))
 			continue;
 
-		modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state);
+		modeset_pipes &= ~intel_joiner_crtc_joined_pipe_mask(new_crtc_state);
 
 		intel_enable_crtc(state, crtc);
 	}
@@ -6974,7 +6967,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
 		if (intel_crtc_is_joiner_secondary(new_crtc_state))
 			continue;
 
-		modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state);
+		modeset_pipes &= ~intel_joiner_crtc_joined_pipe_mask(new_crtc_state);
 
 		intel_enable_crtc(state, crtc);
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 6bf423e36bc9..72643f278c2e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -422,7 +422,6 @@ intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
 bool is_trans_port_sync_master(const struct intel_crtc_state *state);
-u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);
 bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state);
 bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);
 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 15541932b809..0fc76455de1f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -47,6 +47,7 @@
 #include "intel_dpio_phy.h"
 #include "intel_hdcp.h"
 #include "intel_hotplug.h"
+#include "intel_joiner.h"
 #include "intel_link_bw.h"
 #include "intel_psr.h"
 #include "intel_vdsc.h"
@@ -1009,7 +1010,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
 		    !intel_dp_mst_is_master_trans(old_crtc_state));
 
 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
-					 intel_crtc_joined_pipe_mask(old_crtc_state)) {
+					 intel_joiner_crtc_joined_pipe_mask(old_crtc_state)) {
 		const struct intel_crtc_state *old_pipe_crtc_state =
 			intel_atomic_get_old_crtc_state(state, pipe_crtc);
 
@@ -1034,7 +1035,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
 	intel_ddi_disable_transcoder_func(old_crtc_state);
 
 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
-					 intel_crtc_joined_pipe_mask(old_crtc_state)) {
+					 intel_joiner_crtc_joined_pipe_mask(old_crtc_state)) {
 		const struct intel_crtc_state *old_pipe_crtc_state =
 			intel_atomic_get_old_crtc_state(state, pipe_crtc);
 
@@ -1301,7 +1302,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
 	intel_enable_transcoder(pipe_config);
 
 	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
-						 intel_crtc_joined_pipe_mask(pipe_config)) {
+						 intel_joiner_crtc_joined_pipe_mask(pipe_config)) {
 		const struct intel_crtc_state *pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
 
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.c b/drivers/gpu/drm/i915/display/intel_joiner.c
index b24dfdbc9840..e6dfed812564 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.c
+++ b/drivers/gpu/drm/i915/display/intel_joiner.c
@@ -231,3 +231,10 @@ int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
 
 	return 0;
 }
+
+u8 intel_joiner_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	return BIT(crtc->pipe) | crtc_state->joiner_pipes;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.h b/drivers/gpu/drm/i915/display/intel_joiner.h
index 3417274de4a2..f8c0cd27536c 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.h
+++ b/drivers/gpu/drm/i915/display/intel_joiner.h
@@ -28,5 +28,6 @@ u8 intel_joiner_find_secondary_pipes(enum pipe pipe, u8 primary_pipes, u8 second
 void intel_joiner_get_config(struct intel_crtc_state *crtc_state);
 int intel_joiner_add_affected_planes(struct intel_atomic_state *state);
 int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state);
+u8 intel_joiner_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);
 
 #endif/* __INTEL_JOINER_H__ */
-- 
2.45.2

[PATCH 15/19] drm/i915/display: Move helpers for primary joiner to intel_joiner

[Ankit Nautiyal]

Move helpers to get/check primary joiner pipes to intel_joiner.
Rename them to align with other intel_joiner helpers.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c |  3 ++-
 drivers/gpu/drm/i915/display/intel_display.c         |  8 --------
 drivers/gpu/drm/i915/display/intel_display.h         |  1 -
 drivers/gpu/drm/i915/display/intel_joiner.c          | 10 +++++++++-
 drivers/gpu/drm/i915/display/intel_joiner.h          |  1 +
 5 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 705ec5ad385c..606fa069c93c 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -10,6 +10,7 @@
 #include "intel_crtc_state_dump.h"
 #include "intel_display_types.h"
 #include "intel_hdmi.h"
+#include "intel_joiner.h"
 #include "intel_vdsc.h"
 #include "intel_vrr.h"
 
@@ -225,7 +226,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 
 	drm_printf(&p, "joiner: %s, pipes: 0x%x\n",
 		   intel_crtc_is_joiner_secondary(pipe_config) ? "secondary" :
-		   intel_crtc_is_joiner_primary(pipe_config) ? "primary" : "no",
+		   intel_joiner_crtc_is_joiner_primary(pipe_config) ? "primary" : "no",
 		   pipe_config->joiner_pipes);
 
 	drm_printf(&p, "splitter: %s, link count %d, overlap %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 97f01a02efe3..4506cf9fa031 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -266,14 +266,6 @@ bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state)
 		crtc->pipe != intel_joiner_get_primary_pipe(crtc_state);
 }
 
-bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-
-	return crtc_state->joiner_pipes &&
-		crtc->pipe == intel_joiner_get_primary_pipe(crtc_state);
-}
-
 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 72643f278c2e..6ef756a8781e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -423,7 +423,6 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
 bool is_trans_port_sync_master(const struct intel_crtc_state *state);
 bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state);
-bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);
 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);
 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state);
 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.c b/drivers/gpu/drm/i915/display/intel_joiner.c
index e6dfed812564..d36df20f811f 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.c
+++ b/drivers/gpu/drm/i915/display/intel_joiner.c
@@ -225,7 +225,7 @@ int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
 		/* Kill old joiner link, we may re-establish afterwards */
 		if (intel_crtc_needs_modeset(crtc_state) &&
-		    intel_crtc_is_joiner_primary(crtc_state))
+		    intel_joiner_crtc_is_joiner_primary(crtc_state))
 			intel_crtc_kill_joiner_secondaries(state, crtc);
 	}
 
@@ -238,3 +238,11 @@ u8 intel_joiner_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state)
 
 	return BIT(crtc->pipe) | crtc_state->joiner_pipes;
 }
+
+bool intel_joiner_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	return crtc_state->joiner_pipes &&
+		crtc->pipe == intel_joiner_get_primary_pipe(crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.h b/drivers/gpu/drm/i915/display/intel_joiner.h
index f8c0cd27536c..4f19d623558a 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.h
+++ b/drivers/gpu/drm/i915/display/intel_joiner.h
@@ -29,5 +29,6 @@ void intel_joiner_get_config(struct intel_crtc_state *crtc_state);
 int intel_joiner_add_affected_planes(struct intel_atomic_state *state);
 int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state);
 u8 intel_joiner_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);
+bool intel_joiner_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);
 
 #endif/* __INTEL_JOINER_H__ */
-- 
2.45.2

[PATCH 16/19] drm/i915/display: Move intel_crtc_is_joiner_secondary to intel_joiner

[Ankit Nautiyal]

Move the helper to check secondary joiner pipes to intel_joiner.

v2: Rebase.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c |  3 +-
 .../drm/i915/display/intel_crtc_state_dump.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 30 +++++++------------
 drivers/gpu/drm/i915/display/intel_display.h  |  1 -
 .../drm/i915/display/intel_display_debugfs.c  |  3 +-
 drivers/gpu/drm/i915/display/intel_drrs.c     |  5 ++--
 drivers/gpu/drm/i915/display/intel_dss.c      |  5 ++--
 drivers/gpu/drm/i915/display/intel_joiner.c   |  8 +++++
 drivers/gpu/drm/i915/display/intel_joiner.h   |  1 +
 .../drm/i915/display/intel_modeset_setup.c    |  9 +++---
 10 files changed, 36 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..478205b88502 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -49,6 +49,7 @@
 #include "intel_display_types.h"
 #include "intel_fb.h"
 #include "intel_fb_pin.h"
+#include "intel_joiner.h"
 #include "skl_scaler.h"
 #include "skl_watermark.h"
 
@@ -722,7 +723,7 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
 	struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
-	if (new_crtc_state && intel_crtc_is_joiner_secondary(new_crtc_state)) {
+	if (new_crtc_state && intel_joiner_crtc_is_joiner_secondary(new_crtc_state)) {
 		struct intel_crtc *primary_crtc =
 			intel_primary_crtc(new_crtc_state);
 		struct intel_plane *primary_crtc_plane =
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 606fa069c93c..269c97343c72 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -225,7 +225,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 		   pipe_config->sync_mode_slaves_mask);
 
 	drm_printf(&p, "joiner: %s, pipes: 0x%x\n",
-		   intel_crtc_is_joiner_secondary(pipe_config) ? "secondary" :
+		   intel_joiner_crtc_is_joiner_secondary(pipe_config) ? "secondary" :
 		   intel_joiner_crtc_is_joiner_primary(pipe_config) ? "primary" : "no",
 		   pipe_config->joiner_pipes);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4506cf9fa031..71d9f132e46c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -258,19 +258,11 @@ u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
 		return 0;
 }
 
-bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-
-	return crtc_state->joiner_pipes &&
-		crtc->pipe != intel_joiner_get_primary_pipe(crtc_state);
-}
-
 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
-	if (intel_crtc_is_joiner_secondary(crtc_state))
+	if (intel_joiner_crtc_is_joiner_secondary(crtc_state))
 		return intel_crtc_for_pipe(i915, intel_joiner_get_primary_pipe(crtc_state));
 	else
 		return to_intel_crtc(crtc_state->uapi.crtc);
@@ -4311,7 +4303,7 @@ intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
-	WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
+	WARN_ON(intel_joiner_crtc_is_joiner_secondary(crtc_state));
 
 	drm_property_replace_blob(&crtc_state->hw.degamma_lut,
 				  crtc_state->uapi.degamma_lut);
@@ -4328,7 +4320,7 @@ intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
-	WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
+	WARN_ON(intel_joiner_crtc_is_joiner_secondary(crtc_state));
 
 	crtc_state->hw.enable = crtc_state->uapi.enable;
 	crtc_state->hw.active = crtc_state->uapi.active;
@@ -6181,14 +6173,14 @@ static int intel_atomic_check_config(struct intel_atomic_state *state,
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
 		if (!intel_crtc_needs_modeset(new_crtc_state)) {
-			if (intel_crtc_is_joiner_secondary(new_crtc_state))
+			if (intel_joiner_crtc_is_joiner_secondary(new_crtc_state))
 				copy_joiner_crtc_state_nomodeset(state, crtc);
 			else
 				intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
 			continue;
 		}
 
-		if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
+		if (drm_WARN_ON(&i915->drm, intel_joiner_crtc_is_joiner_secondary(new_crtc_state)))
 			continue;
 
 		ret = intel_crtc_prepare_cleared_state(state, crtc);
@@ -6207,7 +6199,7 @@ static int intel_atomic_check_config(struct intel_atomic_state *state,
 		if (!intel_crtc_needs_modeset(new_crtc_state))
 			continue;
 
-		if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
+		if (drm_WARN_ON(&i915->drm, intel_joiner_crtc_is_joiner_secondary(new_crtc_state)))
 			continue;
 
 		if (!new_crtc_state->hw.enable)
@@ -6318,7 +6310,7 @@ int intel_atomic_check(struct drm_device *dev,
 		if (!intel_crtc_needs_modeset(new_crtc_state))
 			continue;
 
-		if (intel_crtc_is_joiner_secondary(new_crtc_state)) {
+		if (intel_joiner_crtc_is_joiner_secondary(new_crtc_state)) {
 			drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
 			continue;
 		}
@@ -6787,7 +6779,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 		if ((disable_pipes & BIT(crtc->pipe)) == 0)
 			continue;
 
-		if (intel_crtc_is_joiner_secondary(old_crtc_state))
+		if (intel_joiner_crtc_is_joiner_secondary(old_crtc_state))
 			continue;
 
 		/* In case of Transcoder port Sync master slave CRTCs can be
@@ -6809,7 +6801,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 		if ((disable_pipes & BIT(crtc->pipe)) == 0)
 			continue;
 
-		if (intel_crtc_is_joiner_secondary(old_crtc_state))
+		if (intel_joiner_crtc_is_joiner_secondary(old_crtc_state))
 			continue;
 
 		intel_old_crtc_state_disables(state, crtc);
@@ -6934,7 +6926,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
 		if ((modeset_pipes & BIT(pipe)) == 0)
 			continue;
 
-		if (intel_crtc_is_joiner_secondary(new_crtc_state))
+		if (intel_joiner_crtc_is_joiner_secondary(new_crtc_state))
 			continue;
 
 		if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
@@ -6956,7 +6948,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
 		if ((modeset_pipes & BIT(pipe)) == 0)
 			continue;
 
-		if (intel_crtc_is_joiner_secondary(new_crtc_state))
+		if (intel_joiner_crtc_is_joiner_secondary(new_crtc_state))
 			continue;
 
 		modeset_pipes &= ~intel_joiner_crtc_joined_pipe_mask(new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 6ef756a8781e..5528e9c9568f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -422,7 +422,6 @@ intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
 bool is_trans_port_sync_master(const struct intel_crtc_state *state);
-bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state);
 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);
 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state);
 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 74f527647aa9..2f862876f269 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -32,6 +32,7 @@
 #include "intel_hdcp.h"
 #include "intel_hdmi.h"
 #include "intel_hotplug.h"
+#include "intel_joiner.h"
 #include "intel_panel.h"
 #include "intel_pps.h"
 #include "intel_psr.h"
@@ -581,7 +582,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
 	if (crtc_state->joiner_pipes)
 		seq_printf(m, "\tLinked to 0x%x pipes as a %s\n",
 			   crtc_state->joiner_pipes,
-			   intel_crtc_is_joiner_secondary(crtc_state) ? "slave" : "master");
+			   intel_joiner_crtc_is_joiner_secondary(crtc_state) ? "slave" : "master");
 
 	intel_vdsc_state_dump(&p, 1, crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index 3ca29afa5422..b80014b66ff4 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -10,6 +10,7 @@
 #include "intel_display_types.h"
 #include "intel_drrs.h"
 #include "intel_frontbuffer.h"
+#include "intel_joiner.h"
 #include "intel_panel.h"
 
 /**
@@ -157,7 +158,7 @@ void intel_drrs_activate(const struct intel_crtc_state *crtc_state)
 	if (!crtc_state->hw.active)
 		return;
 
-	if (intel_crtc_is_joiner_secondary(crtc_state))
+	if (intel_joiner_crtc_is_joiner_secondary(crtc_state))
 		return;
 
 	mutex_lock(&crtc->drrs.mutex);
@@ -189,7 +190,7 @@ void intel_drrs_deactivate(const struct intel_crtc_state *old_crtc_state)
 	if (!old_crtc_state->hw.active)
 		return;
 
-	if (intel_crtc_is_joiner_secondary(old_crtc_state))
+	if (intel_joiner_crtc_is_joiner_secondary(old_crtc_state))
 		return;
 
 	mutex_lock(&crtc->drrs.mutex);
diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c
index 01303feadcef..6029e9a16655 100644
--- a/drivers/gpu/drm/i915/display/intel_dss.c
+++ b/drivers/gpu/drm/i915/display/intel_dss.c
@@ -11,6 +11,7 @@
 #include "intel_dsi.h"
 #include "intel_dss.h"
 #include "intel_dss_regs.h"
+#include "intel_joiner.h"
 #include "intel_vdsc.h"
 
 /*
@@ -168,7 +169,7 @@ void intel_dss_enable_uncompressed_joiner(const struct intel_crtc_state *crtc_st
 	u32 dss_ctl1_val = 0;
 
 	if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {
-		if (intel_crtc_is_joiner_secondary(crtc_state))
+		if (intel_joiner_crtc_is_joiner_secondary(crtc_state))
 			dss_ctl1_val |= UNCOMPRESSED_JOINER_SECONDARY;
 		else
 			dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
@@ -194,7 +195,7 @@ void intel_dss_enable_compressed_joiner(const struct intel_crtc_state *crtc_stat
 	}
 	if (crtc_state->joiner_pipes) {
 		dss_ctl1_val |= BIG_JOINER_ENABLE;
-		if (!intel_crtc_is_joiner_secondary(crtc_state))
+		if (!intel_joiner_crtc_is_joiner_secondary(crtc_state))
 			dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
 	}
 	intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.c b/drivers/gpu/drm/i915/display/intel_joiner.c
index d36df20f811f..f7acd2de8ffb 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.c
+++ b/drivers/gpu/drm/i915/display/intel_joiner.c
@@ -246,3 +246,11 @@ bool intel_joiner_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_sta
 	return crtc_state->joiner_pipes &&
 		crtc->pipe == intel_joiner_get_primary_pipe(crtc_state);
 }
+
+bool intel_joiner_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	return crtc_state->joiner_pipes &&
+		crtc->pipe != intel_joiner_get_primary_pipe(crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.h b/drivers/gpu/drm/i915/display/intel_joiner.h
index 4f19d623558a..b3266ebf8922 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.h
+++ b/drivers/gpu/drm/i915/display/intel_joiner.h
@@ -30,5 +30,6 @@ int intel_joiner_add_affected_planes(struct intel_atomic_state *state);
 int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state);
 u8 intel_joiner_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);
 bool intel_joiner_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);
+bool intel_joiner_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state);
 
 #endif/* __INTEL_JOINER_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 72694dde3c22..466770f8b564 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -25,6 +25,7 @@
 #include "intel_dmc.h"
 #include "intel_fifo_underrun.h"
 #include "intel_modeset_setup.h"
+#include "intel_joiner.h"
 #include "intel_pch_display.h"
 #include "intel_pmdemand.h"
 #include "intel_tc.h"
@@ -204,7 +205,7 @@ static u8 get_transcoder_pipes(struct drm_i915_private *i915,
 		if (temp_crtc_state->cpu_transcoder == INVALID_TRANSCODER)
 			continue;
 
-		if (intel_crtc_is_joiner_secondary(temp_crtc_state))
+		if (intel_joiner_crtc_is_joiner_secondary(temp_crtc_state))
 			continue;
 
 		if (transcoder_mask & BIT(temp_crtc_state->cpu_transcoder))
@@ -328,7 +329,7 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
-	if (intel_crtc_is_joiner_secondary(crtc_state))
+	if (intel_joiner_crtc_is_joiner_secondary(crtc_state))
 		return;
 
 	crtc_state->uapi.enable = crtc_state->hw.enable;
@@ -495,7 +496,7 @@ static bool intel_sanitize_crtc(struct intel_crtc *crtc,
 	}
 
 	if (!crtc_state->hw.active ||
-	    intel_crtc_is_joiner_secondary(crtc_state))
+	    intel_joiner_crtc_is_joiner_secondary(crtc_state))
 		return false;
 
 	needs_link_reset = intel_crtc_needs_link_reset(crtc);
@@ -754,7 +755,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
 				struct intel_crtc *secondary_crtc;
 
 				/* encoder should read be linked to joiner primary */
-				WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
+				WARN_ON(intel_joiner_crtc_is_joiner_secondary(crtc_state));
 
 				for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,
 								 intel_crtc_joiner_secondary_pipes(crtc_state)) {
-- 
2.45.2

[PATCH 17/19] drm/i915/display: Move intel_crtc_joiner_secondary_pipes to intel_joiner

[Ankit Nautiyal]

Move the helper to get secondary joiner pipes to intel_joiner.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c       | 12 ++----------
 drivers/gpu/drm/i915/display/intel_display.h       |  1 -
 drivers/gpu/drm/i915/display/intel_joiner.c        |  8 ++++++++
 drivers/gpu/drm/i915/display/intel_joiner.h        |  1 +
 drivers/gpu/drm/i915/display/intel_modeset_setup.c |  6 +++---
 5 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 71d9f132e46c..556c7774a0b0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -250,14 +250,6 @@ is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 		is_trans_port_sync_slave(crtc_state);
 }
 
-u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
-{
-	if (crtc_state->joiner_pipes)
-		return crtc_state->joiner_pipes & ~BIT(intel_joiner_get_primary_pipe(crtc_state));
-	else
-		return 0;
-}
-
 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
@@ -5806,7 +5798,7 @@ static int intel_atomic_check_joiner(struct intel_atomic_state *state,
 	}
 
 	for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,
-					 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
+					 intel_joiner_crtc_joiner_secondary_pipes(primary_crtc_state)) {
 		struct intel_crtc_state *secondary_crtc_state;
 		int ret;
 
@@ -5860,7 +5852,7 @@ void intel_crtc_kill_joiner_secondaries(struct intel_atomic_state *state,
 	struct intel_crtc *secondary_crtc;
 
 	for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,
-					 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
+					 intel_joiner_crtc_joiner_secondary_pipes(primary_crtc_state)) {
 		struct intel_crtc_state *secondary_crtc_state =
 			intel_atomic_get_new_crtc_state(state, secondary_crtc);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 5528e9c9568f..b0f5303a5bb0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -422,7 +422,6 @@ intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
 bool is_trans_port_sync_master(const struct intel_crtc_state *state);
-u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);
 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state);
 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.c b/drivers/gpu/drm/i915/display/intel_joiner.c
index f7acd2de8ffb..0899cf51a825 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.c
+++ b/drivers/gpu/drm/i915/display/intel_joiner.c
@@ -254,3 +254,11 @@ bool intel_joiner_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_s
 	return crtc_state->joiner_pipes &&
 		crtc->pipe != intel_joiner_get_primary_pipe(crtc_state);
 }
+
+u8 intel_joiner_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
+{
+	if (crtc_state->joiner_pipes)
+		return crtc_state->joiner_pipes & ~BIT(intel_joiner_get_primary_pipe(crtc_state));
+	else
+		return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.h b/drivers/gpu/drm/i915/display/intel_joiner.h
index b3266ebf8922..cae9971c44f6 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.h
+++ b/drivers/gpu/drm/i915/display/intel_joiner.h
@@ -31,5 +31,6 @@ int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state);
 u8 intel_joiner_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);
 bool intel_joiner_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);
 bool intel_joiner_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state);
+u8 intel_joiner_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);
 
 #endif/* __INTEL_JOINER_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 466770f8b564..9b4acafdcdcd 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -69,7 +69,7 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
 	/* Everything's already locked, -EDEADLK can't happen. */
 	for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc,
 					 BIT(pipe) |
-					 intel_crtc_joiner_secondary_pipes(crtc_state)) {
+					 intel_joiner_crtc_joiner_secondary_pipes(crtc_state)) {
 		struct intel_crtc_state *temp_crtc_state =
 			intel_atomic_get_crtc_state(state, temp_crtc);
 		int ret;
@@ -258,7 +258,7 @@ static u8 get_joiner_secondary_pipes(struct drm_i915_private *i915, u8 primary_p
 		struct intel_crtc_state *primary_crtc_state =
 			to_intel_crtc_state(primary_crtc->base.state);
 
-		pipes |= intel_crtc_joiner_secondary_pipes(primary_crtc_state);
+		pipes |= intel_joiner_crtc_joiner_secondary_pipes(primary_crtc_state);
 	}
 
 	return pipes;
@@ -758,7 +758,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
 				WARN_ON(intel_joiner_crtc_is_joiner_secondary(crtc_state));
 
 				for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,
-								 intel_crtc_joiner_secondary_pipes(crtc_state)) {
+								 intel_joiner_crtc_joiner_secondary_pipes(crtc_state)) {
 					struct intel_crtc_state *secondary_crtc_state;
 
 					secondary_crtc_state = to_intel_crtc_state(secondary_crtc->base.state);
-- 
2.45.2

[PATCH 18/19] drm/i915/joiner: Use struct intel_display in intel_joiner_enabled_pipes

[Ankit Nautiyal]

Replace struct drm_i915_private with struct intel_display in the helper
intel_joiner_enabled_pipes and its callers.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  3 ++-
 drivers/gpu/drm/i915/display/intel_joiner.c  | 13 +++++++------
 drivers/gpu/drm/i915/display/intel_joiner.h  |  3 ++-
 3 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 556c7774a0b0..22a65d66f45e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3444,6 +3444,7 @@ static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
 
 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
 {
+	struct intel_display *display = to_intel_display(crtc);
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
@@ -3501,7 +3502,7 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
 		enabled_transcoders |= BIT(cpu_transcoder);
 
 	/* joiner secondary -> consider the primary pipe's transcoder as well */
-	intel_joiner_enabled_pipes(dev_priv, &primary_pipes, &secondary_pipes);
+	intel_joiner_enabled_pipes(display, &primary_pipes, &secondary_pipes);
 	if (secondary_pipes & BIT(crtc->pipe)) {
 		cpu_transcoder = (enum transcoder)
 			intel_joiner_find_primary_pipe(crtc->pipe, primary_pipes, secondary_pipes);
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.c b/drivers/gpu/drm/i915/display/intel_joiner.c
index 0899cf51a825..2c7477914f74 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.c
+++ b/drivers/gpu/drm/i915/display/intel_joiner.c
@@ -86,16 +86,17 @@ u8 intel_joiner_supported_pipes(struct drm_i915_private *i915)
 	return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
 }
 
-void intel_joiner_enabled_pipes(struct drm_i915_private *dev_priv,
+void intel_joiner_enabled_pipes(struct intel_display *display,
 				u8 *primary_pipes, u8 *secondary_pipes)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct intel_crtc *crtc;
 
 	*primary_pipes = 0;
 	*secondary_pipes = 0;
 
-	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
-					 intel_joiner_supported_pipes(dev_priv)) {
+	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc,
+					 intel_joiner_supported_pipes(i915)) {
 		intel_dss_get_compressed_joiner_pipes(crtc,
 						      primary_pipes,
 						      secondary_pipes);
@@ -106,7 +107,7 @@ void intel_joiner_enabled_pipes(struct drm_i915_private *dev_priv,
 	}
 
 	/* Joiner pipes should always be consecutive primary and secondary */
-	drm_WARN(&dev_priv->drm, *secondary_pipes != *primary_pipes << 1,
+	drm_WARN(display->drm, *secondary_pipes != *primary_pipes << 1,
 		 "Joiner misconfigured (primary pipes 0x%x, secondary pipes 0x%x)\n",
 		 *primary_pipes, *secondary_pipes);
 }
@@ -144,12 +145,12 @@ u8 intel_joiner_find_secondary_pipes(enum pipe pipe, u8 primary_pipes, u8 second
 
 void intel_joiner_get_config(struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	u8 primary_pipes, secondary_pipes;
 	enum pipe pipe = crtc->pipe;
 
-	intel_joiner_enabled_pipes(i915, &primary_pipes, &secondary_pipes);
+	intel_joiner_enabled_pipes(display, &primary_pipes, &secondary_pipes);
 
 	if (((primary_pipes | secondary_pipes) & BIT(pipe)) == 0)
 		return;
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.h b/drivers/gpu/drm/i915/display/intel_joiner.h
index cae9971c44f6..49cb2d78f4c8 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.h
+++ b/drivers/gpu/drm/i915/display/intel_joiner.h
@@ -13,6 +13,7 @@ struct drm_display_mode;
 struct drm_i915_private;
 struct intel_atomic_state;
 struct intel_crtc_state;
+struct intel_display;
 
 enum pipe intel_joiner_get_primary_pipe(const struct intel_crtc_state *crtc_state);
 int intel_joiner_get_num_pipes(const struct intel_crtc_state *crtc_state);
@@ -21,7 +22,7 @@ void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,
 void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state);
 void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state);
 u8 intel_joiner_supported_pipes(struct drm_i915_private *i915);
-void intel_joiner_enabled_pipes(struct drm_i915_private *dev_priv,
+void intel_joiner_enabled_pipes(struct intel_display *display,
 				u8 *primary_pipes, u8 *secondary_pipes);
 enum pipe intel_joiner_find_primary_pipe(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes);
 u8 intel_joiner_find_secondary_pipes(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes);
-- 
2.45.2

[PATCH 19/19] drm/i915/joiner: Use struct intel_display in intel_joiner_supported_pipes

[Ankit Nautiyal]

Replace struct drm_i915_private with struct intel_display in the helper
intel_joiner_supported_pipes and its callers.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  6 ++++--
 drivers/gpu/drm/i915/display/intel_joiner.c  | 10 +++++-----
 drivers/gpu/drm/i915/display/intel_joiner.h  |  3 +--
 3 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 22a65d66f45e..a326db662748 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5776,6 +5776,7 @@ static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
 static int intel_atomic_check_joiner(struct intel_atomic_state *state,
 				     struct intel_crtc *primary_crtc)
 {
+	struct intel_display *display = to_intel_display(primary_crtc);
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	struct intel_crtc_state *primary_crtc_state =
 		intel_atomic_get_new_crtc_state(state, primary_crtc);
@@ -5789,12 +5790,13 @@ static int intel_atomic_check_joiner(struct intel_atomic_state *state,
 			primary_crtc->pipe != intel_joiner_get_primary_pipe(primary_crtc_state)))
 		return -EINVAL;
 
-	if (primary_crtc_state->joiner_pipes & ~intel_joiner_supported_pipes(i915)) {
+	if (primary_crtc_state->joiner_pipes & ~intel_joiner_supported_pipes(display)) {
 		drm_dbg_kms(&i915->drm,
 			    "[CRTC:%d:%s] Cannot act as joiner primary "
 			    "(need 0x%x as pipes, only 0x%x possible)\n",
 			    primary_crtc->base.base.id, primary_crtc->base.name,
-			    primary_crtc_state->joiner_pipes, intel_joiner_supported_pipes(i915));
+			    primary_crtc_state->joiner_pipes,
+			    intel_joiner_supported_pipes(display));
 		return -EINVAL;
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.c b/drivers/gpu/drm/i915/display/intel_joiner.c
index 2c7477914f74..32cd0ab4e707 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.c
+++ b/drivers/gpu/drm/i915/display/intel_joiner.c
@@ -72,18 +72,18 @@ void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
 			      (pipe - primary_pipe) * width, 0);
 }
 
-u8 intel_joiner_supported_pipes(struct drm_i915_private *i915)
+u8 intel_joiner_supported_pipes(struct intel_display *display)
 {
 	u8 pipes;
 
-	if (DISPLAY_VER(i915) >= 12)
+	if (DISPLAY_VER(display) >= 12)
 		pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
-	else if (DISPLAY_VER(i915) >= 11)
+	else if (DISPLAY_VER(display) >= 11)
 		pipes = BIT(PIPE_B) | BIT(PIPE_C);
 	else
 		pipes = 0;
 
-	return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
+	return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask;
 }
 
 void intel_joiner_enabled_pipes(struct intel_display *display,
@@ -96,7 +96,7 @@ void intel_joiner_enabled_pipes(struct intel_display *display,
 	*secondary_pipes = 0;
 
 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc,
-					 intel_joiner_supported_pipes(i915)) {
+					 intel_joiner_supported_pipes(display)) {
 		intel_dss_get_compressed_joiner_pipes(crtc,
 						      primary_pipes,
 						      secondary_pipes);
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.h b/drivers/gpu/drm/i915/display/intel_joiner.h
index 49cb2d78f4c8..698f8e55f8ea 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.h
+++ b/drivers/gpu/drm/i915/display/intel_joiner.h
@@ -10,7 +10,6 @@
 
 enum pipe;
 struct drm_display_mode;
-struct drm_i915_private;
 struct intel_atomic_state;
 struct intel_crtc_state;
 struct intel_display;
@@ -21,7 +20,7 @@ void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,
 				 struct drm_display_mode *mode);
 void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state);
 void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state);
-u8 intel_joiner_supported_pipes(struct drm_i915_private *i915);
+u8 intel_joiner_supported_pipes(struct intel_display *display);
 void intel_joiner_enabled_pipes(struct intel_display *display,
 				u8 *primary_pipes, u8 *secondary_pipes);
 enum pipe intel_joiner_find_primary_pipe(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes);
-- 
2.45.2

✓ CI.Patch_applied: success for Consolidation of DSS Control in Separate Files (rev3)

[Patchwork]

== Series Details ==

Series: Consolidation of DSS Control in Separate Files (rev3)
URL   : https://patchwork.freedesktop.org/series/137788/
State : success

== Summary ==

=== Applying kernel patches on branch 'drm-tip' with base: ===
Base commit: d6714e4e0e19 drm-tip: 2024y-08m-30d-05h-34m-31s UTC integration manifest
=== git am output follows ===
Applying: drm/i915/display: Move all DSS control registers to a new file
Applying: drm/i915/dss_regs: Use REG_* macros for the DSS ctl bits
Applying: drm/i915/ddi: Move all mso related helpers to a new file
Applying: drm/i915/dss: Move to struct intel_display
Applying: drm/i915/icl_dsi: Avoid using intel_dsi in configure_dual_link_mode
Applying: drm/i915/icl_dsi: Use intel_display in configure_dual_link_mode
Applying: drm/i915/icl_dsi: Move helpers to configure dsi dual link to intel_dss
Applying: drm/i915/vdsc: Rename helper to check if the pipe supports dsc
Applying: drm/i915/vdsc: Move all dss stuff in dss files
Applying: drm/i915/dss: Use struct intel_display in dss dsc helpers
Applying: drm/i915/display: Move dss stuff in intel_dss files
Applying: drm/i915/display: Rename static functions that use joiner
Applying: drm/i915/display: Separate out joiner stuff in a new file
Applying: drm/i915/display: Move intel_crtc_joined_pipe_mask to intel_joiner
Applying: drm/i915/display: Move helpers for primary joiner to intel_joiner
Applying: drm/i915/display: Move intel_crtc_is_joiner_secondary to intel_joiner
Applying: drm/i915/display: Move intel_crtc_joiner_secondary_pipes to intel_joiner
Applying: drm/i915/joiner: Use struct intel_display in intel_joiner_enabled_pipes
Applying: drm/i915/joiner: Use struct intel_display in intel_joiner_supported_pipes

✗ CI.checkpatch: warning for Consolidation of DSS Control in Separate Files (rev3)

[Patchwork]

== Series Details ==

Series: Consolidation of DSS Control in Separate Files (rev3)
URL   : https://patchwork.freedesktop.org/series/137788/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
9fe5037901cabbcdf27a6fe0dfb047ca1474d363
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit b4bc1d620cfc5a18481902dedb870a580d75cff7
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Date:   Fri Aug 30 10:39:49 2024 +0530

    drm/i915/joiner: Use struct intel_display in intel_joiner_supported_pipes
    
    Replace struct drm_i915_private with struct intel_display in the helper
    intel_joiner_supported_pipes and its callers.
    
    Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+ /mt/dim checkpatch d6714e4e0e19fa8eac4d75293eaae7e479b590a3 drm-intel
f339cb474fe9 drm/i915/display: Move all DSS control registers to a new file
-:69: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#69: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 138 lines checked
66a662c4f58b drm/i915/dss_regs: Use REG_* macros for the DSS ctl bits
bfc1003b6778 drm/i915/ddi: Move all mso related helpers to a new file
-:162: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#162: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 243 lines checked
9670bafe6cf2 drm/i915/dss: Move to struct intel_display
600c22aaebb4 drm/i915/icl_dsi: Avoid using intel_dsi in configure_dual_link_mode
d2470b6b5e87 drm/i915/icl_dsi: Use intel_display in configure_dual_link_mode
7903eaf0e5d4 drm/i915/icl_dsi: Move helpers to configure dsi dual link to intel_dss
c30bd1da2b8f drm/i915/vdsc: Rename helper to check if the pipe supports dsc
10d9dc3bf5e3 drm/i915/vdsc: Move all dss stuff in dss files
bfdf825fcd26 drm/i915/dss: Use struct intel_display in dss dsc helpers
0ea60d5bbd1c drm/i915/display: Move dss stuff in intel_dss files
-:78: CHECK:SPACING: No space is necessary after a cast
#78: FILE: drivers/gpu/drm/i915/display/intel_dss.c:231:
+	power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);

total: 0 errors, 0 warnings, 1 checks, 110 lines checked
2d45fb1eae9c drm/i915/display: Rename static functions that use joiner
445bf8a9b30e drm/i915/display: Separate out joiner stuff in a new file
-:368: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#368: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 601 lines checked
a924fc50d033 drm/i915/display: Move intel_crtc_joined_pipe_mask to intel_joiner
-:89: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#89: FILE: drivers/gpu/drm/i915/display/intel_display.c:1681:
+						 intel_joiner_crtc_joined_pipe_mask(new_crtc_state)) {

-:98: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#98: FILE: drivers/gpu/drm/i915/display/intel_display.c:1692:
+						 intel_joiner_crtc_joined_pipe_mask(new_crtc_state)) {

-:107: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#107: FILE: drivers/gpu/drm/i915/display/intel_display.c:1711:
+						 intel_joiner_crtc_joined_pipe_mask(new_crtc_state)) {

-:116: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#116: FILE: drivers/gpu/drm/i915/display/intel_display.c:1747:
+						 intel_joiner_crtc_joined_pipe_mask(new_crtc_state)) {

-:143: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#143: FILE: drivers/gpu/drm/i915/display/intel_display.c:6628:
+						 intel_joiner_crtc_joined_pipe_mask(new_crtc_state)) {

total: 0 errors, 5 warnings, 0 checks, 216 lines checked
a62742a8d3da drm/i915/display: Move helpers for primary joiner to intel_joiner
1186516aa192 drm/i915/display: Move intel_crtc_is_joiner_secondary to intel_joiner
c1780ffef502 drm/i915/display: Move intel_crtc_joiner_secondary_pipes to intel_joiner
-:35: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#35: FILE: drivers/gpu/drm/i915/display/intel_display.c:5801:
+					 intel_joiner_crtc_joiner_secondary_pipes(primary_crtc_state)) {

-:44: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#44: FILE: drivers/gpu/drm/i915/display/intel_display.c:5855:
+					 intel_joiner_crtc_joiner_secondary_pipes(primary_crtc_state)) {

-:114: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#114: FILE: drivers/gpu/drm/i915/display/intel_modeset_setup.c:761:
+								 intel_joiner_crtc_joiner_secondary_pipes(crtc_state)) {

total: 0 errors, 3 warnings, 0 checks, 78 lines checked
25843674ca87 drm/i915/joiner: Use struct intel_display in intel_joiner_enabled_pipes
b4bc1d620cfc drm/i915/joiner: Use struct intel_display in intel_joiner_supported_pipes

✓ CI.KUnit: success for Consolidation of DSS Control in Separate Files (rev3)

[Patchwork]

== Series Details ==

Series: Consolidation of DSS Control in Separate Files (rev3)
URL   : https://patchwork.freedesktop.org/series/137788/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[06:11:27] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:11:31] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
  156 | u64 ioread64_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
  163 | u64 ioread64_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
  170 | u64 ioread64be_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
  178 | u64 ioread64be_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
  264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
  272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
  280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
  288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~

[06:11:57] Starting KUnit Kernel (1/1)...
[06:11:57] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:11:57] =================== guc_dbm (7 subtests) ===================
[06:11:57] [PASSED] test_empty
[06:11:57] [PASSED] test_default
[06:11:57] ======================== test_size  ========================
[06:11:57] [PASSED] 4
[06:11:57] [PASSED] 8
[06:11:57] [PASSED] 32
[06:11:57] [PASSED] 256
[06:11:57] ==================== [PASSED] test_size ====================
[06:11:57] ======================= test_reuse  ========================
[06:11:57] [PASSED] 4
[06:11:57] [PASSED] 8
[06:11:57] [PASSED] 32
[06:11:57] [PASSED] 256
[06:11:57] =================== [PASSED] test_reuse ====================
[06:11:57] =================== test_range_overlap  ====================
[06:11:57] [PASSED] 4
[06:11:57] [PASSED] 8
[06:11:57] [PASSED] 32
[06:11:57] [PASSED] 256
[06:11:57] =============== [PASSED] test_range_overlap ================
[06:11:57] =================== test_range_compact  ====================
[06:11:57] [PASSED] 4
[06:11:57] [PASSED] 8
[06:11:57] [PASSED] 32
[06:11:57] [PASSED] 256
[06:11:57] =============== [PASSED] test_range_compact ================
[06:11:57] ==================== test_range_spare  =====================
[06:11:57] [PASSED] 4
[06:11:57] [PASSED] 8
[06:11:57] [PASSED] 32
[06:11:57] [PASSED] 256
[06:11:57] ================ [PASSED] test_range_spare =================
[06:11:57] ===================== [PASSED] guc_dbm =====================
[06:11:57] =================== guc_idm (6 subtests) ===================
[06:11:57] [PASSED] bad_init
[06:11:57] [PASSED] no_init
[06:11:57] [PASSED] init_fini
[06:11:57] [PASSED] check_used
[06:11:57] [PASSED] check_quota
[06:11:57] [PASSED] check_all
[06:11:57] ===================== [PASSED] guc_idm =====================
[06:11:57] ================== no_relay (3 subtests) ===================
[06:11:57] [PASSED] xe_drops_guc2pf_if_not_ready
[06:11:57] [PASSED] xe_drops_guc2vf_if_not_ready
[06:11:57] [PASSED] xe_rejects_send_if_not_ready
[06:11:57] ==================== [PASSED] no_relay =====================
[06:11:57] ================== pf_relay (14 subtests) ==================
[06:11:57] [PASSED] pf_rejects_guc2pf_too_short
[06:11:57] [PASSED] pf_rejects_guc2pf_too_long
[06:11:57] [PASSED] pf_rejects_guc2pf_no_payload
[06:11:57] [PASSED] pf_fails_no_payload
[06:11:57] [PASSED] pf_fails_bad_origin
[06:11:57] [PASSED] pf_fails_bad_type
[06:11:57] [PASSED] pf_txn_reports_error
[06:11:57] [PASSED] pf_txn_sends_pf2guc
[06:11:57] [PASSED] pf_sends_pf2guc
[06:11:57] [SKIPPED] pf_loopback_nop
[06:11:57] [SKIPPED] pf_loopback_echo
[06:11:57] [SKIPPED] pf_loopback_fail
[06:11:57] [SKIPPED] pf_loopback_busy
[06:11:57] [SKIPPED] pf_loopback_retry
[06:11:57] ==================== [PASSED] pf_relay =====================
[06:11:57] ================== vf_relay (3 subtests) ===================
[06:11:57] [PASSED] vf_rejects_guc2vf_too_short
[06:11:57] [PASSED] vf_rejects_guc2vf_too_long
[06:11:57] [PASSED] vf_rejects_guc2vf_no_payload
[06:11:57] ==================== [PASSED] vf_relay =====================
[06:11:57] ================= pf_service (11 subtests) =================
[06:11:57] [PASSED] pf_negotiate_any
[06:11:57] [PASSED] pf_negotiate_base_match
[06:11:57] [PASSED] pf_negotiate_base_newer
[06:11:57] [PASSED] pf_negotiate_base_next
[06:11:57] [SKIPPED] pf_negotiate_base_older
[06:11:57] [PASSED] pf_negotiate_base_prev
[06:11:57] [PASSED] pf_negotiate_latest_match
[06:11:57] [PASSED] pf_negotiate_latest_newer
[06:11:57] [PASSED] pf_negotiate_latest_next
[06:11:57] [SKIPPED] pf_negotiate_latest_older
[06:11:57] [SKIPPED] pf_negotiate_latest_prev
[06:11:57] =================== [PASSED] pf_service ====================
[06:11:57] ===================== lmtt (1 subtest) =====================
[06:11:57] ======================== test_ops  =========================
[06:11:57] [PASSED] 2-level
[06:11:57] [PASSED] multi-level
[06:11:57] ==================== [PASSED] test_ops =====================
[06:11:57] ====================== [PASSED] lmtt =======================
[06:11:57] =================== xe_mocs (2 subtests) ===================
[06:11:57] ================ xe_live_mocs_kernel_kunit  ================
[06:11:57] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[06:11:57] ================ xe_live_mocs_reset_kunit  =================
[06:11:57] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[06:11:57] ==================== [SKIPPED] xe_mocs =====================
[06:11:57] ================= xe_migrate (2 subtests) ==================
[06:11:57] ================= xe_migrate_sanity_kunit  =================
[06:11:57] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[06:11:57] ================== xe_validate_ccs_kunit  ==================
[06:11:57] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[06:11:57] =================== [SKIPPED] xe_migrate ===================
[06:11:57] ================== xe_dma_buf (1 subtest) ==================
[06:11:57] ==================== xe_dma_buf_kunit  =====================
[06:11:57] ================ [SKIPPED] xe_dma_buf_kunit ================
[06:11:57] =================== [SKIPPED] xe_dma_buf ===================
[06:11:57] ==================== xe_bo (2 subtests) ====================
[06:11:57] ================== xe_ccs_migrate_kunit  ===================
[06:11:57] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[06:11:57] ==================== xe_bo_evict_kunit  ====================
[06:11:57] =============== [SKIPPED] xe_bo_evict_kunit ================
[06:11:57] ===================== [SKIPPED] xe_bo ======================
[06:11:57] ==================== args (11 subtests) ====================
[06:11:57] [PASSED] count_args_test
[06:11:57] [PASSED] call_args_example
[06:11:57] [PASSED] call_args_test
[06:11:57] [PASSED] drop_first_arg_example
[06:11:57] [PASSED] drop_first_arg_test
[06:11:57] [PASSED] first_arg_example
[06:11:57] [PASSED] first_arg_test
[06:11:57] [PASSED] last_arg_example
[06:11:57] [PASSED] last_arg_test
[06:11:57] [PASSED] pick_arg_example
[06:11:57] [PASSED] sep_comma_example
[06:11:57] ====================== [PASSED] args =======================
[06:11:57] =================== xe_pci (2 subtests) ====================
stty: 'standard input': Inappropriate ioctl for device
[06:11:57] [PASSED] xe_gmdid_graphics_ip
[06:11:57] [PASSED] xe_gmdid_media_ip
[06:11:57] ===================== [PASSED] xe_pci ======================
[06:11:57] =================== xe_rtp (2 subtests) ====================
[06:11:57] =============== xe_rtp_process_to_sr_tests  ================
[06:11:57] [PASSED] coalesce-same-reg
[06:11:57] [PASSED] no-match-no-add
[06:11:57] [PASSED] match-or
[06:11:57] [PASSED] match-or-xfail
[06:11:57] [PASSED] no-match-no-add-multiple-rules
[06:11:57] [PASSED] two-regs-two-entries
[06:11:57] [PASSED] clr-one-set-other
[06:11:57] [PASSED] set-field
[06:11:57] [PASSED] conflict-duplicate
[06:11:57] [PASSED] conflict-not-disjoint
[06:11:57] [PASSED] conflict-reg-type
[06:11:57] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[06:11:57] ================== xe_rtp_process_tests  ===================
[06:11:57] [PASSED] active1
[06:11:57] [PASSED] active2
[06:11:57] [PASSED] active-inactive
[06:11:57] [PASSED] inactive-active
[06:11:57] [PASSED] inactive-1st_or_active-inactive
[06:11:57] [PASSED] inactive-2nd_or_active-inactive
[06:11:57] [PASSED] inactive-last_or_active-inactive
[06:11:57] [PASSED] inactive-no_or_active-inactive
[06:11:57] ============== [PASSED] xe_rtp_process_tests ===============
[06:11:57] ===================== [PASSED] xe_rtp ======================
[06:11:57] ==================== xe_wa (1 subtest) =====================
[06:11:57] ======================== xe_wa_gt  =========================
[06:11:57] [PASSED] TIGERLAKE (B0)
[06:11:57] [PASSED] DG1 (A0)
[06:11:57] [PASSED] DG1 (B0)
[06:11:57] [PASSED] ALDERLAKE_S (A0)
[06:11:57] [PASSED] ALDERLAKE_S (B0)
[06:11:57] [PASSED] ALDERLAKE_S (C0)
[06:11:57] [PASSED] ALDERLAKE_S (D0)
[06:11:57] [PASSED] ALDERLAKE_P (A0)
[06:11:57] [PASSED] ALDERLAKE_P (B0)
[06:11:57] [PASSED] ALDERLAKE_P (C0)
[06:11:57] [PASSED] ALDERLAKE_S_RPLS (D0)
[06:11:57] [PASSED] ALDERLAKE_P_RPLU (E0)
[06:11:57] [PASSED] DG2_G10 (C0)
[06:11:57] [PASSED] DG2_G11 (B1)
[06:11:57] [PASSED] DG2_G12 (A1)
[06:11:57] [PASSED] METEORLAKE (g:A0, m:A0)
[06:11:57] [PASSED] METEORLAKE (g:A0, m:A0)
[06:11:57] [PASSED] METEORLAKE (g:A0, m:A0)
[06:11:57] [PASSED] LUNARLAKE (g:A0, m:A0)
[06:11:57] [PASSED] LUNARLAKE (g:B0, m:A0)
[06:11:57] [PASSED] BATTLEMAGE (g:A0, m:A1)
[06:11:57] ==================== [PASSED] xe_wa_gt =====================
[06:11:57] ====================== [PASSED] xe_wa ======================
[06:11:57] ============================================================
[06:11:57] Testing complete. Ran 121 tests: passed: 106, skipped: 15
[06:11:57] Elapsed time: 30.142s total, 4.158s configuring, 25.713s building, 0.226s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[06:11:57] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:11:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
  156 | u64 ioread64_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
  163 | u64 ioread64_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
  170 | u64 ioread64be_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
  178 | u64 ioread64be_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
  264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
  272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
  280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
  288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~

[06:12:20] Starting KUnit Kernel (1/1)...
[06:12:20] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:12:20] ============ drm_test_pick_cmdline (2 subtests) ============
[06:12:20] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[06:12:20] =============== drm_test_pick_cmdline_named  ===============
[06:12:20] [PASSED] NTSC
[06:12:20] [PASSED] NTSC-J
[06:12:20] [PASSED] PAL
[06:12:20] [PASSED] PAL-M
[06:12:20] =========== [PASSED] drm_test_pick_cmdline_named ===========
[06:12:20] ============== [PASSED] drm_test_pick_cmdline ==============
[06:12:20] ================== drm_buddy (7 subtests) ==================
[06:12:20] [PASSED] drm_test_buddy_alloc_limit
[06:12:20] [PASSED] drm_test_buddy_alloc_optimistic
[06:12:20] [PASSED] drm_test_buddy_alloc_pessimistic
[06:12:20] [PASSED] drm_test_buddy_alloc_pathological
[06:12:20] [PASSED] drm_test_buddy_alloc_contiguous
[06:12:20] [PASSED] drm_test_buddy_alloc_clear
[06:12:20] [PASSED] drm_test_buddy_alloc_range_bias
[06:12:20] ==================== [PASSED] drm_buddy ====================
[06:12:20] ============= drm_cmdline_parser (40 subtests) =============
[06:12:20] [PASSED] drm_test_cmdline_force_d_only
[06:12:20] [PASSED] drm_test_cmdline_force_D_only_dvi
[06:12:20] [PASSED] drm_test_cmdline_force_D_only_hdmi
[06:12:20] [PASSED] drm_test_cmdline_force_D_only_not_digital
[06:12:20] [PASSED] drm_test_cmdline_force_e_only
[06:12:20] [PASSED] drm_test_cmdline_res
[06:12:20] [PASSED] drm_test_cmdline_res_vesa
[06:12:20] [PASSED] drm_test_cmdline_res_vesa_rblank
[06:12:20] [PASSED] drm_test_cmdline_res_rblank
[06:12:20] [PASSED] drm_test_cmdline_res_bpp
[06:12:20] [PASSED] drm_test_cmdline_res_refresh
[06:12:20] [PASSED] drm_test_cmdline_res_bpp_refresh
[06:12:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[06:12:20] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[06:12:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[06:12:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[06:12:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[06:12:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[06:12:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[06:12:20] [PASSED] drm_test_cmdline_res_margins_force_on
[06:12:20] [PASSED] drm_test_cmdline_res_vesa_margins
[06:12:20] [PASSED] drm_test_cmdline_name
[06:12:20] [PASSED] drm_test_cmdline_name_bpp
[06:12:20] [PASSED] drm_test_cmdline_name_option
[06:12:20] [PASSED] drm_test_cmdline_name_bpp_option
[06:12:20] [PASSED] drm_test_cmdline_rotate_0
[06:12:20] [PASSED] drm_test_cmdline_rotate_90
[06:12:20] [PASSED] drm_test_cmdline_rotate_180
[06:12:20] [PASSED] drm_test_cmdline_rotate_270
[06:12:20] [PASSED] drm_test_cmdline_hmirror
[06:12:20] [PASSED] drm_test_cmdline_vmirror
[06:12:20] [PASSED] drm_test_cmdline_margin_options
[06:12:20] [PASSED] drm_test_cmdline_multiple_options
[06:12:20] [PASSED] drm_test_cmdline_bpp_extra_and_option
[06:12:20] [PASSED] drm_test_cmdline_extra_and_option
[06:12:20] [PASSED] drm_test_cmdline_freestanding_options
[06:12:20] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[06:12:20] [PASSED] drm_test_cmdline_panel_orientation
[06:12:20] ================ drm_test_cmdline_invalid  =================
[06:12:20] [PASSED] margin_only
[06:12:20] [PASSED] interlace_only
[06:12:20] [PASSED] res_missing_x
[06:12:20] [PASSED] res_missing_y
[06:12:20] [PASSED] res_bad_y
[06:12:20] [PASSED] res_missing_y_bpp
[06:12:20] [PASSED] res_bad_bpp
[06:12:20] [PASSED] res_bad_refresh
[06:12:20] [PASSED] res_bpp_refresh_force_on_off
[06:12:20] [PASSED] res_invalid_mode
[06:12:20] [PASSED] res_bpp_wrong_place_mode
[06:12:20] [PASSED] name_bpp_refresh
[06:12:20] [PASSED] name_refresh
[06:12:20] [PASSED] name_refresh_wrong_mode
[06:12:20] [PASSED] name_refresh_invalid_mode
[06:12:20] [PASSED] rotate_multiple
[06:12:20] [PASSED] rotate_invalid_val
[06:12:20] [PASSED] rotate_truncated
[06:12:20] [PASSED] invalid_option
[06:12:20] [PASSED] invalid_tv_option
[06:12:20] [PASSED] truncated_tv_option
[06:12:20] ============ [PASSED] drm_test_cmdline_invalid =============
[06:12:20] =============== drm_test_cmdline_tv_options  ===============
[06:12:20] [PASSED] NTSC
[06:12:20] [PASSED] NTSC_443
[06:12:20] [PASSED] NTSC_J
[06:12:20] [PASSED] PAL
[06:12:20] [PASSED] PAL_M
[06:12:20] [PASSED] PAL_N
[06:12:20] [PASSED] SECAM
[06:12:20] [PASSED] MONO_525
[06:12:20] [PASSED] MONO_625
[06:12:20] =========== [PASSED] drm_test_cmdline_tv_options ===========
[06:12:20] =============== [PASSED] drm_cmdline_parser ================
[06:12:20] ========== drmm_connector_hdmi_init (19 subtests) ==========
[06:12:20] [PASSED] drm_test_connector_hdmi_init_valid
[06:12:20] [PASSED] drm_test_connector_hdmi_init_bpc_8
[06:12:20] [PASSED] drm_test_connector_hdmi_init_bpc_10
[06:12:20] [PASSED] drm_test_connector_hdmi_init_bpc_12
[06:12:20] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[06:12:20] [PASSED] drm_test_connector_hdmi_init_bpc_null
[06:12:20] [PASSED] drm_test_connector_hdmi_init_formats_empty
[06:12:20] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[06:12:20] [PASSED] drm_test_connector_hdmi_init_null_ddc
[06:12:20] [PASSED] drm_test_connector_hdmi_init_null_product
[06:12:20] [PASSED] drm_test_connector_hdmi_init_null_vendor
[06:12:20] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[06:12:20] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[06:12:20] [PASSED] drm_test_connector_hdmi_init_product_valid
[06:12:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[06:12:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[06:12:20] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[06:12:20] ========= drm_test_connector_hdmi_init_type_valid  =========
[06:12:20] [PASSED] HDMI-A
[06:12:20] [PASSED] HDMI-B
[06:12:20] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[06:12:20] ======== drm_test_connector_hdmi_init_type_invalid  ========
[06:12:20] [PASSED] Unknown
[06:12:20] [PASSED] VGA
[06:12:20] [PASSED] DVI-I
[06:12:20] [PASSED] DVI-D
[06:12:20] [PASSED] DVI-A
[06:12:20] [PASSED] Composite
[06:12:20] [PASSED] SVIDEO
[06:12:20] [PASSED] LVDS
[06:12:20] [PASSED] Component
[06:12:20] [PASSED] DIN
[06:12:20] [PASSED] DP
[06:12:20] [PASSED] TV
[06:12:20] [PASSED] eDP
[06:12:20] [PASSED] Virtual
[06:12:20] [PASSED] DSI
[06:12:20] [PASSED] DPI
[06:12:20] [PASSED] Writeback
[06:12:20] [PASSED] SPI
[06:12:20] [PASSED] USB
[06:12:20] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[06:12:20] ============ [PASSED] drmm_connector_hdmi_init =============
[06:12:20] ============= drmm_connector_init (3 subtests) =============
[06:12:20] [PASSED] drm_test_drmm_connector_init
[06:12:20] [PASSED] drm_test_drmm_connector_init_null_ddc
[06:12:20] ========= drm_test_drmm_connector_init_type_valid  =========
[06:12:20] [PASSED] Unknown
[06:12:20] [PASSED] VGA
[06:12:20] [PASSED] DVI-I
[06:12:20] [PASSED] DVI-D
[06:12:20] [PASSED] DVI-A
[06:12:20] [PASSED] Composite
[06:12:20] [PASSED] SVIDEO
[06:12:20] [PASSED] LVDS
[06:12:20] [PASSED] Component
[06:12:20] [PASSED] DIN
[06:12:20] [PASSED] DP
[06:12:20] [PASSED] HDMI-A
[06:12:20] [PASSED] HDMI-B
[06:12:20] [PASSED] TV
[06:12:20] [PASSED] eDP
[06:12:20] [PASSED] Virtual
[06:12:20] [PASSED] DSI
[06:12:20] [PASSED] DPI
[06:12:20] [PASSED] Writeback
[06:12:20] [PASSED] SPI
[06:12:20] [PASSED] USB
[06:12:20] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[06:12:20] =============== [PASSED] drmm_connector_init ===============
[06:12:20] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[06:12:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[06:12:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[06:12:20] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[06:12:20] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[06:12:20] ========== drm_test_get_tv_mode_from_name_valid  ===========
[06:12:20] [PASSED] NTSC
[06:12:20] [PASSED] NTSC-443
[06:12:20] [PASSED] NTSC-J
[06:12:20] [PASSED] PAL
[06:12:20] [PASSED] PAL-M
[06:12:20] [PASSED] PAL-N
[06:12:20] [PASSED] SECAM
[06:12:20] [PASSED] Mono
[06:12:20] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[06:12:20] [PASSED] drm_test_get_tv_mode_from_name_truncated
[06:12:20] ============ [PASSED] drm_get_tv_mode_from_name ============
[06:12:20] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[06:12:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[06:12:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[06:12:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[06:12:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[06:12:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[06:12:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[06:12:20] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[06:12:20] [PASSED] VIC 96
[06:12:20] [PASSED] VIC 97
[06:12:20] [PASSED] VIC 101
[06:12:20] [PASSED] VIC 102
[06:12:20] [PASSED] VIC 106
[06:12:20] [PASSED] VIC 107
[06:12:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[06:12:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[06:12:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[06:12:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[06:12:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[06:12:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[06:12:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[06:12:20] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[06:12:20] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[06:12:20] [PASSED] Automatic
[06:12:20] [PASSED] Full
[06:12:20] [PASSED] Limited 16:235
[06:12:20] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[06:12:20] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[06:12:20] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[06:12:20] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[06:12:20] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[06:12:20] [PASSED] RGB
[06:12:20] [PASSED] YUV 4:2:0
[06:12:20] [PASSED] YUV 4:2:2
[06:12:20] [PASSED] YUV 4:4:4
[06:12:20] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[06:12:20] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[06:12:20] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[06:12:20] ============= drm_damage_helper (21 subtests) ==============
[06:12:20] [PASSED] drm_test_damage_iter_no_damage
[06:12:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[06:12:20] [PASSED] drm_test_damage_iter_no_damage_src_moved
[06:12:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[06:12:20] [PASSED] drm_test_damage_iter_no_damage_not_visible
[06:12:20] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[06:12:20] [PASSED] drm_test_damage_iter_no_damage_no_fb
[06:12:20] [PASSED] drm_test_damage_iter_simple_damage
[06:12:20] [PASSED] drm_test_damage_iter_single_damage
[06:12:20] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[06:12:20] [PASSED] drm_test_damage_iter_single_damage_outside_src
[06:12:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[06:12:20] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[06:12:20] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[06:12:20] [PASSED] drm_test_damage_iter_single_damage_src_moved
[06:12:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[06:12:20] [PASSED] drm_test_damage_iter_damage
[06:12:20] [PASSED] drm_test_damage_iter_damage_one_intersect
[06:12:20] [PASSED] drm_test_damage_iter_damage_one_outside
[06:12:20] [PASSED] drm_test_damage_iter_damage_src_moved
[06:12:20] [PASSED] drm_test_damage_iter_damage_not_visible
[06:12:20] ================ [PASSED] drm_damage_helper ================
[06:12:20] ============== drm_dp_mst_helper (3 subtests) ==============
[06:12:20] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[06:12:20] [PASSED] Clock 154000 BPP 30 DSC disabled
[06:12:20] [PASSED] Clock 234000 BPP 30 DSC disabled
[06:12:20] [PASSED] Clock 297000 BPP 24 DSC disabled
[06:12:20] [PASSED] Clock 332880 BPP 24 DSC enabled
[06:12:20] [PASSED] Clock 324540 BPP 24 DSC enabled
[06:12:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[06:12:20] ============== drm_test_dp_mst_calc_pbn_div  ===============
[06:12:20] [PASSED] Link rate 2000000 lane count 4
[06:12:20] [PASSED] Link rate 2000000 lane count 2
[06:12:20] [PASSED] Link rate 2000000 lane count 1
[06:12:20] [PASSED] Link rate 1350000 lane count 4
[06:12:20] [PASSED] Link rate 1350000 lane count 2
[06:12:20] [PASSED] Link rate 1350000 lane count 1
[06:12:20] [PASSED] Link rate 1000000 lane count 4
[06:12:20] [PASSED] Link rate 1000000 lane count 2
[06:12:20] [PASSED] Link rate 1000000 lane count 1
[06:12:20] [PASSED] Link rate 810000 lane count 4
[06:12:20] [PASSED] Link rate 810000 lane count 2
[06:12:20] [PASSED] Link rate 810000 lane count 1
[06:12:20] [PASSED] Link rate 540000 lane count 4
[06:12:20] [PASSED] Link rate 540000 lane count 2
[06:12:20] [PASSED] Link rate 540000 lane count 1
[06:12:20] [PASSED] Link rate 270000 lane count 4
[06:12:20] [PASSED] Link rate 270000 lane count 2
[06:12:20] [PASSED] Link rate 270000 lane count 1
[06:12:20] [PASSED] Link rate 162000 lane count 4
[06:12:20] [PASSED] Link rate 162000 lane count 2
[06:12:20] [PASSED] Link rate 162000 lane count 1
[06:12:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[06:12:20] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[06:12:20] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[06:12:20] [PASSED] DP_POWER_UP_PHY with port number
[06:12:20] [PASSED] DP_POWER_DOWN_PHY with port number
[06:12:20] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[06:12:20] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[06:12:20] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[06:12:20] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[06:12:20] [PASSED] DP_QUERY_PAYLOAD with port number
[06:12:20] [PASSED] DP_QUERY_PAYLOAD with VCPI
[06:12:20] [PASSED] DP_REMOTE_DPCD_READ with port number
[06:12:20] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[06:12:20] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[06:12:20] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[06:12:20] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[06:12:20] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[06:12:20] [PASSED] DP_REMOTE_I2C_READ with port number
[06:12:20] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[06:12:20] [PASSED] DP_REMOTE_I2C_READ with transactions array
[06:12:20] [PASSED] DP_REMOTE_I2C_WRITE with port number
[06:12:20] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[06:12:20] [PASSED] DP_REMOTE_I2C_WRITE with data array
[06:12:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[06:12:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[06:12:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[06:12:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[06:12:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[06:12:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[06:12:20] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[06:12:20] ================ [PASSED] drm_dp_mst_helper ================
[06:12:20] ================== drm_exec (7 subtests) ===================
[06:12:20] [PASSED] sanitycheck
[06:12:20] [PASSED] test_lock
[06:12:20] [PASSED] test_lock_unlock
[06:12:20] [PASSED] test_duplicates
[06:12:20] [PASSED] test_prepare
[06:12:20] [PASSED] test_prepare_array
[06:12:20] [PASSED] test_multiple_loops
[06:12:20] ==================== [PASSED] drm_exec =====================
[06:12:20] =========== drm_format_helper_test (17 subtests) ===========
[06:12:20] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[06:12:20] [PASSED] single_pixel_source_buffer
[06:12:20] [PASSED] single_pixel_clip_rectangle
[06:12:20] [PASSED] well_known_colors
[06:12:20] [PASSED] destination_pitch
[06:12:20] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[06:12:20] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[06:12:20] [PASSED] single_pixel_source_buffer
[06:12:20] [PASSED] single_pixel_clip_rectangle
[06:12:20] [PASSED] well_known_colors
[06:12:20] [PASSED] destination_pitch
[06:12:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[06:12:20] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[06:12:20] [PASSED] single_pixel_source_buffer
[06:12:20] [PASSED] single_pixel_clip_rectangle
[06:12:20] [PASSED] well_known_colors
[06:12:20] [PASSED] destination_pitch
[06:12:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[06:12:20] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[06:12:20] [PASSED] single_pixel_source_buffer
[06:12:20] [PASSED] single_pixel_clip_rectangle
[06:12:20] [PASSED] well_known_colors
[06:12:20] [PASSED] destination_pitch
[06:12:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[06:12:20] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[06:12:20] [PASSED] single_pixel_source_buffer
[06:12:20] [PASSED] single_pixel_clip_rectangle
[06:12:20] [PASSED] well_known_colors
[06:12:20] [PASSED] destination_pitch
[06:12:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[06:12:20] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[06:12:20] [PASSED] single_pixel_source_buffer
[06:12:20] [PASSED] single_pixel_clip_rectangle
[06:12:20] [PASSED] well_known_colors
[06:12:20] [PASSED] destination_pitch
[06:12:20] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[06:12:20] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[06:12:20] [PASSED] single_pixel_source_buffer
[06:12:20] [PASSED] single_pixel_clip_rectangle
[06:12:20] [PASSED] well_known_colors
[06:12:20] [PASSED] destination_pitch
[06:12:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[06:12:20] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[06:12:20] [PASSED] single_pixel_source_buffer
[06:12:20] [PASSED] single_pixel_clip_rectangle
[06:12:20] [PASSED] well_known_colors
[06:12:20] [PASSED] destination_pitch
[06:12:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[06:12:20] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[06:12:20] [PASSED] single_pixel_source_buffer
[06:12:20] [PASSED] single_pixel_clip_rectangle
[06:12:20] [PASSED] well_known_colors
[06:12:20] [PASSED] destination_pitch
[06:12:20] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[06:12:20] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[06:12:20] [PASSED] single_pixel_source_buffer
[06:12:20] [PASSED] single_pixel_clip_rectangle
[06:12:20] [PASSED] well_known_colors
[06:12:20] [PASSED] destination_pitch
[06:12:20] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[06:12:20] ============== drm_test_fb_xrgb8888_to_mono  ===============
[06:12:20] [PASSED] single_pixel_source_buffer
[06:12:20] [PASSED] single_pixel_clip_rectangle
[06:12:20] [PASSED] well_known_colors
[06:12:20] [PASSED] destination_pitch
[06:12:20] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[06:12:20] ==================== drm_test_fb_swab  =====================
[06:12:20] [PASSED] single_pixel_source_buffer
[06:12:20] [PASSED] single_pixel_clip_rectangle
[06:12:20] [PASSED] well_known_colors
[06:12:20] [PASSED] destination_pitch
[06:12:20] ================ [PASSED] drm_test_fb_swab =================
[06:12:20] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[06:12:20] [PASSED] single_pixel_source_buffer
[06:12:20] [PASSED] single_pixel_clip_rectangle
[06:12:20] [PASSED] well_known_colors
[06:12:20] [PASSED] destination_pitch
[06:12:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[06:12:20] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[06:12:20] [PASSED] single_pixel_source_buffer
[06:12:20] [PASSED] single_pixel_clip_rectangle
[06:12:20] [PASSED] well_known_colors
[06:12:20] [PASSED] destination_pitch
[06:12:20] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[06:12:20] ================= drm_test_fb_clip_offset  =================
[06:12:20] [PASSED] pass through
[06:12:20] [PASSED] horizontal offset
[06:12:20] [PASSED] vertical offset
[06:12:20] [PASSED] horizontal and vertical offset
[06:12:20] [PASSED] horizontal offset (custom pitch)
[06:12:20] [PASSED] vertical offset (custom pitch)
[06:12:20] [PASSED] horizontal and vertical offset (custom pitch)
[06:12:20] ============= [PASSED] drm_test_fb_clip_offset =============
[06:12:20] ============== drm_test_fb_build_fourcc_list  ==============
[06:12:20] [PASSED] no native formats
[06:12:20] [PASSED] XRGB8888 as native format
[06:12:20] [PASSED] remove duplicates
[06:12:20] [PASSED] convert alpha formats
[06:12:20] [PASSED] random formats
[06:12:20] ========== [PASSED] drm_test_fb_build_fourcc_list ==========
[06:12:20] =================== drm_test_fb_memcpy  ====================
[06:12:20] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[06:12:20] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[06:12:20] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[06:12:20] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[06:12:20] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[06:12:20] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[06:12:20] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[06:12:20] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[06:12:20] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[06:12:20] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[06:12:20] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[06:12:20] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[06:12:20] =============== [PASSED] drm_test_fb_memcpy ================
[06:12:20] ============= [PASSED] drm_format_helper_test ==============
[06:12:20] ================= drm_format (18 subtests) =================
[06:12:20] [PASSED] drm_test_format_block_width_invalid
[06:12:20] [PASSED] drm_test_format_block_width_one_plane
[06:12:20] [PASSED] drm_test_format_block_width_two_plane
[06:12:20] [PASSED] drm_test_format_block_width_three_plane
[06:12:20] [PASSED] drm_test_format_block_width_tiled
[06:12:20] [PASSED] drm_test_format_block_height_invalid
[06:12:20] [PASSED] drm_test_format_block_height_one_plane
[06:12:20] [PASSED] drm_test_format_block_height_two_plane
[06:12:20] [PASSED] drm_test_format_block_height_three_plane
[06:12:20] [PASSED] drm_test_format_block_height_tiled
[06:12:20] [PASSED] drm_test_format_min_pitch_invalid
[06:12:20] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[06:12:20] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[06:12:20] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[06:12:20] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[06:12:20] [PASSED] drm_test_format_min_pitch_two_plane
[06:12:20] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[06:12:20] [PASSED] drm_test_format_min_pitch_tiled
[06:12:20] =================== [PASSED] drm_format ====================
[06:12:20] =============== drm_framebuffer (1 subtest) ================
[06:12:20] =============== drm_test_framebuffer_create  ===============
[06:12:20] [PASSED] ABGR8888 normal sizes
[06:12:20] [PASSED] ABGR8888 max sizes
[06:12:20] [PASSED] ABGR8888 pitch greater than min required
[06:12:20] [PASSED] ABGR8888 pitch less than min required
[06:12:20] [PASSED] ABGR8888 Invalid width
[06:12:20] [PASSED] ABGR8888 Invalid buffer handle
[06:12:20] [PASSED] No pixel format
[06:12:20] [PASSED] ABGR8888 Width 0
[06:12:20] [PASSED] ABGR8888 Height 0
[06:12:20] [PASSED] ABGR8888 Out of bound height * pitch combination
[06:12:20] [PASSED] ABGR8888 Large buffer offset
[06:12:20] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[06:12:20] [PASSED] ABGR8888 Valid buffer modifier
[06:12:20] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[06:12:20] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[06:12:20] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[06:12:20] [PASSED] NV12 Normal sizes
[06:12:20] [PASSED] NV12 Max sizes
[06:12:20] [PASSED] NV12 Invalid pitch
[06:12:20] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[06:12:20] [PASSED] NV12 different  modifier per-plane
[06:12:20] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[06:12:20] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[06:12:20] [PASSED] NV12 Modifier for inexistent plane
[06:12:20] [PASSED] NV12 Handle for inexistent plane
[06:12:20] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[06:12:20] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[06:12:20] [PASSED] YVU420 Normal sizes
[06:12:20] [PASSED] YVU420 Max sizes
[06:12:20] [PASSED] YVU420 Invalid pitch
[06:12:20] [PASSED] YVU420 Different pitches
[06:12:20] [PASSED] YVU420 Different buffer offsets/pitches
[06:12:20] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[06:12:20] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[06:12:20] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[06:12:20] [PASSED] YVU420 Valid modifier
[06:12:20] [PASSED] YVU420 Different modifiers per plane
[06:12:20] [PASSED] YVU420 Modifier for inexistent plane
[06:12:20] [PASSED] X0L2 Normal sizes
[06:12:20] [PASSED] X0L2 Max sizes
[06:12:20] [PASSED] X0L2 Invalid pitch
[06:12:20] [PASSED] X0L2 Pitch greater than minimum required
[06:12:20] [PASSED] X0L2 Handle for inexistent plane
[06:12:20] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[06:12:20] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[06:12:20] [PASSED] X0L2 Valid modifier
[06:12:20] [PASSED] X0L2 Modifier for inexistent plane
[06:12:20] =========== [PASSED] drm_test_framebuffer_create ===========
[06:12:20] ================= [PASSED] drm_framebuffer =================
[06:12:20] ================ drm_gem_shmem (8 subtests) ================
[06:12:20] [PASSED] drm_gem_shmem_test_obj_create
[06:12:20] [PASSED] drm_gem_shmem_test_obj_create_private
[06:12:20] [PASSED] drm_gem_shmem_test_pin_pages
[06:12:20] [PASSED] drm_gem_shmem_test_vmap
[06:12:20] [PASSED] drm_gem_shmem_test_get_pages_sgt
[06:12:20] [PASSED] drm_gem_shmem_test_get_sg_table
[06:12:20] [PASSED] drm_gem_shmem_test_madvise
[06:12:20] [PASSED] drm_gem_shmem_test_purge
[06:12:20] ================== [PASSED] drm_gem_shmem ==================
[06:12:20] === drm_atomic_helper_connector_hdmi_check (22 subtests) ===
[06:12:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[06:12:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[06:12:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[06:12:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[06:12:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[06:12:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[06:12:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[06:12:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[06:12:20] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[06:12:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback
[06:12:20] [PASSED] drm_test_check_max_tmds_rate_format_fallback
[06:12:20] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[06:12:20] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[06:12:20] [PASSED] drm_test_check_output_bpc_dvi
[06:12:20] [PASSED] drm_test_check_output_bpc_format_vic_1
[06:12:20] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[06:12:20] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[06:12:20] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[06:12:20] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[06:12:20] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[06:12:20] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[06:12:20] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[06:12:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[06:12:20] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[06:12:20] [PASSED] drm_test_check_broadcast_rgb_value
[06:12:20] [PASSED] drm_test_check_bpc_8_value
[06:12:20] [PASSED] drm_test_check_bpc_10_value
[06:12:20] [PASSED] drm_test_check_bpc_12_value
[06:12:20] [PASSED] drm_test_check_format_value
[06:12:20] [PASSED] drm_test_check_tmds_char_value
[06:12:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[06:12:20] ================= drm_managed (2 subtests) =================
[06:12:20] [PASSED] drm_test_managed_release_action
[06:12:20] [PASSED] drm_test_managed_run_action
[06:12:20] =================== [PASSED] drm_managed ===================
[06:12:20] =================== drm_mm (6 subtests) ====================
[06:12:20] [PASSED] drm_test_mm_init
[06:12:20] [PASSED] drm_test_mm_debug
[06:12:20] [PASSED] drm_test_mm_align32
[06:12:20] [PASSED] drm_test_mm_align64
[06:12:20] [PASSED] drm_test_mm_lowest
[06:12:20] [PASSED] drm_test_mm_highest
[06:12:20] ===================== [PASSED] drm_mm ======================
[06:12:20] ============= drm_modes_analog_tv (5 subtests) =============
[06:12:20] [PASSED] drm_test_modes_analog_tv_mono_576i
[06:12:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[06:12:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[06:12:20] [PASSED] drm_test_modes_analog_tv_pal_576i
[06:12:20] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[06:12:20] =============== [PASSED] drm_modes_analog_tv ===============
[06:12:20] ============== drm_plane_helper (2 subtests) ===============
[06:12:20] =============== drm_test_check_plane_state  ================
[06:12:20] [PASSED] clipping_simple
[06:12:20] [PASSED] clipping_rotate_reflect
[06:12:20] [PASSED] positioning_simple
[06:12:20] [PASSED] upscaling
[06:12:20] [PASSED] downscaling
[06:12:20] [PASSED] rounding1
[06:12:20] [PASSED] rounding2
[06:12:20] [PASSED] rounding3
[06:12:20] [PASSED] rounding4
[06:12:20] =========== [PASSED] drm_test_check_plane_state ============
[06:12:20] =========== drm_test_check_invalid_plane_state  ============
[06:12:20] [PASSED] positioning_invalid
[06:12:20] [PASSED] upscaling_invalid
stty: 'standard input': Inappropriate ioctl for device
[06:12:20] [PASSED] downscaling_invalid
[06:12:20] ======= [PASSED] drm_test_check_invalid_plane_state ========
[06:12:20] ================ [PASSED] drm_plane_helper =================
[06:12:20] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[06:12:20] ====== drm_test_connector_helper_tv_get_modes_check  =======
[06:12:20] [PASSED] None
[06:12:20] [PASSED] PAL
[06:12:20] [PASSED] NTSC
[06:12:20] [PASSED] Both, NTSC Default
[06:12:20] [PASSED] Both, PAL Default
[06:12:20] [PASSED] Both, NTSC Default, with PAL on command-line
[06:12:20] [PASSED] Both, PAL Default, with NTSC on command-line
[06:12:20] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[06:12:20] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[06:12:20] ================== drm_rect (9 subtests) ===================
[06:12:20] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[06:12:20] [PASSED] drm_test_rect_clip_scaled_not_clipped
[06:12:20] [PASSED] drm_test_rect_clip_scaled_clipped
[06:12:20] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[06:12:20] ================= drm_test_rect_intersect  =================
[06:12:20] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[06:12:20] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[06:12:20] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[06:12:20] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[06:12:20] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[06:12:20] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[06:12:20] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[06:12:20] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[06:12:20] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[06:12:20] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[06:12:20] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[06:12:20] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[06:12:20] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[06:12:20] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[06:12:20] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[06:12:20] ============= [PASSED] drm_test_rect_intersect =============
[06:12:20] ================ drm_test_rect_calc_hscale  ================
[06:12:20] [PASSED] normal use
[06:12:20] [PASSED] out of max range
[06:12:20] [PASSED] out of min range
[06:12:20] [PASSED] zero dst
[06:12:20] [PASSED] negative src
[06:12:20] [PASSED] negative dst
[06:12:20] ============ [PASSED] drm_test_rect_calc_hscale ============
[06:12:20] ================ drm_test_rect_calc_vscale  ================
[06:12:20] [PASSED] normal use
[06:12:20] [PASSED] out of max range
[06:12:20] [PASSED] out of min range
[06:12:20] [PASSED] zero dst
[06:12:20] [PASSED] negative src
[06:12:20] [PASSED] negative dst
[06:12:20] ============ [PASSED] drm_test_rect_calc_vscale ============
[06:12:20] ================== drm_test_rect_rotate  ===================
[06:12:20] [PASSED] reflect-x
[06:12:20] [PASSED] reflect-y
[06:12:20] [PASSED] rotate-0
[06:12:20] [PASSED] rotate-90
[06:12:20] [PASSED] rotate-180
[06:12:20] [PASSED] rotate-270
[06:12:20] ============== [PASSED] drm_test_rect_rotate ===============
[06:12:20] ================ drm_test_rect_rotate_inv  =================
[06:12:20] [PASSED] reflect-x
[06:12:20] [PASSED] reflect-y
[06:12:20] [PASSED] rotate-0
[06:12:20] [PASSED] rotate-90
[06:12:20] [PASSED] rotate-180
[06:12:20] [PASSED] rotate-270
[06:12:20] ============ [PASSED] drm_test_rect_rotate_inv =============
[06:12:20] ==================== [PASSED] drm_rect =====================
[06:12:20] ============================================================
[06:12:20] Testing complete. Ran 515 tests: passed: 515
[06:12:20] Elapsed time: 23.312s total, 1.740s configuring, 21.402s building, 0.157s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[06:12:20] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:12:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[06:12:31] Starting KUnit Kernel (1/1)...
[06:12:31] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:12:31] ================= ttm_device (5 subtests) ==================
[06:12:31] [PASSED] ttm_device_init_basic
[06:12:31] [PASSED] ttm_device_init_multiple
[06:12:31] [PASSED] ttm_device_fini_basic
[06:12:31] [PASSED] ttm_device_init_no_vma_man
[06:12:31] ================== ttm_device_init_pools  ==================
[06:12:31] [PASSED] No DMA allocations, no DMA32 required
[06:12:31] [PASSED] DMA allocations, DMA32 required
[06:12:31] [PASSED] No DMA allocations, DMA32 required
[06:12:31] [PASSED] DMA allocations, no DMA32 required
[06:12:31] ============== [PASSED] ttm_device_init_pools ==============
[06:12:31] =================== [PASSED] ttm_device ====================
[06:12:31] ================== ttm_pool (8 subtests) ===================
[06:12:31] ================== ttm_pool_alloc_basic  ===================
[06:12:31] [PASSED] One page
[06:12:31] [PASSED] More than one page
[06:12:31] [PASSED] Above the allocation limit
[06:12:31] [PASSED] One page, with coherent DMA mappings enabled
[06:12:31] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:12:31] ============== [PASSED] ttm_pool_alloc_basic ===============
[06:12:31] ============== ttm_pool_alloc_basic_dma_addr  ==============
[06:12:31] [PASSED] One page
[06:12:31] [PASSED] More than one page
[06:12:31] [PASSED] Above the allocation limit
[06:12:31] [PASSED] One page, with coherent DMA mappings enabled
[06:12:31] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:12:31] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[06:12:31] [PASSED] ttm_pool_alloc_order_caching_match
[06:12:31] [PASSED] ttm_pool_alloc_caching_mismatch
[06:12:31] [PASSED] ttm_pool_alloc_order_mismatch
[06:12:31] [PASSED] ttm_pool_free_dma_alloc
[06:12:31] [PASSED] ttm_pool_free_no_dma_alloc
[06:12:31] [PASSED] ttm_pool_fini_basic
[06:12:31] ==================== [PASSED] ttm_pool =====================
[06:12:31] ================ ttm_resource (8 subtests) =================
[06:12:31] ================= ttm_resource_init_basic  =================
[06:12:31] [PASSED] Init resource in TTM_PL_SYSTEM
[06:12:31] [PASSED] Init resource in TTM_PL_VRAM
[06:12:31] [PASSED] Init resource in a private placement
[06:12:31] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[06:12:31] ============= [PASSED] ttm_resource_init_basic =============
[06:12:31] [PASSED] ttm_resource_init_pinned
[06:12:31] [PASSED] ttm_resource_fini_basic
[06:12:31] [PASSED] ttm_resource_manager_init_basic
[06:12:31] [PASSED] ttm_resource_manager_usage_basic
[06:12:31] [PASSED] ttm_resource_manager_set_used_basic
[06:12:31] [PASSED] ttm_sys_man_alloc_basic
[06:12:31] [PASSED] ttm_sys_man_free_basic
[06:12:31] ================== [PASSED] ttm_resource ===================
[06:12:31] =================== ttm_tt (15 subtests) ===================
[06:12:31] ==================== ttm_tt_init_basic  ====================
[06:12:31] [PASSED] Page-aligned size
[06:12:31] [PASSED] Extra pages requested
[06:12:31] ================ [PASSED] ttm_tt_init_basic ================
[06:12:31] [PASSED] ttm_tt_init_misaligned
[06:12:31] [PASSED] ttm_tt_fini_basic
[06:12:31] [PASSED] ttm_tt_fini_sg
[06:12:31] [PASSED] ttm_tt_fini_shmem
[06:12:31] [PASSED] ttm_tt_create_basic
[06:12:31] [PASSED] ttm_tt_create_invalid_bo_type
[06:12:31] [PASSED] ttm_tt_create_ttm_exists
[06:12:31] [PASSED] ttm_tt_create_failed
[06:12:31] [PASSED] ttm_tt_destroy_basic
[06:12:31] [PASSED] ttm_tt_populate_null_ttm
[06:12:31] [PASSED] ttm_tt_populate_populated_ttm
[06:12:31] [PASSED] ttm_tt_unpopulate_basic
[06:12:31] [PASSED] ttm_tt_unpopulate_empty_ttm
[06:12:31] [PASSED] ttm_tt_swapin_basic
[06:12:31] ===================== [PASSED] ttm_tt ======================
[06:12:31] =================== ttm_bo (14 subtests) ===================
[06:12:31] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[06:12:31] [PASSED] Cannot be interrupted and sleeps
[06:12:31] [PASSED] Cannot be interrupted, locks straight away
[06:12:31] [PASSED] Can be interrupted, sleeps
[06:12:31] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[06:12:31] [PASSED] ttm_bo_reserve_locked_no_sleep
[06:12:31] [PASSED] ttm_bo_reserve_no_wait_ticket
[06:12:31] [PASSED] ttm_bo_reserve_double_resv
[06:12:31] [PASSED] ttm_bo_reserve_interrupted
[06:12:31] [PASSED] ttm_bo_reserve_deadlock
[06:12:31] [PASSED] ttm_bo_unreserve_basic
[06:12:31] [PASSED] ttm_bo_unreserve_pinned
[06:12:31] [PASSED] ttm_bo_unreserve_bulk
[06:12:31] [PASSED] ttm_bo_put_basic
[06:12:31] [PASSED] ttm_bo_put_shared_resv
[06:12:31] [PASSED] ttm_bo_pin_basic
[06:12:31] [PASSED] ttm_bo_pin_unpin_resource
[06:12:31] [PASSED] ttm_bo_multiple_pin_one_unpin
[06:12:31] ===================== [PASSED] ttm_bo ======================
[06:12:31] ============== ttm_bo_validate (22 subtests) ===============
[06:12:31] ============== ttm_bo_init_reserved_sys_man  ===============
[06:12:31] [PASSED] Buffer object for userspace
[06:12:31] [PASSED] Kernel buffer object
[06:12:31] [PASSED] Shared buffer object
[06:12:31] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[06:12:31] ============== ttm_bo_init_reserved_mock_man  ==============
[06:12:31] [PASSED] Buffer object for userspace
[06:12:31] [PASSED] Kernel buffer object
[06:12:31] [PASSED] Shared buffer object
[06:12:31] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[06:12:31] [PASSED] ttm_bo_init_reserved_resv
[06:12:31] ================== ttm_bo_validate_basic  ==================
[06:12:31] [PASSED] Buffer object for userspace
[06:12:31] [PASSED] Kernel buffer object
[06:12:31] [PASSED] Shared buffer object
[06:12:31] ============== [PASSED] ttm_bo_validate_basic ==============
[06:12:31] [PASSED] ttm_bo_validate_invalid_placement
[06:12:31] ============= ttm_bo_validate_same_placement  ==============
[06:12:31] [PASSED] System manager
[06:12:31] [PASSED] VRAM manager
[06:12:31] ========= [PASSED] ttm_bo_validate_same_placement ==========
[06:12:31] [PASSED] ttm_bo_validate_failed_alloc
[06:12:31] [PASSED] ttm_bo_validate_pinned
[06:12:31] [PASSED] ttm_bo_validate_busy_placement
[06:12:31] ================ ttm_bo_validate_multihop  =================
[06:12:31] [PASSED] Buffer object for userspace
[06:12:31] [PASSED] Kernel buffer object
[06:12:31] [PASSED] Shared buffer object
[06:12:31] ============ [PASSED] ttm_bo_validate_multihop =============
[06:12:31] ========== ttm_bo_validate_no_placement_signaled  ==========
[06:12:31] [PASSED] Buffer object in system domain, no page vector
[06:12:31] [PASSED] Buffer object in system domain with an existing page vector
[06:12:31] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[06:12:31] ======== ttm_bo_validate_no_placement_not_signaled  ========
[06:12:31] [PASSED] Buffer object for userspace
[06:12:31] [PASSED] Kernel buffer object
[06:12:31] [PASSED] Shared buffer object
[06:12:31] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[06:12:31] [PASSED] ttm_bo_validate_move_fence_signaled
[06:12:31] ========= ttm_bo_validate_move_fence_not_signaled  =========
[06:12:31] [PASSED] Waits for GPU
[06:12:31] [PASSED] Tries to lock straight away
[06:12:31] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[06:12:31] [PASSED] ttm_bo_validate_swapout
[06:12:31] [PASSED] ttm_bo_validate_happy_evict
[06:12:31] [PASSED] ttm_bo_validate_all_pinned_evict
[06:12:31] [PASSED] ttm_bo_validate_allowed_only_evict
[06:12:31] [PASSED] ttm_bo_validate_deleted_evict
[06:12:31] [PASSED] ttm_bo_validate_busy_domain_evict
[06:12:31] [PASSED] ttm_bo_validate_evict_gutting
[06:12:31] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[06:12:31] ================= [PASSED] ttm_bo_validate =================
[06:12:31] ============================================================
[06:12:31] Testing complete. Ran 102 tests: passed: 102
[06:12:32] Elapsed time: 11.209s total, 1.720s configuring, 8.817s building, 0.566s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ CI.Build: success for Consolidation of DSS Control in Separate Files (rev3)

[Patchwork]

== Series Details ==

Series: Consolidation of DSS Control in Separate Files (rev3)
URL   : https://patchwork.freedesktop.org/series/137788/
State : success

== Summary ==

lib/modules/6.11.0-rc5-xe/kernel/sound/core/seq/
lib/modules/6.11.0-rc5-xe/kernel/sound/core/seq/snd-seq.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/core/snd-seq-device.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/core/snd-hwdep.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/core/snd.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/core/snd-pcm.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/core/snd-compress.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/core/snd-timer.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soundcore.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/intel/
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/intel/atom/
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/intel/atom/snd-soc-sst-atom-hifi2-platform.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/intel/atom/sst/
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/intel/atom/sst/snd-intel-sst-acpi.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/intel/atom/sst/snd-intel-sst-core.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/intel/common/
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/intel/common/snd-soc-acpi-intel-match.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/amd/
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/amd/snd-acp-config.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/intel/
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-tgl.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-mlink.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-cnl.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-lnl.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-common.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-generic.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-mtl.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/amd/
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/amd/snd-sof-amd-renoir.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/amd/snd-sof-amd-acp.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/snd-sof-utils.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/snd-sof-pci.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/snd-sof.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/snd-sof-probes.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/xtensa/
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/sof/xtensa/snd-sof-xtensa-dsp.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/snd-soc-core.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/snd-soc-acpi.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/codecs/
lib/modules/6.11.0-rc5-xe/kernel/sound/soc/codecs/snd-soc-hdac-hda.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/hda/
lib/modules/6.11.0-rc5-xe/kernel/sound/hda/snd-intel-sdw-acpi.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/hda/ext/
lib/modules/6.11.0-rc5-xe/kernel/sound/hda/ext/snd-hda-ext-core.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/hda/snd-intel-dspcfg.ko
lib/modules/6.11.0-rc5-xe/kernel/sound/hda/snd-hda-core.ko
lib/modules/6.11.0-rc5-xe/kernel/arch/
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/kernel/
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/kernel/msr.ko
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/kernel/cpuid.ko
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/crypto/
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/crypto/sha512-ssse3.ko
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/crypto/crct10dif-pclmul.ko
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/crypto/ghash-clmulni-intel.ko
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/crypto/sha1-ssse3.ko
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/crypto/crc32-pclmul.ko
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/crypto/sha256-ssse3.ko
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/crypto/aesni-intel.ko
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/crypto/polyval-clmulni.ko
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/events/
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/events/intel/
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/events/intel/intel-cstate.ko
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/events/rapl.ko
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/kvm/
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/kvm/kvm.ko
lib/modules/6.11.0-rc5-xe/kernel/arch/x86/kvm/kvm-intel.ko
lib/modules/6.11.0-rc5-xe/kernel/crypto/
lib/modules/6.11.0-rc5-xe/kernel/crypto/crypto_simd.ko
lib/modules/6.11.0-rc5-xe/kernel/crypto/cmac.ko
lib/modules/6.11.0-rc5-xe/kernel/crypto/ccm.ko
lib/modules/6.11.0-rc5-xe/kernel/crypto/cryptd.ko
lib/modules/6.11.0-rc5-xe/kernel/crypto/polyval-generic.ko
lib/modules/6.11.0-rc5-xe/kernel/crypto/async_tx/
lib/modules/6.11.0-rc5-xe/kernel/crypto/async_tx/async_xor.ko
lib/modules/6.11.0-rc5-xe/kernel/crypto/async_tx/async_tx.ko
lib/modules/6.11.0-rc5-xe/kernel/crypto/async_tx/async_memcpy.ko
lib/modules/6.11.0-rc5-xe/kernel/crypto/async_tx/async_pq.ko
lib/modules/6.11.0-rc5-xe/kernel/crypto/async_tx/async_raid6_recov.ko
lib/modules/6.11.0-rc5-xe/build
lib/modules/6.11.0-rc5-xe/modules.alias.bin
lib/modules/6.11.0-rc5-xe/modules.builtin
lib/modules/6.11.0-rc5-xe/modules.softdep
lib/modules/6.11.0-rc5-xe/modules.alias
lib/modules/6.11.0-rc5-xe/modules.order
lib/modules/6.11.0-rc5-xe/modules.symbols
lib/modules/6.11.0-rc5-xe/modules.dep.bin
+ mv kernel-nodebug.tar.gz ..
+ cd ..
+ rm -rf archive
++ date +%s
+ echo -e '\e[0Ksection_end:1724999059:package_x86_64_nodebug\r\e[0K'
+ sync
^[[0Ksection_end:1724999059:package_x86_64_nodebug
^[[0K
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ CI.BAT: success for Consolidation of DSS Control in Separate Files (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1552 bytes --]

== Series Details ==

Series: Consolidation of DSS Control in Separate Files (rev3)
URL   : https://patchwork.freedesktop.org/series/137788/
State : success

== Summary ==

CI Bug Log - changes from xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158_BAT -> xe-pw-137788v3_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-137788v3_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - bat-lnl-1:          [PASS][1] -> [FAIL][2] ([Intel XE#886]) +1 other test fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/bat-lnl-1/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/bat-lnl-1/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886


Build changes
-------------

  * Linux: xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158 -> xe-pw-137788v3

  IGT_7999: a73311079a5d8ac99eb25336a8369a2c3c6b519b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158: d77e26a2d2f173b7998932b5d76173816ed5e158
  xe-pw-137788v3: 137788v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/index.html

[-- Attachment #2: Type: text/html, Size: 2118 bytes --]

Re: [PATCH 02/19] drm/i915/dss_regs: Use REG_* macros for the DSS ctl bits

[Ville Syrjälä]

On Fri, Aug 30, 2024 at 10:39:32AM +0530, Ankit Nautiyal wrote:
> Cleanup register definitions for DSS CLT reg bits.

DSS_CTL

> Replace the hand rolled (1<<n) with the modern REG_BIT().
> Use REG_GENMASK and REG_FIELD_PREP for the bit fields.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dss_regs.h | 34 ++++++++++---------
>  1 file changed, 18 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dss_regs.h b/drivers/gpu/drm/i915/display/intel_dss_regs.h
> index b1e24ea027c3..cfc8ef451917 100644
> --- a/drivers/gpu/drm/i915/display/intel_dss_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dss_regs.h
> @@ -10,35 +10,37 @@
>  
>  /* Display Stream Splitter Control */
>  #define DSS_CTL1				_MMIO(0x67400)
> -#define  SPLITTER_ENABLE			(1 << 31)
> -#define  JOINER_ENABLE				(1 << 30)
> -#define  DUAL_LINK_MODE_INTERLEAVE		(1 << 24)
> +#define  SPLITTER_ENABLE			REG_BIT(31)
> +#define  JOINER_ENABLE				REG_BIT(30)
> +#define  DUAL_LINK_MODE_INTERLEAVE		REG_BIT(24)
>  #define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)

If we want to keep this then we should define the bit as
DUAL_LINK_MODE_MASK, and then both values should be defined
via REG_FIELD_PREP().

> -#define  OVERLAP_PIXELS_MASK			(0xf << 16)
> -#define  OVERLAP_PIXELS(pixels)			((pixels) << 16)
> -#define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
> -#define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
> +#define  OVERLAP_PIXELS_MASK			REG_GENMASK(19, 16)
> +#define  OVERLAP_PIXELS(pixels)			REG_FIELD_PREP(OVERLAP_PIXELS_MASK, pixels)
> +#define  LEFT_DL_BUF_TARGET_DEPTH_MASK		REG_GENMASK(11, 0)
> +#define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	REG_FIELD_PREP(LEFT_DL_BUF_TARGET_DEPTH_MASK, \
> +							       pixels)

Protect with '(pixels)'

The extra line wrap seems pointless.

>  #define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0
>  
>  #define DSS_CTL2				_MMIO(0x67404)
> -#define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
> -#define  RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
> -#define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
> -#define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
> +#define  LEFT_BRANCH_VDSC_ENABLE		REG_BIT(31)
> +#define  RIGHT_BRANCH_VDSC_ENABLE		REG_BIT(15)
> +#define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		REG_GENMASK(11, 0)
> +#define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	REG_FIELD_PREP(RIGHT_DL_BUF_TARGET_DEPTH_MASK,\
> +							       pixels)

Another unprotected macro argument.

>  
>  #define _ICL_PIPE_DSS_CTL1_PB			0x78200
>  #define _ICL_PIPE_DSS_CTL1_PC			0x78400
>  #define ICL_PIPE_DSS_CTL1(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
>  							   _ICL_PIPE_DSS_CTL1_PB, \
>  							   _ICL_PIPE_DSS_CTL1_PC)
> -#define  BIG_JOINER_ENABLE			(1 << 29)
> -#define  PRIMARY_BIG_JOINER_ENABLE		(1 << 28)
> -#define  VGA_CENTERING_ENABLE			(1 << 27)
> +#define  BIG_JOINER_ENABLE			REG_BIT(29)
> +#define  PRIMARY_BIG_JOINER_ENABLE		REG_BIT(28)
> +#define  VGA_CENTERING_ENABLE			REG_BIT(27)
>  #define  SPLITTER_CONFIGURATION_MASK		REG_GENMASK(26, 25)
>  #define  SPLITTER_CONFIGURATION_2_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
>  #define  SPLITTER_CONFIGURATION_4_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
> -#define  UNCOMPRESSED_JOINER_PRIMARY		(1 << 21)
> -#define  UNCOMPRESSED_JOINER_SECONDARY		(1 << 20)
> +#define  UNCOMPRESSED_JOINER_PRIMARY		REG_BIT(21)
> +#define  UNCOMPRESSED_JOINER_SECONDARY		REG_BIT(20)
>  
>  #define _ICL_PIPE_DSS_CTL2_PB			0x78204
>  #define _ICL_PIPE_DSS_CTL2_PC			0x78404
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 07/19] drm/i915/icl_dsi: Move helpers to configure dsi dual link to intel_dss

[Ville Syrjälä]

On Fri, Aug 30, 2024 at 10:39:37AM +0530, Ankit Nautiyal wrote:
> Move the function to configure dss_ctl for dual_link dsi to intel_dss
> files. While at it, use struct intel_display wherever possible.
> 
> v2: Avoid modifying the code while movement. (Jani)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c   | 57 ++----------------------
>  drivers/gpu/drm/i915/display/intel_dss.c | 50 +++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dss.h |  3 ++
>  3 files changed, 57 insertions(+), 53 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 79e149d51cb2..ec880d1cbbee 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -44,7 +44,7 @@
>  #include "intel_de.h"
>  #include "intel_dsi.h"
>  #include "intel_dsi_vbt.h"
> -#include "intel_dss_regs.h"
> +#include "intel_dss.h"
>  #include "intel_panel.h"
>  #include "intel_vdsc.h"
>  #include "skl_scaler.h"
> @@ -274,55 +274,6 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
>  	}
>  }
>  
> -static void configure_dual_link_mode(struct intel_encoder *encoder,
> -				     const struct intel_crtc_state *pipe_config,
> -				     u8 dual_link, u8 pixel_overlap)
> -{
> -	struct intel_display *display = to_intel_display(encoder);
> -	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> -	u32 dss_ctl1;
> -
> -	/* FIXME: Move all DSS handling to intel_vdsc.c */
> -	if (DISPLAY_VER(display) >= 12) {
> -		struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> -
> -		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
> -		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
> -	} else {
> -		dss_ctl1_reg = DSS_CTL1;
> -		dss_ctl2_reg = DSS_CTL2;
> -	}
> -
> -	dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
> -	dss_ctl1 |= SPLITTER_ENABLE;
> -	dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
> -	dss_ctl1 |= OVERLAP_PIXELS(pixel_overlap);
> -
> -	if (dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> -		const struct drm_display_mode *adjusted_mode =
> -					&pipe_config->hw.adjusted_mode;
> -		u16 hactive = adjusted_mode->crtc_hdisplay;
> -		u16 dl_buffer_depth;
> -
> -		dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
> -		dl_buffer_depth = hactive / 2 + pixel_overlap;
> -
> -		if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
> -			drm_err(display->drm,
> -				"DL buffer depth exceed max value\n");
> -
> -		dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
> -		dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
> -		intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
> -			     RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
> -	} else {
> -		/* Interleave */
> -		dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
> -	}
> -
> -	intel_de_write(display, dss_ctl1_reg, dss_ctl1);
> -}
> -
>  /* aka DSI 8X clock */
>  static int afe_clk(struct intel_encoder *encoder,
>  		   const struct intel_crtc_state *crtc_state)
> @@ -791,9 +742,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>  		}
>  
>  		/* configure stream splitting */
> -		configure_dual_link_mode(encoder, pipe_config,
> -					 intel_dsi->dual_link,
> -					 intel_dsi->pixel_overlap);
> +		intel_dss_dsi_dual_link_mode_configure(encoder, pipe_config,
> +						       intel_dsi->dual_link,
> +						       intel_dsi->pixel_overlap);
>  	}
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c
> index 3f7f416eb3fa..969e32143983 100644
> --- a/drivers/gpu/drm/i915/display/intel_dss.c
> +++ b/drivers/gpu/drm/i915/display/intel_dss.c
> @@ -7,6 +7,7 @@
>  #include "i915_reg_defs.h"
>  #include "intel_de.h"
>  #include "intel_display_types.h"
> +#include "intel_dsi.h"
>  #include "intel_dss.h"
>  #include "intel_dss_regs.h"
>  
> @@ -87,3 +88,52 @@ void intel_dss_mso_configure(const struct intel_crtc_state *crtc_state)
>  		     SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
>  		     OVERLAP_PIXELS_MASK, dss1);
>  }
> +
> +void intel_dss_dsi_dual_link_mode_configure(struct intel_encoder *encoder,
> +					    const struct intel_crtc_state *pipe_config,
> +					    u8 dual_link,
> +					    u8 pixel_overlap)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> +	u32 dss_ctl1;
> +
> +	if (DISPLAY_VER(display) >= 12) {
> +		struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> +
> +		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
> +		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
> +	} else {
> +		dss_ctl1_reg = DSS_CTL1;
> +		dss_ctl2_reg = DSS_CTL2;
> +	}
> +
> +	dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
> +	dss_ctl1 |= SPLITTER_ENABLE;
> +	dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
> +	dss_ctl1 |= OVERLAP_PIXELS(pixel_overlap);
> +
> +	if (dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> +		const struct drm_display_mode *adjusted_mode =
> +					&pipe_config->hw.adjusted_mode;
> +		u16 hactive = adjusted_mode->crtc_hdisplay;
> +		u16 dl_buffer_depth;
> +
> +		dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
> +		dl_buffer_depth = hactive / 2 + pixel_overlap;
> +
> +		if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
> +			drm_err(display->drm,
> +				"DL buffer depth exceed max value\n");
> +
> +		dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
> +		dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
> +		intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
> +			     RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));

Leaking the DSI mess outside of the DSI code is not great. The DSI
code should really just be taught to use the crtc_state properly.

> +	} else {
> +		/* Interleave */
> +		dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
> +	}
> +
> +	intel_de_write(display, dss_ctl1_reg, dss_ctl1);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h
> index d4629052979a..aa8c67c15855 100644
> --- a/drivers/gpu/drm/i915/display/intel_dss.h
> +++ b/drivers/gpu/drm/i915/display/intel_dss.h
> @@ -16,5 +16,8 @@ u8 intel_dss_mso_pipe_mask(struct intel_display *display);
>  void intel_dss_mso_get_config(struct intel_encoder *encoder,
>  			      struct intel_crtc_state *pipe_config);
>  void intel_dss_mso_configure(const struct intel_crtc_state *crtc_state);
> +void intel_dss_dsi_dual_link_mode_configure(struct intel_encoder *encoder,
> +					    const struct intel_crtc_state *pipe_config,
> +					    u8 dual_link, u8 pixel_overlap);
>  
>  #endif /* __INTEL_DSS_H__ */
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

✓ CI.FULL: success for Consolidation of DSS Control in Separate Files (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 58594 bytes --]

== Series Details ==

Series: Consolidation of DSS Control in Separate Files (rev3)
URL   : https://patchwork.freedesktop.org/series/137788/
State : success

== Summary ==

CI Bug Log - changes from xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158_full -> xe-pw-137788v3_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-137788v3_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
    - shard-lnl:          [PASS][1] -> [FAIL][2] ([Intel XE#1701]) +1 other test fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-lnl-2/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-lnl-7/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-lnl:          [PASS][3] -> [FAIL][4] ([Intel XE#1659]) +1 other test fail
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-lnl-3/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-lnl-5/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-adlp:         NOTRUN -> [SKIP][5] ([Intel XE#1201] / [Intel XE#316]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-adlp:         NOTRUN -> [SKIP][6] ([Intel XE#1201] / [Intel XE#607])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-adlp:         NOTRUN -> [SKIP][7] ([Intel XE#1124] / [Intel XE#1201]) +2 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
    - shard-adlp:         NOTRUN -> [SKIP][8] ([Intel XE#1201] / [Intel XE#2191])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
    - shard-adlp:         NOTRUN -> [SKIP][9] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +7 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][10] ([Intel XE#1201] / [Intel XE#787]) +11 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-1.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-adlp:         NOTRUN -> [SKIP][11] ([Intel XE#1201] / [Intel XE#306])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_chamelium_hpd@hdmi-hpd-after-hibernate:
    - shard-adlp:         NOTRUN -> [SKIP][12] ([Intel XE#1201] / [Intel XE#373]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_chamelium_hpd@hdmi-hpd-after-hibernate.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-adlp:         NOTRUN -> [SKIP][13] ([Intel XE#1201] / [Intel XE#309])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-adlp:         NOTRUN -> [SKIP][14] ([Intel XE#1201] / [Intel XE#310])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-y:
    - shard-adlp:         [PASS][15] -> [FAIL][16] ([Intel XE#1874]) +1 other test fail
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-adlp-1/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-y.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-4/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-y.html

  * igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][17] ([Intel XE#1201] / [Intel XE#651]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-move:
    - shard-adlp:         NOTRUN -> [SKIP][18] ([Intel XE#1201] / [Intel XE#651]) +2 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-adlp:         NOTRUN -> [SKIP][19] ([Intel XE#1201] / [Intel XE#656]) +9 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
    - shard-adlp:         NOTRUN -> [SKIP][20] ([Intel XE#1201] / [Intel XE#653]) +2 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-adlp:         NOTRUN -> [SKIP][21] ([Intel XE#1201] / [Intel XE#356])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane@plane-position-covered@pipe-b-plane-3:
    - shard-lnl:          [PASS][22] -> [DMESG-WARN][23] ([Intel XE#324]) +2 other tests dmesg-warn
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-lnl-6/igt@kms_plane@plane-position-covered@pipe-b-plane-3.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-lnl-3/igt@kms_plane@plane-position-covered@pipe-b-plane-3.html

  * igt@kms_plane@plane-position-hole@pipe-a-plane-3:
    - shard-lnl:          [PASS][24] -> [DMESG-FAIL][25] ([Intel XE#324]) +1 other test dmesg-fail
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-lnl-1/igt@kms_plane@plane-position-hole@pipe-a-plane-3.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-lnl-2/igt@kms_plane@plane-position-hole@pipe-a-plane-3.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-adlp:         NOTRUN -> [SKIP][26] ([Intel XE#1201] / [Intel XE#455]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf:
    - shard-adlp:         NOTRUN -> [SKIP][27] ([Intel XE#1201])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@fbc-pr-sprite-render:
    - shard-adlp:         NOTRUN -> [SKIP][28] ([Intel XE#1201] / [Intel XE#929]) +3 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_psr@fbc-pr-sprite-render.html

  * igt@kms_universal_plane@cursor-fb-leak:
    - shard-lnl:          [PASS][29] -> [FAIL][30] ([Intel XE#899]) +1 other test fail
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-lnl-6/igt@kms_universal_plane@cursor-fb-leak.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-lnl-3/igt@kms_universal_plane@cursor-fb-leak.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [PASS][31] -> [FAIL][32] ([Intel XE#899])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-436/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-adlp:         NOTRUN -> [SKIP][33] ([Intel XE#1201] / [Intel XE#756])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_writeback@writeback-pixel-formats.html

  * igt@xe_ccs@suspend-resume:
    - shard-adlp:         NOTRUN -> [SKIP][34] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#488])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@xe_ccs@suspend-resume.html

  * igt@xe_evict@evict-beng-small:
    - shard-adlp:         NOTRUN -> [SKIP][35] ([Intel XE#1201] / [Intel XE#261] / [Intel XE#688]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@xe_evict@evict-beng-small.html

  * igt@xe_evict@evict-beng-threads-small-multi-vm:
    - shard-adlp:         NOTRUN -> [SKIP][36] ([Intel XE#1201] / [Intel XE#261])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@xe_evict@evict-beng-threads-small-multi-vm.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind:
    - shard-adlp:         NOTRUN -> [SKIP][37] ([Intel XE#1201] / [Intel XE#1392]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate:
    - shard-dg2-set2:     NOTRUN -> [SKIP][38] ([Intel XE#1201] / [Intel XE#288])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-466/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_fault_mode@many-rebind-prefetch:
    - shard-adlp:         NOTRUN -> [SKIP][39] ([Intel XE#1201] / [Intel XE#288]) +6 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@xe_exec_fault_mode@many-rebind-prefetch.html

  * igt@xe_pm@d3cold-basic:
    - shard-adlp:         NOTRUN -> [SKIP][40] ([Intel XE#1201] / [Intel XE#2284] / [Intel XE#366])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@xe_pm@d3cold-basic.html

  
#### Possible fixes ####

  * igt@kms_atomic_transition@modeset-transition-nonblocking:
    - shard-lnl:          [FAIL][41] ([Intel XE#1701]) -> [PASS][42] +1 other test pass
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-lnl-7/igt@kms_atomic_transition@modeset-transition-nonblocking.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-lnl-8/igt@kms_atomic_transition@modeset-transition-nonblocking.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1:
    - shard-lnl:          [FAIL][43] ([Intel XE#1426]) -> [PASS][44] +1 other test pass
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-lnl-2/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-lnl-7/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition:
    - {shard-bmg}:        [FAIL][45] ([Intel XE#1426]) -> [PASS][46] +3 other tests pass
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-bmg-3/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-bmg-6/igt@kms_atomic_transition@plane-toggle-modeset-transition.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [FAIL][47] ([Intel XE#1426]) -> [PASS][48] +1 other test pass
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-436/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-6.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-6.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          [FAIL][49] ([Intel XE#1659]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-lnl-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-lnl-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_cursor_legacy@torture-bo:
    - shard-dg2-set2:     [DMESG-WARN][51] ([Intel XE#877]) -> [PASS][52] +1 other test pass
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-435/igt@kms_cursor_legacy@torture-bo.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-466/igt@kms_cursor_legacy@torture-bo.html

  * igt@kms_flip@2x-flip-vs-panning-interruptible@cd-dp2-hdmi-a3:
    - {shard-bmg}:        [DMESG-WARN][53] ([Intel XE#877]) -> [PASS][54] +7 other tests pass
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-bmg-4/igt@kms_flip@2x-flip-vs-panning-interruptible@cd-dp2-hdmi-a3.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-bmg-4/igt@kms_flip@2x-flip-vs-panning-interruptible@cd-dp2-hdmi-a3.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - {shard-bmg}:        [INCOMPLETE][55] ([Intel XE#2635]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-bmg-2/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-bmg-1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
    - shard-dg2-set2:     [INCOMPLETE][57] ([Intel XE#1195]) -> [PASS][58] +1 other test pass
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-434/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-466/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-dp2-hdmi-a3:
    - {shard-bmg}:        [INCOMPLETE][59] -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-bmg-2/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-dp2-hdmi-a3.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-bmg-1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-dp2-hdmi-a3.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1:
    - shard-lnl:          [FAIL][61] ([Intel XE#886]) -> [PASS][62] +1 other test pass
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-lnl-3/igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-lnl-5/igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-x:
    - shard-adlp:         [FAIL][63] ([Intel XE#1874]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-adlp-1/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-x.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-4/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-x.html

  * igt@kms_plane@plane-position-covered@pipe-b-plane-1:
    - shard-lnl:          [DMESG-WARN][65] ([Intel XE#324]) -> [PASS][66] +3 other tests pass
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-lnl-6/igt@kms_plane@plane-position-covered@pipe-b-plane-1.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-lnl-3/igt@kms_plane@plane-position-covered@pipe-b-plane-1.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-lnl:          [FAIL][67] ([Intel XE#718]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-lnl-3/igt@kms_pm_dc@dc5-psr.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-lnl-5/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_rpm@universal-planes:
    - shard-lnl:          [DMESG-WARN][69] ([Intel XE#2042]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-lnl-6/igt@kms_pm_rpm@universal-planes.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-lnl-3/igt@kms_pm_rpm@universal-planes.html

  * igt@kms_pm_rpm@universal-planes@plane-41:
    - shard-lnl:          [DMESG-WARN][71] -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-lnl-6/igt@kms_pm_rpm@universal-planes@plane-41.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-lnl-3/igt@kms_pm_rpm@universal-planes@plane-41.html

  * igt@kms_universal_plane@cursor-fb-leak:
    - shard-adlp:         [FAIL][73] ([Intel XE#771] / [Intel XE#899]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-adlp-6/igt@kms_universal_plane@cursor-fb-leak.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_universal_plane@cursor-fb-leak.html
    - {shard-bmg}:        [FAIL][75] ([Intel XE#899]) -> [PASS][76] +1 other test pass
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-bmg-4/igt@kms_universal_plane@cursor-fb-leak.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-bmg-1/igt@kms_universal_plane@cursor-fb-leak.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
    - shard-adlp:         [FAIL][77] ([Intel XE#899]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-adlp-6/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-8/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-b-dp-4:
    - shard-dg2-set2:     [FAIL][79] ([Intel XE#899]) -> [PASS][80] +1 other test pass
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-436/igt@kms_universal_plane@cursor-fb-leak@pipe-b-dp-4.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@kms_universal_plane@cursor-fb-leak@pipe-b-dp-4.html

  * igt@xe_drm_fdinfo@drm-most-busy-idle-check-all:
    - {shard-bmg}:        [FAIL][81] -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-bmg-2/igt@xe_drm_fdinfo@drm-most-busy-idle-check-all.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-bmg-1/igt@xe_drm_fdinfo@drm-most-busy-idle-check-all.html

  * igt@xe_evict@evict-large-multi-vm-cm:
    - shard-dg2-set2:     [FAIL][83] ([Intel XE#1600]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-463/igt@xe_evict@evict-large-multi-vm-cm.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-436/igt@xe_evict@evict-large-multi-vm-cm.html

  * igt@xe_evict@evict-mixed-threads-large:
    - shard-dg2-set2:     [DMESG-FAIL][85] ([Intel XE#482]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-466/igt@xe_evict@evict-mixed-threads-large.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-436/igt@xe_evict@evict-mixed-threads-large.html

  * igt@xe_pm_residency@toggle-gt-c6:
    - shard-lnl:          [FAIL][87] ([Intel XE#958]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-lnl-8/igt@xe_pm_residency@toggle-gt-c6.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-lnl-5/igt@xe_pm_residency@toggle-gt-c6.html

  
#### Warnings ####

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-6-4-mc-ccs:
    - shard-dg2-set2:     [SKIP][89] ([Intel XE#1201] / [Intel XE#801]) -> [SKIP][90] ([Intel XE#801]) +23 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-434/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-6-4-mc-ccs.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-6-4-mc-ccs.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-y:
    - shard-adlp:         [DMESG-WARN][91] ([Intel XE#1033]) -> [DMESG-WARN][92] ([Intel XE#324])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-adlp-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-y.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-y.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][93] ([Intel XE#316]) -> [SKIP][94] ([Intel XE#1201] / [Intel XE#316])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     [SKIP][95] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][96] ([Intel XE#316]) +4 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-436/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-adlp:         [FAIL][97] ([Intel XE#1231]) -> [FAIL][98] ([Intel XE#1242])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-adlp-9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-adlp:         [FAIL][99] ([Intel XE#1231]) -> [DMESG-FAIL][100] ([Intel XE#324])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-adlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-dg2-set2:     [SKIP][101] ([Intel XE#607]) -> [SKIP][102] ([Intel XE#1201] / [Intel XE#607])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-dg2-set2:     [SKIP][103] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][104] ([Intel XE#1124]) +5 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-434/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-adlp:         [FAIL][105] ([Intel XE#1242]) -> [FAIL][106] ([Intel XE#1231])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-adlp-9/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
    - shard-dg2-set2:     [SKIP][107] ([Intel XE#1124]) -> [SKIP][108] ([Intel XE#1124] / [Intel XE#1201]) +4 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-433/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-dg2-set2:     [SKIP][109] ([Intel XE#1201] / [Intel XE#607]) -> [SKIP][110] ([Intel XE#607])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-436/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-dg2-set2:     [SKIP][111] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][112] ([Intel XE#367])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-434/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
    - shard-dg2-set2:     [SKIP][113] ([Intel XE#1201] / [Intel XE#2191]) -> [SKIP][114] ([Intel XE#2191])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-436/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-1-displays-1920x1080p:
    - shard-dg2-set2:     [SKIP][115] ([Intel XE#367]) -> [SKIP][116] ([Intel XE#1201] / [Intel XE#367]) +3 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-433/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-dg2-set2:     [SKIP][117] ([Intel XE#1201] / [Intel XE#1252]) -> [SKIP][118] ([Intel XE#1252]) +3 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-434/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc@pipe-a-dp-4:
    - shard-dg2-set2:     [SKIP][119] ([Intel XE#787]) -> [SKIP][120] ([Intel XE#1201] / [Intel XE#787]) +41 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc@pipe-a-dp-4.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-433/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc@pipe-a-dp-4.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-4:
    - shard-dg2-set2:     [SKIP][121] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][122] ([Intel XE#455] / [Intel XE#787]) +11 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-436/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-4.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-4.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][123] ([Intel XE#1201] / [Intel XE#787]) -> [SKIP][124] ([Intel XE#787]) +41 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-436/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc:
    - shard-dg2-set2:     [SKIP][125] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][126] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +11 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_cdclk@plane-scaling@pipe-b-dp-4:
    - shard-dg2-set2:     [SKIP][127] ([Intel XE#1152]) -> [SKIP][128] ([Intel XE#1152] / [Intel XE#1201]) +3 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-dg2-set2:     [SKIP][129] ([Intel XE#1201] / [Intel XE#306]) -> [SKIP][130] ([Intel XE#306])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-436/igt@kms_chamelium_color@ctm-0-75.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_chamelium_hpd@vga-hpd:
    - shard-dg2-set2:     [SKIP][131] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][132] ([Intel XE#373]) +8 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-466/igt@kms_chamelium_hpd@vga-hpd.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_chamelium_hpd@vga-hpd.html

  * igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode:
    - shard-dg2-set2:     [SKIP][133] ([Intel XE#373]) -> [SKIP][134] ([Intel XE#1201] / [Intel XE#373]) +5 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-dg2-set2:     [SKIP][135] ([Intel XE#1201] / [Intel XE#308]) -> [SKIP][136] ([Intel XE#308]) +2 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-434/igt@kms_cursor_crc@cursor-offscreen-512x170.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-dg2-set2:     [SKIP][137] ([Intel XE#308]) -> [SKIP][138] ([Intel XE#1201] / [Intel XE#308])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_cursor_crc@cursor-offscreen-512x512.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-433/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_display_modes@mst-extended-mode-negative:
    - shard-dg2-set2:     [SKIP][139] ([Intel XE#1201] / [Intel XE#307]) -> [SKIP][140] ([Intel XE#307])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-466/igt@kms_display_modes@mst-extended-mode-negative.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_display_modes@mst-extended-mode-negative.html

  * igt@kms_feature_discovery@display-3x:
    - shard-dg2-set2:     [SKIP][141] ([Intel XE#703]) -> [SKIP][142] ([Intel XE#1201] / [Intel XE#703])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_feature_discovery@display-3x.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@kms_feature_discovery@display-3x.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-dg2-set2:     [SKIP][143] ([Intel XE#455]) -> [SKIP][144] ([Intel XE#1201] / [Intel XE#455]) +7 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-433/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-dg2-set2:     [SKIP][145] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][146] ([Intel XE#455]) +13 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-434/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - shard-dg2-set2:     [SKIP][147] ([i915#5274]) -> [SKIP][148] ([Intel XE#1201] / [i915#5274])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_force_connector_basic@prune-stale-modes.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-433/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff:
    - shard-dg2-set2:     [SKIP][149] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][150] ([Intel XE#651]) +21 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-blt:
    - shard-dg2-set2:     [SKIP][151] ([Intel XE#651]) -> [SKIP][152] ([Intel XE#1201] / [Intel XE#651]) +13 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-blt.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
    - shard-dg2-set2:     [SKIP][153] ([Intel XE#658]) -> [SKIP][154] ([Intel XE#1201] / [Intel XE#658])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt:
    - shard-dg2-set2:     [SKIP][155] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][156] ([Intel XE#653]) +21 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     [SKIP][157] ([Intel XE#653]) -> [SKIP][158] ([Intel XE#1201] / [Intel XE#653]) +13 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-dg2-set2:     [SKIP][159] ([Intel XE#1201] / [Intel XE#356]) -> [SKIP][160] ([Intel XE#356])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-436/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane@plane-position-hole:
    - shard-lnl:          [DMESG-WARN][161] ([Intel XE#324]) -> [DMESG-FAIL][162] ([Intel XE#324])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-lnl-1/igt@kms_plane@plane-position-hole.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-lnl-2/igt@kms_plane@plane-position-hole.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][163] ([Intel XE#2318]) -> [SKIP][164] ([Intel XE#1201] / [Intel XE#2318]) +2 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-6.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-433/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-6.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][165] ([Intel XE#2318] / [Intel XE#455]) -> [SKIP][166] ([Intel XE#1201] / [Intel XE#2318] / [Intel XE#455]) +1 other test skip
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-6.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-433/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-6.html

  * igt@kms_pm_backlight@fade:
    - shard-dg2-set2:     [SKIP][167] ([Intel XE#870]) -> [SKIP][168] ([Intel XE#1201] / [Intel XE#870])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_pm_backlight@fade.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-433/igt@kms_pm_backlight@fade.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-dg2-set2:     [SKIP][169] ([Intel XE#908]) -> [SKIP][170] ([Intel XE#1201] / [Intel XE#908])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_pm_dc@dc6-dpms.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf:
    - shard-dg2-set2:     [SKIP][171] ([Intel XE#1201] / [Intel XE#1489]) -> [SKIP][172] ([Intel XE#1489]) +1 other test skip
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-436/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area:
    - shard-dg2-set2:     [SKIP][173] ([Intel XE#1489]) -> [SKIP][174] ([Intel XE#1201] / [Intel XE#1489]) +1 other test skip
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-dg2-set2:     [SKIP][175] ([Intel XE#1122]) -> [SKIP][176] ([Intel XE#1122] / [Intel XE#1201])
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_psr2_su@page_flip-nv12.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-psr2-sprite-plane-move:
    - shard-dg2-set2:     [SKIP][177] ([Intel XE#929]) -> [SKIP][178] ([Intel XE#1201] / [Intel XE#929]) +6 other tests skip
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_psr@fbc-psr2-sprite-plane-move.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@kms_psr@fbc-psr2-sprite-plane-move.html

  * igt@kms_psr@psr2-primary-render:
    - shard-dg2-set2:     [SKIP][179] ([Intel XE#1201] / [Intel XE#929]) -> [SKIP][180] ([Intel XE#929]) +11 other tests skip
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-466/igt@kms_psr@psr2-primary-render.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_psr@psr2-primary-render.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-dg2-set2:     [SKIP][181] ([Intel XE#1127] / [Intel XE#1201]) -> [SKIP][182] ([Intel XE#1127])
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-434/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@sprite-rotation-90:
    - shard-dg2-set2:     [SKIP][183] ([Intel XE#1201] / [Intel XE#327]) -> [SKIP][184] ([Intel XE#327])
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-466/igt@kms_rotation_crc@sprite-rotation-90.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_rotation_crc@sprite-rotation-90.html

  * igt@kms_writeback@writeback-check-output:
    - shard-dg2-set2:     [SKIP][185] ([Intel XE#756]) -> [SKIP][186] ([Intel XE#1201] / [Intel XE#756])
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@kms_writeback@writeback-check-output.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-433/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-dg2-set2:     [SKIP][187] ([Intel XE#1201] / [Intel XE#756]) -> [SKIP][188] ([Intel XE#756])
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-436/igt@kms_writeback@writeback-pixel-formats.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@kms_writeback@writeback-pixel-formats.html

  * igt@xe_compute_preempt@compute-preempt:
    - shard-dg2-set2:     [SKIP][189] ([Intel XE#1201] / [Intel XE#1280] / [Intel XE#455]) -> [SKIP][190] ([Intel XE#1280] / [Intel XE#455]) +1 other test skip
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-434/igt@xe_compute_preempt@compute-preempt.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@xe_compute_preempt@compute-preempt.html

  * igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-imm:
    - shard-dg2-set2:     [SKIP][191] ([Intel XE#288]) -> [SKIP][192] ([Intel XE#1201] / [Intel XE#288]) +11 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-imm.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-433/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-imm.html

  * igt@xe_exec_fault_mode@twice-invalid-fault:
    - shard-dg2-set2:     [SKIP][193] ([Intel XE#1201] / [Intel XE#288]) -> [SKIP][194] ([Intel XE#288]) +18 other tests skip
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-436/igt@xe_exec_fault_mode@twice-invalid-fault.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@xe_exec_fault_mode@twice-invalid-fault.html

  * igt@xe_exec_mix_modes@exec-simple-batch-store-lr:
    - shard-dg2-set2:     [SKIP][195] ([Intel XE#1201] / [Intel XE#2360]) -> [SKIP][196] ([Intel XE#2360])
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-466/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html

  * igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence:
    - shard-dg2-set2:     [SKIP][197] ([Intel XE#2360]) -> [SKIP][198] ([Intel XE#1201] / [Intel XE#2360])
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-433/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html

  * igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
    - shard-dg2-set2:     [SKIP][199] ([Intel XE#2229]) -> [SKIP][200] ([Intel XE#1201] / [Intel XE#2229])
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html

  * igt@xe_media_fill@media-fill:
    - shard-dg2-set2:     [SKIP][201] ([Intel XE#1201] / [Intel XE#560]) -> [SKIP][202] ([Intel XE#560])
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-434/igt@xe_media_fill@media-fill.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@xe_media_fill@media-fill.html

  * igt@xe_module_load@force-load:
    - shard-dg2-set2:     [SKIP][203] ([Intel XE#378]) -> [SKIP][204] ([Intel XE#1201] / [Intel XE#378])
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@xe_module_load@force-load.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@xe_module_load@force-load.html

  * igt@xe_oa@mmio-triggered-reports:
    - shard-dg2-set2:     [SKIP][205] ([Intel XE#2541]) -> [SKIP][206] ([Intel XE#1201] / [Intel XE#2541]) +1 other test skip
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@xe_oa@mmio-triggered-reports.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@xe_oa@mmio-triggered-reports.html

  * igt@xe_oa@oa-unit-exclusive-stream-sample-oa:
    - shard-dg2-set2:     [SKIP][207] ([Intel XE#1201] / [Intel XE#2541]) -> [SKIP][208] ([Intel XE#2541]) +2 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-466/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-dg2-set2:     [SKIP][209] ([Intel XE#979]) -> [SKIP][210] ([Intel XE#1201] / [Intel XE#979])
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@xe_pat@pat-index-xehpc.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-433/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pm@d3cold-mmap-system:
    - shard-dg2-set2:     [SKIP][211] ([Intel XE#2284] / [Intel XE#366]) -> [SKIP][212] ([Intel XE#1201] / [Intel XE#2284] / [Intel XE#366])
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@xe_pm@d3cold-mmap-system.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@xe_pm@d3cold-mmap-system.html

  * igt@xe_pm@d3cold-multiple-execs:
    - shard-dg2-set2:     [SKIP][213] ([Intel XE#1201] / [Intel XE#2284] / [Intel XE#366]) -> [SKIP][214] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-466/igt@xe_pm@d3cold-multiple-execs.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@xe_pm@d3cold-multiple-execs.html

  * igt@xe_query@multigpu-query-config:
    - shard-dg2-set2:     [SKIP][215] ([Intel XE#944]) -> [SKIP][216] ([Intel XE#1201] / [Intel XE#944]) +1 other test skip
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-432/igt@xe_query@multigpu-query-config.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-435/igt@xe_query@multigpu-query-config.html

  * igt@xe_query@multigpu-query-invalid-size:
    - shard-dg2-set2:     [SKIP][217] ([Intel XE#1201] / [Intel XE#944]) -> [SKIP][218] ([Intel XE#944])
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158/shard-dg2-466/igt@xe_query@multigpu-query-invalid-size.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/shard-dg2-432/igt@xe_query@multigpu-query-invalid-size.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1033]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1033
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1152]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1152
  [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
  [Intel XE#1201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1201
  [Intel XE#1231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1231
  [Intel XE#1242]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1242
  [Intel XE#1252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1252
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1426
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600
  [Intel XE#1656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1656
  [Intel XE#1659]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1659
  [Intel XE#1701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1701
  [Intel XE#1760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1760
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2042]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2042
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2318]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2318
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2635]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2635
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324
  [Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327
  [Intel XE#356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/356
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/482
  [Intel XE#488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/488
  [Intel XE#560]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/560
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
  [Intel XE#771]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/771
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#801]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/801
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
  [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#958]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/958
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979
  [i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274


Build changes
-------------

  * Linux: xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158 -> xe-pw-137788v3

  IGT_7999: a73311079a5d8ac99eb25336a8369a2c3c6b519b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-1863-d77e26a2d2f173b7998932b5d76173816ed5e158: d77e26a2d2f173b7998932b5d76173816ed5e158
  xe-pw-137788v3: 137788v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-137788v3/index.html

[-- Attachment #2: Type: text/html, Size: 76476 bytes --]

Re: [PATCH 02/19] drm/i915/dss_regs: Use REG_* macros for the DSS ctl bits

[Nautiyal, Ankit K]

Thanks Ville for the comments.

Please my response inline:

On 8/30/2024 4:49 PM, Ville Syrjälä wrote:
> On Fri, Aug 30, 2024 at 10:39:32AM +0530, Ankit Nautiyal wrote:
>> Cleanup register definitions for DSS CLT reg bits.
> DSS_CTL

Will fix this in next version.


>
>> Replace the hand rolled (1<<n) with the modern REG_BIT().
>> Use REG_GENMASK and REG_FIELD_PREP for the bit fields.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dss_regs.h | 34 ++++++++++---------
>>   1 file changed, 18 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dss_regs.h b/drivers/gpu/drm/i915/display/intel_dss_regs.h
>> index b1e24ea027c3..cfc8ef451917 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dss_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dss_regs.h
>> @@ -10,35 +10,37 @@
>>   
>>   /* Display Stream Splitter Control */
>>   #define DSS_CTL1				_MMIO(0x67400)
>> -#define  SPLITTER_ENABLE			(1 << 31)
>> -#define  JOINER_ENABLE				(1 << 30)
>> -#define  DUAL_LINK_MODE_INTERLEAVE		(1 << 24)
>> +#define  SPLITTER_ENABLE			REG_BIT(31)
>> +#define  JOINER_ENABLE				REG_BIT(30)
>> +#define  DUAL_LINK_MODE_INTERLEAVE		REG_BIT(24)
>>   #define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)
> If we want to keep this then we should define the bit as
> DUAL_LINK_MODE_MASK, and then both values should be defined
> via REG_FIELD_PREP().

Makes sense. I will add DUAL_LINK_MODE_MASK and prepare value for 
Interleave and frontback.

>
>> -#define  OVERLAP_PIXELS_MASK			(0xf << 16)
>> -#define  OVERLAP_PIXELS(pixels)			((pixels) << 16)
>> -#define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
>> -#define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
>> +#define  OVERLAP_PIXELS_MASK			REG_GENMASK(19, 16)
>> +#define  OVERLAP_PIXELS(pixels)			REG_FIELD_PREP(OVERLAP_PIXELS_MASK, pixels)
>> +#define  LEFT_DL_BUF_TARGET_DEPTH_MASK		REG_GENMASK(11, 0)
>> +#define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	REG_FIELD_PREP(LEFT_DL_BUF_TARGET_DEPTH_MASK, \
>> +							       pixels)
> Protect with '(pixels)'
Will take care of this.
>
> The extra line wrap seems pointless.

This was just to make checkpatch happy to avoid long line, but if it 
hampers readability I will do away with this.


>
>>   #define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0
>>   
>>   #define DSS_CTL2				_MMIO(0x67404)
>> -#define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
>> -#define  RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
>> -#define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
>> -#define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
>> +#define  LEFT_BRANCH_VDSC_ENABLE		REG_BIT(31)
>> +#define  RIGHT_BRANCH_VDSC_ENABLE		REG_BIT(15)
>> +#define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		REG_GENMASK(11, 0)
>> +#define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	REG_FIELD_PREP(RIGHT_DL_BUF_TARGET_DEPTH_MASK,\
>> +							       pixels)
> Another unprotected macro argument.

Will fix this in the next version.

Thanks again for the suggestions/comments. I will take care of these in 
the next version.

Regards,

Ankit

>
>>   
>>   #define _ICL_PIPE_DSS_CTL1_PB			0x78200
>>   #define _ICL_PIPE_DSS_CTL1_PC			0x78400
>>   #define ICL_PIPE_DSS_CTL1(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
>>   							   _ICL_PIPE_DSS_CTL1_PB, \
>>   							   _ICL_PIPE_DSS_CTL1_PC)
>> -#define  BIG_JOINER_ENABLE			(1 << 29)
>> -#define  PRIMARY_BIG_JOINER_ENABLE		(1 << 28)
>> -#define  VGA_CENTERING_ENABLE			(1 << 27)
>> +#define  BIG_JOINER_ENABLE			REG_BIT(29)
>> +#define  PRIMARY_BIG_JOINER_ENABLE		REG_BIT(28)
>> +#define  VGA_CENTERING_ENABLE			REG_BIT(27)
>>   #define  SPLITTER_CONFIGURATION_MASK		REG_GENMASK(26, 25)
>>   #define  SPLITTER_CONFIGURATION_2_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
>>   #define  SPLITTER_CONFIGURATION_4_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
>> -#define  UNCOMPRESSED_JOINER_PRIMARY		(1 << 21)
>> -#define  UNCOMPRESSED_JOINER_SECONDARY		(1 << 20)
>> +#define  UNCOMPRESSED_JOINER_PRIMARY		REG_BIT(21)
>> +#define  UNCOMPRESSED_JOINER_SECONDARY		REG_BIT(20)
>>   
>>   #define _ICL_PIPE_DSS_CTL2_PB			0x78204
>>   #define _ICL_PIPE_DSS_CTL2_PC			0x78404
>> -- 
>> 2.45.2

Re: [PATCH 07/19] drm/i915/icl_dsi: Move helpers to configure dsi dual link to intel_dss

[Nautiyal, Ankit K]

On 8/30/2024 4:55 PM, Ville Syrjälä wrote:
> On Fri, Aug 30, 2024 at 10:39:37AM +0530, Ankit Nautiyal wrote:
>> Move the function to configure dss_ctl for dual_link dsi to intel_dss
>> files. While at it, use struct intel_display wherever possible.
>>
>> v2: Avoid modifying the code while movement. (Jani)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/icl_dsi.c   | 57 ++----------------------
>>   drivers/gpu/drm/i915/display/intel_dss.c | 50 +++++++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_dss.h |  3 ++
>>   3 files changed, 57 insertions(+), 53 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
>> index 79e149d51cb2..ec880d1cbbee 100644
>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> @@ -44,7 +44,7 @@
>>   #include "intel_de.h"
>>   #include "intel_dsi.h"
>>   #include "intel_dsi_vbt.h"
>> -#include "intel_dss_regs.h"
>> +#include "intel_dss.h"
>>   #include "intel_panel.h"
>>   #include "intel_vdsc.h"
>>   #include "skl_scaler.h"
>> @@ -274,55 +274,6 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
>>   	}
>>   }
>>   
>> -static void configure_dual_link_mode(struct intel_encoder *encoder,
>> -				     const struct intel_crtc_state *pipe_config,
>> -				     u8 dual_link, u8 pixel_overlap)
>> -{
>> -	struct intel_display *display = to_intel_display(encoder);
>> -	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
>> -	u32 dss_ctl1;
>> -
>> -	/* FIXME: Move all DSS handling to intel_vdsc.c */
>> -	if (DISPLAY_VER(display) >= 12) {
>> -		struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>> -
>> -		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
>> -		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
>> -	} else {
>> -		dss_ctl1_reg = DSS_CTL1;
>> -		dss_ctl2_reg = DSS_CTL2;
>> -	}
>> -
>> -	dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
>> -	dss_ctl1 |= SPLITTER_ENABLE;
>> -	dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
>> -	dss_ctl1 |= OVERLAP_PIXELS(pixel_overlap);
>> -
>> -	if (dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>> -		const struct drm_display_mode *adjusted_mode =
>> -					&pipe_config->hw.adjusted_mode;
>> -		u16 hactive = adjusted_mode->crtc_hdisplay;
>> -		u16 dl_buffer_depth;
>> -
>> -		dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
>> -		dl_buffer_depth = hactive / 2 + pixel_overlap;
>> -
>> -		if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
>> -			drm_err(display->drm,
>> -				"DL buffer depth exceed max value\n");
>> -
>> -		dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
>> -		dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
>> -		intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
>> -			     RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
>> -	} else {
>> -		/* Interleave */
>> -		dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
>> -	}
>> -
>> -	intel_de_write(display, dss_ctl1_reg, dss_ctl1);
>> -}
>> -
>>   /* aka DSI 8X clock */
>>   static int afe_clk(struct intel_encoder *encoder,
>>   		   const struct intel_crtc_state *crtc_state)
>> @@ -791,9 +742,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>>   		}
>>   
>>   		/* configure stream splitting */
>> -		configure_dual_link_mode(encoder, pipe_config,
>> -					 intel_dsi->dual_link,
>> -					 intel_dsi->pixel_overlap);
>> +		intel_dss_dsi_dual_link_mode_configure(encoder, pipe_config,
>> +						       intel_dsi->dual_link,
>> +						       intel_dsi->pixel_overlap);
>>   	}
>>   
>>   	for_each_dsi_port(port, intel_dsi->ports) {
>> diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c
>> index 3f7f416eb3fa..969e32143983 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dss.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dss.c
>> @@ -7,6 +7,7 @@
>>   #include "i915_reg_defs.h"
>>   #include "intel_de.h"
>>   #include "intel_display_types.h"
>> +#include "intel_dsi.h"
>>   #include "intel_dss.h"
>>   #include "intel_dss_regs.h"
>>   
>> @@ -87,3 +88,52 @@ void intel_dss_mso_configure(const struct intel_crtc_state *crtc_state)
>>   		     SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
>>   		     OVERLAP_PIXELS_MASK, dss1);
>>   }
>> +
>> +void intel_dss_dsi_dual_link_mode_configure(struct intel_encoder *encoder,
>> +					    const struct intel_crtc_state *pipe_config,
>> +					    u8 dual_link,
>> +					    u8 pixel_overlap)
>> +{
>> +	struct intel_display *display = to_intel_display(encoder);
>> +	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
>> +	u32 dss_ctl1;
>> +
>> +	if (DISPLAY_VER(display) >= 12) {
>> +		struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>> +
>> +		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
>> +		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
>> +	} else {
>> +		dss_ctl1_reg = DSS_CTL1;
>> +		dss_ctl2_reg = DSS_CTL2;
>> +	}
>> +
>> +	dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
>> +	dss_ctl1 |= SPLITTER_ENABLE;
>> +	dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
>> +	dss_ctl1 |= OVERLAP_PIXELS(pixel_overlap);
>> +
>> +	if (dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>> +		const struct drm_display_mode *adjusted_mode =
>> +					&pipe_config->hw.adjusted_mode;
>> +		u16 hactive = adjusted_mode->crtc_hdisplay;
>> +		u16 dl_buffer_depth;
>> +
>> +		dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
>> +		dl_buffer_depth = hactive / 2 + pixel_overlap;
>> +
>> +		if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
>> +			drm_err(display->drm,
>> +				"DL buffer depth exceed max value\n");
>> +
>> +		dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
>> +		dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
>> +		intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
>> +			     RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
> Leaking the DSI mess outside of the DSI code is not great. The DSI
> code should really just be taught to use the crtc_state properly.

I do agree. Perhaps have a separate structure for DSS in 
intel_crtc_state with relevant bits, which would be computed in 
compute_config and then we write it one time.

Can we have a separate patch series to fix this and mso part, and just 
have DSS, joiner things separated from VDSC as a first step?

Regards,

Ankit


>
>> +	} else {
>> +		/* Interleave */
>> +		dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
>> +	}
>> +
>> +	intel_de_write(display, dss_ctl1_reg, dss_ctl1);
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h
>> index d4629052979a..aa8c67c15855 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dss.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dss.h
>> @@ -16,5 +16,8 @@ u8 intel_dss_mso_pipe_mask(struct intel_display *display);
>>   void intel_dss_mso_get_config(struct intel_encoder *encoder,
>>   			      struct intel_crtc_state *pipe_config);
>>   void intel_dss_mso_configure(const struct intel_crtc_state *crtc_state);
>> +void intel_dss_dsi_dual_link_mode_configure(struct intel_encoder *encoder,
>> +					    const struct intel_crtc_state *pipe_config,
>> +					    u8 dual_link, u8 pixel_overlap);
>>   
>>   #endif /* __INTEL_DSS_H__ */
>> -- 
>> 2.45.2