From: "Govindapillai, Vinod" <vinod.govindapillai@intel.com>
To: "intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Deak, Imre" <imre.deak@intel.com>
Subject: Re: [PATCH 23/50] drm/i915/dp: Pass intel_output_format to intel_dp_dsc_sink_{min_max}_compressed_bpp()
Date: Fri, 12 Dec 2025 09:27:28 +0000 [thread overview]
Message-ID: <a791c9d59d80ef707758bf55392db235a2ece4f8.camel@intel.com> (raw)
In-Reply-To: <20251127175023.1522538-24-imre.deak@intel.com>
On Thu, 2025-11-27 at 19:49 +0200, Imre Deak wrote:
> Prepare for follow-up changes also calling
> intel_dp_dsc_min_sink_compressed_bpp() /
> intel_dp_dsc_max_sink_compressed_bpp_x16()
> without an intel_crtc_state.
>
> While at it remove the stale function declarations from the header
> file.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 24 ++++++++++++-----------
> -
> drivers/gpu/drm/i915/display/intel_dp.h | 4 ----
> 2 files changed, 12 insertions(+), 16 deletions(-)
>
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5ad71e697e585..54a037fcf5111 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2156,7 +2156,7 @@ static int dsc_compute_link_config(struct
> intel_dp *intel_dp,
>
> static
> u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct
> intel_connector *connector,
> - const struct
> intel_crtc_state *pipe_config,
> + enum intel_output_format
> output_format,
> int bpc)
> {
> u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector-
> >dp.dsc_dpcd);
> @@ -2167,43 +2167,43 @@ u16
> intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector
> *connec
> * If support not given in DPCD 67h, 68h use the Maximum
> Allowed bit rate
> * values as given in spec Table 2-157 DP v2.0
> */
> - switch (pipe_config->output_format) {
> + switch (output_format) {
> case INTEL_OUTPUT_FORMAT_RGB:
> case INTEL_OUTPUT_FORMAT_YCBCR444:
> return (3 * bpc) << 4;
> case INTEL_OUTPUT_FORMAT_YCBCR420:
> return (3 * (bpc / 2)) << 4;
> default:
> - MISSING_CASE(pipe_config->output_format);
> + MISSING_CASE(output_format);
> break;
> }
>
> return 0;
> }
>
> -int intel_dp_dsc_sink_min_compressed_bpp(const struct
> intel_crtc_state *pipe_config)
> +static int intel_dp_dsc_sink_min_compressed_bpp(enum
> intel_output_format output_format)
> {
> /* From Mandatory bit rate range Support Table 2-157 (DP
> v2.0) */
> - switch (pipe_config->output_format) {
> + switch (output_format) {
> case INTEL_OUTPUT_FORMAT_RGB:
> case INTEL_OUTPUT_FORMAT_YCBCR444:
> return 8;
> case INTEL_OUTPUT_FORMAT_YCBCR420:
> return 6;
> default:
> - MISSING_CASE(pipe_config->output_format);
> + MISSING_CASE(output_format);
> break;
> }
>
> return 0;
> }
>
> -int intel_dp_dsc_sink_max_compressed_bpp(const struct
> intel_connector *connector,
> - const struct
> intel_crtc_state *pipe_config,
> - int bpc)
> +static int intel_dp_dsc_sink_max_compressed_bpp(const struct
> intel_connector *connector,
> + enum
> intel_output_format output_format,
> + int bpc)
> {
> return intel_dp_dsc_max_sink_compressed_bppx16(connector,
> - pipe_config,
> bpc) >> 4;
> +
> output_format, bpc) >> 4;
> }
>
> int intel_dp_dsc_min_src_compressed_bpp(void)
> @@ -2683,7 +2683,7 @@ intel_dp_compute_config_link_bpp_limits(struct
> intel_connector *connector,
> int joiner_max_bpp;
>
> dsc_src_min_bpp =
> intel_dp_dsc_min_src_compressed_bpp();
> - dsc_sink_min_bpp =
> intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
> + dsc_sink_min_bpp =
> intel_dp_dsc_sink_min_compressed_bpp(crtc_state->output_format);
> dsc_min_bpp = max(dsc_src_min_bpp,
> dsc_sink_min_bpp);
> limits->link.min_bpp_x16 =
> fxp_q4_from_int(dsc_min_bpp);
>
> @@ -2697,7 +2697,7 @@ intel_dp_compute_config_link_bpp_limits(struct
> intel_connector *connector,
>
> adjusted_mode->hdisplay,
>
> intel_crtc_num_joined_pipes(crtc_state));
> dsc_sink_max_bpp =
> intel_dp_dsc_sink_max_compressed_bpp(connector,
> -
> crtc_state,
> +
> crtc_state->output_format,
>
> limits->pipe.max_bpp / 3);
> dsc_max_bpp = min(dsc_sink_max_bpp,
> dsc_src_max_bpp);
> dsc_max_bpp = min(dsc_max_bpp, joiner_max_bpp);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 30eebb8cad6d2..489b8c945da39 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -150,10 +150,6 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct
> intel_display *display,
> enum intel_output_format
> output_format,
> u32 pipe_bpp,
> u32 timeslots);
> -int intel_dp_dsc_sink_min_compressed_bpp(const struct
> intel_crtc_state *pipe_config);
> -int intel_dp_dsc_sink_max_compressed_bpp(const struct
> intel_connector *connector,
> - const struct
> intel_crtc_state *pipe_config,
> - int bpc);
> bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp,
> int bpp_x16);
> u8 intel_dp_dsc_get_slice_count(const struct intel_connector
> *connector,
> int mode_clock, int mode_hdisplay,
next prev parent reply other threads:[~2025-12-12 9:27 UTC|newest]
Thread overview: 141+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-27 17:49 [PATCH 00/50] drm/i915/dp: Clean up link BW/DSC slice config computation Imre Deak
2025-11-27 17:49 ` [PATCH 01/50] drm/dp: Parse all DSC slice count caps for eDP 1.5 Imre Deak
2025-12-08 11:24 ` Luca Coelho
2025-12-08 12:36 ` Imre Deak
2025-11-27 17:49 ` [PATCH 02/50] drm/dp: Add drm_dp_dsc_sink_slice_count_mask() Imre Deak
2025-12-09 8:48 ` Luca Coelho
2025-11-27 17:49 ` [PATCH 03/50] drm/i915/dp: Fix DSC sink's slice count capability check Imre Deak
2025-12-09 8:51 ` Luca Coelho
2025-12-09 9:53 ` Imre Deak
2025-12-09 11:14 ` Luca Coelho
2025-11-27 17:49 ` [PATCH 04/50] drm/i915/dp: Return a fixed point BPP value from intel_dp_output_bpp() Imre Deak
2025-12-09 9:10 ` Luca Coelho
2025-11-27 17:49 ` [PATCH 05/50] drm/i915/dp: Use a mode's crtc_clock vs. clock during state computation Imre Deak
2025-12-09 12:51 ` Luca Coelho
2025-11-27 17:49 ` [PATCH 06/50] drm/i915/dp: Factor out intel_dp_link_bw_overhead() Imre Deak
2025-12-09 12:52 ` Luca Coelho
2025-11-27 17:49 ` [PATCH 07/50] drm/i915/dp: Fix BW check in is_bw_sufficient_for_dsc_config() Imre Deak
2025-12-09 12:53 ` Luca Coelho
2025-11-27 17:49 ` [PATCH 08/50] drm/i915/dp: Use the effective data rate for DP BW calculation Imre Deak
2025-12-10 12:48 ` Luca Coelho
2025-11-27 17:49 ` [PATCH 09/50] drm/i915/dp: Use the effective data rate for DP compressed " Imre Deak
2025-12-10 12:50 ` Luca Coelho
2025-11-27 17:49 ` [PATCH 10/50] drm/i915/dp: Account with MST, SSC BW overhead for uncompressed DP-MST stream BW Imre Deak
2025-12-10 13:08 ` Luca Coelho
2025-11-27 17:49 ` [PATCH 11/50] drm/i915/dp: Account with DSC BW overhead for compressed DP-SST " Imre Deak
2025-12-10 13:39 ` Luca Coelho
2025-11-27 17:49 ` [PATCH 12/50] drm/i915/dp: Account with pipe joiner max compressed BPP limit for DP-MST and eDP Imre Deak
2025-12-10 14:29 ` Luca Coelho
2025-11-27 17:49 ` [PATCH 13/50] drm/i915/dp: Drop unused timeslots param from dsc_compute_link_config() Imre Deak
2025-12-10 14:31 ` Luca Coelho
2025-11-27 17:49 ` [PATCH 14/50] drm/i915/dp: Factor out align_max_sink_dsc_input_bpp() Imre Deak
2025-12-12 15:41 ` Govindapillai, Vinod
2025-12-15 7:46 ` Luca Coelho
2025-12-15 11:53 ` Imre Deak
2025-12-15 12:02 ` Luca Coelho
2025-12-15 12:33 ` Imre Deak
2025-11-27 17:49 ` [PATCH 15/50] drm/i915/dp: Factor out align_max_vesa_compressed_bpp_x16() Imre Deak
2025-12-12 15:46 ` Govindapillai, Vinod
2025-12-15 7:49 ` Luca Coelho
2025-12-15 12:00 ` Imre Deak
2025-12-15 12:08 ` Luca Coelho
2025-12-15 12:24 ` Imre Deak
2025-11-27 17:49 ` [PATCH 16/50] drm/i915/dp: Fail state computation for invalid min/max link BPP values Imre Deak
2025-12-12 15:48 ` Govindapillai, Vinod
2025-12-15 7:51 ` Luca Coelho
2025-11-27 17:49 ` [PATCH 17/50] drm/i915/dp: Fail state computation for invalid max throughput BPP value Imre Deak
2025-12-12 15:51 ` Govindapillai, Vinod
2025-12-15 7:51 ` Luca Coelho
2025-11-27 17:49 ` [PATCH 18/50] drm/i915/dp: Fail state computation for invalid max sink compressed " Imre Deak
2025-12-12 15:52 ` Govindapillai, Vinod
2025-12-15 7:52 ` Luca Coelho
2025-11-27 17:49 ` [PATCH 19/50] drm/i915/dp: Fail state computation for invalid DSC source input BPP values Imre Deak
2025-12-11 8:29 ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 20/50] drm/i915/dp: Align min/max DSC input BPPs to sink caps Imre Deak
2025-12-11 8:51 ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 21/50] drm/i915/dp: Align min/max compressed BPPs when calculating BPP limits Imre Deak
2025-12-12 9:17 ` Govindapillai, Vinod
2025-12-12 11:09 ` Imre Deak
2025-11-27 17:49 ` [PATCH 22/50] drm/i915/dp: Drop intel_dp parameter from intel_dp_compute_config_link_bpp_limits() Imre Deak
2025-12-12 9:23 ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 23/50] drm/i915/dp: Pass intel_output_format to intel_dp_dsc_sink_{min_max}_compressed_bpp() Imre Deak
2025-12-12 9:27 ` Govindapillai, Vinod [this message]
2025-11-27 17:49 ` [PATCH 24/50] drm/i915/dp: Pass mode clock to dsc_throughput_quirk_max_bpp_x16() Imre Deak
2025-12-12 9:31 ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 25/50] drm/i915/dp: Factor out compute_min_compressed_bpp_x16() Imre Deak
2025-12-12 9:39 ` Govindapillai, Vinod
2025-12-12 11:01 ` Imre Deak
2025-12-12 11:41 ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 26/50] drm/i915/dp: Factor out compute_max_compressed_bpp_x16() Imre Deak
2025-12-12 9:50 ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 27/50] drm/i915/dp: Add intel_dp_mode_valid_with_dsc() Imre Deak
2025-12-12 11:43 ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 28/50] drm/i915/dp: Unify detect and compute time DSC mode BW validation Imre Deak
2025-12-12 14:29 ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 29/50] drm/i915/dp: Use helpers to align min/max compressed BPPs Imre Deak
2025-12-12 14:34 ` Govindapillai, Vinod
2025-12-12 14:39 ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 30/50] drm/i915/dp: Simplify computing DSC BPPs for eDP Imre Deak
2025-12-12 14:45 ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 31/50] drm/i915/dp: Simplify computing DSC BPPs for DP-SST Imre Deak
2025-12-12 14:59 ` Govindapillai, Vinod
2025-12-12 18:41 ` Imre Deak
2025-11-27 17:50 ` [PATCH 32/50] drm/i915/dp: Simplify computing forced DSC BPP " Imre Deak
2025-12-12 15:21 ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 33/50] drm/i915/dp: Unify computing compressed BPP for DP-SST and eDP Imre Deak
2025-12-12 15:38 ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 34/50] drm/i915/dp: Simplify eDP vs. DP compressed BPP computation Imre Deak
2025-12-12 15:39 ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 35/50] drm/i915/dp: Simplify computing the DSC compressed BPP for DP-MST Imre Deak
2025-12-08 13:08 ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 36/50] drm/i915/dsc: Track the detaild DSC slice configuration Imre Deak
2025-12-09 8:24 ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 37/50] drm/i915/dsc: Track the DSC stream count in the DSC slice config state Imre Deak
2025-12-09 8:28 ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 38/50] drm/i915/dsi: Move initialization of DSI DSC streams-per-pipe to fill_dsc() Imre Deak
2025-12-09 8:47 ` Hogander, Jouni
2025-12-09 10:38 ` Imre Deak
2025-12-09 11:37 ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 39/50] drm/i915/dsi: Track the detailed DSC slice configuration Imre Deak
2025-12-09 12:43 ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 40/50] drm/i915/dp: " Imre Deak
2025-12-09 14:06 ` Hogander, Jouni
2025-12-09 14:30 ` Imre Deak
2025-12-09 17:50 ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 41/50] drm/i915/dsc: Switch to using intel_dsc_line_slice_count() Imre Deak
2025-12-09 17:14 ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 42/50] drm/i915/dp: Factor out intel_dp_dsc_min_slice_count() Imre Deak
2025-12-09 17:26 ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 43/50] drm/i915/dp: Use int for DSC slice count variables Imre Deak
2025-12-09 17:30 ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 44/50] drm/i915/dp: Rename test_slice_count to slices_per_line Imre Deak
2025-12-09 17:34 ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 45/50] drm/i915/dp: Simplify the DSC slice config loop's slices-per-pipe iteration Imre Deak
2025-12-10 12:38 ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 46/50] drm/i915/dsc: Add intel_dsc_get_slice_config() Imre Deak
2025-12-10 14:06 ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 47/50] drm/i915/dsi: Use intel_dsc_get_slice_config() Imre Deak
2025-12-10 14:44 ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 48/50] drm/i915/dp: Unify DP and eDP slice count computation Imre Deak
2025-12-11 6:48 ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 49/50] drm/i915/dp: Add intel_dp_dsc_get_slice_config() Imre Deak
2025-12-11 6:55 ` Hogander, Jouni
2025-12-11 9:52 ` Imre Deak
2025-12-12 18:17 ` [PATCH v2 " Imre Deak
2025-12-15 6:06 ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 50/50] drm/i915/dp: Use intel_dp_dsc_get_slice_config() Imre Deak
2025-12-11 6:59 ` Hogander, Jouni
2025-12-11 10:23 ` Imre Deak
2025-12-12 18:03 ` Imre Deak
2025-12-12 18:17 ` [PATCH v2 " Imre Deak
2025-11-27 20:28 ` ✗ CI.checkpatch: warning for drm/i915/dp: Clean up link BW/DSC slice config computation Patchwork
2025-11-27 20:29 ` ✓ CI.KUnit: success " Patchwork
2025-11-27 20:44 ` ✗ CI.checksparse: warning " Patchwork
2025-11-27 21:47 ` ✓ Xe.CI.BAT: success " Patchwork
2025-11-27 23:11 ` ✗ Xe.CI.Full: failure " Patchwork
[not found] ` <20251128162050.1600107-1-imre.deak@intel.com>
2025-12-12 13:23 ` [CI 09/50] drm/i915/dp: Use the effective data rate for DP compressed BW calculation Govindapillai, Vinod
2025-12-12 20:45 ` ✗ CI.checkpatch: warning for drm/i915/dp: Clean up link BW/DSC slice config computation (rev3) Patchwork
2025-12-12 20:46 ` ✓ CI.KUnit: success " Patchwork
2025-12-12 21:01 ` ✗ CI.checksparse: warning " Patchwork
2025-12-12 22:03 ` ✓ Xe.CI.BAT: success " Patchwork
2025-12-13 16:47 ` ✗ Xe.CI.Full: failure " Patchwork
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