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From: "Hogander, Jouni" <jouni.hogander@intel.com>
To: "intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Deak, Imre" <imre.deak@intel.com>
Subject: Re: [PATCH 46/50] drm/i915/dsc: Add intel_dsc_get_slice_config()
Date: Wed, 10 Dec 2025 14:06:38 +0000	[thread overview]
Message-ID: <b4d8ed0f1c6d2010ecbd1fd04010655254e5bc7a.camel@intel.com> (raw)
In-Reply-To: <20251127175023.1522538-47-imre.deak@intel.com>

On Thu, 2025-11-27 at 19:50 +0200, Imre Deak wrote:
> Add intel_dsc_get_slice_config() and move the logic to select a given
> slice configuration to that function from the configuration loop in
> intel_dp_dsc_get_slice_count(). The same functionality can be used by
> other outputs like DSI as well, done as a follow-up.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c   | 22 ++++-------
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 48
> +++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_vdsc.h |  4 ++
>  3 files changed, 59 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index a4ff1ffc8f7d4..461f80bd54cbf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1029,28 +1029,20 @@ u8 intel_dp_dsc_get_slice_count(const struct
> intel_connector *connector,
>  	 * TGL+: 2x4 (TODO: Add support for this)
>  	 */
>  	for (slices_per_pipe = 1; slices_per_pipe <= 4;
> slices_per_pipe++) {
> -		int slices_per_line = slices_per_pipe *
> num_joined_pipes;
> +		struct intel_dsc_slice_config config;
> +		int slices_per_line;
>  
> -		/*
> -		 * 3 DSC Slices per pipe need 3 DSC engines, which
> is supported only
> -		 * with Ultrajoiner only for some platforms.
> -		 */
> -		if (slices_per_pipe == 3 &&
> -		    (!HAS_DSC_3ENGINES(display) || num_joined_pipes
> != 4))
> +		if (!intel_dsc_get_slice_config(display,
> +						num_joined_pipes,
> slices_per_pipe,
> +						&config))
>  			continue;
>  
> +		slices_per_line =
> intel_dsc_line_slice_count(&config);
> +
>  		if
> (!(drm_dp_dsc_slice_count_to_mask(slices_per_line) &
>  		      sink_slice_count_mask))
>  			continue;
>  
> -		 /*
> -		  * Bigjoiner needs small joiner to be enabled.
> -		  * So there should be at least 2 dsc slices per
> pipe,
> -		  * whenever bigjoiner is enabled.
> -		  */
> -		if (num_joined_pipes > 1 && slices_per_pipe < 2)
> -			continue;
> -
>  		if (mode_hdisplay % slices_per_line)
>  			continue;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 190ce567bc7fa..9910134d52653 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -40,6 +40,54 @@ int intel_dsc_line_slice_count(const struct
> intel_dsc_slice_config *config)
>  	return config->pipes_per_line * config->streams_per_pipe *
> config->slices_per_stream;
>  }
>  
> +bool intel_dsc_get_slice_config(struct intel_display *display,
> +				int pipes_per_line, int
> slices_per_pipe,
> +				struct intel_dsc_slice_config
> *config)
> +{
> +	int streams_per_pipe;
> +
> +	/* TODO: Add support for 8 slices per pipe on TGL+. */
> +	switch (slices_per_pipe) {
> +	case 3:
> +		/*
> +		 * 3 DSC Slices per pipe need 3 DSC engines, which
> is supported only
> +		 * with Ultrajoiner only for some platforms.
> +		 */
> +		if (!HAS_DSC_3ENGINES(display) || pipes_per_line !=
> 4)
> +			return false;
> +
> +		streams_per_pipe = 3;
> +		break;
> +	case 4:
> +		/* TODO: Consider using 1 DSC engine stream x 4
> slices instead. */
> +	case 2:
> +		/* TODO: Consider using 1 DSC engine stream x 2
> slices instead. */
> +		streams_per_pipe = 2;
> +		break;
> +	case 1:
> +		 /*
> +		  * Bigjoiner needs small joiner to be enabled.
> +		  * So there should be at least 2 dsc slices per
> pipe,
> +		  * whenever bigjoiner is enabled.
> +		  */
> +		if (pipes_per_line > 1)
> +			return false;
> +
> +		streams_per_pipe = 1;
> +		break;
> +	default:
> +		MISSING_CASE(slices_per_pipe);
> +		return false;
> +	}
> +
> +	config->pipes_per_line = pipes_per_line;
> +	config->streams_per_pipe = streams_per_pipe;
> +	config->slices_per_stream = slices_per_pipe /
> streams_per_pipe;
> +
> +	return true;
> +}
> +
> +
>  static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder
> cpu_transcoder)
>  {
>  	struct intel_display *display = to_intel_display(crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h
> b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index e61116d5297c8..aeb17670307b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -13,11 +13,15 @@ struct drm_printer;
>  enum transcoder;
>  struct intel_crtc;
>  struct intel_crtc_state;
> +struct intel_display;
>  struct intel_dsc_slice_config;
>  struct intel_encoder;
>  
>  bool intel_dsc_source_support(const struct intel_crtc_state
> *crtc_state);
>  int intel_dsc_line_slice_count(const struct intel_dsc_slice_config
> *config);
> +bool intel_dsc_get_slice_config(struct intel_display *display,
> +				int num_joined_pipes, int
> slice_per_pipe,
> +				struct intel_dsc_slice_config
> *config);
>  void intel_uncompressed_joiner_enable(const struct intel_crtc_state
> *crtc_state);
>  void intel_dsc_enable(const struct intel_crtc_state *crtc_state);
>  void intel_dsc_disable(const struct intel_crtc_state *crtc_state);


  reply	other threads:[~2025-12-10 14:06 UTC|newest]

Thread overview: 141+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-27 17:49 [PATCH 00/50] drm/i915/dp: Clean up link BW/DSC slice config computation Imre Deak
2025-11-27 17:49 ` [PATCH 01/50] drm/dp: Parse all DSC slice count caps for eDP 1.5 Imre Deak
2025-12-08 11:24   ` Luca Coelho
2025-12-08 12:36     ` Imre Deak
2025-11-27 17:49 ` [PATCH 02/50] drm/dp: Add drm_dp_dsc_sink_slice_count_mask() Imre Deak
2025-12-09  8:48   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 03/50] drm/i915/dp: Fix DSC sink's slice count capability check Imre Deak
2025-12-09  8:51   ` Luca Coelho
2025-12-09  9:53     ` Imre Deak
2025-12-09 11:14       ` Luca Coelho
2025-11-27 17:49 ` [PATCH 04/50] drm/i915/dp: Return a fixed point BPP value from intel_dp_output_bpp() Imre Deak
2025-12-09  9:10   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 05/50] drm/i915/dp: Use a mode's crtc_clock vs. clock during state computation Imre Deak
2025-12-09 12:51   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 06/50] drm/i915/dp: Factor out intel_dp_link_bw_overhead() Imre Deak
2025-12-09 12:52   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 07/50] drm/i915/dp: Fix BW check in is_bw_sufficient_for_dsc_config() Imre Deak
2025-12-09 12:53   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 08/50] drm/i915/dp: Use the effective data rate for DP BW calculation Imre Deak
2025-12-10 12:48   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 09/50] drm/i915/dp: Use the effective data rate for DP compressed " Imre Deak
2025-12-10 12:50   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 10/50] drm/i915/dp: Account with MST, SSC BW overhead for uncompressed DP-MST stream BW Imre Deak
2025-12-10 13:08   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 11/50] drm/i915/dp: Account with DSC BW overhead for compressed DP-SST " Imre Deak
2025-12-10 13:39   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 12/50] drm/i915/dp: Account with pipe joiner max compressed BPP limit for DP-MST and eDP Imre Deak
2025-12-10 14:29   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 13/50] drm/i915/dp: Drop unused timeslots param from dsc_compute_link_config() Imre Deak
2025-12-10 14:31   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 14/50] drm/i915/dp: Factor out align_max_sink_dsc_input_bpp() Imre Deak
2025-12-12 15:41   ` Govindapillai, Vinod
2025-12-15  7:46   ` Luca Coelho
2025-12-15 11:53     ` Imre Deak
2025-12-15 12:02       ` Luca Coelho
2025-12-15 12:33         ` Imre Deak
2025-11-27 17:49 ` [PATCH 15/50] drm/i915/dp: Factor out align_max_vesa_compressed_bpp_x16() Imre Deak
2025-12-12 15:46   ` Govindapillai, Vinod
2025-12-15  7:49   ` Luca Coelho
2025-12-15 12:00     ` Imre Deak
2025-12-15 12:08       ` Luca Coelho
2025-12-15 12:24         ` Imre Deak
2025-11-27 17:49 ` [PATCH 16/50] drm/i915/dp: Fail state computation for invalid min/max link BPP values Imre Deak
2025-12-12 15:48   ` Govindapillai, Vinod
2025-12-15  7:51   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 17/50] drm/i915/dp: Fail state computation for invalid max throughput BPP value Imre Deak
2025-12-12 15:51   ` Govindapillai, Vinod
2025-12-15  7:51   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 18/50] drm/i915/dp: Fail state computation for invalid max sink compressed " Imre Deak
2025-12-12 15:52   ` Govindapillai, Vinod
2025-12-15  7:52   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 19/50] drm/i915/dp: Fail state computation for invalid DSC source input BPP values Imre Deak
2025-12-11  8:29   ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 20/50] drm/i915/dp: Align min/max DSC input BPPs to sink caps Imre Deak
2025-12-11  8:51   ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 21/50] drm/i915/dp: Align min/max compressed BPPs when calculating BPP limits Imre Deak
2025-12-12  9:17   ` Govindapillai, Vinod
2025-12-12 11:09     ` Imre Deak
2025-11-27 17:49 ` [PATCH 22/50] drm/i915/dp: Drop intel_dp parameter from intel_dp_compute_config_link_bpp_limits() Imre Deak
2025-12-12  9:23   ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 23/50] drm/i915/dp: Pass intel_output_format to intel_dp_dsc_sink_{min_max}_compressed_bpp() Imre Deak
2025-12-12  9:27   ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 24/50] drm/i915/dp: Pass mode clock to dsc_throughput_quirk_max_bpp_x16() Imre Deak
2025-12-12  9:31   ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 25/50] drm/i915/dp: Factor out compute_min_compressed_bpp_x16() Imre Deak
2025-12-12  9:39   ` Govindapillai, Vinod
2025-12-12 11:01     ` Imre Deak
2025-12-12 11:41       ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 26/50] drm/i915/dp: Factor out compute_max_compressed_bpp_x16() Imre Deak
2025-12-12  9:50   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 27/50] drm/i915/dp: Add intel_dp_mode_valid_with_dsc() Imre Deak
2025-12-12 11:43   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 28/50] drm/i915/dp: Unify detect and compute time DSC mode BW validation Imre Deak
2025-12-12 14:29   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 29/50] drm/i915/dp: Use helpers to align min/max compressed BPPs Imre Deak
2025-12-12 14:34   ` Govindapillai, Vinod
2025-12-12 14:39   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 30/50] drm/i915/dp: Simplify computing DSC BPPs for eDP Imre Deak
2025-12-12 14:45   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 31/50] drm/i915/dp: Simplify computing DSC BPPs for DP-SST Imre Deak
2025-12-12 14:59   ` Govindapillai, Vinod
2025-12-12 18:41     ` Imre Deak
2025-11-27 17:50 ` [PATCH 32/50] drm/i915/dp: Simplify computing forced DSC BPP " Imre Deak
2025-12-12 15:21   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 33/50] drm/i915/dp: Unify computing compressed BPP for DP-SST and eDP Imre Deak
2025-12-12 15:38   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 34/50] drm/i915/dp: Simplify eDP vs. DP compressed BPP computation Imre Deak
2025-12-12 15:39   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 35/50] drm/i915/dp: Simplify computing the DSC compressed BPP for DP-MST Imre Deak
2025-12-08 13:08   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 36/50] drm/i915/dsc: Track the detaild DSC slice configuration Imre Deak
2025-12-09  8:24   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 37/50] drm/i915/dsc: Track the DSC stream count in the DSC slice config state Imre Deak
2025-12-09  8:28   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 38/50] drm/i915/dsi: Move initialization of DSI DSC streams-per-pipe to fill_dsc() Imre Deak
2025-12-09  8:47   ` Hogander, Jouni
2025-12-09 10:38     ` Imre Deak
2025-12-09 11:37       ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 39/50] drm/i915/dsi: Track the detailed DSC slice configuration Imre Deak
2025-12-09 12:43   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 40/50] drm/i915/dp: " Imre Deak
2025-12-09 14:06   ` Hogander, Jouni
2025-12-09 14:30     ` Imre Deak
2025-12-09 17:50       ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 41/50] drm/i915/dsc: Switch to using intel_dsc_line_slice_count() Imre Deak
2025-12-09 17:14   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 42/50] drm/i915/dp: Factor out intel_dp_dsc_min_slice_count() Imre Deak
2025-12-09 17:26   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 43/50] drm/i915/dp: Use int for DSC slice count variables Imre Deak
2025-12-09 17:30   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 44/50] drm/i915/dp: Rename test_slice_count to slices_per_line Imre Deak
2025-12-09 17:34   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 45/50] drm/i915/dp: Simplify the DSC slice config loop's slices-per-pipe iteration Imre Deak
2025-12-10 12:38   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 46/50] drm/i915/dsc: Add intel_dsc_get_slice_config() Imre Deak
2025-12-10 14:06   ` Hogander, Jouni [this message]
2025-11-27 17:50 ` [PATCH 47/50] drm/i915/dsi: Use intel_dsc_get_slice_config() Imre Deak
2025-12-10 14:44   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 48/50] drm/i915/dp: Unify DP and eDP slice count computation Imre Deak
2025-12-11  6:48   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 49/50] drm/i915/dp: Add intel_dp_dsc_get_slice_config() Imre Deak
2025-12-11  6:55   ` Hogander, Jouni
2025-12-11  9:52     ` Imre Deak
2025-12-12 18:17   ` [PATCH v2 " Imre Deak
2025-12-15  6:06     ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 50/50] drm/i915/dp: Use intel_dp_dsc_get_slice_config() Imre Deak
2025-12-11  6:59   ` Hogander, Jouni
2025-12-11 10:23     ` Imre Deak
2025-12-12 18:03       ` Imre Deak
2025-12-12 18:17   ` [PATCH v2 " Imre Deak
2025-11-27 20:28 ` ✗ CI.checkpatch: warning for drm/i915/dp: Clean up link BW/DSC slice config computation Patchwork
2025-11-27 20:29 ` ✓ CI.KUnit: success " Patchwork
2025-11-27 20:44 ` ✗ CI.checksparse: warning " Patchwork
2025-11-27 21:47 ` ✓ Xe.CI.BAT: success " Patchwork
2025-11-27 23:11 ` ✗ Xe.CI.Full: failure " Patchwork
     [not found] ` <20251128162050.1600107-1-imre.deak@intel.com>
2025-12-12 13:23   ` [CI 09/50] drm/i915/dp: Use the effective data rate for DP compressed BW calculation Govindapillai, Vinod
2025-12-12 20:45 ` ✗ CI.checkpatch: warning for drm/i915/dp: Clean up link BW/DSC slice config computation (rev3) Patchwork
2025-12-12 20:46 ` ✓ CI.KUnit: success " Patchwork
2025-12-12 21:01 ` ✗ CI.checksparse: warning " Patchwork
2025-12-12 22:03 ` ✓ Xe.CI.BAT: success " Patchwork
2025-12-13 16:47 ` ✗ Xe.CI.Full: failure " Patchwork

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