* [PATCH 0/5] Optimize vrr.guardband
@ 2025-10-17 5:01 Ankit Nautiyal
2025-10-17 5:01 ` [PATCH 1/5] drm/i915/psr: Add helper to get min psr guardband Ankit Nautiyal
` (8 more replies)
0 siblings, 9 replies; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-17 5:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal
Instead of setting vrr.guardband to vblank, use optimal guardband that
works for most of the cases. This will help in avoiding need of change
in guardband and fix the LRR feature that needs seamless switching to
a lower refresh rate.
Rev2:
- Drop patch to check guardband in crtc_check phase, instead check
guardband for SDP in compute_config_late.
- Modify the helper to get the min sdp guardband if all SDPs are assumed
to be enabled.
- Rename the helpers to get min guardband for sdp and psr.
Rev3:
- Drop the squashed patches as the dependency changes are already
merged.
- Avoid optimized guardband for HDMI for now.
- Allow support for optmized guardband only to platforms that always have
VRR TG active in the main patch.
- Add a separate patch for extending support for optimized guardband to
other platforms whenever VRR TG gets enabled.
Ankit Nautiyal (5):
drm/i915/psr: Add helper to get min psr guardband
drm/i915/dp: Add helper to get min sdp guardband
drm/i915/dp: Check if guardband can accommodate sdp latencies
drm/i915/vrr: Use the min static optimized guardband
drm/i915/vrr: Use optimized guardband whenever VRR TG is active
drivers/gpu/drm/i915/display/intel_dp.c | 58 ++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 2 +
drivers/gpu/drm/i915/display/intel_psr.c | 12 +++++
drivers/gpu/drm/i915/display/intel_psr.h | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 62 +++++++++++++++++++++++-
5 files changed, 133 insertions(+), 2 deletions(-)
--
2.45.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 1/5] drm/i915/psr: Add helper to get min psr guardband
2025-10-17 5:01 [PATCH 0/5] Optimize vrr.guardband Ankit Nautiyal
@ 2025-10-17 5:01 ` Ankit Nautiyal
2025-10-17 9:07 ` Hogander, Jouni
2025-10-17 5:01 ` [PATCH 2/5] drm/i915/dp: Add helper to get min sdp guardband Ankit Nautiyal
` (7 subsequent siblings)
8 siblings, 1 reply; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-17 5:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal
Introduce a helper to compute the max link wake latency when using
Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.
This will be used to compute the minimum guardband so that the link wake
latencies are accounted and these features work smoothly for higher
refresh rate panels.
Bspec: 70151, 71477
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
drivers/gpu/drm/i915/display/intel_psr.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 703e5f6af04c..a8303b669853 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -4416,3 +4416,15 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp,
intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
}
+
+int intel_psr_min_guardband(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ int auxless_wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
+ int wake_lines = DISPLAY_VER(display) < 20 ?
+ psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
+ crtc_state->alpm_state.fast_wake_lines) :
+ crtc_state->alpm_state.io_wake_lines;
+
+ return max(auxless_wake_lines, wake_lines);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index b17ce312dc37..620b35928832 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -85,5 +85,6 @@ bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
void intel_psr_compute_config_late(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state);
+int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
#endif /* __INTEL_PSR_H__ */
--
2.45.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 2/5] drm/i915/dp: Add helper to get min sdp guardband
2025-10-17 5:01 [PATCH 0/5] Optimize vrr.guardband Ankit Nautiyal
2025-10-17 5:01 ` [PATCH 1/5] drm/i915/psr: Add helper to get min psr guardband Ankit Nautiyal
@ 2025-10-17 5:01 ` Ankit Nautiyal
2025-10-17 10:50 ` Hogander, Jouni
2025-10-17 5:02 ` [PATCH 3/5] drm/i915/dp: Check if guardband can accommodate sdp latencies Ankit Nautiyal
` (6 subsequent siblings)
8 siblings, 1 reply; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-17 5:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal
Add a helper to compute vblank time needed for transmitting specific
DisplayPort SDPs like PPS, GAMUT_METADATA, and VSC_EXT. Latency is
based on line count per packet type.
This will be used to ensure adequate guardband when features like DSC/HDR
are enabled.
Bspec: 70151
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 36 +++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
2 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7059d55687cf..3f2c319e3d6f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6990,3 +6990,39 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
return 0;
}
+
+static
+int intel_dp_get_lines_for_sdp(u32 type)
+{
+ switch (type) {
+ case DP_SDP_VSC_EXT_VESA:
+ case DP_SDP_VSC_EXT_CEA:
+ return 10;
+ case HDMI_PACKET_TYPE_GAMUT_METADATA:
+ return 8;
+ case DP_SDP_PPS:
+ return 6;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
+ bool assume_all_enabled)
+{
+ int sdp_guardband = 0;
+
+ if (assume_all_enabled ||
+ crtc_state->infoframes.enable &
+ intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
+ sdp_guardband = max(sdp_guardband,
+ intel_dp_get_lines_for_sdp(HDMI_PACKET_TYPE_GAMUT_METADATA));
+
+ if (assume_all_enabled ||
+ crtc_state->dsc.compression_enable)
+ sdp_guardband = max(sdp_guardband, intel_dp_get_lines_for_sdp(DP_SDP_PPS));
+
+ return sdp_guardband;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 281ced3a3b39..7ee5aeb28fe2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -221,5 +221,7 @@ bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
int intel_dp_compute_config_late(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
+int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
+ bool assume_all_enabled);
#endif /* __INTEL_DP_H__ */
--
2.45.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 3/5] drm/i915/dp: Check if guardband can accommodate sdp latencies
2025-10-17 5:01 [PATCH 0/5] Optimize vrr.guardband Ankit Nautiyal
2025-10-17 5:01 ` [PATCH 1/5] drm/i915/psr: Add helper to get min psr guardband Ankit Nautiyal
2025-10-17 5:01 ` [PATCH 2/5] drm/i915/dp: Add helper to get min sdp guardband Ankit Nautiyal
@ 2025-10-17 5:02 ` Ankit Nautiyal
2025-10-17 12:02 ` Ville Syrjälä
2025-10-17 5:02 ` [PATCH 4/5] drm/i915/vrr: Use the min static optimized guardband Ankit Nautiyal
` (5 subsequent siblings)
8 siblings, 1 reply; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-17 5:02 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal
Check if guardband is sufficient for all DP SDP latencies.
If its not, fail .compute_config_late().
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3f2c319e3d6f..8ae99cee79d4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -93,6 +93,7 @@
#include "intel_psr.h"
#include "intel_quirks.h"
#include "intel_tc.h"
+#include "intel_vblank.h"
#include "intel_vdsc.h"
#include "intel_vrr.h"
@@ -6980,14 +6981,35 @@ void intel_dp_mst_resume(struct intel_display *display)
}
}
+static
+int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ int guardband = intel_crtc_vblank_length(crtc_state);
+ int min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);
+
+ if (guardband < min_sdp_guardband) {
+ drm_dbg_kms(display->drm, "guardband %d < min sdp guardband %d\n",
+ guardband, min_sdp_guardband);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
int intel_dp_compute_config_late(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ int ret;
intel_psr_compute_config_late(intel_dp, crtc_state);
+ ret = intel_dp_sdp_compute_config_late(crtc_state);
+ if (ret)
+ return ret;
+
return 0;
}
--
2.45.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 4/5] drm/i915/vrr: Use the min static optimized guardband
2025-10-17 5:01 [PATCH 0/5] Optimize vrr.guardband Ankit Nautiyal
` (2 preceding siblings ...)
2025-10-17 5:02 ` [PATCH 3/5] drm/i915/dp: Check if guardband can accommodate sdp latencies Ankit Nautiyal
@ 2025-10-17 5:02 ` Ankit Nautiyal
2025-10-17 12:06 ` Ville Syrjälä
2025-10-17 5:02 ` [PATCH 5/5] drm/i915/vrr: Use optimized guardband whenever VRR TG is active Ankit Nautiyal
` (4 subsequent siblings)
8 siblings, 1 reply; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-17 5:02 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal
In the current VRR implementation, vrr.vmin and vrr.guardband are set such
that they do not need to change when switching from fixed refresh rate to
variable refresh rate. Specifically, vrr.guardband is always set to match
the vblank length. This approach works for most cases, but not for LRR,
where the guardband would need to change while the VRR timing generator is
still active.
With the VRR TG always active, live updates to guardband are unsafe and not
recommended. To ensure hardware safety, guardband was moved out of the
!fastset block, meaning any change now requires a full modeset.
This breaks seamless LRR switching, which was previously supported.
Since the problem arises from guardband being matched to the vblank length,
solution is to use a minimal, sufficient static value, instead. So we use a
static guardband defined during mode-set that fits within the smallest
expected vblank and remains unchanged in case of features like LRR where
vtotal changes. To compute this minimum guardband we take into account
latencies/delays due to different features as mentioned in the Bspec.
Introduce a helper to compute the minimal sufficient guardband.
On platforms where the VRR timing generator is always ON, we optimize the
guardband regardless of whether the display is operating in fixed or
variable refresh rate mode.
v2:
- Use max of sagv latency and skl_wm_latency(1) for PM delay
computation. (Ville)
- Avoid guardband optimization for HDMI for now. (Ville)
- Allow guardband optimization only for platforms with
intel_vrr_always_use_vrr_tg = true. (Ville)
- Add comments for PM delay and a #TODO note for HDMI.
Bspec: 70151
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 62 +++++++++++++++++++++++-
1 file changed, 60 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 597008a6c744..cd7bed358984 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -6,12 +6,16 @@
#include <drm/drm_print.h>
+#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
+#include "intel_psr.h"
#include "intel_vrr.h"
#include "intel_vrr_regs.h"
+#include "skl_prefill.h"
+#include "skl_watermark.h"
#define FIXED_POINT_PRECISION 100
#define CMRR_PRECISION_TOLERANCE 10
@@ -433,17 +437,71 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
intel_vrr_max_vblank_guardband(crtc_state));
}
+static
+int intel_vrr_compute_optimized_guardband(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct skl_prefill_ctx prefill_ctx;
+ int prefill_min_guardband;
+ int prefill_latency_us;
+ int guardband = 0;
+
+ skl_prefill_init_worst(&prefill_ctx, crtc_state);
+
+ /*
+ * The SoC power controller runs SAGV mutually exclusive with package C states,
+ * so the max of package C and SAGV latencies is used to compute the min prefill guardband.
+ * PM delay = max(sagv_latency, pkgc_max_latency (highest enabled wm level 1 and up))
+ */
+ prefill_latency_us = max(display->sagv.block_time_us,
+ skl_watermark_max_latency(display, 1));
+ prefill_min_guardband =
+ skl_prefill_min_guardband(&prefill_ctx,
+ crtc_state,
+ prefill_latency_us);
+
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
+ guardband = max(guardband, intel_psr_min_guardband(crtc_state));
+ guardband = max(guardband, intel_dp_sdp_min_guardband(crtc_state, true));
+ }
+
+ guardband = max(guardband, prefill_min_guardband);
+
+ return guardband;
+}
+
+static bool intel_vrr_use_optimized_guardband(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ /*
+ * #TODO: Enable optimized guardband for HDMI
+ * For HDMI lot of infoframes are transmitted a line or two after vsync.
+ * Since with optimized guardband the double bufferring point is at delayed vblank,
+ * we need to ensure that vsync happens after delayed vblank for the HDMI case.
+ */
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return false;
+
+ return intel_vrr_always_use_vrr_tg(display);
+}
+
void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
+ int guardband;
if (!intel_vrr_possible(crtc_state))
return;
- crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
- intel_vrr_max_guardband(crtc_state));
+ if (intel_vrr_use_optimized_guardband(crtc_state))
+ guardband = intel_vrr_compute_optimized_guardband(crtc_state);
+ else
+ guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;
+
+ crtc_state->vrr.guardband = min(guardband, intel_vrr_max_guardband(crtc_state));
if (intel_vrr_always_use_vrr_tg(display)) {
adjusted_mode->crtc_vblank_start =
--
2.45.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 5/5] drm/i915/vrr: Use optimized guardband whenever VRR TG is active
2025-10-17 5:01 [PATCH 0/5] Optimize vrr.guardband Ankit Nautiyal
` (3 preceding siblings ...)
2025-10-17 5:02 ` [PATCH 4/5] drm/i915/vrr: Use the min static optimized guardband Ankit Nautiyal
@ 2025-10-17 5:02 ` Ankit Nautiyal
2025-10-17 12:13 ` Ville Syrjälä
2025-10-17 5:23 ` ✓ CI.KUnit: success for Optimize vrr.guardband (rev3) Patchwork
` (3 subsequent siblings)
8 siblings, 1 reply; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-17 5:02 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal
Currently the guardband is optimized only for platforms where the
VRR timing generator is always ON.
Extend the usage of optimized guardband to other platforms only when the
VRR is enabled.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index cd7bed358984..eb5aa0d7fc49 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -483,7 +483,7 @@ static bool intel_vrr_use_optimized_guardband(const struct intel_crtc_state *crt
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
return false;
- return intel_vrr_always_use_vrr_tg(display);
+ return intel_vrr_always_use_vrr_tg(display) || crtc_state->vrr.enable;
}
void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
--
2.45.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* ✓ CI.KUnit: success for Optimize vrr.guardband (rev3)
2025-10-17 5:01 [PATCH 0/5] Optimize vrr.guardband Ankit Nautiyal
` (4 preceding siblings ...)
2025-10-17 5:02 ` [PATCH 5/5] drm/i915/vrr: Use optimized guardband whenever VRR TG is active Ankit Nautiyal
@ 2025-10-17 5:23 ` Patchwork
2025-10-17 5:38 ` ✗ CI.checksparse: warning " Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-10-17 5:23 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
== Series Details ==
Series: Optimize vrr.guardband (rev3)
URL : https://patchwork.freedesktop.org/series/155979/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[05:22:30] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:22:34] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:23:05] Starting KUnit Kernel (1/1)...
[05:23:05] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:23:05] ================== guc_buf (11 subtests) ===================
[05:23:05] [PASSED] test_smallest
[05:23:05] [PASSED] test_largest
[05:23:05] [PASSED] test_granular
[05:23:05] [PASSED] test_unique
[05:23:05] [PASSED] test_overlap
[05:23:05] [PASSED] test_reusable
[05:23:05] [PASSED] test_too_big
[05:23:05] [PASSED] test_flush
[05:23:05] [PASSED] test_lookup
[05:23:05] [PASSED] test_data
[05:23:05] [PASSED] test_class
[05:23:05] ===================== [PASSED] guc_buf =====================
[05:23:05] =================== guc_dbm (7 subtests) ===================
[05:23:05] [PASSED] test_empty
[05:23:05] [PASSED] test_default
[05:23:05] ======================== test_size ========================
[05:23:05] [PASSED] 4
[05:23:05] [PASSED] 8
[05:23:05] [PASSED] 32
[05:23:05] [PASSED] 256
[05:23:05] ==================== [PASSED] test_size ====================
[05:23:05] ======================= test_reuse ========================
[05:23:05] [PASSED] 4
[05:23:05] [PASSED] 8
[05:23:05] [PASSED] 32
[05:23:05] [PASSED] 256
[05:23:05] =================== [PASSED] test_reuse ====================
[05:23:05] =================== test_range_overlap ====================
[05:23:05] [PASSED] 4
[05:23:05] [PASSED] 8
[05:23:05] [PASSED] 32
[05:23:05] [PASSED] 256
[05:23:05] =============== [PASSED] test_range_overlap ================
[05:23:05] =================== test_range_compact ====================
[05:23:05] [PASSED] 4
[05:23:05] [PASSED] 8
[05:23:05] [PASSED] 32
[05:23:05] [PASSED] 256
[05:23:05] =============== [PASSED] test_range_compact ================
[05:23:05] ==================== test_range_spare =====================
[05:23:05] [PASSED] 4
[05:23:05] [PASSED] 8
[05:23:05] [PASSED] 32
[05:23:05] [PASSED] 256
[05:23:05] ================ [PASSED] test_range_spare =================
[05:23:05] ===================== [PASSED] guc_dbm =====================
[05:23:05] =================== guc_idm (6 subtests) ===================
[05:23:05] [PASSED] bad_init
[05:23:05] [PASSED] no_init
[05:23:05] [PASSED] init_fini
[05:23:05] [PASSED] check_used
[05:23:05] [PASSED] check_quota
[05:23:05] [PASSED] check_all
[05:23:05] ===================== [PASSED] guc_idm =====================
[05:23:05] ================== no_relay (3 subtests) ===================
[05:23:05] [PASSED] xe_drops_guc2pf_if_not_ready
[05:23:05] [PASSED] xe_drops_guc2vf_if_not_ready
[05:23:05] [PASSED] xe_rejects_send_if_not_ready
[05:23:05] ==================== [PASSED] no_relay =====================
[05:23:05] ================== pf_relay (14 subtests) ==================
[05:23:05] [PASSED] pf_rejects_guc2pf_too_short
[05:23:05] [PASSED] pf_rejects_guc2pf_too_long
[05:23:05] [PASSED] pf_rejects_guc2pf_no_payload
[05:23:05] [PASSED] pf_fails_no_payload
[05:23:05] [PASSED] pf_fails_bad_origin
[05:23:05] [PASSED] pf_fails_bad_type
[05:23:05] [PASSED] pf_txn_reports_error
[05:23:05] [PASSED] pf_txn_sends_pf2guc
[05:23:05] [PASSED] pf_sends_pf2guc
[05:23:05] [SKIPPED] pf_loopback_nop
[05:23:05] [SKIPPED] pf_loopback_echo
[05:23:05] [SKIPPED] pf_loopback_fail
[05:23:05] [SKIPPED] pf_loopback_busy
[05:23:05] [SKIPPED] pf_loopback_retry
[05:23:05] ==================== [PASSED] pf_relay =====================
[05:23:05] ================== vf_relay (3 subtests) ===================
[05:23:05] [PASSED] vf_rejects_guc2vf_too_short
[05:23:05] [PASSED] vf_rejects_guc2vf_too_long
[05:23:05] [PASSED] vf_rejects_guc2vf_no_payload
[05:23:05] ==================== [PASSED] vf_relay =====================
[05:23:05] ===================== lmtt (1 subtest) =====================
[05:23:05] ======================== test_ops =========================
[05:23:05] [PASSED] 2-level
[05:23:05] [PASSED] multi-level
[05:23:05] ==================== [PASSED] test_ops =====================
[05:23:05] ====================== [PASSED] lmtt =======================
[05:23:05] ================= pf_service (11 subtests) =================
[05:23:05] [PASSED] pf_negotiate_any
[05:23:05] [PASSED] pf_negotiate_base_match
[05:23:05] [PASSED] pf_negotiate_base_newer
[05:23:05] [PASSED] pf_negotiate_base_next
[05:23:05] [SKIPPED] pf_negotiate_base_older
[05:23:05] [PASSED] pf_negotiate_base_prev
[05:23:05] [PASSED] pf_negotiate_latest_match
[05:23:05] [PASSED] pf_negotiate_latest_newer
[05:23:05] [PASSED] pf_negotiate_latest_next
[05:23:05] [SKIPPED] pf_negotiate_latest_older
[05:23:05] [SKIPPED] pf_negotiate_latest_prev
[05:23:05] =================== [PASSED] pf_service ====================
[05:23:05] ================= xe_guc_g2g (2 subtests) ==================
[05:23:05] ============== xe_live_guc_g2g_kunit_default ==============
[05:23:05] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[05:23:05] ============== xe_live_guc_g2g_kunit_allmem ===============
[05:23:05] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[05:23:05] =================== [SKIPPED] xe_guc_g2g ===================
[05:23:05] =================== xe_mocs (2 subtests) ===================
[05:23:05] ================ xe_live_mocs_kernel_kunit ================
[05:23:05] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[05:23:05] ================ xe_live_mocs_reset_kunit =================
[05:23:05] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[05:23:05] ==================== [SKIPPED] xe_mocs =====================
[05:23:05] ================= xe_migrate (2 subtests) ==================
[05:23:05] ================= xe_migrate_sanity_kunit =================
[05:23:05] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[05:23:05] ================== xe_validate_ccs_kunit ==================
[05:23:05] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[05:23:05] =================== [SKIPPED] xe_migrate ===================
[05:23:05] ================== xe_dma_buf (1 subtest) ==================
[05:23:05] ==================== xe_dma_buf_kunit =====================
[05:23:05] ================ [SKIPPED] xe_dma_buf_kunit ================
[05:23:05] =================== [SKIPPED] xe_dma_buf ===================
[05:23:05] ================= xe_bo_shrink (1 subtest) =================
[05:23:05] =================== xe_bo_shrink_kunit ====================
[05:23:05] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[05:23:05] ================== [SKIPPED] xe_bo_shrink ==================
[05:23:05] ==================== xe_bo (2 subtests) ====================
[05:23:05] ================== xe_ccs_migrate_kunit ===================
[05:23:05] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[05:23:05] ==================== xe_bo_evict_kunit ====================
[05:23:05] =============== [SKIPPED] xe_bo_evict_kunit ================
[05:23:05] ===================== [SKIPPED] xe_bo ======================
[05:23:05] ==================== args (11 subtests) ====================
[05:23:05] [PASSED] count_args_test
[05:23:05] [PASSED] call_args_example
[05:23:05] [PASSED] call_args_test
[05:23:05] [PASSED] drop_first_arg_example
[05:23:05] [PASSED] drop_first_arg_test
[05:23:05] [PASSED] first_arg_example
[05:23:05] [PASSED] first_arg_test
[05:23:05] [PASSED] last_arg_example
[05:23:05] [PASSED] last_arg_test
[05:23:05] [PASSED] pick_arg_example
[05:23:05] [PASSED] sep_comma_example
[05:23:05] ====================== [PASSED] args =======================
[05:23:05] =================== xe_pci (3 subtests) ====================
[05:23:05] ==================== check_graphics_ip ====================
[05:23:05] [PASSED] 12.00 Xe_LP
[05:23:05] [PASSED] 12.10 Xe_LP+
[05:23:05] [PASSED] 12.55 Xe_HPG
[05:23:05] [PASSED] 12.60 Xe_HPC
[05:23:05] [PASSED] 12.70 Xe_LPG
[05:23:05] [PASSED] 12.71 Xe_LPG
[05:23:05] [PASSED] 12.74 Xe_LPG+
[05:23:05] [PASSED] 20.01 Xe2_HPG
[05:23:05] [PASSED] 20.02 Xe2_HPG
[05:23:05] [PASSED] 20.04 Xe2_LPG
[05:23:05] [PASSED] 30.00 Xe3_LPG
[05:23:05] [PASSED] 30.01 Xe3_LPG
[05:23:05] [PASSED] 30.03 Xe3_LPG
[05:23:05] ================ [PASSED] check_graphics_ip ================
[05:23:05] ===================== check_media_ip ======================
[05:23:05] [PASSED] 12.00 Xe_M
[05:23:05] [PASSED] 12.55 Xe_HPM
[05:23:05] [PASSED] 13.00 Xe_LPM+
[05:23:05] [PASSED] 13.01 Xe2_HPM
[05:23:05] [PASSED] 20.00 Xe2_LPM
[05:23:05] [PASSED] 30.00 Xe3_LPM
[05:23:05] [PASSED] 30.02 Xe3_LPM
[05:23:05] ================= [PASSED] check_media_ip ==================
[05:23:05] ================= check_platform_gt_count =================
[05:23:05] [PASSED] 0x9A60 (TIGERLAKE)
[05:23:05] [PASSED] 0x9A68 (TIGERLAKE)
[05:23:05] [PASSED] 0x9A70 (TIGERLAKE)
[05:23:05] [PASSED] 0x9A40 (TIGERLAKE)
[05:23:05] [PASSED] 0x9A49 (TIGERLAKE)
[05:23:05] [PASSED] 0x9A59 (TIGERLAKE)
[05:23:05] [PASSED] 0x9A78 (TIGERLAKE)
[05:23:05] [PASSED] 0x9AC0 (TIGERLAKE)
[05:23:05] [PASSED] 0x9AC9 (TIGERLAKE)
[05:23:05] [PASSED] 0x9AD9 (TIGERLAKE)
[05:23:05] [PASSED] 0x9AF8 (TIGERLAKE)
[05:23:05] [PASSED] 0x4C80 (ROCKETLAKE)
[05:23:05] [PASSED] 0x4C8A (ROCKETLAKE)
[05:23:05] [PASSED] 0x4C8B (ROCKETLAKE)
[05:23:05] [PASSED] 0x4C8C (ROCKETLAKE)
[05:23:05] [PASSED] 0x4C90 (ROCKETLAKE)
[05:23:05] [PASSED] 0x4C9A (ROCKETLAKE)
[05:23:05] [PASSED] 0x4680 (ALDERLAKE_S)
[05:23:05] [PASSED] 0x4682 (ALDERLAKE_S)
[05:23:05] [PASSED] 0x4688 (ALDERLAKE_S)
[05:23:05] [PASSED] 0x468A (ALDERLAKE_S)
[05:23:05] [PASSED] 0x468B (ALDERLAKE_S)
[05:23:05] [PASSED] 0x4690 (ALDERLAKE_S)
[05:23:05] [PASSED] 0x4692 (ALDERLAKE_S)
[05:23:05] [PASSED] 0x4693 (ALDERLAKE_S)
[05:23:05] [PASSED] 0x46A0 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x46A1 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x46A2 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x46A3 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x46A6 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x46A8 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x46AA (ALDERLAKE_P)
[05:23:05] [PASSED] 0x462A (ALDERLAKE_P)
[05:23:05] [PASSED] 0x4626 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x4628 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x46B0 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x46B1 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x46B2 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x46B3 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x46C0 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x46C1 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x46C2 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x46C3 (ALDERLAKE_P)
[05:23:05] [PASSED] 0x46D0 (ALDERLAKE_N)
[05:23:05] [PASSED] 0x46D1 (ALDERLAKE_N)
[05:23:05] [PASSED] 0x46D2 (ALDERLAKE_N)
[05:23:05] [PASSED] 0x46D3 (ALDERLAKE_N)
[05:23:05] [PASSED] 0x46D4 (ALDERLAKE_N)
[05:23:05] [PASSED] 0xA721 (ALDERLAKE_P)
[05:23:05] [PASSED] 0xA7A1 (ALDERLAKE_P)
[05:23:05] [PASSED] 0xA7A9 (ALDERLAKE_P)
[05:23:05] [PASSED] 0xA7AC (ALDERLAKE_P)
[05:23:05] [PASSED] 0xA7AD (ALDERLAKE_P)
[05:23:05] [PASSED] 0xA720 (ALDERLAKE_P)
[05:23:05] [PASSED] 0xA7A0 (ALDERLAKE_P)
[05:23:05] [PASSED] 0xA7A8 (ALDERLAKE_P)
[05:23:05] [PASSED] 0xA7AA (ALDERLAKE_P)
[05:23:05] [PASSED] 0xA7AB (ALDERLAKE_P)
[05:23:05] [PASSED] 0xA780 (ALDERLAKE_S)
[05:23:05] [PASSED] 0xA781 (ALDERLAKE_S)
[05:23:05] [PASSED] 0xA782 (ALDERLAKE_S)
[05:23:05] [PASSED] 0xA783 (ALDERLAKE_S)
[05:23:05] [PASSED] 0xA788 (ALDERLAKE_S)
[05:23:05] [PASSED] 0xA789 (ALDERLAKE_S)
[05:23:05] [PASSED] 0xA78A (ALDERLAKE_S)
[05:23:05] [PASSED] 0xA78B (ALDERLAKE_S)
[05:23:05] [PASSED] 0x4905 (DG1)
[05:23:05] [PASSED] 0x4906 (DG1)
[05:23:05] [PASSED] 0x4907 (DG1)
[05:23:05] [PASSED] 0x4908 (DG1)
[05:23:05] [PASSED] 0x4909 (DG1)
[05:23:05] [PASSED] 0x56C0 (DG2)
[05:23:05] [PASSED] 0x56C2 (DG2)
[05:23:05] [PASSED] 0x56C1 (DG2)
[05:23:05] [PASSED] 0x7D51 (METEORLAKE)
[05:23:05] [PASSED] 0x7DD1 (METEORLAKE)
[05:23:05] [PASSED] 0x7D41 (METEORLAKE)
[05:23:05] [PASSED] 0x7D67 (METEORLAKE)
[05:23:05] [PASSED] 0xB640 (METEORLAKE)
[05:23:05] [PASSED] 0x56A0 (DG2)
[05:23:05] [PASSED] 0x56A1 (DG2)
[05:23:05] [PASSED] 0x56A2 (DG2)
[05:23:05] [PASSED] 0x56BE (DG2)
[05:23:05] [PASSED] 0x56BF (DG2)
[05:23:05] [PASSED] 0x5690 (DG2)
[05:23:05] [PASSED] 0x5691 (DG2)
[05:23:05] [PASSED] 0x5692 (DG2)
[05:23:05] [PASSED] 0x56A5 (DG2)
[05:23:05] [PASSED] 0x56A6 (DG2)
[05:23:05] [PASSED] 0x56B0 (DG2)
[05:23:05] [PASSED] 0x56B1 (DG2)
[05:23:05] [PASSED] 0x56BA (DG2)
[05:23:05] [PASSED] 0x56BB (DG2)
[05:23:05] [PASSED] 0x56BC (DG2)
[05:23:05] [PASSED] 0x56BD (DG2)
[05:23:05] [PASSED] 0x5693 (DG2)
[05:23:05] [PASSED] 0x5694 (DG2)
[05:23:05] [PASSED] 0x5695 (DG2)
[05:23:05] [PASSED] 0x56A3 (DG2)
[05:23:05] [PASSED] 0x56A4 (DG2)
[05:23:05] [PASSED] 0x56B2 (DG2)
[05:23:05] [PASSED] 0x56B3 (DG2)
[05:23:05] [PASSED] 0x5696 (DG2)
[05:23:05] [PASSED] 0x5697 (DG2)
[05:23:05] [PASSED] 0xB69 (PVC)
[05:23:05] [PASSED] 0xB6E (PVC)
[05:23:05] [PASSED] 0xBD4 (PVC)
[05:23:05] [PASSED] 0xBD5 (PVC)
[05:23:05] [PASSED] 0xBD6 (PVC)
[05:23:05] [PASSED] 0xBD7 (PVC)
[05:23:05] [PASSED] 0xBD8 (PVC)
[05:23:05] [PASSED] 0xBD9 (PVC)
[05:23:05] [PASSED] 0xBDA (PVC)
[05:23:05] [PASSED] 0xBDB (PVC)
[05:23:05] [PASSED] 0xBE0 (PVC)
[05:23:05] [PASSED] 0xBE1 (PVC)
[05:23:05] [PASSED] 0xBE5 (PVC)
[05:23:05] [PASSED] 0x7D40 (METEORLAKE)
[05:23:05] [PASSED] 0x7D45 (METEORLAKE)
[05:23:05] [PASSED] 0x7D55 (METEORLAKE)
[05:23:05] [PASSED] 0x7D60 (METEORLAKE)
[05:23:05] [PASSED] 0x7DD5 (METEORLAKE)
[05:23:05] [PASSED] 0x6420 (LUNARLAKE)
[05:23:05] [PASSED] 0x64A0 (LUNARLAKE)
[05:23:05] [PASSED] 0x64B0 (LUNARLAKE)
[05:23:05] [PASSED] 0xE202 (BATTLEMAGE)
[05:23:05] [PASSED] 0xE209 (BATTLEMAGE)
[05:23:05] [PASSED] 0xE20B (BATTLEMAGE)
[05:23:05] [PASSED] 0xE20C (BATTLEMAGE)
[05:23:05] [PASSED] 0xE20D (BATTLEMAGE)
[05:23:05] [PASSED] 0xE210 (BATTLEMAGE)
[05:23:05] [PASSED] 0xE211 (BATTLEMAGE)
[05:23:05] [PASSED] 0xE212 (BATTLEMAGE)
[05:23:05] [PASSED] 0xE216 (BATTLEMAGE)
[05:23:05] [PASSED] 0xE220 (BATTLEMAGE)
[05:23:05] [PASSED] 0xE221 (BATTLEMAGE)
[05:23:05] [PASSED] 0xE222 (BATTLEMAGE)
[05:23:05] [PASSED] 0xE223 (BATTLEMAGE)
[05:23:05] [PASSED] 0xB080 (PANTHERLAKE)
[05:23:05] [PASSED] 0xB081 (PANTHERLAKE)
[05:23:05] [PASSED] 0xB082 (PANTHERLAKE)
[05:23:05] [PASSED] 0xB083 (PANTHERLAKE)
[05:23:05] [PASSED] 0xB084 (PANTHERLAKE)
[05:23:05] [PASSED] 0xB085 (PANTHERLAKE)
[05:23:05] [PASSED] 0xB086 (PANTHERLAKE)
[05:23:05] [PASSED] 0xB087 (PANTHERLAKE)
[05:23:05] [PASSED] 0xB08F (PANTHERLAKE)
[05:23:05] [PASSED] 0xB090 (PANTHERLAKE)
[05:23:05] [PASSED] 0xB0A0 (PANTHERLAKE)
[05:23:05] [PASSED] 0xB0B0 (PANTHERLAKE)
[05:23:05] [PASSED] 0xFD80 (PANTHERLAKE)
[05:23:05] [PASSED] 0xFD81 (PANTHERLAKE)
[05:23:05] ============= [PASSED] check_platform_gt_count =============
[05:23:05] ===================== [PASSED] xe_pci ======================
[05:23:05] =================== xe_rtp (2 subtests) ====================
[05:23:05] =============== xe_rtp_process_to_sr_tests ================
[05:23:05] [PASSED] coalesce-same-reg
[05:23:05] [PASSED] no-match-no-add
[05:23:05] [PASSED] match-or
[05:23:05] [PASSED] match-or-xfail
[05:23:05] [PASSED] no-match-no-add-multiple-rules
[05:23:05] [PASSED] two-regs-two-entries
[05:23:05] [PASSED] clr-one-set-other
[05:23:05] [PASSED] set-field
[05:23:05] [PASSED] conflict-duplicate
[05:23:05] [PASSED] conflict-not-disjoint
[05:23:05] [PASSED] conflict-reg-type
[05:23:05] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[05:23:05] ================== xe_rtp_process_tests ===================
[05:23:05] [PASSED] active1
[05:23:05] [PASSED] active2
[05:23:05] [PASSED] active-inactive
[05:23:05] [PASSED] inactive-active
[05:23:05] [PASSED] inactive-1st_or_active-inactive
[05:23:05] [PASSED] inactive-2nd_or_active-inactive
[05:23:05] [PASSED] inactive-last_or_active-inactive
[05:23:05] [PASSED] inactive-no_or_active-inactive
[05:23:05] ============== [PASSED] xe_rtp_process_tests ===============
[05:23:05] ===================== [PASSED] xe_rtp ======================
[05:23:05] ==================== xe_wa (1 subtest) =====================
[05:23:05] ======================== xe_wa_gt =========================
[05:23:05] [PASSED] TIGERLAKE B0
[05:23:05] [PASSED] DG1 A0
[05:23:05] [PASSED] DG1 B0
[05:23:05] [PASSED] ALDERLAKE_S A0
[05:23:05] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[05:23:05] [PASSED] ALDERLAKE_S C0
[05:23:05] [PASSED] ALDERLAKE_S D0
[05:23:05] [PASSED] ALDERLAKE_P A0
[05:23:05] [PASSED] ALDERLAKE_P B0
[05:23:05] [PASSED] ALDERLAKE_P C0
[05:23:05] [PASSED] ALDERLAKE_S RPLS D0
[05:23:05] [PASSED] ALDERLAKE_P RPLU E0
[05:23:05] [PASSED] DG2 G10 C0
[05:23:05] [PASSED] DG2 G11 B1
[05:23:05] [PASSED] DG2 G12 A1
[05:23:05] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:23:05] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:23:05] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[05:23:05] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[05:23:05] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[05:23:05] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[05:23:05] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[05:23:05] ==================== [PASSED] xe_wa_gt =====================
[05:23:05] ====================== [PASSED] xe_wa ======================
[05:23:05] ============================================================
[05:23:05] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[05:23:05] Elapsed time: 35.134s total, 4.228s configuring, 30.541s building, 0.327s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[05:23:05] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:23:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:23:32] Starting KUnit Kernel (1/1)...
[05:23:32] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:23:32] ============ drm_test_pick_cmdline (2 subtests) ============
[05:23:32] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[05:23:32] =============== drm_test_pick_cmdline_named ===============
[05:23:32] [PASSED] NTSC
[05:23:32] [PASSED] NTSC-J
[05:23:32] [PASSED] PAL
[05:23:32] [PASSED] PAL-M
[05:23:32] =========== [PASSED] drm_test_pick_cmdline_named ===========
[05:23:32] ============== [PASSED] drm_test_pick_cmdline ==============
[05:23:32] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[05:23:32] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[05:23:32] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[05:23:32] =========== drm_validate_clone_mode (2 subtests) ===========
[05:23:32] ============== drm_test_check_in_clone_mode ===============
[05:23:32] [PASSED] in_clone_mode
[05:23:32] [PASSED] not_in_clone_mode
[05:23:32] ========== [PASSED] drm_test_check_in_clone_mode ===========
[05:23:32] =============== drm_test_check_valid_clones ===============
[05:23:32] [PASSED] not_in_clone_mode
[05:23:32] [PASSED] valid_clone
[05:23:32] [PASSED] invalid_clone
[05:23:32] =========== [PASSED] drm_test_check_valid_clones ===========
[05:23:32] ============= [PASSED] drm_validate_clone_mode =============
[05:23:32] ============= drm_validate_modeset (1 subtest) =============
[05:23:32] [PASSED] drm_test_check_connector_changed_modeset
[05:23:32] ============== [PASSED] drm_validate_modeset ===============
[05:23:32] ====== drm_test_bridge_get_current_state (2 subtests) ======
[05:23:32] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[05:23:32] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[05:23:32] ======== [PASSED] drm_test_bridge_get_current_state ========
[05:23:32] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[05:23:32] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[05:23:32] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[05:23:32] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[05:23:32] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[05:23:32] ============== drm_bridge_alloc (2 subtests) ===============
[05:23:32] [PASSED] drm_test_drm_bridge_alloc_basic
[05:23:32] [PASSED] drm_test_drm_bridge_alloc_get_put
[05:23:32] ================ [PASSED] drm_bridge_alloc =================
[05:23:32] ================== drm_buddy (8 subtests) ==================
[05:23:32] [PASSED] drm_test_buddy_alloc_limit
[05:23:32] [PASSED] drm_test_buddy_alloc_optimistic
[05:23:32] [PASSED] drm_test_buddy_alloc_pessimistic
[05:23:32] [PASSED] drm_test_buddy_alloc_pathological
[05:23:32] [PASSED] drm_test_buddy_alloc_contiguous
[05:23:32] [PASSED] drm_test_buddy_alloc_clear
[05:23:32] [PASSED] drm_test_buddy_alloc_range_bias
[05:23:32] [PASSED] drm_test_buddy_fragmentation_performance
[05:23:32] ==================== [PASSED] drm_buddy ====================
[05:23:32] ============= drm_cmdline_parser (40 subtests) =============
[05:23:32] [PASSED] drm_test_cmdline_force_d_only
[05:23:32] [PASSED] drm_test_cmdline_force_D_only_dvi
[05:23:32] [PASSED] drm_test_cmdline_force_D_only_hdmi
[05:23:32] [PASSED] drm_test_cmdline_force_D_only_not_digital
[05:23:32] [PASSED] drm_test_cmdline_force_e_only
[05:23:32] [PASSED] drm_test_cmdline_res
[05:23:32] [PASSED] drm_test_cmdline_res_vesa
[05:23:32] [PASSED] drm_test_cmdline_res_vesa_rblank
[05:23:32] [PASSED] drm_test_cmdline_res_rblank
[05:23:32] [PASSED] drm_test_cmdline_res_bpp
[05:23:32] [PASSED] drm_test_cmdline_res_refresh
[05:23:32] [PASSED] drm_test_cmdline_res_bpp_refresh
[05:23:32] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[05:23:32] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[05:23:32] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[05:23:32] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[05:23:32] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[05:23:32] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[05:23:32] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[05:23:32] [PASSED] drm_test_cmdline_res_margins_force_on
[05:23:32] [PASSED] drm_test_cmdline_res_vesa_margins
[05:23:32] [PASSED] drm_test_cmdline_name
[05:23:32] [PASSED] drm_test_cmdline_name_bpp
[05:23:32] [PASSED] drm_test_cmdline_name_option
[05:23:32] [PASSED] drm_test_cmdline_name_bpp_option
[05:23:32] [PASSED] drm_test_cmdline_rotate_0
[05:23:32] [PASSED] drm_test_cmdline_rotate_90
[05:23:32] [PASSED] drm_test_cmdline_rotate_180
[05:23:32] [PASSED] drm_test_cmdline_rotate_270
[05:23:32] [PASSED] drm_test_cmdline_hmirror
[05:23:32] [PASSED] drm_test_cmdline_vmirror
[05:23:32] [PASSED] drm_test_cmdline_margin_options
[05:23:32] [PASSED] drm_test_cmdline_multiple_options
[05:23:32] [PASSED] drm_test_cmdline_bpp_extra_and_option
[05:23:32] [PASSED] drm_test_cmdline_extra_and_option
[05:23:32] [PASSED] drm_test_cmdline_freestanding_options
[05:23:32] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[05:23:32] [PASSED] drm_test_cmdline_panel_orientation
[05:23:32] ================ drm_test_cmdline_invalid =================
[05:23:32] [PASSED] margin_only
[05:23:32] [PASSED] interlace_only
[05:23:32] [PASSED] res_missing_x
[05:23:32] [PASSED] res_missing_y
[05:23:32] [PASSED] res_bad_y
[05:23:32] [PASSED] res_missing_y_bpp
[05:23:32] [PASSED] res_bad_bpp
[05:23:32] [PASSED] res_bad_refresh
[05:23:32] [PASSED] res_bpp_refresh_force_on_off
[05:23:32] [PASSED] res_invalid_mode
[05:23:32] [PASSED] res_bpp_wrong_place_mode
[05:23:32] [PASSED] name_bpp_refresh
[05:23:32] [PASSED] name_refresh
[05:23:32] [PASSED] name_refresh_wrong_mode
[05:23:32] [PASSED] name_refresh_invalid_mode
[05:23:32] [PASSED] rotate_multiple
[05:23:32] [PASSED] rotate_invalid_val
[05:23:32] [PASSED] rotate_truncated
[05:23:32] [PASSED] invalid_option
[05:23:32] [PASSED] invalid_tv_option
[05:23:32] [PASSED] truncated_tv_option
[05:23:32] ============ [PASSED] drm_test_cmdline_invalid =============
[05:23:32] =============== drm_test_cmdline_tv_options ===============
[05:23:32] [PASSED] NTSC
[05:23:32] [PASSED] NTSC_443
[05:23:32] [PASSED] NTSC_J
[05:23:32] [PASSED] PAL
[05:23:32] [PASSED] PAL_M
[05:23:32] [PASSED] PAL_N
[05:23:32] [PASSED] SECAM
[05:23:32] [PASSED] MONO_525
[05:23:32] [PASSED] MONO_625
[05:23:32] =========== [PASSED] drm_test_cmdline_tv_options ===========
[05:23:32] =============== [PASSED] drm_cmdline_parser ================
[05:23:32] ========== drmm_connector_hdmi_init (20 subtests) ==========
[05:23:32] [PASSED] drm_test_connector_hdmi_init_valid
[05:23:32] [PASSED] drm_test_connector_hdmi_init_bpc_8
[05:23:32] [PASSED] drm_test_connector_hdmi_init_bpc_10
[05:23:32] [PASSED] drm_test_connector_hdmi_init_bpc_12
[05:23:32] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[05:23:32] [PASSED] drm_test_connector_hdmi_init_bpc_null
[05:23:32] [PASSED] drm_test_connector_hdmi_init_formats_empty
[05:23:32] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[05:23:32] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[05:23:32] [PASSED] supported_formats=0x9 yuv420_allowed=1
[05:23:32] [PASSED] supported_formats=0x9 yuv420_allowed=0
[05:23:32] [PASSED] supported_formats=0x3 yuv420_allowed=1
[05:23:32] [PASSED] supported_formats=0x3 yuv420_allowed=0
[05:23:32] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[05:23:32] [PASSED] drm_test_connector_hdmi_init_null_ddc
[05:23:32] [PASSED] drm_test_connector_hdmi_init_null_product
[05:23:32] [PASSED] drm_test_connector_hdmi_init_null_vendor
[05:23:32] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[05:23:32] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[05:23:32] [PASSED] drm_test_connector_hdmi_init_product_valid
[05:23:32] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[05:23:32] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[05:23:32] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[05:23:32] ========= drm_test_connector_hdmi_init_type_valid =========
[05:23:32] [PASSED] HDMI-A
[05:23:32] [PASSED] HDMI-B
[05:23:32] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[05:23:32] ======== drm_test_connector_hdmi_init_type_invalid ========
[05:23:32] [PASSED] Unknown
[05:23:32] [PASSED] VGA
[05:23:32] [PASSED] DVI-I
[05:23:32] [PASSED] DVI-D
[05:23:32] [PASSED] DVI-A
[05:23:32] [PASSED] Composite
[05:23:32] [PASSED] SVIDEO
[05:23:32] [PASSED] LVDS
[05:23:32] [PASSED] Component
[05:23:32] [PASSED] DIN
[05:23:32] [PASSED] DP
[05:23:32] [PASSED] TV
[05:23:32] [PASSED] eDP
[05:23:32] [PASSED] Virtual
[05:23:32] [PASSED] DSI
[05:23:32] [PASSED] DPI
[05:23:32] [PASSED] Writeback
[05:23:32] [PASSED] SPI
[05:23:32] [PASSED] USB
[05:23:32] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[05:23:32] ============ [PASSED] drmm_connector_hdmi_init =============
[05:23:32] ============= drmm_connector_init (3 subtests) =============
[05:23:32] [PASSED] drm_test_drmm_connector_init
[05:23:32] [PASSED] drm_test_drmm_connector_init_null_ddc
[05:23:32] ========= drm_test_drmm_connector_init_type_valid =========
[05:23:32] [PASSED] Unknown
[05:23:32] [PASSED] VGA
[05:23:32] [PASSED] DVI-I
[05:23:32] [PASSED] DVI-D
[05:23:32] [PASSED] DVI-A
[05:23:32] [PASSED] Composite
[05:23:32] [PASSED] SVIDEO
[05:23:32] [PASSED] LVDS
[05:23:32] [PASSED] Component
[05:23:32] [PASSED] DIN
[05:23:32] [PASSED] DP
[05:23:32] [PASSED] HDMI-A
[05:23:32] [PASSED] HDMI-B
[05:23:32] [PASSED] TV
[05:23:32] [PASSED] eDP
[05:23:32] [PASSED] Virtual
[05:23:32] [PASSED] DSI
[05:23:32] [PASSED] DPI
[05:23:32] [PASSED] Writeback
[05:23:32] [PASSED] SPI
[05:23:32] [PASSED] USB
[05:23:32] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[05:23:32] =============== [PASSED] drmm_connector_init ===============
[05:23:32] ========= drm_connector_dynamic_init (6 subtests) ==========
[05:23:32] [PASSED] drm_test_drm_connector_dynamic_init
[05:23:32] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[05:23:32] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[05:23:32] [PASSED] drm_test_drm_connector_dynamic_init_properties
[05:23:32] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[05:23:32] [PASSED] Unknown
[05:23:32] [PASSED] VGA
[05:23:32] [PASSED] DVI-I
[05:23:32] [PASSED] DVI-D
[05:23:32] [PASSED] DVI-A
[05:23:32] [PASSED] Composite
[05:23:32] [PASSED] SVIDEO
[05:23:32] [PASSED] LVDS
[05:23:32] [PASSED] Component
[05:23:32] [PASSED] DIN
[05:23:32] [PASSED] DP
[05:23:32] [PASSED] HDMI-A
[05:23:32] [PASSED] HDMI-B
[05:23:32] [PASSED] TV
[05:23:32] [PASSED] eDP
[05:23:32] [PASSED] Virtual
[05:23:32] [PASSED] DSI
[05:23:32] [PASSED] DPI
[05:23:32] [PASSED] Writeback
[05:23:32] [PASSED] SPI
[05:23:32] [PASSED] USB
[05:23:32] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[05:23:32] ======== drm_test_drm_connector_dynamic_init_name =========
[05:23:32] [PASSED] Unknown
[05:23:32] [PASSED] VGA
[05:23:32] [PASSED] DVI-I
[05:23:32] [PASSED] DVI-D
[05:23:32] [PASSED] DVI-A
[05:23:32] [PASSED] Composite
[05:23:32] [PASSED] SVIDEO
[05:23:32] [PASSED] LVDS
[05:23:32] [PASSED] Component
[05:23:32] [PASSED] DIN
[05:23:32] [PASSED] DP
[05:23:32] [PASSED] HDMI-A
[05:23:32] [PASSED] HDMI-B
[05:23:32] [PASSED] TV
[05:23:32] [PASSED] eDP
[05:23:32] [PASSED] Virtual
[05:23:32] [PASSED] DSI
[05:23:32] [PASSED] DPI
[05:23:32] [PASSED] Writeback
[05:23:32] [PASSED] SPI
[05:23:32] [PASSED] USB
[05:23:32] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[05:23:32] =========== [PASSED] drm_connector_dynamic_init ============
[05:23:32] ==== drm_connector_dynamic_register_early (4 subtests) =====
[05:23:32] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[05:23:32] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[05:23:32] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[05:23:32] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[05:23:32] ====== [PASSED] drm_connector_dynamic_register_early =======
[05:23:32] ======= drm_connector_dynamic_register (7 subtests) ========
[05:23:32] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[05:23:32] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[05:23:32] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[05:23:32] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[05:23:32] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[05:23:32] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[05:23:32] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[05:23:32] ========= [PASSED] drm_connector_dynamic_register ==========
[05:23:32] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[05:23:32] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[05:23:32] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[05:23:32] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[05:23:32] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[05:23:32] ========== drm_test_get_tv_mode_from_name_valid ===========
[05:23:32] [PASSED] NTSC
[05:23:32] [PASSED] NTSC-443
[05:23:32] [PASSED] NTSC-J
[05:23:32] [PASSED] PAL
[05:23:32] [PASSED] PAL-M
[05:23:32] [PASSED] PAL-N
[05:23:32] [PASSED] SECAM
[05:23:32] [PASSED] Mono
[05:23:32] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[05:23:32] [PASSED] drm_test_get_tv_mode_from_name_truncated
[05:23:32] ============ [PASSED] drm_get_tv_mode_from_name ============
[05:23:32] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[05:23:32] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[05:23:32] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[05:23:32] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[05:23:32] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[05:23:32] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[05:23:32] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[05:23:32] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[05:23:32] [PASSED] VIC 96
[05:23:32] [PASSED] VIC 97
[05:23:32] [PASSED] VIC 101
[05:23:32] [PASSED] VIC 102
[05:23:32] [PASSED] VIC 106
[05:23:32] [PASSED] VIC 107
[05:23:32] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[05:23:32] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[05:23:32] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[05:23:32] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[05:23:32] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[05:23:32] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[05:23:32] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[05:23:32] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[05:23:32] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[05:23:32] [PASSED] Automatic
[05:23:32] [PASSED] Full
[05:23:32] [PASSED] Limited 16:235
[05:23:32] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[05:23:32] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[05:23:32] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[05:23:32] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[05:23:32] === drm_test_drm_hdmi_connector_get_output_format_name ====
[05:23:32] [PASSED] RGB
[05:23:32] [PASSED] YUV 4:2:0
[05:23:32] [PASSED] YUV 4:2:2
[05:23:32] [PASSED] YUV 4:4:4
[05:23:32] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[05:23:32] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[05:23:32] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[05:23:32] ============= drm_damage_helper (21 subtests) ==============
[05:23:32] [PASSED] drm_test_damage_iter_no_damage
[05:23:32] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[05:23:32] [PASSED] drm_test_damage_iter_no_damage_src_moved
[05:23:32] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[05:23:32] [PASSED] drm_test_damage_iter_no_damage_not_visible
[05:23:32] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[05:23:32] [PASSED] drm_test_damage_iter_no_damage_no_fb
[05:23:32] [PASSED] drm_test_damage_iter_simple_damage
[05:23:32] [PASSED] drm_test_damage_iter_single_damage
[05:23:32] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[05:23:32] [PASSED] drm_test_damage_iter_single_damage_outside_src
[05:23:32] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[05:23:32] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[05:23:32] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[05:23:32] [PASSED] drm_test_damage_iter_single_damage_src_moved
[05:23:32] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[05:23:32] [PASSED] drm_test_damage_iter_damage
[05:23:32] [PASSED] drm_test_damage_iter_damage_one_intersect
[05:23:32] [PASSED] drm_test_damage_iter_damage_one_outside
[05:23:32] [PASSED] drm_test_damage_iter_damage_src_moved
[05:23:32] [PASSED] drm_test_damage_iter_damage_not_visible
[05:23:32] ================ [PASSED] drm_damage_helper ================
[05:23:32] ============== drm_dp_mst_helper (3 subtests) ==============
[05:23:32] ============== drm_test_dp_mst_calc_pbn_mode ==============
[05:23:32] [PASSED] Clock 154000 BPP 30 DSC disabled
[05:23:32] [PASSED] Clock 234000 BPP 30 DSC disabled
[05:23:32] [PASSED] Clock 297000 BPP 24 DSC disabled
[05:23:32] [PASSED] Clock 332880 BPP 24 DSC enabled
[05:23:32] [PASSED] Clock 324540 BPP 24 DSC enabled
[05:23:32] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[05:23:32] ============== drm_test_dp_mst_calc_pbn_div ===============
[05:23:32] [PASSED] Link rate 2000000 lane count 4
[05:23:32] [PASSED] Link rate 2000000 lane count 2
[05:23:32] [PASSED] Link rate 2000000 lane count 1
[05:23:32] [PASSED] Link rate 1350000 lane count 4
[05:23:32] [PASSED] Link rate 1350000 lane count 2
[05:23:32] [PASSED] Link rate 1350000 lane count 1
[05:23:32] [PASSED] Link rate 1000000 lane count 4
[05:23:32] [PASSED] Link rate 1000000 lane count 2
[05:23:32] [PASSED] Link rate 1000000 lane count 1
[05:23:32] [PASSED] Link rate 810000 lane count 4
[05:23:32] [PASSED] Link rate 810000 lane count 2
[05:23:32] [PASSED] Link rate 810000 lane count 1
[05:23:32] [PASSED] Link rate 540000 lane count 4
[05:23:32] [PASSED] Link rate 540000 lane count 2
[05:23:32] [PASSED] Link rate 540000 lane count 1
[05:23:32] [PASSED] Link rate 270000 lane count 4
[05:23:32] [PASSED] Link rate 270000 lane count 2
[05:23:32] [PASSED] Link rate 270000 lane count 1
[05:23:32] [PASSED] Link rate 162000 lane count 4
[05:23:32] [PASSED] Link rate 162000 lane count 2
[05:23:32] [PASSED] Link rate 162000 lane count 1
[05:23:32] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[05:23:32] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[05:23:32] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[05:23:32] [PASSED] DP_POWER_UP_PHY with port number
[05:23:32] [PASSED] DP_POWER_DOWN_PHY with port number
[05:23:32] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[05:23:32] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[05:23:32] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[05:23:32] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[05:23:32] [PASSED] DP_QUERY_PAYLOAD with port number
[05:23:32] [PASSED] DP_QUERY_PAYLOAD with VCPI
[05:23:32] [PASSED] DP_REMOTE_DPCD_READ with port number
[05:23:32] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[05:23:32] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[05:23:32] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[05:23:32] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[05:23:32] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[05:23:32] [PASSED] DP_REMOTE_I2C_READ with port number
[05:23:32] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[05:23:32] [PASSED] DP_REMOTE_I2C_READ with transactions array
[05:23:32] [PASSED] DP_REMOTE_I2C_WRITE with port number
[05:23:32] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[05:23:32] [PASSED] DP_REMOTE_I2C_WRITE with data array
[05:23:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[05:23:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[05:23:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[05:23:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[05:23:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[05:23:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[05:23:32] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[05:23:32] ================ [PASSED] drm_dp_mst_helper ================
[05:23:32] ================== drm_exec (7 subtests) ===================
[05:23:32] [PASSED] sanitycheck
[05:23:32] [PASSED] test_lock
[05:23:32] [PASSED] test_lock_unlock
[05:23:32] [PASSED] test_duplicates
[05:23:32] [PASSED] test_prepare
[05:23:32] [PASSED] test_prepare_array
[05:23:32] [PASSED] test_multiple_loops
[05:23:32] ==================== [PASSED] drm_exec =====================
[05:23:32] =========== drm_format_helper_test (17 subtests) ===========
[05:23:32] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[05:23:32] [PASSED] single_pixel_source_buffer
[05:23:32] [PASSED] single_pixel_clip_rectangle
[05:23:32] [PASSED] well_known_colors
[05:23:32] [PASSED] destination_pitch
[05:23:32] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[05:23:32] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[05:23:32] [PASSED] single_pixel_source_buffer
[05:23:32] [PASSED] single_pixel_clip_rectangle
[05:23:32] [PASSED] well_known_colors
[05:23:32] [PASSED] destination_pitch
[05:23:32] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[05:23:32] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[05:23:32] [PASSED] single_pixel_source_buffer
[05:23:32] [PASSED] single_pixel_clip_rectangle
[05:23:32] [PASSED] well_known_colors
[05:23:32] [PASSED] destination_pitch
[05:23:32] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[05:23:32] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[05:23:32] [PASSED] single_pixel_source_buffer
[05:23:32] [PASSED] single_pixel_clip_rectangle
[05:23:32] [PASSED] well_known_colors
[05:23:32] [PASSED] destination_pitch
[05:23:32] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[05:23:32] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[05:23:32] [PASSED] single_pixel_source_buffer
[05:23:32] [PASSED] single_pixel_clip_rectangle
[05:23:32] [PASSED] well_known_colors
[05:23:32] [PASSED] destination_pitch
[05:23:32] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[05:23:32] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[05:23:32] [PASSED] single_pixel_source_buffer
[05:23:32] [PASSED] single_pixel_clip_rectangle
[05:23:32] [PASSED] well_known_colors
[05:23:32] [PASSED] destination_pitch
[05:23:32] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[05:23:32] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[05:23:32] [PASSED] single_pixel_source_buffer
[05:23:32] [PASSED] single_pixel_clip_rectangle
[05:23:32] [PASSED] well_known_colors
[05:23:32] [PASSED] destination_pitch
[05:23:32] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[05:23:32] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[05:23:32] [PASSED] single_pixel_source_buffer
[05:23:32] [PASSED] single_pixel_clip_rectangle
[05:23:32] [PASSED] well_known_colors
[05:23:32] [PASSED] destination_pitch
[05:23:32] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[05:23:32] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[05:23:32] [PASSED] single_pixel_source_buffer
[05:23:32] [PASSED] single_pixel_clip_rectangle
[05:23:32] [PASSED] well_known_colors
[05:23:32] [PASSED] destination_pitch
[05:23:32] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[05:23:32] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[05:23:32] [PASSED] single_pixel_source_buffer
[05:23:32] [PASSED] single_pixel_clip_rectangle
[05:23:32] [PASSED] well_known_colors
[05:23:32] [PASSED] destination_pitch
[05:23:32] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[05:23:32] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[05:23:32] [PASSED] single_pixel_source_buffer
[05:23:32] [PASSED] single_pixel_clip_rectangle
[05:23:32] [PASSED] well_known_colors
[05:23:32] [PASSED] destination_pitch
[05:23:32] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[05:23:32] ============== drm_test_fb_xrgb8888_to_mono ===============
[05:23:32] [PASSED] single_pixel_source_buffer
[05:23:32] [PASSED] single_pixel_clip_rectangle
[05:23:32] [PASSED] well_known_colors
[05:23:32] [PASSED] destination_pitch
[05:23:32] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[05:23:32] ==================== drm_test_fb_swab =====================
[05:23:32] [PASSED] single_pixel_source_buffer
[05:23:32] [PASSED] single_pixel_clip_rectangle
[05:23:32] [PASSED] well_known_colors
[05:23:32] [PASSED] destination_pitch
[05:23:32] ================ [PASSED] drm_test_fb_swab =================
[05:23:32] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[05:23:32] [PASSED] single_pixel_source_buffer
[05:23:32] [PASSED] single_pixel_clip_rectangle
[05:23:32] [PASSED] well_known_colors
[05:23:32] [PASSED] destination_pitch
[05:23:32] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[05:23:32] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[05:23:32] [PASSED] single_pixel_source_buffer
[05:23:32] [PASSED] single_pixel_clip_rectangle
[05:23:32] [PASSED] well_known_colors
[05:23:32] [PASSED] destination_pitch
[05:23:32] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[05:23:32] ================= drm_test_fb_clip_offset =================
[05:23:32] [PASSED] pass through
[05:23:32] [PASSED] horizontal offset
[05:23:32] [PASSED] vertical offset
[05:23:32] [PASSED] horizontal and vertical offset
[05:23:32] [PASSED] horizontal offset (custom pitch)
[05:23:32] [PASSED] vertical offset (custom pitch)
[05:23:32] [PASSED] horizontal and vertical offset (custom pitch)
[05:23:32] ============= [PASSED] drm_test_fb_clip_offset =============
[05:23:32] =================== drm_test_fb_memcpy ====================
[05:23:32] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[05:23:32] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[05:23:32] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[05:23:32] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[05:23:32] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[05:23:32] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[05:23:32] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[05:23:32] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[05:23:32] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[05:23:32] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[05:23:32] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[05:23:32] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[05:23:32] =============== [PASSED] drm_test_fb_memcpy ================
[05:23:32] ============= [PASSED] drm_format_helper_test ==============
[05:23:32] ================= drm_format (18 subtests) =================
[05:23:32] [PASSED] drm_test_format_block_width_invalid
[05:23:32] [PASSED] drm_test_format_block_width_one_plane
[05:23:32] [PASSED] drm_test_format_block_width_two_plane
[05:23:32] [PASSED] drm_test_format_block_width_three_plane
[05:23:32] [PASSED] drm_test_format_block_width_tiled
[05:23:32] [PASSED] drm_test_format_block_height_invalid
[05:23:32] [PASSED] drm_test_format_block_height_one_plane
[05:23:32] [PASSED] drm_test_format_block_height_two_plane
[05:23:32] [PASSED] drm_test_format_block_height_three_plane
[05:23:32] [PASSED] drm_test_format_block_height_tiled
[05:23:32] [PASSED] drm_test_format_min_pitch_invalid
[05:23:32] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[05:23:32] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[05:23:32] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[05:23:32] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[05:23:32] [PASSED] drm_test_format_min_pitch_two_plane
[05:23:32] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[05:23:32] [PASSED] drm_test_format_min_pitch_tiled
[05:23:32] =================== [PASSED] drm_format ====================
[05:23:32] ============== drm_framebuffer (10 subtests) ===============
[05:23:32] ========== drm_test_framebuffer_check_src_coords ==========
[05:23:32] [PASSED] Success: source fits into fb
[05:23:32] [PASSED] Fail: overflowing fb with x-axis coordinate
[05:23:32] [PASSED] Fail: overflowing fb with y-axis coordinate
[05:23:32] [PASSED] Fail: overflowing fb with source width
[05:23:32] [PASSED] Fail: overflowing fb with source height
[05:23:32] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[05:23:32] [PASSED] drm_test_framebuffer_cleanup
[05:23:32] =============== drm_test_framebuffer_create ===============
[05:23:32] [PASSED] ABGR8888 normal sizes
[05:23:32] [PASSED] ABGR8888 max sizes
[05:23:32] [PASSED] ABGR8888 pitch greater than min required
[05:23:32] [PASSED] ABGR8888 pitch less than min required
[05:23:32] [PASSED] ABGR8888 Invalid width
[05:23:32] [PASSED] ABGR8888 Invalid buffer handle
[05:23:32] [PASSED] No pixel format
[05:23:32] [PASSED] ABGR8888 Width 0
[05:23:32] [PASSED] ABGR8888 Height 0
[05:23:32] [PASSED] ABGR8888 Out of bound height * pitch combination
[05:23:32] [PASSED] ABGR8888 Large buffer offset
[05:23:32] [PASSED] ABGR8888 Buffer offset for inexistent plane
[05:23:32] [PASSED] ABGR8888 Invalid flag
[05:23:32] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[05:23:32] [PASSED] ABGR8888 Valid buffer modifier
[05:23:32] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[05:23:32] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[05:23:32] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[05:23:32] [PASSED] NV12 Normal sizes
[05:23:32] [PASSED] NV12 Max sizes
[05:23:32] [PASSED] NV12 Invalid pitch
[05:23:32] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[05:23:32] [PASSED] NV12 different modifier per-plane
[05:23:32] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[05:23:32] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[05:23:32] [PASSED] NV12 Modifier for inexistent plane
[05:23:32] [PASSED] NV12 Handle for inexistent plane
[05:23:32] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[05:23:32] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[05:23:32] [PASSED] YVU420 Normal sizes
[05:23:32] [PASSED] YVU420 Max sizes
[05:23:32] [PASSED] YVU420 Invalid pitch
[05:23:32] [PASSED] YVU420 Different pitches
[05:23:32] [PASSED] YVU420 Different buffer offsets/pitches
[05:23:32] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[05:23:32] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[05:23:32] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[05:23:32] [PASSED] YVU420 Valid modifier
[05:23:32] [PASSED] YVU420 Different modifiers per plane
[05:23:32] [PASSED] YVU420 Modifier for inexistent plane
[05:23:32] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[05:23:32] [PASSED] X0L2 Normal sizes
[05:23:32] [PASSED] X0L2 Max sizes
[05:23:32] [PASSED] X0L2 Invalid pitch
[05:23:32] [PASSED] X0L2 Pitch greater than minimum required
[05:23:32] [PASSED] X0L2 Handle for inexistent plane
[05:23:32] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[05:23:32] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[05:23:32] [PASSED] X0L2 Valid modifier
[05:23:32] [PASSED] X0L2 Modifier for inexistent plane
[05:23:32] =========== [PASSED] drm_test_framebuffer_create ===========
[05:23:32] [PASSED] drm_test_framebuffer_free
[05:23:32] [PASSED] drm_test_framebuffer_init
[05:23:32] [PASSED] drm_test_framebuffer_init_bad_format
[05:23:32] [PASSED] drm_test_framebuffer_init_dev_mismatch
[05:23:32] [PASSED] drm_test_framebuffer_lookup
[05:23:32] [PASSED] drm_test_framebuffer_lookup_inexistent
[05:23:32] [PASSED] drm_test_framebuffer_modifiers_not_supported
[05:23:32] ================= [PASSED] drm_framebuffer =================
[05:23:32] ================ drm_gem_shmem (8 subtests) ================
[05:23:32] [PASSED] drm_gem_shmem_test_obj_create
[05:23:32] [PASSED] drm_gem_shmem_test_obj_create_private
[05:23:32] [PASSED] drm_gem_shmem_test_pin_pages
[05:23:32] [PASSED] drm_gem_shmem_test_vmap
[05:23:32] [PASSED] drm_gem_shmem_test_get_pages_sgt
[05:23:32] [PASSED] drm_gem_shmem_test_get_sg_table
[05:23:32] [PASSED] drm_gem_shmem_test_madvise
[05:23:32] [PASSED] drm_gem_shmem_test_purge
[05:23:32] ================== [PASSED] drm_gem_shmem ==================
[05:23:32] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[05:23:32] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[05:23:32] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[05:23:32] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[05:23:32] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[05:23:32] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[05:23:32] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[05:23:32] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[05:23:32] [PASSED] Automatic
[05:23:32] [PASSED] Full
[05:23:32] [PASSED] Limited 16:235
[05:23:32] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[05:23:32] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[05:23:32] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[05:23:32] [PASSED] drm_test_check_disable_connector
[05:23:32] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[05:23:32] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[05:23:32] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[05:23:32] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[05:23:32] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[05:23:32] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[05:23:32] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[05:23:32] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[05:23:32] [PASSED] drm_test_check_output_bpc_dvi
[05:23:32] [PASSED] drm_test_check_output_bpc_format_vic_1
[05:23:32] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[05:23:32] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[05:23:32] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[05:23:32] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[05:23:32] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[05:23:32] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[05:23:32] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[05:23:32] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[05:23:32] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[05:23:32] [PASSED] drm_test_check_broadcast_rgb_value
[05:23:32] [PASSED] drm_test_check_bpc_8_value
[05:23:32] [PASSED] drm_test_check_bpc_10_value
[05:23:32] [PASSED] drm_test_check_bpc_12_value
[05:23:32] [PASSED] drm_test_check_format_value
[05:23:32] [PASSED] drm_test_check_tmds_char_value
[05:23:32] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[05:23:32] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[05:23:32] [PASSED] drm_test_check_mode_valid
[05:23:32] [PASSED] drm_test_check_mode_valid_reject
[05:23:32] [PASSED] drm_test_check_mode_valid_reject_rate
[05:23:32] [PASSED] drm_test_check_mode_valid_reject_max_clock
[05:23:32] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[05:23:32] ================= drm_managed (2 subtests) =================
[05:23:32] [PASSED] drm_test_managed_release_action
[05:23:32] [PASSED] drm_test_managed_run_action
[05:23:32] =================== [PASSED] drm_managed ===================
[05:23:32] =================== drm_mm (6 subtests) ====================
[05:23:32] [PASSED] drm_test_mm_init
[05:23:32] [PASSED] drm_test_mm_debug
[05:23:32] [PASSED] drm_test_mm_align32
[05:23:32] [PASSED] drm_test_mm_align64
[05:23:32] [PASSED] drm_test_mm_lowest
[05:23:32] [PASSED] drm_test_mm_highest
[05:23:32] ===================== [PASSED] drm_mm ======================
[05:23:32] ============= drm_modes_analog_tv (5 subtests) =============
[05:23:32] [PASSED] drm_test_modes_analog_tv_mono_576i
[05:23:32] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[05:23:32] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[05:23:32] [PASSED] drm_test_modes_analog_tv_pal_576i
[05:23:32] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[05:23:32] =============== [PASSED] drm_modes_analog_tv ===============
[05:23:32] ============== drm_plane_helper (2 subtests) ===============
[05:23:32] =============== drm_test_check_plane_state ================
[05:23:32] [PASSED] clipping_simple
[05:23:32] [PASSED] clipping_rotate_reflect
[05:23:32] [PASSED] positioning_simple
[05:23:32] [PASSED] upscaling
[05:23:32] [PASSED] downscaling
[05:23:32] [PASSED] rounding1
[05:23:32] [PASSED] rounding2
[05:23:32] [PASSED] rounding3
[05:23:32] [PASSED] rounding4
[05:23:32] =========== [PASSED] drm_test_check_plane_state ============
[05:23:32] =========== drm_test_check_invalid_plane_state ============
[05:23:32] [PASSED] positioning_invalid
[05:23:32] [PASSED] upscaling_invalid
[05:23:32] [PASSED] downscaling_invalid
[05:23:32] ======= [PASSED] drm_test_check_invalid_plane_state ========
[05:23:32] ================ [PASSED] drm_plane_helper =================
[05:23:32] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[05:23:32] ====== drm_test_connector_helper_tv_get_modes_check =======
[05:23:32] [PASSED] None
[05:23:32] [PASSED] PAL
[05:23:32] [PASSED] NTSC
[05:23:32] [PASSED] Both, NTSC Default
[05:23:32] [PASSED] Both, PAL Default
[05:23:32] [PASSED] Both, NTSC Default, with PAL on command-line
[05:23:32] [PASSED] Both, PAL Default, with NTSC on command-line
[05:23:32] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[05:23:32] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[05:23:32] ================== drm_rect (9 subtests) ===================
[05:23:32] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[05:23:32] [PASSED] drm_test_rect_clip_scaled_not_clipped
[05:23:32] [PASSED] drm_test_rect_clip_scaled_clipped
[05:23:32] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[05:23:32] ================= drm_test_rect_intersect =================
[05:23:32] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[05:23:32] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[05:23:32] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[05:23:32] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[05:23:32] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[05:23:32] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[05:23:32] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[05:23:32] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[05:23:32] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[05:23:32] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[05:23:32] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[05:23:32] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[05:23:32] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[05:23:32] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[05:23:32] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[05:23:32] ============= [PASSED] drm_test_rect_intersect =============
[05:23:32] ================ drm_test_rect_calc_hscale ================
[05:23:32] [PASSED] normal use
[05:23:32] [PASSED] out of max range
[05:23:32] [PASSED] out of min range
[05:23:32] [PASSED] zero dst
[05:23:32] [PASSED] negative src
[05:23:32] [PASSED] negative dst
[05:23:32] ============ [PASSED] drm_test_rect_calc_hscale ============
[05:23:32] ================ drm_test_rect_calc_vscale ================
[05:23:32] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[05:23:32] [PASSED] out of max range
[05:23:32] [PASSED] out of min range
[05:23:32] [PASSED] zero dst
[05:23:32] [PASSED] negative src
[05:23:32] [PASSED] negative dst
[05:23:32] ============ [PASSED] drm_test_rect_calc_vscale ============
[05:23:32] ================== drm_test_rect_rotate ===================
[05:23:32] [PASSED] reflect-x
[05:23:32] [PASSED] reflect-y
[05:23:32] [PASSED] rotate-0
[05:23:32] [PASSED] rotate-90
[05:23:32] [PASSED] rotate-180
[05:23:32] [PASSED] rotate-270
[05:23:32] ============== [PASSED] drm_test_rect_rotate ===============
[05:23:32] ================ drm_test_rect_rotate_inv =================
[05:23:32] [PASSED] reflect-x
[05:23:32] [PASSED] reflect-y
[05:23:32] [PASSED] rotate-0
[05:23:32] [PASSED] rotate-90
[05:23:32] [PASSED] rotate-180
[05:23:32] [PASSED] rotate-270
[05:23:32] ============ [PASSED] drm_test_rect_rotate_inv =============
[05:23:32] ==================== [PASSED] drm_rect =====================
[05:23:32] ============ drm_sysfb_modeset_test (1 subtest) ============
[05:23:32] ============ drm_test_sysfb_build_fourcc_list =============
[05:23:32] [PASSED] no native formats
[05:23:32] [PASSED] XRGB8888 as native format
[05:23:32] [PASSED] remove duplicates
[05:23:32] [PASSED] convert alpha formats
[05:23:32] [PASSED] random formats
[05:23:32] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[05:23:32] ============= [PASSED] drm_sysfb_modeset_test ==============
[05:23:32] ============================================================
[05:23:32] Testing complete. Ran 622 tests: passed: 622
[05:23:32] Elapsed time: 26.859s total, 1.710s configuring, 24.727s building, 0.393s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[05:23:32] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:23:34] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:23:43] Starting KUnit Kernel (1/1)...
[05:23:43] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:23:43] ================= ttm_device (5 subtests) ==================
[05:23:43] [PASSED] ttm_device_init_basic
[05:23:43] [PASSED] ttm_device_init_multiple
[05:23:43] [PASSED] ttm_device_fini_basic
[05:23:43] [PASSED] ttm_device_init_no_vma_man
[05:23:43] ================== ttm_device_init_pools ==================
[05:23:43] [PASSED] No DMA allocations, no DMA32 required
[05:23:43] [PASSED] DMA allocations, DMA32 required
[05:23:43] [PASSED] No DMA allocations, DMA32 required
[05:23:43] [PASSED] DMA allocations, no DMA32 required
[05:23:43] ============== [PASSED] ttm_device_init_pools ==============
[05:23:43] =================== [PASSED] ttm_device ====================
[05:23:43] ================== ttm_pool (8 subtests) ===================
[05:23:43] ================== ttm_pool_alloc_basic ===================
[05:23:43] [PASSED] One page
[05:23:43] [PASSED] More than one page
[05:23:43] [PASSED] Above the allocation limit
[05:23:43] [PASSED] One page, with coherent DMA mappings enabled
[05:23:43] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:23:43] ============== [PASSED] ttm_pool_alloc_basic ===============
[05:23:43] ============== ttm_pool_alloc_basic_dma_addr ==============
[05:23:43] [PASSED] One page
[05:23:43] [PASSED] More than one page
[05:23:43] [PASSED] Above the allocation limit
[05:23:43] [PASSED] One page, with coherent DMA mappings enabled
[05:23:43] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:23:43] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[05:23:43] [PASSED] ttm_pool_alloc_order_caching_match
[05:23:43] [PASSED] ttm_pool_alloc_caching_mismatch
[05:23:43] [PASSED] ttm_pool_alloc_order_mismatch
[05:23:43] [PASSED] ttm_pool_free_dma_alloc
[05:23:43] [PASSED] ttm_pool_free_no_dma_alloc
[05:23:43] [PASSED] ttm_pool_fini_basic
[05:23:43] ==================== [PASSED] ttm_pool =====================
[05:23:43] ================ ttm_resource (8 subtests) =================
[05:23:43] ================= ttm_resource_init_basic =================
[05:23:43] [PASSED] Init resource in TTM_PL_SYSTEM
[05:23:43] [PASSED] Init resource in TTM_PL_VRAM
[05:23:43] [PASSED] Init resource in a private placement
[05:23:43] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[05:23:43] ============= [PASSED] ttm_resource_init_basic =============
[05:23:43] [PASSED] ttm_resource_init_pinned
[05:23:43] [PASSED] ttm_resource_fini_basic
[05:23:43] [PASSED] ttm_resource_manager_init_basic
[05:23:43] [PASSED] ttm_resource_manager_usage_basic
[05:23:43] [PASSED] ttm_resource_manager_set_used_basic
[05:23:43] [PASSED] ttm_sys_man_alloc_basic
[05:23:43] [PASSED] ttm_sys_man_free_basic
[05:23:43] ================== [PASSED] ttm_resource ===================
[05:23:43] =================== ttm_tt (15 subtests) ===================
[05:23:43] ==================== ttm_tt_init_basic ====================
[05:23:43] [PASSED] Page-aligned size
[05:23:43] [PASSED] Extra pages requested
[05:23:43] ================ [PASSED] ttm_tt_init_basic ================
[05:23:43] [PASSED] ttm_tt_init_misaligned
[05:23:43] [PASSED] ttm_tt_fini_basic
[05:23:43] [PASSED] ttm_tt_fini_sg
[05:23:43] [PASSED] ttm_tt_fini_shmem
[05:23:43] [PASSED] ttm_tt_create_basic
[05:23:43] [PASSED] ttm_tt_create_invalid_bo_type
[05:23:43] [PASSED] ttm_tt_create_ttm_exists
[05:23:43] [PASSED] ttm_tt_create_failed
[05:23:43] [PASSED] ttm_tt_destroy_basic
[05:23:43] [PASSED] ttm_tt_populate_null_ttm
[05:23:43] [PASSED] ttm_tt_populate_populated_ttm
[05:23:43] [PASSED] ttm_tt_unpopulate_basic
[05:23:43] [PASSED] ttm_tt_unpopulate_empty_ttm
[05:23:43] [PASSED] ttm_tt_swapin_basic
[05:23:43] ===================== [PASSED] ttm_tt ======================
[05:23:43] =================== ttm_bo (14 subtests) ===================
[05:23:43] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[05:23:43] [PASSED] Cannot be interrupted and sleeps
[05:23:43] [PASSED] Cannot be interrupted, locks straight away
[05:23:43] [PASSED] Can be interrupted, sleeps
[05:23:43] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[05:23:43] [PASSED] ttm_bo_reserve_locked_no_sleep
[05:23:43] [PASSED] ttm_bo_reserve_no_wait_ticket
[05:23:43] [PASSED] ttm_bo_reserve_double_resv
[05:23:43] [PASSED] ttm_bo_reserve_interrupted
[05:23:43] [PASSED] ttm_bo_reserve_deadlock
[05:23:43] [PASSED] ttm_bo_unreserve_basic
[05:23:43] [PASSED] ttm_bo_unreserve_pinned
[05:23:43] [PASSED] ttm_bo_unreserve_bulk
[05:23:43] [PASSED] ttm_bo_fini_basic
[05:23:43] [PASSED] ttm_bo_fini_shared_resv
[05:23:43] [PASSED] ttm_bo_pin_basic
[05:23:43] [PASSED] ttm_bo_pin_unpin_resource
[05:23:43] [PASSED] ttm_bo_multiple_pin_one_unpin
[05:23:43] ===================== [PASSED] ttm_bo ======================
[05:23:43] ============== ttm_bo_validate (21 subtests) ===============
[05:23:43] ============== ttm_bo_init_reserved_sys_man ===============
[05:23:43] [PASSED] Buffer object for userspace
[05:23:43] [PASSED] Kernel buffer object
[05:23:43] [PASSED] Shared buffer object
[05:23:43] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[05:23:43] ============== ttm_bo_init_reserved_mock_man ==============
[05:23:43] [PASSED] Buffer object for userspace
[05:23:43] [PASSED] Kernel buffer object
[05:23:43] [PASSED] Shared buffer object
[05:23:43] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[05:23:43] [PASSED] ttm_bo_init_reserved_resv
[05:23:43] ================== ttm_bo_validate_basic ==================
[05:23:43] [PASSED] Buffer object for userspace
[05:23:43] [PASSED] Kernel buffer object
[05:23:43] [PASSED] Shared buffer object
[05:23:43] ============== [PASSED] ttm_bo_validate_basic ==============
[05:23:43] [PASSED] ttm_bo_validate_invalid_placement
[05:23:43] ============= ttm_bo_validate_same_placement ==============
[05:23:43] [PASSED] System manager
[05:23:43] [PASSED] VRAM manager
[05:23:43] ========= [PASSED] ttm_bo_validate_same_placement ==========
[05:23:43] [PASSED] ttm_bo_validate_failed_alloc
[05:23:43] [PASSED] ttm_bo_validate_pinned
[05:23:43] [PASSED] ttm_bo_validate_busy_placement
[05:23:43] ================ ttm_bo_validate_multihop =================
[05:23:43] [PASSED] Buffer object for userspace
[05:23:43] [PASSED] Kernel buffer object
[05:23:43] [PASSED] Shared buffer object
[05:23:43] ============ [PASSED] ttm_bo_validate_multihop =============
[05:23:43] ========== ttm_bo_validate_no_placement_signaled ==========
[05:23:43] [PASSED] Buffer object in system domain, no page vector
[05:23:43] [PASSED] Buffer object in system domain with an existing page vector
[05:23:43] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[05:23:43] ======== ttm_bo_validate_no_placement_not_signaled ========
[05:23:43] [PASSED] Buffer object for userspace
[05:23:43] [PASSED] Kernel buffer object
[05:23:43] [PASSED] Shared buffer object
[05:23:43] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[05:23:43] [PASSED] ttm_bo_validate_move_fence_signaled
[05:23:43] ========= ttm_bo_validate_move_fence_not_signaled =========
[05:23:43] [PASSED] Waits for GPU
[05:23:43] [PASSED] Tries to lock straight away
[05:23:43] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[05:23:43] [PASSED] ttm_bo_validate_happy_evict
[05:23:43] [PASSED] ttm_bo_validate_all_pinned_evict
[05:23:43] [PASSED] ttm_bo_validate_allowed_only_evict
[05:23:43] [PASSED] ttm_bo_validate_deleted_evict
[05:23:43] [PASSED] ttm_bo_validate_busy_domain_evict
[05:23:43] [PASSED] ttm_bo_validate_evict_gutting
[05:23:43] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[05:23:43] ================= [PASSED] ttm_bo_validate =================
[05:23:43] ============================================================
[05:23:43] Testing complete. Ran 101 tests: passed: 101
[05:23:44] Elapsed time: 11.228s total, 1.722s configuring, 9.290s building, 0.181s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✗ CI.checksparse: warning for Optimize vrr.guardband (rev3)
2025-10-17 5:01 [PATCH 0/5] Optimize vrr.guardband Ankit Nautiyal
` (5 preceding siblings ...)
2025-10-17 5:23 ` ✓ CI.KUnit: success for Optimize vrr.guardband (rev3) Patchwork
@ 2025-10-17 5:38 ` Patchwork
2025-10-17 6:14 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-18 4:53 ` ✗ Xe.CI.Full: failure " Patchwork
8 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-10-17 5:38 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
== Series Details ==
Series: Optimize vrr.guardband (rev3)
URL : https://patchwork.freedesktop.org/series/155979/
State : warning
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast b4f191dddaee9ae1871344e3dabcc40f2f14d2cb
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2057:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2057:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ Xe.CI.BAT: success for Optimize vrr.guardband (rev3)
2025-10-17 5:01 [PATCH 0/5] Optimize vrr.guardband Ankit Nautiyal
` (6 preceding siblings ...)
2025-10-17 5:38 ` ✗ CI.checksparse: warning " Patchwork
@ 2025-10-17 6:14 ` Patchwork
2025-10-18 4:53 ` ✗ Xe.CI.Full: failure " Patchwork
8 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-10-17 6:14 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1454 bytes --]
== Series Details ==
Series: Optimize vrr.guardband (rev3)
URL : https://patchwork.freedesktop.org/series/155979/
State : success
== Summary ==
CI Bug Log - changes from xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb_BAT -> xe-pw-155979v3_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-155979v3_BAT that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@kms_flip@basic-plain-flip@d-edp1:
- bat-adlp-7: [DMESG-WARN][1] ([Intel XE#4543]) -> [PASS][2] +1 other test pass
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/bat-adlp-7/igt@kms_flip@basic-plain-flip@d-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/bat-adlp-7/igt@kms_flip@basic-plain-flip@d-edp1.html
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
Build changes
-------------
* Linux: xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb -> xe-pw-155979v3
IGT_8589: 8589
xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb: b4f191dddaee9ae1871344e3dabcc40f2f14d2cb
xe-pw-155979v3: 155979v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/index.html
[-- Attachment #2: Type: text/html, Size: 2019 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/5] drm/i915/psr: Add helper to get min psr guardband
2025-10-17 5:01 ` [PATCH 1/5] drm/i915/psr: Add helper to get min psr guardband Ankit Nautiyal
@ 2025-10-17 9:07 ` Hogander, Jouni
2025-10-17 9:30 ` Hogander, Jouni
2025-10-17 9:37 ` Nautiyal, Ankit K
0 siblings, 2 replies; 25+ messages in thread
From: Hogander, Jouni @ 2025-10-17 9:07 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
On Fri, 2025-10-17 at 10:31 +0530, Ankit Nautiyal wrote:
> Introduce a helper to compute the max link wake latency when using
> Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.
>
> This will be used to compute the minimum guardband so that the link
> wake
> latencies are accounted and these features work smoothly for higher
> refresh rate panels.
>
> Bspec: 70151, 71477
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
> drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 703e5f6af04c..a8303b669853 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -4416,3 +4416,15 @@ void intel_psr_compute_config_late(struct
> intel_dp *intel_dp,
>
> intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
> }
> +
> +int intel_psr_min_guardband(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display =
> to_intel_display(crtc_state);
> + int auxless_wake_lines = crtc_state-
> >alpm_state.aux_less_wake_lines;
> + int wake_lines = DISPLAY_VER(display) < 20 ?
> + psr2_block_count_lines(crtc_state-
> >alpm_state.io_wake_lines,
> + crtc_state-
> >alpm_state.fast_wake_lines) :
> + crtc_state->alpm_state.io_wake_lines;
> +
> + return max(auxless_wake_lines, wake_lines);
hmm, now if you add:
if (crtc_state->req_psr2_sdp_prior_scanline)
psr_min_guardband++;
Whatever is the PSR mode it can be enabled what comes to vblank
restrictions and you can drop psr_compute_config_late?
BR,
Jouni Högander
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index b17ce312dc37..620b35928832 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -85,5 +85,6 @@ bool intel_psr_needs_alpm_aux_less(struct intel_dp
> *intel_dp,
> const struct intel_crtc_state
> *crtc_state);
> void intel_psr_compute_config_late(struct intel_dp *intel_dp,
> struct intel_crtc_state
> *crtc_state);
> +int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_PSR_H__ */
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/5] drm/i915/psr: Add helper to get min psr guardband
2025-10-17 9:07 ` Hogander, Jouni
@ 2025-10-17 9:30 ` Hogander, Jouni
2025-10-17 9:41 ` Nautiyal, Ankit K
2025-10-17 9:37 ` Nautiyal, Ankit K
1 sibling, 1 reply; 25+ messages in thread
From: Hogander, Jouni @ 2025-10-17 9:30 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
On Fri, 2025-10-17 at 09:07 +0000, Hogander, Jouni wrote:
> On Fri, 2025-10-17 at 10:31 +0530, Ankit Nautiyal wrote:
> > Introduce a helper to compute the max link wake latency when using
> > Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.
> >
> > This will be used to compute the minimum guardband so that the link
> > wake
> > latencies are accounted and these features work smoothly for higher
> > refresh rate panels.
> >
> > Bspec: 70151, 71477
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
> > drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> > 2 files changed, 13 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 703e5f6af04c..a8303b669853 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -4416,3 +4416,15 @@ void intel_psr_compute_config_late(struct
> > intel_dp *intel_dp,
> >
> > intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
> > }
> > +
> > +int intel_psr_min_guardband(struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_display *display =
> > to_intel_display(crtc_state);
> > + int auxless_wake_lines = crtc_state-
> > > alpm_state.aux_less_wake_lines;
> > + int wake_lines = DISPLAY_VER(display) < 20 ?
> > + psr2_block_count_lines(crtc_state-
> > > alpm_state.io_wake_lines,
> > + crtc_state-
> > > alpm_state.fast_wake_lines) :
> > + crtc_state->alpm_state.io_wake_lines;
> > +
> > + return max(auxless_wake_lines, wake_lines);
>
> hmm, now if you add:
>
> if (crtc_state->req_psr2_sdp_prior_scanline)
> psr_min_guardband++;
>
> Whatever is the PSR mode it can be enabled what comes to vblank
> restrictions and you can drop psr_compute_config_late?
also this should be added to remove psr_compute_config_late:
psr_min_guardband += _intel_psr_min_set_context_latency(crtc_state,
crtc_state->has_panel_replay,
crtc_state->has_sel_update);
BR,
Jouni Högander
>
> BR,
>
> Jouni Högander
>
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index b17ce312dc37..620b35928832 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -85,5 +85,6 @@ bool intel_psr_needs_alpm_aux_less(struct
> > intel_dp
> > *intel_dp,
> > const struct intel_crtc_state
> > *crtc_state);
> > void intel_psr_compute_config_late(struct intel_dp *intel_dp,
> > struct intel_crtc_state
> > *crtc_state);
> > +int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
> >
> > #endif /* __INTEL_PSR_H__ */
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/5] drm/i915/psr: Add helper to get min psr guardband
2025-10-17 9:07 ` Hogander, Jouni
2025-10-17 9:30 ` Hogander, Jouni
@ 2025-10-17 9:37 ` Nautiyal, Ankit K
2025-10-17 9:58 ` Hogander, Jouni
1 sibling, 1 reply; 25+ messages in thread
From: Nautiyal, Ankit K @ 2025-10-17 9:37 UTC (permalink / raw)
To: Hogander, Jouni, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
On 10/17/2025 2:37 PM, Hogander, Jouni wrote:
> On Fri, 2025-10-17 at 10:31 +0530, Ankit Nautiyal wrote:
>> Introduce a helper to compute the max link wake latency when using
>> Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.
>>
>> This will be used to compute the minimum guardband so that the link
>> wake
>> latencies are accounted and these features work smoothly for higher
>> refresh rate panels.
>>
>> Bspec: 70151, 71477
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
>> drivers/gpu/drm/i915/display/intel_psr.h | 1 +
>> 2 files changed, 13 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>> b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 703e5f6af04c..a8303b669853 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -4416,3 +4416,15 @@ void intel_psr_compute_config_late(struct
>> intel_dp *intel_dp,
>>
>> intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
>> }
>> +
>> +int intel_psr_min_guardband(struct intel_crtc_state *crtc_state)
>> +{
>> + struct intel_display *display =
>> to_intel_display(crtc_state);
>> + int auxless_wake_lines = crtc_state-
>>> alpm_state.aux_less_wake_lines;
>> + int wake_lines = DISPLAY_VER(display) < 20 ?
>> + psr2_block_count_lines(crtc_state-
>>> alpm_state.io_wake_lines,
>> + crtc_state-
>>> alpm_state.fast_wake_lines) :
>> + crtc_state->alpm_state.io_wake_lines;
>> +
>> + return max(auxless_wake_lines, wake_lines);
> hmm, now if you add:
>
> if (crtc_state->req_psr2_sdp_prior_scanline)
> psr_min_guardband++;
I did not get this part. Do we need to account for 1 more wakelines if
this flag is set?
What we want to do is to check for min guardband for
panel_replay/sel_update based on the required wakelines.
Whether we can use the auxless_wake_lines and wake_lines as computed
above to estimate the max wakelines or instead we should use functions
from alpm.c :
io_buffer_wake_time() and _lnl_compute_aux_less_wake_time() to get the
worst case wakelines.
>
> Whatever is the PSR mode it can be enabled what comes to vblank
> restrictions and you can drop psr_compute_config_late?
I think we cannot drop the psr_compute_config_late as it checks whether
the actual guardband is enough for PSR features.
intel_psr_min_guardband() is used along with other features to have an estimate on the guardband that works for all cases, without a need to change the guardband.
It is bounded by the vblank length available
Regards,
Ankit
>
> BR,
>
> Jouni Högander
>
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
>> b/drivers/gpu/drm/i915/display/intel_psr.h
>> index b17ce312dc37..620b35928832 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
>> @@ -85,5 +85,6 @@ bool intel_psr_needs_alpm_aux_less(struct intel_dp
>> *intel_dp,
>> const struct intel_crtc_state
>> *crtc_state);
>> void intel_psr_compute_config_late(struct intel_dp *intel_dp,
>> struct intel_crtc_state
>> *crtc_state);
>> +int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
>>
>> #endif /* __INTEL_PSR_H__ */
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/5] drm/i915/psr: Add helper to get min psr guardband
2025-10-17 9:30 ` Hogander, Jouni
@ 2025-10-17 9:41 ` Nautiyal, Ankit K
0 siblings, 0 replies; 25+ messages in thread
From: Nautiyal, Ankit K @ 2025-10-17 9:41 UTC (permalink / raw)
To: Hogander, Jouni, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
On 10/17/2025 3:00 PM, Hogander, Jouni wrote:
> On Fri, 2025-10-17 at 09:07 +0000, Hogander, Jouni wrote:
>> On Fri, 2025-10-17 at 10:31 +0530, Ankit Nautiyal wrote:
>>> Introduce a helper to compute the max link wake latency when using
>>> Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.
>>>
>>> This will be used to compute the minimum guardband so that the link
>>> wake
>>> latencies are accounted and these features work smoothly for higher
>>> refresh rate panels.
>>>
>>> Bspec: 70151, 71477
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
>>> drivers/gpu/drm/i915/display/intel_psr.h | 1 +
>>> 2 files changed, 13 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>>> b/drivers/gpu/drm/i915/display/intel_psr.c
>>> index 703e5f6af04c..a8303b669853 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>> @@ -4416,3 +4416,15 @@ void intel_psr_compute_config_late(struct
>>> intel_dp *intel_dp,
>>>
>>> intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
>>> }
>>> +
>>> +int intel_psr_min_guardband(struct intel_crtc_state *crtc_state)
>>> +{
>>> + struct intel_display *display =
>>> to_intel_display(crtc_state);
>>> + int auxless_wake_lines = crtc_state-
>>>> alpm_state.aux_less_wake_lines;
>>> + int wake_lines = DISPLAY_VER(display) < 20 ?
>>> + psr2_block_count_lines(crtc_state-
>>>> alpm_state.io_wake_lines,
>>> + crtc_state-
>>>> alpm_state.fast_wake_lines) :
>>> + crtc_state->alpm_state.io_wake_lines;
>>> +
>>> + return max(auxless_wake_lines, wake_lines);
>> hmm, now if you add:
>>
>> if (crtc_state->req_psr2_sdp_prior_scanline)
>> psr_min_guardband++;
>>
>> Whatever is the PSR mode it can be enabled what comes to vblank
>> restrictions and you can drop psr_compute_config_late?
> also this should be added to remove psr_compute_config_late:
>
> psr_min_guardband += _intel_psr_min_set_context_latency(crtc_state,
> crtc_state->has_panel_replay,
> crtc_state->has_sel_update);
No we dont need to use scl here.
We compare the actual optimized guardband based on different features
and then take min(optimized_guardband, intel_vrr_max_vblank_guardband())
intel_vrr_max_vblank_guardband() takes into account if there are SCL
lines, so those are subtracted.
Regards,
Ankit
>
> BR,
>
> Jouni Högander
>
>> BR,
>>
>> Jouni Högander
>>
>>> +}
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
>>> b/drivers/gpu/drm/i915/display/intel_psr.h
>>> index b17ce312dc37..620b35928832 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
>>> @@ -85,5 +85,6 @@ bool intel_psr_needs_alpm_aux_less(struct
>>> intel_dp
>>> *intel_dp,
>>> const struct intel_crtc_state
>>> *crtc_state);
>>> void intel_psr_compute_config_late(struct intel_dp *intel_dp,
>>> struct intel_crtc_state
>>> *crtc_state);
>>> +int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
>>>
>>> #endif /* __INTEL_PSR_H__ */
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/5] drm/i915/psr: Add helper to get min psr guardband
2025-10-17 9:37 ` Nautiyal, Ankit K
@ 2025-10-17 9:58 ` Hogander, Jouni
2025-10-17 10:15 ` Hogander, Jouni
0 siblings, 1 reply; 25+ messages in thread
From: Hogander, Jouni @ 2025-10-17 9:58 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
On Fri, 2025-10-17 at 15:07 +0530, Nautiyal, Ankit K wrote:
>
> On 10/17/2025 2:37 PM, Hogander, Jouni wrote:
> > On Fri, 2025-10-17 at 10:31 +0530, Ankit Nautiyal wrote:
> > > Introduce a helper to compute the max link wake latency when
> > > using
> > > Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.
> > >
> > > This will be used to compute the minimum guardband so that the
> > > link
> > > wake
> > > latencies are accounted and these features work smoothly for
> > > higher
> > > refresh rate panels.
> > >
> > > Bspec: 70151, 71477
> > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
> > > drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> > > 2 files changed, 13 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 703e5f6af04c..a8303b669853 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -4416,3 +4416,15 @@ void intel_psr_compute_config_late(struct
> > > intel_dp *intel_dp,
> > >
> > > intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
> > > }
> > > +
> > > +int intel_psr_min_guardband(struct intel_crtc_state *crtc_state)
> > > +{
> > > + struct intel_display *display =
> > > to_intel_display(crtc_state);
> > > + int auxless_wake_lines = crtc_state-
> > > > alpm_state.aux_less_wake_lines;
> > > + int wake_lines = DISPLAY_VER(display) < 20 ?
> > > + psr2_block_count_lines(crtc_state-
> > > > alpm_state.io_wake_lines,
> > > + crtc_state-
> > > > alpm_state.fast_wake_lines) :
> > > + crtc_state->alpm_state.io_wake_lines;
> > > +
> > > + return max(auxless_wake_lines, wake_lines);
> > hmm, now if you add:
> >
> > if (crtc_state->req_psr2_sdp_prior_scanline)
> > psr_min_guardband++;
>
> I did not get this part. Do we need to account for 1 more wakelines
> if
> this flag is set?
If you look at how that flag affects vblank check in
intel_psr_compute_config_late:
...
static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state,
int vblank,
int wake_lines)
{
if (crtc_state->req_psr2_sdp_prior_scanline)
vblank -= 1;
...
So to take that into account when calculating minimum guardband needed
by PSR you need to increase by one. Same goes with SCL:
...
int scl = _intel_psr_min_set_context_latency(crtc_state,
needs_panel_replay,
needs_sel_update);
vblank -= scl;
...
You are already partially taking into account PSR needs when
calculating optimized guardband except these two lines which are needed
conditionally.
Also intel_psr_compute_config is run at this point -> you know which
one to use: auxless wake time or aux wake time. no need to use max()
with them. Just choose the one which is relevant.
With these changes you could drop intel_psr_compute_config_late as
vblank would be long enough for PSR mode computed by
intel_psr_compute_config, no?
BR,
Jouni Högander
>
> What we want to do is to check for min guardband for
> panel_replay/sel_update based on the required wakelines.
>
> Whether we can use the auxless_wake_lines and wake_lines as computed
> above to estimate the max wakelines or instead we should use
> functions
> from alpm.c :
>
> io_buffer_wake_time() and _lnl_compute_aux_less_wake_time() to get
> the
> worst case wakelines.
>
>
> >
> > Whatever is the PSR mode it can be enabled what comes to vblank
> > restrictions and you can drop psr_compute_config_late?
>
>
> I think we cannot drop the psr_compute_config_late as it checks
> whether
> the actual guardband is enough for PSR features.
>
> intel_psr_min_guardband() is used along with other features to have
> an estimate on the guardband that works for all cases, without a need
> to change the guardband.
> It is bounded by the vblank length available
>
> Regards,
>
> Ankit
>
> >
> > BR,
> >
> > Jouni Högander
> >
> > > +}
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > index b17ce312dc37..620b35928832 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > @@ -85,5 +85,6 @@ bool intel_psr_needs_alpm_aux_less(struct
> > > intel_dp
> > > *intel_dp,
> > > const struct intel_crtc_state
> > > *crtc_state);
> > > void intel_psr_compute_config_late(struct intel_dp *intel_dp,
> > > struct intel_crtc_state
> > > *crtc_state);
> > > +int intel_psr_min_guardband(struct intel_crtc_state
> > > *crtc_state);
> > >
> > > #endif /* __INTEL_PSR_H__ */
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/5] drm/i915/psr: Add helper to get min psr guardband
2025-10-17 9:58 ` Hogander, Jouni
@ 2025-10-17 10:15 ` Hogander, Jouni
2025-10-17 10:30 ` Hogander, Jouni
2025-10-17 11:11 ` Nautiyal, Ankit K
0 siblings, 2 replies; 25+ messages in thread
From: Hogander, Jouni @ 2025-10-17 10:15 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
On Fri, 2025-10-17 at 12:58 +0300, Hogander, Jouni wrote:
> On Fri, 2025-10-17 at 15:07 +0530, Nautiyal, Ankit K wrote:
> >
> > On 10/17/2025 2:37 PM, Hogander, Jouni wrote:
> > > On Fri, 2025-10-17 at 10:31 +0530, Ankit Nautiyal wrote:
> > > > Introduce a helper to compute the max link wake latency when
> > > > using
> > > > Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.
> > > >
> > > > This will be used to compute the minimum guardband so that the
> > > > link
> > > > wake
> > > > latencies are accounted and these features work smoothly for
> > > > higher
> > > > refresh rate panels.
> > > >
> > > > Bspec: 70151, 71477
> > > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
> > > > drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> > > > 2 files changed, 13 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 703e5f6af04c..a8303b669853 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -4416,3 +4416,15 @@ void
> > > > intel_psr_compute_config_late(struct
> > > > intel_dp *intel_dp,
> > > >
> > > > intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
> > > > }
> > > > +
> > > > +int intel_psr_min_guardband(struct intel_crtc_state
> > > > *crtc_state)
> > > > +{
> > > > + struct intel_display *display =
> > > > to_intel_display(crtc_state);
> > > > + int auxless_wake_lines = crtc_state-
> > > > > alpm_state.aux_less_wake_lines;
> > > > + int wake_lines = DISPLAY_VER(display) < 20 ?
> > > > + psr2_block_count_lines(crtc_state-
> > > > > alpm_state.io_wake_lines,
> > > > + crtc_state-
> > > > > alpm_state.fast_wake_lines) :
> > > > + crtc_state->alpm_state.io_wake_lines;
> > > > +
> > > > + return max(auxless_wake_lines, wake_lines);
> > > hmm, now if you add:
> > >
> > > if (crtc_state->req_psr2_sdp_prior_scanline)
> > > psr_min_guardband++;
> >
> > I did not get this part. Do we need to account for 1 more wakelines
> > if
> > this flag is set?
>
> If you look at how that flag affects vblank check in
> intel_psr_compute_config_late:
>
> ...
> static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state
> *crtc_state,
> int vblank,
> int wake_lines)
> {
> if (crtc_state->req_psr2_sdp_prior_scanline)
> vblank -= 1;
> ...
>
> So to take that into account when calculating minimum guardband
> needed
> by PSR you need to increase by one. Same goes with SCL:
>
> ...
> int scl = _intel_psr_min_set_context_latency(crtc_state,
>
> needs_panel_replay,
>
> needs_sel_update);
> vblank -= scl;
> ...
>
> You are already partially taking into account PSR needs when
> calculating optimized guardband except these two lines which are
> needed
> conditionally.
>
> Also intel_psr_compute_config is run at this point -> you know which
> one to use: auxless wake time or aux wake time. no need to use max()
> with them. Just choose the one which is relevant.
>
> With these changes you could drop intel_psr_compute_config_late as
> vblank would be long enough for PSR mode computed by
> intel_psr_compute_config, no?
Ok, noticed now this in the last patch:
...
crtc_state->vrr.guardband = min(guardband, intel_vrr_max_guardband(crtc_state));
...
So if we need to fall back to intel_vrr_max_guardband we need to have
that intel_psr_compute_config_late.
Anyways I think you need to take into account that
req_psr2_sdp_prior_scanline and _intel_psr_min_set_context_latency in
intel_psr_min_guardband.
BR,
Jouni Högander
>
> BR,
>
> Jouni Högander
>
>
> >
> > What we want to do is to check for min guardband for
> > panel_replay/sel_update based on the required wakelines.
> >
> > Whether we can use the auxless_wake_lines and wake_lines as
> > computed
> > above to estimate the max wakelines or instead we should use
> > functions
> > from alpm.c :
> >
> > io_buffer_wake_time() and _lnl_compute_aux_less_wake_time() to get
> > the
> > worst case wakelines.
> >
> >
> > >
> > > Whatever is the PSR mode it can be enabled what comes to vblank
> > > restrictions and you can drop psr_compute_config_late?
> >
> >
> > I think we cannot drop the psr_compute_config_late as it checks
> > whether
> > the actual guardband is enough for PSR features.
> >
> > intel_psr_min_guardband() is used along with other features to have
> > an estimate on the guardband that works for all cases, without a
> > need
> > to change the guardband.
> > It is bounded by the vblank length available
> >
> > Regards,
> >
> > Ankit
> >
> > >
> > > BR,
> > >
> > > Jouni Högander
> > >
> > > > +}
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > index b17ce312dc37..620b35928832 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > @@ -85,5 +85,6 @@ bool intel_psr_needs_alpm_aux_less(struct
> > > > intel_dp
> > > > *intel_dp,
> > > > const struct
> > > > intel_crtc_state
> > > > *crtc_state);
> > > > void intel_psr_compute_config_late(struct intel_dp *intel_dp,
> > > > struct intel_crtc_state
> > > > *crtc_state);
> > > > +int intel_psr_min_guardband(struct intel_crtc_state
> > > > *crtc_state);
> > > >
> > > > #endif /* __INTEL_PSR_H__ */
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/5] drm/i915/psr: Add helper to get min psr guardband
2025-10-17 10:15 ` Hogander, Jouni
@ 2025-10-17 10:30 ` Hogander, Jouni
2025-10-17 11:11 ` Nautiyal, Ankit K
1 sibling, 0 replies; 25+ messages in thread
From: Hogander, Jouni @ 2025-10-17 10:30 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
On Fri, 2025-10-17 at 13:15 +0300, Hogander, Jouni wrote:
> On Fri, 2025-10-17 at 12:58 +0300, Hogander, Jouni wrote:
> > On Fri, 2025-10-17 at 15:07 +0530, Nautiyal, Ankit K wrote:
> > >
> > > On 10/17/2025 2:37 PM, Hogander, Jouni wrote:
> > > > On Fri, 2025-10-17 at 10:31 +0530, Ankit Nautiyal wrote:
> > > > > Introduce a helper to compute the max link wake latency when
> > > > > using
> > > > > Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF
> > > > > features.
> > > > >
> > > > > This will be used to compute the minimum guardband so that
> > > > > the
> > > > > link
> > > > > wake
> > > > > latencies are accounted and these features work smoothly for
> > > > > higher
> > > > > refresh rate panels.
> > > > >
> > > > > Bspec: 70151, 71477
> > > > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
> > > > > drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> > > > > 2 files changed, 13 insertions(+)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > index 703e5f6af04c..a8303b669853 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > @@ -4416,3 +4416,15 @@ void
> > > > > intel_psr_compute_config_late(struct
> > > > > intel_dp *intel_dp,
> > > > >
> > > > > intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
> > > > > }
> > > > > +
> > > > > +int intel_psr_min_guardband(struct intel_crtc_state
> > > > > *crtc_state)
> > > > > +{
> > > > > + struct intel_display *display =
> > > > > to_intel_display(crtc_state);
> > > > > + int auxless_wake_lines = crtc_state-
> > > > > > alpm_state.aux_less_wake_lines;
> > > > > + int wake_lines = DISPLAY_VER(display) < 20 ?
> > > > > + psr2_block_count_lines(crtc_state-
> > > > > > alpm_state.io_wake_lines,
> > > > > + crtc_state-
> > > > > > alpm_state.fast_wake_lines) :
> > > > > + crtc_state-
> > > > > >alpm_state.io_wake_lines;
> > > > > +
> > > > > + return max(auxless_wake_lines, wake_lines);
> > > > hmm, now if you add:
> > > >
> > > > if (crtc_state->req_psr2_sdp_prior_scanline)
> > > > psr_min_guardband++;
> > >
> > > I did not get this part. Do we need to account for 1 more
> > > wakelines
> > > if
> > > this flag is set?
> >
> > If you look at how that flag affects vblank check in
> > intel_psr_compute_config_late:
> >
> > ...
> > static bool _wake_lines_fit_into_vblank(const struct
> > intel_crtc_state
> > *crtc_state,
> > int vblank,
> > int wake_lines)
> > {
> > if (crtc_state->req_psr2_sdp_prior_scanline)
> > vblank -= 1;
> > ...
> >
> > So to take that into account when calculating minimum guardband
> > needed
> > by PSR you need to increase by one. Same goes with SCL:
> >
> > ...
> > int scl = _intel_psr_min_set_context_latency(crtc_state,
> >
> > needs_panel_replay,
> >
> > needs_sel_update);
> > vblank -= scl;
> > ...
> >
> > You are already partially taking into account PSR needs when
> > calculating optimized guardband except these two lines which are
> > needed
> > conditionally.
> >
> > Also intel_psr_compute_config is run at this point -> you know
> > which
> > one to use: auxless wake time or aux wake time. no need to use
> > max()
> > with them. Just choose the one which is relevant.
> >
> > With these changes you could drop intel_psr_compute_config_late as
> > vblank would be long enough for PSR mode computed by
> > intel_psr_compute_config, no?
>
> Ok, noticed now this in the last patch:
>
> ...
> crtc_state->vrr.guardband = min(guardband,
> intel_vrr_max_guardband(crtc_state));
> ...
>
> So if we need to fall back to intel_vrr_max_guardband we need to have
> that intel_psr_compute_config_late.
>
> Anyways I think you need to take into account that
> req_psr2_sdp_prior_scanline and _intel_psr_min_set_context_latency in
> intel_psr_min_guardband.
Also you can use auxless wake time for Panel Replay with ALPM and aux
wake time for PSR2 because only following changes are possible in
intel_psr_compute_config_late:
PSR2 (aux wake time) -> PSR1 -> guardband length doesn't matter
Panel Replay (auxless wake time) -> disabled -> guardband length
doesn't matter
BR,
Jouni Högander
>
> BR,
>
> Jouni Högander
> >
> > BR,
> >
> > Jouni Högander
> >
> >
> > >
> > > What we want to do is to check for min guardband for
> > > panel_replay/sel_update based on the required wakelines.
> > >
> > > Whether we can use the auxless_wake_lines and wake_lines as
> > > computed
> > > above to estimate the max wakelines or instead we should use
> > > functions
> > > from alpm.c :
> > >
> > > io_buffer_wake_time() and _lnl_compute_aux_less_wake_time() to
> > > get
> > > the
> > > worst case wakelines.
> > >
> > >
> > > >
> > > > Whatever is the PSR mode it can be enabled what comes to vblank
> > > > restrictions and you can drop psr_compute_config_late?
> > >
> > >
> > > I think we cannot drop the psr_compute_config_late as it checks
> > > whether
> > > the actual guardband is enough for PSR features.
> > >
> > > intel_psr_min_guardband() is used along with other features to
> > > have
> > > an estimate on the guardband that works for all cases, without a
> > > need
> > > to change the guardband.
> > > It is bounded by the vblank length available
> > >
> > > Regards,
> > >
> > > Ankit
> > >
> > > >
> > > > BR,
> > > >
> > > > Jouni Högander
> > > >
> > > > > +}
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > index b17ce312dc37..620b35928832 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > @@ -85,5 +85,6 @@ bool intel_psr_needs_alpm_aux_less(struct
> > > > > intel_dp
> > > > > *intel_dp,
> > > > > const struct
> > > > > intel_crtc_state
> > > > > *crtc_state);
> > > > > void intel_psr_compute_config_late(struct intel_dp
> > > > > *intel_dp,
> > > > > struct intel_crtc_state
> > > > > *crtc_state);
> > > > > +int intel_psr_min_guardband(struct intel_crtc_state
> > > > > *crtc_state);
> > > > >
> > > > > #endif /* __INTEL_PSR_H__ */
> >
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/5] drm/i915/dp: Add helper to get min sdp guardband
2025-10-17 5:01 ` [PATCH 2/5] drm/i915/dp: Add helper to get min sdp guardband Ankit Nautiyal
@ 2025-10-17 10:50 ` Hogander, Jouni
2025-10-17 11:07 ` Nautiyal, Ankit K
0 siblings, 1 reply; 25+ messages in thread
From: Hogander, Jouni @ 2025-10-17 10:50 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
On Fri, 2025-10-17 at 10:31 +0530, Ankit Nautiyal wrote:
> Add a helper to compute vblank time needed for transmitting specific
> DisplayPort SDPs like PPS, GAMUT_METADATA, and VSC_EXT. Latency is
> based on line count per packet type.
>
> This will be used to ensure adequate guardband when features like
> DSC/HDR
> are enabled.
>
> Bspec: 70151
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 36
> +++++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> 2 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7059d55687cf..3f2c319e3d6f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6990,3 +6990,39 @@ int intel_dp_compute_config_late(struct
> intel_encoder *encoder,
>
> return 0;
> }
> +
> +static
> +int intel_dp_get_lines_for_sdp(u32 type)
> +{
> + switch (type) {
> + case DP_SDP_VSC_EXT_VESA:
> + case DP_SDP_VSC_EXT_CEA:
> + return 10;
> + case HDMI_PACKET_TYPE_GAMUT_METADATA:
> + return 8;
> + case DP_SDP_PPS:
> + return 6;
I found value 7 in the Bspec you are referring in commit message?
BR,
Jouni Högander
> + default:
> + break;
> + }
> +
> + return 0;
> +}
> +
> +int intel_dp_sdp_min_guardband(const struct intel_crtc_state
> *crtc_state,
> + bool assume_all_enabled)
> +{
> + int sdp_guardband = 0;
> +
> + if (assume_all_enabled ||
> + crtc_state->infoframes.enable &
> +
> intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
> + sdp_guardband = max(sdp_guardband,
> +
> intel_dp_get_lines_for_sdp(HDMI_PACKET_TYPE_GAMUT_METADATA));
> +
> + if (assume_all_enabled ||
> + crtc_state->dsc.compression_enable)
> + sdp_guardband = max(sdp_guardband,
> intel_dp_get_lines_for_sdp(DP_SDP_PPS));
> +
> + return sdp_guardband;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 281ced3a3b39..7ee5aeb28fe2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -221,5 +221,7 @@ bool intel_dp_in_hdr_mode(const struct
> drm_connector_state *conn_state);
> int intel_dp_compute_config_late(struct intel_encoder *encoder,
> struct intel_crtc_state
> *crtc_state,
> struct drm_connector_state
> *conn_state);
> +int intel_dp_sdp_min_guardband(const struct intel_crtc_state
> *crtc_state,
> + bool assume_all_enabled);
>
> #endif /* __INTEL_DP_H__ */
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/5] drm/i915/dp: Add helper to get min sdp guardband
2025-10-17 10:50 ` Hogander, Jouni
@ 2025-10-17 11:07 ` Nautiyal, Ankit K
0 siblings, 0 replies; 25+ messages in thread
From: Nautiyal, Ankit K @ 2025-10-17 11:07 UTC (permalink / raw)
To: Hogander, Jouni, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
On 10/17/2025 4:20 PM, Hogander, Jouni wrote:
> On Fri, 2025-10-17 at 10:31 +0530, Ankit Nautiyal wrote:
>> Add a helper to compute vblank time needed for transmitting specific
>> DisplayPort SDPs like PPS, GAMUT_METADATA, and VSC_EXT. Latency is
>> based on line count per packet type.
>>
>> This will be used to ensure adequate guardband when features like
>> DSC/HDR
>> are enabled.
>>
>> Bspec: 70151
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 36
>> +++++++++++++++++++++++++
>> drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
>> 2 files changed, 38 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 7059d55687cf..3f2c319e3d6f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -6990,3 +6990,39 @@ int intel_dp_compute_config_late(struct
>> intel_encoder *encoder,
>>
>> return 0;
>> }
>> +
>> +static
>> +int intel_dp_get_lines_for_sdp(u32 type)
>> +{
>> + switch (type) {
>> + case DP_SDP_VSC_EXT_VESA:
>> + case DP_SDP_VSC_EXT_CEA:
>> + return 10;
>> + case HDMI_PACKET_TYPE_GAMUT_METADATA:
>> + return 8;
>> + case DP_SDP_PPS:
>> + return 6;
> I found value 7 in the Bspec you are referring in commit message?
Hmm this indeed is 7, seems I misread the spec. Thanks for catching this!
Regards,
Ankit
>
> BR,
>
> Jouni Högander
>
>> + default:
>> + break;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +int intel_dp_sdp_min_guardband(const struct intel_crtc_state
>> *crtc_state,
>> + bool assume_all_enabled)
>> +{
>> + int sdp_guardband = 0;
>> +
>> + if (assume_all_enabled ||
>> + crtc_state->infoframes.enable &
>> +
>> intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
>> + sdp_guardband = max(sdp_guardband,
>> +
>> intel_dp_get_lines_for_sdp(HDMI_PACKET_TYPE_GAMUT_METADATA));
>> +
>> + if (assume_all_enabled ||
>> + crtc_state->dsc.compression_enable)
>> + sdp_guardband = max(sdp_guardband,
>> intel_dp_get_lines_for_sdp(DP_SDP_PPS));
>> +
>> + return sdp_guardband;
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
>> b/drivers/gpu/drm/i915/display/intel_dp.h
>> index 281ced3a3b39..7ee5aeb28fe2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -221,5 +221,7 @@ bool intel_dp_in_hdr_mode(const struct
>> drm_connector_state *conn_state);
>> int intel_dp_compute_config_late(struct intel_encoder *encoder,
>> struct intel_crtc_state
>> *crtc_state,
>> struct drm_connector_state
>> *conn_state);
>> +int intel_dp_sdp_min_guardband(const struct intel_crtc_state
>> *crtc_state,
>> + bool assume_all_enabled);
>>
>> #endif /* __INTEL_DP_H__ */
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/5] drm/i915/psr: Add helper to get min psr guardband
2025-10-17 10:15 ` Hogander, Jouni
2025-10-17 10:30 ` Hogander, Jouni
@ 2025-10-17 11:11 ` Nautiyal, Ankit K
2025-10-17 11:30 ` Hogander, Jouni
1 sibling, 1 reply; 25+ messages in thread
From: Nautiyal, Ankit K @ 2025-10-17 11:11 UTC (permalink / raw)
To: Hogander, Jouni, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
On 10/17/2025 3:45 PM, Hogander, Jouni wrote:
> On Fri, 2025-10-17 at 12:58 +0300, Hogander, Jouni wrote:
>> On Fri, 2025-10-17 at 15:07 +0530, Nautiyal, Ankit K wrote:
>>> On 10/17/2025 2:37 PM, Hogander, Jouni wrote:
>>>> On Fri, 2025-10-17 at 10:31 +0530, Ankit Nautiyal wrote:
>>>>> Introduce a helper to compute the max link wake latency when
>>>>> using
>>>>> Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.
>>>>>
>>>>> This will be used to compute the minimum guardband so that the
>>>>> link
>>>>> wake
>>>>> latencies are accounted and these features work smoothly for
>>>>> higher
>>>>> refresh rate panels.
>>>>>
>>>>> Bspec: 70151, 71477
>>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
>>>>> drivers/gpu/drm/i915/display/intel_psr.h | 1 +
>>>>> 2 files changed, 13 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> b/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> index 703e5f6af04c..a8303b669853 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> @@ -4416,3 +4416,15 @@ void
>>>>> intel_psr_compute_config_late(struct
>>>>> intel_dp *intel_dp,
>>>>>
>>>>> intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
>>>>> }
>>>>> +
>>>>> +int intel_psr_min_guardband(struct intel_crtc_state
>>>>> *crtc_state)
>>>>> +{
>>>>> + struct intel_display *display =
>>>>> to_intel_display(crtc_state);
>>>>> + int auxless_wake_lines = crtc_state-
>>>>>> alpm_state.aux_less_wake_lines;
>>>>> + int wake_lines = DISPLAY_VER(display) < 20 ?
>>>>> + psr2_block_count_lines(crtc_state-
>>>>>> alpm_state.io_wake_lines,
>>>>> + crtc_state-
>>>>>> alpm_state.fast_wake_lines) :
>>>>> + crtc_state->alpm_state.io_wake_lines;
>>>>> +
>>>>> + return max(auxless_wake_lines, wake_lines);
>>>> hmm, now if you add:
>>>>
>>>> if (crtc_state->req_psr2_sdp_prior_scanline)
>>>> psr_min_guardband++;
>>> I did not get this part. Do we need to account for 1 more wakelines
>>> if
>>> this flag is set?
>> If you look at how that flag affects vblank check in
>> intel_psr_compute_config_late:
>>
>> ...
>> static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state
>> *crtc_state,
>> int vblank,
>> int wake_lines)
>> {
>> if (crtc_state->req_psr2_sdp_prior_scanline)
>> vblank -= 1;
>> ...
>>
>> So to take that into account when calculating minimum guardband
>> needed
>> by PSR you need to increase by one. Same goes with SCL:
>>
>> ...
>> int scl = _intel_psr_min_set_context_latency(crtc_state,
>>
>> needs_panel_replay,
>>
>> needs_sel_update);
>> vblank -= scl;
>> ...
>>
>> You are already partially taking into account PSR needs when
>> calculating optimized guardband except these two lines which are
>> needed
>> conditionally.
>>
>> Also intel_psr_compute_config is run at this point -> you know which
>> one to use: auxless wake time or aux wake time. no need to use max()
>> with them. Just choose the one which is relevant.
>>
>> With these changes you could drop intel_psr_compute_config_late as
>> vblank would be long enough for PSR mode computed by
>> intel_psr_compute_config, no?
> Ok, noticed now this in the last patch:
>
> ...
> crtc_state->vrr.guardband = min(guardband, intel_vrr_max_guardband(crtc_state));
> ...
>
> So if we need to fall back to intel_vrr_max_guardband we need to have
> that intel_psr_compute_config_late.
>
> Anyways I think you need to take into account that
> req_psr2_sdp_prior_scanline and _intel_psr_min_set_context_latency in
> intel_psr_min_guardband.
Hmm I think you are right, we need to account for
req_psr2_sdp_prior_scanline here.
But for SCL I still think we do not need to account in wakelines as we
are already accounting in intel_vrr_max_guardband() which calls :
intel_vrr_max_vblank_guardband(const struct intel_crtc_state
*crtc_state) { struct intel_display *display =
to_intel_display(crtc_state); const struct drm_display_mode
*adjusted_mode = &crtc_state->hw.adjusted_mode; return
crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay -
crtc_state->set_context_latency - intel_vrr_extra_vblank_delay(display); }
Regards,
Ankit
>
> BR,
>
> Jouni Högander
>> BR,
>>
>> Jouni Högander
>>
>>
>>> What we want to do is to check for min guardband for
>>> panel_replay/sel_update based on the required wakelines.
>>>
>>> Whether we can use the auxless_wake_lines and wake_lines as
>>> computed
>>> above to estimate the max wakelines or instead we should use
>>> functions
>>> from alpm.c :
>>>
>>> io_buffer_wake_time() and _lnl_compute_aux_less_wake_time() to get
>>> the
>>> worst case wakelines.
>>>
>>>
>>>> Whatever is the PSR mode it can be enabled what comes to vblank
>>>> restrictions and you can drop psr_compute_config_late?
>>>
>>> I think we cannot drop the psr_compute_config_late as it checks
>>> whether
>>> the actual guardband is enough for PSR features.
>>>
>>> intel_psr_min_guardband() is used along with other features to have
>>> an estimate on the guardband that works for all cases, without a
>>> need
>>> to change the guardband.
>>> It is bounded by the vblank length available
>>>
>>> Regards,
>>>
>>> Ankit
>>>
>>>> BR,
>>>>
>>>> Jouni Högander
>>>>
>>>>> +}
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
>>>>> b/drivers/gpu/drm/i915/display/intel_psr.h
>>>>> index b17ce312dc37..620b35928832 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_psr.h
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
>>>>> @@ -85,5 +85,6 @@ bool intel_psr_needs_alpm_aux_less(struct
>>>>> intel_dp
>>>>> *intel_dp,
>>>>> const struct
>>>>> intel_crtc_state
>>>>> *crtc_state);
>>>>> void intel_psr_compute_config_late(struct intel_dp *intel_dp,
>>>>> struct intel_crtc_state
>>>>> *crtc_state);
>>>>> +int intel_psr_min_guardband(struct intel_crtc_state
>>>>> *crtc_state);
>>>>>
>>>>> #endif /* __INTEL_PSR_H__ */
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/5] drm/i915/psr: Add helper to get min psr guardband
2025-10-17 11:11 ` Nautiyal, Ankit K
@ 2025-10-17 11:30 ` Hogander, Jouni
0 siblings, 0 replies; 25+ messages in thread
From: Hogander, Jouni @ 2025-10-17 11:30 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
On Fri, 2025-10-17 at 16:41 +0530, Nautiyal, Ankit K wrote:
>
> On 10/17/2025 3:45 PM, Hogander, Jouni wrote:
> > On Fri, 2025-10-17 at 12:58 +0300, Hogander, Jouni wrote:
> > > On Fri, 2025-10-17 at 15:07 +0530, Nautiyal, Ankit K wrote:
> > > > On 10/17/2025 2:37 PM, Hogander, Jouni wrote:
> > > > > On Fri, 2025-10-17 at 10:31 +0530, Ankit Nautiyal wrote:
> > > > > > Introduce a helper to compute the max link wake latency
> > > > > > when
> > > > > > using
> > > > > > Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF
> > > > > > features.
> > > > > >
> > > > > > This will be used to compute the minimum guardband so that
> > > > > > the
> > > > > > link
> > > > > > wake
> > > > > > latencies are accounted and these features work smoothly
> > > > > > for
> > > > > > higher
> > > > > > refresh rate panels.
> > > > > >
> > > > > > Bspec: 70151, 71477
> > > > > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/display/intel_psr.c | 12
> > > > > > ++++++++++++
> > > > > > drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> > > > > > 2 files changed, 13 insertions(+)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > index 703e5f6af04c..a8303b669853 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > @@ -4416,3 +4416,15 @@ void
> > > > > > intel_psr_compute_config_late(struct
> > > > > > intel_dp *intel_dp,
> > > > > >
> > > > > > intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
> > > > > > }
> > > > > > +
> > > > > > +int intel_psr_min_guardband(struct intel_crtc_state
> > > > > > *crtc_state)
> > > > > > +{
> > > > > > + struct intel_display *display =
> > > > > > to_intel_display(crtc_state);
> > > > > > + int auxless_wake_lines = crtc_state-
> > > > > > > alpm_state.aux_less_wake_lines;
> > > > > > + int wake_lines = DISPLAY_VER(display) < 20 ?
> > > > > > +
> > > > > > psr2_block_count_lines(crtc_state-
> > > > > > > alpm_state.io_wake_lines,
> > > > > > + crtc_state
> > > > > > -
> > > > > > > alpm_state.fast_wake_lines) :
> > > > > > + crtc_state-
> > > > > > >alpm_state.io_wake_lines;
> > > > > > +
> > > > > > + return max(auxless_wake_lines, wake_lines);
> > > > > hmm, now if you add:
> > > > >
> > > > > if (crtc_state->req_psr2_sdp_prior_scanline)
> > > > > psr_min_guardband++;
> > > > I did not get this part. Do we need to account for 1 more
> > > > wakelines
> > > > if
> > > > this flag is set?
> > > If you look at how that flag affects vblank check in
> > > intel_psr_compute_config_late:
> > >
> > > ...
> > > static bool _wake_lines_fit_into_vblank(const struct
> > > intel_crtc_state
> > > *crtc_state,
> > > int vblank,
> > > int wake_lines)
> > > {
> > > if (crtc_state->req_psr2_sdp_prior_scanline)
> > > vblank -= 1;
> > > ...
> > >
> > > So to take that into account when calculating minimum guardband
> > > needed
> > > by PSR you need to increase by one. Same goes with SCL:
> > >
> > > ...
> > > int scl = _intel_psr_min_set_context_latency(crtc_state,
> > >
> > > needs_panel_replay,
> > >
> > > needs_sel_update);
> > > vblank -= scl;
> > > ...
> > >
> > > You are already partially taking into account PSR needs when
> > > calculating optimized guardband except these two lines which are
> > > needed
> > > conditionally.
> > >
> > > Also intel_psr_compute_config is run at this point -> you know
> > > which
> > > one to use: auxless wake time or aux wake time. no need to use
> > > max()
> > > with them. Just choose the one which is relevant.
> > >
> > > With these changes you could drop intel_psr_compute_config_late
> > > as
> > > vblank would be long enough for PSR mode computed by
> > > intel_psr_compute_config, no?
> > Ok, noticed now this in the last patch:
> >
> > ...
> > crtc_state->vrr.guardband = min(guardband,
> > intel_vrr_max_guardband(crtc_state));
> > ...
> >
> > So if we need to fall back to intel_vrr_max_guardband we need to
> > have
> > that intel_psr_compute_config_late.
> >
> > Anyways I think you need to take into account that
> > req_psr2_sdp_prior_scanline and _intel_psr_min_set_context_latency
> > in
> > intel_psr_min_guardband.
>
>
> Hmm I think you are right, we need to account for
> req_psr2_sdp_prior_scanline here.
>
> But for SCL I still think we do not need to account in wakelines as
> we
> are already accounting in intel_vrr_max_guardband() which calls :
>
> intel_vrr_max_vblank_guardband(const struct intel_crtc_state
> *crtc_state) { struct intel_display *display =
> to_intel_display(crtc_state); const struct drm_display_mode
> *adjusted_mode = &crtc_state->hw.adjusted_mode; return
> crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay -
> crtc_state->set_context_latency -
> intel_vrr_extra_vblank_delay(display); }
intel_vrr_max_guardband is used only if it's smaller than what is
computed by intel_vrr_compute_optimized_guardband. I.e. case where
intel_psr_min_guard rules used guardband it is not taken into account
unless you add it into intel_psr_min_guard.
BR,
Jouni Högander
>
> Regards,
>
> Ankit
>
> >
> > BR,
> >
> > Jouni Högander
> > > BR,
> > >
> > > Jouni Högander
> > >
> > >
> > > > What we want to do is to check for min guardband for
> > > > panel_replay/sel_update based on the required wakelines.
> > > >
> > > > Whether we can use the auxless_wake_lines and wake_lines as
> > > > computed
> > > > above to estimate the max wakelines or instead we should use
> > > > functions
> > > > from alpm.c :
> > > >
> > > > io_buffer_wake_time() and _lnl_compute_aux_less_wake_time() to
> > > > get
> > > > the
> > > > worst case wakelines.
> > > >
> > > >
> > > > > Whatever is the PSR mode it can be enabled what comes to
> > > > > vblank
> > > > > restrictions and you can drop psr_compute_config_late?
> > > >
> > > > I think we cannot drop the psr_compute_config_late as it checks
> > > > whether
> > > > the actual guardband is enough for PSR features.
> > > >
> > > > intel_psr_min_guardband() is used along with other features to
> > > > have
> > > > an estimate on the guardband that works for all cases, without
> > > > a
> > > > need
> > > > to change the guardband.
> > > > It is bounded by the vblank length available
> > > >
> > > > Regards,
> > > >
> > > > Ankit
> > > >
> > > > > BR,
> > > > >
> > > > > Jouni Högander
> > > > >
> > > > > > +}
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > > index b17ce312dc37..620b35928832 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > > @@ -85,5 +85,6 @@ bool intel_psr_needs_alpm_aux_less(struct
> > > > > > intel_dp
> > > > > > *intel_dp,
> > > > > > const struct
> > > > > > intel_crtc_state
> > > > > > *crtc_state);
> > > > > > void intel_psr_compute_config_late(struct intel_dp
> > > > > > *intel_dp,
> > > > > > struct intel_crtc_state
> > > > > > *crtc_state);
> > > > > > +int intel_psr_min_guardband(struct intel_crtc_state
> > > > > > *crtc_state);
> > > > > >
> > > > > > #endif /* __INTEL_PSR_H__ */
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 3/5] drm/i915/dp: Check if guardband can accommodate sdp latencies
2025-10-17 5:02 ` [PATCH 3/5] drm/i915/dp: Check if guardband can accommodate sdp latencies Ankit Nautiyal
@ 2025-10-17 12:02 ` Ville Syrjälä
0 siblings, 0 replies; 25+ messages in thread
From: Ville Syrjälä @ 2025-10-17 12:02 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe
On Fri, Oct 17, 2025 at 10:32:00AM +0530, Ankit Nautiyal wrote:
> Check if guardband is sufficient for all DP SDP latencies.
> If its not, fail .compute_config_late().
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3f2c319e3d6f..8ae99cee79d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -93,6 +93,7 @@
> #include "intel_psr.h"
> #include "intel_quirks.h"
> #include "intel_tc.h"
> +#include "intel_vblank.h"
> #include "intel_vdsc.h"
> #include "intel_vrr.h"
>
> @@ -6980,14 +6981,35 @@ void intel_dp_mst_resume(struct intel_display *display)
> }
> }
>
> +static
> +int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + int guardband = intel_crtc_vblank_length(crtc_state);
In theory we might have enough legacy TG vblank but not VRR guardband
(I suppose that can only happen on ICL/TGL due to the pipeline full
limit) so I was pondering whether we might need to check both. But I
think this is fine. We would just fail when trying to enable VRR in
those cases, but without VRR enabled we can still light up th display.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + int min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);
> +
> + if (guardband < min_sdp_guardband) {
> + drm_dbg_kms(display->drm, "guardband %d < min sdp guardband %d\n",
> + guardband, min_sdp_guardband);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> int intel_dp_compute_config_late(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> + int ret;
>
> intel_psr_compute_config_late(intel_dp, crtc_state);
>
> + ret = intel_dp_sdp_compute_config_late(crtc_state);
> + if (ret)
> + return ret;
> +
> return 0;
> }
>
> --
> 2.45.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/5] drm/i915/vrr: Use the min static optimized guardband
2025-10-17 5:02 ` [PATCH 4/5] drm/i915/vrr: Use the min static optimized guardband Ankit Nautiyal
@ 2025-10-17 12:06 ` Ville Syrjälä
0 siblings, 0 replies; 25+ messages in thread
From: Ville Syrjälä @ 2025-10-17 12:06 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe
On Fri, Oct 17, 2025 at 10:32:01AM +0530, Ankit Nautiyal wrote:
> In the current VRR implementation, vrr.vmin and vrr.guardband are set such
> that they do not need to change when switching from fixed refresh rate to
> variable refresh rate. Specifically, vrr.guardband is always set to match
> the vblank length. This approach works for most cases, but not for LRR,
> where the guardband would need to change while the VRR timing generator is
> still active.
>
> With the VRR TG always active, live updates to guardband are unsafe and not
> recommended. To ensure hardware safety, guardband was moved out of the
> !fastset block, meaning any change now requires a full modeset.
> This breaks seamless LRR switching, which was previously supported.
>
> Since the problem arises from guardband being matched to the vblank length,
> solution is to use a minimal, sufficient static value, instead. So we use a
> static guardband defined during mode-set that fits within the smallest
> expected vblank and remains unchanged in case of features like LRR where
> vtotal changes. To compute this minimum guardband we take into account
> latencies/delays due to different features as mentioned in the Bspec.
>
> Introduce a helper to compute the minimal sufficient guardband.
> On platforms where the VRR timing generator is always ON, we optimize the
> guardband regardless of whether the display is operating in fixed or
> variable refresh rate mode.
>
> v2:
> - Use max of sagv latency and skl_wm_latency(1) for PM delay
> computation. (Ville)
> - Avoid guardband optimization for HDMI for now. (Ville)
> - Allow guardband optimization only for platforms with
> intel_vrr_always_use_vrr_tg = true. (Ville)
> - Add comments for PM delay and a #TODO note for HDMI.
>
> Bspec: 70151
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 62 +++++++++++++++++++++++-
> 1 file changed, 60 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 597008a6c744..cd7bed358984 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -6,12 +6,16 @@
>
> #include <drm/drm_print.h>
>
> +#include "intel_crtc.h"
> #include "intel_de.h"
> #include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> +#include "intel_psr.h"
> #include "intel_vrr.h"
> #include "intel_vrr_regs.h"
> +#include "skl_prefill.h"
> +#include "skl_watermark.h"
>
> #define FIXED_POINT_PRECISION 100
> #define CMRR_PRECISION_TOLERANCE 10
> @@ -433,17 +437,71 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
> intel_vrr_max_vblank_guardband(crtc_state));
> }
>
> +static
> +int intel_vrr_compute_optimized_guardband(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct skl_prefill_ctx prefill_ctx;
> + int prefill_min_guardband;
> + int prefill_latency_us;
> + int guardband = 0;
> +
> + skl_prefill_init_worst(&prefill_ctx, crtc_state);
> +
> + /*
> + * The SoC power controller runs SAGV mutually exclusive with package C states,
> + * so the max of package C and SAGV latencies is used to compute the min prefill guardband.
> + * PM delay = max(sagv_latency, pkgc_max_latency (highest enabled wm level 1 and up))
> + */
> + prefill_latency_us = max(display->sagv.block_time_us,
> + skl_watermark_max_latency(display, 1));
> + prefill_min_guardband =
> + skl_prefill_min_guardband(&prefill_ctx,
> + crtc_state,
> + prefill_latency_us);
This could be just
guardband = skl_prefill_min_guardband(...)
and you can then get rid of the prefill_min_guardband
variable as well.
But in general lgtm
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> +
> + if (intel_crtc_has_dp_encoder(crtc_state)) {
> + guardband = max(guardband, intel_psr_min_guardband(crtc_state));
> + guardband = max(guardband, intel_dp_sdp_min_guardband(crtc_state, true));
> + }
> +
> + guardband = max(guardband, prefill_min_guardband);
> +
> + return guardband;
> +}
> +
> +static bool intel_vrr_use_optimized_guardband(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> +
> + /*
> + * #TODO: Enable optimized guardband for HDMI
> + * For HDMI lot of infoframes are transmitted a line or two after vsync.
> + * Since with optimized guardband the double bufferring point is at delayed vblank,
> + * we need to ensure that vsync happens after delayed vblank for the HDMI case.
> + */
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> + return false;
> +
> + return intel_vrr_always_use_vrr_tg(display);
> +}
> +
> void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> + int guardband;
>
> if (!intel_vrr_possible(crtc_state))
> return;
>
> - crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
> - intel_vrr_max_guardband(crtc_state));
> + if (intel_vrr_use_optimized_guardband(crtc_state))
> + guardband = intel_vrr_compute_optimized_guardband(crtc_state);
> + else
> + guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;
> +
> + crtc_state->vrr.guardband = min(guardband, intel_vrr_max_guardband(crtc_state));
>
> if (intel_vrr_always_use_vrr_tg(display)) {
> adjusted_mode->crtc_vblank_start =
> --
> 2.45.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 5/5] drm/i915/vrr: Use optimized guardband whenever VRR TG is active
2025-10-17 5:02 ` [PATCH 5/5] drm/i915/vrr: Use optimized guardband whenever VRR TG is active Ankit Nautiyal
@ 2025-10-17 12:13 ` Ville Syrjälä
0 siblings, 0 replies; 25+ messages in thread
From: Ville Syrjälä @ 2025-10-17 12:13 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe
On Fri, Oct 17, 2025 at 10:32:02AM +0530, Ankit Nautiyal wrote:
> Currently the guardband is optimized only for platforms where the
> VRR timing generator is always ON.
>
> Extend the usage of optimized guardband to other platforms only when the
> VRR is enabled.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index cd7bed358984..eb5aa0d7fc49 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -483,7 +483,7 @@ static bool intel_vrr_use_optimized_guardband(const struct intel_crtc_state *crt
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> return false;
>
> - return intel_vrr_always_use_vrr_tg(display);
> + return intel_vrr_always_use_vrr_tg(display) || crtc_state->vrr.enable;
I was going to say this is fine, and I guess it kinda is because
intel_pipe_config_compare() will allow fastsets with a change in
guardband on !intel_vrr_always_use_vrr_tg() platforms. But I
don't think there's any real reason to compute the guardband
differently between vrr.enable==true vs. vrr.enable==false.
So I'm thinking we should just 'return true' unconditionally
here.
> }
>
> void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
> --
> 2.45.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 4/5] drm/i915/vrr: Use the min static optimized guardband
2025-10-17 12:34 [PATCH 0/5] Optimize vrr.guardband Ankit Nautiyal
@ 2025-10-17 12:35 ` Ankit Nautiyal
0 siblings, 0 replies; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-17 12:35 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, jouni.hogander, Ankit Nautiyal
In the current VRR implementation, vrr.vmin and vrr.guardband are set such
that they do not need to change when switching from fixed refresh rate to
variable refresh rate. Specifically, vrr.guardband is always set to match
the vblank length. This approach works for most cases, but not for LRR,
where the guardband would need to change while the VRR timing generator is
still active.
With the VRR TG always active, live updates to guardband are unsafe and not
recommended. To ensure hardware safety, guardband was moved out of the
!fastset block, meaning any change now requires a full modeset.
This breaks seamless LRR switching, which was previously supported.
Since the problem arises from guardband being matched to the vblank length,
solution is to use a minimal, sufficient static value, instead. So we use a
static guardband defined during mode-set that fits within the smallest
expected vblank and remains unchanged in case of features like LRR where
vtotal changes. To compute this minimum guardband we take into account
latencies/delays due to different features as mentioned in the Bspec.
Introduce a helper to compute the minimal sufficient guardband.
On platforms where the VRR timing generator is always ON, we optimize the
guardband regardless of whether the display is operating in fixed or
variable refresh rate mode.
v2:
- Use max of sagv latency and skl_wm_latency(1) for PM delay
computation. (Ville)
- Avoid guardband optimization for HDMI for now. (Ville)
- Allow guardband optimization only for platforms with
intel_vrr_always_use_vrr_tg = true. (Ville)
- Add comments for PM delay and a #TODO note for HDMI.
v3: Drop the variable prefill_min_guardband. (Ville)
Bspec: 70151
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 58 +++++++++++++++++++++++-
1 file changed, 56 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 597008a6c744..3da84a247193 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -10,8 +10,11 @@
#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
+#include "intel_psr.h"
#include "intel_vrr.h"
#include "intel_vrr_regs.h"
+#include "skl_prefill.h"
+#include "skl_watermark.h"
#define FIXED_POINT_PRECISION 100
#define CMRR_PRECISION_TOLERANCE 10
@@ -433,17 +436,68 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
intel_vrr_max_vblank_guardband(crtc_state));
}
+static
+int intel_vrr_compute_optimized_guardband(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct skl_prefill_ctx prefill_ctx;
+ int prefill_latency_us;
+ int guardband = 0;
+
+ skl_prefill_init_worst(&prefill_ctx, crtc_state);
+
+ /*
+ * The SoC power controller runs SAGV mutually exclusive with package C states,
+ * so the max of package C and SAGV latencies is used to compute the min prefill guardband.
+ * PM delay = max(sagv_latency, pkgc_max_latency (highest enabled wm level 1 and up))
+ */
+ prefill_latency_us = max(display->sagv.block_time_us,
+ skl_watermark_max_latency(display, 1));
+
+ guardband = skl_prefill_min_guardband(&prefill_ctx,
+ crtc_state,
+ prefill_latency_us);
+
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
+ guardband = max(guardband, intel_psr_min_guardband(crtc_state));
+ guardband = max(guardband, intel_dp_sdp_min_guardband(crtc_state, true));
+ }
+
+ return guardband;
+}
+
+static bool intel_vrr_use_optimized_guardband(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ /*
+ * #TODO: Enable optimized guardband for HDMI
+ * For HDMI lot of infoframes are transmitted a line or two after vsync.
+ * Since with optimized guardband the double bufferring point is at delayed vblank,
+ * we need to ensure that vsync happens after delayed vblank for the HDMI case.
+ */
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return false;
+
+ return intel_vrr_always_use_vrr_tg(display);
+}
+
void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
+ int guardband;
if (!intel_vrr_possible(crtc_state))
return;
- crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
- intel_vrr_max_guardband(crtc_state));
+ if (intel_vrr_use_optimized_guardband(crtc_state))
+ guardband = intel_vrr_compute_optimized_guardband(crtc_state);
+ else
+ guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;
+
+ crtc_state->vrr.guardband = min(guardband, intel_vrr_max_guardband(crtc_state));
if (intel_vrr_always_use_vrr_tg(display)) {
adjusted_mode->crtc_vblank_start =
--
2.45.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* ✗ Xe.CI.Full: failure for Optimize vrr.guardband (rev3)
2025-10-17 5:01 [PATCH 0/5] Optimize vrr.guardband Ankit Nautiyal
` (7 preceding siblings ...)
2025-10-17 6:14 ` ✓ Xe.CI.BAT: success " Patchwork
@ 2025-10-18 4:53 ` Patchwork
8 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-10-18 4:53 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 58043 bytes --]
== Series Details ==
Series: Optimize vrr.guardband (rev3)
URL : https://patchwork.freedesktop.org/series/155979/
State : failure
== Summary ==
CI Bug Log - changes from xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb_FULL -> xe-pw-155979v3_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-155979v3_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-155979v3_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-155979v3_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@xe_pm@s3-mocs:
- shard-adlp: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-8/igt@xe_pm@s3-mocs.html
Known issues
------------
Here are the changes found in xe-pw-155979v3_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][2] ([Intel XE#2327]) +1 other test skip
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-adlp: NOTRUN -> [SKIP][3] ([Intel XE#619])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
- shard-adlp: NOTRUN -> [SKIP][4] ([Intel XE#607]) +1 other test skip
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-9/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0:
- shard-adlp: NOTRUN -> [SKIP][5] ([Intel XE#1124]) +7 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-adlp: NOTRUN -> [SKIP][6] ([Intel XE#316]) +3 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-8/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-adlp: NOTRUN -> [DMESG-FAIL][7] ([Intel XE#4543]) +7 other tests dmesg-fail
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][8] ([Intel XE#1124]) +3 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-7/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-dg2-set2: NOTRUN -> [SKIP][9] ([Intel XE#610])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][10] ([Intel XE#1124]) +3 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-464/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
- shard-bmg: NOTRUN -> [SKIP][11] ([Intel XE#2314] / [Intel XE#2894])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
* igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p:
- shard-adlp: NOTRUN -> [SKIP][12] ([Intel XE#2191])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-9/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-1-displays-1920x1080p:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][13] ([Intel XE#2594])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-464/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-2-displays-2160x1440p:
- shard-adlp: NOTRUN -> [SKIP][14] ([Intel XE#367]) +3 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html
* igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
- shard-adlp: NOTRUN -> [SKIP][15] ([Intel XE#455] / [Intel XE#787]) +31 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][16] ([Intel XE#455] / [Intel XE#787]) +9 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-4.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][17] ([Intel XE#2907])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-c-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][18] ([Intel XE#787]) +47 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-c-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#3432])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
- shard-adlp: NOTRUN -> [SKIP][20] ([Intel XE#2907]) +1 other test skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][21] ([Intel XE#787]) +34 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#2887]) +3 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-adlp: NOTRUN -> [SKIP][23] ([Intel XE#373]) +8 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_color@ctm-0-50:
- shard-adlp: NOTRUN -> [SKIP][24] ([Intel XE#306]) +2 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-9/igt@kms_chamelium_color@ctm-0-50.html
* igt@kms_chamelium_hpd@hdmi-hpd-fast:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#2252]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_chamelium_hpd@hdmi-hpd-fast.html
* igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
- shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#373]) +5 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#2390])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-dg2-set2: NOTRUN -> [SKIP][28] ([Intel XE#307])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-adlp: NOTRUN -> [SKIP][29] ([Intel XE#308]) +1 other test skip
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-8/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#2321])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
- shard-adlp: NOTRUN -> [SKIP][31] ([Intel XE#309]) +4 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_display_modes@extended-mode-basic:
- shard-adlp: NOTRUN -> [SKIP][32] ([Intel XE#4302])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-9/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#2244]) +1 other test skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-adlp: NOTRUN -> [SKIP][34] ([Intel XE#776])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@display-2x:
- shard-adlp: NOTRUN -> [SKIP][35] ([Intel XE#702])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@kms_feature_discovery@display-2x.html
* igt@kms_feature_discovery@display-4x:
- shard-adlp: NOTRUN -> [SKIP][36] ([Intel XE#1138])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-8/igt@kms_feature_discovery@display-4x.html
* igt@kms_feature_discovery@psr2:
- shard-adlp: NOTRUN -> [SKIP][37] ([Intel XE#1135])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop:
- shard-adlp: NOTRUN -> [SKIP][38] ([Intel XE#310]) +6 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
- shard-bmg: [PASS][39] -> [SKIP][40] ([Intel XE#2316])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-2/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-bmg: NOTRUN -> [SKIP][41] ([Intel XE#2316]) +1 other test skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
- shard-adlp: NOTRUN -> [DMESG-WARN][42] ([Intel XE#4543]) +3 other tests dmesg-warn
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-adlp: [PASS][43] -> [DMESG-WARN][44] ([Intel XE#4543]) +5 other tests dmesg-warn
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-2/igt@kms_flip@flip-vs-suspend-interruptible.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-9/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
- shard-adlp: [PASS][45] -> [DMESG-WARN][46] ([Intel XE#2953] / [Intel XE#4173])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-1/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
- shard-bmg: NOTRUN -> [SKIP][47] ([Intel XE#2380]) +1 other test skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-adlp: NOTRUN -> [DMESG-FAIL][48] ([Intel XE#4543] / [Intel XE#4921]) +1 other test dmesg-fail
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen:
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#2311]) +4 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][50] ([Intel XE#5390])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#5427])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][52] ([Intel XE#2312]) +8 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render:
- shard-dg2-set2: NOTRUN -> [SKIP][53] ([Intel XE#651]) +10 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-fullscreen:
- shard-adlp: NOTRUN -> [SKIP][54] ([Intel XE#651]) +14 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-adlp: NOTRUN -> [SKIP][55] ([Intel XE#653]) +11 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@plane-fbc-rte:
- shard-adlp: NOTRUN -> [SKIP][56] ([Intel XE#1158])
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][57] ([Intel XE#653]) +8 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt:
- shard-adlp: NOTRUN -> [SKIP][58] ([Intel XE#656]) +41 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt:
- shard-bmg: NOTRUN -> [SKIP][59] ([Intel XE#2313]) +4 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_joiner@basic-big-joiner:
- shard-adlp: NOTRUN -> [SKIP][60] ([Intel XE#346])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_joiner@basic-big-joiner.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-adlp: NOTRUN -> [SKIP][61] ([Intel XE#3012])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_joiner@basic-force-big-joiner.html
- shard-bmg: [PASS][62] -> [SKIP][63] ([Intel XE#3012])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-2/igt@kms_joiner@basic-force-big-joiner.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_joiner@basic-max-non-joiner:
- shard-adlp: NOTRUN -> [SKIP][64] ([Intel XE#4298])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@kms_joiner@basic-max-non-joiner.html
* igt@kms_joiner@invalid-modeset-big-joiner:
- shard-dg2-set2: NOTRUN -> [SKIP][65] ([Intel XE#346])
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@kms_joiner@invalid-modeset-big-joiner.html
* igt@kms_panel_fitting@legacy:
- shard-adlp: NOTRUN -> [SKIP][66] ([Intel XE#455]) +24 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_multiple@2x-tiling-x:
- shard-adlp: NOTRUN -> [SKIP][67] ([Intel XE#4596])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_plane_multiple@2x-tiling-x.html
* igt@kms_plane_multiple@2x-tiling-y:
- shard-bmg: NOTRUN -> [SKIP][68] ([Intel XE#4596])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-y.html
* igt@kms_pm_backlight@fade:
- shard-adlp: NOTRUN -> [SKIP][69] ([Intel XE#870])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-9/igt@kms_pm_backlight@fade.html
* igt@kms_pm_dc@dc5-retention-flops:
- shard-adlp: NOTRUN -> [SKIP][70] ([Intel XE#3309])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@kms_pm_dc@dc5-retention-flops.html
* igt@kms_pm_dc@dc6-psr:
- shard-bmg: NOTRUN -> [SKIP][71] ([Intel XE#2392])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_rpm@drm-resources-equal:
- shard-adlp: NOTRUN -> [SKIP][72] ([Intel XE#6070])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-8/igt@kms_pm_rpm@drm-resources-equal.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-adlp: NOTRUN -> [SKIP][73] ([Intel XE#836])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area:
- shard-dg2-set2: NOTRUN -> [SKIP][74] ([Intel XE#1406] / [Intel XE#1489])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf:
- shard-adlp: NOTRUN -> [SKIP][75] ([Intel XE#1406] / [Intel XE#1489]) +5 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
- shard-bmg: NOTRUN -> [SKIP][76] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-p010:
- shard-adlp: NOTRUN -> [SKIP][77] ([Intel XE#1122] / [Intel XE#1406] / [Intel XE#5580]) +1 other test skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@fbc-psr-dpms:
- shard-bmg: NOTRUN -> [SKIP][78] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_psr@fbc-psr-dpms.html
* igt@kms_psr@psr-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][79] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +5 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-464/igt@kms_psr@psr-dpms.html
* igt@kms_psr@psr-sprite-plane-onoff:
- shard-adlp: NOTRUN -> [SKIP][80] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +12 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_psr@psr-sprite-plane-onoff.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-adlp: NOTRUN -> [SKIP][81] ([Intel XE#1406] / [Intel XE#2939] / [Intel XE#5585])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-9/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-dg2-set2: NOTRUN -> [SKIP][82] ([Intel XE#1127])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
- shard-adlp: NOTRUN -> [SKIP][83] ([Intel XE#3414]) +1 other test skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-dg2-set2: NOTRUN -> [SKIP][84] ([Intel XE#3414])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_setmode@invalid-clone-single-crtc:
- shard-bmg: [PASS][85] -> [SKIP][86] ([Intel XE#1435])
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-2/igt@kms_setmode@invalid-clone-single-crtc.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_setmode@invalid-clone-single-crtc.html
* igt@kms_vrr@cmrr:
- shard-adlp: NOTRUN -> [SKIP][87] ([Intel XE#2168])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@kms_vrr@cmrr.html
* igt@kms_vrr@flip-basic-fastset:
- shard-dg2-set2: NOTRUN -> [SKIP][88] ([Intel XE#455]) +2 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@negative-basic:
- shard-bmg: NOTRUN -> [SKIP][89] ([Intel XE#1499])
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_vrr@negative-basic.html
* igt@xe_ccs@ctrl-surf-copy-new-ctx:
- shard-adlp: NOTRUN -> [SKIP][90] ([Intel XE#455] / [Intel XE#488] / [Intel XE#5607])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-9/igt@xe_ccs@ctrl-surf-copy-new-ctx.html
* igt@xe_compute_preempt@compute-preempt-many:
- shard-adlp: NOTRUN -> [SKIP][91] ([Intel XE#6360]) +1 other test skip
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@xe_compute_preempt@compute-preempt-many.html
* igt@xe_create@create-big-vram:
- shard-adlp: NOTRUN -> [SKIP][92] ([Intel XE#1062])
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@xe_create@create-big-vram.html
* igt@xe_create@multigpu-create-massive-size:
- shard-dg2-set2: NOTRUN -> [SKIP][93] ([Intel XE#944])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-464/igt@xe_create@multigpu-create-massive-size.html
* igt@xe_eu_stall@blocking-read:
- shard-adlp: NOTRUN -> [SKIP][94] ([Intel XE#5626]) +1 other test skip
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@xe_eu_stall@blocking-read.html
* igt@xe_eudebug@basic-vm-access-parameters-userptr-faultable:
- shard-adlp: NOTRUN -> [SKIP][95] ([Intel XE#4837] / [Intel XE#5565]) +14 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-8/igt@xe_eudebug@basic-vm-access-parameters-userptr-faultable.html
* igt@xe_eudebug@vma-ufence-faultable:
- shard-dg2-set2: NOTRUN -> [SKIP][96] ([Intel XE#4837]) +3 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@xe_eudebug@vma-ufence-faultable.html
* igt@xe_eudebug_online@basic-breakpoint:
- shard-bmg: NOTRUN -> [SKIP][97] ([Intel XE#4837]) +3 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@xe_eudebug_online@basic-breakpoint.html
* igt@xe_evict@evict-beng-cm-threads-small:
- shard-adlp: NOTRUN -> [SKIP][98] ([Intel XE#261]) +3 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-9/igt@xe_evict@evict-beng-cm-threads-small.html
* igt@xe_evict@evict-beng-large-external-cm:
- shard-adlp: NOTRUN -> [SKIP][99] ([Intel XE#261] / [Intel XE#5564]) +1 other test skip
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@xe_evict@evict-beng-large-external-cm.html
* igt@xe_evict@evict-beng-small:
- shard-adlp: NOTRUN -> [SKIP][100] ([Intel XE#261] / [Intel XE#5564] / [Intel XE#688]) +3 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@xe_evict@evict-beng-small.html
* igt@xe_evict@evict-mixed-threads-small:
- shard-adlp: NOTRUN -> [SKIP][101] ([Intel XE#261] / [Intel XE#688])
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@xe_evict@evict-mixed-threads-small.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate:
- shard-adlp: NOTRUN -> [SKIP][102] ([Intel XE#1392] / [Intel XE#5575]) +6 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue:
- shard-dg2-set2: NOTRUN -> [SKIP][103] ([Intel XE#1392])
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue.html
* igt@xe_exec_basic@multigpu-no-exec-null:
- shard-bmg: NOTRUN -> [SKIP][104] ([Intel XE#2322])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@xe_exec_basic@multigpu-no-exec-null.html
* igt@xe_exec_fault_mode@invalid-va-scratch-nopagefault:
- shard-adlp: NOTRUN -> [SKIP][105] ([Intel XE#288] / [Intel XE#5561]) +28 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@xe_exec_fault_mode@invalid-va-scratch-nopagefault.html
* igt@xe_exec_fault_mode@twice-userptr-prefetch:
- shard-dg2-set2: NOTRUN -> [SKIP][106] ([Intel XE#288]) +8 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@xe_exec_fault_mode@twice-userptr-prefetch.html
* igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence:
- shard-adlp: NOTRUN -> [SKIP][107] ([Intel XE#2360]) +1 other test skip
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-8/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html
* igt@xe_exec_system_allocator@process-many-execqueues-mmap-nomemset:
- shard-adlp: NOTRUN -> [SKIP][108] ([Intel XE#4915]) +280 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-9/igt@xe_exec_system_allocator@process-many-execqueues-mmap-nomemset.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge:
- shard-bmg: NOTRUN -> [SKIP][109] ([Intel XE#4943]) +5 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-remap-eocheck:
- shard-dg2-set2: NOTRUN -> [SKIP][110] ([Intel XE#4915]) +88 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-remap-eocheck.html
* igt@xe_module_load@force-load:
- shard-adlp: NOTRUN -> [SKIP][111] ([Intel XE#378] / [Intel XE#5612])
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@xe_module_load@force-load.html
* igt@xe_oa@oa-unit-exclusive-stream-sample-oa:
- shard-dg2-set2: NOTRUN -> [SKIP][112] ([Intel XE#3573]) +4 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html
* igt@xe_oa@rc6-disable:
- shard-adlp: NOTRUN -> [SKIP][113] ([Intel XE#3573]) +5 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@xe_oa@rc6-disable.html
* igt@xe_pat@display-vs-wb-transient:
- shard-adlp: NOTRUN -> [SKIP][114] ([Intel XE#1337] / [Intel XE#5572])
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@xe_pat@display-vs-wb-transient.html
* igt@xe_pm@d3cold-mocs:
- shard-dg2-set2: NOTRUN -> [SKIP][115] ([Intel XE#2284])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-464/igt@xe_pm@d3cold-mocs.html
* igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_render0:
- shard-adlp: NOTRUN -> [TIMEOUT][116] ([Intel XE#5213]) +1 other test timeout
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-8/igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_render0.html
* igt@xe_pmu@fn-engine-activity-sched-if-idle:
- shard-bmg: NOTRUN -> [DMESG-WARN][117] ([Intel XE#3876])
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-7/igt@xe_pmu@fn-engine-activity-sched-if-idle.html
- shard-dg2-set2: NOTRUN -> [SKIP][118] ([Intel XE#4650])
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@xe_pmu@fn-engine-activity-sched-if-idle.html
* igt@xe_pxp@pxp-termination-key-update-post-termination-irq:
- shard-adlp: NOTRUN -> [SKIP][119] ([Intel XE#4733] / [Intel XE#5594]) +3 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@xe_pxp@pxp-termination-key-update-post-termination-irq.html
* igt@xe_query@multigpu-query-invalid-extension:
- shard-adlp: NOTRUN -> [SKIP][120] ([Intel XE#944]) +2 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-9/igt@xe_query@multigpu-query-invalid-extension.html
#### Possible fixes ####
* igt@kms_addfb_basic@no-handle:
- shard-adlp: [DMESG-WARN][121] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][122] +4 other tests pass
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-8/igt@kms_addfb_basic@no-handle.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@kms_addfb_basic@no-handle.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-bmg: [FAIL][123] ([Intel XE#3718] / [Intel XE#6078]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-1/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-c-dp-2:
- shard-bmg: [FAIL][125] ([Intel XE#6078]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-dp-2.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-1/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-dp-2.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
- shard-dg2-set2: [INCOMPLETE][127] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6:
- shard-dg2-set2: [INCOMPLETE][129] ([Intel XE#1727] / [Intel XE#3113]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-bmg: [DMESG-WARN][131] ([Intel XE#5354]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-4/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-5/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-bmg: [FAIL][133] ([Intel XE#4633]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-lnl: [FAIL][135] ([Intel XE#301]) -> [PASS][136] +3 other tests pass
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend@d-hdmi-a1:
- shard-adlp: [DMESG-WARN][137] ([Intel XE#4543]) -> [PASS][138] +7 other tests pass
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-1/igt@kms_flip@flip-vs-suspend@d-hdmi-a1.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_flip@flip-vs-suspend@d-hdmi-a1.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [SKIP][139] ([Intel XE#1503]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-5/igt@kms_hdr@invalid-hdr.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-4/igt@kms_hdr@invalid-hdr.html
* igt@kms_vrr@cmrr@pipe-a-edp-1:
- shard-lnl: [FAIL][141] ([Intel XE#4459]) -> [PASS][142] +1 other test pass
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-lnl-5/igt@kms_vrr@cmrr@pipe-a-edp-1.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-lnl-7/igt@kms_vrr@cmrr@pipe-a-edp-1.html
* {igt@xe_configfs@ctx-restore-post-bb}:
- shard-bmg: [DMESG-WARN][143] ([Intel XE#3428]) -> [PASS][144]
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-6/igt@xe_configfs@ctx-restore-post-bb.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-8/igt@xe_configfs@ctx-restore-post-bb.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-bmg: [INCOMPLETE][145] ([Intel XE#6321]) -> [PASS][146]
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-8/igt@xe_evict@evict-mixed-many-threads-small.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-2/igt@xe_evict@evict-mixed-many-threads-small.html
* {igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma}:
- shard-lnl: [FAIL][147] ([Intel XE#5625]) -> [PASS][148]
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-lnl-4/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-lnl-3/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
* igt@xe_module_load@load:
- shard-adlp: ([PASS][149], [PASS][150], [SKIP][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156], [PASS][157], [PASS][158], [PASS][159], [PASS][160], [PASS][161], [PASS][162]) ([Intel XE#378] / [Intel XE#5612]) -> ([PASS][163], [PASS][164], [PASS][165], [PASS][166], [PASS][167], [PASS][168], [PASS][169], [PASS][170], [PASS][171], [PASS][172], [PASS][173], [PASS][174], [PASS][175], [PASS][176], [PASS][177])
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-2/igt@xe_module_load@load.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-2/igt@xe_module_load@load.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-8/igt@xe_module_load@load.html
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-2/igt@xe_module_load@load.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-8/igt@xe_module_load@load.html
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-6/igt@xe_module_load@load.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-6/igt@xe_module_load@load.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-6/igt@xe_module_load@load.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-8/igt@xe_module_load@load.html
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-8/igt@xe_module_load@load.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-9/igt@xe_module_load@load.html
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-1/igt@xe_module_load@load.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-1/igt@xe_module_load@load.html
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-1/igt@xe_module_load@load.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-9/igt@xe_module_load@load.html
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@xe_module_load@load.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-9/igt@xe_module_load@load.html
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@xe_module_load@load.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@xe_module_load@load.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@xe_module_load@load.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@xe_module_load@load.html
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-6/igt@xe_module_load@load.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-9/igt@xe_module_load@load.html
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-8/igt@xe_module_load@load.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-8/igt@xe_module_load@load.html
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-8/igt@xe_module_load@load.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-2/igt@xe_module_load@load.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-2/igt@xe_module_load@load.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-2/igt@xe_module_load@load.html
* igt@xe_pmu@gt-frequency:
- shard-dg2-set2: [FAIL][178] ([Intel XE#4819]) -> [PASS][179] +1 other test pass
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-dg2-435/igt@xe_pmu@gt-frequency.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-464/igt@xe_pmu@gt-frequency.html
* igt@xe_waitfence@exec_queue-reset-wait:
- shard-dg2-set2: [INCOMPLETE][180] -> [PASS][181]
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-dg2-434/igt@xe_waitfence@exec_queue-reset-wait.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-464/igt@xe_waitfence@exec_queue-reset-wait.html
#### Warnings ####
* igt@kms_content_protection@atomic-dpms:
- shard-dg2-set2: [INCOMPLETE][182] ([Intel XE#4907]) -> [FAIL][183] ([Intel XE#1178]) +1 other test fail
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-dg2-466/igt@kms_content_protection@atomic-dpms.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-dg2-432/igt@kms_content_protection@atomic-dpms.html
* igt@kms_flip@flip-vs-panning-vs-hang@d-hdmi-a1:
- shard-adlp: [TIMEOUT][184] ([Intel XE#4543]) -> [DMESG-WARN][185] ([Intel XE#4543]) +1 other test dmesg-warn
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-2/igt@kms_flip@flip-vs-panning-vs-hang@d-hdmi-a1.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-8/igt@kms_flip@flip-vs-panning-vs-hang@d-hdmi-a1.html
* igt@kms_flip@flip-vs-rmfb:
- shard-adlp: [DMESG-WARN][186] ([Intel XE#4543] / [Intel XE#5208]) -> [DMESG-WARN][187] ([Intel XE#5208])
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-2/igt@kms_flip@flip-vs-rmfb.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-8/igt@kms_flip@flip-vs-rmfb.html
* igt@kms_flip@flip-vs-suspend:
- shard-adlp: [DMESG-WARN][188] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543]) -> [DMESG-WARN][189] ([Intel XE#2953] / [Intel XE#4173])
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-1/igt@kms_flip@flip-vs-suspend.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-adlp-1/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt:
- shard-bmg: [SKIP][190] ([Intel XE#2311]) -> [SKIP][191] ([Intel XE#2312]) +1 other test skip
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt:
- shard-bmg: [SKIP][192] ([Intel XE#5390]) -> [SKIP][193] ([Intel XE#2312])
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-blt:
- shard-bmg: [SKIP][194] ([Intel XE#2313]) -> [SKIP][195] ([Intel XE#2312]) +2 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-blt.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][196] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][197] ([Intel XE#3544])
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][198] ([Intel XE#2509]) -> [SKIP][199] ([Intel XE#2426])
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-bmg: [ABORT][200] ([Intel XE#5466] / [Intel XE#5530]) -> [ABORT][201] ([Intel XE#4917] / [Intel XE#5466] / [Intel XE#5530])
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-1/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/shard-bmg-4/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1062]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1062
[Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
[Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
[Intel XE#1158]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1158
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
[Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2594
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
[Intel XE#2939]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2939
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3428
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
[Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
[Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4819
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/488
[Intel XE#4907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4907
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
[Intel XE#4921]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4921
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
[Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
[Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
[Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5427
[Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
[Intel XE#5503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5503
[Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
[Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
[Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
[Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
[Intel XE#5572]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5572
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5580]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5580
[Intel XE#5585]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5585
[Intel XE#5594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5594
[Intel XE#5607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5607
[Intel XE#5612]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5612
[Intel XE#5624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5624
[Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
[Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
[Intel XE#5745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5745
[Intel XE#6032]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6032
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#6070]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6070
[Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
[Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
[Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
[Intel XE#6259]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6259
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6313
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6360
[Intel XE#6376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6376
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#702]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/702
[Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb -> xe-pw-155979v3
IGT_8589: 8589
xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb: b4f191dddaee9ae1871344e3dabcc40f2f14d2cb
xe-pw-155979v3: 155979v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v3/index.html
[-- Attachment #2: Type: text/html, Size: 66687 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2025-10-18 4:53 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-17 5:01 [PATCH 0/5] Optimize vrr.guardband Ankit Nautiyal
2025-10-17 5:01 ` [PATCH 1/5] drm/i915/psr: Add helper to get min psr guardband Ankit Nautiyal
2025-10-17 9:07 ` Hogander, Jouni
2025-10-17 9:30 ` Hogander, Jouni
2025-10-17 9:41 ` Nautiyal, Ankit K
2025-10-17 9:37 ` Nautiyal, Ankit K
2025-10-17 9:58 ` Hogander, Jouni
2025-10-17 10:15 ` Hogander, Jouni
2025-10-17 10:30 ` Hogander, Jouni
2025-10-17 11:11 ` Nautiyal, Ankit K
2025-10-17 11:30 ` Hogander, Jouni
2025-10-17 5:01 ` [PATCH 2/5] drm/i915/dp: Add helper to get min sdp guardband Ankit Nautiyal
2025-10-17 10:50 ` Hogander, Jouni
2025-10-17 11:07 ` Nautiyal, Ankit K
2025-10-17 5:02 ` [PATCH 3/5] drm/i915/dp: Check if guardband can accommodate sdp latencies Ankit Nautiyal
2025-10-17 12:02 ` Ville Syrjälä
2025-10-17 5:02 ` [PATCH 4/5] drm/i915/vrr: Use the min static optimized guardband Ankit Nautiyal
2025-10-17 12:06 ` Ville Syrjälä
2025-10-17 5:02 ` [PATCH 5/5] drm/i915/vrr: Use optimized guardband whenever VRR TG is active Ankit Nautiyal
2025-10-17 12:13 ` Ville Syrjälä
2025-10-17 5:23 ` ✓ CI.KUnit: success for Optimize vrr.guardband (rev3) Patchwork
2025-10-17 5:38 ` ✗ CI.checksparse: warning " Patchwork
2025-10-17 6:14 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-18 4:53 ` ✗ Xe.CI.Full: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2025-10-17 12:34 [PATCH 0/5] Optimize vrr.guardband Ankit Nautiyal
2025-10-17 12:35 ` [PATCH 4/5] drm/i915/vrr: Use the min static optimized guardband Ankit Nautiyal
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