* [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
@ 2025-10-23 8:16 Ankit Nautiyal
2025-10-23 10:35 ` Hogander, Jouni
` (4 more replies)
0 siblings, 5 replies; 16+ messages in thread
From: Ankit Nautiyal @ 2025-10-23 8:16 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jouni.hogander, ville.syrjala, Ankit Nautiyal
Currently the EMP_AS_SDP_TL is set to vrr.vsync_start which is
incorrect.
As per Bspec:71197 the transmission line must be within the SCL +
guardband region. Before guardband optimization, guradband was same as
vblank length so EMP_AS_SDP_TL set with vrr.sync_start was falling in
this region and it was not giving an issue.
Now with optimized guardband, this is falling outside the SCL +
guardband region and since the same transmission line is used by VSC SDP
also, this results in PSR timeout issues.
Further restrictions on the position of the transmission line:
For DP/eDP, if there is a set context latency (SCL) window, then it
cannot be the first line of SCL
For DP/eDP, if there is no SCL window, then it cannot be the first line of
the Delayed V. Blank
Fix the EMP_AS_SDP_TL to VTOTAL - (delayed vblank_start - SCL + 1)
Internally the HW computes the value as VTOTAL - EMP_AS_SDP_TL.
Fixes: e1123e617e51 ("drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDP")
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 92fb72b56f16..dd81d2133aba 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -655,18 +655,24 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
{
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+ int transmission_line;
/*
* For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
* double buffering point and transmission line for VRR packets for
* HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
* Since currently we support VRR only for DP/eDP, so this is programmed
- * to for Adaptive Sync SDP to Vsync start.
+ * for Adaptive Sync SDP.
*/
- if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
+ if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) {
+ transmission_line = adjusted_mode->crtc_vtotal - (adjusted_mode->crtc_vblank_start -
+ crtc_state->set_context_latency +
+ 1);
intel_de_write(display,
EMP_AS_SDP_TL(display, cpu_transcoder),
- EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
+ EMP_AS_SDP_DB_TL(transmission_line));
+ }
}
static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
--
2.45.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
2025-10-23 8:16 [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP Ankit Nautiyal
@ 2025-10-23 10:35 ` Hogander, Jouni
2025-10-23 12:04 ` Ville Syrjälä
` (3 subsequent siblings)
4 siblings, 0 replies; 16+ messages in thread
From: Hogander, Jouni @ 2025-10-23 10:35 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
On Thu, 2025-10-23 at 13:46 +0530, Ankit Nautiyal wrote:
> Currently the EMP_AS_SDP_TL is set to vrr.vsync_start which is
> incorrect.
>
> As per Bspec:71197 the transmission line must be within the SCL +
> guardband region. Before guardband optimization, guradband was same
> as
> vblank length so EMP_AS_SDP_TL set with vrr.sync_start was falling in
> this region and it was not giving an issue.
>
> Now with optimized guardband, this is falling outside the SCL +
> guardband region and since the same transmission line is used by VSC
> SDP
> also, this results in PSR timeout issues.
>
> Further restrictions on the position of the transmission line:
> For DP/eDP, if there is a set context latency (SCL) window, then it
> cannot be the first line of SCL
> For DP/eDP, if there is no SCL window, then it cannot be the first
> line of
> the Delayed V. Blank
>
> Fix the EMP_AS_SDP_TL to VTOTAL - (delayed vblank_start - SCL + 1)
> Internally the HW computes the value as VTOTAL - EMP_AS_SDP_TL.
>
> Fixes: e1123e617e51 ("drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS
> SDP")
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 92fb72b56f16..dd81d2133aba 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -655,18 +655,24 @@ void
> intel_vrr_set_db_point_and_transmission_line(const struct
> intel_crtc_state
> {
> struct intel_display *display =
> to_intel_display(crtc_state);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> + int transmission_line;
>
> /*
> * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for
> programming
> * double buffering point and transmission line for VRR
> packets for
> * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
> * Since currently we support VRR only for DP/eDP, so this
> is programmed
> - * to for Adaptive Sync SDP to Vsync start.
> + * for Adaptive Sync SDP.
> */
> - if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display)
> >= 20)
> + if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display)
> >= 20) {
> + transmission_line = adjusted_mode->crtc_vtotal -
> (adjusted_mode->crtc_vblank_start -
> +
> crtc_state->set_context_latency +
> +
> 1);
> intel_de_write(display,
> EMP_AS_SDP_TL(display,
> cpu_transcoder),
> - EMP_AS_SDP_DB_TL(crtc_state-
> >vrr.vsync_start));
> + EMP_AS_SDP_DB_TL(transmission_line));
> + }
> }
>
> static int intel_vrr_hw_vmin(const struct intel_crtc_state
> *crtc_state)
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
2025-10-23 8:16 [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP Ankit Nautiyal
2025-10-23 10:35 ` Hogander, Jouni
@ 2025-10-23 12:04 ` Ville Syrjälä
2025-10-23 12:27 ` Nautiyal, Ankit K
2025-10-23 12:22 ` ✓ CI.KUnit: success for " Patchwork
` (2 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Ville Syrjälä @ 2025-10-23 12:04 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe, jouni.hogander
On Thu, Oct 23, 2025 at 01:46:14PM +0530, Ankit Nautiyal wrote:
> Currently the EMP_AS_SDP_TL is set to vrr.vsync_start which is
> incorrect.
>
> As per Bspec:71197 the transmission line must be within the SCL +
> guardband region. Before guardband optimization, guradband was same as
> vblank length so EMP_AS_SDP_TL set with vrr.sync_start was falling in
> this region and it was not giving an issue.
>
> Now with optimized guardband, this is falling outside the SCL +
> guardband region and since the same transmission line is used by VSC SDP
> also, this results in PSR timeout issues.
>
> Further restrictions on the position of the transmission line:
> For DP/eDP, if there is a set context latency (SCL) window, then it
> cannot be the first line of SCL
> For DP/eDP, if there is no SCL window, then it cannot be the first line of
> the Delayed V. Blank
>
> Fix the EMP_AS_SDP_TL to VTOTAL - (delayed vblank_start - SCL + 1)
> Internally the HW computes the value as VTOTAL - EMP_AS_SDP_TL.
>
> Fixes: e1123e617e51 ("drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDP")
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 92fb72b56f16..dd81d2133aba 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -655,18 +655,24 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
> {
> struct intel_display *display = to_intel_display(crtc_state);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> + int transmission_line;
>
> /*
> * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
> * double buffering point and transmission line for VRR packets for
> * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
> * Since currently we support VRR only for DP/eDP, so this is programmed
> - * to for Adaptive Sync SDP to Vsync start.
> + * for Adaptive Sync SDP.
> */
> - if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
> + if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) {
> + transmission_line = adjusted_mode->crtc_vtotal - (adjusted_mode->crtc_vblank_start -
> + crtc_state->set_context_latency +
> + 1);
> intel_de_write(display,
> EMP_AS_SDP_TL(display, cpu_transcoder),
> - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> + EMP_AS_SDP_DB_TL(transmission_line));
> + }
Pretty sure we are expected to send it at vsync_start.
> }
>
> static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
> --
> 2.45.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ CI.KUnit: success for drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
2025-10-23 8:16 [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP Ankit Nautiyal
2025-10-23 10:35 ` Hogander, Jouni
2025-10-23 12:04 ` Ville Syrjälä
@ 2025-10-23 12:22 ` Patchwork
2025-10-23 13:05 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-23 20:28 ` ✗ Xe.CI.Full: failure " Patchwork
4 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2025-10-23 12:22 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-xe
== Series Details ==
Series: drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
URL : https://patchwork.freedesktop.org/series/156410/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[12:21:25] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:21:29] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:22:00] Starting KUnit Kernel (1/1)...
[12:22:00] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:22:00] ================== guc_buf (11 subtests) ===================
[12:22:00] [PASSED] test_smallest
[12:22:00] [PASSED] test_largest
[12:22:00] [PASSED] test_granular
[12:22:00] [PASSED] test_unique
[12:22:00] [PASSED] test_overlap
[12:22:00] [PASSED] test_reusable
[12:22:00] [PASSED] test_too_big
[12:22:00] [PASSED] test_flush
[12:22:00] [PASSED] test_lookup
[12:22:00] [PASSED] test_data
[12:22:00] [PASSED] test_class
[12:22:00] ===================== [PASSED] guc_buf =====================
[12:22:00] =================== guc_dbm (7 subtests) ===================
[12:22:00] [PASSED] test_empty
[12:22:00] [PASSED] test_default
[12:22:00] ======================== test_size ========================
[12:22:00] [PASSED] 4
[12:22:00] [PASSED] 8
[12:22:00] [PASSED] 32
[12:22:00] [PASSED] 256
[12:22:00] ==================== [PASSED] test_size ====================
[12:22:00] ======================= test_reuse ========================
[12:22:00] [PASSED] 4
[12:22:00] [PASSED] 8
[12:22:00] [PASSED] 32
[12:22:00] [PASSED] 256
[12:22:00] =================== [PASSED] test_reuse ====================
[12:22:00] =================== test_range_overlap ====================
[12:22:00] [PASSED] 4
[12:22:00] [PASSED] 8
[12:22:00] [PASSED] 32
[12:22:00] [PASSED] 256
[12:22:00] =============== [PASSED] test_range_overlap ================
[12:22:00] =================== test_range_compact ====================
[12:22:00] [PASSED] 4
[12:22:00] [PASSED] 8
[12:22:00] [PASSED] 32
[12:22:00] [PASSED] 256
[12:22:00] =============== [PASSED] test_range_compact ================
[12:22:00] ==================== test_range_spare =====================
[12:22:00] [PASSED] 4
[12:22:00] [PASSED] 8
[12:22:00] [PASSED] 32
[12:22:00] [PASSED] 256
[12:22:00] ================ [PASSED] test_range_spare =================
[12:22:00] ===================== [PASSED] guc_dbm =====================
[12:22:00] =================== guc_idm (6 subtests) ===================
[12:22:00] [PASSED] bad_init
[12:22:00] [PASSED] no_init
[12:22:00] [PASSED] init_fini
[12:22:00] [PASSED] check_used
[12:22:00] [PASSED] check_quota
[12:22:00] [PASSED] check_all
[12:22:00] ===================== [PASSED] guc_idm =====================
[12:22:00] ================== no_relay (3 subtests) ===================
[12:22:00] [PASSED] xe_drops_guc2pf_if_not_ready
[12:22:00] [PASSED] xe_drops_guc2vf_if_not_ready
[12:22:00] [PASSED] xe_rejects_send_if_not_ready
[12:22:00] ==================== [PASSED] no_relay =====================
[12:22:00] ================== pf_relay (14 subtests) ==================
[12:22:00] [PASSED] pf_rejects_guc2pf_too_short
[12:22:00] [PASSED] pf_rejects_guc2pf_too_long
[12:22:00] [PASSED] pf_rejects_guc2pf_no_payload
[12:22:00] [PASSED] pf_fails_no_payload
[12:22:00] [PASSED] pf_fails_bad_origin
[12:22:00] [PASSED] pf_fails_bad_type
[12:22:00] [PASSED] pf_txn_reports_error
[12:22:00] [PASSED] pf_txn_sends_pf2guc
[12:22:00] [PASSED] pf_sends_pf2guc
[12:22:00] [SKIPPED] pf_loopback_nop
[12:22:00] [SKIPPED] pf_loopback_echo
[12:22:00] [SKIPPED] pf_loopback_fail
[12:22:00] [SKIPPED] pf_loopback_busy
[12:22:00] [SKIPPED] pf_loopback_retry
[12:22:00] ==================== [PASSED] pf_relay =====================
[12:22:00] ================== vf_relay (3 subtests) ===================
[12:22:00] [PASSED] vf_rejects_guc2vf_too_short
[12:22:00] [PASSED] vf_rejects_guc2vf_too_long
[12:22:00] [PASSED] vf_rejects_guc2vf_no_payload
[12:22:00] ==================== [PASSED] vf_relay =====================
[12:22:00] ===================== lmtt (1 subtest) =====================
[12:22:00] ======================== test_ops =========================
[12:22:00] [PASSED] 2-level
[12:22:00] [PASSED] multi-level
[12:22:00] ==================== [PASSED] test_ops =====================
[12:22:00] ====================== [PASSED] lmtt =======================
[12:22:00] ================= pf_service (11 subtests) =================
[12:22:00] [PASSED] pf_negotiate_any
[12:22:00] [PASSED] pf_negotiate_base_match
[12:22:00] [PASSED] pf_negotiate_base_newer
[12:22:00] [PASSED] pf_negotiate_base_next
[12:22:00] [SKIPPED] pf_negotiate_base_older
[12:22:00] [PASSED] pf_negotiate_base_prev
[12:22:00] [PASSED] pf_negotiate_latest_match
[12:22:00] [PASSED] pf_negotiate_latest_newer
[12:22:00] [PASSED] pf_negotiate_latest_next
[12:22:00] [SKIPPED] pf_negotiate_latest_older
[12:22:00] [SKIPPED] pf_negotiate_latest_prev
[12:22:00] =================== [PASSED] pf_service ====================
[12:22:00] ================= xe_guc_g2g (2 subtests) ==================
[12:22:00] ============== xe_live_guc_g2g_kunit_default ==============
[12:22:00] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[12:22:00] ============== xe_live_guc_g2g_kunit_allmem ===============
[12:22:00] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[12:22:00] =================== [SKIPPED] xe_guc_g2g ===================
[12:22:00] =================== xe_mocs (2 subtests) ===================
[12:22:00] ================ xe_live_mocs_kernel_kunit ================
[12:22:00] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[12:22:00] ================ xe_live_mocs_reset_kunit =================
[12:22:00] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[12:22:00] ==================== [SKIPPED] xe_mocs =====================
[12:22:00] ================= xe_migrate (2 subtests) ==================
[12:22:00] ================= xe_migrate_sanity_kunit =================
[12:22:00] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[12:22:00] ================== xe_validate_ccs_kunit ==================
[12:22:00] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[12:22:00] =================== [SKIPPED] xe_migrate ===================
[12:22:00] ================== xe_dma_buf (1 subtest) ==================
[12:22:00] ==================== xe_dma_buf_kunit =====================
[12:22:00] ================ [SKIPPED] xe_dma_buf_kunit ================
[12:22:00] =================== [SKIPPED] xe_dma_buf ===================
[12:22:00] ================= xe_bo_shrink (1 subtest) =================
[12:22:00] =================== xe_bo_shrink_kunit ====================
[12:22:00] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[12:22:00] ================== [SKIPPED] xe_bo_shrink ==================
[12:22:00] ==================== xe_bo (2 subtests) ====================
[12:22:00] ================== xe_ccs_migrate_kunit ===================
[12:22:00] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[12:22:00] ==================== xe_bo_evict_kunit ====================
[12:22:00] =============== [SKIPPED] xe_bo_evict_kunit ================
[12:22:00] ===================== [SKIPPED] xe_bo ======================
[12:22:00] ==================== args (11 subtests) ====================
[12:22:00] [PASSED] count_args_test
[12:22:00] [PASSED] call_args_example
[12:22:00] [PASSED] call_args_test
[12:22:00] [PASSED] drop_first_arg_example
[12:22:00] [PASSED] drop_first_arg_test
[12:22:00] [PASSED] first_arg_example
[12:22:00] [PASSED] first_arg_test
[12:22:00] [PASSED] last_arg_example
[12:22:00] [PASSED] last_arg_test
[12:22:00] [PASSED] pick_arg_example
[12:22:00] [PASSED] sep_comma_example
[12:22:00] ====================== [PASSED] args =======================
[12:22:00] =================== xe_pci (3 subtests) ====================
[12:22:00] ==================== check_graphics_ip ====================
[12:22:00] [PASSED] 12.00 Xe_LP
[12:22:00] [PASSED] 12.10 Xe_LP+
[12:22:00] [PASSED] 12.55 Xe_HPG
[12:22:00] [PASSED] 12.60 Xe_HPC
[12:22:00] [PASSED] 12.70 Xe_LPG
[12:22:00] [PASSED] 12.71 Xe_LPG
[12:22:00] [PASSED] 12.74 Xe_LPG+
[12:22:00] [PASSED] 20.01 Xe2_HPG
[12:22:00] [PASSED] 20.02 Xe2_HPG
[12:22:00] [PASSED] 20.04 Xe2_LPG
[12:22:00] [PASSED] 30.00 Xe3_LPG
[12:22:00] [PASSED] 30.01 Xe3_LPG
[12:22:00] [PASSED] 30.03 Xe3_LPG
[12:22:00] [PASSED] 30.04 Xe3_LPG
[12:22:00] [PASSED] 30.05 Xe3_LPG
[12:22:00] [PASSED] 35.11 Xe3p_XPC
[12:22:00] ================ [PASSED] check_graphics_ip ================
[12:22:00] ===================== check_media_ip ======================
[12:22:00] [PASSED] 12.00 Xe_M
[12:22:00] [PASSED] 12.55 Xe_HPM
[12:22:00] [PASSED] 13.00 Xe_LPM+
[12:22:00] [PASSED] 13.01 Xe2_HPM
[12:22:00] [PASSED] 20.00 Xe2_LPM
[12:22:00] [PASSED] 30.00 Xe3_LPM
[12:22:00] [PASSED] 30.02 Xe3_LPM
[12:22:00] [PASSED] 35.00 Xe3p_LPM
[12:22:00] [PASSED] 35.03 Xe3p_HPM
[12:22:00] ================= [PASSED] check_media_ip ==================
[12:22:00] =================== check_platform_desc ===================
[12:22:00] [PASSED] 0x9A60 (TIGERLAKE)
[12:22:00] [PASSED] 0x9A68 (TIGERLAKE)
[12:22:00] [PASSED] 0x9A70 (TIGERLAKE)
[12:22:00] [PASSED] 0x9A40 (TIGERLAKE)
[12:22:00] [PASSED] 0x9A49 (TIGERLAKE)
[12:22:00] [PASSED] 0x9A59 (TIGERLAKE)
[12:22:00] [PASSED] 0x9A78 (TIGERLAKE)
[12:22:00] [PASSED] 0x9AC0 (TIGERLAKE)
[12:22:00] [PASSED] 0x9AC9 (TIGERLAKE)
[12:22:00] [PASSED] 0x9AD9 (TIGERLAKE)
[12:22:00] [PASSED] 0x9AF8 (TIGERLAKE)
[12:22:00] [PASSED] 0x4C80 (ROCKETLAKE)
[12:22:00] [PASSED] 0x4C8A (ROCKETLAKE)
[12:22:00] [PASSED] 0x4C8B (ROCKETLAKE)
[12:22:00] [PASSED] 0x4C8C (ROCKETLAKE)
[12:22:00] [PASSED] 0x4C90 (ROCKETLAKE)
[12:22:00] [PASSED] 0x4C9A (ROCKETLAKE)
[12:22:00] [PASSED] 0x4680 (ALDERLAKE_S)
[12:22:00] [PASSED] 0x4682 (ALDERLAKE_S)
[12:22:00] [PASSED] 0x4688 (ALDERLAKE_S)
[12:22:00] [PASSED] 0x468A (ALDERLAKE_S)
[12:22:00] [PASSED] 0x468B (ALDERLAKE_S)
[12:22:00] [PASSED] 0x4690 (ALDERLAKE_S)
[12:22:00] [PASSED] 0x4692 (ALDERLAKE_S)
[12:22:00] [PASSED] 0x4693 (ALDERLAKE_S)
[12:22:00] [PASSED] 0x46A0 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x46A1 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x46A2 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x46A3 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x46A6 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x46A8 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x46AA (ALDERLAKE_P)
[12:22:00] [PASSED] 0x462A (ALDERLAKE_P)
[12:22:00] [PASSED] 0x4626 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x4628 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x46B0 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x46B1 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x46B2 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x46B3 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x46C0 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x46C1 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x46C2 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x46C3 (ALDERLAKE_P)
[12:22:00] [PASSED] 0x46D0 (ALDERLAKE_N)
[12:22:00] [PASSED] 0x46D1 (ALDERLAKE_N)
[12:22:00] [PASSED] 0x46D2 (ALDERLAKE_N)
[12:22:00] [PASSED] 0x46D3 (ALDERLAKE_N)
[12:22:00] [PASSED] 0x46D4 (ALDERLAKE_N)
[12:22:00] [PASSED] 0xA721 (ALDERLAKE_P)
[12:22:00] [PASSED] 0xA7A1 (ALDERLAKE_P)
[12:22:00] [PASSED] 0xA7A9 (ALDERLAKE_P)
[12:22:00] [PASSED] 0xA7AC (ALDERLAKE_P)
[12:22:00] [PASSED] 0xA7AD (ALDERLAKE_P)
[12:22:00] [PASSED] 0xA720 (ALDERLAKE_P)
[12:22:00] [PASSED] 0xA7A0 (ALDERLAKE_P)
[12:22:00] [PASSED] 0xA7A8 (ALDERLAKE_P)
[12:22:00] [PASSED] 0xA7AA (ALDERLAKE_P)
[12:22:00] [PASSED] 0xA7AB (ALDERLAKE_P)
[12:22:00] [PASSED] 0xA780 (ALDERLAKE_S)
[12:22:00] [PASSED] 0xA781 (ALDERLAKE_S)
[12:22:00] [PASSED] 0xA782 (ALDERLAKE_S)
[12:22:00] [PASSED] 0xA783 (ALDERLAKE_S)
[12:22:00] [PASSED] 0xA788 (ALDERLAKE_S)
[12:22:00] [PASSED] 0xA789 (ALDERLAKE_S)
[12:22:00] [PASSED] 0xA78A (ALDERLAKE_S)
[12:22:00] [PASSED] 0xA78B (ALDERLAKE_S)
[12:22:00] [PASSED] 0x4905 (DG1)
[12:22:00] [PASSED] 0x4906 (DG1)
[12:22:00] [PASSED] 0x4907 (DG1)
[12:22:00] [PASSED] 0x4908 (DG1)
[12:22:00] [PASSED] 0x4909 (DG1)
[12:22:00] [PASSED] 0x56C0 (DG2)
[12:22:00] [PASSED] 0x56C2 (DG2)
[12:22:00] [PASSED] 0x56C1 (DG2)
[12:22:00] [PASSED] 0x7D51 (METEORLAKE)
[12:22:00] [PASSED] 0x7DD1 (METEORLAKE)
[12:22:00] [PASSED] 0x7D41 (METEORLAKE)
[12:22:00] [PASSED] 0x7D67 (METEORLAKE)
[12:22:00] [PASSED] 0xB640 (METEORLAKE)
[12:22:00] [PASSED] 0x56A0 (DG2)
[12:22:00] [PASSED] 0x56A1 (DG2)
[12:22:00] [PASSED] 0x56A2 (DG2)
[12:22:00] [PASSED] 0x56BE (DG2)
[12:22:00] [PASSED] 0x56BF (DG2)
[12:22:00] [PASSED] 0x5690 (DG2)
[12:22:00] [PASSED] 0x5691 (DG2)
[12:22:00] [PASSED] 0x5692 (DG2)
[12:22:00] [PASSED] 0x56A5 (DG2)
[12:22:00] [PASSED] 0x56A6 (DG2)
[12:22:00] [PASSED] 0x56B0 (DG2)
[12:22:00] [PASSED] 0x56B1 (DG2)
[12:22:00] [PASSED] 0x56BA (DG2)
[12:22:00] [PASSED] 0x56BB (DG2)
[12:22:00] [PASSED] 0x56BC (DG2)
[12:22:00] [PASSED] 0x56BD (DG2)
[12:22:00] [PASSED] 0x5693 (DG2)
[12:22:00] [PASSED] 0x5694 (DG2)
[12:22:00] [PASSED] 0x5695 (DG2)
[12:22:00] [PASSED] 0x56A3 (DG2)
[12:22:00] [PASSED] 0x56A4 (DG2)
[12:22:00] [PASSED] 0x56B2 (DG2)
[12:22:00] [PASSED] 0x56B3 (DG2)
[12:22:00] [PASSED] 0x5696 (DG2)
[12:22:00] [PASSED] 0x5697 (DG2)
[12:22:00] [PASSED] 0xB69 (PVC)
[12:22:00] [PASSED] 0xB6E (PVC)
[12:22:00] [PASSED] 0xBD4 (PVC)
[12:22:00] [PASSED] 0xBD5 (PVC)
[12:22:00] [PASSED] 0xBD6 (PVC)
[12:22:00] [PASSED] 0xBD7 (PVC)
[12:22:00] [PASSED] 0xBD8 (PVC)
[12:22:00] [PASSED] 0xBD9 (PVC)
[12:22:00] [PASSED] 0xBDA (PVC)
[12:22:00] [PASSED] 0xBDB (PVC)
[12:22:00] [PASSED] 0xBE0 (PVC)
[12:22:00] [PASSED] 0xBE1 (PVC)
[12:22:00] [PASSED] 0xBE5 (PVC)
[12:22:00] [PASSED] 0x7D40 (METEORLAKE)
[12:22:00] [PASSED] 0x7D45 (METEORLAKE)
[12:22:00] [PASSED] 0x7D55 (METEORLAKE)
[12:22:00] [PASSED] 0x7D60 (METEORLAKE)
[12:22:00] [PASSED] 0x7DD5 (METEORLAKE)
[12:22:00] [PASSED] 0x6420 (LUNARLAKE)
[12:22:00] [PASSED] 0x64A0 (LUNARLAKE)
[12:22:00] [PASSED] 0x64B0 (LUNARLAKE)
[12:22:00] [PASSED] 0xE202 (BATTLEMAGE)
[12:22:00] [PASSED] 0xE209 (BATTLEMAGE)
[12:22:00] [PASSED] 0xE20B (BATTLEMAGE)
[12:22:00] [PASSED] 0xE20C (BATTLEMAGE)
[12:22:00] [PASSED] 0xE20D (BATTLEMAGE)
[12:22:00] [PASSED] 0xE210 (BATTLEMAGE)
[12:22:00] [PASSED] 0xE211 (BATTLEMAGE)
[12:22:00] [PASSED] 0xE212 (BATTLEMAGE)
[12:22:00] [PASSED] 0xE216 (BATTLEMAGE)
[12:22:00] [PASSED] 0xE220 (BATTLEMAGE)
[12:22:00] [PASSED] 0xE221 (BATTLEMAGE)
[12:22:00] [PASSED] 0xE222 (BATTLEMAGE)
[12:22:00] [PASSED] 0xE223 (BATTLEMAGE)
[12:22:00] [PASSED] 0xB080 (PANTHERLAKE)
[12:22:00] [PASSED] 0xB081 (PANTHERLAKE)
[12:22:00] [PASSED] 0xB082 (PANTHERLAKE)
[12:22:00] [PASSED] 0xB083 (PANTHERLAKE)
[12:22:00] [PASSED] 0xB084 (PANTHERLAKE)
[12:22:00] [PASSED] 0xB085 (PANTHERLAKE)
[12:22:00] [PASSED] 0xB086 (PANTHERLAKE)
[12:22:00] [PASSED] 0xB087 (PANTHERLAKE)
[12:22:00] [PASSED] 0xB08F (PANTHERLAKE)
[12:22:00] [PASSED] 0xB090 (PANTHERLAKE)
[12:22:00] [PASSED] 0xB0A0 (PANTHERLAKE)
[12:22:00] [PASSED] 0xB0B0 (PANTHERLAKE)
[12:22:00] [PASSED] 0xFD80 (PANTHERLAKE)
[12:22:00] [PASSED] 0xFD81 (PANTHERLAKE)
[12:22:00] [PASSED] 0xD740 (NOVALAKE_S)
[12:22:00] [PASSED] 0xD741 (NOVALAKE_S)
[12:22:00] [PASSED] 0xD742 (NOVALAKE_S)
[12:22:00] [PASSED] 0xD743 (NOVALAKE_S)
[12:22:00] [PASSED] 0xD744 (NOVALAKE_S)
[12:22:00] [PASSED] 0xD745 (NOVALAKE_S)
[12:22:00] [PASSED] 0x674C (CRESCENTISLAND)
[12:22:00] =============== [PASSED] check_platform_desc ===============
[12:22:00] ===================== [PASSED] xe_pci ======================
[12:22:00] =================== xe_rtp (2 subtests) ====================
[12:22:00] =============== xe_rtp_process_to_sr_tests ================
[12:22:00] [PASSED] coalesce-same-reg
[12:22:00] [PASSED] no-match-no-add
[12:22:00] [PASSED] match-or
[12:22:00] [PASSED] match-or-xfail
[12:22:00] [PASSED] no-match-no-add-multiple-rules
[12:22:00] [PASSED] two-regs-two-entries
[12:22:00] [PASSED] clr-one-set-other
[12:22:00] [PASSED] set-field
[12:22:00] [PASSED] conflict-duplicate
[12:22:00] [PASSED] conflict-not-disjoint
[12:22:00] [PASSED] conflict-reg-type
[12:22:00] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[12:22:00] ================== xe_rtp_process_tests ===================
[12:22:00] [PASSED] active1
[12:22:00] [PASSED] active2
[12:22:00] [PASSED] active-inactive
[12:22:00] [PASSED] inactive-active
[12:22:00] [PASSED] inactive-1st_or_active-inactive
[12:22:00] [PASSED] inactive-2nd_or_active-inactive
[12:22:00] [PASSED] inactive-last_or_active-inactive
stty: 'standard input': Inappropriate ioctl for device
[12:22:00] [PASSED] inactive-no_or_active-inactive
[12:22:00] ============== [PASSED] xe_rtp_process_tests ===============
[12:22:00] ===================== [PASSED] xe_rtp ======================
[12:22:00] ==================== xe_wa (1 subtest) =====================
[12:22:00] ======================== xe_wa_gt =========================
[12:22:00] [PASSED] TIGERLAKE B0
[12:22:00] [PASSED] DG1 A0
[12:22:00] [PASSED] DG1 B0
[12:22:00] [PASSED] ALDERLAKE_S A0
[12:22:00] [PASSED] ALDERLAKE_S B0
[12:22:00] [PASSED] ALDERLAKE_S C0
[12:22:00] [PASSED] ALDERLAKE_S D0
[12:22:00] [PASSED] ALDERLAKE_P A0
[12:22:00] [PASSED] ALDERLAKE_P B0
[12:22:00] [PASSED] ALDERLAKE_P C0
[12:22:00] [PASSED] ALDERLAKE_S RPLS D0
[12:22:00] [PASSED] ALDERLAKE_P RPLU E0
[12:22:00] [PASSED] DG2 G10 C0
[12:22:00] [PASSED] DG2 G11 B1
[12:22:00] [PASSED] DG2 G12 A1
[12:22:00] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:22:00] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:22:00] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[12:22:00] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[12:22:00] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[12:22:00] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[12:22:00] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[12:22:00] ==================== [PASSED] xe_wa_gt =====================
[12:22:00] ====================== [PASSED] xe_wa ======================
[12:22:00] ============================================================
[12:22:00] Testing complete. Ran 318 tests: passed: 300, skipped: 18
[12:22:00] Elapsed time: 35.226s total, 4.208s configuring, 30.651s building, 0.332s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[12:22:00] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:22:02] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:22:27] Starting KUnit Kernel (1/1)...
[12:22:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:22:27] ============ drm_test_pick_cmdline (2 subtests) ============
[12:22:27] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[12:22:27] =============== drm_test_pick_cmdline_named ===============
[12:22:27] [PASSED] NTSC
[12:22:27] [PASSED] NTSC-J
[12:22:27] [PASSED] PAL
[12:22:27] [PASSED] PAL-M
[12:22:27] =========== [PASSED] drm_test_pick_cmdline_named ===========
[12:22:27] ============== [PASSED] drm_test_pick_cmdline ==============
[12:22:27] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[12:22:27] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[12:22:27] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[12:22:27] =========== drm_validate_clone_mode (2 subtests) ===========
[12:22:27] ============== drm_test_check_in_clone_mode ===============
[12:22:27] [PASSED] in_clone_mode
[12:22:27] [PASSED] not_in_clone_mode
[12:22:27] ========== [PASSED] drm_test_check_in_clone_mode ===========
[12:22:27] =============== drm_test_check_valid_clones ===============
[12:22:27] [PASSED] not_in_clone_mode
[12:22:27] [PASSED] valid_clone
[12:22:27] [PASSED] invalid_clone
[12:22:27] =========== [PASSED] drm_test_check_valid_clones ===========
[12:22:27] ============= [PASSED] drm_validate_clone_mode =============
[12:22:27] ============= drm_validate_modeset (1 subtest) =============
[12:22:27] [PASSED] drm_test_check_connector_changed_modeset
[12:22:27] ============== [PASSED] drm_validate_modeset ===============
[12:22:27] ====== drm_test_bridge_get_current_state (2 subtests) ======
[12:22:27] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[12:22:27] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[12:22:27] ======== [PASSED] drm_test_bridge_get_current_state ========
[12:22:27] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[12:22:27] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[12:22:27] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[12:22:27] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[12:22:27] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[12:22:27] ============== drm_bridge_alloc (2 subtests) ===============
[12:22:27] [PASSED] drm_test_drm_bridge_alloc_basic
[12:22:27] [PASSED] drm_test_drm_bridge_alloc_get_put
[12:22:27] ================ [PASSED] drm_bridge_alloc =================
[12:22:27] ================== drm_buddy (8 subtests) ==================
[12:22:27] [PASSED] drm_test_buddy_alloc_limit
[12:22:27] [PASSED] drm_test_buddy_alloc_optimistic
[12:22:27] [PASSED] drm_test_buddy_alloc_pessimistic
[12:22:27] [PASSED] drm_test_buddy_alloc_pathological
[12:22:27] [PASSED] drm_test_buddy_alloc_contiguous
[12:22:27] [PASSED] drm_test_buddy_alloc_clear
[12:22:27] [PASSED] drm_test_buddy_alloc_range_bias
[12:22:27] [PASSED] drm_test_buddy_fragmentation_performance
[12:22:27] ==================== [PASSED] drm_buddy ====================
[12:22:27] ============= drm_cmdline_parser (40 subtests) =============
[12:22:27] [PASSED] drm_test_cmdline_force_d_only
[12:22:27] [PASSED] drm_test_cmdline_force_D_only_dvi
[12:22:27] [PASSED] drm_test_cmdline_force_D_only_hdmi
[12:22:27] [PASSED] drm_test_cmdline_force_D_only_not_digital
[12:22:27] [PASSED] drm_test_cmdline_force_e_only
[12:22:27] [PASSED] drm_test_cmdline_res
[12:22:27] [PASSED] drm_test_cmdline_res_vesa
[12:22:27] [PASSED] drm_test_cmdline_res_vesa_rblank
[12:22:27] [PASSED] drm_test_cmdline_res_rblank
[12:22:27] [PASSED] drm_test_cmdline_res_bpp
[12:22:27] [PASSED] drm_test_cmdline_res_refresh
[12:22:27] [PASSED] drm_test_cmdline_res_bpp_refresh
[12:22:27] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[12:22:27] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[12:22:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[12:22:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[12:22:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[12:22:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[12:22:27] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[12:22:27] [PASSED] drm_test_cmdline_res_margins_force_on
[12:22:27] [PASSED] drm_test_cmdline_res_vesa_margins
[12:22:27] [PASSED] drm_test_cmdline_name
[12:22:27] [PASSED] drm_test_cmdline_name_bpp
[12:22:27] [PASSED] drm_test_cmdline_name_option
[12:22:27] [PASSED] drm_test_cmdline_name_bpp_option
[12:22:27] [PASSED] drm_test_cmdline_rotate_0
[12:22:27] [PASSED] drm_test_cmdline_rotate_90
[12:22:27] [PASSED] drm_test_cmdline_rotate_180
[12:22:27] [PASSED] drm_test_cmdline_rotate_270
[12:22:27] [PASSED] drm_test_cmdline_hmirror
[12:22:27] [PASSED] drm_test_cmdline_vmirror
[12:22:27] [PASSED] drm_test_cmdline_margin_options
[12:22:27] [PASSED] drm_test_cmdline_multiple_options
[12:22:27] [PASSED] drm_test_cmdline_bpp_extra_and_option
[12:22:27] [PASSED] drm_test_cmdline_extra_and_option
[12:22:27] [PASSED] drm_test_cmdline_freestanding_options
[12:22:27] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[12:22:27] [PASSED] drm_test_cmdline_panel_orientation
[12:22:27] ================ drm_test_cmdline_invalid =================
[12:22:27] [PASSED] margin_only
[12:22:27] [PASSED] interlace_only
[12:22:27] [PASSED] res_missing_x
[12:22:27] [PASSED] res_missing_y
[12:22:27] [PASSED] res_bad_y
[12:22:27] [PASSED] res_missing_y_bpp
[12:22:27] [PASSED] res_bad_bpp
[12:22:27] [PASSED] res_bad_refresh
[12:22:27] [PASSED] res_bpp_refresh_force_on_off
[12:22:27] [PASSED] res_invalid_mode
[12:22:27] [PASSED] res_bpp_wrong_place_mode
[12:22:27] [PASSED] name_bpp_refresh
[12:22:27] [PASSED] name_refresh
[12:22:27] [PASSED] name_refresh_wrong_mode
[12:22:27] [PASSED] name_refresh_invalid_mode
[12:22:27] [PASSED] rotate_multiple
[12:22:27] [PASSED] rotate_invalid_val
[12:22:27] [PASSED] rotate_truncated
[12:22:27] [PASSED] invalid_option
[12:22:27] [PASSED] invalid_tv_option
[12:22:27] [PASSED] truncated_tv_option
[12:22:27] ============ [PASSED] drm_test_cmdline_invalid =============
[12:22:27] =============== drm_test_cmdline_tv_options ===============
[12:22:27] [PASSED] NTSC
[12:22:27] [PASSED] NTSC_443
[12:22:27] [PASSED] NTSC_J
[12:22:27] [PASSED] PAL
[12:22:27] [PASSED] PAL_M
[12:22:27] [PASSED] PAL_N
[12:22:27] [PASSED] SECAM
[12:22:27] [PASSED] MONO_525
[12:22:27] [PASSED] MONO_625
[12:22:27] =========== [PASSED] drm_test_cmdline_tv_options ===========
[12:22:27] =============== [PASSED] drm_cmdline_parser ================
[12:22:27] ========== drmm_connector_hdmi_init (20 subtests) ==========
[12:22:27] [PASSED] drm_test_connector_hdmi_init_valid
[12:22:27] [PASSED] drm_test_connector_hdmi_init_bpc_8
[12:22:27] [PASSED] drm_test_connector_hdmi_init_bpc_10
[12:22:27] [PASSED] drm_test_connector_hdmi_init_bpc_12
[12:22:27] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[12:22:27] [PASSED] drm_test_connector_hdmi_init_bpc_null
[12:22:27] [PASSED] drm_test_connector_hdmi_init_formats_empty
[12:22:27] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[12:22:27] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:22:27] [PASSED] supported_formats=0x9 yuv420_allowed=1
[12:22:27] [PASSED] supported_formats=0x9 yuv420_allowed=0
[12:22:27] [PASSED] supported_formats=0x3 yuv420_allowed=1
[12:22:27] [PASSED] supported_formats=0x3 yuv420_allowed=0
[12:22:27] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:22:27] [PASSED] drm_test_connector_hdmi_init_null_ddc
[12:22:27] [PASSED] drm_test_connector_hdmi_init_null_product
[12:22:27] [PASSED] drm_test_connector_hdmi_init_null_vendor
[12:22:27] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[12:22:27] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[12:22:27] [PASSED] drm_test_connector_hdmi_init_product_valid
[12:22:27] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[12:22:27] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[12:22:27] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[12:22:27] ========= drm_test_connector_hdmi_init_type_valid =========
[12:22:27] [PASSED] HDMI-A
[12:22:27] [PASSED] HDMI-B
[12:22:27] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[12:22:27] ======== drm_test_connector_hdmi_init_type_invalid ========
[12:22:27] [PASSED] Unknown
[12:22:27] [PASSED] VGA
[12:22:27] [PASSED] DVI-I
[12:22:27] [PASSED] DVI-D
[12:22:27] [PASSED] DVI-A
[12:22:27] [PASSED] Composite
[12:22:27] [PASSED] SVIDEO
[12:22:27] [PASSED] LVDS
[12:22:27] [PASSED] Component
[12:22:27] [PASSED] DIN
[12:22:27] [PASSED] DP
[12:22:27] [PASSED] TV
[12:22:27] [PASSED] eDP
[12:22:27] [PASSED] Virtual
[12:22:27] [PASSED] DSI
[12:22:27] [PASSED] DPI
[12:22:27] [PASSED] Writeback
[12:22:27] [PASSED] SPI
[12:22:27] [PASSED] USB
[12:22:27] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[12:22:27] ============ [PASSED] drmm_connector_hdmi_init =============
[12:22:27] ============= drmm_connector_init (3 subtests) =============
[12:22:27] [PASSED] drm_test_drmm_connector_init
[12:22:27] [PASSED] drm_test_drmm_connector_init_null_ddc
[12:22:27] ========= drm_test_drmm_connector_init_type_valid =========
[12:22:27] [PASSED] Unknown
[12:22:27] [PASSED] VGA
[12:22:27] [PASSED] DVI-I
[12:22:27] [PASSED] DVI-D
[12:22:27] [PASSED] DVI-A
[12:22:27] [PASSED] Composite
[12:22:27] [PASSED] SVIDEO
[12:22:27] [PASSED] LVDS
[12:22:27] [PASSED] Component
[12:22:27] [PASSED] DIN
[12:22:27] [PASSED] DP
[12:22:27] [PASSED] HDMI-A
[12:22:27] [PASSED] HDMI-B
[12:22:27] [PASSED] TV
[12:22:27] [PASSED] eDP
[12:22:27] [PASSED] Virtual
[12:22:27] [PASSED] DSI
[12:22:27] [PASSED] DPI
[12:22:27] [PASSED] Writeback
[12:22:27] [PASSED] SPI
[12:22:27] [PASSED] USB
[12:22:27] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[12:22:27] =============== [PASSED] drmm_connector_init ===============
[12:22:27] ========= drm_connector_dynamic_init (6 subtests) ==========
[12:22:27] [PASSED] drm_test_drm_connector_dynamic_init
[12:22:27] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[12:22:27] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[12:22:27] [PASSED] drm_test_drm_connector_dynamic_init_properties
[12:22:27] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[12:22:27] [PASSED] Unknown
[12:22:27] [PASSED] VGA
[12:22:27] [PASSED] DVI-I
[12:22:27] [PASSED] DVI-D
[12:22:27] [PASSED] DVI-A
[12:22:27] [PASSED] Composite
[12:22:27] [PASSED] SVIDEO
[12:22:27] [PASSED] LVDS
[12:22:27] [PASSED] Component
[12:22:27] [PASSED] DIN
[12:22:27] [PASSED] DP
[12:22:27] [PASSED] HDMI-A
[12:22:27] [PASSED] HDMI-B
[12:22:27] [PASSED] TV
[12:22:27] [PASSED] eDP
[12:22:27] [PASSED] Virtual
[12:22:27] [PASSED] DSI
[12:22:27] [PASSED] DPI
[12:22:27] [PASSED] Writeback
[12:22:27] [PASSED] SPI
[12:22:27] [PASSED] USB
[12:22:27] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[12:22:27] ======== drm_test_drm_connector_dynamic_init_name =========
[12:22:27] [PASSED] Unknown
[12:22:27] [PASSED] VGA
[12:22:27] [PASSED] DVI-I
[12:22:27] [PASSED] DVI-D
[12:22:27] [PASSED] DVI-A
[12:22:27] [PASSED] Composite
[12:22:27] [PASSED] SVIDEO
[12:22:27] [PASSED] LVDS
[12:22:27] [PASSED] Component
[12:22:27] [PASSED] DIN
[12:22:27] [PASSED] DP
[12:22:27] [PASSED] HDMI-A
[12:22:27] [PASSED] HDMI-B
[12:22:27] [PASSED] TV
[12:22:27] [PASSED] eDP
[12:22:27] [PASSED] Virtual
[12:22:27] [PASSED] DSI
[12:22:27] [PASSED] DPI
[12:22:27] [PASSED] Writeback
[12:22:27] [PASSED] SPI
[12:22:27] [PASSED] USB
[12:22:27] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[12:22:27] =========== [PASSED] drm_connector_dynamic_init ============
[12:22:27] ==== drm_connector_dynamic_register_early (4 subtests) =====
[12:22:27] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[12:22:27] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[12:22:27] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[12:22:27] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[12:22:27] ====== [PASSED] drm_connector_dynamic_register_early =======
[12:22:27] ======= drm_connector_dynamic_register (7 subtests) ========
[12:22:27] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[12:22:27] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[12:22:27] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[12:22:27] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[12:22:27] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[12:22:27] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[12:22:27] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[12:22:27] ========= [PASSED] drm_connector_dynamic_register ==========
[12:22:27] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[12:22:27] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[12:22:27] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[12:22:27] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[12:22:27] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[12:22:27] ========== drm_test_get_tv_mode_from_name_valid ===========
[12:22:27] [PASSED] NTSC
[12:22:27] [PASSED] NTSC-443
[12:22:27] [PASSED] NTSC-J
[12:22:27] [PASSED] PAL
[12:22:27] [PASSED] PAL-M
[12:22:27] [PASSED] PAL-N
[12:22:27] [PASSED] SECAM
[12:22:27] [PASSED] Mono
[12:22:27] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[12:22:27] [PASSED] drm_test_get_tv_mode_from_name_truncated
[12:22:27] ============ [PASSED] drm_get_tv_mode_from_name ============
[12:22:27] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[12:22:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[12:22:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[12:22:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[12:22:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[12:22:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[12:22:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[12:22:27] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[12:22:27] [PASSED] VIC 96
[12:22:27] [PASSED] VIC 97
[12:22:27] [PASSED] VIC 101
[12:22:27] [PASSED] VIC 102
[12:22:27] [PASSED] VIC 106
[12:22:27] [PASSED] VIC 107
[12:22:27] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[12:22:27] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[12:22:27] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[12:22:27] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[12:22:27] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[12:22:27] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[12:22:27] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[12:22:27] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[12:22:27] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[12:22:27] [PASSED] Automatic
[12:22:27] [PASSED] Full
[12:22:27] [PASSED] Limited 16:235
[12:22:27] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[12:22:27] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[12:22:27] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[12:22:27] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[12:22:27] === drm_test_drm_hdmi_connector_get_output_format_name ====
[12:22:27] [PASSED] RGB
[12:22:27] [PASSED] YUV 4:2:0
[12:22:27] [PASSED] YUV 4:2:2
[12:22:27] [PASSED] YUV 4:4:4
[12:22:27] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[12:22:27] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[12:22:27] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[12:22:27] ============= drm_damage_helper (21 subtests) ==============
[12:22:27] [PASSED] drm_test_damage_iter_no_damage
[12:22:27] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[12:22:27] [PASSED] drm_test_damage_iter_no_damage_src_moved
[12:22:27] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[12:22:27] [PASSED] drm_test_damage_iter_no_damage_not_visible
[12:22:27] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[12:22:27] [PASSED] drm_test_damage_iter_no_damage_no_fb
[12:22:27] [PASSED] drm_test_damage_iter_simple_damage
[12:22:27] [PASSED] drm_test_damage_iter_single_damage
[12:22:27] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[12:22:27] [PASSED] drm_test_damage_iter_single_damage_outside_src
[12:22:27] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[12:22:27] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[12:22:27] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[12:22:27] [PASSED] drm_test_damage_iter_single_damage_src_moved
[12:22:27] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[12:22:27] [PASSED] drm_test_damage_iter_damage
[12:22:27] [PASSED] drm_test_damage_iter_damage_one_intersect
[12:22:27] [PASSED] drm_test_damage_iter_damage_one_outside
[12:22:27] [PASSED] drm_test_damage_iter_damage_src_moved
[12:22:27] [PASSED] drm_test_damage_iter_damage_not_visible
[12:22:27] ================ [PASSED] drm_damage_helper ================
[12:22:27] ============== drm_dp_mst_helper (3 subtests) ==============
[12:22:27] ============== drm_test_dp_mst_calc_pbn_mode ==============
[12:22:27] [PASSED] Clock 154000 BPP 30 DSC disabled
[12:22:27] [PASSED] Clock 234000 BPP 30 DSC disabled
[12:22:27] [PASSED] Clock 297000 BPP 24 DSC disabled
[12:22:27] [PASSED] Clock 332880 BPP 24 DSC enabled
[12:22:27] [PASSED] Clock 324540 BPP 24 DSC enabled
[12:22:27] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[12:22:27] ============== drm_test_dp_mst_calc_pbn_div ===============
[12:22:27] [PASSED] Link rate 2000000 lane count 4
[12:22:27] [PASSED] Link rate 2000000 lane count 2
[12:22:27] [PASSED] Link rate 2000000 lane count 1
[12:22:27] [PASSED] Link rate 1350000 lane count 4
[12:22:27] [PASSED] Link rate 1350000 lane count 2
[12:22:27] [PASSED] Link rate 1350000 lane count 1
[12:22:27] [PASSED] Link rate 1000000 lane count 4
[12:22:27] [PASSED] Link rate 1000000 lane count 2
[12:22:27] [PASSED] Link rate 1000000 lane count 1
[12:22:27] [PASSED] Link rate 810000 lane count 4
[12:22:27] [PASSED] Link rate 810000 lane count 2
[12:22:27] [PASSED] Link rate 810000 lane count 1
[12:22:27] [PASSED] Link rate 540000 lane count 4
[12:22:27] [PASSED] Link rate 540000 lane count 2
[12:22:27] [PASSED] Link rate 540000 lane count 1
[12:22:27] [PASSED] Link rate 270000 lane count 4
[12:22:27] [PASSED] Link rate 270000 lane count 2
[12:22:27] [PASSED] Link rate 270000 lane count 1
[12:22:27] [PASSED] Link rate 162000 lane count 4
[12:22:27] [PASSED] Link rate 162000 lane count 2
[12:22:27] [PASSED] Link rate 162000 lane count 1
[12:22:27] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[12:22:27] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[12:22:27] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[12:22:27] [PASSED] DP_POWER_UP_PHY with port number
[12:22:27] [PASSED] DP_POWER_DOWN_PHY with port number
[12:22:27] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[12:22:27] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[12:22:27] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[12:22:27] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[12:22:27] [PASSED] DP_QUERY_PAYLOAD with port number
[12:22:27] [PASSED] DP_QUERY_PAYLOAD with VCPI
[12:22:27] [PASSED] DP_REMOTE_DPCD_READ with port number
[12:22:27] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[12:22:27] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[12:22:27] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[12:22:27] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[12:22:27] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[12:22:27] [PASSED] DP_REMOTE_I2C_READ with port number
[12:22:27] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[12:22:27] [PASSED] DP_REMOTE_I2C_READ with transactions array
[12:22:27] [PASSED] DP_REMOTE_I2C_WRITE with port number
[12:22:27] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[12:22:27] [PASSED] DP_REMOTE_I2C_WRITE with data array
[12:22:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[12:22:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[12:22:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[12:22:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[12:22:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[12:22:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[12:22:27] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[12:22:27] ================ [PASSED] drm_dp_mst_helper ================
[12:22:27] ================== drm_exec (7 subtests) ===================
[12:22:27] [PASSED] sanitycheck
[12:22:27] [PASSED] test_lock
[12:22:27] [PASSED] test_lock_unlock
[12:22:27] [PASSED] test_duplicates
[12:22:27] [PASSED] test_prepare
[12:22:27] [PASSED] test_prepare_array
[12:22:27] [PASSED] test_multiple_loops
[12:22:27] ==================== [PASSED] drm_exec =====================
[12:22:27] =========== drm_format_helper_test (17 subtests) ===========
[12:22:27] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[12:22:27] [PASSED] single_pixel_source_buffer
[12:22:27] [PASSED] single_pixel_clip_rectangle
[12:22:27] [PASSED] well_known_colors
[12:22:27] [PASSED] destination_pitch
[12:22:27] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[12:22:27] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[12:22:27] [PASSED] single_pixel_source_buffer
[12:22:27] [PASSED] single_pixel_clip_rectangle
[12:22:27] [PASSED] well_known_colors
[12:22:27] [PASSED] destination_pitch
[12:22:27] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[12:22:27] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[12:22:27] [PASSED] single_pixel_source_buffer
[12:22:27] [PASSED] single_pixel_clip_rectangle
[12:22:27] [PASSED] well_known_colors
[12:22:27] [PASSED] destination_pitch
[12:22:27] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[12:22:27] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[12:22:27] [PASSED] single_pixel_source_buffer
[12:22:27] [PASSED] single_pixel_clip_rectangle
[12:22:27] [PASSED] well_known_colors
[12:22:27] [PASSED] destination_pitch
[12:22:27] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[12:22:27] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[12:22:27] [PASSED] single_pixel_source_buffer
[12:22:27] [PASSED] single_pixel_clip_rectangle
[12:22:27] [PASSED] well_known_colors
[12:22:27] [PASSED] destination_pitch
[12:22:27] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[12:22:27] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[12:22:27] [PASSED] single_pixel_source_buffer
[12:22:27] [PASSED] single_pixel_clip_rectangle
[12:22:27] [PASSED] well_known_colors
[12:22:27] [PASSED] destination_pitch
[12:22:27] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[12:22:27] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[12:22:27] [PASSED] single_pixel_source_buffer
[12:22:27] [PASSED] single_pixel_clip_rectangle
[12:22:27] [PASSED] well_known_colors
[12:22:27] [PASSED] destination_pitch
[12:22:27] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[12:22:27] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[12:22:27] [PASSED] single_pixel_source_buffer
[12:22:27] [PASSED] single_pixel_clip_rectangle
[12:22:27] [PASSED] well_known_colors
[12:22:27] [PASSED] destination_pitch
[12:22:27] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[12:22:27] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[12:22:27] [PASSED] single_pixel_source_buffer
[12:22:27] [PASSED] single_pixel_clip_rectangle
[12:22:27] [PASSED] well_known_colors
[12:22:27] [PASSED] destination_pitch
[12:22:27] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[12:22:27] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[12:22:27] [PASSED] single_pixel_source_buffer
[12:22:27] [PASSED] single_pixel_clip_rectangle
[12:22:27] [PASSED] well_known_colors
[12:22:27] [PASSED] destination_pitch
[12:22:27] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[12:22:27] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[12:22:27] [PASSED] single_pixel_source_buffer
[12:22:27] [PASSED] single_pixel_clip_rectangle
[12:22:27] [PASSED] well_known_colors
[12:22:27] [PASSED] destination_pitch
[12:22:27] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[12:22:27] ============== drm_test_fb_xrgb8888_to_mono ===============
[12:22:27] [PASSED] single_pixel_source_buffer
[12:22:27] [PASSED] single_pixel_clip_rectangle
[12:22:27] [PASSED] well_known_colors
[12:22:27] [PASSED] destination_pitch
[12:22:27] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[12:22:27] ==================== drm_test_fb_swab =====================
[12:22:27] [PASSED] single_pixel_source_buffer
[12:22:27] [PASSED] single_pixel_clip_rectangle
[12:22:27] [PASSED] well_known_colors
[12:22:27] [PASSED] destination_pitch
[12:22:27] ================ [PASSED] drm_test_fb_swab =================
[12:22:27] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[12:22:27] [PASSED] single_pixel_source_buffer
[12:22:27] [PASSED] single_pixel_clip_rectangle
[12:22:27] [PASSED] well_known_colors
[12:22:27] [PASSED] destination_pitch
[12:22:27] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[12:22:27] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[12:22:27] [PASSED] single_pixel_source_buffer
[12:22:27] [PASSED] single_pixel_clip_rectangle
[12:22:27] [PASSED] well_known_colors
[12:22:27] [PASSED] destination_pitch
[12:22:27] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[12:22:27] ================= drm_test_fb_clip_offset =================
[12:22:27] [PASSED] pass through
[12:22:27] [PASSED] horizontal offset
[12:22:27] [PASSED] vertical offset
[12:22:27] [PASSED] horizontal and vertical offset
[12:22:27] [PASSED] horizontal offset (custom pitch)
[12:22:27] [PASSED] vertical offset (custom pitch)
[12:22:27] [PASSED] horizontal and vertical offset (custom pitch)
[12:22:27] ============= [PASSED] drm_test_fb_clip_offset =============
[12:22:27] =================== drm_test_fb_memcpy ====================
[12:22:27] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[12:22:27] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[12:22:27] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[12:22:27] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[12:22:27] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[12:22:27] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[12:22:27] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[12:22:27] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[12:22:27] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[12:22:27] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[12:22:27] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[12:22:27] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[12:22:27] =============== [PASSED] drm_test_fb_memcpy ================
[12:22:27] ============= [PASSED] drm_format_helper_test ==============
[12:22:27] ================= drm_format (18 subtests) =================
[12:22:27] [PASSED] drm_test_format_block_width_invalid
[12:22:27] [PASSED] drm_test_format_block_width_one_plane
[12:22:27] [PASSED] drm_test_format_block_width_two_plane
[12:22:27] [PASSED] drm_test_format_block_width_three_plane
[12:22:27] [PASSED] drm_test_format_block_width_tiled
[12:22:27] [PASSED] drm_test_format_block_height_invalid
[12:22:27] [PASSED] drm_test_format_block_height_one_plane
[12:22:27] [PASSED] drm_test_format_block_height_two_plane
[12:22:27] [PASSED] drm_test_format_block_height_three_plane
[12:22:27] [PASSED] drm_test_format_block_height_tiled
[12:22:27] [PASSED] drm_test_format_min_pitch_invalid
[12:22:27] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[12:22:27] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[12:22:27] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[12:22:27] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[12:22:27] [PASSED] drm_test_format_min_pitch_two_plane
[12:22:27] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[12:22:27] [PASSED] drm_test_format_min_pitch_tiled
[12:22:27] =================== [PASSED] drm_format ====================
[12:22:27] ============== drm_framebuffer (10 subtests) ===============
[12:22:27] ========== drm_test_framebuffer_check_src_coords ==========
[12:22:27] [PASSED] Success: source fits into fb
[12:22:27] [PASSED] Fail: overflowing fb with x-axis coordinate
[12:22:27] [PASSED] Fail: overflowing fb with y-axis coordinate
[12:22:27] [PASSED] Fail: overflowing fb with source width
[12:22:27] [PASSED] Fail: overflowing fb with source height
[12:22:27] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[12:22:27] [PASSED] drm_test_framebuffer_cleanup
[12:22:27] =============== drm_test_framebuffer_create ===============
[12:22:27] [PASSED] ABGR8888 normal sizes
[12:22:27] [PASSED] ABGR8888 max sizes
[12:22:27] [PASSED] ABGR8888 pitch greater than min required
[12:22:27] [PASSED] ABGR8888 pitch less than min required
[12:22:27] [PASSED] ABGR8888 Invalid width
[12:22:27] [PASSED] ABGR8888 Invalid buffer handle
[12:22:27] [PASSED] No pixel format
[12:22:27] [PASSED] ABGR8888 Width 0
[12:22:27] [PASSED] ABGR8888 Height 0
[12:22:27] [PASSED] ABGR8888 Out of bound height * pitch combination
[12:22:27] [PASSED] ABGR8888 Large buffer offset
[12:22:27] [PASSED] ABGR8888 Buffer offset for inexistent plane
[12:22:27] [PASSED] ABGR8888 Invalid flag
[12:22:27] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[12:22:27] [PASSED] ABGR8888 Valid buffer modifier
[12:22:27] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[12:22:27] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[12:22:27] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[12:22:27] [PASSED] NV12 Normal sizes
[12:22:27] [PASSED] NV12 Max sizes
[12:22:27] [PASSED] NV12 Invalid pitch
[12:22:27] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[12:22:27] [PASSED] NV12 different modifier per-plane
[12:22:27] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[12:22:27] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[12:22:27] [PASSED] NV12 Modifier for inexistent plane
[12:22:27] [PASSED] NV12 Handle for inexistent plane
[12:22:27] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[12:22:27] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[12:22:27] [PASSED] YVU420 Normal sizes
[12:22:27] [PASSED] YVU420 Max sizes
[12:22:27] [PASSED] YVU420 Invalid pitch
[12:22:27] [PASSED] YVU420 Different pitches
[12:22:27] [PASSED] YVU420 Different buffer offsets/pitches
[12:22:27] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[12:22:27] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[12:22:27] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[12:22:27] [PASSED] YVU420 Valid modifier
[12:22:27] [PASSED] YVU420 Different modifiers per plane
[12:22:27] [PASSED] YVU420 Modifier for inexistent plane
[12:22:27] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[12:22:27] [PASSED] X0L2 Normal sizes
[12:22:27] [PASSED] X0L2 Max sizes
[12:22:27] [PASSED] X0L2 Invalid pitch
[12:22:27] [PASSED] X0L2 Pitch greater than minimum required
[12:22:27] [PASSED] X0L2 Handle for inexistent plane
[12:22:27] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[12:22:27] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[12:22:27] [PASSED] X0L2 Valid modifier
[12:22:27] [PASSED] X0L2 Modifier for inexistent plane
[12:22:27] =========== [PASSED] drm_test_framebuffer_create ===========
[12:22:27] [PASSED] drm_test_framebuffer_free
[12:22:27] [PASSED] drm_test_framebuffer_init
[12:22:27] [PASSED] drm_test_framebuffer_init_bad_format
[12:22:27] [PASSED] drm_test_framebuffer_init_dev_mismatch
[12:22:27] [PASSED] drm_test_framebuffer_lookup
[12:22:27] [PASSED] drm_test_framebuffer_lookup_inexistent
[12:22:27] [PASSED] drm_test_framebuffer_modifiers_not_supported
[12:22:27] ================= [PASSED] drm_framebuffer =================
[12:22:27] ================ drm_gem_shmem (8 subtests) ================
[12:22:27] [PASSED] drm_gem_shmem_test_obj_create
[12:22:27] [PASSED] drm_gem_shmem_test_obj_create_private
[12:22:27] [PASSED] drm_gem_shmem_test_pin_pages
[12:22:27] [PASSED] drm_gem_shmem_test_vmap
[12:22:27] [PASSED] drm_gem_shmem_test_get_pages_sgt
[12:22:27] [PASSED] drm_gem_shmem_test_get_sg_table
[12:22:27] [PASSED] drm_gem_shmem_test_madvise
[12:22:27] [PASSED] drm_gem_shmem_test_purge
[12:22:27] ================== [PASSED] drm_gem_shmem ==================
[12:22:27] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[12:22:27] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[12:22:27] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[12:22:27] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[12:22:27] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[12:22:27] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[12:22:27] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[12:22:27] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[12:22:27] [PASSED] Automatic
[12:22:27] [PASSED] Full
[12:22:27] [PASSED] Limited 16:235
[12:22:27] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[12:22:27] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[12:22:27] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[12:22:27] [PASSED] drm_test_check_disable_connector
[12:22:27] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[12:22:27] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[12:22:27] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[12:22:27] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[12:22:27] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[12:22:27] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[12:22:27] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[12:22:27] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[12:22:27] [PASSED] drm_test_check_output_bpc_dvi
[12:22:27] [PASSED] drm_test_check_output_bpc_format_vic_1
[12:22:27] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[12:22:27] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[12:22:27] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[12:22:27] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[12:22:27] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[12:22:27] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[12:22:27] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[12:22:27] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[12:22:27] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[12:22:27] [PASSED] drm_test_check_broadcast_rgb_value
[12:22:27] [PASSED] drm_test_check_bpc_8_value
[12:22:27] [PASSED] drm_test_check_bpc_10_value
[12:22:27] [PASSED] drm_test_check_bpc_12_value
[12:22:27] [PASSED] drm_test_check_format_value
[12:22:27] [PASSED] drm_test_check_tmds_char_value
[12:22:27] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[12:22:27] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[12:22:27] [PASSED] drm_test_check_mode_valid
[12:22:27] [PASSED] drm_test_check_mode_valid_reject
[12:22:27] [PASSED] drm_test_check_mode_valid_reject_rate
[12:22:27] [PASSED] drm_test_check_mode_valid_reject_max_clock
[12:22:27] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[12:22:27] ================= drm_managed (2 subtests) =================
[12:22:27] [PASSED] drm_test_managed_release_action
[12:22:27] [PASSED] drm_test_managed_run_action
[12:22:27] =================== [PASSED] drm_managed ===================
[12:22:27] =================== drm_mm (6 subtests) ====================
[12:22:27] [PASSED] drm_test_mm_init
[12:22:27] [PASSED] drm_test_mm_debug
[12:22:27] [PASSED] drm_test_mm_align32
[12:22:27] [PASSED] drm_test_mm_align64
[12:22:27] [PASSED] drm_test_mm_lowest
[12:22:27] [PASSED] drm_test_mm_highest
[12:22:27] ===================== [PASSED] drm_mm ======================
[12:22:27] ============= drm_modes_analog_tv (5 subtests) =============
[12:22:27] [PASSED] drm_test_modes_analog_tv_mono_576i
[12:22:27] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[12:22:27] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[12:22:27] [PASSED] drm_test_modes_analog_tv_pal_576i
[12:22:27] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[12:22:27] =============== [PASSED] drm_modes_analog_tv ===============
[12:22:27] ============== drm_plane_helper (2 subtests) ===============
[12:22:27] =============== drm_test_check_plane_state ================
[12:22:27] [PASSED] clipping_simple
[12:22:27] [PASSED] clipping_rotate_reflect
[12:22:27] [PASSED] positioning_simple
[12:22:27] [PASSED] upscaling
[12:22:27] [PASSED] downscaling
[12:22:27] [PASSED] rounding1
[12:22:27] [PASSED] rounding2
[12:22:27] [PASSED] rounding3
[12:22:27] [PASSED] rounding4
[12:22:27] =========== [PASSED] drm_test_check_plane_state ============
[12:22:27] =========== drm_test_check_invalid_plane_state ============
[12:22:27] [PASSED] positioning_invalid
[12:22:27] [PASSED] upscaling_invalid
[12:22:27] [PASSED] downscaling_invalid
[12:22:27] ======= [PASSED] drm_test_check_invalid_plane_state ========
[12:22:27] ================ [PASSED] drm_plane_helper =================
[12:22:27] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[12:22:27] ====== drm_test_connector_helper_tv_get_modes_check =======
[12:22:27] [PASSED] None
[12:22:27] [PASSED] PAL
[12:22:27] [PASSED] NTSC
[12:22:27] [PASSED] Both, NTSC Default
[12:22:27] [PASSED] Both, PAL Default
[12:22:27] [PASSED] Both, NTSC Default, with PAL on command-line
[12:22:27] [PASSED] Both, PAL Default, with NTSC on command-line
[12:22:27] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[12:22:27] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[12:22:27] ================== drm_rect (9 subtests) ===================
[12:22:27] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[12:22:27] [PASSED] drm_test_rect_clip_scaled_not_clipped
[12:22:27] [PASSED] drm_test_rect_clip_scaled_clipped
[12:22:27] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[12:22:27] ================= drm_test_rect_intersect =================
[12:22:27] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[12:22:27] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[12:22:27] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[12:22:27] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[12:22:27] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[12:22:27] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[12:22:27] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[12:22:27] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[12:22:27] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[12:22:27] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[12:22:27] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[12:22:27] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[12:22:27] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[12:22:27] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[12:22:27] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[12:22:27] ============= [PASSED] drm_test_rect_intersect =============
[12:22:27] ================ drm_test_rect_calc_hscale ================
[12:22:27] [PASSED] normal use
[12:22:27] [PASSED] out of max range
[12:22:27] [PASSED] out of min range
[12:22:27] [PASSED] zero dst
[12:22:27] [PASSED] negative src
[12:22:27] [PASSED] negative dst
[12:22:27] ============ [PASSED] drm_test_rect_calc_hscale ============
[12:22:27] ================ drm_test_rect_calc_vscale ================
[12:22:27] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[12:22:27] [PASSED] out of max range
[12:22:27] [PASSED] out of min range
[12:22:27] [PASSED] zero dst
[12:22:27] [PASSED] negative src
[12:22:27] [PASSED] negative dst
[12:22:27] ============ [PASSED] drm_test_rect_calc_vscale ============
[12:22:27] ================== drm_test_rect_rotate ===================
[12:22:27] [PASSED] reflect-x
[12:22:27] [PASSED] reflect-y
[12:22:27] [PASSED] rotate-0
[12:22:27] [PASSED] rotate-90
[12:22:27] [PASSED] rotate-180
[12:22:27] [PASSED] rotate-270
[12:22:27] ============== [PASSED] drm_test_rect_rotate ===============
[12:22:27] ================ drm_test_rect_rotate_inv =================
[12:22:27] [PASSED] reflect-x
[12:22:27] [PASSED] reflect-y
[12:22:27] [PASSED] rotate-0
[12:22:27] [PASSED] rotate-90
[12:22:27] [PASSED] rotate-180
[12:22:27] [PASSED] rotate-270
[12:22:27] ============ [PASSED] drm_test_rect_rotate_inv =============
[12:22:27] ==================== [PASSED] drm_rect =====================
[12:22:27] ============ drm_sysfb_modeset_test (1 subtest) ============
[12:22:27] ============ drm_test_sysfb_build_fourcc_list =============
[12:22:27] [PASSED] no native formats
[12:22:27] [PASSED] XRGB8888 as native format
[12:22:27] [PASSED] remove duplicates
[12:22:27] [PASSED] convert alpha formats
[12:22:27] [PASSED] random formats
[12:22:27] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[12:22:27] ============= [PASSED] drm_sysfb_modeset_test ==============
[12:22:27] ============================================================
[12:22:27] Testing complete. Ran 622 tests: passed: 622
[12:22:27] Elapsed time: 26.985s total, 1.699s configuring, 24.866s building, 0.385s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[12:22:27] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:22:29] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:22:38] Starting KUnit Kernel (1/1)...
[12:22:38] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:22:38] ================= ttm_device (5 subtests) ==================
[12:22:38] [PASSED] ttm_device_init_basic
[12:22:38] [PASSED] ttm_device_init_multiple
[12:22:38] [PASSED] ttm_device_fini_basic
[12:22:38] [PASSED] ttm_device_init_no_vma_man
[12:22:38] ================== ttm_device_init_pools ==================
[12:22:38] [PASSED] No DMA allocations, no DMA32 required
[12:22:38] [PASSED] DMA allocations, DMA32 required
[12:22:38] [PASSED] No DMA allocations, DMA32 required
[12:22:38] [PASSED] DMA allocations, no DMA32 required
[12:22:38] ============== [PASSED] ttm_device_init_pools ==============
[12:22:38] =================== [PASSED] ttm_device ====================
[12:22:38] ================== ttm_pool (8 subtests) ===================
[12:22:38] ================== ttm_pool_alloc_basic ===================
[12:22:38] [PASSED] One page
[12:22:38] [PASSED] More than one page
[12:22:38] [PASSED] Above the allocation limit
[12:22:38] [PASSED] One page, with coherent DMA mappings enabled
[12:22:38] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:22:38] ============== [PASSED] ttm_pool_alloc_basic ===============
[12:22:38] ============== ttm_pool_alloc_basic_dma_addr ==============
[12:22:38] [PASSED] One page
[12:22:38] [PASSED] More than one page
[12:22:38] [PASSED] Above the allocation limit
[12:22:38] [PASSED] One page, with coherent DMA mappings enabled
[12:22:38] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:22:38] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[12:22:38] [PASSED] ttm_pool_alloc_order_caching_match
[12:22:38] [PASSED] ttm_pool_alloc_caching_mismatch
[12:22:38] [PASSED] ttm_pool_alloc_order_mismatch
[12:22:38] [PASSED] ttm_pool_free_dma_alloc
[12:22:38] [PASSED] ttm_pool_free_no_dma_alloc
[12:22:38] [PASSED] ttm_pool_fini_basic
[12:22:38] ==================== [PASSED] ttm_pool =====================
[12:22:38] ================ ttm_resource (8 subtests) =================
[12:22:38] ================= ttm_resource_init_basic =================
[12:22:38] [PASSED] Init resource in TTM_PL_SYSTEM
[12:22:38] [PASSED] Init resource in TTM_PL_VRAM
[12:22:38] [PASSED] Init resource in a private placement
[12:22:38] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[12:22:38] ============= [PASSED] ttm_resource_init_basic =============
[12:22:38] [PASSED] ttm_resource_init_pinned
[12:22:38] [PASSED] ttm_resource_fini_basic
[12:22:38] [PASSED] ttm_resource_manager_init_basic
[12:22:38] [PASSED] ttm_resource_manager_usage_basic
[12:22:38] [PASSED] ttm_resource_manager_set_used_basic
[12:22:38] [PASSED] ttm_sys_man_alloc_basic
[12:22:38] [PASSED] ttm_sys_man_free_basic
[12:22:38] ================== [PASSED] ttm_resource ===================
[12:22:38] =================== ttm_tt (15 subtests) ===================
[12:22:38] ==================== ttm_tt_init_basic ====================
[12:22:38] [PASSED] Page-aligned size
[12:22:38] [PASSED] Extra pages requested
[12:22:38] ================ [PASSED] ttm_tt_init_basic ================
[12:22:38] [PASSED] ttm_tt_init_misaligned
[12:22:38] [PASSED] ttm_tt_fini_basic
[12:22:38] [PASSED] ttm_tt_fini_sg
[12:22:38] [PASSED] ttm_tt_fini_shmem
[12:22:38] [PASSED] ttm_tt_create_basic
[12:22:38] [PASSED] ttm_tt_create_invalid_bo_type
[12:22:38] [PASSED] ttm_tt_create_ttm_exists
[12:22:38] [PASSED] ttm_tt_create_failed
[12:22:38] [PASSED] ttm_tt_destroy_basic
[12:22:38] [PASSED] ttm_tt_populate_null_ttm
[12:22:38] [PASSED] ttm_tt_populate_populated_ttm
[12:22:38] [PASSED] ttm_tt_unpopulate_basic
[12:22:38] [PASSED] ttm_tt_unpopulate_empty_ttm
[12:22:38] [PASSED] ttm_tt_swapin_basic
[12:22:38] ===================== [PASSED] ttm_tt ======================
[12:22:38] =================== ttm_bo (14 subtests) ===================
[12:22:38] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[12:22:38] [PASSED] Cannot be interrupted and sleeps
[12:22:38] [PASSED] Cannot be interrupted, locks straight away
[12:22:38] [PASSED] Can be interrupted, sleeps
[12:22:38] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[12:22:38] [PASSED] ttm_bo_reserve_locked_no_sleep
[12:22:38] [PASSED] ttm_bo_reserve_no_wait_ticket
[12:22:39] [PASSED] ttm_bo_reserve_double_resv
[12:22:39] [PASSED] ttm_bo_reserve_interrupted
[12:22:39] [PASSED] ttm_bo_reserve_deadlock
[12:22:39] [PASSED] ttm_bo_unreserve_basic
[12:22:39] [PASSED] ttm_bo_unreserve_pinned
[12:22:39] [PASSED] ttm_bo_unreserve_bulk
[12:22:39] [PASSED] ttm_bo_fini_basic
[12:22:39] [PASSED] ttm_bo_fini_shared_resv
[12:22:39] [PASSED] ttm_bo_pin_basic
[12:22:39] [PASSED] ttm_bo_pin_unpin_resource
[12:22:39] [PASSED] ttm_bo_multiple_pin_one_unpin
[12:22:39] ===================== [PASSED] ttm_bo ======================
[12:22:39] ============== ttm_bo_validate (21 subtests) ===============
[12:22:39] ============== ttm_bo_init_reserved_sys_man ===============
[12:22:39] [PASSED] Buffer object for userspace
[12:22:39] [PASSED] Kernel buffer object
[12:22:39] [PASSED] Shared buffer object
[12:22:39] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[12:22:39] ============== ttm_bo_init_reserved_mock_man ==============
[12:22:39] [PASSED] Buffer object for userspace
[12:22:39] [PASSED] Kernel buffer object
[12:22:39] [PASSED] Shared buffer object
[12:22:39] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[12:22:39] [PASSED] ttm_bo_init_reserved_resv
[12:22:39] ================== ttm_bo_validate_basic ==================
[12:22:39] [PASSED] Buffer object for userspace
[12:22:39] [PASSED] Kernel buffer object
[12:22:39] [PASSED] Shared buffer object
[12:22:39] ============== [PASSED] ttm_bo_validate_basic ==============
[12:22:39] [PASSED] ttm_bo_validate_invalid_placement
[12:22:39] ============= ttm_bo_validate_same_placement ==============
[12:22:39] [PASSED] System manager
[12:22:39] [PASSED] VRAM manager
[12:22:39] ========= [PASSED] ttm_bo_validate_same_placement ==========
[12:22:39] [PASSED] ttm_bo_validate_failed_alloc
[12:22:39] [PASSED] ttm_bo_validate_pinned
[12:22:39] [PASSED] ttm_bo_validate_busy_placement
[12:22:39] ================ ttm_bo_validate_multihop =================
[12:22:39] [PASSED] Buffer object for userspace
[12:22:39] [PASSED] Kernel buffer object
[12:22:39] [PASSED] Shared buffer object
[12:22:39] ============ [PASSED] ttm_bo_validate_multihop =============
[12:22:39] ========== ttm_bo_validate_no_placement_signaled ==========
[12:22:39] [PASSED] Buffer object in system domain, no page vector
[12:22:39] [PASSED] Buffer object in system domain with an existing page vector
[12:22:39] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[12:22:39] ======== ttm_bo_validate_no_placement_not_signaled ========
[12:22:39] [PASSED] Buffer object for userspace
[12:22:39] [PASSED] Kernel buffer object
[12:22:39] [PASSED] Shared buffer object
[12:22:39] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[12:22:39] [PASSED] ttm_bo_validate_move_fence_signaled
[12:22:39] ========= ttm_bo_validate_move_fence_not_signaled =========
[12:22:39] [PASSED] Waits for GPU
[12:22:39] [PASSED] Tries to lock straight away
[12:22:39] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[12:22:39] [PASSED] ttm_bo_validate_happy_evict
[12:22:39] [PASSED] ttm_bo_validate_all_pinned_evict
[12:22:39] [PASSED] ttm_bo_validate_allowed_only_evict
[12:22:39] [PASSED] ttm_bo_validate_deleted_evict
[12:22:39] [PASSED] ttm_bo_validate_busy_domain_evict
[12:22:39] [PASSED] ttm_bo_validate_evict_gutting
[12:22:39] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[12:22:39] ================= [PASSED] ttm_bo_validate =================
[12:22:39] ============================================================
[12:22:39] Testing complete. Ran 101 tests: passed: 101
[12:22:39] Elapsed time: 11.310s total, 1.704s configuring, 9.390s building, 0.177s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
2025-10-23 12:04 ` Ville Syrjälä
@ 2025-10-23 12:27 ` Nautiyal, Ankit K
2025-10-23 12:45 ` Nautiyal, Ankit K
2025-10-23 14:40 ` Ville Syrjälä
0 siblings, 2 replies; 16+ messages in thread
From: Nautiyal, Ankit K @ 2025-10-23 12:27 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe, jouni.hogander
On 10/23/2025 5:34 PM, Ville Syrjälä wrote:
> On Thu, Oct 23, 2025 at 01:46:14PM +0530, Ankit Nautiyal wrote:
>> Currently the EMP_AS_SDP_TL is set to vrr.vsync_start which is
>> incorrect.
>>
>> As per Bspec:71197 the transmission line must be within the SCL +
>> guardband region. Before guardband optimization, guradband was same as
>> vblank length so EMP_AS_SDP_TL set with vrr.sync_start was falling in
>> this region and it was not giving an issue.
>>
>> Now with optimized guardband, this is falling outside the SCL +
>> guardband region and since the same transmission line is used by VSC SDP
>> also, this results in PSR timeout issues.
>>
>> Further restrictions on the position of the transmission line:
>> For DP/eDP, if there is a set context latency (SCL) window, then it
>> cannot be the first line of SCL
>> For DP/eDP, if there is no SCL window, then it cannot be the first line of
>> the Delayed V. Blank
>>
>> Fix the EMP_AS_SDP_TL to VTOTAL - (delayed vblank_start - SCL + 1)
>> Internally the HW computes the value as VTOTAL - EMP_AS_SDP_TL.
>>
>> Fixes: e1123e617e51 ("drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDP")
>> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Cc: Jouni Högander <jouni.hogander@intel.com>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
>> 1 file changed, 9 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 92fb72b56f16..dd81d2133aba 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -655,18 +655,24 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
>> {
>> struct intel_display *display = to_intel_display(crtc_state);
>> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>> + int transmission_line;
>>
>> /*
>> * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
>> * double buffering point and transmission line for VRR packets for
>> * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
>> * Since currently we support VRR only for DP/eDP, so this is programmed
>> - * to for Adaptive Sync SDP to Vsync start.
>> + * for Adaptive Sync SDP.
>> */
>> - if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
>> + if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) {
>> + transmission_line = adjusted_mode->crtc_vtotal - (adjusted_mode->crtc_vblank_start -
>> + crtc_state->set_context_latency +
>> + 1);
>> intel_de_write(display,
>> EMP_AS_SDP_TL(display, cpu_transcoder),
>> - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
>> + EMP_AS_SDP_DB_TL(transmission_line));
>> + }
> Pretty sure we are expected to send it at vsync_start.
Hmm.. then do we need to move vsync_start too similar to vblank_start
for optimized guardband?
If we do not move vsync_start, and set the transmission line to
vsync_start, it will never fall in the region SCL + guardband with a
reduced guardband.
Meaning effectively the guardband will be full vblank length.
Regards,
Ankit
>> }
>>
>> static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
>> --
>> 2.45.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
2025-10-23 12:27 ` Nautiyal, Ankit K
@ 2025-10-23 12:45 ` Nautiyal, Ankit K
2025-10-23 14:40 ` Ville Syrjälä
1 sibling, 0 replies; 16+ messages in thread
From: Nautiyal, Ankit K @ 2025-10-23 12:45 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe, jouni.hogander
On 10/23/2025 5:57 PM, Nautiyal, Ankit K wrote:
>
> On 10/23/2025 5:34 PM, Ville Syrjälä wrote:
>> On Thu, Oct 23, 2025 at 01:46:14PM +0530, Ankit Nautiyal wrote:
>>> Currently the EMP_AS_SDP_TL is set to vrr.vsync_start which is
>>> incorrect.
>>>
>>> As per Bspec:71197 the transmission line must be within the SCL +
>>> guardband region. Before guardband optimization, guradband was same as
>>> vblank length so EMP_AS_SDP_TL set with vrr.sync_start was falling in
>>> this region and it was not giving an issue.
>>>
>>> Now with optimized guardband, this is falling outside the SCL +
>>> guardband region and since the same transmission line is used by VSC
>>> SDP
>>> also, this results in PSR timeout issues.
>>>
>>> Further restrictions on the position of the transmission line:
>>> For DP/eDP, if there is a set context latency (SCL) window, then it
>>> cannot be the first line of SCL
>>> For DP/eDP, if there is no SCL window, then it cannot be the first
>>> line of
>>> the Delayed V. Blank
>>>
>>> Fix the EMP_AS_SDP_TL to VTOTAL - (delayed vblank_start - SCL + 1)
>>> Internally the HW computes the value as VTOTAL - EMP_AS_SDP_TL.
>>>
>>> Fixes: e1123e617e51 ("drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS
>>> SDP")
>>> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> Cc: Jouni Högander <jouni.hogander@intel.com>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
>>> 1 file changed, 9 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
>>> b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> index 92fb72b56f16..dd81d2133aba 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> @@ -655,18 +655,24 @@ void
>>> intel_vrr_set_db_point_and_transmission_line(const struct
>>> intel_crtc_state
>>> {
>>> struct intel_display *display = to_intel_display(crtc_state);
>>> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>>> + const struct drm_display_mode *adjusted_mode =
>>> &crtc_state->hw.adjusted_mode;
>>> + int transmission_line;
>>> /*
>>> * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for
>>> programming
>>> * double buffering point and transmission line for VRR
>>> packets for
>>> * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
>>> * Since currently we support VRR only for DP/eDP, so this is
>>> programmed
>>> - * to for Adaptive Sync SDP to Vsync start.
>>> + * for Adaptive Sync SDP.
>>> */
>>> - if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >=
>>> 20)
>>> + if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >=
>>> 20) {
>>> + transmission_line = adjusted_mode->crtc_vtotal -
>>> (adjusted_mode->crtc_vblank_start -
>>> + crtc_state->set_context_latency +
>>> + 1);
>>> intel_de_write(display,
>>> EMP_AS_SDP_TL(display, cpu_transcoder),
>>> - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
>>> + EMP_AS_SDP_DB_TL(transmission_line));
>>> + }
>> Pretty sure we are expected to send it at vsync_start.
>
> Hmm.. then do we need to move vsync_start too similar to vblank_start
> for optimized guardband?
>
> If we do not move vsync_start, and set the transmission line to
> vsync_start, it will never fall in the region SCL + guardband with a
> reduced guardband.
Technically for AS_SDP case with optimized guardband, we can increase
SCL lines such that it starts at vsync _start and guardband is reduced,
but I am not sure if it is right.
-Ankit
>
> Meaning effectively the guardband will be full vblank length.
>
>
> Regards,
>
> Ankit
>
>
>>> }
>>> static int intel_vrr_hw_vmin(const struct intel_crtc_state
>>> *crtc_state)
>>> --
>>> 2.45.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
2025-10-23 8:16 [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP Ankit Nautiyal
` (2 preceding siblings ...)
2025-10-23 12:22 ` ✓ CI.KUnit: success for " Patchwork
@ 2025-10-23 13:05 ` Patchwork
2025-10-23 20:28 ` ✗ Xe.CI.Full: failure " Patchwork
4 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2025-10-23 13:05 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 880 bytes --]
== Series Details ==
Series: drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
URL : https://patchwork.freedesktop.org/series/156410/
State : success
== Summary ==
CI Bug Log - changes from xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7_BAT -> xe-pw-156410v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7 -> xe-pw-156410v1
IGT_8595: 8595
xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7: 7d2b8257998e069f9db25e43941b83eab2dc4cd7
xe-pw-156410v1: 156410v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/index.html
[-- Attachment #2: Type: text/html, Size: 1428 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
2025-10-23 12:27 ` Nautiyal, Ankit K
2025-10-23 12:45 ` Nautiyal, Ankit K
@ 2025-10-23 14:40 ` Ville Syrjälä
2025-10-23 15:07 ` Nautiyal, Ankit K
2025-10-23 15:08 ` Ville Syrjälä
1 sibling, 2 replies; 16+ messages in thread
From: Ville Syrjälä @ 2025-10-23 14:40 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx, intel-xe, jouni.hogander
On Thu, Oct 23, 2025 at 05:57:02PM +0530, Nautiyal, Ankit K wrote:
>
> On 10/23/2025 5:34 PM, Ville Syrjälä wrote:
> > On Thu, Oct 23, 2025 at 01:46:14PM +0530, Ankit Nautiyal wrote:
> >> Currently the EMP_AS_SDP_TL is set to vrr.vsync_start which is
> >> incorrect.
> >>
> >> As per Bspec:71197 the transmission line must be within the SCL +
> >> guardband region. Before guardband optimization, guradband was same as
> >> vblank length so EMP_AS_SDP_TL set with vrr.sync_start was falling in
> >> this region and it was not giving an issue.
> >>
> >> Now with optimized guardband, this is falling outside the SCL +
> >> guardband region and since the same transmission line is used by VSC SDP
> >> also, this results in PSR timeout issues.
> >>
> >> Further restrictions on the position of the transmission line:
> >> For DP/eDP, if there is a set context latency (SCL) window, then it
> >> cannot be the first line of SCL
> >> For DP/eDP, if there is no SCL window, then it cannot be the first line of
> >> the Delayed V. Blank
> >>
> >> Fix the EMP_AS_SDP_TL to VTOTAL - (delayed vblank_start - SCL + 1)
> >> Internally the HW computes the value as VTOTAL - EMP_AS_SDP_TL.
> >>
> >> Fixes: e1123e617e51 ("drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDP")
> >> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >> Cc: Jouni Högander <jouni.hogander@intel.com>
> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
> >> 1 file changed, 9 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> >> index 92fb72b56f16..dd81d2133aba 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> >> @@ -655,18 +655,24 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
> >> {
> >> struct intel_display *display = to_intel_display(crtc_state);
> >> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> >> + int transmission_line;
> >>
> >> /*
> >> * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
> >> * double buffering point and transmission line for VRR packets for
> >> * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
> >> * Since currently we support VRR only for DP/eDP, so this is programmed
> >> - * to for Adaptive Sync SDP to Vsync start.
> >> + * for Adaptive Sync SDP.
> >> */
> >> - if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
> >> + if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) {
> >> + transmission_line = adjusted_mode->crtc_vtotal - (adjusted_mode->crtc_vblank_start -
> >> + crtc_state->set_context_latency +
> >> + 1);
> >> intel_de_write(display,
> >> EMP_AS_SDP_TL(display, cpu_transcoder),
> >> - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> >> + EMP_AS_SDP_DB_TL(transmission_line));
> >> + }
> > Pretty sure we are expected to send it at vsync_start.
>
> Hmm.. then do we need to move vsync_start too similar to vblank_start
> for optimized guardband?
The vsync pulse location is dictated by the timings.
>
> If we do not move vsync_start, and set the transmission line to
> vsync_start, it will never fall in the region SCL + guardband with a
> reduced guardband.
Only if the vsync pulse is early in the vblank. That's up to the
display.
>
> Meaning effectively the guardband will be full vblank length.
>
>
> Regards,
>
> Ankit
>
>
> >> }
> >>
> >> static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
> >> --
> >> 2.45.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
2025-10-23 14:40 ` Ville Syrjälä
@ 2025-10-23 15:07 ` Nautiyal, Ankit K
2025-10-23 16:57 ` Ville Syrjälä
2025-10-23 15:08 ` Ville Syrjälä
1 sibling, 1 reply; 16+ messages in thread
From: Nautiyal, Ankit K @ 2025-10-23 15:07 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe, jouni.hogander
On 10/23/2025 8:10 PM, Ville Syrjälä wrote:
> On Thu, Oct 23, 2025 at 05:57:02PM +0530, Nautiyal, Ankit K wrote:
>> On 10/23/2025 5:34 PM, Ville Syrjälä wrote:
>>> On Thu, Oct 23, 2025 at 01:46:14PM +0530, Ankit Nautiyal wrote:
>>>> Currently the EMP_AS_SDP_TL is set to vrr.vsync_start which is
>>>> incorrect.
>>>>
>>>> As per Bspec:71197 the transmission line must be within the SCL +
>>>> guardband region. Before guardband optimization, guradband was same as
>>>> vblank length so EMP_AS_SDP_TL set with vrr.sync_start was falling in
>>>> this region and it was not giving an issue.
>>>>
>>>> Now with optimized guardband, this is falling outside the SCL +
>>>> guardband region and since the same transmission line is used by VSC SDP
>>>> also, this results in PSR timeout issues.
>>>>
>>>> Further restrictions on the position of the transmission line:
>>>> For DP/eDP, if there is a set context latency (SCL) window, then it
>>>> cannot be the first line of SCL
>>>> For DP/eDP, if there is no SCL window, then it cannot be the first line of
>>>> the Delayed V. Blank
>>>>
>>>> Fix the EMP_AS_SDP_TL to VTOTAL - (delayed vblank_start - SCL + 1)
>>>> Internally the HW computes the value as VTOTAL - EMP_AS_SDP_TL.
>>>>
>>>> Fixes: e1123e617e51 ("drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDP")
>>>> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> Cc: Jouni Högander <jouni.hogander@intel.com>
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
>>>> 1 file changed, 9 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>>>> index 92fb72b56f16..dd81d2133aba 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>>>> @@ -655,18 +655,24 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
>>>> {
>>>> struct intel_display *display = to_intel_display(crtc_state);
>>>> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>>>> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>>>> + int transmission_line;
>>>>
>>>> /*
>>>> * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
>>>> * double buffering point and transmission line for VRR packets for
>>>> * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
>>>> * Since currently we support VRR only for DP/eDP, so this is programmed
>>>> - * to for Adaptive Sync SDP to Vsync start.
>>>> + * for Adaptive Sync SDP.
>>>> */
>>>> - if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
>>>> + if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) {
>>>> + transmission_line = adjusted_mode->crtc_vtotal - (adjusted_mode->crtc_vblank_start -
>>>> + crtc_state->set_context_latency +
>>>> + 1);
>>>> intel_de_write(display,
>>>> EMP_AS_SDP_TL(display, cpu_transcoder),
>>>> - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
>>>> + EMP_AS_SDP_DB_TL(transmission_line));
>>>> + }
>>> Pretty sure we are expected to send it at vsync_start.
>> Hmm.. then do we need to move vsync_start too similar to vblank_start
>> for optimized guardband?
> The vsync pulse location is dictated by the timings.
Hmm... then with transmission line set as vsync_start, with a reduced
guardband we might need to increase the SCL so that vsync_start is more
or less inside the SCL + guardband.
So, if the panel supports AS_SDP while optimizing the guardband we
increase the SCL for this.
-Ankit
>
>> If we do not move vsync_start, and set the transmission line to
>> vsync_start, it will never fall in the region SCL + guardband with a
>> reduced guardband.
> Only if the vsync pulse is early in the vblank. That's up to the
> display.
>
>> Meaning effectively the guardband will be full vblank length.
>>
>>
>> Regards,
>>
>> Ankit
>>
>>
>>>> }
>>>>
>>>> static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
>>>> --
>>>> 2.45.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
2025-10-23 14:40 ` Ville Syrjälä
2025-10-23 15:07 ` Nautiyal, Ankit K
@ 2025-10-23 15:08 ` Ville Syrjälä
2025-10-24 4:00 ` Nautiyal, Ankit K
2025-10-24 12:39 ` Ville Syrjälä
1 sibling, 2 replies; 16+ messages in thread
From: Ville Syrjälä @ 2025-10-23 15:08 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx, intel-xe, jouni.hogander
On Thu, Oct 23, 2025 at 05:40:09PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 23, 2025 at 05:57:02PM +0530, Nautiyal, Ankit K wrote:
> >
> > On 10/23/2025 5:34 PM, Ville Syrjälä wrote:
> > > On Thu, Oct 23, 2025 at 01:46:14PM +0530, Ankit Nautiyal wrote:
> > >> Currently the EMP_AS_SDP_TL is set to vrr.vsync_start which is
> > >> incorrect.
> > >>
> > >> As per Bspec:71197 the transmission line must be within the SCL +
> > >> guardband region. Before guardband optimization, guradband was same as
> > >> vblank length so EMP_AS_SDP_TL set with vrr.sync_start was falling in
> > >> this region and it was not giving an issue.
> > >>
> > >> Now with optimized guardband, this is falling outside the SCL +
> > >> guardband region and since the same transmission line is used by VSC SDP
> > >> also, this results in PSR timeout issues.
> > >>
> > >> Further restrictions on the position of the transmission line:
> > >> For DP/eDP, if there is a set context latency (SCL) window, then it
> > >> cannot be the first line of SCL
> > >> For DP/eDP, if there is no SCL window, then it cannot be the first line of
> > >> the Delayed V. Blank
> > >>
> > >> Fix the EMP_AS_SDP_TL to VTOTAL - (delayed vblank_start - SCL + 1)
> > >> Internally the HW computes the value as VTOTAL - EMP_AS_SDP_TL.
> > >>
> > >> Fixes: e1123e617e51 ("drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDP")
> > >> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > >> Cc: Jouni Högander <jouni.hogander@intel.com>
> > >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > >> ---
> > >> drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
> > >> 1 file changed, 9 insertions(+), 3 deletions(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> > >> index 92fb72b56f16..dd81d2133aba 100644
> > >> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > >> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > >> @@ -655,18 +655,24 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
> > >> {
> > >> struct intel_display *display = to_intel_display(crtc_state);
> > >> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > >> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> > >> + int transmission_line;
> > >>
> > >> /*
> > >> * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
> > >> * double buffering point and transmission line for VRR packets for
> > >> * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
> > >> * Since currently we support VRR only for DP/eDP, so this is programmed
> > >> - * to for Adaptive Sync SDP to Vsync start.
> > >> + * for Adaptive Sync SDP.
> > >> */
> > >> - if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
> > >> + if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) {
> > >> + transmission_line = adjusted_mode->crtc_vtotal - (adjusted_mode->crtc_vblank_start -
> > >> + crtc_state->set_context_latency +
> > >> + 1);
> > >> intel_de_write(display,
> > >> EMP_AS_SDP_TL(display, cpu_transcoder),
> > >> - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> > >> + EMP_AS_SDP_DB_TL(transmission_line));
> > >> + }
> > > Pretty sure we are expected to send it at vsync_start.
> >
> > Hmm.. then do we need to move vsync_start too similar to vblank_start
> > for optimized guardband?
>
> The vsync pulse location is dictated by the timings.
>
> >
> > If we do not move vsync_start, and set the transmission line to
> > vsync_start, it will never fall in the region SCL + guardband with a
> > reduced guardband.
>
> Only if the vsync pulse is early in the vblank. That's up to the
> display.
Oh and I think we should get rid of that 'assume_all_enabled' stuff
for the AS SDP, and account for it only when actually needed.
Which I *think* means PCON or panel replay with AUX-less ALPM.
There's also that t1 vs. t2 setup time thing for the panel replay,
which seems to be telling me that we could sometimes transmit the
AS SDP later. But if I'm reading that right we have to switch to the
t1 (vsync) transmission line whenever we switch to live frame mode,
which I presume can happen basically at any time. So maybe we can't
actually use that t2 transmission line.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
2025-10-23 15:07 ` Nautiyal, Ankit K
@ 2025-10-23 16:57 ` Ville Syrjälä
0 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjälä @ 2025-10-23 16:57 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx, intel-xe, jouni.hogander
On Thu, Oct 23, 2025 at 08:37:14PM +0530, Nautiyal, Ankit K wrote:
>
> On 10/23/2025 8:10 PM, Ville Syrjälä wrote:
> > On Thu, Oct 23, 2025 at 05:57:02PM +0530, Nautiyal, Ankit K wrote:
> >> On 10/23/2025 5:34 PM, Ville Syrjälä wrote:
> >>> On Thu, Oct 23, 2025 at 01:46:14PM +0530, Ankit Nautiyal wrote:
> >>>> Currently the EMP_AS_SDP_TL is set to vrr.vsync_start which is
> >>>> incorrect.
> >>>>
> >>>> As per Bspec:71197 the transmission line must be within the SCL +
> >>>> guardband region. Before guardband optimization, guradband was same as
> >>>> vblank length so EMP_AS_SDP_TL set with vrr.sync_start was falling in
> >>>> this region and it was not giving an issue.
> >>>>
> >>>> Now with optimized guardband, this is falling outside the SCL +
> >>>> guardband region and since the same transmission line is used by VSC SDP
> >>>> also, this results in PSR timeout issues.
> >>>>
> >>>> Further restrictions on the position of the transmission line:
> >>>> For DP/eDP, if there is a set context latency (SCL) window, then it
> >>>> cannot be the first line of SCL
> >>>> For DP/eDP, if there is no SCL window, then it cannot be the first line of
> >>>> the Delayed V. Blank
> >>>>
> >>>> Fix the EMP_AS_SDP_TL to VTOTAL - (delayed vblank_start - SCL + 1)
> >>>> Internally the HW computes the value as VTOTAL - EMP_AS_SDP_TL.
> >>>>
> >>>> Fixes: e1123e617e51 ("drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDP")
> >>>> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >>>> Cc: Jouni Högander <jouni.hogander@intel.com>
> >>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >>>> ---
> >>>> drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
> >>>> 1 file changed, 9 insertions(+), 3 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> >>>> index 92fb72b56f16..dd81d2133aba 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> >>>> @@ -655,18 +655,24 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
> >>>> {
> >>>> struct intel_display *display = to_intel_display(crtc_state);
> >>>> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >>>> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> >>>> + int transmission_line;
> >>>>
> >>>> /*
> >>>> * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
> >>>> * double buffering point and transmission line for VRR packets for
> >>>> * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
> >>>> * Since currently we support VRR only for DP/eDP, so this is programmed
> >>>> - * to for Adaptive Sync SDP to Vsync start.
> >>>> + * for Adaptive Sync SDP.
> >>>> */
> >>>> - if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
> >>>> + if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) {
> >>>> + transmission_line = adjusted_mode->crtc_vtotal - (adjusted_mode->crtc_vblank_start -
> >>>> + crtc_state->set_context_latency +
> >>>> + 1);
> >>>> intel_de_write(display,
> >>>> EMP_AS_SDP_TL(display, cpu_transcoder),
> >>>> - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> >>>> + EMP_AS_SDP_DB_TL(transmission_line));
> >>>> + }
> >>> Pretty sure we are expected to send it at vsync_start.
> >> Hmm.. then do we need to move vsync_start too similar to vblank_start
> >> for optimized guardband?
> > The vsync pulse location is dictated by the timings.
>
> Hmm... then with transmission line set as vsync_start, with a reduced
> guardband we might need to increase the SCL so that vsync_start is more
> or less inside the SCL + guardband.
>
> So, if the panel supports AS_SDP while optimizing the guardband we
> increase the SCL for this.
From the vblank evasion pov the easiest thing would be to make
delayed vblank match vsync start exactly, and then bump SCL up one
line to deal with whatever PSR issue there is. But that wouldn't
allow us to use the max guardband, so I guess not really an option.
So at the very least we do need to allow guardband > vsync_start,
but that actually already has a vblank evasion issue because we
might be past the delayed vblank but not yet at vsync start when
we write the registers. Fixing that for the DSB should be pretty
easy, but for the MMIO path it'll take more thinking...
And the guardband < vsync_start case I guess could be made to work
as well. The MMIO vblank evasion would need to be updated to evade
the SCL window when the AS SDP needs reprogramming (or at least
evade starting from vsync_start). IIRC the DSB vblank evasion
evades the entire SCL window anyway so should already be fine.
But that last point actually means that the deadline for a commit
is anyway defined by the start of SCL, so not sure there's any actual
benefit from stretching the SCL rather than the guardband.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ Xe.CI.Full: failure for drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
2025-10-23 8:16 [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP Ankit Nautiyal
` (3 preceding siblings ...)
2025-10-23 13:05 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-10-23 20:28 ` Patchwork
4 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2025-10-23 20:28 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 33335 bytes --]
== Series Details ==
Series: drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
URL : https://patchwork.freedesktop.org/series/156410/
State : failure
== Summary ==
CI Bug Log - changes from xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7_FULL -> xe-pw-156410v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-156410v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-156410v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-156410v1_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@xe_configfs@ctx-restore-mid-bb-invalid:
- shard-bmg: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-4/igt@xe_configfs@ctx-restore-mid-bb-invalid.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-8/igt@xe_configfs@ctx-restore-mid-bb-invalid.html
Known issues
------------
Here are the changes found in xe-pw-156410v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@x-tiled-8bpp-rotate-90:
- shard-dg2-set2: NOTRUN -> [SKIP][3] ([Intel XE#316])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-dg2-set2: NOTRUN -> [SKIP][4] ([Intel XE#607])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-433/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-dg2-set2: NOTRUN -> [SKIP][5] ([Intel XE#1124]) +5 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-463/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
* igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p:
- shard-dg2-set2: NOTRUN -> [SKIP][6] ([Intel XE#2191])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][7] ([Intel XE#787]) +41 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-6.html
* igt@kms_ccs@bad-pixel-format-yf-tiled-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][8] ([Intel XE#455] / [Intel XE#787]) +11 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-433/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#2652] / [Intel XE#787]) +11 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2.html
* igt@kms_cdclk@plane-scaling@pipe-b-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][10] ([Intel XE#4416]) +3 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html
* igt@kms_chamelium_color@ctm-limited-range:
- shard-dg2-set2: NOTRUN -> [SKIP][11] ([Intel XE#306])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@kms_chamelium_color@ctm-limited-range.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- shard-dg2-set2: NOTRUN -> [SKIP][12] ([Intel XE#373]) +2 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_content_protection@srm@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][13] ([Intel XE#1178])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-5/igt@kms_content_protection@srm@pipe-a-dp-2.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-bmg: [PASS][14] -> [SKIP][15] ([Intel XE#2291]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-bmg: [PASS][16] -> [FAIL][17] ([Intel XE#5299])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_dp_link_training@uhbr-sst:
- shard-dg2-set2: NOTRUN -> [SKIP][18] ([Intel XE#4356])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@kms_dp_link_training@uhbr-sst.html
* igt@kms_feature_discovery@display-3x:
- shard-dg2-set2: NOTRUN -> [SKIP][19] ([Intel XE#703])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@kms_feature_discovery@display-3x.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-bmg: [PASS][20] -> [SKIP][21] ([Intel XE#2316]) +5 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-8/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@flip-vs-suspend@d-hdmi-a1:
- shard-adlp: [PASS][22] -> [DMESG-WARN][23] ([Intel XE#4543]) +1 other test dmesg-warn
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-adlp-9/igt@kms_flip@flip-vs-suspend@d-hdmi-a1.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-adlp-2/igt@kms_flip@flip-vs-suspend@d-hdmi-a1.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-x:
- shard-adlp: [PASS][24] -> [DMESG-FAIL][25] ([Intel XE#4543])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-x.html
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-x.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-x:
- shard-adlp: [PASS][26] -> [FAIL][27] ([Intel XE#1874])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-x.html
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-x.html
* igt@kms_frontbuffer_tracking@drrs-suspend:
- shard-dg2-set2: NOTRUN -> [SKIP][28] ([Intel XE#651]) +9 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-dg2-set2: NOTRUN -> [SKIP][29] ([Intel XE#653]) +10 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][30] ([Intel XE#6312]) +2 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt.html
* igt@kms_joiner@basic-force-ultra-joiner:
- shard-dg2-set2: NOTRUN -> [SKIP][31] ([Intel XE#2925])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-463/igt@kms_joiner@basic-force-ultra-joiner.html
* igt@kms_joiner@basic-ultra-joiner:
- shard-dg2-set2: NOTRUN -> [SKIP][32] ([Intel XE#2927])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@kms_joiner@basic-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-bmg: [PASS][33] -> [SKIP][34] ([Intel XE#3012])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-1/igt@kms_joiner@invalid-modeset-force-big-joiner.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_plane_multiple@2x-tiling-x:
- shard-bmg: [PASS][35] -> [SKIP][36] ([Intel XE#4596])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-8/igt@kms_plane_multiple@2x-tiling-x.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-x.html
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-bmg: [PASS][37] -> [SKIP][38] ([Intel XE#2571])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-8/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-6/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
- shard-dg2-set2: NOTRUN -> [SKIP][39] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-dg2-set2: NOTRUN -> [SKIP][40] ([Intel XE#1122] / [Intel XE#1406])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@fbc-psr2-primary-render:
- shard-dg2-set2: NOTRUN -> [SKIP][41] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +4 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@kms_psr@fbc-psr2-primary-render.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-bmg: [PASS][42] -> [SKIP][43] ([Intel XE#1435]) +1 other test skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-8/igt@kms_setmode@clone-exclusive-crtc.html
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-6/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_tv_load_detect@load-detect:
- shard-dg2-set2: NOTRUN -> [SKIP][44] ([Intel XE#330])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-433/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vblank@ts-continuation-dpms-suspend:
- shard-adlp: [PASS][45] -> [DMESG-WARN][46] ([Intel XE#2953] / [Intel XE#4173]) +3 other tests dmesg-warn
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-adlp-8/igt@kms_vblank@ts-continuation-dpms-suspend.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-adlp-4/igt@kms_vblank@ts-continuation-dpms-suspend.html
* igt@kms_vrr@flipline:
- shard-dg2-set2: NOTRUN -> [SKIP][47] ([Intel XE#455]) +3 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@kms_vrr@flipline.html
* igt@xe_copy_basic@mem-copy-linear-0xfd:
- shard-dg2-set2: NOTRUN -> [SKIP][48] ([Intel XE#1123])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@xe_copy_basic@mem-copy-linear-0xfd.html
* igt@xe_copy_basic@mem-set-linear-0xfffe:
- shard-dg2-set2: NOTRUN -> [SKIP][49] ([Intel XE#1126])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-433/igt@xe_copy_basic@mem-set-linear-0xfffe.html
* igt@xe_eu_stall@blocking-read:
- shard-dg2-set2: NOTRUN -> [SKIP][50] ([Intel XE#5626])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-463/igt@xe_eu_stall@blocking-read.html
* igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][51] ([Intel XE#288]) +7 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm.html
* igt@xe_exec_sip_eudebug@breakpoint-waitsip:
- shard-dg2-set2: NOTRUN -> [SKIP][52] ([Intel XE#4837]) +3 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@xe_exec_sip_eudebug@breakpoint-waitsip.html
* igt@xe_exec_system_allocator@threads-many-stride-mmap-remap-eocheck:
- shard-dg2-set2: NOTRUN -> [SKIP][53] ([Intel XE#4915]) +126 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-463/igt@xe_exec_system_allocator@threads-many-stride-mmap-remap-eocheck.html
* igt@xe_oa@oa-unit-exclusive-stream-sample-oa:
- shard-dg2-set2: NOTRUN -> [SKIP][54] ([Intel XE#3573]) +2 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-433/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html
* igt@xe_pxp@pxp-termination-key-update-post-suspend:
- shard-dg2-set2: NOTRUN -> [SKIP][55] ([Intel XE#4733]) +1 other test skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-433/igt@xe_pxp@pxp-termination-key-update-post-suspend.html
* igt@xe_query@multigpu-query-invalid-cs-cycles:
- shard-dg2-set2: NOTRUN -> [SKIP][56] ([Intel XE#944])
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@xe_query@multigpu-query-invalid-cs-cycles.html
* igt@xe_sriov_auto_provisioning@fair-allocation:
- shard-dg2-set2: NOTRUN -> [SKIP][57] ([Intel XE#4130])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-434/igt@xe_sriov_auto_provisioning@fair-allocation.html
#### Possible fixes ####
* igt@kms_atomic_transition@plane-all-transition@pipe-b-dp-4:
- shard-dg2-set2: [INCOMPLETE][58] -> [PASS][59] +1 other test pass
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-dg2-435/igt@kms_atomic_transition@plane-all-transition@pipe-b-dp-4.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-433/igt@kms_atomic_transition@plane-all-transition@pipe-b-dp-4.html
* igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
- shard-bmg: [SKIP][60] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-bmg: [SKIP][62] ([Intel XE#2291]) -> [PASS][63] +2 other tests pass
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-5/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_dp_linktrain_fallback@dp-fallback:
- shard-bmg: [SKIP][64] ([Intel XE#4294]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-6/igt@kms_dp_linktrain_fallback@dp-fallback.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-5/igt@kms_dp_linktrain_fallback@dp-fallback.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-bmg: [SKIP][66] ([Intel XE#2316]) -> [PASS][67] +8 other tests pass
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-6/igt@kms_flip@2x-nonexisting-fb.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-1/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: [FAIL][68] ([Intel XE#301]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-lnl: [FAIL][70] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][71] +1 other test pass
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
- shard-adlp: [DMESG-WARN][72] ([Intel XE#4543]) -> [PASS][73] +6 other tests pass
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-adlp-9/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-adlp-2/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y:
- shard-adlp: [DMESG-FAIL][74] ([Intel XE#4543]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html
* igt@kms_hdr@static-toggle:
- shard-bmg: [SKIP][76] ([Intel XE#1503]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-6/igt@kms_hdr@static-toggle.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-1/igt@kms_hdr@static-toggle.html
* igt@kms_plane_multiple@tiling-x:
- shard-adlp: [DMESG-WARN][78] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][79] +2 other tests pass
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-adlp-1/igt@kms_plane_multiple@tiling-x.html
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-adlp-3/igt@kms_plane_multiple@tiling-x.html
* igt@kms_setmode@invalid-clone-single-crtc:
- shard-bmg: [SKIP][80] ([Intel XE#1435]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-6/igt@kms_setmode@invalid-clone-single-crtc.html
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-1/igt@kms_setmode@invalid-clone-single-crtc.html
* igt@kms_vrr@cmrr@pipe-a-edp-1:
- shard-lnl: [FAIL][82] ([Intel XE#4459]) -> [PASS][83] +1 other test pass
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-lnl-3/igt@kms_vrr@cmrr@pipe-a-edp-1.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-lnl-5/igt@kms_vrr@cmrr@pipe-a-edp-1.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
- shard-dg2-set2: [DMESG-WARN][84] ([Intel XE#5893]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-dg2-432/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-dg2-435/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
* igt@xe_pm@s2idle-multiple-execs:
- shard-adlp: [DMESG-WARN][86] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4504]) -> [PASS][87] +1 other test pass
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-adlp-4/igt@xe_pm@s2idle-multiple-execs.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-adlp-6/igt@xe_pm@s2idle-multiple-execs.html
#### Warnings ####
* igt@kms_async_flips@async-flip-dpms@pipe-b-hdmi-a-1:
- shard-adlp: [DMESG-FAIL][88] ([Intel XE#4543]) -> [DMESG-WARN][89] ([Intel XE#4543]) +1 other test dmesg-warn
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-adlp-8/igt@kms_async_flips@async-flip-dpms@pipe-b-hdmi-a-1.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-adlp-4/igt@kms_async_flips@async-flip-dpms@pipe-b-hdmi-a-1.html
* igt@kms_content_protection@atomic-dpms:
- shard-bmg: [FAIL][90] ([Intel XE#1178]) -> [SKIP][91] ([Intel XE#2341])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-1/igt@kms_content_protection@atomic-dpms.html
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@srm:
- shard-bmg: [SKIP][92] ([Intel XE#2341]) -> [FAIL][93] ([Intel XE#1178])
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-6/igt@kms_content_protection@srm.html
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-5/igt@kms_content_protection@srm.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-adlp: [DMESG-WARN][94] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543]) -> [DMESG-WARN][95] ([Intel XE#2953] / [Intel XE#4173])
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-adlp-3/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1:
- shard-adlp: [DMESG-WARN][96] ([Intel XE#4543]) -> [DMESG-WARN][97] ([Intel XE#2953] / [Intel XE#4173])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-adlp-3/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-blt:
- shard-bmg: [SKIP][98] ([Intel XE#2312]) -> [SKIP][99] ([Intel XE#2311]) +10 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-blt.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
- shard-bmg: [SKIP][100] ([Intel XE#2311]) -> [SKIP][101] ([Intel XE#2312]) +14 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-mmap-wc:
- shard-adlp: [DMESG-FAIL][102] ([Intel XE#4543]) -> [FAIL][103] ([Intel XE#5671])
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-adlp-1/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-mmap-wc.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-adlp-3/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
- shard-bmg: [SKIP][104] ([Intel XE#2312]) -> [SKIP][105] ([Intel XE#5390]) +4 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
- shard-bmg: [SKIP][106] ([Intel XE#5390]) -> [SKIP][107] ([Intel XE#2312]) +6 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
- shard-bmg: [SKIP][108] ([Intel XE#2312]) -> [SKIP][109] ([Intel XE#2313]) +11 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
- shard-bmg: [SKIP][110] ([Intel XE#2313]) -> [SKIP][111] ([Intel XE#2312]) +10 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][112] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][113] ([Intel XE#3544])
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-7/igt@kms_hdr@brightness-with-hdr.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-bmg: [ABORT][114] ([Intel XE#4917] / [Intel XE#5466] / [Intel XE#5530]) -> [ABORT][115] ([Intel XE#5466] / [Intel XE#5530])
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7/shard-bmg-2/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/shard-bmg-5/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
[Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2571
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
[Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4294
[Intel XE#4356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4356
[Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
[Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
[Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
[Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
[Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
[Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
[Intel XE#5671]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5671
[Intel XE#5893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5893
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7 -> xe-pw-156410v1
IGT_8595: 8595
xe-3971-7d2b8257998e069f9db25e43941b83eab2dc4cd7: 7d2b8257998e069f9db25e43941b83eab2dc4cd7
xe-pw-156410v1: 156410v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156410v1/index.html
[-- Attachment #2: Type: text/html, Size: 38380 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
2025-10-23 15:08 ` Ville Syrjälä
@ 2025-10-24 4:00 ` Nautiyal, Ankit K
2025-10-24 12:00 ` Ville Syrjälä
2025-10-24 12:39 ` Ville Syrjälä
1 sibling, 1 reply; 16+ messages in thread
From: Nautiyal, Ankit K @ 2025-10-24 4:00 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe, jouni.hogander
On 10/23/2025 8:38 PM, Ville Syrjälä wrote:
> On Thu, Oct 23, 2025 at 05:40:09PM +0300, Ville Syrjälä wrote:
>> On Thu, Oct 23, 2025 at 05:57:02PM +0530, Nautiyal, Ankit K wrote:
>>> On 10/23/2025 5:34 PM, Ville Syrjälä wrote:
>>>> On Thu, Oct 23, 2025 at 01:46:14PM +0530, Ankit Nautiyal wrote:
>>>>> Currently the EMP_AS_SDP_TL is set to vrr.vsync_start which is
>>>>> incorrect.
>>>>>
>>>>> As per Bspec:71197 the transmission line must be within the SCL +
>>>>> guardband region. Before guardband optimization, guradband was same as
>>>>> vblank length so EMP_AS_SDP_TL set with vrr.sync_start was falling in
>>>>> this region and it was not giving an issue.
>>>>>
>>>>> Now with optimized guardband, this is falling outside the SCL +
>>>>> guardband region and since the same transmission line is used by VSC SDP
>>>>> also, this results in PSR timeout issues.
>>>>>
>>>>> Further restrictions on the position of the transmission line:
>>>>> For DP/eDP, if there is a set context latency (SCL) window, then it
>>>>> cannot be the first line of SCL
>>>>> For DP/eDP, if there is no SCL window, then it cannot be the first line of
>>>>> the Delayed V. Blank
>>>>>
>>>>> Fix the EMP_AS_SDP_TL to VTOTAL - (delayed vblank_start - SCL + 1)
>>>>> Internally the HW computes the value as VTOTAL - EMP_AS_SDP_TL.
>>>>>
>>>>> Fixes: e1123e617e51 ("drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDP")
>>>>> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>>> Cc: Jouni Högander <jouni.hogander@intel.com>
>>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
>>>>> 1 file changed, 9 insertions(+), 3 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>>>>> index 92fb72b56f16..dd81d2133aba 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>>>>> @@ -655,18 +655,24 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
>>>>> {
>>>>> struct intel_display *display = to_intel_display(crtc_state);
>>>>> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>>>>> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>>>>> + int transmission_line;
>>>>>
>>>>> /*
>>>>> * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
>>>>> * double buffering point and transmission line for VRR packets for
>>>>> * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
>>>>> * Since currently we support VRR only for DP/eDP, so this is programmed
>>>>> - * to for Adaptive Sync SDP to Vsync start.
>>>>> + * for Adaptive Sync SDP.
>>>>> */
>>>>> - if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
>>>>> + if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) {
>>>>> + transmission_line = adjusted_mode->crtc_vtotal - (adjusted_mode->crtc_vblank_start -
>>>>> + crtc_state->set_context_latency +
>>>>> + 1);
>>>>> intel_de_write(display,
>>>>> EMP_AS_SDP_TL(display, cpu_transcoder),
>>>>> - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
>>>>> + EMP_AS_SDP_DB_TL(transmission_line));
>>>>> + }
>>>> Pretty sure we are expected to send it at vsync_start.
>>> Hmm.. then do we need to move vsync_start too similar to vblank_start
>>> for optimized guardband?
>> The vsync pulse location is dictated by the timings.
>>
>>> If we do not move vsync_start, and set the transmission line to
>>> vsync_start, it will never fall in the region SCL + guardband with a
>>> reduced guardband.
>> Only if the vsync pulse is early in the vblank. That's up to the
>> display.
> Oh and I think we should get rid of that 'assume_all_enabled' stuff
> for the AS SDP, and account for it only when actually needed.
> Which I *think* means PCON or panel replay with AUX-less ALPM.
Currently we are enabling it for VRR and CMRR with AVT and FAVT mode
respectively.
>
> There's also that t1 vs. t2 setup time thing for the panel replay,
> which seems to be telling me that we could sometimes transmit the
> AS SDP later. But if I'm reading that right we have to switch to the
> t1 (vsync) transmission line whenever we switch to live frame mode,
> which I presume can happen basically at any time. So maybe we can't
> actually use that t2 transmission line.
I think it will be prudent to set the min guardband to accommodate the
vsync_start as done by Jouni in patch:
https://patchwork.freedesktop.org/patch/682984/?series=156341&rev=2
Need to remove 'assume_all_enabled' as mentioned, and have some check
for whether AS_SDP is supported (and can be enabled later).
To have this check is a bit challenging in intel_dp_sdp_min_guardband()
since its called from
intel_crtc_compute_config()->intel_vrr_compute_guardband() also, where
we do not have obvious way to get intel_dp.
Regards,
Ankit
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
2025-10-24 4:00 ` Nautiyal, Ankit K
@ 2025-10-24 12:00 ` Ville Syrjälä
0 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjälä @ 2025-10-24 12:00 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx, intel-xe, jouni.hogander
On Fri, Oct 24, 2025 at 09:30:26AM +0530, Nautiyal, Ankit K wrote:
>
> On 10/23/2025 8:38 PM, Ville Syrjälä wrote:
> > On Thu, Oct 23, 2025 at 05:40:09PM +0300, Ville Syrjälä wrote:
> >> On Thu, Oct 23, 2025 at 05:57:02PM +0530, Nautiyal, Ankit K wrote:
> >>> On 10/23/2025 5:34 PM, Ville Syrjälä wrote:
> >>>> On Thu, Oct 23, 2025 at 01:46:14PM +0530, Ankit Nautiyal wrote:
> >>>>> Currently the EMP_AS_SDP_TL is set to vrr.vsync_start which is
> >>>>> incorrect.
> >>>>>
> >>>>> As per Bspec:71197 the transmission line must be within the SCL +
> >>>>> guardband region. Before guardband optimization, guradband was same as
> >>>>> vblank length so EMP_AS_SDP_TL set with vrr.sync_start was falling in
> >>>>> this region and it was not giving an issue.
> >>>>>
> >>>>> Now with optimized guardband, this is falling outside the SCL +
> >>>>> guardband region and since the same transmission line is used by VSC SDP
> >>>>> also, this results in PSR timeout issues.
> >>>>>
> >>>>> Further restrictions on the position of the transmission line:
> >>>>> For DP/eDP, if there is a set context latency (SCL) window, then it
> >>>>> cannot be the first line of SCL
> >>>>> For DP/eDP, if there is no SCL window, then it cannot be the first line of
> >>>>> the Delayed V. Blank
> >>>>>
> >>>>> Fix the EMP_AS_SDP_TL to VTOTAL - (delayed vblank_start - SCL + 1)
> >>>>> Internally the HW computes the value as VTOTAL - EMP_AS_SDP_TL.
> >>>>>
> >>>>> Fixes: e1123e617e51 ("drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDP")
> >>>>> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >>>>> Cc: Jouni Högander <jouni.hogander@intel.com>
> >>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >>>>> ---
> >>>>> drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
> >>>>> 1 file changed, 9 insertions(+), 3 deletions(-)
> >>>>>
> >>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> >>>>> index 92fb72b56f16..dd81d2133aba 100644
> >>>>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> >>>>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> >>>>> @@ -655,18 +655,24 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
> >>>>> {
> >>>>> struct intel_display *display = to_intel_display(crtc_state);
> >>>>> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >>>>> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> >>>>> + int transmission_line;
> >>>>>
> >>>>> /*
> >>>>> * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
> >>>>> * double buffering point and transmission line for VRR packets for
> >>>>> * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
> >>>>> * Since currently we support VRR only for DP/eDP, so this is programmed
> >>>>> - * to for Adaptive Sync SDP to Vsync start.
> >>>>> + * for Adaptive Sync SDP.
> >>>>> */
> >>>>> - if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
> >>>>> + if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) {
> >>>>> + transmission_line = adjusted_mode->crtc_vtotal - (adjusted_mode->crtc_vblank_start -
> >>>>> + crtc_state->set_context_latency +
> >>>>> + 1);
> >>>>> intel_de_write(display,
> >>>>> EMP_AS_SDP_TL(display, cpu_transcoder),
> >>>>> - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> >>>>> + EMP_AS_SDP_DB_TL(transmission_line));
> >>>>> + }
> >>>> Pretty sure we are expected to send it at vsync_start.
> >>> Hmm.. then do we need to move vsync_start too similar to vblank_start
> >>> for optimized guardband?
> >> The vsync pulse location is dictated by the timings.
> >>
> >>> If we do not move vsync_start, and set the transmission line to
> >>> vsync_start, it will never fall in the region SCL + guardband with a
> >>> reduced guardband.
> >> Only if the vsync pulse is early in the vblank. That's up to the
> >> display.
> > Oh and I think we should get rid of that 'assume_all_enabled' stuff
> > for the AS SDP, and account for it only when actually needed.
> > Which I *think* means PCON or panel replay with AUX-less ALPM.
>
> Currently we are enabling it for VRR and CMRR with AVT and FAVT mode
> respectively.
>
>
> >
> > There's also that t1 vs. t2 setup time thing for the panel replay,
> > which seems to be telling me that we could sometimes transmit the
> > AS SDP later. But if I'm reading that right we have to switch to the
> > t1 (vsync) transmission line whenever we switch to live frame mode,
> > which I presume can happen basically at any time. So maybe we can't
> > actually use that t2 transmission line.
>
> I think it will be prudent to set the min guardband to accommodate the
> vsync_start as done by Jouni in patch:
> https://patchwork.freedesktop.org/patch/682984/?series=156341&rev=2
>
> Need to remove 'assume_all_enabled' as mentioned, and have some check
> for whether AS_SDP is supported (and can be enabled later).
I'm thinking we should perhaps just enable it always if
PCON+vrr.in_range or PR+AUX-less ALPM is possible. Although I'm
not sure if we're actually handling all the VRR details correctly
with PCONs, and not sure we even can due to the disaster that is
HDMI 2.1...
> To have this check is a bit challenging in intel_dp_sdp_min_guardband()
> since its called from
> intel_crtc_compute_config()->intel_vrr_compute_guardband() also, where
> we do not have obvious way to get intel_dp.
.compute_config() should be able to decide whether AS SDP is needed or
not.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
2025-10-23 15:08 ` Ville Syrjälä
2025-10-24 4:00 ` Nautiyal, Ankit K
@ 2025-10-24 12:39 ` Ville Syrjälä
2025-10-27 11:07 ` Nautiyal, Ankit K
1 sibling, 1 reply; 16+ messages in thread
From: Ville Syrjälä @ 2025-10-24 12:39 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx, intel-xe, jouni.hogander
On Thu, Oct 23, 2025 at 06:08:47PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 23, 2025 at 05:40:09PM +0300, Ville Syrjälä wrote:
> > On Thu, Oct 23, 2025 at 05:57:02PM +0530, Nautiyal, Ankit K wrote:
> > >
> > > On 10/23/2025 5:34 PM, Ville Syrjälä wrote:
> > > > On Thu, Oct 23, 2025 at 01:46:14PM +0530, Ankit Nautiyal wrote:
> > > >> Currently the EMP_AS_SDP_TL is set to vrr.vsync_start which is
> > > >> incorrect.
> > > >>
> > > >> As per Bspec:71197 the transmission line must be within the SCL +
> > > >> guardband region. Before guardband optimization, guradband was same as
> > > >> vblank length so EMP_AS_SDP_TL set with vrr.sync_start was falling in
> > > >> this region and it was not giving an issue.
> > > >>
> > > >> Now with optimized guardband, this is falling outside the SCL +
> > > >> guardband region and since the same transmission line is used by VSC SDP
> > > >> also, this results in PSR timeout issues.
> > > >>
> > > >> Further restrictions on the position of the transmission line:
> > > >> For DP/eDP, if there is a set context latency (SCL) window, then it
> > > >> cannot be the first line of SCL
> > > >> For DP/eDP, if there is no SCL window, then it cannot be the first line of
> > > >> the Delayed V. Blank
> > > >>
> > > >> Fix the EMP_AS_SDP_TL to VTOTAL - (delayed vblank_start - SCL + 1)
> > > >> Internally the HW computes the value as VTOTAL - EMP_AS_SDP_TL.
> > > >>
> > > >> Fixes: e1123e617e51 ("drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDP")
> > > >> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > >> Cc: Jouni Högander <jouni.hogander@intel.com>
> > > >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > >> ---
> > > >> drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
> > > >> 1 file changed, 9 insertions(+), 3 deletions(-)
> > > >>
> > > >> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> > > >> index 92fb72b56f16..dd81d2133aba 100644
> > > >> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > > >> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > > >> @@ -655,18 +655,24 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
> > > >> {
> > > >> struct intel_display *display = to_intel_display(crtc_state);
> > > >> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > > >> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> > > >> + int transmission_line;
> > > >>
> > > >> /*
> > > >> * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
> > > >> * double buffering point and transmission line for VRR packets for
> > > >> * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
> > > >> * Since currently we support VRR only for DP/eDP, so this is programmed
> > > >> - * to for Adaptive Sync SDP to Vsync start.
> > > >> + * for Adaptive Sync SDP.
> > > >> */
> > > >> - if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
> > > >> + if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) {
> > > >> + transmission_line = adjusted_mode->crtc_vtotal - (adjusted_mode->crtc_vblank_start -
> > > >> + crtc_state->set_context_latency +
> > > >> + 1);
> > > >> intel_de_write(display,
> > > >> EMP_AS_SDP_TL(display, cpu_transcoder),
> > > >> - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> > > >> + EMP_AS_SDP_DB_TL(transmission_line));
> > > >> + }
> > > > Pretty sure we are expected to send it at vsync_start.
> > >
> > > Hmm.. then do we need to move vsync_start too similar to vblank_start
> > > for optimized guardband?
> >
> > The vsync pulse location is dictated by the timings.
> >
> > >
> > > If we do not move vsync_start, and set the transmission line to
> > > vsync_start, it will never fall in the region SCL + guardband with a
> > > reduced guardband.
> >
> > Only if the vsync pulse is early in the vblank. That's up to the
> > display.
>
> Oh and I think we should get rid of that 'assume_all_enabled' stuff
> for the AS SDP, and account for it only when actually needed.
> Which I *think* means PCON or panel replay with AUX-less ALPM.
>
> There's also that t1 vs. t2 setup time thing for the panel replay,
> which seems to be telling me that we could sometimes transmit the
> AS SDP later. But if I'm reading that right we have to switch to the
> t1 (vsync) transmission line whenever we switch to live frame mode,
> which I presume can happen basically at any time. So maybe we can't
> actually use that t2 transmission line.
Ah, apparently we have to always put t1 into EMP_AS_SDP_TL, and
there's some other logic for panel replay to use t2 when possible.
But since it's all dynamic we have to use t1 when calculating the
guardband/SCL.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP
2025-10-24 12:39 ` Ville Syrjälä
@ 2025-10-27 11:07 ` Nautiyal, Ankit K
0 siblings, 0 replies; 16+ messages in thread
From: Nautiyal, Ankit K @ 2025-10-27 11:07 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe, jouni.hogander
On 10/24/2025 6:09 PM, Ville Syrjälä wrote:
> On Thu, Oct 23, 2025 at 06:08:47PM +0300, Ville Syrjälä wrote:
>> On Thu, Oct 23, 2025 at 05:40:09PM +0300, Ville Syrjälä wrote:
>>> On Thu, Oct 23, 2025 at 05:57:02PM +0530, Nautiyal, Ankit K wrote:
>>>> On 10/23/2025 5:34 PM, Ville Syrjälä wrote:
>>>>> On Thu, Oct 23, 2025 at 01:46:14PM +0530, Ankit Nautiyal wrote:
>>>>>> Currently the EMP_AS_SDP_TL is set to vrr.vsync_start which is
>>>>>> incorrect.
>>>>>>
>>>>>> As per Bspec:71197 the transmission line must be within the SCL +
>>>>>> guardband region. Before guardband optimization, guradband was same as
>>>>>> vblank length so EMP_AS_SDP_TL set with vrr.sync_start was falling in
>>>>>> this region and it was not giving an issue.
>>>>>>
>>>>>> Now with optimized guardband, this is falling outside the SCL +
>>>>>> guardband region and since the same transmission line is used by VSC SDP
>>>>>> also, this results in PSR timeout issues.
>>>>>>
>>>>>> Further restrictions on the position of the transmission line:
>>>>>> For DP/eDP, if there is a set context latency (SCL) window, then it
>>>>>> cannot be the first line of SCL
>>>>>> For DP/eDP, if there is no SCL window, then it cannot be the first line of
>>>>>> the Delayed V. Blank
>>>>>>
>>>>>> Fix the EMP_AS_SDP_TL to VTOTAL - (delayed vblank_start - SCL + 1)
>>>>>> Internally the HW computes the value as VTOTAL - EMP_AS_SDP_TL.
>>>>>>
>>>>>> Fixes: e1123e617e51 ("drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDP")
>>>>>> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>>>> Cc: Jouni Högander <jouni.hogander@intel.com>
>>>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>>>> ---
>>>>>> drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
>>>>>> 1 file changed, 9 insertions(+), 3 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>>>>>> index 92fb72b56f16..dd81d2133aba 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>>>>>> @@ -655,18 +655,24 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
>>>>>> {
>>>>>> struct intel_display *display = to_intel_display(crtc_state);
>>>>>> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>>>>>> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>>>>>> + int transmission_line;
>>>>>>
>>>>>> /*
>>>>>> * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
>>>>>> * double buffering point and transmission line for VRR packets for
>>>>>> * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
>>>>>> * Since currently we support VRR only for DP/eDP, so this is programmed
>>>>>> - * to for Adaptive Sync SDP to Vsync start.
>>>>>> + * for Adaptive Sync SDP.
>>>>>> */
>>>>>> - if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
>>>>>> + if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) {
>>>>>> + transmission_line = adjusted_mode->crtc_vtotal - (adjusted_mode->crtc_vblank_start -
>>>>>> + crtc_state->set_context_latency +
>>>>>> + 1);
>>>>>> intel_de_write(display,
>>>>>> EMP_AS_SDP_TL(display, cpu_transcoder),
>>>>>> - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
>>>>>> + EMP_AS_SDP_DB_TL(transmission_line));
>>>>>> + }
>>>>> Pretty sure we are expected to send it at vsync_start.
>>>> Hmm.. then do we need to move vsync_start too similar to vblank_start
>>>> for optimized guardband?
>>> The vsync pulse location is dictated by the timings.
>>>
>>>> If we do not move vsync_start, and set the transmission line to
>>>> vsync_start, it will never fall in the region SCL + guardband with a
>>>> reduced guardband.
>>> Only if the vsync pulse is early in the vblank. That's up to the
>>> display.
>> Oh and I think we should get rid of that 'assume_all_enabled' stuff
>> for the AS SDP, and account for it only when actually needed.
>> Which I *think* means PCON or panel replay with AUX-less ALPM.
>>
>> There's also that t1 vs. t2 setup time thing for the panel replay,
>> which seems to be telling me that we could sometimes transmit the
>> AS SDP later. But if I'm reading that right we have to switch to the
>> t1 (vsync) transmission line whenever we switch to live frame mode,
>> which I presume can happen basically at any time. So maybe we can't
>> actually use that t2 transmission line.
> Ah, apparently we have to always put t1 into EMP_AS_SDP_TL, and
> there's some other logic for panel replay to use t2 when possible.
> But since it's all dynamic we have to use t1 when calculating the
> guardband/SCL.
Yeah t2 will be taken up by HW based on PR_ALPM_CTL adaptive sync SDP
position (to have either t1/t2 or t1 always or t2 always) and also what
we send in AS SDP payload wrt to Fixed Vtotal, Fixed AVG VTotal mode.
I agree with your suggestion above. For PCON, VRR support still needs
work so perhaps we can skip that. Makes sense to always enable AS SDP
when Panel replay with Auxless-ALPM is supported.
With that we can use Jouni's patch to increase the guardband such that
Vsync falls in the required region [1], effectively
`crtc_state->vrr.vsync_start + 1`.
I was trying with the above changes suggested, sent also to trybot [2].
But now I see that we have a problem with LRR on such panels.
When switching to lower mode with LRR, the `vsync_start` changes, which
results in guardband being changed.
So seamless switch to the required lower mode cannot take place. :-(
[1] https://patchwork.freedesktop.org/patch/682984/?series=156341&rev=2
[2] https://patchwork.freedesktop.org/series/156569/
Regards,
Ankit
>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2025-10-27 11:07 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-23 8:16 [PATCH] drm/i915/vrr: Fix transmission line for Adaptive Sync SDP Ankit Nautiyal
2025-10-23 10:35 ` Hogander, Jouni
2025-10-23 12:04 ` Ville Syrjälä
2025-10-23 12:27 ` Nautiyal, Ankit K
2025-10-23 12:45 ` Nautiyal, Ankit K
2025-10-23 14:40 ` Ville Syrjälä
2025-10-23 15:07 ` Nautiyal, Ankit K
2025-10-23 16:57 ` Ville Syrjälä
2025-10-23 15:08 ` Ville Syrjälä
2025-10-24 4:00 ` Nautiyal, Ankit K
2025-10-24 12:00 ` Ville Syrjälä
2025-10-24 12:39 ` Ville Syrjälä
2025-10-27 11:07 ` Nautiyal, Ankit K
2025-10-23 12:22 ` ✓ CI.KUnit: success for " Patchwork
2025-10-23 13:05 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-23 20:28 ` ✗ Xe.CI.Full: failure " Patchwork
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