[PATCH v1 0/1] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms

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* [PATCH v1 0/1] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms
@ 2025-12-30 15:17 Anoop, Vijay
  2025-12-30 15:17 ` [PATCH v1 1/1] " Anoop, Vijay
                   ` (4 more replies)
  0 siblings, 5 replies; 8+ messages in thread
From: Anoop, Vijay @ 2025-12-30 15:17 UTC (permalink / raw)
  To: intel-xe
  Cc: umesh.nerlige.ramappa, badal.nilawar, rodrigo.vivi,
	aravind.iddamsetty, riana.tauro, anshuman.gupta, matthew.d.roper,
	michael.j.ruhl, paul.e.luse, mohamed.mansoor.v, kam.nasim

From: Anoop Vijay <anoop.c.vijay@intel.com>

This patch introduces System Controller (sysctrl) component for Intel Xe3p dGPU platforms.

This component provides the foundational infrastructure for communication
with the System Controller firmware using MKHI protocol over a mailbox interface.

Key features introduced:
- Detection and initialization of System Controller interface on Xe3p dGPU platforms
- Mailbox communication with System Controller firmware
- Fragmented message transfer for large command payloads

This implementation establishes the base for future System Controller feature
enablement and firmware command handling.

Anoop Vijay (1):
  drm/xe/sysctrl: Add system controller component for Xe3p dGPU
    platforms

 drivers/gpu/drm/xe/Makefile               |   2 +
 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h |  44 +++
 drivers/gpu/drm/xe/xe_device.c            |   5 +
 drivers/gpu/drm/xe/xe_device_types.h      |   6 +
 drivers/gpu/drm/xe/xe_pci.c               |   2 +
 drivers/gpu/drm/xe/xe_pci_types.h         |   1 +
 drivers/gpu/drm/xe/xe_sysctrl.c           |  64 ++++
 drivers/gpu/drm/xe/xe_sysctrl.h           |  13 +
 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c   | 438 ++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h   |  61 +++
 drivers/gpu/drm/xe/xe_sysctrl_types.h     |  25 ++
 11 files changed, 661 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.c
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_types.h

-- 
2.43.0


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v1 1/1] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms
  2025-12-30 15:17 [PATCH v1 0/1] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms Anoop, Vijay
@ 2025-12-30 15:17 ` Anoop, Vijay
  2025-12-30 23:36   ` Umesh Nerlige Ramappa
  2025-12-30 15:22 ` ✗ CI.checkpatch: warning for " Patchwork
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 8+ messages in thread
From: Anoop, Vijay @ 2025-12-30 15:17 UTC (permalink / raw)
  To: intel-xe
  Cc: umesh.nerlige.ramappa, badal.nilawar, rodrigo.vivi,
	aravind.iddamsetty, riana.tauro, anshuman.gupta, matthew.d.roper,
	michael.j.ruhl, paul.e.luse, mohamed.mansoor.v, kam.nasim

From: Anoop Vijay <anoop.c.vijay@intel.com>

Add a new system controller (sysctrl) component for Intel Xe3p dGPU platforms.

This component provides the foundational infrastructure for communication
with the System Controller firmware using MKHI protocol over a mailbox interface.

Key features introduced:
 - Detection and initialization of System Controller interface on Xe3p dGPU platforms
 - Mailbox communication with System Controller firmware
 - Fragmented message transfer for large command payloads

This implementation establishes the base for future System Controller feature
enablement and firmware command handling.

Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
---
 drivers/gpu/drm/xe/Makefile               |   2 +
 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h |  44 +++
 drivers/gpu/drm/xe/xe_device.c            |   5 +
 drivers/gpu/drm/xe/xe_device_types.h      |   6 +
 drivers/gpu/drm/xe/xe_pci.c               |   2 +
 drivers/gpu/drm/xe/xe_pci_types.h         |   1 +
 drivers/gpu/drm/xe/xe_sysctrl.c           |  64 ++++
 drivers/gpu/drm/xe/xe_sysctrl.h           |  13 +
 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c   | 438 ++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h   |  61 +++
 drivers/gpu/drm/xe/xe_sysctrl_types.h     |  25 ++
 11 files changed, 661 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.c
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_types.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 3315f93a35b2..cd03e4c53127 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -121,6 +121,8 @@ xe-y += xe_bb.o \
 	xe_step.o \
 	xe_survivability_mode.o \
 	xe_sync.o \
+	xe_sysctrl.o \
+	xe_sysctrl_mailbox.o \
 	xe_tile.o \
 	xe_tile_sysfs.o \
 	xe_tlb_inval.o \
diff --git a/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
new file mode 100644
index 000000000000..b31b6e24c18e
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_REGS_H_
+#define _XE_SYSCTRL_REGS_H_
+
+#include "xe_regs.h"
+
+#define SYSCTRL_BASE_OFFSET		0xDB000
+#define SYSCTRL_BASE			(SOC_BASE + SYSCTRL_BASE_OFFSET)
+#define SYSCTRL_MAILBOX_INDEX		0x03
+#define SC_BAR_LENGTH			0x1000
+
+#define SC_MB_CTRL			XE_REG(SYSCTRL_BASE + 0x10)
+#define   SC_MB_CTRL_RUN_BUSY		REG_BIT(31)
+#define   SC_MB_CTRL_IRQ		REG_BIT(30)
+#define   SC_MB_CTRL_RUN_BUSY_OUT	REG_BIT(29)
+#define   SC_MB_CTRL_PARAM3_MASK	REG_GENMASK(28, 24)
+#define   SC_MB_CTRL_PARAM2_MASK	REG_GENMASK(23, 16)
+#define   SC_MB_CTRL_PARAM1_MASK	REG_GENMASK(15, 8)
+#define   SC_MB_CTRL_COMMAND_MASK	REG_GENMASK(7, 0)
+
+#define SC_MB_DATA0			XE_REG(SYSCTRL_BASE + 0x14)
+#define SC_MB_DATA1			XE_REG(SYSCTRL_BASE + 0x18)
+#define SC_MB_DATA2			XE_REG(SYSCTRL_BASE + 0x1C)
+#define SC_MB_DATA3			XE_REG(SYSCTRL_BASE + 0x20)
+
+#define MKHI_FRAME_PHASE		REG_BIT(24)
+#define MKHI_FRAME_CURRENT_MASK		REG_GENMASK(21, 16)
+#define MKHI_FRAME_TOTAL_MASK		REG_GENMASK(13, 8)
+#define MKHI_FRAME_COMMAND_MASK		REG_GENMASK(7, 0)
+
+#define SC_MB_FRAME_SIZE		16
+#define SC_MB_MAX_FRAMES		64
+#define SC_MB_MAX_MESSAGE_SIZE		(SC_MB_FRAME_SIZE * SC_MB_MAX_FRAMES)
+#define SC_MKHI_COMMAND			5
+
+#define SC_MB_DEFAULT_TIMEOUT_MS	500
+#define SC_MB_RETRY_TIMEOUT_MS		20
+#define SC_MB_POLL_INTERVAL_US		100
+
+#endif /* _XE_SYSCTRL_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index e101d290b2a6..805d48dd954d 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -66,6 +66,7 @@
 #include "xe_survivability_mode.h"
 #include "xe_sriov.h"
 #include "xe_svm.h"
+#include "xe_sysctrl.h"
 #include "xe_tile.h"
 #include "xe_ttm_stolen_mgr.h"
 #include "xe_ttm_sys_mgr.h"
@@ -1032,6 +1033,10 @@ int xe_device_probe(struct xe_device *xe)
 	if (err)
 		goto err_unregister_display;
 
+	err = xe_sysctrl_init(xe);
+	if (err)
+		goto err_unregister_display;
+
 	err = xe_device_sysfs_init(xe);
 	if (err)
 		goto err_unregister_display;
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index a85be9ba175e..6295b2c35d4a 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -29,6 +29,7 @@
 #include "xe_sriov_vf_ccs_types.h"
 #include "xe_step_types.h"
 #include "xe_survivability_mode_types.h"
+#include "xe_sysctrl_types.h"
 #include "xe_tile_sriov_vf_types.h"
 #include "xe_validation.h"
 
@@ -340,6 +341,8 @@ struct xe_device {
 		u8 has_soc_remapper_telem:1;
 		/** @info.has_sriov: Supports SR-IOV */
 		u8 has_sriov:1;
+		/** @info.has_sysctrl: Supports System Controller */
+		u8 has_sysctrl:1;
 		/** @info.has_usm: Device has unified shared memory support */
 		u8 has_usm:1;
 		/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
@@ -606,6 +609,9 @@ struct xe_device {
 	/** @heci_gsc: graphics security controller */
 	struct xe_heci_gsc heci_gsc;
 
+	/** @sc: System Controller */
+	struct xe_sysctrl sc;
+
 	/** @nvm: discrete graphics non-volatile memory */
 	struct intel_dg_nvm_dev *nvm;
 
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 91e0553a8163..b6dc3030b673 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -426,6 +426,7 @@ static const struct xe_device_desc cri_desc = {
 	.has_soc_remapper_sysctrl = true,
 	.has_soc_remapper_telem = true,
 	.has_sriov = true,
+	.has_sysctrl = true,
 	.max_gt_per_tile = 2,
 	.require_force_probe = true,
 	.va_bits = 57,
@@ -701,6 +702,7 @@ static int xe_info_init_early(struct xe_device *xe,
 	xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
 	xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
 		desc->has_sriov;
+	xe->info.has_sysctrl = desc->has_sysctrl;
 	xe->info.has_mem_copy_instr = desc->has_mem_copy_instr;
 	xe->info.skip_guc_pc = desc->skip_guc_pc;
 	xe->info.skip_mtcfg = desc->skip_mtcfg;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 5f20f56571d1..53e44a32883d 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -56,6 +56,7 @@ struct xe_device_desc {
 	u8 has_soc_remapper_sysctrl:1;
 	u8 has_soc_remapper_telem:1;
 	u8 has_sriov:1;
+	u8 has_sysctrl:1;
 	u8 needs_scratch:1;
 	u8 skip_guc_pc:1;
 	u8 skip_mtcfg:1;
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
new file mode 100644
index 000000000000..9f3e0b1db380
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include "xe_sysctrl.h"
+
+#include <linux/device.h>
+#include <linux/mutex.h>
+
+#include <drm/drm_managed.h>
+
+#include "regs/xe_sysctrl_regs.h"
+#include "xe_device.h"
+#include "xe_printk.h"
+#include "xe_soc_remapper.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_types.h"
+
+static void xe_sysctrl_fini(void *arg)
+{
+	struct xe_sysctrl *sc = arg;
+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
+
+	if (!xe->soc_remapper.set_sysctrl_region)
+		return;
+
+	xe->soc_remapper.set_sysctrl_region(xe, 0);
+}
+
+/**
+ * xe_sysctrl_init - Initialize SC subsystem
+ * @xe: xe device instance
+ *
+ * Entry point for SC initialization, called from xe_device_probe().
+ * This function checks platform support and initializes the system controller.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int xe_sysctrl_init(struct xe_device *xe)
+{
+	struct xe_sysctrl *sc = &xe->sc;
+	int ret;
+
+	if (!xe->info.has_sysctrl)
+		return 0;
+
+	ret = devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, sc);
+	if (ret)
+		return ret;
+
+	if (!xe->soc_remapper.set_sysctrl_region)
+		return -ENODEV;
+
+	xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
+
+	ret = drmm_mutex_init(&xe->drm, &sc->cmd_lock);
+	if (ret)
+		return ret;
+
+	xe_sysctrl_mailbox_init(sc);
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
new file mode 100644
index 000000000000..f1ad12656e48
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_H_
+#define _XE_SYSCTRL_H_
+
+struct xe_device;
+
+int xe_sysctrl_init(struct xe_device *xe);
+
+#endif /* _XE_SYSCTRL_H_ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
new file mode 100644
index 000000000000..e9f4d4b13bb1
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
@@ -0,0 +1,438 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/errno.h>
+#include <linux/minmax.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include <drm/drm_print.h>
+
+#include "xe_device.h"
+#include "xe_mmio.h"
+#include "xe_pm.h"
+#include "xe_printk.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_types.h"
+#include "regs/xe_sysctrl_regs.h"
+
+static bool xe_sysctrl_mailbox_wait_bit_clear(struct xe_sysctrl *sc, u32 bit_mask,
+					      unsigned int timeout_ms)
+{
+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
+	int ret;
+
+	ret = xe_mmio_wait32_not(xe_root_tile_mmio(xe), SC_MB_CTRL, bit_mask, bit_mask,
+				 timeout_ms * 1000, NULL, false);
+
+	return ret == 0;
+}
+
+static bool xe_sysctrl_mailbox_wait_bit_set(struct xe_sysctrl *sc, u32 bit_mask,
+					    unsigned int timeout_ms)
+{
+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
+	int ret;
+
+	ret = xe_mmio_wait32(xe_root_tile_mmio(xe), SC_MB_CTRL, bit_mask, bit_mask,
+			     timeout_ms * 1000, NULL, false);
+
+	return ret == 0;
+}
+
+static int xe_sysctrl_mailbox_write_frame(struct xe_sysctrl *sc, const void *frame,
+					  size_t len)
+{
+	static const struct xe_reg data_regs[] = {
+		SC_MB_DATA0, SC_MB_DATA1, SC_MB_DATA2, SC_MB_DATA3
+	};
+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
+	const u8 *bytes = frame;
+	u32 reg_data;
+	size_t i;
+
+	if (len == 0 || len > SC_MB_FRAME_SIZE) {
+		xe_err(xe, "sysctrl: Invalid frame len: %zu\n", len);
+		return -EINVAL;
+	}
+
+	for (i = 0; i + sizeof(u32) <= len; i += sizeof(u32)) {
+		reg_data = *(const u32 *)(bytes + i);
+		xe_mmio_write32(xe_root_tile_mmio(xe), data_regs[i / sizeof(u32)], reg_data);
+	}
+
+	if (i < len) {
+		size_t remaining = len - i;
+		size_t j;
+
+		reg_data = 0;
+		for (j = 0; j < remaining; j++)
+			reg_data |= (u32)bytes[i + j] << (j * 8);
+
+		xe_mmio_write32(xe_root_tile_mmio(xe), data_regs[i / sizeof(u32)], reg_data);
+	}
+
+	return 0;
+}
+
+static int xe_sysctrl_mailbox_read_frame(struct xe_sysctrl *sc, void *frame,
+					 size_t len)
+{
+	static const struct xe_reg data_regs[] = {
+		SC_MB_DATA0, SC_MB_DATA1, SC_MB_DATA2, SC_MB_DATA3
+	};
+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
+	u8 *bytes = frame;
+	u32 reg_data;
+	size_t i;
+
+	if (len == 0 || len > SC_MB_FRAME_SIZE) {
+		xe_err(xe, "sysctrl: Invalid frame len: %zu\n", len);
+		return -EINVAL;
+	}
+
+	for (i = 0; i + sizeof(u32) <= len; i += sizeof(u32)) {
+		reg_data = xe_mmio_read32(xe_root_tile_mmio(xe), data_regs[i / sizeof(u32)]);
+		*(u32 *)(bytes + i) = reg_data;
+	}
+
+	if (i < len) {
+		size_t remaining = len - i;
+		size_t j;
+
+		reg_data = xe_mmio_read32(xe_root_tile_mmio(xe), data_regs[i / sizeof(u32)]);
+
+		for (j = 0; j < remaining; j++)
+			bytes[i + j] = (reg_data >> (j * 8)) & 0xFF;
+	}
+
+	return 0;
+}
+
+static void xe_sysctrl_mailbox_clear_response(struct xe_sysctrl *sc)
+{
+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
+	u32 ctrl_reg;
+
+	ctrl_reg = xe_mmio_read32(xe_root_tile_mmio(xe), SC_MB_CTRL);
+	ctrl_reg &= ~SC_MB_CTRL_RUN_BUSY_OUT;
+	xe_mmio_write32(xe_root_tile_mmio(xe), SC_MB_CTRL, ctrl_reg);
+}
+
+static int xe_sysctrl_mailbox_prepare_command(struct xe_sysctrl *sc,
+					      u8 group_id, u8 command,
+					       const void *data_in, size_t data_in_len,
+					       u8 **cmd_buffer, size_t *cmd_size)
+{
+	struct xe_sysctrl_mailbox_mkhi_msg_hdr *mkhi_hdr;
+	size_t size;
+	u8 *buffer;
+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
+
+	size = sizeof(*mkhi_hdr) + data_in_len;
+	if (size > SC_MB_MAX_MESSAGE_SIZE) {
+		xe_err(xe, "sysctrl: Message too large: %zu bytes\n", size);
+		return -EINVAL;
+	}
+
+	buffer = kmalloc(size, GFP_KERNEL);
+	if (!buffer)
+		return -ENOMEM;
+
+	mkhi_hdr = (struct xe_sysctrl_mailbox_mkhi_msg_hdr *)buffer;
+	mkhi_hdr->data = cpu_to_le32(FIELD_PREP(MKHI_HDR_GROUP_ID_MASK, group_id) |
+				      FIELD_PREP(MKHI_HDR_COMMAND_MASK, command & 0x7F) |
+				      FIELD_PREP(MKHI_HDR_IS_RESPONSE, 0) |
+				      FIELD_PREP(MKHI_HDR_RESERVED_MASK, 0) |
+				      FIELD_PREP(MKHI_HDR_RESULT_MASK, 0));
+
+	if (data_in && data_in_len)
+		memcpy(buffer + sizeof(*mkhi_hdr), data_in, data_in_len);
+
+	*cmd_buffer = buffer;
+	*cmd_size = size;
+
+	return 0;
+}
+
+static int xe_sysctrl_mailbox_send_frames(struct xe_sysctrl *sc, const u8 *cmd_buffer,
+					  size_t cmd_size, unsigned int timeout_ms)
+{
+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
+	u32 ctrl_reg, total_frames, frame;
+	size_t bytes_sent, frame_size;
+
+	total_frames = DIV_ROUND_UP(cmd_size, SC_MB_FRAME_SIZE);
+
+	if (!xe_sysctrl_mailbox_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
+		xe_err(xe, "sysctrl: Mailbox busy\n");
+		return -EBUSY;
+	}
+
+	sc->phase_bit ^= 1;
+
+	bytes_sent = 0;
+
+	for (frame = 0; frame < total_frames; frame++) {
+		frame_size = min(cmd_size - bytes_sent, (size_t)SC_MB_FRAME_SIZE);
+
+		if (xe_sysctrl_mailbox_write_frame(sc, cmd_buffer + bytes_sent, frame_size)) {
+			xe_err(xe, "sysctrl: Failed to write frame %u\n", frame);
+			return -EIO;
+		}
+
+		ctrl_reg = SC_MB_CTRL_RUN_BUSY |
+			   FIELD_PREP(MKHI_FRAME_CURRENT_MASK, frame) |
+			   FIELD_PREP(MKHI_FRAME_TOTAL_MASK, total_frames - 1) |
+			   FIELD_PREP(MKHI_FRAME_COMMAND_MASK, SC_MKHI_COMMAND) |
+			   (sc->phase_bit ? MKHI_FRAME_PHASE : 0);
+
+		xe_mmio_write32(xe_root_tile_mmio(xe), SC_MB_CTRL, ctrl_reg);
+
+		if (!xe_sysctrl_mailbox_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
+			xe_err(xe, "sysctrl: Frame %u acknowledgment timeout\n", frame);
+			return -ETIMEDOUT;
+		}
+
+		bytes_sent += frame_size;
+	}
+
+	return 0;
+}
+
+static int xe_sysctrl_mailbox_process_first_frame(struct xe_sysctrl *sc,
+						  const struct xe_sysctrl_mailbox_mkhi_msg_hdr *req_hdr,
+						  void *out,
+						  size_t frame_size,
+						  size_t *payload_bytes)
+{
+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
+	u32 frame_data[4];
+	struct xe_sysctrl_mailbox_mkhi_msg_hdr *resp_hdr;
+	size_t hdr_size = sizeof(*resp_hdr);
+	size_t payload_size;
+	int ret;
+
+	ret = xe_sysctrl_mailbox_read_frame(sc, frame_data, frame_size);
+	if (ret)
+		return ret;
+
+	resp_hdr = (struct xe_sysctrl_mailbox_mkhi_msg_hdr *)frame_data;
+
+	if (!XE_SYSCTRL_MKHI_HDR_IS_RESPONSE(resp_hdr) ||
+	    XE_SYSCTRL_MKHI_HDR_GROUP_ID(resp_hdr) != XE_SYSCTRL_MKHI_HDR_GROUP_ID(req_hdr) ||
+	    XE_SYSCTRL_MKHI_HDR_COMMAND(resp_hdr) != XE_SYSCTRL_MKHI_HDR_COMMAND(req_hdr)) {
+		xe_err(xe, "SC: Response header mismatch\n");
+		return -EPROTO;
+	}
+
+	if (XE_SYSCTRL_MKHI_HDR_RESULT(resp_hdr) != 0) {
+		xe_err(xe, "SC: Firmware error: 0x%02lx\n",
+		       XE_SYSCTRL_MKHI_HDR_RESULT(resp_hdr));
+		return -EIO;
+	}
+
+	payload_size = frame_size - hdr_size;
+	if (payload_size > 0)
+		memcpy(out, (u8 *)frame_data + hdr_size, payload_size);
+
+	*payload_bytes = payload_size;
+
+	xe_sysctrl_mailbox_clear_response(sc);
+
+	return 0;
+}
+
+static int xe_sysctrl_mailbox_process_frame(struct xe_sysctrl *sc,
+					    void *out, size_t frame_size,
+					     unsigned int timeout_ms)
+{
+	int ret;
+
+	if (!xe_sysctrl_mailbox_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms))
+		return -ETIMEDOUT;
+
+	ret = xe_sysctrl_mailbox_read_frame(sc, out, frame_size);
+	if (ret)
+		return ret;
+
+	xe_sysctrl_mailbox_clear_response(sc);
+
+	return 0;
+}
+
+static int xe_sysctrl_mailbox_receive_frames(struct xe_sysctrl *sc,
+					     const struct xe_sysctrl_mailbox_mkhi_msg_hdr *req_hdr,
+					      void *data_out, size_t data_out_len,
+					      size_t *rdata_len, unsigned int timeout_ms)
+{
+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
+	struct xe_sysctrl_mailbox_mkhi_msg_hdr *mkhi_hdr;
+	u32 ctrl_reg, total_frames, frame;
+	size_t hdr_size = sizeof(*mkhi_hdr);
+	u8 *out = data_out;
+	size_t received = 0;
+	size_t frame_size;
+	int ret;
+
+	if (!xe_sysctrl_mailbox_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
+		xe_err(xe, "sysctrl: Response frame 0 timeout\n");
+		return -ETIMEDOUT;
+	}
+
+	ctrl_reg = xe_mmio_read32(xe_root_tile_mmio(xe), SC_MB_CTRL);
+	total_frames = FIELD_GET(MKHI_FRAME_TOTAL_MASK, ctrl_reg) + 1;
+
+	if (total_frames == 1)
+		frame_size = min(hdr_size + data_out_len, (size_t)SC_MB_FRAME_SIZE);
+	else
+		frame_size = SC_MB_FRAME_SIZE;
+
+	ret = xe_sysctrl_mailbox_process_first_frame(sc, req_hdr, out, frame_size, &received);
+	if (ret)
+		return ret;
+
+	out += received;
+
+	for (frame = 1; frame < total_frames; frame++) {
+		size_t remaining = data_out_len - received;
+
+		frame_size = min_t(size_t, remaining, SC_MB_FRAME_SIZE);
+
+		ret = xe_sysctrl_mailbox_process_frame(sc, out, frame_size, timeout_ms);
+		if (ret) {
+			xe_err(xe, "sysctrl: Response frame %u timeout\n", frame);
+			return ret;
+		}
+
+		received += frame_size;
+		out += frame_size;
+	}
+
+	*rdata_len = received;
+
+	return 0;
+}
+
+static int xe_sysctrl_mailbox_send_command(struct xe_sysctrl *sc,
+					   const u8 *cmd_buffer, size_t cmd_size,
+					    void *data_out, size_t data_out_len,
+					    size_t *rdata_len, unsigned int timeout_ms)
+{
+	const struct xe_sysctrl_mailbox_mkhi_msg_hdr *mkhi_hdr;
+	size_t received;
+	int ret;
+
+	ret = xe_sysctrl_mailbox_send_frames(sc, cmd_buffer, cmd_size, timeout_ms);
+	if (ret)
+		return ret;
+
+	if (!data_out) {
+		if (rdata_len)
+			*rdata_len = 0;
+		return 0;
+	}
+
+	mkhi_hdr = (const struct xe_sysctrl_mailbox_mkhi_msg_hdr *)cmd_buffer;
+
+	ret = xe_sysctrl_mailbox_receive_frames(sc, mkhi_hdr, data_out, data_out_len,
+						&received, timeout_ms);
+	if (ret)
+		return ret;
+
+	if (rdata_len)
+		*rdata_len = received;
+
+	return 0;
+}
+
+/**
+ * xe_sysctrl_send_command - Send command to System Controller via mailbox
+ * @handle: XE device handle
+ * @cmd_buffer: Pointer to xe_sysctrl_mailbox_command structure
+ * @rdata_len: Pointer to store actual response data size (can be NULL)
+ *
+ * Send a command to the System Controller using MKHI protocol. Handles
+ * command preparation, fragmentation, transmission, and response reception.
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int xe_sysctrl_send_command(void *handle, void *cmd_buffer, size_t *rdata_len)
+{
+	struct xe_device *xe = handle;
+	struct xe_sysctrl *sc = &xe->sc;
+	struct xe_sysctrl_mailbox_command *cmd = cmd_buffer;
+	u8 *buffer = NULL;
+	size_t command_size = 0;
+	u8 group_id, command_code;
+	int ret = 0;
+
+	if (!xe || !cmd) {
+		if (xe)
+			xe_err(xe, "sysctrl: Invalid parameters\n");
+		return -EINVAL;
+	}
+
+	if (!xe->info.has_sysctrl)
+		return -ENODEV;
+
+	group_id = XE_SYSCTRL_APP_HDR_GROUP_ID(&cmd->header);
+	command_code = XE_SYSCTRL_APP_HDR_COMMAND(&cmd->header);
+
+	if (!cmd->data_in && cmd->data_in_len) {
+		xe_err(xe, "sysctrl: Invalid input parameters\n");
+		return -EINVAL;
+	}
+
+	if (!cmd->data_out && cmd->data_out_len) {
+		xe_err(xe, "sysctrl: Invalid output parameters\n");
+		return -EINVAL;
+	}
+
+	might_sleep();
+
+	ret = xe_sysctrl_mailbox_prepare_command(sc, group_id, command_code,
+						 cmd->data_in, cmd->data_in_len,
+						 &buffer, &command_size);
+	if (ret) {
+		xe_err(xe, "sysctrl: Failed to prepare command: %d\n", ret);
+		return ret;
+	}
+
+	xe_pm_runtime_get(xe);
+
+	guard(mutex)(&sc->cmd_lock);
+
+	ret = xe_sysctrl_mailbox_send_command(sc, buffer, command_size,
+					      cmd->data_out, cmd->data_out_len, rdata_len,
+					      SC_MB_DEFAULT_TIMEOUT_MS);
+	if (ret)
+		xe_err(xe, "sysctrl: Mailbox command failed: %d\n", ret);
+
+	xe_pm_runtime_put(xe);
+
+	kfree(buffer);
+
+	return ret;
+}
+
+/**
+ * xe_sysctrl_mailbox_init - Initialize the system controller mailbox state
+ * @sysctrl: System controller structure
+ */
+void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc)
+{
+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
+	u32 ctrl_reg;
+
+	ctrl_reg = xe_mmio_read32(xe_root_tile_mmio(xe), SC_MB_CTRL);
+	sc->phase_bit = (ctrl_reg & MKHI_FRAME_PHASE) ? 1 : 0;
+
+	xe_mmio_write32(xe_root_tile_mmio(xe), SC_MB_CTRL, 0);
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
new file mode 100644
index 000000000000..6380d1d68f8f
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __XE_SYSCTRL_MAILBOX_H__
+#define __XE_SYSCTRL_MAILBOX_H__
+
+#include <linux/bitfield.h>
+#include <linux/types.h>
+
+struct xe_sysctrl;
+
+#define MKHI_HDR_GROUP_ID_MASK		GENMASK(7, 0)
+#define MKHI_HDR_COMMAND_MASK		GENMASK(14, 8)
+#define MKHI_HDR_IS_RESPONSE		BIT(15)
+#define MKHI_HDR_RESERVED_MASK		GENMASK(23, 16)
+#define MKHI_HDR_RESULT_MASK		GENMASK(31, 24)
+
+struct xe_sysctrl_mailbox_mkhi_msg_hdr {
+	__le32 data;
+} __packed;
+
+#define APP_HDR_GROUP_ID_MASK		GENMASK(7, 0)
+#define APP_HDR_COMMAND_MASK		GENMASK(15, 8)
+#define APP_HDR_VERSION_MASK		GENMASK(23, 16)
+#define APP_HDR_RESERVED_MASK		GENMASK(31, 24)
+
+struct xe_sysctrl_mailbox_app_msg_hdr {
+	__le32 data;
+} __packed;
+
+#define XE_SYSCTRL_APP_HDR_GROUP_ID(hdr)	FIELD_GET(APP_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
+#define XE_SYSCTRL_APP_HDR_COMMAND(hdr)		FIELD_GET(APP_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
+#define XE_SYSCTRL_APP_HDR_VERSION(hdr)		FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_MKHI_HDR_GROUP_ID(hdr)	FIELD_GET(MKHI_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
+#define XE_SYSCTRL_MKHI_HDR_COMMAND(hdr)	FIELD_GET(MKHI_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
+#define XE_SYSCTRL_MKHI_HDR_IS_RESPONSE(hdr)	FIELD_GET(MKHI_HDR_IS_RESPONSE, le32_to_cpu((hdr)->data))
+#define XE_SYSCTRL_MKHI_HDR_RESULT(hdr)		FIELD_GET(MKHI_HDR_RESULT_MASK, le32_to_cpu((hdr)->data))
+
+/**
+ * struct xe_sysctrl_mailbox_command - System Controller mailbox command structure
+ */
+struct xe_sysctrl_mailbox_command {
+	/** @header: Application message header containing command information */
+	struct xe_sysctrl_mailbox_app_msg_hdr header;
+	/** @data_in: Pointer to input payload data (can be NULL if no input data) */
+	void *data_in;
+	/** @data_in_len: Size of input payload in bytes (0 if no input data) */
+	size_t data_in_len;
+	/** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
+	void *data_out;
+	/** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
+	size_t data_out_len;
+};
+
+void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
+int xe_sysctrl_send_command(void *handle, void *cmd_buffer, size_t *rdata_len);
+
+#endif /* __XE_SYSCTRL_MAILBOX_H__ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
new file mode 100644
index 000000000000..80e674cfa385
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_TYPES_H_
+#define _XE_SYSCTRL_TYPES_H_
+
+#include <linux/completion.h>
+#include <linux/mutex.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+/**
+ * struct xe_sysctrl - System Controller driver context
+ */
+struct xe_sysctrl {
+	/** @cmd_lock: Mutex protecting mailbox command operations */
+	struct mutex cmd_lock;
+
+	/** @phase_bit: MKHI message boundary phase toggle bit */
+	u32 phase_bit;
+};
+
+#endif /* _XE_SYSCTRL_TYPES_H_ */
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 8+ messages in thread

* ✗ CI.checkpatch: warning for drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms
  2025-12-30 15:17 [PATCH v1 0/1] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms Anoop, Vijay
  2025-12-30 15:17 ` [PATCH v1 1/1] " Anoop, Vijay
@ 2025-12-30 15:22 ` Patchwork
  2025-12-30 15:24 ` ✓ CI.KUnit: success " Patchwork
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2025-12-30 15:22 UTC (permalink / raw)
  To: Anoop, Vijay; +Cc: intel-xe

== Series Details ==

Series: drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms
URL   : https://patchwork.freedesktop.org/series/159554/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
99339247d1ae4378b24366da182e712bdc623311
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit e3057ab1ae0402acf51382bf2cc17d6f2aec7c10
Author: Anoop Vijay <anoop.c.vijay@intel.com>
Date:   Tue Dec 30 07:17:23 2025 -0800

    drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms
    
    Add a new system controller (sysctrl) component for Intel Xe3p dGPU platforms.
    
    This component provides the foundational infrastructure for communication
    with the System Controller firmware using MKHI protocol over a mailbox interface.
    
    Key features introduced:
     - Detection and initialization of System Controller interface on Xe3p dGPU platforms
     - Mailbox communication with System Controller firmware
     - Fragmented message transfer for large command payloads
    
    This implementation establishes the base for future System Controller feature
    enablement and firmware command handling.
    
    Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
+ /mt/dim checkpatch cbb25c38097a953da8605c68dd979be9a776ec83 drm-intel
e3057ab1ae04 drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms
-:7: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#7: 
Add a new system controller (sysctrl) component for Intel Xe3p dGPU platforms.

-:36: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#36: 
new file mode 100644

-:475: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#475: FILE: drivers/gpu/drm/xe/xe_sysctrl_mailbox.c:210:
+						  const struct xe_sysctrl_mailbox_mkhi_msg_hdr *req_hdr,

-:742: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#742: FILE: drivers/gpu/drm/xe/xe_sysctrl_mailbox.h:33:
+#define XE_SYSCTRL_APP_HDR_GROUP_ID(hdr)	FIELD_GET(APP_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))

-:743: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#743: FILE: drivers/gpu/drm/xe/xe_sysctrl_mailbox.h:34:
+#define XE_SYSCTRL_APP_HDR_COMMAND(hdr)		FIELD_GET(APP_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))

-:744: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#744: FILE: drivers/gpu/drm/xe/xe_sysctrl_mailbox.h:35:
+#define XE_SYSCTRL_APP_HDR_VERSION(hdr)		FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))

-:746: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#746: FILE: drivers/gpu/drm/xe/xe_sysctrl_mailbox.h:37:
+#define XE_SYSCTRL_MKHI_HDR_GROUP_ID(hdr)	FIELD_GET(MKHI_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))

-:747: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#747: FILE: drivers/gpu/drm/xe/xe_sysctrl_mailbox.h:38:
+#define XE_SYSCTRL_MKHI_HDR_COMMAND(hdr)	FIELD_GET(MKHI_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))

-:748: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#748: FILE: drivers/gpu/drm/xe/xe_sysctrl_mailbox.h:39:
+#define XE_SYSCTRL_MKHI_HDR_IS_RESPONSE(hdr)	FIELD_GET(MKHI_HDR_IS_RESPONSE, le32_to_cpu((hdr)->data))

-:749: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#749: FILE: drivers/gpu/drm/xe/xe_sysctrl_mailbox.h:40:
+#define XE_SYSCTRL_MKHI_HDR_RESULT(hdr)		FIELD_GET(MKHI_HDR_RESULT_MASK, le32_to_cpu((hdr)->data))

total: 0 errors, 10 warnings, 0 checks, 715 lines checked



^ permalink raw reply	[flat|nested] 8+ messages in thread

* ✓ CI.KUnit: success for drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms
  2025-12-30 15:17 [PATCH v1 0/1] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms Anoop, Vijay
  2025-12-30 15:17 ` [PATCH v1 1/1] " Anoop, Vijay
  2025-12-30 15:22 ` ✗ CI.checkpatch: warning for " Patchwork
@ 2025-12-30 15:24 ` Patchwork
  2025-12-30 15:57 ` ✓ Xe.CI.BAT: " Patchwork
  2025-12-30 16:57 ` ✓ Xe.CI.Full: " Patchwork
  4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2025-12-30 15:24 UTC (permalink / raw)
  To: Anoop, Vijay; +Cc: intel-xe

== Series Details ==

Series: drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms
URL   : https://patchwork.freedesktop.org/series/159554/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[15:22:57] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:23:01] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:23:32] Starting KUnit Kernel (1/1)...
[15:23:32] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:23:33] ================== guc_buf (11 subtests) ===================
[15:23:33] [PASSED] test_smallest
[15:23:33] [PASSED] test_largest
[15:23:33] [PASSED] test_granular
[15:23:33] [PASSED] test_unique
[15:23:33] [PASSED] test_overlap
[15:23:33] [PASSED] test_reusable
[15:23:33] [PASSED] test_too_big
[15:23:33] [PASSED] test_flush
[15:23:33] [PASSED] test_lookup
[15:23:33] [PASSED] test_data
[15:23:33] [PASSED] test_class
[15:23:33] ===================== [PASSED] guc_buf =====================
[15:23:33] =================== guc_dbm (7 subtests) ===================
[15:23:33] [PASSED] test_empty
[15:23:33] [PASSED] test_default
[15:23:33] ======================== test_size  ========================
[15:23:33] [PASSED] 4
[15:23:33] [PASSED] 8
[15:23:33] [PASSED] 32
[15:23:33] [PASSED] 256
[15:23:33] ==================== [PASSED] test_size ====================
[15:23:33] ======================= test_reuse  ========================
[15:23:33] [PASSED] 4
[15:23:33] [PASSED] 8
[15:23:33] [PASSED] 32
[15:23:33] [PASSED] 256
[15:23:33] =================== [PASSED] test_reuse ====================
[15:23:33] =================== test_range_overlap  ====================
[15:23:33] [PASSED] 4
[15:23:33] [PASSED] 8
[15:23:33] [PASSED] 32
[15:23:33] [PASSED] 256
[15:23:33] =============== [PASSED] test_range_overlap ================
[15:23:33] =================== test_range_compact  ====================
[15:23:33] [PASSED] 4
[15:23:33] [PASSED] 8
[15:23:33] [PASSED] 32
[15:23:33] [PASSED] 256
[15:23:33] =============== [PASSED] test_range_compact ================
[15:23:33] ==================== test_range_spare  =====================
[15:23:33] [PASSED] 4
[15:23:33] [PASSED] 8
[15:23:33] [PASSED] 32
[15:23:33] [PASSED] 256
[15:23:33] ================ [PASSED] test_range_spare =================
[15:23:33] ===================== [PASSED] guc_dbm =====================
[15:23:33] =================== guc_idm (6 subtests) ===================
[15:23:33] [PASSED] bad_init
[15:23:33] [PASSED] no_init
[15:23:33] [PASSED] init_fini
[15:23:33] [PASSED] check_used
[15:23:33] [PASSED] check_quota
[15:23:33] [PASSED] check_all
[15:23:33] ===================== [PASSED] guc_idm =====================
[15:23:33] ================== no_relay (3 subtests) ===================
[15:23:33] [PASSED] xe_drops_guc2pf_if_not_ready
[15:23:33] [PASSED] xe_drops_guc2vf_if_not_ready
[15:23:33] [PASSED] xe_rejects_send_if_not_ready
[15:23:33] ==================== [PASSED] no_relay =====================
[15:23:33] ================== pf_relay (14 subtests) ==================
[15:23:33] [PASSED] pf_rejects_guc2pf_too_short
[15:23:33] [PASSED] pf_rejects_guc2pf_too_long
[15:23:33] [PASSED] pf_rejects_guc2pf_no_payload
[15:23:33] [PASSED] pf_fails_no_payload
[15:23:33] [PASSED] pf_fails_bad_origin
[15:23:33] [PASSED] pf_fails_bad_type
[15:23:33] [PASSED] pf_txn_reports_error
[15:23:33] [PASSED] pf_txn_sends_pf2guc
[15:23:33] [PASSED] pf_sends_pf2guc
[15:23:33] [SKIPPED] pf_loopback_nop
[15:23:33] [SKIPPED] pf_loopback_echo
[15:23:33] [SKIPPED] pf_loopback_fail
[15:23:33] [SKIPPED] pf_loopback_busy
[15:23:33] [SKIPPED] pf_loopback_retry
[15:23:33] ==================== [PASSED] pf_relay =====================
[15:23:33] ================== vf_relay (3 subtests) ===================
[15:23:33] [PASSED] vf_rejects_guc2vf_too_short
[15:23:33] [PASSED] vf_rejects_guc2vf_too_long
[15:23:33] [PASSED] vf_rejects_guc2vf_no_payload
[15:23:33] ==================== [PASSED] vf_relay =====================
[15:23:33] ================ pf_gt_config (6 subtests) =================
[15:23:33] [PASSED] fair_contexts_1vf
[15:23:33] [PASSED] fair_doorbells_1vf
[15:23:33] [PASSED] fair_ggtt_1vf
[15:23:33] ====================== fair_contexts  ======================
[15:23:33] [PASSED] 1 VF
[15:23:33] [PASSED] 2 VFs
[15:23:33] [PASSED] 3 VFs
[15:23:33] [PASSED] 4 VFs
[15:23:33] [PASSED] 5 VFs
[15:23:33] [PASSED] 6 VFs
[15:23:33] [PASSED] 7 VFs
[15:23:33] [PASSED] 8 VFs
[15:23:33] [PASSED] 9 VFs
[15:23:33] [PASSED] 10 VFs
[15:23:33] [PASSED] 11 VFs
[15:23:33] [PASSED] 12 VFs
[15:23:33] [PASSED] 13 VFs
[15:23:33] [PASSED] 14 VFs
[15:23:33] [PASSED] 15 VFs
[15:23:33] [PASSED] 16 VFs
[15:23:33] [PASSED] 17 VFs
[15:23:33] [PASSED] 18 VFs
[15:23:33] [PASSED] 19 VFs
[15:23:33] [PASSED] 20 VFs
[15:23:33] [PASSED] 21 VFs
[15:23:33] [PASSED] 22 VFs
[15:23:33] [PASSED] 23 VFs
[15:23:33] [PASSED] 24 VFs
[15:23:33] [PASSED] 25 VFs
[15:23:33] [PASSED] 26 VFs
[15:23:33] [PASSED] 27 VFs
[15:23:33] [PASSED] 28 VFs
[15:23:33] [PASSED] 29 VFs
[15:23:33] [PASSED] 30 VFs
[15:23:33] [PASSED] 31 VFs
[15:23:33] [PASSED] 32 VFs
[15:23:33] [PASSED] 33 VFs
[15:23:33] [PASSED] 34 VFs
[15:23:33] [PASSED] 35 VFs
[15:23:33] [PASSED] 36 VFs
[15:23:33] [PASSED] 37 VFs
[15:23:33] [PASSED] 38 VFs
[15:23:33] [PASSED] 39 VFs
[15:23:33] [PASSED] 40 VFs
[15:23:33] [PASSED] 41 VFs
[15:23:33] [PASSED] 42 VFs
[15:23:33] [PASSED] 43 VFs
[15:23:33] [PASSED] 44 VFs
[15:23:33] [PASSED] 45 VFs
[15:23:33] [PASSED] 46 VFs
[15:23:33] [PASSED] 47 VFs
[15:23:33] [PASSED] 48 VFs
[15:23:33] [PASSED] 49 VFs
[15:23:33] [PASSED] 50 VFs
[15:23:33] [PASSED] 51 VFs
[15:23:33] [PASSED] 52 VFs
[15:23:33] [PASSED] 53 VFs
[15:23:33] [PASSED] 54 VFs
[15:23:33] [PASSED] 55 VFs
[15:23:33] [PASSED] 56 VFs
[15:23:33] [PASSED] 57 VFs
[15:23:33] [PASSED] 58 VFs
[15:23:33] [PASSED] 59 VFs
[15:23:33] [PASSED] 60 VFs
[15:23:33] [PASSED] 61 VFs
[15:23:33] [PASSED] 62 VFs
[15:23:33] [PASSED] 63 VFs
[15:23:33] ================== [PASSED] fair_contexts ==================
[15:23:33] ===================== fair_doorbells  ======================
[15:23:33] [PASSED] 1 VF
[15:23:33] [PASSED] 2 VFs
[15:23:33] [PASSED] 3 VFs
[15:23:33] [PASSED] 4 VFs
[15:23:33] [PASSED] 5 VFs
[15:23:33] [PASSED] 6 VFs
[15:23:33] [PASSED] 7 VFs
[15:23:33] [PASSED] 8 VFs
[15:23:33] [PASSED] 9 VFs
[15:23:33] [PASSED] 10 VFs
[15:23:33] [PASSED] 11 VFs
[15:23:33] [PASSED] 12 VFs
[15:23:33] [PASSED] 13 VFs
[15:23:33] [PASSED] 14 VFs
[15:23:33] [PASSED] 15 VFs
[15:23:33] [PASSED] 16 VFs
[15:23:33] [PASSED] 17 VFs
[15:23:33] [PASSED] 18 VFs
[15:23:33] [PASSED] 19 VFs
[15:23:33] [PASSED] 20 VFs
[15:23:33] [PASSED] 21 VFs
[15:23:33] [PASSED] 22 VFs
[15:23:33] [PASSED] 23 VFs
[15:23:33] [PASSED] 24 VFs
[15:23:33] [PASSED] 25 VFs
[15:23:33] [PASSED] 26 VFs
[15:23:33] [PASSED] 27 VFs
[15:23:33] [PASSED] 28 VFs
[15:23:33] [PASSED] 29 VFs
[15:23:33] [PASSED] 30 VFs
[15:23:33] [PASSED] 31 VFs
[15:23:33] [PASSED] 32 VFs
[15:23:33] [PASSED] 33 VFs
[15:23:33] [PASSED] 34 VFs
[15:23:33] [PASSED] 35 VFs
[15:23:33] [PASSED] 36 VFs
[15:23:33] [PASSED] 37 VFs
[15:23:33] [PASSED] 38 VFs
[15:23:33] [PASSED] 39 VFs
[15:23:33] [PASSED] 40 VFs
[15:23:33] [PASSED] 41 VFs
[15:23:33] [PASSED] 42 VFs
[15:23:33] [PASSED] 43 VFs
[15:23:33] [PASSED] 44 VFs
[15:23:33] [PASSED] 45 VFs
[15:23:33] [PASSED] 46 VFs
[15:23:33] [PASSED] 47 VFs
[15:23:33] [PASSED] 48 VFs
[15:23:33] [PASSED] 49 VFs
[15:23:33] [PASSED] 50 VFs
[15:23:33] [PASSED] 51 VFs
[15:23:33] [PASSED] 52 VFs
[15:23:33] [PASSED] 53 VFs
[15:23:33] [PASSED] 54 VFs
[15:23:33] [PASSED] 55 VFs
[15:23:33] [PASSED] 56 VFs
[15:23:33] [PASSED] 57 VFs
[15:23:33] [PASSED] 58 VFs
[15:23:33] [PASSED] 59 VFs
[15:23:33] [PASSED] 60 VFs
[15:23:33] [PASSED] 61 VFs
[15:23:33] [PASSED] 62 VFs
[15:23:33] [PASSED] 63 VFs
[15:23:33] ================= [PASSED] fair_doorbells ==================
[15:23:33] ======================== fair_ggtt  ========================
[15:23:33] [PASSED] 1 VF
[15:23:33] [PASSED] 2 VFs
[15:23:33] [PASSED] 3 VFs
[15:23:33] [PASSED] 4 VFs
[15:23:33] [PASSED] 5 VFs
[15:23:33] [PASSED] 6 VFs
[15:23:33] [PASSED] 7 VFs
[15:23:33] [PASSED] 8 VFs
[15:23:33] [PASSED] 9 VFs
[15:23:33] [PASSED] 10 VFs
[15:23:33] [PASSED] 11 VFs
[15:23:33] [PASSED] 12 VFs
[15:23:33] [PASSED] 13 VFs
[15:23:33] [PASSED] 14 VFs
[15:23:33] [PASSED] 15 VFs
[15:23:33] [PASSED] 16 VFs
[15:23:33] [PASSED] 17 VFs
[15:23:33] [PASSED] 18 VFs
[15:23:33] [PASSED] 19 VFs
[15:23:33] [PASSED] 20 VFs
[15:23:33] [PASSED] 21 VFs
[15:23:33] [PASSED] 22 VFs
[15:23:33] [PASSED] 23 VFs
[15:23:33] [PASSED] 24 VFs
[15:23:33] [PASSED] 25 VFs
[15:23:33] [PASSED] 26 VFs
[15:23:33] [PASSED] 27 VFs
[15:23:33] [PASSED] 28 VFs
[15:23:33] [PASSED] 29 VFs
[15:23:33] [PASSED] 30 VFs
[15:23:33] [PASSED] 31 VFs
[15:23:33] [PASSED] 32 VFs
[15:23:33] [PASSED] 33 VFs
[15:23:33] [PASSED] 34 VFs
[15:23:33] [PASSED] 35 VFs
[15:23:33] [PASSED] 36 VFs
[15:23:33] [PASSED] 37 VFs
[15:23:33] [PASSED] 38 VFs
[15:23:33] [PASSED] 39 VFs
[15:23:33] [PASSED] 40 VFs
[15:23:33] [PASSED] 41 VFs
[15:23:33] [PASSED] 42 VFs
[15:23:33] [PASSED] 43 VFs
[15:23:33] [PASSED] 44 VFs
[15:23:33] [PASSED] 45 VFs
[15:23:33] [PASSED] 46 VFs
[15:23:33] [PASSED] 47 VFs
[15:23:33] [PASSED] 48 VFs
[15:23:33] [PASSED] 49 VFs
[15:23:33] [PASSED] 50 VFs
[15:23:33] [PASSED] 51 VFs
[15:23:33] [PASSED] 52 VFs
[15:23:33] [PASSED] 53 VFs
[15:23:33] [PASSED] 54 VFs
[15:23:33] [PASSED] 55 VFs
[15:23:33] [PASSED] 56 VFs
[15:23:33] [PASSED] 57 VFs
[15:23:33] [PASSED] 58 VFs
[15:23:33] [PASSED] 59 VFs
[15:23:33] [PASSED] 60 VFs
[15:23:33] [PASSED] 61 VFs
[15:23:33] [PASSED] 62 VFs
[15:23:33] [PASSED] 63 VFs
[15:23:33] ==================== [PASSED] fair_ggtt ====================
[15:23:33] ================== [PASSED] pf_gt_config ===================
[15:23:33] ===================== lmtt (1 subtest) =====================
[15:23:33] ======================== test_ops  =========================
[15:23:33] [PASSED] 2-level
[15:23:33] [PASSED] multi-level
[15:23:33] ==================== [PASSED] test_ops =====================
[15:23:33] ====================== [PASSED] lmtt =======================
[15:23:33] ================= pf_service (11 subtests) =================
[15:23:33] [PASSED] pf_negotiate_any
[15:23:33] [PASSED] pf_negotiate_base_match
[15:23:33] [PASSED] pf_negotiate_base_newer
[15:23:33] [PASSED] pf_negotiate_base_next
[15:23:33] [SKIPPED] pf_negotiate_base_older
[15:23:33] [PASSED] pf_negotiate_base_prev
[15:23:33] [PASSED] pf_negotiate_latest_match
[15:23:33] [PASSED] pf_negotiate_latest_newer
[15:23:33] [PASSED] pf_negotiate_latest_next
[15:23:33] [SKIPPED] pf_negotiate_latest_older
[15:23:33] [SKIPPED] pf_negotiate_latest_prev
[15:23:33] =================== [PASSED] pf_service ====================
[15:23:33] ================= xe_guc_g2g (2 subtests) ==================
[15:23:33] ============== xe_live_guc_g2g_kunit_default  ==============
[15:23:33] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[15:23:33] ============== xe_live_guc_g2g_kunit_allmem  ===============
[15:23:33] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[15:23:33] =================== [SKIPPED] xe_guc_g2g ===================
[15:23:33] =================== xe_mocs (2 subtests) ===================
[15:23:33] ================ xe_live_mocs_kernel_kunit  ================
[15:23:33] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[15:23:33] ================ xe_live_mocs_reset_kunit  =================
[15:23:33] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[15:23:33] ==================== [SKIPPED] xe_mocs =====================
[15:23:33] ================= xe_migrate (2 subtests) ==================
[15:23:33] ================= xe_migrate_sanity_kunit  =================
[15:23:33] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[15:23:33] ================== xe_validate_ccs_kunit  ==================
[15:23:33] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[15:23:33] =================== [SKIPPED] xe_migrate ===================
[15:23:33] ================== xe_dma_buf (1 subtest) ==================
[15:23:33] ==================== xe_dma_buf_kunit  =====================
[15:23:33] ================ [SKIPPED] xe_dma_buf_kunit ================
[15:23:33] =================== [SKIPPED] xe_dma_buf ===================
[15:23:33] ================= xe_bo_shrink (1 subtest) =================
[15:23:33] =================== xe_bo_shrink_kunit  ====================
[15:23:33] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[15:23:33] ================== [SKIPPED] xe_bo_shrink ==================
[15:23:33] ==================== xe_bo (2 subtests) ====================
[15:23:33] ================== xe_ccs_migrate_kunit  ===================
[15:23:33] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[15:23:33] ==================== xe_bo_evict_kunit  ====================
[15:23:33] =============== [SKIPPED] xe_bo_evict_kunit ================
[15:23:33] ===================== [SKIPPED] xe_bo ======================
[15:23:33] ==================== args (13 subtests) ====================
[15:23:33] [PASSED] count_args_test
[15:23:33] [PASSED] call_args_example
[15:23:33] [PASSED] call_args_test
[15:23:33] [PASSED] drop_first_arg_example
[15:23:33] [PASSED] drop_first_arg_test
[15:23:33] [PASSED] first_arg_example
[15:23:33] [PASSED] first_arg_test
[15:23:33] [PASSED] last_arg_example
[15:23:33] [PASSED] last_arg_test
[15:23:33] [PASSED] pick_arg_example
[15:23:33] [PASSED] if_args_example
[15:23:33] [PASSED] if_args_test
[15:23:33] [PASSED] sep_comma_example
[15:23:33] ====================== [PASSED] args =======================
[15:23:33] =================== xe_pci (3 subtests) ====================
[15:23:33] ==================== check_graphics_ip  ====================
[15:23:33] [PASSED] 12.00 Xe_LP
[15:23:33] [PASSED] 12.10 Xe_LP+
[15:23:33] [PASSED] 12.55 Xe_HPG
[15:23:33] [PASSED] 12.60 Xe_HPC
[15:23:33] [PASSED] 12.70 Xe_LPG
[15:23:33] [PASSED] 12.71 Xe_LPG
[15:23:33] [PASSED] 12.74 Xe_LPG+
[15:23:33] [PASSED] 20.01 Xe2_HPG
[15:23:33] [PASSED] 20.02 Xe2_HPG
[15:23:33] [PASSED] 20.04 Xe2_LPG
[15:23:33] [PASSED] 30.00 Xe3_LPG
[15:23:33] [PASSED] 30.01 Xe3_LPG
[15:23:33] [PASSED] 30.03 Xe3_LPG
[15:23:33] [PASSED] 30.04 Xe3_LPG
[15:23:33] [PASSED] 30.05 Xe3_LPG
[15:23:33] [PASSED] 35.11 Xe3p_XPC
[15:23:33] ================ [PASSED] check_graphics_ip ================
[15:23:33] ===================== check_media_ip  ======================
[15:23:33] [PASSED] 12.00 Xe_M
[15:23:33] [PASSED] 12.55 Xe_HPM
[15:23:33] [PASSED] 13.00 Xe_LPM+
[15:23:33] [PASSED] 13.01 Xe2_HPM
[15:23:33] [PASSED] 20.00 Xe2_LPM
[15:23:33] [PASSED] 30.00 Xe3_LPM
[15:23:33] [PASSED] 30.02 Xe3_LPM
[15:23:33] [PASSED] 35.00 Xe3p_LPM
[15:23:33] [PASSED] 35.03 Xe3p_HPM
[15:23:33] ================= [PASSED] check_media_ip ==================
[15:23:33] =================== check_platform_desc  ===================
[15:23:33] [PASSED] 0x9A60 (TIGERLAKE)
[15:23:33] [PASSED] 0x9A68 (TIGERLAKE)
[15:23:33] [PASSED] 0x9A70 (TIGERLAKE)
[15:23:33] [PASSED] 0x9A40 (TIGERLAKE)
[15:23:33] [PASSED] 0x9A49 (TIGERLAKE)
[15:23:33] [PASSED] 0x9A59 (TIGERLAKE)
[15:23:33] [PASSED] 0x9A78 (TIGERLAKE)
[15:23:33] [PASSED] 0x9AC0 (TIGERLAKE)
[15:23:33] [PASSED] 0x9AC9 (TIGERLAKE)
[15:23:33] [PASSED] 0x9AD9 (TIGERLAKE)
[15:23:33] [PASSED] 0x9AF8 (TIGERLAKE)
[15:23:33] [PASSED] 0x4C80 (ROCKETLAKE)
[15:23:33] [PASSED] 0x4C8A (ROCKETLAKE)
[15:23:33] [PASSED] 0x4C8B (ROCKETLAKE)
[15:23:33] [PASSED] 0x4C8C (ROCKETLAKE)
[15:23:33] [PASSED] 0x4C90 (ROCKETLAKE)
[15:23:33] [PASSED] 0x4C9A (ROCKETLAKE)
[15:23:33] [PASSED] 0x4680 (ALDERLAKE_S)
[15:23:33] [PASSED] 0x4682 (ALDERLAKE_S)
[15:23:33] [PASSED] 0x4688 (ALDERLAKE_S)
[15:23:33] [PASSED] 0x468A (ALDERLAKE_S)
[15:23:33] [PASSED] 0x468B (ALDERLAKE_S)
[15:23:33] [PASSED] 0x4690 (ALDERLAKE_S)
[15:23:33] [PASSED] 0x4692 (ALDERLAKE_S)
[15:23:33] [PASSED] 0x4693 (ALDERLAKE_S)
[15:23:33] [PASSED] 0x46A0 (ALDERLAKE_P)
[15:23:33] [PASSED] 0x46A1 (ALDERLAKE_P)
[15:23:33] [PASSED] 0x46A2 (ALDERLAKE_P)
[15:23:33] [PASSED] 0x46A3 (ALDERLAKE_P)
[15:23:33] [PASSED] 0x46A6 (ALDERLAKE_P)
[15:23:33] [PASSED] 0x46A8 (ALDERLAKE_P)
[15:23:33] [PASSED] 0x46AA (ALDERLAKE_P)
[15:23:33] [PASSED] 0x462A (ALDERLAKE_P)
[15:23:33] [PASSED] 0x4626 (ALDERLAKE_P)
[15:23:33] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[15:23:33] [PASSED] 0x46B0 (ALDERLAKE_P)
[15:23:33] [PASSED] 0x46B1 (ALDERLAKE_P)
[15:23:33] [PASSED] 0x46B2 (ALDERLAKE_P)
[15:23:33] [PASSED] 0x46B3 (ALDERLAKE_P)
[15:23:33] [PASSED] 0x46C0 (ALDERLAKE_P)
[15:23:33] [PASSED] 0x46C1 (ALDERLAKE_P)
[15:23:33] [PASSED] 0x46C2 (ALDERLAKE_P)
[15:23:33] [PASSED] 0x46C3 (ALDERLAKE_P)
[15:23:33] [PASSED] 0x46D0 (ALDERLAKE_N)
[15:23:33] [PASSED] 0x46D1 (ALDERLAKE_N)
[15:23:33] [PASSED] 0x46D2 (ALDERLAKE_N)
[15:23:33] [PASSED] 0x46D3 (ALDERLAKE_N)
[15:23:33] [PASSED] 0x46D4 (ALDERLAKE_N)
[15:23:33] [PASSED] 0xA721 (ALDERLAKE_P)
[15:23:33] [PASSED] 0xA7A1 (ALDERLAKE_P)
[15:23:33] [PASSED] 0xA7A9 (ALDERLAKE_P)
[15:23:33] [PASSED] 0xA7AC (ALDERLAKE_P)
[15:23:33] [PASSED] 0xA7AD (ALDERLAKE_P)
[15:23:33] [PASSED] 0xA720 (ALDERLAKE_P)
[15:23:33] [PASSED] 0xA7A0 (ALDERLAKE_P)
[15:23:33] [PASSED] 0xA7A8 (ALDERLAKE_P)
[15:23:33] [PASSED] 0xA7AA (ALDERLAKE_P)
[15:23:33] [PASSED] 0xA7AB (ALDERLAKE_P)
[15:23:33] [PASSED] 0xA780 (ALDERLAKE_S)
[15:23:33] [PASSED] 0xA781 (ALDERLAKE_S)
[15:23:33] [PASSED] 0xA782 (ALDERLAKE_S)
[15:23:33] [PASSED] 0xA783 (ALDERLAKE_S)
[15:23:33] [PASSED] 0xA788 (ALDERLAKE_S)
[15:23:33] [PASSED] 0xA789 (ALDERLAKE_S)
[15:23:33] [PASSED] 0xA78A (ALDERLAKE_S)
[15:23:33] [PASSED] 0xA78B (ALDERLAKE_S)
[15:23:33] [PASSED] 0x4905 (DG1)
[15:23:33] [PASSED] 0x4906 (DG1)
[15:23:33] [PASSED] 0x4907 (DG1)
[15:23:33] [PASSED] 0x4908 (DG1)
[15:23:33] [PASSED] 0x4909 (DG1)
[15:23:33] [PASSED] 0x56C0 (DG2)
[15:23:33] [PASSED] 0x56C2 (DG2)
[15:23:33] [PASSED] 0x56C1 (DG2)
[15:23:33] [PASSED] 0x7D51 (METEORLAKE)
[15:23:33] [PASSED] 0x7DD1 (METEORLAKE)
[15:23:33] [PASSED] 0x7D41 (METEORLAKE)
[15:23:33] [PASSED] 0x7D67 (METEORLAKE)
[15:23:33] [PASSED] 0xB640 (METEORLAKE)
[15:23:33] [PASSED] 0x56A0 (DG2)
[15:23:33] [PASSED] 0x56A1 (DG2)
[15:23:33] [PASSED] 0x56A2 (DG2)
[15:23:33] [PASSED] 0x56BE (DG2)
[15:23:33] [PASSED] 0x56BF (DG2)
[15:23:33] [PASSED] 0x5690 (DG2)
[15:23:33] [PASSED] 0x5691 (DG2)
[15:23:33] [PASSED] 0x5692 (DG2)
[15:23:33] [PASSED] 0x56A5 (DG2)
[15:23:33] [PASSED] 0x56A6 (DG2)
[15:23:33] [PASSED] 0x56B0 (DG2)
[15:23:33] [PASSED] 0x56B1 (DG2)
[15:23:33] [PASSED] 0x56BA (DG2)
[15:23:33] [PASSED] 0x56BB (DG2)
[15:23:33] [PASSED] 0x56BC (DG2)
[15:23:33] [PASSED] 0x56BD (DG2)
[15:23:33] [PASSED] 0x5693 (DG2)
[15:23:33] [PASSED] 0x5694 (DG2)
[15:23:33] [PASSED] 0x5695 (DG2)
[15:23:33] [PASSED] 0x56A3 (DG2)
[15:23:33] [PASSED] 0x56A4 (DG2)
[15:23:33] [PASSED] 0x56B2 (DG2)
[15:23:33] [PASSED] 0x56B3 (DG2)
[15:23:33] [PASSED] 0x5696 (DG2)
[15:23:33] [PASSED] 0x5697 (DG2)
[15:23:33] [PASSED] 0xB69 (PVC)
[15:23:33] [PASSED] 0xB6E (PVC)
[15:23:33] [PASSED] 0xBD4 (PVC)
[15:23:33] [PASSED] 0xBD5 (PVC)
[15:23:33] [PASSED] 0xBD6 (PVC)
[15:23:33] [PASSED] 0xBD7 (PVC)
[15:23:33] [PASSED] 0xBD8 (PVC)
[15:23:33] [PASSED] 0xBD9 (PVC)
[15:23:33] [PASSED] 0xBDA (PVC)
[15:23:33] [PASSED] 0xBDB (PVC)
[15:23:33] [PASSED] 0xBE0 (PVC)
[15:23:33] [PASSED] 0xBE1 (PVC)
[15:23:33] [PASSED] 0xBE5 (PVC)
[15:23:33] [PASSED] 0x7D40 (METEORLAKE)
[15:23:33] [PASSED] 0x7D45 (METEORLAKE)
[15:23:33] [PASSED] 0x7D55 (METEORLAKE)
[15:23:33] [PASSED] 0x7D60 (METEORLAKE)
[15:23:33] [PASSED] 0x7DD5 (METEORLAKE)
[15:23:33] [PASSED] 0x6420 (LUNARLAKE)
[15:23:33] [PASSED] 0x64A0 (LUNARLAKE)
[15:23:33] [PASSED] 0x64B0 (LUNARLAKE)
[15:23:33] [PASSED] 0xE202 (BATTLEMAGE)
[15:23:33] [PASSED] 0xE209 (BATTLEMAGE)
[15:23:33] [PASSED] 0xE20B (BATTLEMAGE)
[15:23:33] [PASSED] 0xE20C (BATTLEMAGE)
[15:23:33] [PASSED] 0xE20D (BATTLEMAGE)
[15:23:33] [PASSED] 0xE210 (BATTLEMAGE)
[15:23:33] [PASSED] 0xE211 (BATTLEMAGE)
[15:23:33] [PASSED] 0xE212 (BATTLEMAGE)
[15:23:33] [PASSED] 0xE216 (BATTLEMAGE)
[15:23:33] [PASSED] 0xE220 (BATTLEMAGE)
[15:23:33] [PASSED] 0xE221 (BATTLEMAGE)
[15:23:33] [PASSED] 0xE222 (BATTLEMAGE)
[15:23:33] [PASSED] 0xE223 (BATTLEMAGE)
[15:23:33] [PASSED] 0xB080 (PANTHERLAKE)
[15:23:33] [PASSED] 0xB081 (PANTHERLAKE)
[15:23:33] [PASSED] 0xB082 (PANTHERLAKE)
[15:23:33] [PASSED] 0xB083 (PANTHERLAKE)
[15:23:33] [PASSED] 0xB084 (PANTHERLAKE)
[15:23:33] [PASSED] 0xB085 (PANTHERLAKE)
[15:23:33] [PASSED] 0xB086 (PANTHERLAKE)
[15:23:33] [PASSED] 0xB087 (PANTHERLAKE)
[15:23:33] [PASSED] 0xB08F (PANTHERLAKE)
[15:23:33] [PASSED] 0xB090 (PANTHERLAKE)
[15:23:33] [PASSED] 0xB0A0 (PANTHERLAKE)
[15:23:33] [PASSED] 0xB0B0 (PANTHERLAKE)
[15:23:33] [PASSED] 0xFD80 (PANTHERLAKE)
[15:23:33] [PASSED] 0xFD81 (PANTHERLAKE)
[15:23:33] [PASSED] 0xD740 (NOVALAKE_S)
[15:23:33] [PASSED] 0xD741 (NOVALAKE_S)
[15:23:33] [PASSED] 0xD742 (NOVALAKE_S)
[15:23:33] [PASSED] 0xD743 (NOVALAKE_S)
[15:23:33] [PASSED] 0xD744 (NOVALAKE_S)
[15:23:33] [PASSED] 0xD745 (NOVALAKE_S)
[15:23:33] [PASSED] 0x674C (CRESCENTISLAND)
[15:23:33] =============== [PASSED] check_platform_desc ===============
[15:23:33] ===================== [PASSED] xe_pci ======================
[15:23:33] =================== xe_rtp (2 subtests) ====================
[15:23:33] =============== xe_rtp_process_to_sr_tests  ================
[15:23:33] [PASSED] coalesce-same-reg
[15:23:33] [PASSED] no-match-no-add
[15:23:33] [PASSED] match-or
[15:23:33] [PASSED] match-or-xfail
[15:23:33] [PASSED] no-match-no-add-multiple-rules
[15:23:33] [PASSED] two-regs-two-entries
[15:23:33] [PASSED] clr-one-set-other
[15:23:33] [PASSED] set-field
[15:23:33] [PASSED] conflict-duplicate
[15:23:33] [PASSED] conflict-not-disjoint
[15:23:33] [PASSED] conflict-reg-type
[15:23:33] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[15:23:33] ================== xe_rtp_process_tests  ===================
[15:23:33] [PASSED] active1
[15:23:33] [PASSED] active2
[15:23:33] [PASSED] active-inactive
[15:23:33] [PASSED] inactive-active
[15:23:33] [PASSED] inactive-1st_or_active-inactive
[15:23:33] [PASSED] inactive-2nd_or_active-inactive
[15:23:33] [PASSED] inactive-last_or_active-inactive
[15:23:33] [PASSED] inactive-no_or_active-inactive
[15:23:33] ============== [PASSED] xe_rtp_process_tests ===============
[15:23:33] ===================== [PASSED] xe_rtp ======================
[15:23:33] ==================== xe_wa (1 subtest) =====================
[15:23:33] ======================== xe_wa_gt  =========================
[15:23:33] [PASSED] TIGERLAKE B0
[15:23:33] [PASSED] DG1 A0
[15:23:33] [PASSED] DG1 B0
[15:23:33] [PASSED] ALDERLAKE_S A0
[15:23:33] [PASSED] ALDERLAKE_S B0
[15:23:33] [PASSED] ALDERLAKE_S C0
[15:23:33] [PASSED] ALDERLAKE_S D0
[15:23:33] [PASSED] ALDERLAKE_P A0
[15:23:33] [PASSED] ALDERLAKE_P B0
[15:23:33] [PASSED] ALDERLAKE_P C0
[15:23:33] [PASSED] ALDERLAKE_S RPLS D0
[15:23:33] [PASSED] ALDERLAKE_P RPLU E0
[15:23:33] [PASSED] DG2 G10 C0
[15:23:33] [PASSED] DG2 G11 B1
[15:23:33] [PASSED] DG2 G12 A1
[15:23:33] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:23:33] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:23:33] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[15:23:33] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[15:23:33] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[15:23:33] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[15:23:33] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[15:23:33] ==================== [PASSED] xe_wa_gt =====================
[15:23:33] ====================== [PASSED] xe_wa ======================
[15:23:33] ============================================================
[15:23:33] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[15:23:33] Elapsed time: 36.092s total, 4.130s configuring, 31.445s building, 0.471s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[15:23:33] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:23:35] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:24:00] Starting KUnit Kernel (1/1)...
[15:24:00] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:24:00] ============ drm_test_pick_cmdline (2 subtests) ============
[15:24:00] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[15:24:00] =============== drm_test_pick_cmdline_named  ===============
[15:24:00] [PASSED] NTSC
[15:24:00] [PASSED] NTSC-J
[15:24:00] [PASSED] PAL
[15:24:00] [PASSED] PAL-M
[15:24:00] =========== [PASSED] drm_test_pick_cmdline_named ===========
[15:24:00] ============== [PASSED] drm_test_pick_cmdline ==============
[15:24:00] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[15:24:00] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[15:24:00] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[15:24:00] =========== drm_validate_clone_mode (2 subtests) ===========
[15:24:00] ============== drm_test_check_in_clone_mode  ===============
[15:24:00] [PASSED] in_clone_mode
[15:24:00] [PASSED] not_in_clone_mode
[15:24:00] ========== [PASSED] drm_test_check_in_clone_mode ===========
[15:24:00] =============== drm_test_check_valid_clones  ===============
[15:24:00] [PASSED] not_in_clone_mode
[15:24:00] [PASSED] valid_clone
[15:24:00] [PASSED] invalid_clone
[15:24:00] =========== [PASSED] drm_test_check_valid_clones ===========
[15:24:00] ============= [PASSED] drm_validate_clone_mode =============
[15:24:00] ============= drm_validate_modeset (1 subtest) =============
[15:24:00] [PASSED] drm_test_check_connector_changed_modeset
[15:24:00] ============== [PASSED] drm_validate_modeset ===============
[15:24:00] ====== drm_test_bridge_get_current_state (2 subtests) ======
[15:24:00] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[15:24:00] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[15:24:00] ======== [PASSED] drm_test_bridge_get_current_state ========
[15:24:00] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[15:24:00] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[15:24:00] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[15:24:00] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[15:24:00] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[15:24:00] ============== drm_bridge_alloc (2 subtests) ===============
[15:24:00] [PASSED] drm_test_drm_bridge_alloc_basic
[15:24:00] [PASSED] drm_test_drm_bridge_alloc_get_put
[15:24:00] ================ [PASSED] drm_bridge_alloc =================
[15:24:00] ================== drm_buddy (8 subtests) ==================
[15:24:00] [PASSED] drm_test_buddy_alloc_limit
[15:24:00] [PASSED] drm_test_buddy_alloc_optimistic
[15:24:00] [PASSED] drm_test_buddy_alloc_pessimistic
[15:24:00] [PASSED] drm_test_buddy_alloc_pathological
[15:24:00] [PASSED] drm_test_buddy_alloc_contiguous
[15:24:00] [PASSED] drm_test_buddy_alloc_clear
[15:24:01] [PASSED] drm_test_buddy_alloc_range_bias
[15:24:01] [PASSED] drm_test_buddy_fragmentation_performance
[15:24:01] ==================== [PASSED] drm_buddy ====================
[15:24:01] ============= drm_cmdline_parser (40 subtests) =============
[15:24:01] [PASSED] drm_test_cmdline_force_d_only
[15:24:01] [PASSED] drm_test_cmdline_force_D_only_dvi
[15:24:01] [PASSED] drm_test_cmdline_force_D_only_hdmi
[15:24:01] [PASSED] drm_test_cmdline_force_D_only_not_digital
[15:24:01] [PASSED] drm_test_cmdline_force_e_only
[15:24:01] [PASSED] drm_test_cmdline_res
[15:24:01] [PASSED] drm_test_cmdline_res_vesa
[15:24:01] [PASSED] drm_test_cmdline_res_vesa_rblank
[15:24:01] [PASSED] drm_test_cmdline_res_rblank
[15:24:01] [PASSED] drm_test_cmdline_res_bpp
[15:24:01] [PASSED] drm_test_cmdline_res_refresh
[15:24:01] [PASSED] drm_test_cmdline_res_bpp_refresh
[15:24:01] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[15:24:01] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[15:24:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[15:24:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[15:24:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[15:24:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[15:24:01] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[15:24:01] [PASSED] drm_test_cmdline_res_margins_force_on
[15:24:01] [PASSED] drm_test_cmdline_res_vesa_margins
[15:24:01] [PASSED] drm_test_cmdline_name
[15:24:01] [PASSED] drm_test_cmdline_name_bpp
[15:24:01] [PASSED] drm_test_cmdline_name_option
[15:24:01] [PASSED] drm_test_cmdline_name_bpp_option
[15:24:01] [PASSED] drm_test_cmdline_rotate_0
[15:24:01] [PASSED] drm_test_cmdline_rotate_90
[15:24:01] [PASSED] drm_test_cmdline_rotate_180
[15:24:01] [PASSED] drm_test_cmdline_rotate_270
[15:24:01] [PASSED] drm_test_cmdline_hmirror
[15:24:01] [PASSED] drm_test_cmdline_vmirror
[15:24:01] [PASSED] drm_test_cmdline_margin_options
[15:24:01] [PASSED] drm_test_cmdline_multiple_options
[15:24:01] [PASSED] drm_test_cmdline_bpp_extra_and_option
[15:24:01] [PASSED] drm_test_cmdline_extra_and_option
[15:24:01] [PASSED] drm_test_cmdline_freestanding_options
[15:24:01] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[15:24:01] [PASSED] drm_test_cmdline_panel_orientation
[15:24:01] ================ drm_test_cmdline_invalid  =================
[15:24:01] [PASSED] margin_only
[15:24:01] [PASSED] interlace_only
[15:24:01] [PASSED] res_missing_x
[15:24:01] [PASSED] res_missing_y
[15:24:01] [PASSED] res_bad_y
[15:24:01] [PASSED] res_missing_y_bpp
[15:24:01] [PASSED] res_bad_bpp
[15:24:01] [PASSED] res_bad_refresh
[15:24:01] [PASSED] res_bpp_refresh_force_on_off
[15:24:01] [PASSED] res_invalid_mode
[15:24:01] [PASSED] res_bpp_wrong_place_mode
[15:24:01] [PASSED] name_bpp_refresh
[15:24:01] [PASSED] name_refresh
[15:24:01] [PASSED] name_refresh_wrong_mode
[15:24:01] [PASSED] name_refresh_invalid_mode
[15:24:01] [PASSED] rotate_multiple
[15:24:01] [PASSED] rotate_invalid_val
[15:24:01] [PASSED] rotate_truncated
[15:24:01] [PASSED] invalid_option
[15:24:01] [PASSED] invalid_tv_option
[15:24:01] [PASSED] truncated_tv_option
[15:24:01] ============ [PASSED] drm_test_cmdline_invalid =============
[15:24:01] =============== drm_test_cmdline_tv_options  ===============
[15:24:01] [PASSED] NTSC
[15:24:01] [PASSED] NTSC_443
[15:24:01] [PASSED] NTSC_J
[15:24:01] [PASSED] PAL
[15:24:01] [PASSED] PAL_M
[15:24:01] [PASSED] PAL_N
[15:24:01] [PASSED] SECAM
[15:24:01] [PASSED] MONO_525
[15:24:01] [PASSED] MONO_625
[15:24:01] =========== [PASSED] drm_test_cmdline_tv_options ===========
[15:24:01] =============== [PASSED] drm_cmdline_parser ================
[15:24:01] ========== drmm_connector_hdmi_init (20 subtests) ==========
[15:24:01] [PASSED] drm_test_connector_hdmi_init_valid
[15:24:01] [PASSED] drm_test_connector_hdmi_init_bpc_8
[15:24:01] [PASSED] drm_test_connector_hdmi_init_bpc_10
[15:24:01] [PASSED] drm_test_connector_hdmi_init_bpc_12
[15:24:01] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[15:24:01] [PASSED] drm_test_connector_hdmi_init_bpc_null
[15:24:01] [PASSED] drm_test_connector_hdmi_init_formats_empty
[15:24:01] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[15:24:01] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[15:24:01] [PASSED] supported_formats=0x9 yuv420_allowed=1
[15:24:01] [PASSED] supported_formats=0x9 yuv420_allowed=0
[15:24:01] [PASSED] supported_formats=0x3 yuv420_allowed=1
[15:24:01] [PASSED] supported_formats=0x3 yuv420_allowed=0
[15:24:01] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:24:01] [PASSED] drm_test_connector_hdmi_init_null_ddc
[15:24:01] [PASSED] drm_test_connector_hdmi_init_null_product
[15:24:01] [PASSED] drm_test_connector_hdmi_init_null_vendor
[15:24:01] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[15:24:01] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[15:24:01] [PASSED] drm_test_connector_hdmi_init_product_valid
[15:24:01] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[15:24:01] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[15:24:01] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[15:24:01] ========= drm_test_connector_hdmi_init_type_valid  =========
[15:24:01] [PASSED] HDMI-A
[15:24:01] [PASSED] HDMI-B
[15:24:01] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[15:24:01] ======== drm_test_connector_hdmi_init_type_invalid  ========
[15:24:01] [PASSED] Unknown
[15:24:01] [PASSED] VGA
[15:24:01] [PASSED] DVI-I
[15:24:01] [PASSED] DVI-D
[15:24:01] [PASSED] DVI-A
[15:24:01] [PASSED] Composite
[15:24:01] [PASSED] SVIDEO
[15:24:01] [PASSED] LVDS
[15:24:01] [PASSED] Component
[15:24:01] [PASSED] DIN
[15:24:01] [PASSED] DP
[15:24:01] [PASSED] TV
[15:24:01] [PASSED] eDP
[15:24:01] [PASSED] Virtual
[15:24:01] [PASSED] DSI
[15:24:01] [PASSED] DPI
[15:24:01] [PASSED] Writeback
[15:24:01] [PASSED] SPI
[15:24:01] [PASSED] USB
[15:24:01] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[15:24:01] ============ [PASSED] drmm_connector_hdmi_init =============
[15:24:01] ============= drmm_connector_init (3 subtests) =============
[15:24:01] [PASSED] drm_test_drmm_connector_init
[15:24:01] [PASSED] drm_test_drmm_connector_init_null_ddc
[15:24:01] ========= drm_test_drmm_connector_init_type_valid  =========
[15:24:01] [PASSED] Unknown
[15:24:01] [PASSED] VGA
[15:24:01] [PASSED] DVI-I
[15:24:01] [PASSED] DVI-D
[15:24:01] [PASSED] DVI-A
[15:24:01] [PASSED] Composite
[15:24:01] [PASSED] SVIDEO
[15:24:01] [PASSED] LVDS
[15:24:01] [PASSED] Component
[15:24:01] [PASSED] DIN
[15:24:01] [PASSED] DP
[15:24:01] [PASSED] HDMI-A
[15:24:01] [PASSED] HDMI-B
[15:24:01] [PASSED] TV
[15:24:01] [PASSED] eDP
[15:24:01] [PASSED] Virtual
[15:24:01] [PASSED] DSI
[15:24:01] [PASSED] DPI
[15:24:01] [PASSED] Writeback
[15:24:01] [PASSED] SPI
[15:24:01] [PASSED] USB
[15:24:01] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[15:24:01] =============== [PASSED] drmm_connector_init ===============
[15:24:01] ========= drm_connector_dynamic_init (6 subtests) ==========
[15:24:01] [PASSED] drm_test_drm_connector_dynamic_init
[15:24:01] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[15:24:01] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[15:24:01] [PASSED] drm_test_drm_connector_dynamic_init_properties
[15:24:01] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[15:24:01] [PASSED] Unknown
[15:24:01] [PASSED] VGA
[15:24:01] [PASSED] DVI-I
[15:24:01] [PASSED] DVI-D
[15:24:01] [PASSED] DVI-A
[15:24:01] [PASSED] Composite
[15:24:01] [PASSED] SVIDEO
[15:24:01] [PASSED] LVDS
[15:24:01] [PASSED] Component
[15:24:01] [PASSED] DIN
[15:24:01] [PASSED] DP
[15:24:01] [PASSED] HDMI-A
[15:24:01] [PASSED] HDMI-B
[15:24:01] [PASSED] TV
[15:24:01] [PASSED] eDP
[15:24:01] [PASSED] Virtual
[15:24:01] [PASSED] DSI
[15:24:01] [PASSED] DPI
[15:24:01] [PASSED] Writeback
[15:24:01] [PASSED] SPI
[15:24:01] [PASSED] USB
[15:24:01] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[15:24:01] ======== drm_test_drm_connector_dynamic_init_name  =========
[15:24:01] [PASSED] Unknown
[15:24:01] [PASSED] VGA
[15:24:01] [PASSED] DVI-I
[15:24:01] [PASSED] DVI-D
[15:24:01] [PASSED] DVI-A
[15:24:01] [PASSED] Composite
[15:24:01] [PASSED] SVIDEO
[15:24:01] [PASSED] LVDS
[15:24:01] [PASSED] Component
[15:24:01] [PASSED] DIN
[15:24:01] [PASSED] DP
[15:24:01] [PASSED] HDMI-A
[15:24:01] [PASSED] HDMI-B
[15:24:01] [PASSED] TV
[15:24:01] [PASSED] eDP
[15:24:01] [PASSED] Virtual
[15:24:01] [PASSED] DSI
[15:24:01] [PASSED] DPI
[15:24:01] [PASSED] Writeback
[15:24:01] [PASSED] SPI
[15:24:01] [PASSED] USB
[15:24:01] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[15:24:01] =========== [PASSED] drm_connector_dynamic_init ============
[15:24:01] ==== drm_connector_dynamic_register_early (4 subtests) =====
[15:24:01] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[15:24:01] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[15:24:01] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[15:24:01] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[15:24:01] ====== [PASSED] drm_connector_dynamic_register_early =======
[15:24:01] ======= drm_connector_dynamic_register (7 subtests) ========
[15:24:01] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[15:24:01] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[15:24:01] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[15:24:01] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[15:24:01] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[15:24:01] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[15:24:01] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[15:24:01] ========= [PASSED] drm_connector_dynamic_register ==========
[15:24:01] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[15:24:01] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[15:24:01] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[15:24:01] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[15:24:01] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[15:24:01] ========== drm_test_get_tv_mode_from_name_valid  ===========
[15:24:01] [PASSED] NTSC
[15:24:01] [PASSED] NTSC-443
[15:24:01] [PASSED] NTSC-J
[15:24:01] [PASSED] PAL
[15:24:01] [PASSED] PAL-M
[15:24:01] [PASSED] PAL-N
[15:24:01] [PASSED] SECAM
[15:24:01] [PASSED] Mono
[15:24:01] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[15:24:01] [PASSED] drm_test_get_tv_mode_from_name_truncated
[15:24:01] ============ [PASSED] drm_get_tv_mode_from_name ============
[15:24:01] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[15:24:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[15:24:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[15:24:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[15:24:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[15:24:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[15:24:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[15:24:01] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[15:24:01] [PASSED] VIC 96
[15:24:01] [PASSED] VIC 97
[15:24:01] [PASSED] VIC 101
[15:24:01] [PASSED] VIC 102
[15:24:01] [PASSED] VIC 106
[15:24:01] [PASSED] VIC 107
[15:24:01] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[15:24:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[15:24:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[15:24:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[15:24:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[15:24:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[15:24:01] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[15:24:01] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[15:24:01] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[15:24:01] [PASSED] Automatic
[15:24:01] [PASSED] Full
[15:24:01] [PASSED] Limited 16:235
[15:24:01] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[15:24:01] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[15:24:01] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[15:24:01] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[15:24:01] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[15:24:01] [PASSED] RGB
[15:24:01] [PASSED] YUV 4:2:0
[15:24:01] [PASSED] YUV 4:2:2
[15:24:01] [PASSED] YUV 4:4:4
[15:24:01] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[15:24:01] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[15:24:01] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[15:24:01] ============= drm_damage_helper (21 subtests) ==============
[15:24:01] [PASSED] drm_test_damage_iter_no_damage
[15:24:01] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[15:24:01] [PASSED] drm_test_damage_iter_no_damage_src_moved
[15:24:01] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[15:24:01] [PASSED] drm_test_damage_iter_no_damage_not_visible
[15:24:01] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[15:24:01] [PASSED] drm_test_damage_iter_no_damage_no_fb
[15:24:01] [PASSED] drm_test_damage_iter_simple_damage
[15:24:01] [PASSED] drm_test_damage_iter_single_damage
[15:24:01] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[15:24:01] [PASSED] drm_test_damage_iter_single_damage_outside_src
[15:24:01] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[15:24:01] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[15:24:01] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[15:24:01] [PASSED] drm_test_damage_iter_single_damage_src_moved
[15:24:01] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[15:24:01] [PASSED] drm_test_damage_iter_damage
[15:24:01] [PASSED] drm_test_damage_iter_damage_one_intersect
[15:24:01] [PASSED] drm_test_damage_iter_damage_one_outside
[15:24:01] [PASSED] drm_test_damage_iter_damage_src_moved
[15:24:01] [PASSED] drm_test_damage_iter_damage_not_visible
[15:24:01] ================ [PASSED] drm_damage_helper ================
[15:24:01] ============== drm_dp_mst_helper (3 subtests) ==============
[15:24:01] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[15:24:01] [PASSED] Clock 154000 BPP 30 DSC disabled
[15:24:01] [PASSED] Clock 234000 BPP 30 DSC disabled
[15:24:01] [PASSED] Clock 297000 BPP 24 DSC disabled
[15:24:01] [PASSED] Clock 332880 BPP 24 DSC enabled
[15:24:01] [PASSED] Clock 324540 BPP 24 DSC enabled
[15:24:01] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[15:24:01] ============== drm_test_dp_mst_calc_pbn_div  ===============
[15:24:01] [PASSED] Link rate 2000000 lane count 4
[15:24:01] [PASSED] Link rate 2000000 lane count 2
[15:24:01] [PASSED] Link rate 2000000 lane count 1
[15:24:01] [PASSED] Link rate 1350000 lane count 4
[15:24:01] [PASSED] Link rate 1350000 lane count 2
[15:24:01] [PASSED] Link rate 1350000 lane count 1
[15:24:01] [PASSED] Link rate 1000000 lane count 4
[15:24:01] [PASSED] Link rate 1000000 lane count 2
[15:24:01] [PASSED] Link rate 1000000 lane count 1
[15:24:01] [PASSED] Link rate 810000 lane count 4
[15:24:01] [PASSED] Link rate 810000 lane count 2
[15:24:01] [PASSED] Link rate 810000 lane count 1
[15:24:01] [PASSED] Link rate 540000 lane count 4
[15:24:01] [PASSED] Link rate 540000 lane count 2
[15:24:01] [PASSED] Link rate 540000 lane count 1
[15:24:01] [PASSED] Link rate 270000 lane count 4
[15:24:01] [PASSED] Link rate 270000 lane count 2
[15:24:01] [PASSED] Link rate 270000 lane count 1
[15:24:01] [PASSED] Link rate 162000 lane count 4
[15:24:01] [PASSED] Link rate 162000 lane count 2
[15:24:01] [PASSED] Link rate 162000 lane count 1
[15:24:01] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[15:24:01] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[15:24:01] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[15:24:01] [PASSED] DP_POWER_UP_PHY with port number
[15:24:01] [PASSED] DP_POWER_DOWN_PHY with port number
[15:24:01] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[15:24:01] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[15:24:01] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[15:24:01] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[15:24:01] [PASSED] DP_QUERY_PAYLOAD with port number
[15:24:01] [PASSED] DP_QUERY_PAYLOAD with VCPI
[15:24:01] [PASSED] DP_REMOTE_DPCD_READ with port number
[15:24:01] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[15:24:01] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[15:24:01] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[15:24:01] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[15:24:01] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[15:24:01] [PASSED] DP_REMOTE_I2C_READ with port number
[15:24:01] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[15:24:01] [PASSED] DP_REMOTE_I2C_READ with transactions array
[15:24:01] [PASSED] DP_REMOTE_I2C_WRITE with port number
[15:24:01] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[15:24:01] [PASSED] DP_REMOTE_I2C_WRITE with data array
[15:24:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[15:24:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[15:24:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[15:24:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[15:24:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[15:24:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[15:24:01] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[15:24:01] ================ [PASSED] drm_dp_mst_helper ================
[15:24:01] ================== drm_exec (7 subtests) ===================
[15:24:01] [PASSED] sanitycheck
[15:24:01] [PASSED] test_lock
[15:24:01] [PASSED] test_lock_unlock
[15:24:01] [PASSED] test_duplicates
[15:24:01] [PASSED] test_prepare
[15:24:01] [PASSED] test_prepare_array
[15:24:01] [PASSED] test_multiple_loops
[15:24:01] ==================== [PASSED] drm_exec =====================
[15:24:01] =========== drm_format_helper_test (17 subtests) ===========
[15:24:01] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[15:24:01] [PASSED] single_pixel_source_buffer
[15:24:01] [PASSED] single_pixel_clip_rectangle
[15:24:01] [PASSED] well_known_colors
[15:24:01] [PASSED] destination_pitch
[15:24:01] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[15:24:01] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[15:24:01] [PASSED] single_pixel_source_buffer
[15:24:01] [PASSED] single_pixel_clip_rectangle
[15:24:01] [PASSED] well_known_colors
[15:24:01] [PASSED] destination_pitch
[15:24:01] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[15:24:01] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[15:24:01] [PASSED] single_pixel_source_buffer
[15:24:01] [PASSED] single_pixel_clip_rectangle
[15:24:01] [PASSED] well_known_colors
[15:24:01] [PASSED] destination_pitch
[15:24:01] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[15:24:01] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[15:24:01] [PASSED] single_pixel_source_buffer
[15:24:01] [PASSED] single_pixel_clip_rectangle
[15:24:01] [PASSED] well_known_colors
[15:24:01] [PASSED] destination_pitch
[15:24:01] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[15:24:01] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[15:24:01] [PASSED] single_pixel_source_buffer
[15:24:01] [PASSED] single_pixel_clip_rectangle
[15:24:01] [PASSED] well_known_colors
[15:24:01] [PASSED] destination_pitch
[15:24:01] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[15:24:01] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[15:24:01] [PASSED] single_pixel_source_buffer
[15:24:01] [PASSED] single_pixel_clip_rectangle
[15:24:01] [PASSED] well_known_colors
[15:24:01] [PASSED] destination_pitch
[15:24:01] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[15:24:01] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[15:24:01] [PASSED] single_pixel_source_buffer
[15:24:01] [PASSED] single_pixel_clip_rectangle
[15:24:01] [PASSED] well_known_colors
[15:24:01] [PASSED] destination_pitch
[15:24:01] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[15:24:01] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[15:24:01] [PASSED] single_pixel_source_buffer
[15:24:01] [PASSED] single_pixel_clip_rectangle
[15:24:01] [PASSED] well_known_colors
[15:24:01] [PASSED] destination_pitch
[15:24:01] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[15:24:01] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[15:24:01] [PASSED] single_pixel_source_buffer
[15:24:01] [PASSED] single_pixel_clip_rectangle
[15:24:01] [PASSED] well_known_colors
[15:24:01] [PASSED] destination_pitch
[15:24:01] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[15:24:01] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[15:24:01] [PASSED] single_pixel_source_buffer
[15:24:01] [PASSED] single_pixel_clip_rectangle
[15:24:01] [PASSED] well_known_colors
[15:24:01] [PASSED] destination_pitch
[15:24:01] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[15:24:01] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[15:24:01] [PASSED] single_pixel_source_buffer
[15:24:01] [PASSED] single_pixel_clip_rectangle
[15:24:01] [PASSED] well_known_colors
[15:24:01] [PASSED] destination_pitch
[15:24:01] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[15:24:01] ============== drm_test_fb_xrgb8888_to_mono  ===============
[15:24:01] [PASSED] single_pixel_source_buffer
[15:24:01] [PASSED] single_pixel_clip_rectangle
[15:24:01] [PASSED] well_known_colors
[15:24:01] [PASSED] destination_pitch
[15:24:01] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[15:24:01] ==================== drm_test_fb_swab  =====================
[15:24:01] [PASSED] single_pixel_source_buffer
[15:24:01] [PASSED] single_pixel_clip_rectangle
[15:24:01] [PASSED] well_known_colors
[15:24:01] [PASSED] destination_pitch
[15:24:01] ================ [PASSED] drm_test_fb_swab =================
[15:24:01] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[15:24:01] [PASSED] single_pixel_source_buffer
[15:24:01] [PASSED] single_pixel_clip_rectangle
[15:24:01] [PASSED] well_known_colors
[15:24:01] [PASSED] destination_pitch
[15:24:01] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[15:24:01] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[15:24:01] [PASSED] single_pixel_source_buffer
[15:24:01] [PASSED] single_pixel_clip_rectangle
[15:24:01] [PASSED] well_known_colors
[15:24:01] [PASSED] destination_pitch
[15:24:01] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[15:24:01] ================= drm_test_fb_clip_offset  =================
[15:24:01] [PASSED] pass through
[15:24:01] [PASSED] horizontal offset
[15:24:01] [PASSED] vertical offset
[15:24:01] [PASSED] horizontal and vertical offset
[15:24:01] [PASSED] horizontal offset (custom pitch)
[15:24:01] [PASSED] vertical offset (custom pitch)
[15:24:01] [PASSED] horizontal and vertical offset (custom pitch)
[15:24:01] ============= [PASSED] drm_test_fb_clip_offset =============
[15:24:01] =================== drm_test_fb_memcpy  ====================
[15:24:01] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[15:24:01] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[15:24:01] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[15:24:01] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[15:24:01] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[15:24:01] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[15:24:01] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[15:24:01] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[15:24:01] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[15:24:01] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[15:24:01] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[15:24:01] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[15:24:01] =============== [PASSED] drm_test_fb_memcpy ================
[15:24:01] ============= [PASSED] drm_format_helper_test ==============
[15:24:01] ================= drm_format (18 subtests) =================
[15:24:01] [PASSED] drm_test_format_block_width_invalid
[15:24:01] [PASSED] drm_test_format_block_width_one_plane
[15:24:01] [PASSED] drm_test_format_block_width_two_plane
[15:24:01] [PASSED] drm_test_format_block_width_three_plane
[15:24:01] [PASSED] drm_test_format_block_width_tiled
[15:24:01] [PASSED] drm_test_format_block_height_invalid
[15:24:01] [PASSED] drm_test_format_block_height_one_plane
[15:24:01] [PASSED] drm_test_format_block_height_two_plane
[15:24:01] [PASSED] drm_test_format_block_height_three_plane
[15:24:01] [PASSED] drm_test_format_block_height_tiled
[15:24:01] [PASSED] drm_test_format_min_pitch_invalid
[15:24:01] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[15:24:01] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[15:24:01] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[15:24:01] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[15:24:01] [PASSED] drm_test_format_min_pitch_two_plane
[15:24:01] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[15:24:01] [PASSED] drm_test_format_min_pitch_tiled
[15:24:01] =================== [PASSED] drm_format ====================
[15:24:01] ============== drm_framebuffer (10 subtests) ===============
[15:24:01] ========== drm_test_framebuffer_check_src_coords  ==========
[15:24:01] [PASSED] Success: source fits into fb
[15:24:01] [PASSED] Fail: overflowing fb with x-axis coordinate
[15:24:01] [PASSED] Fail: overflowing fb with y-axis coordinate
[15:24:01] [PASSED] Fail: overflowing fb with source width
[15:24:01] [PASSED] Fail: overflowing fb with source height
[15:24:01] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[15:24:01] [PASSED] drm_test_framebuffer_cleanup
[15:24:01] =============== drm_test_framebuffer_create  ===============
[15:24:01] [PASSED] ABGR8888 normal sizes
[15:24:01] [PASSED] ABGR8888 max sizes
[15:24:01] [PASSED] ABGR8888 pitch greater than min required
[15:24:01] [PASSED] ABGR8888 pitch less than min required
[15:24:01] [PASSED] ABGR8888 Invalid width
[15:24:01] [PASSED] ABGR8888 Invalid buffer handle
[15:24:01] [PASSED] No pixel format
[15:24:01] [PASSED] ABGR8888 Width 0
[15:24:01] [PASSED] ABGR8888 Height 0
[15:24:01] [PASSED] ABGR8888 Out of bound height * pitch combination
[15:24:01] [PASSED] ABGR8888 Large buffer offset
[15:24:01] [PASSED] ABGR8888 Buffer offset for inexistent plane
[15:24:01] [PASSED] ABGR8888 Invalid flag
[15:24:01] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[15:24:01] [PASSED] ABGR8888 Valid buffer modifier
[15:24:01] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[15:24:01] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[15:24:01] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[15:24:01] [PASSED] NV12 Normal sizes
[15:24:01] [PASSED] NV12 Max sizes
[15:24:01] [PASSED] NV12 Invalid pitch
[15:24:01] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[15:24:01] [PASSED] NV12 different  modifier per-plane
[15:24:01] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[15:24:01] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[15:24:01] [PASSED] NV12 Modifier for inexistent plane
[15:24:01] [PASSED] NV12 Handle for inexistent plane
[15:24:01] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[15:24:01] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[15:24:01] [PASSED] YVU420 Normal sizes
[15:24:01] [PASSED] YVU420 Max sizes
[15:24:01] [PASSED] YVU420 Invalid pitch
[15:24:01] [PASSED] YVU420 Different pitches
[15:24:01] [PASSED] YVU420 Different buffer offsets/pitches
[15:24:01] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[15:24:01] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[15:24:01] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[15:24:01] [PASSED] YVU420 Valid modifier
[15:24:01] [PASSED] YVU420 Different modifiers per plane
[15:24:01] [PASSED] YVU420 Modifier for inexistent plane
[15:24:01] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[15:24:01] [PASSED] X0L2 Normal sizes
[15:24:01] [PASSED] X0L2 Max sizes
[15:24:01] [PASSED] X0L2 Invalid pitch
[15:24:01] [PASSED] X0L2 Pitch greater than minimum required
[15:24:01] [PASSED] X0L2 Handle for inexistent plane
[15:24:01] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[15:24:01] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[15:24:01] [PASSED] X0L2 Valid modifier
[15:24:01] [PASSED] X0L2 Modifier for inexistent plane
[15:24:01] =========== [PASSED] drm_test_framebuffer_create ===========
[15:24:01] [PASSED] drm_test_framebuffer_free
[15:24:01] [PASSED] drm_test_framebuffer_init
[15:24:01] [PASSED] drm_test_framebuffer_init_bad_format
[15:24:01] [PASSED] drm_test_framebuffer_init_dev_mismatch
[15:24:01] [PASSED] drm_test_framebuffer_lookup
[15:24:01] [PASSED] drm_test_framebuffer_lookup_inexistent
[15:24:01] [PASSED] drm_test_framebuffer_modifiers_not_supported
[15:24:01] ================= [PASSED] drm_framebuffer =================
[15:24:01] ================ drm_gem_shmem (8 subtests) ================
[15:24:01] [PASSED] drm_gem_shmem_test_obj_create
[15:24:01] [PASSED] drm_gem_shmem_test_obj_create_private
[15:24:01] [PASSED] drm_gem_shmem_test_pin_pages
[15:24:01] [PASSED] drm_gem_shmem_test_vmap
[15:24:01] [PASSED] drm_gem_shmem_test_get_sg_table
[15:24:01] [PASSED] drm_gem_shmem_test_get_pages_sgt
[15:24:01] [PASSED] drm_gem_shmem_test_madvise
[15:24:01] [PASSED] drm_gem_shmem_test_purge
[15:24:01] ================== [PASSED] drm_gem_shmem ==================
[15:24:01] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[15:24:01] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[15:24:01] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[15:24:01] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[15:24:01] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[15:24:01] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[15:24:01] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[15:24:01] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[15:24:01] [PASSED] Automatic
[15:24:01] [PASSED] Full
[15:24:01] [PASSED] Limited 16:235
[15:24:01] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[15:24:01] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[15:24:01] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[15:24:01] [PASSED] drm_test_check_disable_connector
[15:24:01] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[15:24:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[15:24:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[15:24:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[15:24:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[15:24:01] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[15:24:01] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[15:24:01] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[15:24:01] [PASSED] drm_test_check_output_bpc_dvi
[15:24:01] [PASSED] drm_test_check_output_bpc_format_vic_1
[15:24:01] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[15:24:01] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[15:24:01] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[15:24:01] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[15:24:01] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[15:24:01] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[15:24:01] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[15:24:01] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[15:24:01] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[15:24:01] [PASSED] drm_test_check_broadcast_rgb_value
[15:24:01] [PASSED] drm_test_check_bpc_8_value
[15:24:01] [PASSED] drm_test_check_bpc_10_value
[15:24:01] [PASSED] drm_test_check_bpc_12_value
[15:24:01] [PASSED] drm_test_check_format_value
[15:24:01] [PASSED] drm_test_check_tmds_char_value
[15:24:01] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[15:24:01] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[15:24:01] [PASSED] drm_test_check_mode_valid
[15:24:01] [PASSED] drm_test_check_mode_valid_reject
[15:24:01] [PASSED] drm_test_check_mode_valid_reject_rate
[15:24:01] [PASSED] drm_test_check_mode_valid_reject_max_clock
[15:24:01] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[15:24:01] ================= drm_managed (2 subtests) =================
[15:24:01] [PASSED] drm_test_managed_release_action
[15:24:01] [PASSED] drm_test_managed_run_action
[15:24:01] =================== [PASSED] drm_managed ===================
[15:24:01] =================== drm_mm (6 subtests) ====================
[15:24:01] [PASSED] drm_test_mm_init
[15:24:01] [PASSED] drm_test_mm_debug
[15:24:01] [PASSED] drm_test_mm_align32
[15:24:01] [PASSED] drm_test_mm_align64
[15:24:01] [PASSED] drm_test_mm_lowest
[15:24:01] [PASSED] drm_test_mm_highest
[15:24:01] ===================== [PASSED] drm_mm ======================
[15:24:01] ============= drm_modes_analog_tv (5 subtests) =============
[15:24:01] [PASSED] drm_test_modes_analog_tv_mono_576i
[15:24:01] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[15:24:01] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[15:24:01] [PASSED] drm_test_modes_analog_tv_pal_576i
[15:24:01] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[15:24:01] =============== [PASSED] drm_modes_analog_tv ===============
[15:24:01] ============== drm_plane_helper (2 subtests) ===============
[15:24:01] =============== drm_test_check_plane_state  ================
[15:24:01] [PASSED] clipping_simple
[15:24:01] [PASSED] clipping_rotate_reflect
[15:24:01] [PASSED] positioning_simple
[15:24:01] [PASSED] upscaling
[15:24:01] [PASSED] downscaling
[15:24:01] [PASSED] rounding1
[15:24:01] [PASSED] rounding2
[15:24:01] [PASSED] rounding3
[15:24:01] [PASSED] rounding4
[15:24:01] =========== [PASSED] drm_test_check_plane_state ============
[15:24:01] =========== drm_test_check_invalid_plane_state  ============
[15:24:01] [PASSED] positioning_invalid
[15:24:01] [PASSED] upscaling_invalid
[15:24:01] [PASSED] downscaling_invalid
[15:24:01] ======= [PASSED] drm_test_check_invalid_plane_state ========
[15:24:01] ================ [PASSED] drm_plane_helper =================
[15:24:01] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[15:24:01] ====== drm_test_connector_helper_tv_get_modes_check  =======
[15:24:01] [PASSED] None
[15:24:01] [PASSED] PAL
[15:24:01] [PASSED] NTSC
[15:24:01] [PASSED] Both, NTSC Default
[15:24:01] [PASSED] Both, PAL Default
[15:24:01] [PASSED] Both, NTSC Default, with PAL on command-line
[15:24:01] [PASSED] Both, PAL Default, with NTSC on command-line
[15:24:01] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[15:24:01] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[15:24:01] ================== drm_rect (9 subtests) ===================
[15:24:01] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[15:24:01] [PASSED] drm_test_rect_clip_scaled_not_clipped
[15:24:01] [PASSED] drm_test_rect_clip_scaled_clipped
[15:24:01] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[15:24:01] ================= drm_test_rect_intersect  =================
[15:24:01] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[15:24:01] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[15:24:01] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[15:24:01] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[15:24:01] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[15:24:01] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[15:24:01] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[15:24:01] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[15:24:01] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[15:24:01] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[15:24:01] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[15:24:01] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[15:24:01] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[15:24:01] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[15:24:01] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[15:24:01] ============= [PASSED] drm_test_rect_intersect =============
[15:24:01] ================ drm_test_rect_calc_hscale  ================
[15:24:01] [PASSED] normal use
[15:24:01] [PASSED] out of max range
[15:24:01] [PASSED] out of min range
[15:24:01] [PASSED] zero dst
[15:24:01] [PASSED] negative src
[15:24:01] [PASSED] negative dst
[15:24:01] ============ [PASSED] drm_test_rect_calc_hscale ============
[15:24:01] ================ drm_test_rect_calc_vscale  ================
[15:24:01] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[15:24:01] [PASSED] out of max range
[15:24:01] [PASSED] out of min range
[15:24:01] [PASSED] zero dst
[15:24:01] [PASSED] negative src
[15:24:01] [PASSED] negative dst
[15:24:01] ============ [PASSED] drm_test_rect_calc_vscale ============
[15:24:01] ================== drm_test_rect_rotate  ===================
[15:24:01] [PASSED] reflect-x
[15:24:01] [PASSED] reflect-y
[15:24:01] [PASSED] rotate-0
[15:24:01] [PASSED] rotate-90
[15:24:01] [PASSED] rotate-180
[15:24:01] [PASSED] rotate-270
[15:24:01] ============== [PASSED] drm_test_rect_rotate ===============
[15:24:01] ================ drm_test_rect_rotate_inv  =================
[15:24:01] [PASSED] reflect-x
[15:24:01] [PASSED] reflect-y
[15:24:01] [PASSED] rotate-0
[15:24:01] [PASSED] rotate-90
[15:24:01] [PASSED] rotate-180
[15:24:01] [PASSED] rotate-270
[15:24:01] ============ [PASSED] drm_test_rect_rotate_inv =============
[15:24:01] ==================== [PASSED] drm_rect =====================
[15:24:01] ============ drm_sysfb_modeset_test (1 subtest) ============
[15:24:01] ============ drm_test_sysfb_build_fourcc_list  =============
[15:24:01] [PASSED] no native formats
[15:24:01] [PASSED] XRGB8888 as native format
[15:24:01] [PASSED] remove duplicates
[15:24:01] [PASSED] convert alpha formats
[15:24:01] [PASSED] random formats
[15:24:01] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[15:24:01] ============= [PASSED] drm_sysfb_modeset_test ==============
[15:24:01] ================== drm_fixp (2 subtests) ===================
[15:24:01] [PASSED] drm_test_int2fixp
[15:24:01] [PASSED] drm_test_sm2fixp
[15:24:01] ==================== [PASSED] drm_fixp =====================
[15:24:01] ============================================================
[15:24:01] Testing complete. Ran 624 tests: passed: 624
[15:24:01] Elapsed time: 27.661s total, 1.685s configuring, 25.548s building, 0.410s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[15:24:01] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:24:02] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:24:12] Starting KUnit Kernel (1/1)...
[15:24:12] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:24:12] ================= ttm_device (5 subtests) ==================
[15:24:12] [PASSED] ttm_device_init_basic
[15:24:12] [PASSED] ttm_device_init_multiple
[15:24:12] [PASSED] ttm_device_fini_basic
[15:24:12] [PASSED] ttm_device_init_no_vma_man
[15:24:12] ================== ttm_device_init_pools  ==================
[15:24:12] [PASSED] No DMA allocations, no DMA32 required
[15:24:12] [PASSED] DMA allocations, DMA32 required
[15:24:12] [PASSED] No DMA allocations, DMA32 required
[15:24:12] [PASSED] DMA allocations, no DMA32 required
[15:24:12] ============== [PASSED] ttm_device_init_pools ==============
[15:24:12] =================== [PASSED] ttm_device ====================
[15:24:12] ================== ttm_pool (8 subtests) ===================
[15:24:12] ================== ttm_pool_alloc_basic  ===================
[15:24:12] [PASSED] One page
[15:24:12] [PASSED] More than one page
[15:24:12] [PASSED] Above the allocation limit
[15:24:12] [PASSED] One page, with coherent DMA mappings enabled
[15:24:12] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:24:12] ============== [PASSED] ttm_pool_alloc_basic ===============
[15:24:12] ============== ttm_pool_alloc_basic_dma_addr  ==============
[15:24:12] [PASSED] One page
[15:24:12] [PASSED] More than one page
[15:24:12] [PASSED] Above the allocation limit
[15:24:12] [PASSED] One page, with coherent DMA mappings enabled
[15:24:12] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:24:12] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[15:24:12] [PASSED] ttm_pool_alloc_order_caching_match
[15:24:12] [PASSED] ttm_pool_alloc_caching_mismatch
[15:24:12] [PASSED] ttm_pool_alloc_order_mismatch
[15:24:12] [PASSED] ttm_pool_free_dma_alloc
[15:24:12] [PASSED] ttm_pool_free_no_dma_alloc
[15:24:12] [PASSED] ttm_pool_fini_basic
[15:24:12] ==================== [PASSED] ttm_pool =====================
[15:24:12] ================ ttm_resource (8 subtests) =================
[15:24:12] ================= ttm_resource_init_basic  =================
[15:24:12] [PASSED] Init resource in TTM_PL_SYSTEM
[15:24:12] [PASSED] Init resource in TTM_PL_VRAM
[15:24:12] [PASSED] Init resource in a private placement
[15:24:12] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[15:24:12] ============= [PASSED] ttm_resource_init_basic =============
[15:24:12] [PASSED] ttm_resource_init_pinned
[15:24:12] [PASSED] ttm_resource_fini_basic
[15:24:12] [PASSED] ttm_resource_manager_init_basic
[15:24:12] [PASSED] ttm_resource_manager_usage_basic
[15:24:12] [PASSED] ttm_resource_manager_set_used_basic
[15:24:12] [PASSED] ttm_sys_man_alloc_basic
[15:24:12] [PASSED] ttm_sys_man_free_basic
[15:24:12] ================== [PASSED] ttm_resource ===================
[15:24:12] =================== ttm_tt (15 subtests) ===================
[15:24:12] ==================== ttm_tt_init_basic  ====================
[15:24:12] [PASSED] Page-aligned size
[15:24:12] [PASSED] Extra pages requested
[15:24:12] ================ [PASSED] ttm_tt_init_basic ================
[15:24:12] [PASSED] ttm_tt_init_misaligned
[15:24:12] [PASSED] ttm_tt_fini_basic
[15:24:12] [PASSED] ttm_tt_fini_sg
[15:24:12] [PASSED] ttm_tt_fini_shmem
[15:24:12] [PASSED] ttm_tt_create_basic
[15:24:12] [PASSED] ttm_tt_create_invalid_bo_type
[15:24:12] [PASSED] ttm_tt_create_ttm_exists
[15:24:12] [PASSED] ttm_tt_create_failed
[15:24:12] [PASSED] ttm_tt_destroy_basic
[15:24:12] [PASSED] ttm_tt_populate_null_ttm
[15:24:12] [PASSED] ttm_tt_populate_populated_ttm
[15:24:12] [PASSED] ttm_tt_unpopulate_basic
[15:24:12] [PASSED] ttm_tt_unpopulate_empty_ttm
[15:24:12] [PASSED] ttm_tt_swapin_basic
[15:24:12] ===================== [PASSED] ttm_tt ======================
[15:24:12] =================== ttm_bo (14 subtests) ===================
[15:24:12] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[15:24:12] [PASSED] Cannot be interrupted and sleeps
[15:24:12] [PASSED] Cannot be interrupted, locks straight away
[15:24:12] [PASSED] Can be interrupted, sleeps
[15:24:12] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[15:24:12] [PASSED] ttm_bo_reserve_locked_no_sleep
[15:24:12] [PASSED] ttm_bo_reserve_no_wait_ticket
[15:24:12] [PASSED] ttm_bo_reserve_double_resv
[15:24:12] [PASSED] ttm_bo_reserve_interrupted
[15:24:12] [PASSED] ttm_bo_reserve_deadlock
[15:24:12] [PASSED] ttm_bo_unreserve_basic
[15:24:12] [PASSED] ttm_bo_unreserve_pinned
[15:24:12] [PASSED] ttm_bo_unreserve_bulk
[15:24:12] [PASSED] ttm_bo_fini_basic
[15:24:12] [PASSED] ttm_bo_fini_shared_resv
[15:24:12] [PASSED] ttm_bo_pin_basic
[15:24:12] [PASSED] ttm_bo_pin_unpin_resource
[15:24:12] [PASSED] ttm_bo_multiple_pin_one_unpin
[15:24:12] ===================== [PASSED] ttm_bo ======================
[15:24:12] ============== ttm_bo_validate (21 subtests) ===============
[15:24:12] ============== ttm_bo_init_reserved_sys_man  ===============
[15:24:12] [PASSED] Buffer object for userspace
[15:24:12] [PASSED] Kernel buffer object
[15:24:12] [PASSED] Shared buffer object
[15:24:12] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[15:24:12] ============== ttm_bo_init_reserved_mock_man  ==============
[15:24:12] [PASSED] Buffer object for userspace
[15:24:12] [PASSED] Kernel buffer object
[15:24:12] [PASSED] Shared buffer object
[15:24:12] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[15:24:12] [PASSED] ttm_bo_init_reserved_resv
[15:24:12] ================== ttm_bo_validate_basic  ==================
[15:24:12] [PASSED] Buffer object for userspace
[15:24:12] [PASSED] Kernel buffer object
[15:24:12] [PASSED] Shared buffer object
[15:24:12] ============== [PASSED] ttm_bo_validate_basic ==============
[15:24:12] [PASSED] ttm_bo_validate_invalid_placement
[15:24:12] ============= ttm_bo_validate_same_placement  ==============
[15:24:12] [PASSED] System manager
[15:24:12] [PASSED] VRAM manager
[15:24:12] ========= [PASSED] ttm_bo_validate_same_placement ==========
[15:24:12] [PASSED] ttm_bo_validate_failed_alloc
[15:24:12] [PASSED] ttm_bo_validate_pinned
[15:24:12] [PASSED] ttm_bo_validate_busy_placement
[15:24:12] ================ ttm_bo_validate_multihop  =================
[15:24:12] [PASSED] Buffer object for userspace
[15:24:12] [PASSED] Kernel buffer object
[15:24:12] [PASSED] Shared buffer object
[15:24:12] ============ [PASSED] ttm_bo_validate_multihop =============
[15:24:12] ========== ttm_bo_validate_no_placement_signaled  ==========
[15:24:12] [PASSED] Buffer object in system domain, no page vector
[15:24:12] [PASSED] Buffer object in system domain with an existing page vector
[15:24:12] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[15:24:12] ======== ttm_bo_validate_no_placement_not_signaled  ========
[15:24:12] [PASSED] Buffer object for userspace
[15:24:12] [PASSED] Kernel buffer object
[15:24:12] [PASSED] Shared buffer object
[15:24:12] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[15:24:12] [PASSED] ttm_bo_validate_move_fence_signaled
[15:24:12] ========= ttm_bo_validate_move_fence_not_signaled  =========
[15:24:12] [PASSED] Waits for GPU
[15:24:12] [PASSED] Tries to lock straight away
[15:24:12] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[15:24:12] [PASSED] ttm_bo_validate_happy_evict
[15:24:12] [PASSED] ttm_bo_validate_all_pinned_evict
[15:24:12] [PASSED] ttm_bo_validate_allowed_only_evict
[15:24:12] [PASSED] ttm_bo_validate_deleted_evict
[15:24:12] [PASSED] ttm_bo_validate_busy_domain_evict
[15:24:12] [PASSED] ttm_bo_validate_evict_gutting
[15:24:12] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[15:24:12] ================= [PASSED] ttm_bo_validate =================
[15:24:12] ============================================================
[15:24:12] Testing complete. Ran 101 tests: passed: 101
[15:24:12] Elapsed time: 11.354s total, 1.675s configuring, 9.462s building, 0.178s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 8+ messages in thread

* ✓ Xe.CI.BAT: success for drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms
  2025-12-30 15:17 [PATCH v1 0/1] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms Anoop, Vijay
                   ` (2 preceding siblings ...)
  2025-12-30 15:24 ` ✓ CI.KUnit: success " Patchwork
@ 2025-12-30 15:57 ` Patchwork
  2025-12-30 16:57 ` ✓ Xe.CI.Full: " Patchwork
  4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2025-12-30 15:57 UTC (permalink / raw)
  To: Anoop, Vijay; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 1566 bytes --]

== Series Details ==

Series: drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms
URL   : https://patchwork.freedesktop.org/series/159554/
State : success

== Summary ==

CI Bug Log - changes from xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb_BAT -> xe-pw-159554v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 11)
------------------------------

  Missing    (1): bat-bmg-1 

Known issues
------------

  Here are the changes found in xe-pw-159554v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@reltime:
    - bat-dg2-oem2:       [PASS][1] -> [FAIL][2] ([Intel XE#6520])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/bat-dg2-oem2/igt@xe_waitfence@reltime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/bat-dg2-oem2/igt@xe_waitfence@reltime.html

  
  [Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520


Build changes
-------------

  * IGT: IGT_8679 -> IGT_8681
  * Linux: xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb -> xe-pw-159554v1

  IGT_8679: 8679
  IGT_8681: c49f35440873244aa86e778007ed2dcbe5bf0ecb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb: 633f3e5eab13c5bc2d760d1f3db65eb346d9babb
  xe-pw-159554v1: 159554v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/index.html

[-- Attachment #2: Type: text/html, Size: 2145 bytes --]

^ permalink raw reply	[flat|nested] 8+ messages in thread

* ✓ Xe.CI.Full: success for drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms
  2025-12-30 15:17 [PATCH v1 0/1] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms Anoop, Vijay
                   ` (3 preceding siblings ...)
  2025-12-30 15:57 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-12-30 16:57 ` Patchwork
  4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2025-12-30 16:57 UTC (permalink / raw)
  To: Anoop, Vijay; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 58008 bytes --]

== Series Details ==

Series: drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms
URL   : https://patchwork.freedesktop.org/series/159554/
State : success

== Summary ==

CI Bug Log - changes from xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb_FULL -> xe-pw-159554v1_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-159554v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear:
    - shard-lnl:          [PASS][1] -> [FAIL][2] ([Intel XE#5993]) +3 other tests fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-4/igt@kms_async_flips@async-flip-with-page-flip-events-linear.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-4/igt@kms_async_flips@async-flip-with-page-flip-events-linear.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2327]) +4 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-3/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][4] ([Intel XE#1407]) +2 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-lnl:          NOTRUN -> [SKIP][5] ([Intel XE#1477])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#607])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-3/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#1124]) +4 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#1467])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-2/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#1124]) +15 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-9/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2314] / [Intel XE#2894]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-2/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-2-displays-3840x2160p:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#367])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@kms_bw@linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-4-displays-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#367]) +3 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-7/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#3432])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc.html
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#3432]) +2 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#2887]) +5 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2887]) +17 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-9/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2724]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-3/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_chamelium_color@ctm-0-50:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2325])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-7/igt@kms_chamelium_color@ctm-0-50.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2252]) +12 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-3/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@vga-hpd-fast:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#373]) +4 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-7/igt@kms_chamelium_hpd@vga-hpd-fast.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2390])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-3/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@dp-mst-suspend-resume:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#6743])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-1/igt@kms_content_protection@dp-mst-suspend-resume.html

  * igt@kms_content_protection@lic-type-1:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2341])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-2/igt@kms_content_protection@lic-type-1.html

  * igt@kms_content_protection@srm@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][24] ([Intel XE#1178]) +3 other tests fail
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-10/igt@kms_content_protection@srm@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2321]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-9/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#2321])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-7/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-max-size:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2320]) +6 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-7/igt@kms_cursor_crc@cursor-onscreen-max-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#309]) +2 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-2/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2286])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#1340])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2244]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-9/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_fb_coherency@memset-crc:
    - shard-bmg:          NOTRUN -> [CRASH][32] ([Intel XE#6706]) +1 other test crash
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-8/igt@kms_fb_coherency@memset-crc.html

  * igt@kms_fb_coherency@memset-crc@mmap-offset-wc:
    - shard-lnl:          NOTRUN -> [CRASH][33] ([Intel XE#6706]) +1 other test crash
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-2/igt@kms_fb_coherency@memset-crc@mmap-offset-wc.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#4156])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-9/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_feature_discovery@display-4x:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#1138])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-8/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2375])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-1/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [PASS][37] -> [FAIL][38] ([Intel XE#301])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#1397] / [Intel XE#1745])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#1397])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#2293] / [Intel XE#2380]) +5 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2293]) +5 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#1401] / [Intel XE#1745])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#1401])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2380]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#651]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-4/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2311]) +43 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-9/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#4141]) +16 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#6312])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#656]) +9 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2313]) +45 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_hdmi_inject@inject-4k:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#1470])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-3/igt@kms_hdmi_inject@inject-4k.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#6911]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-8/igt@kms_joiner@basic-force-ultra-joiner.html
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#6900])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-2/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#6901])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#4329] / [Intel XE#6912])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-8/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#2393])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-10/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#5021])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#736])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-4/igt@kms_pm_dc@dc3co-vpb-simulation.html
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#2391])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-3/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#3309])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@kms_pm_dc@dc5-retention-flops.html
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#3309])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-1/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-lnl:          [PASS][63] -> [FAIL][64] ([Intel XE#718])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-3/igt@kms_pm_dc@dc6-psr.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-4/igt@kms_pm_dc@dc6-psr.html
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#2392])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-10/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#2499])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-2/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#1406] / [Intel XE#2893]) +1 other test skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-3/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#1406] / [Intel XE#2893] / [Intel XE#4608])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#1406] / [Intel XE#4608]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#1406] / [Intel XE#1489]) +11 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-10/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#1406] / [Intel XE#2387]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-8/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-lnl:          NOTRUN -> [SKIP][72] ([Intel XE#1128] / [Intel XE#1406])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-5/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#1406] / [Intel XE#4609])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@kms_psr@fbc-psr2-cursor-plane-move@edp-1.html

  * igt@kms_psr@pr-no-drrs:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#1406]) +2 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@kms_psr@pr-no-drrs.html

  * igt@kms_psr@psr-primary-page-flip:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +17 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-3/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#1406] / [Intel XE#2414])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-lnl:          NOTRUN -> [SKIP][77] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-4/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#3414] / [Intel XE#3904]) +2 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-10/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_sharpness_filter@filter-rotations:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#6503]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-1/igt@kms_sharpness_filter@filter-rotations.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#2450])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-10/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vrr@flip-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][81] ([Intel XE#1499]) +1 other test skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-9/igt@kms_vrr@flip-suspend.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [PASS][82] -> [FAIL][83] ([Intel XE#2142]) +1 other test fail
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-7/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_configfs@survivability-mode:
    - shard-lnl:          NOTRUN -> [SKIP][84] ([Intel XE#6010])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-2/igt@xe_configfs@survivability-mode.html

  * igt@xe_eudebug@basic-vm-bind-metadata-discovery:
    - shard-bmg:          NOTRUN -> [SKIP][85] ([Intel XE#4837]) +11 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-10/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html

  * igt@xe_eudebug@basic-vm-bind-ufence-reconnect:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#4837]) +1 other test skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@xe_eudebug@basic-vm-bind-ufence-reconnect.html

  * igt@xe_eudebug_online@set-breakpoint-sigint-debugger:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#4837] / [Intel XE#6665]) +6 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-9/igt@xe_eudebug_online@set-breakpoint-sigint-debugger.html

  * igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram:
    - shard-lnl:          NOTRUN -> [SKIP][88] ([Intel XE#4837] / [Intel XE#6665]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-4/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram.html

  * igt@xe_eudebug_sriov@deny-sriov:
    - shard-bmg:          NOTRUN -> [SKIP][89] ([Intel XE#5793])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-1/igt@xe_eudebug_sriov@deny-sriov.html

  * igt@xe_evict@evict-small-cm:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#688]) +2 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-7/igt@xe_evict@evict-small-cm.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][91] ([Intel XE#1392]) +1 other test skip
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-5/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-once-null-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][92] ([Intel XE#2322]) +10 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-1/igt@xe_exec_basic@multigpu-once-null-rebind.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-close-fd:
    - shard-lnl:          NOTRUN -> [SKIP][93] ([Intel XE#6874]) +10 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-3/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-close-fd.html

  * igt@xe_exec_multi_queue@one-queue-priority-smem:
    - shard-bmg:          NOTRUN -> [SKIP][94] ([Intel XE#6874]) +42 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-7/igt@xe_exec_multi_queue@one-queue-priority-smem.html

  * igt@xe_exec_system_allocator@many-64k-mmap-free-huge-nomemset:
    - shard-lnl:          NOTRUN -> [SKIP][95] ([Intel XE#5007])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-7/igt@xe_exec_system_allocator@many-64k-mmap-free-huge-nomemset.html
    - shard-bmg:          NOTRUN -> [SKIP][96] ([Intel XE#5007]) +1 other test skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-2/igt@xe_exec_system_allocator@many-64k-mmap-free-huge-nomemset.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma:
    - shard-lnl:          [PASS][97] -> [FAIL][98] ([Intel XE#5625])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-7/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-3/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge:
    - shard-bmg:          NOTRUN -> [SKIP][99] ([Intel XE#4943]) +28 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-7/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge.html

  * igt@xe_exec_system_allocator@twice-large-mmap-new-huge:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#4943]) +3 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-7/igt@xe_exec_system_allocator@twice-large-mmap-new-huge.html

  * igt@xe_media_fill@media-fill:
    - shard-bmg:          NOTRUN -> [SKIP][101] ([Intel XE#2459] / [Intel XE#2596])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-1/igt@xe_media_fill@media-fill.html

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126]) -> ([PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [SKIP][145], [PASS][146], [PASS][147], [PASS][148], [PASS][149], [PASS][150], [PASS][151], [PASS][152]) ([Intel XE#378])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-1/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-2/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-2/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-1/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-2/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-3/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-3/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-3/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-3/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-7/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-7/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-7/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-5/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-5/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-5/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-4/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-4/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-4/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-4/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-8/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-8/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-5/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-8/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-1/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-1/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-7/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-5/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-5/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-8/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-2/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-2/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-8/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-7/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-7/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-2/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-8/igt@xe_module_load@load.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@xe_module_load@load.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@xe_module_load@load.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@xe_module_load@load.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-4/igt@xe_module_load@load.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-4/igt@xe_module_load@load.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-2/igt@xe_module_load@load.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-3/igt@xe_module_load@load.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-4/igt@xe_module_load@load.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-8/igt@xe_module_load@load.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-5/igt@xe_module_load@load.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-7/igt@xe_module_load@load.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-3/igt@xe_module_load@load.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-3/igt@xe_module_load@load.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@xe_module_load@load.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-4/igt@xe_module_load@load.html
    - shard-bmg:          ([PASS][153], [PASS][154], [PASS][155], [PASS][156], [PASS][157], [PASS][158], [PASS][159], [PASS][160], [PASS][161], [PASS][162], [PASS][163], [PASS][164], [PASS][165], [PASS][166], [PASS][167], [PASS][168], [PASS][169], [PASS][170], [PASS][171], [PASS][172]) -> ([PASS][173], [PASS][174], [PASS][175], [PASS][176], [PASS][177], [PASS][178], [PASS][179], [PASS][180], [PASS][181], [PASS][182], [PASS][183], [PASS][184], [PASS][185], [PASS][186], [SKIP][187], [PASS][188], [PASS][189], [PASS][190], [PASS][191], [PASS][192], [PASS][193]) ([Intel XE#2457])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-3/igt@xe_module_load@load.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-2/igt@xe_module_load@load.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-3/igt@xe_module_load@load.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-2/igt@xe_module_load@load.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-2/igt@xe_module_load@load.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-9/igt@xe_module_load@load.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-9/igt@xe_module_load@load.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-7/igt@xe_module_load@load.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-7/igt@xe_module_load@load.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-7/igt@xe_module_load@load.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-7/igt@xe_module_load@load.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-1/igt@xe_module_load@load.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-1/igt@xe_module_load@load.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-1/igt@xe_module_load@load.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-10/igt@xe_module_load@load.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-10/igt@xe_module_load@load.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-10/igt@xe_module_load@load.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-8/igt@xe_module_load@load.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-8/igt@xe_module_load@load.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-8/igt@xe_module_load@load.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-2/igt@xe_module_load@load.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-7/igt@xe_module_load@load.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-9/igt@xe_module_load@load.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-10/igt@xe_module_load@load.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-8/igt@xe_module_load@load.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-2/igt@xe_module_load@load.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-8/igt@xe_module_load@load.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-3/igt@xe_module_load@load.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-10/igt@xe_module_load@load.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-10/igt@xe_module_load@load.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-7/igt@xe_module_load@load.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-7/igt@xe_module_load@load.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-3/igt@xe_module_load@load.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-3/igt@xe_module_load@load.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-10/igt@xe_module_load@load.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-8/igt@xe_module_load@load.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-1/igt@xe_module_load@load.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-1/igt@xe_module_load@load.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-2/igt@xe_module_load@load.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-1/igt@xe_module_load@load.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-9/igt@xe_module_load@load.html

  * igt@xe_pat@pat-index-xelp:
    - shard-bmg:          NOTRUN -> [SKIP][194] ([Intel XE#2245])
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-1/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-lnl:          NOTRUN -> [SKIP][195] ([Intel XE#979])
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-8/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_pm@s3-basic:
    - shard-lnl:          NOTRUN -> [SKIP][196] ([Intel XE#584])
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-4/igt@xe_pm@s3-basic.html

  * igt@xe_pm@s4-d3cold-basic-exec:
    - shard-bmg:          NOTRUN -> [SKIP][197] ([Intel XE#2284]) +1 other test skip
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-2/igt@xe_pm@s4-d3cold-basic-exec.html

  * igt@xe_pxp@pxp-termination-key-update-post-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][198] ([Intel XE#4733]) +3 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-3/igt@xe_pxp@pxp-termination-key-update-post-suspend.html

  * igt@xe_query@multigpu-query-invalid-cs-cycles:
    - shard-lnl:          NOTRUN -> [SKIP][199] ([Intel XE#944])
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-8/igt@xe_query@multigpu-query-invalid-cs-cycles.html

  * igt@xe_query@multigpu-query-pxp-status:
    - shard-bmg:          NOTRUN -> [SKIP][200] ([Intel XE#944]) +1 other test skip
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-10/igt@xe_query@multigpu-query-pxp-status.html

  * igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs:
    - shard-lnl:          NOTRUN -> [SKIP][201] ([Intel XE#4130])
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-1/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs.html

  * igt@xe_sriov_vram@vf-access-after-resize-up:
    - shard-bmg:          [PASS][202] -> [FAIL][203] ([Intel XE#5937])
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-7/igt@xe_sriov_vram@vf-access-after-resize-up.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-2/igt@xe_sriov_vram@vf-access-after-resize-up.html

  
#### Possible fixes ####

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2:
    - shard-bmg:          [INCOMPLETE][204] ([Intel XE#2705]) -> [PASS][205] +1 other test pass
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-3/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-10/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][206] ([Intel XE#4633]) -> [PASS][207]
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [FAIL][208] ([Intel XE#301]) -> [PASS][209]
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [FAIL][210] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][211] +2 other tests pass
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling:
    - shard-lnl:          [FAIL][212] ([Intel XE#4683]) -> [PASS][213] +3 other tests pass
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-1/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling@pipe-a-default-mode:
    - shard-lnl:          [FAIL][214] ([Intel XE#3106] / [Intel XE#4683]) -> [PASS][215] +1 other test pass
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-5/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling@pipe-a-default-mode.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling@pipe-a-default-mode.html

  * igt@kms_plane@pixel-format-source-clamping@pipe-b-plane-0:
    - shard-lnl:          [FAIL][216] ([Intel XE#5195]) -> [PASS][217] +2 other tests pass
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-3/igt@kms_plane@pixel-format-source-clamping@pipe-b-plane-0.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-8/igt@kms_plane@pixel-format-source-clamping@pipe-b-plane-0.html

  * igt@kms_plane_multiple@tiling-x@pipe-c-edp-1:
    - shard-lnl:          [FAIL][218] ([Intel XE#4658]) -> [PASS][219] +3 other tests pass
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-1/igt@kms_plane_multiple@tiling-x@pipe-c-edp-1.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-4/igt@kms_plane_multiple@tiling-x@pipe-c-edp-1.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-bmg:          [SKIP][220] ([Intel XE#2685] / [Intel XE#3307]) -> [PASS][221]
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-2/igt@kms_plane_scaling@intel-max-src-size.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-8/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-lnl:          [SKIP][222] ([Intel XE#1406] / [Intel XE#4692]) -> [PASS][223]
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-8/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@primary-x-tiled-reflect-x-180:
    - shard-lnl:          [FAIL][224] ([Intel XE#4689]) -> [PASS][225] +1 other test pass
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-2/igt@kms_rotation_crc@primary-x-tiled-reflect-x-180.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-5/igt@kms_rotation_crc@primary-x-tiled-reflect-x-180.html

  * igt@kms_setmode@basic@pipe-b-edp-1:
    - shard-lnl:          [FAIL][226] ([Intel XE#6361]) -> [PASS][227]
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-2/igt@kms_setmode@basic@pipe-b-edp-1.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-8/igt@kms_setmode@basic@pipe-b-edp-1.html

  * igt@xe_pmu@engine-activity-accuracy-50:
    - shard-lnl:          [FAIL][228] ([Intel XE#6251]) -> [PASS][229] +1 other test pass
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-50.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-8/igt@xe_pmu@engine-activity-accuracy-50.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][230] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][231] ([Intel XE#301])
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][232] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][233] ([Intel XE#3544])
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-3/igt@kms_hdr@brightness-with-hdr.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-10/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][234] ([Intel XE#2509]) -> [SKIP][235] ([Intel XE#2426])
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1467
  [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
  [Intel XE#1477]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1477
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2391
  [Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2450
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
  [Intel XE#2499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2499
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
  [Intel XE#2685]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2685
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3106]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3106
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3307
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
  [Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
  [Intel XE#4658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4658
  [Intel XE#4683]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4683
  [Intel XE#4689]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4689
  [Intel XE#4692]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4692
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5195
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5793
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5937
  [Intel XE#5993]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5993
  [Intel XE#6010]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6010
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6361
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6706]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6706
  [Intel XE#6743]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6743
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#736]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/736
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979


Build changes
-------------

  * IGT: IGT_8679 -> IGT_8681
  * Linux: xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb -> xe-pw-159554v1

  IGT_8679: 8679
  IGT_8681: c49f35440873244aa86e778007ed2dcbe5bf0ecb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4315-633f3e5eab13c5bc2d760d1f3db65eb346d9babb: 633f3e5eab13c5bc2d760d1f3db65eb346d9babb
  xe-pw-159554v1: 159554v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v1/index.html

[-- Attachment #2: Type: text/html, Size: 64397 bytes --]

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v1 1/1] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms
  2025-12-30 15:17 ` [PATCH v1 1/1] " Anoop, Vijay
@ 2025-12-30 23:36   ` Umesh Nerlige Ramappa
  2026-01-02 16:49     ` Anoop Vijay
  0 siblings, 1 reply; 8+ messages in thread
From: Umesh Nerlige Ramappa @ 2025-12-30 23:36 UTC (permalink / raw)
  To: Anoop, Vijay
  Cc: intel-xe, badal.nilawar, rodrigo.vivi, aravind.iddamsetty,
	riana.tauro, anshuman.gupta, matthew.d.roper, michael.j.ruhl,
	paul.e.luse, mohamed.mansoor.v, kam.nasim

On Tue, Dec 30, 2025 at 07:17:23AM -0800, Anoop, Vijay wrote:
>From: Anoop Vijay <anoop.c.vijay@intel.com>
>
>Add a new system controller (sysctrl) component for Intel Xe3p dGPU platforms.
>
>This component provides the foundational infrastructure for communication
>with the System Controller firmware using MKHI protocol over a mailbox interface.
>
>Key features introduced:
> - Detection and initialization of System Controller interface on Xe3p dGPU platforms
> - Mailbox communication with System Controller firmware
> - Fragmented message transfer for large command payloads
>
>This implementation establishes the base for future System Controller feature
>enablement and firmware command handling.
>
>Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>

Commit message should follow '75 chars per line' format. In general, 
please look at the CI.Hooks and CI.checkpatch warnings/errors and fix 
those.

checkpatch can be run before posting:
https://docs.kernel.org/dev-tools/checkpatch.html

>---
> drivers/gpu/drm/xe/Makefile               |   2 +
> drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h |  44 +++
> drivers/gpu/drm/xe/xe_device.c            |   5 +
> drivers/gpu/drm/xe/xe_device_types.h      |   6 +
> drivers/gpu/drm/xe/xe_pci.c               |   2 +
> drivers/gpu/drm/xe/xe_pci_types.h         |   1 +
> drivers/gpu/drm/xe/xe_sysctrl.c           |  64 ++++
> drivers/gpu/drm/xe/xe_sysctrl.h           |  13 +
> drivers/gpu/drm/xe/xe_sysctrl_mailbox.c   | 438 ++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl_mailbox.h   |  61 +++
> drivers/gpu/drm/xe/xe_sysctrl_types.h     |  25 ++
> 11 files changed, 661 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.c
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.h
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_types.h
>
>diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>index 3315f93a35b2..cd03e4c53127 100644
>--- a/drivers/gpu/drm/xe/Makefile
>+++ b/drivers/gpu/drm/xe/Makefile
>@@ -121,6 +121,8 @@ xe-y += xe_bb.o \
> 	xe_step.o \
> 	xe_survivability_mode.o \
> 	xe_sync.o \
>+	xe_sysctrl.o \
>+	xe_sysctrl_mailbox.o \
> 	xe_tile.o \
> 	xe_tile_sysfs.o \
> 	xe_tlb_inval.o \
>diff --git a/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
>new file mode 100644
>index 000000000000..b31b6e24c18e
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
>@@ -0,0 +1,44 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#ifndef _XE_SYSCTRL_REGS_H_
>+#define _XE_SYSCTRL_REGS_H_
>+
>+#include "xe_regs.h"
>+
>+#define SYSCTRL_BASE_OFFSET		0xDB000
>+#define SYSCTRL_BASE			(SOC_BASE + SYSCTRL_BASE_OFFSET)
>+#define SYSCTRL_MAILBOX_INDEX		0x03
>+#define SC_BAR_LENGTH			0x1000
>+
>+#define SC_MB_CTRL			XE_REG(SYSCTRL_BASE + 0x10)
>+#define   SC_MB_CTRL_RUN_BUSY		REG_BIT(31)
>+#define   SC_MB_CTRL_IRQ		REG_BIT(30)
>+#define   SC_MB_CTRL_RUN_BUSY_OUT	REG_BIT(29)
>+#define   SC_MB_CTRL_PARAM3_MASK	REG_GENMASK(28, 24)
>+#define   SC_MB_CTRL_PARAM2_MASK	REG_GENMASK(23, 16)
>+#define   SC_MB_CTRL_PARAM1_MASK	REG_GENMASK(15, 8)
>+#define   SC_MB_CTRL_COMMAND_MASK	REG_GENMASK(7, 0)
>+
>+#define SC_MB_DATA0			XE_REG(SYSCTRL_BASE + 0x14)
>+#define SC_MB_DATA1			XE_REG(SYSCTRL_BASE + 0x18)
>+#define SC_MB_DATA2			XE_REG(SYSCTRL_BASE + 0x1C)
>+#define SC_MB_DATA3			XE_REG(SYSCTRL_BASE + 0x20)
>+
>+#define MKHI_FRAME_PHASE		REG_BIT(24)
>+#define MKHI_FRAME_CURRENT_MASK		REG_GENMASK(21, 16)
>+#define MKHI_FRAME_TOTAL_MASK		REG_GENMASK(13, 8)
>+#define MKHI_FRAME_COMMAND_MASK		REG_GENMASK(7, 0)
>+
>+#define SC_MB_FRAME_SIZE		16
>+#define SC_MB_MAX_FRAMES		64
>+#define SC_MB_MAX_MESSAGE_SIZE		(SC_MB_FRAME_SIZE * SC_MB_MAX_FRAMES)
>+#define SC_MKHI_COMMAND			5
>+
>+#define SC_MB_DEFAULT_TIMEOUT_MS	500
>+#define SC_MB_RETRY_TIMEOUT_MS		20
>+#define SC_MB_POLL_INTERVAL_US		100
>+
>+#endif /* _XE_SYSCTRL_REGS_H_ */
>diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>index e101d290b2a6..805d48dd954d 100644
>--- a/drivers/gpu/drm/xe/xe_device.c
>+++ b/drivers/gpu/drm/xe/xe_device.c
>@@ -66,6 +66,7 @@
> #include "xe_survivability_mode.h"
> #include "xe_sriov.h"
> #include "xe_svm.h"
>+#include "xe_sysctrl.h"
> #include "xe_tile.h"
> #include "xe_ttm_stolen_mgr.h"
> #include "xe_ttm_sys_mgr.h"
>@@ -1032,6 +1033,10 @@ int xe_device_probe(struct xe_device *xe)
> 	if (err)
> 		goto err_unregister_display;
>
>+	err = xe_sysctrl_init(xe);
>+	if (err)
>+		goto err_unregister_display;
>+
> 	err = xe_device_sysfs_init(xe);
> 	if (err)
> 		goto err_unregister_display;
>diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>index a85be9ba175e..6295b2c35d4a 100644
>--- a/drivers/gpu/drm/xe/xe_device_types.h
>+++ b/drivers/gpu/drm/xe/xe_device_types.h
>@@ -29,6 +29,7 @@
> #include "xe_sriov_vf_ccs_types.h"
> #include "xe_step_types.h"
> #include "xe_survivability_mode_types.h"
>+#include "xe_sysctrl_types.h"
> #include "xe_tile_sriov_vf_types.h"
> #include "xe_validation.h"
>
>@@ -340,6 +341,8 @@ struct xe_device {
> 		u8 has_soc_remapper_telem:1;
> 		/** @info.has_sriov: Supports SR-IOV */
> 		u8 has_sriov:1;
>+		/** @info.has_sysctrl: Supports System Controller */
>+		u8 has_sysctrl:1;
> 		/** @info.has_usm: Device has unified shared memory support */
> 		u8 has_usm:1;
> 		/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
>@@ -606,6 +609,9 @@ struct xe_device {
> 	/** @heci_gsc: graphics security controller */
> 	struct xe_heci_gsc heci_gsc;
>
>+	/** @sc: System Controller */
>+	struct xe_sysctrl sc;
>+
> 	/** @nvm: discrete graphics non-volatile memory */
> 	struct intel_dg_nvm_dev *nvm;
>
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index 91e0553a8163..b6dc3030b673 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -426,6 +426,7 @@ static const struct xe_device_desc cri_desc = {
> 	.has_soc_remapper_sysctrl = true,
> 	.has_soc_remapper_telem = true,
> 	.has_sriov = true,
>+	.has_sysctrl = true,
> 	.max_gt_per_tile = 2,
> 	.require_force_probe = true,
> 	.va_bits = 57,
>@@ -701,6 +702,7 @@ static int xe_info_init_early(struct xe_device *xe,
> 	xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
> 	xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
> 		desc->has_sriov;
>+	xe->info.has_sysctrl = desc->has_sysctrl;
> 	xe->info.has_mem_copy_instr = desc->has_mem_copy_instr;
> 	xe->info.skip_guc_pc = desc->skip_guc_pc;
> 	xe->info.skip_mtcfg = desc->skip_mtcfg;
>diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
>index 5f20f56571d1..53e44a32883d 100644
>--- a/drivers/gpu/drm/xe/xe_pci_types.h
>+++ b/drivers/gpu/drm/xe/xe_pci_types.h
>@@ -56,6 +56,7 @@ struct xe_device_desc {
> 	u8 has_soc_remapper_sysctrl:1;
> 	u8 has_soc_remapper_telem:1;
> 	u8 has_sriov:1;
>+	u8 has_sysctrl:1;
> 	u8 needs_scratch:1;
> 	u8 skip_guc_pc:1;
> 	u8 skip_mtcfg:1;
>diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
>new file mode 100644
>index 000000000000..9f3e0b1db380
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
>@@ -0,0 +1,64 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#include "xe_sysctrl.h"

The above header should just be placed in alphabetical order below.

>+
>+#include <linux/device.h>
>+#include <linux/mutex.h>
>+
>+#include <drm/drm_managed.h>
>+
>+#include "regs/xe_sysctrl_regs.h"
>+#include "xe_device.h"
>+#include "xe_printk.h"
>+#include "xe_soc_remapper.h"
>+#include "xe_sysctrl_mailbox.h"
>+#include "xe_sysctrl_types.h"
>+
>+static void xe_sysctrl_fini(void *arg)
>+{
>+	struct xe_sysctrl *sc = arg;
>+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);

You could use a helper and replace it everywhere with sc_to_xe(sc):

static struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
{
	return container_of(sc, struct xe_device, sc);
}

>+
>+	if (!xe->soc_remapper.set_sysctrl_region)
>+		return;
>+
>+	xe->soc_remapper.set_sysctrl_region(xe, 0);
>+}
>+
>+/**
>+ * xe_sysctrl_init - Initialize SC subsystem
>+ * @xe: xe device instance
>+ *
>+ * Entry point for SC initialization, called from xe_device_probe().
>+ * This function checks platform support and initializes the system controller.
>+ *
>+ * Return: 0 on success, error code on failure
>+ */
>+int xe_sysctrl_init(struct xe_device *xe)
>+{
>+	struct xe_sysctrl *sc = &xe->sc;
>+	int ret;
>+
>+	if (!xe->info.has_sysctrl)
>+		return 0;
>+
>+	ret = devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, sc);
>+	if (ret)
>+		return ret;
>+
>+	if (!xe->soc_remapper.set_sysctrl_region)
>+		return -ENODEV;
>+
>+	xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
>+
>+	ret = drmm_mutex_init(&xe->drm, &sc->cmd_lock);
>+	if (ret)
>+		return ret;
>+
>+	xe_sysctrl_mailbox_init(sc);
>+
>+	return 0;
>+}
>diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
>new file mode 100644
>index 000000000000..f1ad12656e48
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
>@@ -0,0 +1,13 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#ifndef _XE_SYSCTRL_H_
>+#define _XE_SYSCTRL_H_
>+
>+struct xe_device;
>+
>+int xe_sysctrl_init(struct xe_device *xe);
>+
>+#endif /* _XE_SYSCTRL_H_ */
>diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
>new file mode 100644
>index 000000000000..e9f4d4b13bb1
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
>@@ -0,0 +1,438 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#include <linux/bitfield.h>
>+#include <linux/errno.h>
>+#include <linux/minmax.h>
>+#include <linux/mutex.h>
>+#include <linux/slab.h>
>+#include <linux/string.h>
>+#include <linux/types.h>
>+
>+#include <drm/drm_print.h>

Do you still need this one? Can you also double check if all headers 
here are needed.

>+
>+#include "xe_device.h"
>+#include "xe_mmio.h"
>+#include "xe_pm.h"
>+#include "xe_printk.h"
>+#include "xe_sysctrl.h"
>+#include "xe_sysctrl_mailbox.h"
>+#include "xe_sysctrl_types.h"
>+#include "regs/xe_sysctrl_regs.h"
>+
>+static bool xe_sysctrl_mailbox_wait_bit_clear(struct xe_sysctrl *sc, u32 bit_mask,
>+					      unsigned int timeout_ms)
>+{
>+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>+	int ret;
>+
>+	ret = xe_mmio_wait32_not(xe_root_tile_mmio(xe), SC_MB_CTRL, bit_mask, bit_mask,
>+				 timeout_ms * 1000, NULL, false);
>+
>+	return ret == 0;
>+}
>+
>+static bool xe_sysctrl_mailbox_wait_bit_set(struct xe_sysctrl *sc, u32 bit_mask,
>+					    unsigned int timeout_ms)
>+{
>+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>+	int ret;
>+
>+	ret = xe_mmio_wait32(xe_root_tile_mmio(xe), SC_MB_CTRL, bit_mask, bit_mask,
>+			     timeout_ms * 1000, NULL, false);
>+
>+	return ret == 0;
>+}
>+
>+static int xe_sysctrl_mailbox_write_frame(struct xe_sysctrl *sc, const void *frame,
>+					  size_t len)
>+{
>+	static const struct xe_reg data_regs[] = {
>+		SC_MB_DATA0, SC_MB_DATA1, SC_MB_DATA2, SC_MB_DATA3
>+	};
>+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>+	const u8 *bytes = frame;
>+	u32 reg_data;
>+	size_t i;
>+
>+	if (len == 0 || len > SC_MB_FRAME_SIZE) {
>+		xe_err(xe, "sysctrl: Invalid frame len: %zu\n", len);
>+		return -EINVAL;
>+	}

This check seems redundant. You are already rounding up cmd_size to 
frames and then the frame size passed to this function can only be up to 
SC_MB_FRAME_SIZE, but not zero. If this function were called from 
outside this file, then additional checks makes sense, but it's static, 
so this check can be dropped.

>+
>+	for (i = 0; i + sizeof(u32) <= len; i += sizeof(u32)) {
>+		reg_data = *(const u32 *)(bytes + i);
>+		xe_mmio_write32(xe_root_tile_mmio(xe), data_regs[i / sizeof(u32)], reg_data);
>+	}
>+
>+	if (i < len) {
>+		size_t remaining = len - i;
>+		size_t j;
>+
>+		reg_data = 0;
>+		for (j = 0; j < remaining; j++)
>+			reg_data |= (u32)bytes[i + j] << (j * 8);
>+
>+		xe_mmio_write32(xe_root_tile_mmio(xe), data_regs[i / sizeof(u32)], reg_data);
>+	}

I would suggest to simplify the logic here to make it more readable, something
like:

static const struct xe_reg regs[] = {
	SC_MB_DATA0, SC_MB_DATA1, SC_MB_DATA2, SC_MB_DATA3
};
struct xe_device *xe = container_of(sc, typeof(*xe), sc);
struct xe_mmio *mmio = xe_root_tile_mmio(xe);
u32 dw = DIV_ROUND_UP(len, sizeof(u32));
u32 val[SC_MB_FRAME_SIZE/4] = {0}, i;

memcpy(val, frame, len);
for (i = 0; i < dw; i++)
	xe_mmio_write32(mmio, regs[i], val[i]);

return 0;

>+
>+	return 0;
>+}
>+
>+static int xe_sysctrl_mailbox_read_frame(struct xe_sysctrl *sc, void *frame,
>+					 size_t len)
>+{
>+	static const struct xe_reg data_regs[] = {
>+		SC_MB_DATA0, SC_MB_DATA1, SC_MB_DATA2, SC_MB_DATA3
>+	};
>+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>+	u8 *bytes = frame;
>+	u32 reg_data;
>+	size_t i;
>+
>+	if (len == 0 || len > SC_MB_FRAME_SIZE) {
>+		xe_err(xe, "sysctrl: Invalid frame len: %zu\n", len);
>+		return -EINVAL;
>+	}
>+
>+	for (i = 0; i + sizeof(u32) <= len; i += sizeof(u32)) {
>+		reg_data = xe_mmio_read32(xe_root_tile_mmio(xe), data_regs[i / sizeof(u32)]);
>+		*(u32 *)(bytes + i) = reg_data;
>+	}
>+
>+	if (i < len) {
>+		size_t remaining = len - i;
>+		size_t j;
>+
>+		reg_data = xe_mmio_read32(xe_root_tile_mmio(xe), data_regs[i / sizeof(u32)]);
>+
>+		for (j = 0; j < remaining; j++)
>+			bytes[i + j] = (reg_data >> (j * 8)) & 0xFF;
>+	}

A logic similar to the write frame can likely be used to simplify this function.

static const struct xe_reg regs[] = {
	SC_MB_DATA0, SC_MB_DATA1, SC_MB_DATA2, SC_MB_DATA3
};
struct xe_device *xe = container_of(sc, typeof(*xe), sc);
struct xe_mmio *mmio = xe_root_tile_mmio(xe);
u32 dw = DIV_ROUND_UP(len, sizeof(u32));
u32 val[SC_MB_FRAME_SIZE/4] = {0}, i;

for (i = 0; i < dw; i++)
	val[i] = xe_mmio_read32(mmio, regs[i]);

memcpy(frame, val, len);

return 0;
>+
>+	return 0;
>+}
>+
>+static void xe_sysctrl_mailbox_clear_response(struct xe_sysctrl *sc)
>+{
>+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>+	u32 ctrl_reg;
>+
>+	ctrl_reg = xe_mmio_read32(xe_root_tile_mmio(xe), SC_MB_CTRL);
>+	ctrl_reg &= ~SC_MB_CTRL_RUN_BUSY_OUT;
>+	xe_mmio_write32(xe_root_tile_mmio(xe), SC_MB_CTRL, ctrl_reg);

You could use xe_mmio_rmw32() instead.

>+}
>+
>+static int xe_sysctrl_mailbox_prepare_command(struct xe_sysctrl *sc,
>+					      u8 group_id, u8 command,
>+					       const void *data_in, size_t data_in_len,
>+					       u8 **cmd_buffer, size_t *cmd_size)
>+{

In the caller cmd_buffer has a different type and here it is u8**. For 
readability, I would recommend using a different name here, maybe 
mkhi_msg.

>+	struct xe_sysctrl_mailbox_mkhi_msg_hdr *mkhi_hdr;
>+	size_t size;
>+	u8 *buffer;
>+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);

I would move the xe initialization to the top.

>+
>+	size = sizeof(*mkhi_hdr) + data_in_len;
>+	if (size > SC_MB_MAX_MESSAGE_SIZE) {
>+		xe_err(xe, "sysctrl: Message too large: %zu bytes\n", size);
>+		return -EINVAL;
>+	}
>+
>+	buffer = kmalloc(size, GFP_KERNEL);
>+	if (!buffer)
>+		return -ENOMEM;
>+
>+	mkhi_hdr = (struct xe_sysctrl_mailbox_mkhi_msg_hdr *)buffer;
>+	mkhi_hdr->data = cpu_to_le32(FIELD_PREP(MKHI_HDR_GROUP_ID_MASK, group_id) |
>+				      FIELD_PREP(MKHI_HDR_COMMAND_MASK, command & 0x7F) |
>+				      FIELD_PREP(MKHI_HDR_IS_RESPONSE, 0) |
>+				      FIELD_PREP(MKHI_HDR_RESERVED_MASK, 0) |
>+				      FIELD_PREP(MKHI_HDR_RESULT_MASK, 0));
>+

FIELD_PREPs un-aligned by one space.

>+	if (data_in && data_in_len)
>+		memcpy(buffer + sizeof(*mkhi_hdr), data_in, data_in_len);
>+
>+	*cmd_buffer = buffer;
>+	*cmd_size = size;
>+
>+	return 0;
>+}
>+
>+static int xe_sysctrl_mailbox_send_frames(struct xe_sysctrl *sc, const u8 *cmd_buffer,
>+					  size_t cmd_size, unsigned int timeout_ms)
>+{
>+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>+	u32 ctrl_reg, total_frames, frame;
>+	size_t bytes_sent, frame_size;
>+
>+	total_frames = DIV_ROUND_UP(cmd_size, SC_MB_FRAME_SIZE);
>+
>+	if (!xe_sysctrl_mailbox_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
>+		xe_err(xe, "sysctrl: Mailbox busy\n");
>+		return -EBUSY;
>+	}
>+
>+	sc->phase_bit ^= 1;
>+
Empty line not needed here.
>+	bytes_sent = 0;
>+
>+	for (frame = 0; frame < total_frames; frame++) {
>+		frame_size = min(cmd_size - bytes_sent, (size_t)SC_MB_FRAME_SIZE);
>+
>+		if (xe_sysctrl_mailbox_write_frame(sc, cmd_buffer + bytes_sent, frame_size)) {
>+			xe_err(xe, "sysctrl: Failed to write frame %u\n", frame);
>+			return -EIO;

If you failed to write the frame here, what happens to phase bit. Should 
you toggle it back?

>+		}
>+
>+		ctrl_reg = SC_MB_CTRL_RUN_BUSY |
>+			   FIELD_PREP(MKHI_FRAME_CURRENT_MASK, frame) |
>+			   FIELD_PREP(MKHI_FRAME_TOTAL_MASK, total_frames - 1) |
>+			   FIELD_PREP(MKHI_FRAME_COMMAND_MASK, SC_MKHI_COMMAND) |
>+			   (sc->phase_bit ? MKHI_FRAME_PHASE : 0);
>+
>+		xe_mmio_write32(xe_root_tile_mmio(xe), SC_MB_CTRL, ctrl_reg);
>+
>+		if (!xe_sysctrl_mailbox_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
>+			xe_err(xe, "sysctrl: Frame %u acknowledgment timeout\n", frame);
>+			return -ETIMEDOUT;
>+		}
>+
>+		bytes_sent += frame_size;
>+	}
>+
>+	return 0;
>+}
>+
>+static int xe_sysctrl_mailbox_process_first_frame(struct xe_sysctrl *sc,
>+						  const struct xe_sysctrl_mailbox_mkhi_msg_hdr *req_hdr,
>+						  void *out,
>+						  size_t frame_size,
>+						  size_t *payload_bytes)
>+{
>+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>+	u32 frame_data[4];
>+	struct xe_sysctrl_mailbox_mkhi_msg_hdr *resp_hdr;
>+	size_t hdr_size = sizeof(*resp_hdr);
>+	size_t payload_size;
>+	int ret;
>+
>+	ret = xe_sysctrl_mailbox_read_frame(sc, frame_data, frame_size);
>+	if (ret)
>+		return ret;
>+
>+	resp_hdr = (struct xe_sysctrl_mailbox_mkhi_msg_hdr *)frame_data;
>+
>+	if (!XE_SYSCTRL_MKHI_HDR_IS_RESPONSE(resp_hdr) ||
>+	    XE_SYSCTRL_MKHI_HDR_GROUP_ID(resp_hdr) != XE_SYSCTRL_MKHI_HDR_GROUP_ID(req_hdr) ||
>+	    XE_SYSCTRL_MKHI_HDR_COMMAND(resp_hdr) != XE_SYSCTRL_MKHI_HDR_COMMAND(req_hdr)) {
>+		xe_err(xe, "SC: Response header mismatch\n");
>+		return -EPROTO;
>+	}
>+
>+	if (XE_SYSCTRL_MKHI_HDR_RESULT(resp_hdr) != 0) {
>+		xe_err(xe, "SC: Firmware error: 0x%02lx\n",
>+		       XE_SYSCTRL_MKHI_HDR_RESULT(resp_hdr));
>+		return -EIO;
>+	}
>+
>+	payload_size = frame_size - hdr_size;
>+	if (payload_size > 0)
>+		memcpy(out, (u8 *)frame_data + hdr_size, payload_size);
>+
>+	*payload_bytes = payload_size;
>+
>+	xe_sysctrl_mailbox_clear_response(sc);
>+
>+	return 0;
>+}
>+
>+static int xe_sysctrl_mailbox_process_frame(struct xe_sysctrl *sc,
>+					    void *out, size_t frame_size,
>+					     unsigned int timeout_ms)
>+{
>+	int ret;
>+
>+	if (!xe_sysctrl_mailbox_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms))

response frame timedout message must be here.

>+		return -ETIMEDOUT;
>+
>+	ret = xe_sysctrl_mailbox_read_frame(sc, out, frame_size);
>+	if (ret)
>+		return ret;
>+
>+	xe_sysctrl_mailbox_clear_response(sc);
>+
>+	return 0;
>+}
>+
>+static int xe_sysctrl_mailbox_receive_frames(struct xe_sysctrl *sc,
>+					     const struct xe_sysctrl_mailbox_mkhi_msg_hdr *req_hdr,
>+					      void *data_out, size_t data_out_len,
>+					      size_t *rdata_len, unsigned int timeout_ms)
>+{
>+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>+	struct xe_sysctrl_mailbox_mkhi_msg_hdr *mkhi_hdr;
>+	u32 ctrl_reg, total_frames, frame;
>+	size_t hdr_size = sizeof(*mkhi_hdr);
>+	u8 *out = data_out;
>+	size_t received = 0;
>+	size_t frame_size;
>+	int ret;

int ret = 0;

>+
>+	if (!xe_sysctrl_mailbox_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
>+		xe_err(xe, "sysctrl: Response frame 0 timeout\n");
>+		return -ETIMEDOUT;
>+	}
>+
>+	ctrl_reg = xe_mmio_read32(xe_root_tile_mmio(xe), SC_MB_CTRL);
>+	total_frames = FIELD_GET(MKHI_FRAME_TOTAL_MASK, ctrl_reg) + 1;
>+
>+	if (total_frames == 1)
>+		frame_size = min(hdr_size + data_out_len, (size_t)SC_MB_FRAME_SIZE);
>+	else
>+		frame_size = SC_MB_FRAME_SIZE;
>+
>+	ret = xe_sysctrl_mailbox_process_first_frame(sc, req_hdr, out, frame_size, &received);
>+	if (ret)
>+		return ret;
>+
>+	out += received;
>+
>+	for (frame = 1; frame < total_frames; frame++) {
>+		size_t remaining = data_out_len - received;
>+
>+		frame_size = min_t(size_t, remaining, SC_MB_FRAME_SIZE);
>+
>+		ret = xe_sysctrl_mailbox_process_frame(sc, out, frame_size, timeout_ms);
>+		if (ret) {
>+			xe_err(xe, "sysctrl: Response frame %u timeout\n", frame);

this message should be in xe_sysctrl_mailbox_process_frame.

At this point you have already copied some data into the out pointer, so 
you might as well update *rdata_len with the partial copied data. So you 
can break here and return ret at the end of the function.

>+			return ret;
>+		}
>+
>+		received += frame_size;
>+		out += frame_size;
>+	}
>+
>+	*rdata_len = received;
>+
>+	return 0;

return ret;

>+}
>+
>+static int xe_sysctrl_mailbox_send_command(struct xe_sysctrl *sc,
>+					   const u8 *cmd_buffer, size_t cmd_size,
>+					    void *data_out, size_t data_out_len,
>+					    size_t *rdata_len, unsigned int timeout_ms)
>+{
>+	const struct xe_sysctrl_mailbox_mkhi_msg_hdr *mkhi_hdr;
>+	size_t received;
>+	int ret;
>+
>+	ret = xe_sysctrl_mailbox_send_frames(sc, cmd_buffer, cmd_size, timeout_ms);
>+	if (ret)
>+		return ret;
>+
>+	if (!data_out) {
>+		if (rdata_len)
>+			*rdata_len = 0;
>+		return 0;
>+	}

The above check should just be

	if (!data_out || !rdata_len)
		return 0;

I would recommend writing to *rdata_len only on successful receive.

>+
>+	mkhi_hdr = (const struct xe_sysctrl_mailbox_mkhi_msg_hdr *)cmd_buffer;
>+
>+	ret = xe_sysctrl_mailbox_receive_frames(sc, mkhi_hdr, data_out, data_out_len,
>+						&received, timeout_ms);
>+	if (ret)
>+		return ret;
>+
>+	if (rdata_len)
>+		*rdata_len = received;

If you added the above comment, then at this point you already know rdata_len
is valid, so the check can be dropped.

>+
>+	return 0;
>+}
>+
>+/**
>+ * xe_sysctrl_send_command - Send command to System Controller via mailbox
>+ * @handle: XE device handle
>+ * @cmd_buffer: Pointer to xe_sysctrl_mailbox_command structure
>+ * @rdata_len: Pointer to store actual response data size (can be NULL)
>+ *
>+ * Send a command to the System Controller using MKHI protocol. Handles
>+ * command preparation, fragmentation, transmission, and response reception.
>+ *
>+ * Return: 0 on success, negative error code on failure
>+ */
>+int xe_sysctrl_send_command(void *handle, void *cmd_buffer, size_t *rdata_len)
>+{

Why void *cmd_buffer? Do you expect anything other than 
xe_sysctrl_mailbox_command? If you do, your function signature will 
change anyways, so why not just define it as struct 
xe_sysctrl_mailbox_command *cmd?

>+	struct xe_device *xe = handle;
>+	struct xe_sysctrl *sc = &xe->sc;
>+	struct xe_sysctrl_mailbox_command *cmd = cmd_buffer;
>+	u8 *buffer = NULL;
>+	size_t command_size = 0;
>+	u8 group_id, command_code;
>+	int ret = 0;
>+
>+	if (!xe || !cmd) {

I suggest splitting the 2 checks here into separate if blocks and use 
pr_err or pr_debug if xe is NULL.

>+		if (xe)
>+			xe_err(xe, "sysctrl: Invalid parameters\n");
>+		return -EINVAL;
>+	}
>+
>+	if (!xe->info.has_sysctrl)
>+		return -ENODEV;
>+
>+	group_id = XE_SYSCTRL_APP_HDR_GROUP_ID(&cmd->header);
>+	command_code = XE_SYSCTRL_APP_HDR_COMMAND(&cmd->header);

Would be good to check if the group_id and command_id are valid here.
>+
>+	if (!cmd->data_in && cmd->data_in_len) {
>+		xe_err(xe, "sysctrl: Invalid input parameters\n");
>+		return -EINVAL;
>+	}
>+
>+	if (!cmd->data_out && cmd->data_out_len) {
>+		xe_err(xe, "sysctrl: Invalid output parameters\n");
>+		return -EINVAL;
>+	}
>+
>+	might_sleep();
>+
>+	ret = xe_sysctrl_mailbox_prepare_command(sc, group_id, command_code,
>+						 cmd->data_in, cmd->data_in_len,
>+						 &buffer, &command_size);
>+	if (ret) {
>+		xe_err(xe, "sysctrl: Failed to prepare command: %d\n", ret);
>+		return ret;
>+	}
>+
>+	xe_pm_runtime_get(xe);
>+
>+	guard(mutex)(&sc->cmd_lock);
>+
>+	ret = xe_sysctrl_mailbox_send_command(sc, buffer, command_size,
>+					      cmd->data_out, cmd->data_out_len, rdata_len,
>+					      SC_MB_DEFAULT_TIMEOUT_MS);
>+	if (ret)
>+		xe_err(xe, "sysctrl: Mailbox command failed: %d\n", ret);
>+
>+	xe_pm_runtime_put(xe);

hmm, not sure this ordering is correct. Ideally you want mutex_unlock 
before runtime pm put, but the guard will only make sure unlock happens 
at function return. If using guard, you may want to define a similar 
guard for runtime pm. Maybe that's what Michal was suggesting earlier.

>+
>+	kfree(buffer);
>+
>+	return ret;
>+}
>+
>+/**
>+ * xe_sysctrl_mailbox_init - Initialize the system controller mailbox state
>+ * @sysctrl: System controller structure
>+ */
>+void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc)
>+{
>+	struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>+	u32 ctrl_reg;
>+
>+	ctrl_reg = xe_mmio_read32(xe_root_tile_mmio(xe), SC_MB_CTRL);
>+	sc->phase_bit = (ctrl_reg & MKHI_FRAME_PHASE) ? 1 : 0;
>+
>+	xe_mmio_write32(xe_root_tile_mmio(xe), SC_MB_CTRL, 0);

You could use xe_mmio_rmw32() instead.

>+}
>diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
>new file mode 100644
>index 000000000000..6380d1d68f8f
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
>@@ -0,0 +1,61 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#ifndef __XE_SYSCTRL_MAILBOX_H__
>+#define __XE_SYSCTRL_MAILBOX_H__
>+
>+#include <linux/bitfield.h>
>+#include <linux/types.h>
>+
>+struct xe_sysctrl;
>+
>+#define MKHI_HDR_GROUP_ID_MASK		GENMASK(7, 0)
>+#define MKHI_HDR_COMMAND_MASK		GENMASK(14, 8)
>+#define MKHI_HDR_IS_RESPONSE		BIT(15)
>+#define MKHI_HDR_RESERVED_MASK		GENMASK(23, 16)
>+#define MKHI_HDR_RESULT_MASK		GENMASK(31, 24)

My interpretation was different from reading the spec. More like 
group_id is at bit[31:24] and result at bit[7:0]. Have you confirmed the 
above bitmask?

>+
>+struct xe_sysctrl_mailbox_mkhi_msg_hdr {
>+	__le32 data;
>+} __packed;
>+
>+#define APP_HDR_GROUP_ID_MASK		GENMASK(7, 0)
>+#define APP_HDR_COMMAND_MASK		GENMASK(15, 8)
>+#define APP_HDR_VERSION_MASK		GENMASK(23, 16)
>+#define APP_HDR_RESERVED_MASK		GENMASK(31, 24)
>+
>+struct xe_sysctrl_mailbox_app_msg_hdr {
>+	__le32 data;
>+} __packed;
>+
>+#define XE_SYSCTRL_APP_HDR_GROUP_ID(hdr)	FIELD_GET(APP_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
>+#define XE_SYSCTRL_APP_HDR_COMMAND(hdr)		FIELD_GET(APP_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
>+#define XE_SYSCTRL_APP_HDR_VERSION(hdr)		FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
>+
>+#define XE_SYSCTRL_MKHI_HDR_GROUP_ID(hdr)	FIELD_GET(MKHI_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
>+#define XE_SYSCTRL_MKHI_HDR_COMMAND(hdr)	FIELD_GET(MKHI_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
>+#define XE_SYSCTRL_MKHI_HDR_IS_RESPONSE(hdr)	FIELD_GET(MKHI_HDR_IS_RESPONSE, le32_to_cpu((hdr)->data))
>+#define XE_SYSCTRL_MKHI_HDR_RESULT(hdr)		FIELD_GET(MKHI_HDR_RESULT_MASK, le32_to_cpu((hdr)->data))
>+
>+/**
>+ * struct xe_sysctrl_mailbox_command - System Controller mailbox command structure
>+ */
>+struct xe_sysctrl_mailbox_command {
>+	/** @header: Application message header containing command information */
>+	struct xe_sysctrl_mailbox_app_msg_hdr header;

>+	/** @data_in: Pointer to input payload data (can be NULL if no input data) */
>+	void *data_in;

>+	/** @data_in_len: Size of input payload in bytes (0 if no input data) */
>+	size_t data_in_len;

>+	/** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
>+	void *data_out;

>+	/** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
>+	size_t data_out_len;

Empty lines between members above will help readability.

>+};
>+
>+void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
>+int xe_sysctrl_send_command(void *handle, void *cmd_buffer, size_t *rdata_len);
>+
>+#endif /* __XE_SYSCTRL_MAILBOX_H__ */
>diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
>new file mode 100644
>index 000000000000..80e674cfa385
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
>@@ -0,0 +1,25 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#ifndef _XE_SYSCTRL_TYPES_H_
>+#define _XE_SYSCTRL_TYPES_H_
>+
>+#include <linux/completion.h>
>+#include <linux/mutex.h>
>+#include <linux/types.h>
>+#include <linux/workqueue.h>

Use only what's needed in this header. If you C file requires some of 
these headers, you want to move those to the C file.

Regards,
Umesh

>+
>+/**
>+ * struct xe_sysctrl - System Controller driver context
>+ */
>+struct xe_sysctrl {
>+	/** @cmd_lock: Mutex protecting mailbox command operations */
>+	struct mutex cmd_lock;
>+
>+	/** @phase_bit: MKHI message boundary phase toggle bit */
>+	u32 phase_bit;
>+};
>+
>+#endif /* _XE_SYSCTRL_TYPES_H_ */
>-- 
>2.43.0
>

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v1 1/1] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms
  2025-12-30 23:36   ` Umesh Nerlige Ramappa
@ 2026-01-02 16:49     ` Anoop Vijay
  0 siblings, 0 replies; 8+ messages in thread
From: Anoop Vijay @ 2026-01-02 16:49 UTC (permalink / raw)
  To: Umesh Nerlige Ramappa
  Cc: intel-xe, badal.nilawar, rodrigo.vivi, aravind.iddamsetty,
	riana.tauro, anshuman.gupta, matthew.d.roper, michael.j.ruhl,
	paul.e.luse, mohamed.mansoor.v, kam.nasim



On 12/31/2025 5:06 AM, Umesh Nerlige Ramappa wrote:
> On Tue, Dec 30, 2025 at 07:17:23AM -0800, Anoop, Vijay wrote:
>> From: Anoop Vijay <anoop.c.vijay@intel.com>
>>
>> Add a new system controller (sysctrl) component for Intel Xe3p dGPU 
>> platforms.
>>
>> This component provides the foundational infrastructure for communication
>> with the System Controller firmware using MKHI protocol over a mailbox 
>> interface.
>>
>> Key features introduced:
>> - Detection and initialization of System Controller interface on Xe3p 
>> dGPU platforms
>> - Mailbox communication with System Controller firmware
>> - Fragmented message transfer for large command payloads
>>
>> This implementation establishes the base for future System Controller 
>> feature
>> enablement and firmware command handling.
>>
>> Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
> 
> Commit message should follow '75 chars per line' format. In general, 
> please look at the CI.Hooks and CI.checkpatch warnings/errors and fix 
> those.
> 
> checkpatch can be run before posting:
> https://docs.kernel.org/dev-tools/checkpatch.html
> 
>> ---
>> drivers/gpu/drm/xe/Makefile               |   2 +
>> drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h |  44 +++
>> drivers/gpu/drm/xe/xe_device.c            |   5 +
>> drivers/gpu/drm/xe/xe_device_types.h      |   6 +
>> drivers/gpu/drm/xe/xe_pci.c               |   2 +
>> drivers/gpu/drm/xe/xe_pci_types.h         |   1 +
>> drivers/gpu/drm/xe/xe_sysctrl.c           |  64 ++++
>> drivers/gpu/drm/xe/xe_sysctrl.h           |  13 +
>> drivers/gpu/drm/xe/xe_sysctrl_mailbox.c   | 438 ++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_sysctrl_mailbox.h   |  61 +++
>> drivers/gpu/drm/xe/xe_sysctrl_types.h     |  25 ++
>> 11 files changed, 661 insertions(+)
>> create mode 100644 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
>> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.c
>> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.h
>> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
>> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
>> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_types.h
>>
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index 3315f93a35b2..cd03e4c53127 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -121,6 +121,8 @@ xe-y += xe_bb.o \
>>     xe_step.o \
>>     xe_survivability_mode.o \
>>     xe_sync.o \
>> +    xe_sysctrl.o \
>> +    xe_sysctrl_mailbox.o \
>>     xe_tile.o \
>>     xe_tile_sysfs.o \
>>     xe_tlb_inval.o \
>> diff --git a/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h b/drivers/gpu/ 
>> drm/xe/regs/xe_sysctrl_regs.h
>> new file mode 100644
>> index 000000000000..b31b6e24c18e
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
>> @@ -0,0 +1,44 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2025 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_SYSCTRL_REGS_H_
>> +#define _XE_SYSCTRL_REGS_H_
>> +
>> +#include "xe_regs.h"
>> +
>> +#define SYSCTRL_BASE_OFFSET        0xDB000
>> +#define SYSCTRL_BASE            (SOC_BASE + SYSCTRL_BASE_OFFSET)
>> +#define SYSCTRL_MAILBOX_INDEX        0x03
>> +#define SC_BAR_LENGTH            0x1000
>> +
>> +#define SC_MB_CTRL            XE_REG(SYSCTRL_BASE + 0x10)
>> +#define   SC_MB_CTRL_RUN_BUSY        REG_BIT(31)
>> +#define   SC_MB_CTRL_IRQ        REG_BIT(30)
>> +#define   SC_MB_CTRL_RUN_BUSY_OUT    REG_BIT(29)
>> +#define   SC_MB_CTRL_PARAM3_MASK    REG_GENMASK(28, 24)
>> +#define   SC_MB_CTRL_PARAM2_MASK    REG_GENMASK(23, 16)
>> +#define   SC_MB_CTRL_PARAM1_MASK    REG_GENMASK(15, 8)
>> +#define   SC_MB_CTRL_COMMAND_MASK    REG_GENMASK(7, 0)
>> +
>> +#define SC_MB_DATA0            XE_REG(SYSCTRL_BASE + 0x14)
>> +#define SC_MB_DATA1            XE_REG(SYSCTRL_BASE + 0x18)
>> +#define SC_MB_DATA2            XE_REG(SYSCTRL_BASE + 0x1C)
>> +#define SC_MB_DATA3            XE_REG(SYSCTRL_BASE + 0x20)
>> +
>> +#define MKHI_FRAME_PHASE        REG_BIT(24)
>> +#define MKHI_FRAME_CURRENT_MASK        REG_GENMASK(21, 16)
>> +#define MKHI_FRAME_TOTAL_MASK        REG_GENMASK(13, 8)
>> +#define MKHI_FRAME_COMMAND_MASK        REG_GENMASK(7, 0)
>> +
>> +#define SC_MB_FRAME_SIZE        16
>> +#define SC_MB_MAX_FRAMES        64
>> +#define SC_MB_MAX_MESSAGE_SIZE        (SC_MB_FRAME_SIZE * 
>> SC_MB_MAX_FRAMES)
>> +#define SC_MKHI_COMMAND            5
>> +
>> +#define SC_MB_DEFAULT_TIMEOUT_MS    500
>> +#define SC_MB_RETRY_TIMEOUT_MS        20
>> +#define SC_MB_POLL_INTERVAL_US        100
>> +
>> +#endif /* _XE_SYSCTRL_REGS_H_ */
>> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/ 
>> xe_device.c
>> index e101d290b2a6..805d48dd954d 100644
>> --- a/drivers/gpu/drm/xe/xe_device.c
>> +++ b/drivers/gpu/drm/xe/xe_device.c
>> @@ -66,6 +66,7 @@
>> #include "xe_survivability_mode.h"
>> #include "xe_sriov.h"
>> #include "xe_svm.h"
>> +#include "xe_sysctrl.h"
>> #include "xe_tile.h"
>> #include "xe_ttm_stolen_mgr.h"
>> #include "xe_ttm_sys_mgr.h"
>> @@ -1032,6 +1033,10 @@ int xe_device_probe(struct xe_device *xe)
>>     if (err)
>>         goto err_unregister_display;
>>
>> +    err = xe_sysctrl_init(xe);
>> +    if (err)
>> +        goto err_unregister_display;
>> +
>>     err = xe_device_sysfs_init(xe);
>>     if (err)
>>         goto err_unregister_display;
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/ 
>> xe/xe_device_types.h
>> index a85be9ba175e..6295b2c35d4a 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -29,6 +29,7 @@
>> #include "xe_sriov_vf_ccs_types.h"
>> #include "xe_step_types.h"
>> #include "xe_survivability_mode_types.h"
>> +#include "xe_sysctrl_types.h"
>> #include "xe_tile_sriov_vf_types.h"
>> #include "xe_validation.h"
>>
>> @@ -340,6 +341,8 @@ struct xe_device {
>>         u8 has_soc_remapper_telem:1;
>>         /** @info.has_sriov: Supports SR-IOV */
>>         u8 has_sriov:1;
>> +        /** @info.has_sysctrl: Supports System Controller */
>> +        u8 has_sysctrl:1;
>>         /** @info.has_usm: Device has unified shared memory support */
>>         u8 has_usm:1;
>>         /** @info.has_64bit_timestamp: Device supports 64-bit 
>> timestamps */
>> @@ -606,6 +609,9 @@ struct xe_device {
>>     /** @heci_gsc: graphics security controller */
>>     struct xe_heci_gsc heci_gsc;
>>
>> +    /** @sc: System Controller */
>> +    struct xe_sysctrl sc;
>> +
>>     /** @nvm: discrete graphics non-volatile memory */
>>     struct intel_dg_nvm_dev *nvm;
>>
>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> index 91e0553a8163..b6dc3030b673 100644
>> --- a/drivers/gpu/drm/xe/xe_pci.c
>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>> @@ -426,6 +426,7 @@ static const struct xe_device_desc cri_desc = {
>>     .has_soc_remapper_sysctrl = true,
>>     .has_soc_remapper_telem = true,
>>     .has_sriov = true,
>> +    .has_sysctrl = true,
>>     .max_gt_per_tile = 2,
>>     .require_force_probe = true,
>>     .va_bits = 57,
>> @@ -701,6 +702,7 @@ static int xe_info_init_early(struct xe_device *xe,
>>     xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
>>     xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe- 
>> >drm.dev)) &&
>>         desc->has_sriov;
>> +    xe->info.has_sysctrl = desc->has_sysctrl;
>>     xe->info.has_mem_copy_instr = desc->has_mem_copy_instr;
>>     xe->info.skip_guc_pc = desc->skip_guc_pc;
>>     xe->info.skip_mtcfg = desc->skip_mtcfg;
>> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/ 
>> xe_pci_types.h
>> index 5f20f56571d1..53e44a32883d 100644
>> --- a/drivers/gpu/drm/xe/xe_pci_types.h
>> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
>> @@ -56,6 +56,7 @@ struct xe_device_desc {
>>     u8 has_soc_remapper_sysctrl:1;
>>     u8 has_soc_remapper_telem:1;
>>     u8 has_sriov:1;
>> +    u8 has_sysctrl:1;
>>     u8 needs_scratch:1;
>>     u8 skip_guc_pc:1;
>>     u8 skip_mtcfg:1;
>> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/ 
>> xe_sysctrl.c
>> new file mode 100644
>> index 000000000000..9f3e0b1db380
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
>> @@ -0,0 +1,64 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2025 Intel Corporation
>> + */
>> +
>> +#include "xe_sysctrl.h"
> 
> The above header should just be placed in alphabetical order below.
> 
>> +
>> +#include <linux/device.h>
>> +#include <linux/mutex.h>
>> +
>> +#include <drm/drm_managed.h>
>> +
>> +#include "regs/xe_sysctrl_regs.h"
>> +#include "xe_device.h"
>> +#include "xe_printk.h"
>> +#include "xe_soc_remapper.h"
>> +#include "xe_sysctrl_mailbox.h"
>> +#include "xe_sysctrl_types.h"
>> +
>> +static void xe_sysctrl_fini(void *arg)
>> +{
>> +    struct xe_sysctrl *sc = arg;
>> +    struct xe_device *xe = container_of(sc, typeof(*xe), sc);
> 
> You could use a helper and replace it everywhere with sc_to_xe(sc):
> 
> static struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
> {
>      return container_of(sc, struct xe_device, sc);
> }
> 
>> +
>> +    if (!xe->soc_remapper.set_sysctrl_region)
>> +        return;
>> +
>> +    xe->soc_remapper.set_sysctrl_region(xe, 0);
>> +}
>> +
>> +/**
>> + * xe_sysctrl_init - Initialize SC subsystem
>> + * @xe: xe device instance
>> + *
>> + * Entry point for SC initialization, called from xe_device_probe().
>> + * This function checks platform support and initializes the system 
>> controller.
>> + *
>> + * Return: 0 on success, error code on failure
>> + */
>> +int xe_sysctrl_init(struct xe_device *xe)
>> +{
>> +    struct xe_sysctrl *sc = &xe->sc;
>> +    int ret;
>> +
>> +    if (!xe->info.has_sysctrl)
>> +        return 0;
>> +
>> +    ret = devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, sc);
>> +    if (ret)
>> +        return ret;
>> +
>> +    if (!xe->soc_remapper.set_sysctrl_region)
>> +        return -ENODEV;
>> +
>> +    xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
>> +
>> +    ret = drmm_mutex_init(&xe->drm, &sc->cmd_lock);
>> +    if (ret)
>> +        return ret;
>> +
>> +    xe_sysctrl_mailbox_init(sc);
>> +
>> +    return 0;
>> +}
>> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/ 
>> xe_sysctrl.h
>> new file mode 100644
>> index 000000000000..f1ad12656e48
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
>> @@ -0,0 +1,13 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2025 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_SYSCTRL_H_
>> +#define _XE_SYSCTRL_H_
>> +
>> +struct xe_device;
>> +
>> +int xe_sysctrl_init(struct xe_device *xe);
>> +
>> +#endif /* _XE_SYSCTRL_H_ */
>> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c b/drivers/gpu/ 
>> drm/xe/xe_sysctrl_mailbox.c
>> new file mode 100644
>> index 000000000000..e9f4d4b13bb1
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
>> @@ -0,0 +1,438 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2025 Intel Corporation
>> + */
>> +
>> +#include <linux/bitfield.h>
>> +#include <linux/errno.h>
>> +#include <linux/minmax.h>
>> +#include <linux/mutex.h>
>> +#include <linux/slab.h>
>> +#include <linux/string.h>
>> +#include <linux/types.h>
>> +
>> +#include <drm/drm_print.h>
> 
> Do you still need this one? Can you also double check if all headers 
> here are needed.
> 
>> +
>> +#include "xe_device.h"
>> +#include "xe_mmio.h"
>> +#include "xe_pm.h"
>> +#include "xe_printk.h"
>> +#include "xe_sysctrl.h"
>> +#include "xe_sysctrl_mailbox.h"
>> +#include "xe_sysctrl_types.h"
>> +#include "regs/xe_sysctrl_regs.h"
>> +
>> +static bool xe_sysctrl_mailbox_wait_bit_clear(struct xe_sysctrl *sc, 
>> u32 bit_mask,
>> +                          unsigned int timeout_ms)
>> +{
>> +    struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>> +    int ret;
>> +
>> +    ret = xe_mmio_wait32_not(xe_root_tile_mmio(xe), SC_MB_CTRL, 
>> bit_mask, bit_mask,
>> +                 timeout_ms * 1000, NULL, false);
>> +
>> +    return ret == 0;
>> +}
>> +
>> +static bool xe_sysctrl_mailbox_wait_bit_set(struct xe_sysctrl *sc, 
>> u32 bit_mask,
>> +                        unsigned int timeout_ms)
>> +{
>> +    struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>> +    int ret;
>> +
>> +    ret = xe_mmio_wait32(xe_root_tile_mmio(xe), SC_MB_CTRL, bit_mask, 
>> bit_mask,
>> +                 timeout_ms * 1000, NULL, false);
>> +
>> +    return ret == 0;
>> +}
>> +
>> +static int xe_sysctrl_mailbox_write_frame(struct xe_sysctrl *sc, 
>> const void *frame,
>> +                      size_t len)
>> +{
>> +    static const struct xe_reg data_regs[] = {
>> +        SC_MB_DATA0, SC_MB_DATA1, SC_MB_DATA2, SC_MB_DATA3
>> +    };
>> +    struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>> +    const u8 *bytes = frame;
>> +    u32 reg_data;
>> +    size_t i;
>> +
>> +    if (len == 0 || len > SC_MB_FRAME_SIZE) {
>> +        xe_err(xe, "sysctrl: Invalid frame len: %zu\n", len);
>> +        return -EINVAL;
>> +    }
> 
> This check seems redundant. You are already rounding up cmd_size to 
> frames and then the frame size passed to this function can only be up to 
> SC_MB_FRAME_SIZE, but not zero. If this function were called from 
> outside this file, then additional checks makes sense, but it's static, 
> so this check can be dropped.
> 
>> +
>> +    for (i = 0; i + sizeof(u32) <= len; i += sizeof(u32)) {
>> +        reg_data = *(const u32 *)(bytes + i);
>> +        xe_mmio_write32(xe_root_tile_mmio(xe), data_regs[i / 
>> sizeof(u32)], reg_data);
>> +    }
>> +
>> +    if (i < len) {
>> +        size_t remaining = len - i;
>> +        size_t j;
>> +
>> +        reg_data = 0;
>> +        for (j = 0; j < remaining; j++)
>> +            reg_data |= (u32)bytes[i + j] << (j * 8);
>> +
>> +        xe_mmio_write32(xe_root_tile_mmio(xe), data_regs[i / 
>> sizeof(u32)], reg_data);
>> +    }
> 
> I would suggest to simplify the logic here to make it more readable, 
> something
> like:
> 
> static const struct xe_reg regs[] = {
>      SC_MB_DATA0, SC_MB_DATA1, SC_MB_DATA2, SC_MB_DATA3
> };
> struct xe_device *xe = container_of(sc, typeof(*xe), sc);
> struct xe_mmio *mmio = xe_root_tile_mmio(xe);
> u32 dw = DIV_ROUND_UP(len, sizeof(u32));
> u32 val[SC_MB_FRAME_SIZE/4] = {0}, i;
> 
> memcpy(val, frame, len);
> for (i = 0; i < dw; i++)
>      xe_mmio_write32(mmio, regs[i], val[i]);
> 
> return 0;
> 
>> +
>> +    return 0;
>> +}
>> +
>> +static int xe_sysctrl_mailbox_read_frame(struct xe_sysctrl *sc, void 
>> *frame,
>> +                     size_t len)
>> +{
>> +    static const struct xe_reg data_regs[] = {
>> +        SC_MB_DATA0, SC_MB_DATA1, SC_MB_DATA2, SC_MB_DATA3
>> +    };
>> +    struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>> +    u8 *bytes = frame;
>> +    u32 reg_data;
>> +    size_t i;
>> +
>> +    if (len == 0 || len > SC_MB_FRAME_SIZE) {
>> +        xe_err(xe, "sysctrl: Invalid frame len: %zu\n", len);
>> +        return -EINVAL;
>> +    }
>> +
>> +    for (i = 0; i + sizeof(u32) <= len; i += sizeof(u32)) {
>> +        reg_data = xe_mmio_read32(xe_root_tile_mmio(xe), 
>> data_regs[i / sizeof(u32)]);
>> +        *(u32 *)(bytes + i) = reg_data;
>> +    }
>> +
>> +    if (i < len) {
>> +        size_t remaining = len - i;
>> +        size_t j;
>> +
>> +        reg_data = xe_mmio_read32(xe_root_tile_mmio(xe), 
>> data_regs[i / sizeof(u32)]);
>> +
>> +        for (j = 0; j < remaining; j++)
>> +            bytes[i + j] = (reg_data >> (j * 8)) & 0xFF;
>> +    }
> 
> A logic similar to the write frame can likely be used to simplify this 
> function.
> 
> static const struct xe_reg regs[] = {
>      SC_MB_DATA0, SC_MB_DATA1, SC_MB_DATA2, SC_MB_DATA3
> };
> struct xe_device *xe = container_of(sc, typeof(*xe), sc);
> struct xe_mmio *mmio = xe_root_tile_mmio(xe);
> u32 dw = DIV_ROUND_UP(len, sizeof(u32));
> u32 val[SC_MB_FRAME_SIZE/4] = {0}, i;
> 
> for (i = 0; i < dw; i++)
>      val[i] = xe_mmio_read32(mmio, regs[i]);
> 
> memcpy(frame, val, len);
> 
> return 0;
>> +
>> +    return 0;
>> +}
>> +
>> +static void xe_sysctrl_mailbox_clear_response(struct xe_sysctrl *sc)
>> +{
>> +    struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>> +    u32 ctrl_reg;
>> +
>> +    ctrl_reg = xe_mmio_read32(xe_root_tile_mmio(xe), SC_MB_CTRL);
>> +    ctrl_reg &= ~SC_MB_CTRL_RUN_BUSY_OUT;
>> +    xe_mmio_write32(xe_root_tile_mmio(xe), SC_MB_CTRL, ctrl_reg);
> 
> You could use xe_mmio_rmw32() instead.
> 
>> +}
>> +
>> +static int xe_sysctrl_mailbox_prepare_command(struct xe_sysctrl *sc,
>> +                          u8 group_id, u8 command,
>> +                           const void *data_in, size_t data_in_len,
>> +                           u8 **cmd_buffer, size_t *cmd_size)
>> +{
> 
> In the caller cmd_buffer has a different type and here it is u8**. For 
> readability, I would recommend using a different name here, maybe mkhi_msg.
> 
>> +    struct xe_sysctrl_mailbox_mkhi_msg_hdr *mkhi_hdr;
>> +    size_t size;
>> +    u8 *buffer;
>> +    struct xe_device *xe = container_of(sc, typeof(*xe), sc);
> 
> I would move the xe initialization to the top.
> 
>> +
>> +    size = sizeof(*mkhi_hdr) + data_in_len;
>> +    if (size > SC_MB_MAX_MESSAGE_SIZE) {
>> +        xe_err(xe, "sysctrl: Message too large: %zu bytes\n", size);
>> +        return -EINVAL;
>> +    }
>> +
>> +    buffer = kmalloc(size, GFP_KERNEL);
>> +    if (!buffer)
>> +        return -ENOMEM;
>> +
>> +    mkhi_hdr = (struct xe_sysctrl_mailbox_mkhi_msg_hdr *)buffer;
>> +    mkhi_hdr->data = cpu_to_le32(FIELD_PREP(MKHI_HDR_GROUP_ID_MASK, 
>> group_id) |
>> +                      FIELD_PREP(MKHI_HDR_COMMAND_MASK, command & 
>> 0x7F) |
>> +                      FIELD_PREP(MKHI_HDR_IS_RESPONSE, 0) |
>> +                      FIELD_PREP(MKHI_HDR_RESERVED_MASK, 0) |
>> +                      FIELD_PREP(MKHI_HDR_RESULT_MASK, 0));
>> +
> 
> FIELD_PREPs un-aligned by one space.
> 
>> +    if (data_in && data_in_len)
>> +        memcpy(buffer + sizeof(*mkhi_hdr), data_in, data_in_len);
>> +
>> +    *cmd_buffer = buffer;
>> +    *cmd_size = size;
>> +
>> +    return 0;
>> +}
>> +
>> +static int xe_sysctrl_mailbox_send_frames(struct xe_sysctrl *sc, 
>> const u8 *cmd_buffer,
>> +                      size_t cmd_size, unsigned int timeout_ms)
>> +{
>> +    struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>> +    u32 ctrl_reg, total_frames, frame;
>> +    size_t bytes_sent, frame_size;
>> +
>> +    total_frames = DIV_ROUND_UP(cmd_size, SC_MB_FRAME_SIZE);
>> +
>> +    if (!xe_sysctrl_mailbox_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, 
>> timeout_ms)) {
>> +        xe_err(xe, "sysctrl: Mailbox busy\n");
>> +        return -EBUSY;
>> +    }
>> +
>> +    sc->phase_bit ^= 1;
>> +
> Empty line not needed here.
>> +    bytes_sent = 0;
>> +
>> +    for (frame = 0; frame < total_frames; frame++) {
>> +        frame_size = min(cmd_size - bytes_sent, 
>> (size_t)SC_MB_FRAME_SIZE);
>> +
>> +        if (xe_sysctrl_mailbox_write_frame(sc, cmd_buffer + 
>> bytes_sent, frame_size)) {
>> +            xe_err(xe, "sysctrl: Failed to write frame %u\n", frame);
>> +            return -EIO;
> 
> If you failed to write the frame here, what happens to phase bit. Should 
> you toggle it back?
> 
>> +        }
>> +
>> +        ctrl_reg = SC_MB_CTRL_RUN_BUSY |
>> +               FIELD_PREP(MKHI_FRAME_CURRENT_MASK, frame) |
>> +               FIELD_PREP(MKHI_FRAME_TOTAL_MASK, total_frames - 1) |
>> +               FIELD_PREP(MKHI_FRAME_COMMAND_MASK, SC_MKHI_COMMAND) |
>> +               (sc->phase_bit ? MKHI_FRAME_PHASE : 0);
>> +
>> +        xe_mmio_write32(xe_root_tile_mmio(xe), SC_MB_CTRL, ctrl_reg);
>> +
>> +        if (!xe_sysctrl_mailbox_wait_bit_clear(sc, 
>> SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
>> +            xe_err(xe, "sysctrl: Frame %u acknowledgment timeout\n", 
>> frame);
>> +            return -ETIMEDOUT;
>> +        }
>> +
>> +        bytes_sent += frame_size;
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>> +static int xe_sysctrl_mailbox_process_first_frame(struct xe_sysctrl *sc,
>> +                          const struct 
>> xe_sysctrl_mailbox_mkhi_msg_hdr *req_hdr,
>> +                          void *out,
>> +                          size_t frame_size,
>> +                          size_t *payload_bytes)
>> +{
>> +    struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>> +    u32 frame_data[4];
>> +    struct xe_sysctrl_mailbox_mkhi_msg_hdr *resp_hdr;
>> +    size_t hdr_size = sizeof(*resp_hdr);
>> +    size_t payload_size;
>> +    int ret;
>> +
>> +    ret = xe_sysctrl_mailbox_read_frame(sc, frame_data, frame_size);
>> +    if (ret)
>> +        return ret;
>> +
>> +    resp_hdr = (struct xe_sysctrl_mailbox_mkhi_msg_hdr *)frame_data;
>> +
>> +    if (!XE_SYSCTRL_MKHI_HDR_IS_RESPONSE(resp_hdr) ||
>> +        XE_SYSCTRL_MKHI_HDR_GROUP_ID(resp_hdr) != 
>> XE_SYSCTRL_MKHI_HDR_GROUP_ID(req_hdr) ||
>> +        XE_SYSCTRL_MKHI_HDR_COMMAND(resp_hdr) != 
>> XE_SYSCTRL_MKHI_HDR_COMMAND(req_hdr)) {
>> +        xe_err(xe, "SC: Response header mismatch\n");
>> +        return -EPROTO;
>> +    }
>> +
>> +    if (XE_SYSCTRL_MKHI_HDR_RESULT(resp_hdr) != 0) {
>> +        xe_err(xe, "SC: Firmware error: 0x%02lx\n",
>> +               XE_SYSCTRL_MKHI_HDR_RESULT(resp_hdr));
>> +        return -EIO;
>> +    }
>> +
>> +    payload_size = frame_size - hdr_size;
>> +    if (payload_size > 0)
>> +        memcpy(out, (u8 *)frame_data + hdr_size, payload_size);
>> +
>> +    *payload_bytes = payload_size;
>> +
>> +    xe_sysctrl_mailbox_clear_response(sc);
>> +
>> +    return 0;
>> +}
>> +
>> +static int xe_sysctrl_mailbox_process_frame(struct xe_sysctrl *sc,
>> +                        void *out, size_t frame_size,
>> +                         unsigned int timeout_ms)
>> +{
>> +    int ret;
>> +
>> +    if (!xe_sysctrl_mailbox_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, 
>> timeout_ms))
> 
> response frame timedout message must be here.
> 
>> +        return -ETIMEDOUT;
>> +
>> +    ret = xe_sysctrl_mailbox_read_frame(sc, out, frame_size);
>> +    if (ret)
>> +        return ret;
>> +
>> +    xe_sysctrl_mailbox_clear_response(sc);
>> +
>> +    return 0;
>> +}
>> +
>> +static int xe_sysctrl_mailbox_receive_frames(struct xe_sysctrl *sc,
>> +                         const struct xe_sysctrl_mailbox_mkhi_msg_hdr 
>> *req_hdr,
>> +                          void *data_out, size_t data_out_len,
>> +                          size_t *rdata_len, unsigned int timeout_ms)
>> +{
>> +    struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>> +    struct xe_sysctrl_mailbox_mkhi_msg_hdr *mkhi_hdr;
>> +    u32 ctrl_reg, total_frames, frame;
>> +    size_t hdr_size = sizeof(*mkhi_hdr);
>> +    u8 *out = data_out;
>> +    size_t received = 0;
>> +    size_t frame_size;
>> +    int ret;
> 
> int ret = 0;
> 
>> +
>> +    if (!xe_sysctrl_mailbox_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, 
>> timeout_ms)) {
>> +        xe_err(xe, "sysctrl: Response frame 0 timeout\n");
>> +        return -ETIMEDOUT;
>> +    }
>> +
>> +    ctrl_reg = xe_mmio_read32(xe_root_tile_mmio(xe), SC_MB_CTRL);
>> +    total_frames = FIELD_GET(MKHI_FRAME_TOTAL_MASK, ctrl_reg) + 1;
>> +
>> +    if (total_frames == 1)
>> +        frame_size = min(hdr_size + data_out_len, 
>> (size_t)SC_MB_FRAME_SIZE);
>> +    else
>> +        frame_size = SC_MB_FRAME_SIZE;
>> +
>> +    ret = xe_sysctrl_mailbox_process_first_frame(sc, req_hdr, out, 
>> frame_size, &received);
>> +    if (ret)
>> +        return ret;
>> +
>> +    out += received;
>> +
>> +    for (frame = 1; frame < total_frames; frame++) {
>> +        size_t remaining = data_out_len - received;
>> +
>> +        frame_size = min_t(size_t, remaining, SC_MB_FRAME_SIZE);
>> +
>> +        ret = xe_sysctrl_mailbox_process_frame(sc, out, frame_size, 
>> timeout_ms);
>> +        if (ret) {
>> +            xe_err(xe, "sysctrl: Response frame %u timeout\n", frame);
> 
> this message should be in xe_sysctrl_mailbox_process_frame.
> 
> At this point you have already copied some data into the out pointer, so 
> you might as well update *rdata_len with the partial copied data. So you 
> can break here and return ret at the end of the function.
> 
>> +            return ret;
>> +        }
>> +
>> +        received += frame_size;
>> +        out += frame_size;
>> +    }
>> +
>> +    *rdata_len = received;
>> +
>> +    return 0;
> 
> return ret;
> 
>> +}
>> +
>> +static int xe_sysctrl_mailbox_send_command(struct xe_sysctrl *sc,
>> +                       const u8 *cmd_buffer, size_t cmd_size,
>> +                        void *data_out, size_t data_out_len,
>> +                        size_t *rdata_len, unsigned int timeout_ms)
>> +{
>> +    const struct xe_sysctrl_mailbox_mkhi_msg_hdr *mkhi_hdr;
>> +    size_t received;
>> +    int ret;
>> +
>> +    ret = xe_sysctrl_mailbox_send_frames(sc, cmd_buffer, cmd_size, 
>> timeout_ms);
>> +    if (ret)
>> +        return ret;
>> +
>> +    if (!data_out) {
>> +        if (rdata_len)
>> +            *rdata_len = 0;
>> +        return 0;
>> +    }
> 
> The above check should just be
> 
>      if (!data_out || !rdata_len)
>          return 0;
> 
> I would recommend writing to *rdata_len only on successful receive.
> 
>> +
>> +    mkhi_hdr = (const struct xe_sysctrl_mailbox_mkhi_msg_hdr 
>> *)cmd_buffer;
>> +
>> +    ret = xe_sysctrl_mailbox_receive_frames(sc, mkhi_hdr, data_out, 
>> data_out_len,
>> +                        &received, timeout_ms);
>> +    if (ret)
>> +        return ret;
>> +
>> +    if (rdata_len)
>> +        *rdata_len = received;
> 
> If you added the above comment, then at this point you already know 
> rdata_len
> is valid, so the check can be dropped.
> 
>> +
>> +    return 0;
>> +}
>> +
>> +/**
>> + * xe_sysctrl_send_command - Send command to System Controller via 
>> mailbox
>> + * @handle: XE device handle
>> + * @cmd_buffer: Pointer to xe_sysctrl_mailbox_command structure
>> + * @rdata_len: Pointer to store actual response data size (can be NULL)
>> + *
>> + * Send a command to the System Controller using MKHI protocol. Handles
>> + * command preparation, fragmentation, transmission, and response 
>> reception.
>> + *
>> + * Return: 0 on success, negative error code on failure
>> + */
>> +int xe_sysctrl_send_command(void *handle, void *cmd_buffer, size_t 
>> *rdata_len)
>> +{
> 
> Why void *cmd_buffer? Do you expect anything other than 
> xe_sysctrl_mailbox_command? If you do, your function signature will 
> change anyways, so why not just define it as struct 
> xe_sysctrl_mailbox_command *cmd?
> 
We used void *cmd_buffer for flexibility and future payload support. If 
a strongly typed API is preferred, we can align with consumer modules 
and update it accordingly.

>> +    struct xe_device *xe = handle;
>> +    struct xe_sysctrl *sc = &xe->sc;
>> +    struct xe_sysctrl_mailbox_command *cmd = cmd_buffer;
>> +    u8 *buffer = NULL;
>> +    size_t command_size = 0;
>> +    u8 group_id, command_code;
>> +    int ret = 0;
>> +
>> +    if (!xe || !cmd) {
> 
> I suggest splitting the 2 checks here into separate if blocks and use 
> pr_err or pr_debug if xe is NULL.
> 
>> +        if (xe)
>> +            xe_err(xe, "sysctrl: Invalid parameters\n");
>> +        return -EINVAL;
>> +    }
>> +
>> +    if (!xe->info.has_sysctrl)
>> +        return -ENODEV;
>> +
>> +    group_id = XE_SYSCTRL_APP_HDR_GROUP_ID(&cmd->header);
>> +    command_code = XE_SYSCTRL_APP_HDR_COMMAND(&cmd->header);
> 
> Would be good to check if the group_id and command_id are valid here.
This function is intended to support multiple groups and commands, so we 
avoid enforcing strict group_id and command_code checks here.

>> +
>> +    if (!cmd->data_in && cmd->data_in_len) {
>> +        xe_err(xe, "sysctrl: Invalid input parameters\n");
>> +        return -EINVAL;
>> +    }
>> +
>> +    if (!cmd->data_out && cmd->data_out_len) {
>> +        xe_err(xe, "sysctrl: Invalid output parameters\n");
>> +        return -EINVAL;
>> +    }
>> +
>> +    might_sleep();
>> +
>> +    ret = xe_sysctrl_mailbox_prepare_command(sc, group_id, command_code,
>> +                         cmd->data_in, cmd->data_in_len,
>> +                         &buffer, &command_size);
>> +    if (ret) {
>> +        xe_err(xe, "sysctrl: Failed to prepare command: %d\n", ret);
>> +        return ret;
>> +    }
>> +
>> +    xe_pm_runtime_get(xe);
>> +
>> +    guard(mutex)(&sc->cmd_lock);
>> +
>> +    ret = xe_sysctrl_mailbox_send_command(sc, buffer, command_size,
>> +                          cmd->data_out, cmd->data_out_len, rdata_len,
>> +                          SC_MB_DEFAULT_TIMEOUT_MS);
>> +    if (ret)
>> +        xe_err(xe, "sysctrl: Mailbox command failed: %d\n", ret);
>> +
>> +    xe_pm_runtime_put(xe);
> 
> hmm, not sure this ordering is correct. Ideally you want mutex_unlock 
> before runtime pm put, but the guard will only make sure unlock happens 
> at function return. If using guard, you may want to define a similar 
> guard for runtime pm. Maybe that's what Michal was suggesting earlier.
> 
>> +
>> +    kfree(buffer);
>> +
>> +    return ret;
>> +}
>> +
>> +/**
>> + * xe_sysctrl_mailbox_init - Initialize the system controller mailbox 
>> state
>> + * @sysctrl: System controller structure
>> + */
>> +void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc)
>> +{
>> +    struct xe_device *xe = container_of(sc, typeof(*xe), sc);
>> +    u32 ctrl_reg;
>> +
>> +    ctrl_reg = xe_mmio_read32(xe_root_tile_mmio(xe), SC_MB_CTRL);
>> +    sc->phase_bit = (ctrl_reg & MKHI_FRAME_PHASE) ? 1 : 0;
>> +
>> +    xe_mmio_write32(xe_root_tile_mmio(xe), SC_MB_CTRL, 0);
> 
> You could use xe_mmio_rmw32() instead.
> 
>> +}
>> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/ 
>> drm/xe/xe_sysctrl_mailbox.h
>> new file mode 100644
>> index 000000000000..6380d1d68f8f
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
>> @@ -0,0 +1,61 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2025 Intel Corporation
>> + */
>> +
>> +#ifndef __XE_SYSCTRL_MAILBOX_H__
>> +#define __XE_SYSCTRL_MAILBOX_H__
>> +
>> +#include <linux/bitfield.h>
>> +#include <linux/types.h>
>> +
>> +struct xe_sysctrl;
>> +
>> +#define MKHI_HDR_GROUP_ID_MASK        GENMASK(7, 0)
>> +#define MKHI_HDR_COMMAND_MASK        GENMASK(14, 8)
>> +#define MKHI_HDR_IS_RESPONSE        BIT(15)
>> +#define MKHI_HDR_RESERVED_MASK        GENMASK(23, 16)
>> +#define MKHI_HDR_RESULT_MASK        GENMASK(31, 24)
> 
> My interpretation was different from reading the spec. More like 
> group_id is at bit[31:24] and result at bit[7:0]. Have you confirmed the 
> above bitmask?
Yes, this bitmask works as expected in loopback testing.

Thanks,
Anoop
> 
>> +
>> +struct xe_sysctrl_mailbox_mkhi_msg_hdr {
>> +    __le32 data;
>> +} __packed;
>> +
>> +#define APP_HDR_GROUP_ID_MASK        GENMASK(7, 0)
>> +#define APP_HDR_COMMAND_MASK        GENMASK(15, 8)
>> +#define APP_HDR_VERSION_MASK        GENMASK(23, 16)
>> +#define APP_HDR_RESERVED_MASK        GENMASK(31, 24)
>> +
>> +struct xe_sysctrl_mailbox_app_msg_hdr {
>> +    __le32 data;
>> +} __packed;
>> +
>> +#define XE_SYSCTRL_APP_HDR_GROUP_ID(hdr)    
>> FIELD_GET(APP_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
>> +#define XE_SYSCTRL_APP_HDR_COMMAND(hdr)        
>> FIELD_GET(APP_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
>> +#define XE_SYSCTRL_APP_HDR_VERSION(hdr)        
>> FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
>> +
>> +#define XE_SYSCTRL_MKHI_HDR_GROUP_ID(hdr)    
>> FIELD_GET(MKHI_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
>> +#define XE_SYSCTRL_MKHI_HDR_COMMAND(hdr)    
>> FIELD_GET(MKHI_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
>> +#define XE_SYSCTRL_MKHI_HDR_IS_RESPONSE(hdr)    
>> FIELD_GET(MKHI_HDR_IS_RESPONSE, le32_to_cpu((hdr)->data))
>> +#define XE_SYSCTRL_MKHI_HDR_RESULT(hdr)        
>> FIELD_GET(MKHI_HDR_RESULT_MASK, le32_to_cpu((hdr)->data))
>> +
>> +/**
>> + * struct xe_sysctrl_mailbox_command - System Controller mailbox 
>> command structure
>> + */
>> +struct xe_sysctrl_mailbox_command {
>> +    /** @header: Application message header containing command 
>> information */
>> +    struct xe_sysctrl_mailbox_app_msg_hdr header;
> 
>> +    /** @data_in: Pointer to input payload data (can be NULL if no 
>> input data) */
>> +    void *data_in;
> 
>> +    /** @data_in_len: Size of input payload in bytes (0 if no input 
>> data) */
>> +    size_t data_in_len;
> 
>> +    /** @data_out: Pointer to output buffer for response data (can be 
>> NULL if no response) */
>> +    void *data_out;
> 
>> +    /** @data_out_len: Size of output buffer in bytes (0 if no 
>> response expected) */
>> +    size_t data_out_len;
> 
> Empty lines between members above will help readability.
> 
>> +};
>> +
>> +void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
>> +int xe_sysctrl_send_command(void *handle, void *cmd_buffer, size_t 
>> *rdata_len);
>> +
>> +#endif /* __XE_SYSCTRL_MAILBOX_H__ */
>> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/ 
>> xe/xe_sysctrl_types.h
>> new file mode 100644
>> index 000000000000..80e674cfa385
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
>> @@ -0,0 +1,25 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2025 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_SYSCTRL_TYPES_H_
>> +#define _XE_SYSCTRL_TYPES_H_
>> +
>> +#include <linux/completion.h>
>> +#include <linux/mutex.h>
>> +#include <linux/types.h>
>> +#include <linux/workqueue.h>
> 
> Use only what's needed in this header. If you C file requires some of 
> these headers, you want to move those to the C file.
> 
> Regards,
> Umesh
> 
>> +
>> +/**
>> + * struct xe_sysctrl - System Controller driver context
>> + */
>> +struct xe_sysctrl {
>> +    /** @cmd_lock: Mutex protecting mailbox command operations */
>> +    struct mutex cmd_lock;
>> +
>> +    /** @phase_bit: MKHI message boundary phase toggle bit */
>> +    u32 phase_bit;
>> +};
>> +
>> +#endif /* _XE_SYSCTRL_TYPES_H_ */
>> -- 
>> 2.43.0
>>


^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2026-01-02 16:49 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-12-30 15:17 [PATCH v1 0/1] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms Anoop, Vijay
2025-12-30 15:17 ` [PATCH v1 1/1] " Anoop, Vijay
2025-12-30 23:36   ` Umesh Nerlige Ramappa
2026-01-02 16:49     ` Anoop Vijay
2025-12-30 15:22 ` ✗ CI.checkpatch: warning for " Patchwork
2025-12-30 15:24 ` ✓ CI.KUnit: success " Patchwork
2025-12-30 15:57 ` ✓ Xe.CI.BAT: " Patchwork
2025-12-30 16:57 ` ✓ Xe.CI.Full: " Patchwork

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