* [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx
@ 2026-02-19 9:43 Arun R Murthy
2026-02-19 10:45 ` ✗ CI.checkpatch: warning for " Patchwork
` (10 more replies)
0 siblings, 11 replies; 24+ messages in thread
From: Arun R Murthy @ 2026-02-19 9:43 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: imre.deak, suraj.kandpal, Arun R Murthy
Before reading the DPCD caps for eDP wake the sink device and for DP
after reading the lttpr caps and before reading the dpcd caps wake up
the sink device.
Closes: https://issues.redhat.com/browse/RHEL-120913
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
.../drm/i915/display/intel_dp_link_training.c | 3 ++
3 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 454e6144ee4e..2fbb947e6cc8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4705,6 +4705,45 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
intel_edp_set_data_override_rates(intel_dp);
}
+void intel_dp_wake_sink(struct intel_dp *intel_dp)
+{
+ u8 value = 0;
+ int ret = 0, try = 0;
+
+ intel_dp_dpcd_set_probe(intel_dp, false);
+
+ /*
+ * Wake the sink device
+ * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by writing 0x02
+ * to DP_SET_POWER dpcd reg, 1ms time would be required to wake it up
+ */
+ while (try < 10 && ret < 0) {
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value);
+ /*
+ * If sink is in D3 then it may not respond to the AUX tx so
+ * wake it up to D3_AUX_ON state
+ */
+ if (value == DP_SET_POWER_D3) {
+ /* After setting to D0 need a min of 1ms to wake(Spec DP2.1 sec 2.3.1.2) */
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
+ DP_SET_POWER_D0);
+ fsleep(1000);
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
+ DP_SET_POWER_D3_AUX_ON);
+ break;
+ } else if ((value == DP_SET_POWER_D0) ||
+ (value == DP_SET_POWER_D3_AUX_ON)) {
+ /* if in D0 or D3_AUX_ON exit */
+ break;
+ }
+ /* Sink in D0 or even if read fails a minimum of 1ms is required to wake and respond */
+ fsleep(1000);
+ try++;
+ }
+
+ intel_dp_dpcd_set_probe(intel_dp, true);
+}
+
static bool
intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
{
@@ -4713,6 +4752,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
/* this function is meant to be called only once */
drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
+ intel_dp_wake_sink(intel_dp);
+
if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
return false;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index b0bbd5981f57..3f16077c0cc7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
int hdisplay,
int num_joined_pipes);
+void intel_dp_wake_sink(struct intel_dp *intel_dp);
#define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 54c585c59b90..cbb712ea9f60 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -270,6 +270,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
}
+ /* After reading LTTPR wake up the sink before reading DPRX caps */
+ intel_dp_wake_sink(intel_dp);
+
/*
* The DPTX shall read the DPRX caps after LTTPR detection, so re-read
* it here.
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* ✗ CI.checkpatch: warning for drm/i915/dp: On DPCD init/caps wake the DPRx
2026-02-19 9:43 [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx Arun R Murthy
@ 2026-02-19 10:45 ` Patchwork
2026-02-19 10:46 ` ✓ CI.KUnit: success " Patchwork
` (9 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2026-02-19 10:45 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-xe
== Series Details ==
Series: drm/i915/dp: On DPCD init/caps wake the DPRx
URL : https://patchwork.freedesktop.org/series/161817/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 6a253cafe4938078a6bdf6897e3e24f610d69d7e
Author: Arun R Murthy <arun.r.murthy@intel.com>
Date: Thu Feb 19 15:13:26 2026 +0530
drm/i915/dp: On DPCD init/caps wake the DPRx
Before reading the DPCD caps for eDP wake the sink device and for DP
after reading the lttpr caps and before reading the dpcd caps wake up
the sink device.
Closes: https://issues.redhat.com/browse/RHEL-120913
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
+ /mt/dim checkpatch c81e41f7aca96f583296a2a875f0179484b7a81f drm-intel
6a253cafe493 drm/i915/dp: On DPCD init/caps wake the DPRx
-:52: WARNING:LONG_LINE_COMMENT: line length of 103 exceeds 100 columns
#52: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4739:
+ /* Sink in D0 or even if read fails a minimum of 1ms is required to wake and respond */
total: 0 errors, 1 warnings, 0 checks, 69 lines checked
^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ CI.KUnit: success for drm/i915/dp: On DPCD init/caps wake the DPRx
2026-02-19 9:43 [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx Arun R Murthy
2026-02-19 10:45 ` ✗ CI.checkpatch: warning for " Patchwork
@ 2026-02-19 10:46 ` Patchwork
2026-02-19 11:22 ` ✓ Xe.CI.BAT: " Patchwork
` (8 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2026-02-19 10:46 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-xe
== Series Details ==
Series: drm/i915/dp: On DPCD init/caps wake the DPRx
URL : https://patchwork.freedesktop.org/series/161817/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:45:18] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:45:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:45:54] Starting KUnit Kernel (1/1)...
[10:45:54] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:45:54] ================== guc_buf (11 subtests) ===================
[10:45:54] [PASSED] test_smallest
[10:45:54] [PASSED] test_largest
[10:45:54] [PASSED] test_granular
[10:45:54] [PASSED] test_unique
[10:45:54] [PASSED] test_overlap
[10:45:54] [PASSED] test_reusable
[10:45:54] [PASSED] test_too_big
[10:45:54] [PASSED] test_flush
[10:45:54] [PASSED] test_lookup
[10:45:54] [PASSED] test_data
[10:45:54] [PASSED] test_class
[10:45:54] ===================== [PASSED] guc_buf =====================
[10:45:54] =================== guc_dbm (7 subtests) ===================
[10:45:54] [PASSED] test_empty
[10:45:54] [PASSED] test_default
[10:45:54] ======================== test_size ========================
[10:45:54] [PASSED] 4
[10:45:54] [PASSED] 8
[10:45:54] [PASSED] 32
[10:45:54] [PASSED] 256
[10:45:54] ==================== [PASSED] test_size ====================
[10:45:54] ======================= test_reuse ========================
[10:45:54] [PASSED] 4
[10:45:54] [PASSED] 8
[10:45:54] [PASSED] 32
[10:45:54] [PASSED] 256
[10:45:54] =================== [PASSED] test_reuse ====================
[10:45:54] =================== test_range_overlap ====================
[10:45:54] [PASSED] 4
[10:45:54] [PASSED] 8
[10:45:54] [PASSED] 32
[10:45:54] [PASSED] 256
[10:45:54] =============== [PASSED] test_range_overlap ================
[10:45:54] =================== test_range_compact ====================
[10:45:54] [PASSED] 4
[10:45:54] [PASSED] 8
[10:45:54] [PASSED] 32
[10:45:54] [PASSED] 256
[10:45:54] =============== [PASSED] test_range_compact ================
[10:45:54] ==================== test_range_spare =====================
[10:45:54] [PASSED] 4
[10:45:54] [PASSED] 8
[10:45:54] [PASSED] 32
[10:45:54] [PASSED] 256
[10:45:54] ================ [PASSED] test_range_spare =================
[10:45:54] ===================== [PASSED] guc_dbm =====================
[10:45:54] =================== guc_idm (6 subtests) ===================
[10:45:54] [PASSED] bad_init
[10:45:54] [PASSED] no_init
[10:45:54] [PASSED] init_fini
[10:45:54] [PASSED] check_used
[10:45:54] [PASSED] check_quota
[10:45:54] [PASSED] check_all
[10:45:54] ===================== [PASSED] guc_idm =====================
[10:45:54] ================== no_relay (3 subtests) ===================
[10:45:54] [PASSED] xe_drops_guc2pf_if_not_ready
[10:45:54] [PASSED] xe_drops_guc2vf_if_not_ready
[10:45:54] [PASSED] xe_rejects_send_if_not_ready
[10:45:54] ==================== [PASSED] no_relay =====================
[10:45:54] ================== pf_relay (14 subtests) ==================
[10:45:54] [PASSED] pf_rejects_guc2pf_too_short
[10:45:54] [PASSED] pf_rejects_guc2pf_too_long
[10:45:54] [PASSED] pf_rejects_guc2pf_no_payload
[10:45:54] [PASSED] pf_fails_no_payload
[10:45:54] [PASSED] pf_fails_bad_origin
[10:45:54] [PASSED] pf_fails_bad_type
[10:45:54] [PASSED] pf_txn_reports_error
[10:45:54] [PASSED] pf_txn_sends_pf2guc
[10:45:54] [PASSED] pf_sends_pf2guc
[10:45:54] [SKIPPED] pf_loopback_nop
[10:45:54] [SKIPPED] pf_loopback_echo
[10:45:54] [SKIPPED] pf_loopback_fail
[10:45:54] [SKIPPED] pf_loopback_busy
[10:45:54] [SKIPPED] pf_loopback_retry
[10:45:54] ==================== [PASSED] pf_relay =====================
[10:45:54] ================== vf_relay (3 subtests) ===================
[10:45:54] [PASSED] vf_rejects_guc2vf_too_short
[10:45:54] [PASSED] vf_rejects_guc2vf_too_long
[10:45:54] [PASSED] vf_rejects_guc2vf_no_payload
[10:45:54] ==================== [PASSED] vf_relay =====================
[10:45:54] ================ pf_gt_config (6 subtests) =================
[10:45:54] [PASSED] fair_contexts_1vf
[10:45:54] [PASSED] fair_doorbells_1vf
[10:45:54] [PASSED] fair_ggtt_1vf
[10:45:54] ====================== fair_contexts ======================
[10:45:54] [PASSED] 1 VF
[10:45:54] [PASSED] 2 VFs
[10:45:54] [PASSED] 3 VFs
[10:45:54] [PASSED] 4 VFs
[10:45:54] [PASSED] 5 VFs
[10:45:54] [PASSED] 6 VFs
[10:45:54] [PASSED] 7 VFs
[10:45:54] [PASSED] 8 VFs
[10:45:54] [PASSED] 9 VFs
[10:45:54] [PASSED] 10 VFs
[10:45:54] [PASSED] 11 VFs
[10:45:54] [PASSED] 12 VFs
[10:45:54] [PASSED] 13 VFs
[10:45:54] [PASSED] 14 VFs
[10:45:54] [PASSED] 15 VFs
[10:45:54] [PASSED] 16 VFs
[10:45:54] [PASSED] 17 VFs
[10:45:54] [PASSED] 18 VFs
[10:45:54] [PASSED] 19 VFs
[10:45:54] [PASSED] 20 VFs
[10:45:54] [PASSED] 21 VFs
[10:45:54] [PASSED] 22 VFs
[10:45:54] [PASSED] 23 VFs
[10:45:54] [PASSED] 24 VFs
[10:45:54] [PASSED] 25 VFs
[10:45:54] [PASSED] 26 VFs
[10:45:54] [PASSED] 27 VFs
[10:45:54] [PASSED] 28 VFs
[10:45:54] [PASSED] 29 VFs
[10:45:54] [PASSED] 30 VFs
[10:45:54] [PASSED] 31 VFs
[10:45:54] [PASSED] 32 VFs
[10:45:54] [PASSED] 33 VFs
[10:45:54] [PASSED] 34 VFs
[10:45:54] [PASSED] 35 VFs
[10:45:54] [PASSED] 36 VFs
[10:45:54] [PASSED] 37 VFs
[10:45:54] [PASSED] 38 VFs
[10:45:54] [PASSED] 39 VFs
[10:45:54] [PASSED] 40 VFs
[10:45:54] [PASSED] 41 VFs
[10:45:54] [PASSED] 42 VFs
[10:45:54] [PASSED] 43 VFs
[10:45:54] [PASSED] 44 VFs
[10:45:54] [PASSED] 45 VFs
[10:45:54] [PASSED] 46 VFs
[10:45:54] [PASSED] 47 VFs
[10:45:54] [PASSED] 48 VFs
[10:45:54] [PASSED] 49 VFs
[10:45:54] [PASSED] 50 VFs
[10:45:54] [PASSED] 51 VFs
[10:45:54] [PASSED] 52 VFs
[10:45:54] [PASSED] 53 VFs
[10:45:54] [PASSED] 54 VFs
[10:45:54] [PASSED] 55 VFs
[10:45:54] [PASSED] 56 VFs
[10:45:54] [PASSED] 57 VFs
[10:45:54] [PASSED] 58 VFs
[10:45:54] [PASSED] 59 VFs
[10:45:54] [PASSED] 60 VFs
[10:45:54] [PASSED] 61 VFs
[10:45:54] [PASSED] 62 VFs
[10:45:54] [PASSED] 63 VFs
[10:45:54] ================== [PASSED] fair_contexts ==================
[10:45:54] ===================== fair_doorbells ======================
[10:45:54] [PASSED] 1 VF
[10:45:54] [PASSED] 2 VFs
[10:45:54] [PASSED] 3 VFs
[10:45:54] [PASSED] 4 VFs
[10:45:54] [PASSED] 5 VFs
[10:45:54] [PASSED] 6 VFs
[10:45:54] [PASSED] 7 VFs
[10:45:54] [PASSED] 8 VFs
[10:45:54] [PASSED] 9 VFs
[10:45:54] [PASSED] 10 VFs
[10:45:54] [PASSED] 11 VFs
[10:45:54] [PASSED] 12 VFs
[10:45:54] [PASSED] 13 VFs
[10:45:54] [PASSED] 14 VFs
[10:45:54] [PASSED] 15 VFs
[10:45:54] [PASSED] 16 VFs
[10:45:54] [PASSED] 17 VFs
[10:45:54] [PASSED] 18 VFs
[10:45:54] [PASSED] 19 VFs
[10:45:54] [PASSED] 20 VFs
[10:45:54] [PASSED] 21 VFs
[10:45:54] [PASSED] 22 VFs
[10:45:54] [PASSED] 23 VFs
[10:45:54] [PASSED] 24 VFs
[10:45:54] [PASSED] 25 VFs
[10:45:54] [PASSED] 26 VFs
[10:45:54] [PASSED] 27 VFs
[10:45:54] [PASSED] 28 VFs
[10:45:54] [PASSED] 29 VFs
[10:45:54] [PASSED] 30 VFs
[10:45:54] [PASSED] 31 VFs
[10:45:54] [PASSED] 32 VFs
[10:45:54] [PASSED] 33 VFs
[10:45:54] [PASSED] 34 VFs
[10:45:54] [PASSED] 35 VFs
[10:45:54] [PASSED] 36 VFs
[10:45:54] [PASSED] 37 VFs
[10:45:54] [PASSED] 38 VFs
[10:45:54] [PASSED] 39 VFs
[10:45:54] [PASSED] 40 VFs
[10:45:54] [PASSED] 41 VFs
[10:45:54] [PASSED] 42 VFs
[10:45:54] [PASSED] 43 VFs
[10:45:54] [PASSED] 44 VFs
[10:45:54] [PASSED] 45 VFs
[10:45:54] [PASSED] 46 VFs
[10:45:54] [PASSED] 47 VFs
[10:45:54] [PASSED] 48 VFs
[10:45:54] [PASSED] 49 VFs
[10:45:54] [PASSED] 50 VFs
[10:45:54] [PASSED] 51 VFs
[10:45:54] [PASSED] 52 VFs
[10:45:54] [PASSED] 53 VFs
[10:45:54] [PASSED] 54 VFs
[10:45:54] [PASSED] 55 VFs
[10:45:54] [PASSED] 56 VFs
[10:45:54] [PASSED] 57 VFs
[10:45:54] [PASSED] 58 VFs
[10:45:54] [PASSED] 59 VFs
[10:45:54] [PASSED] 60 VFs
[10:45:54] [PASSED] 61 VFs
[10:45:54] [PASSED] 62 VFs
[10:45:54] [PASSED] 63 VFs
[10:45:54] ================= [PASSED] fair_doorbells ==================
[10:45:54] ======================== fair_ggtt ========================
[10:45:54] [PASSED] 1 VF
[10:45:54] [PASSED] 2 VFs
[10:45:54] [PASSED] 3 VFs
[10:45:54] [PASSED] 4 VFs
[10:45:54] [PASSED] 5 VFs
[10:45:54] [PASSED] 6 VFs
[10:45:54] [PASSED] 7 VFs
[10:45:54] [PASSED] 8 VFs
[10:45:54] [PASSED] 9 VFs
[10:45:54] [PASSED] 10 VFs
[10:45:54] [PASSED] 11 VFs
[10:45:54] [PASSED] 12 VFs
[10:45:54] [PASSED] 13 VFs
[10:45:54] [PASSED] 14 VFs
[10:45:54] [PASSED] 15 VFs
[10:45:54] [PASSED] 16 VFs
[10:45:54] [PASSED] 17 VFs
[10:45:54] [PASSED] 18 VFs
[10:45:54] [PASSED] 19 VFs
[10:45:54] [PASSED] 20 VFs
[10:45:54] [PASSED] 21 VFs
[10:45:54] [PASSED] 22 VFs
[10:45:54] [PASSED] 23 VFs
[10:45:54] [PASSED] 24 VFs
[10:45:54] [PASSED] 25 VFs
[10:45:54] [PASSED] 26 VFs
[10:45:54] [PASSED] 27 VFs
[10:45:54] [PASSED] 28 VFs
[10:45:54] [PASSED] 29 VFs
[10:45:54] [PASSED] 30 VFs
[10:45:54] [PASSED] 31 VFs
[10:45:54] [PASSED] 32 VFs
[10:45:54] [PASSED] 33 VFs
[10:45:54] [PASSED] 34 VFs
[10:45:54] [PASSED] 35 VFs
[10:45:54] [PASSED] 36 VFs
[10:45:54] [PASSED] 37 VFs
[10:45:54] [PASSED] 38 VFs
[10:45:54] [PASSED] 39 VFs
[10:45:54] [PASSED] 40 VFs
[10:45:54] [PASSED] 41 VFs
[10:45:54] [PASSED] 42 VFs
[10:45:54] [PASSED] 43 VFs
[10:45:54] [PASSED] 44 VFs
[10:45:54] [PASSED] 45 VFs
[10:45:54] [PASSED] 46 VFs
[10:45:54] [PASSED] 47 VFs
[10:45:54] [PASSED] 48 VFs
[10:45:54] [PASSED] 49 VFs
[10:45:54] [PASSED] 50 VFs
[10:45:54] [PASSED] 51 VFs
[10:45:54] [PASSED] 52 VFs
[10:45:54] [PASSED] 53 VFs
[10:45:54] [PASSED] 54 VFs
[10:45:54] [PASSED] 55 VFs
[10:45:54] [PASSED] 56 VFs
[10:45:54] [PASSED] 57 VFs
[10:45:54] [PASSED] 58 VFs
[10:45:54] [PASSED] 59 VFs
[10:45:54] [PASSED] 60 VFs
[10:45:54] [PASSED] 61 VFs
[10:45:54] [PASSED] 62 VFs
[10:45:54] [PASSED] 63 VFs
[10:45:54] ==================== [PASSED] fair_ggtt ====================
[10:45:54] ================== [PASSED] pf_gt_config ===================
[10:45:54] ===================== lmtt (1 subtest) =====================
[10:45:54] ======================== test_ops =========================
[10:45:54] [PASSED] 2-level
[10:45:54] [PASSED] multi-level
[10:45:54] ==================== [PASSED] test_ops =====================
[10:45:54] ====================== [PASSED] lmtt =======================
[10:45:54] ================= pf_service (11 subtests) =================
[10:45:54] [PASSED] pf_negotiate_any
[10:45:54] [PASSED] pf_negotiate_base_match
[10:45:54] [PASSED] pf_negotiate_base_newer
[10:45:54] [PASSED] pf_negotiate_base_next
[10:45:54] [SKIPPED] pf_negotiate_base_older
[10:45:54] [PASSED] pf_negotiate_base_prev
[10:45:54] [PASSED] pf_negotiate_latest_match
[10:45:54] [PASSED] pf_negotiate_latest_newer
[10:45:54] [PASSED] pf_negotiate_latest_next
[10:45:54] [SKIPPED] pf_negotiate_latest_older
[10:45:54] [SKIPPED] pf_negotiate_latest_prev
[10:45:54] =================== [PASSED] pf_service ====================
[10:45:54] ================= xe_guc_g2g (2 subtests) ==================
[10:45:54] ============== xe_live_guc_g2g_kunit_default ==============
[10:45:54] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[10:45:54] ============== xe_live_guc_g2g_kunit_allmem ===============
[10:45:54] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[10:45:54] =================== [SKIPPED] xe_guc_g2g ===================
[10:45:54] =================== xe_mocs (2 subtests) ===================
[10:45:54] ================ xe_live_mocs_kernel_kunit ================
[10:45:54] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:45:54] ================ xe_live_mocs_reset_kunit =================
[10:45:54] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:45:54] ==================== [SKIPPED] xe_mocs =====================
[10:45:54] ================= xe_migrate (2 subtests) ==================
[10:45:54] ================= xe_migrate_sanity_kunit =================
[10:45:54] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:45:54] ================== xe_validate_ccs_kunit ==================
[10:45:54] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:45:54] =================== [SKIPPED] xe_migrate ===================
[10:45:54] ================== xe_dma_buf (1 subtest) ==================
[10:45:54] ==================== xe_dma_buf_kunit =====================
[10:45:54] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:45:54] =================== [SKIPPED] xe_dma_buf ===================
[10:45:54] ================= xe_bo_shrink (1 subtest) =================
[10:45:54] =================== xe_bo_shrink_kunit ====================
[10:45:54] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:45:54] ================== [SKIPPED] xe_bo_shrink ==================
[10:45:54] ==================== xe_bo (2 subtests) ====================
[10:45:54] ================== xe_ccs_migrate_kunit ===================
[10:45:54] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:45:54] ==================== xe_bo_evict_kunit ====================
[10:45:54] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:45:54] ===================== [SKIPPED] xe_bo ======================
[10:45:54] ==================== args (13 subtests) ====================
[10:45:54] [PASSED] count_args_test
[10:45:54] [PASSED] call_args_example
[10:45:54] [PASSED] call_args_test
[10:45:54] [PASSED] drop_first_arg_example
[10:45:54] [PASSED] drop_first_arg_test
[10:45:54] [PASSED] first_arg_example
[10:45:54] [PASSED] first_arg_test
[10:45:54] [PASSED] last_arg_example
[10:45:54] [PASSED] last_arg_test
[10:45:54] [PASSED] pick_arg_example
[10:45:54] [PASSED] if_args_example
[10:45:54] [PASSED] if_args_test
[10:45:54] [PASSED] sep_comma_example
[10:45:54] ====================== [PASSED] args =======================
[10:45:54] =================== xe_pci (3 subtests) ====================
[10:45:54] ==================== check_graphics_ip ====================
[10:45:54] [PASSED] 12.00 Xe_LP
[10:45:54] [PASSED] 12.10 Xe_LP+
[10:45:54] [PASSED] 12.55 Xe_HPG
[10:45:54] [PASSED] 12.60 Xe_HPC
[10:45:54] [PASSED] 12.70 Xe_LPG
[10:45:54] [PASSED] 12.71 Xe_LPG
[10:45:54] [PASSED] 12.74 Xe_LPG+
[10:45:54] [PASSED] 20.01 Xe2_HPG
[10:45:54] [PASSED] 20.02 Xe2_HPG
[10:45:54] [PASSED] 20.04 Xe2_LPG
[10:45:54] [PASSED] 30.00 Xe3_LPG
[10:45:54] [PASSED] 30.01 Xe3_LPG
[10:45:54] [PASSED] 30.03 Xe3_LPG
[10:45:54] [PASSED] 30.04 Xe3_LPG
[10:45:54] [PASSED] 30.05 Xe3_LPG
[10:45:54] [PASSED] 35.10 Xe3p_LPG
[10:45:54] [PASSED] 35.11 Xe3p_XPC
[10:45:54] ================ [PASSED] check_graphics_ip ================
[10:45:54] ===================== check_media_ip ======================
[10:45:54] [PASSED] 12.00 Xe_M
[10:45:54] [PASSED] 12.55 Xe_HPM
[10:45:54] [PASSED] 13.00 Xe_LPM+
[10:45:54] [PASSED] 13.01 Xe2_HPM
[10:45:54] [PASSED] 20.00 Xe2_LPM
[10:45:54] [PASSED] 30.00 Xe3_LPM
[10:45:54] [PASSED] 30.02 Xe3_LPM
[10:45:54] [PASSED] 35.00 Xe3p_LPM
[10:45:54] [PASSED] 35.03 Xe3p_HPM
[10:45:54] ================= [PASSED] check_media_ip ==================
[10:45:54] =================== check_platform_desc ===================
[10:45:54] [PASSED] 0x9A60 (TIGERLAKE)
[10:45:54] [PASSED] 0x9A68 (TIGERLAKE)
[10:45:54] [PASSED] 0x9A70 (TIGERLAKE)
[10:45:54] [PASSED] 0x9A40 (TIGERLAKE)
[10:45:54] [PASSED] 0x9A49 (TIGERLAKE)
[10:45:54] [PASSED] 0x9A59 (TIGERLAKE)
[10:45:54] [PASSED] 0x9A78 (TIGERLAKE)
[10:45:54] [PASSED] 0x9AC0 (TIGERLAKE)
[10:45:54] [PASSED] 0x9AC9 (TIGERLAKE)
[10:45:54] [PASSED] 0x9AD9 (TIGERLAKE)
[10:45:54] [PASSED] 0x9AF8 (TIGERLAKE)
[10:45:54] [PASSED] 0x4C80 (ROCKETLAKE)
[10:45:54] [PASSED] 0x4C8A (ROCKETLAKE)
[10:45:54] [PASSED] 0x4C8B (ROCKETLAKE)
[10:45:54] [PASSED] 0x4C8C (ROCKETLAKE)
[10:45:54] [PASSED] 0x4C90 (ROCKETLAKE)
[10:45:54] [PASSED] 0x4C9A (ROCKETLAKE)
[10:45:54] [PASSED] 0x4680 (ALDERLAKE_S)
[10:45:54] [PASSED] 0x4682 (ALDERLAKE_S)
[10:45:54] [PASSED] 0x4688 (ALDERLAKE_S)
[10:45:54] [PASSED] 0x468A (ALDERLAKE_S)
[10:45:54] [PASSED] 0x468B (ALDERLAKE_S)
[10:45:54] [PASSED] 0x4690 (ALDERLAKE_S)
[10:45:54] [PASSED] 0x4692 (ALDERLAKE_S)
[10:45:54] [PASSED] 0x4693 (ALDERLAKE_S)
[10:45:54] [PASSED] 0x46A0 (ALDERLAKE_P)
[10:45:54] [PASSED] 0x46A1 (ALDERLAKE_P)
[10:45:54] [PASSED] 0x46A2 (ALDERLAKE_P)
[10:45:54] [PASSED] 0x46A3 (ALDERLAKE_P)
[10:45:54] [PASSED] 0x46A6 (ALDERLAKE_P)
[10:45:54] [PASSED] 0x46A8 (ALDERLAKE_P)
[10:45:54] [PASSED] 0x46AA (ALDERLAKE_P)
[10:45:54] [PASSED] 0x462A (ALDERLAKE_P)
[10:45:54] [PASSED] 0x4626 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[10:45:54] [PASSED] 0x4628 (ALDERLAKE_P)
[10:45:54] [PASSED] 0x46B0 (ALDERLAKE_P)
[10:45:54] [PASSED] 0x46B1 (ALDERLAKE_P)
[10:45:54] [PASSED] 0x46B2 (ALDERLAKE_P)
[10:45:54] [PASSED] 0x46B3 (ALDERLAKE_P)
[10:45:54] [PASSED] 0x46C0 (ALDERLAKE_P)
[10:45:54] [PASSED] 0x46C1 (ALDERLAKE_P)
[10:45:54] [PASSED] 0x46C2 (ALDERLAKE_P)
[10:45:54] [PASSED] 0x46C3 (ALDERLAKE_P)
[10:45:54] [PASSED] 0x46D0 (ALDERLAKE_N)
[10:45:54] [PASSED] 0x46D1 (ALDERLAKE_N)
[10:45:54] [PASSED] 0x46D2 (ALDERLAKE_N)
[10:45:54] [PASSED] 0x46D3 (ALDERLAKE_N)
[10:45:54] [PASSED] 0x46D4 (ALDERLAKE_N)
[10:45:54] [PASSED] 0xA721 (ALDERLAKE_P)
[10:45:54] [PASSED] 0xA7A1 (ALDERLAKE_P)
[10:45:54] [PASSED] 0xA7A9 (ALDERLAKE_P)
[10:45:54] [PASSED] 0xA7AC (ALDERLAKE_P)
[10:45:54] [PASSED] 0xA7AD (ALDERLAKE_P)
[10:45:54] [PASSED] 0xA720 (ALDERLAKE_P)
[10:45:54] [PASSED] 0xA7A0 (ALDERLAKE_P)
[10:45:54] [PASSED] 0xA7A8 (ALDERLAKE_P)
[10:45:54] [PASSED] 0xA7AA (ALDERLAKE_P)
[10:45:54] [PASSED] 0xA7AB (ALDERLAKE_P)
[10:45:54] [PASSED] 0xA780 (ALDERLAKE_S)
[10:45:54] [PASSED] 0xA781 (ALDERLAKE_S)
[10:45:54] [PASSED] 0xA782 (ALDERLAKE_S)
[10:45:54] [PASSED] 0xA783 (ALDERLAKE_S)
[10:45:54] [PASSED] 0xA788 (ALDERLAKE_S)
[10:45:54] [PASSED] 0xA789 (ALDERLAKE_S)
[10:45:54] [PASSED] 0xA78A (ALDERLAKE_S)
[10:45:54] [PASSED] 0xA78B (ALDERLAKE_S)
[10:45:54] [PASSED] 0x4905 (DG1)
[10:45:54] [PASSED] 0x4906 (DG1)
[10:45:54] [PASSED] 0x4907 (DG1)
[10:45:54] [PASSED] 0x4908 (DG1)
[10:45:54] [PASSED] 0x4909 (DG1)
[10:45:54] [PASSED] 0x56C0 (DG2)
[10:45:54] [PASSED] 0x56C2 (DG2)
[10:45:54] [PASSED] 0x56C1 (DG2)
[10:45:54] [PASSED] 0x7D51 (METEORLAKE)
[10:45:54] [PASSED] 0x7DD1 (METEORLAKE)
[10:45:54] [PASSED] 0x7D41 (METEORLAKE)
[10:45:54] [PASSED] 0x7D67 (METEORLAKE)
[10:45:54] [PASSED] 0xB640 (METEORLAKE)
[10:45:54] [PASSED] 0x56A0 (DG2)
[10:45:54] [PASSED] 0x56A1 (DG2)
[10:45:54] [PASSED] 0x56A2 (DG2)
[10:45:54] [PASSED] 0x56BE (DG2)
[10:45:54] [PASSED] 0x56BF (DG2)
[10:45:54] [PASSED] 0x5690 (DG2)
[10:45:54] [PASSED] 0x5691 (DG2)
[10:45:54] [PASSED] 0x5692 (DG2)
[10:45:54] [PASSED] 0x56A5 (DG2)
[10:45:54] [PASSED] 0x56A6 (DG2)
[10:45:54] [PASSED] 0x56B0 (DG2)
[10:45:54] [PASSED] 0x56B1 (DG2)
[10:45:54] [PASSED] 0x56BA (DG2)
[10:45:54] [PASSED] 0x56BB (DG2)
[10:45:54] [PASSED] 0x56BC (DG2)
[10:45:54] [PASSED] 0x56BD (DG2)
[10:45:54] [PASSED] 0x5693 (DG2)
[10:45:54] [PASSED] 0x5694 (DG2)
[10:45:54] [PASSED] 0x5695 (DG2)
[10:45:54] [PASSED] 0x56A3 (DG2)
[10:45:54] [PASSED] 0x56A4 (DG2)
[10:45:54] [PASSED] 0x56B2 (DG2)
[10:45:54] [PASSED] 0x56B3 (DG2)
[10:45:54] [PASSED] 0x5696 (DG2)
[10:45:54] [PASSED] 0x5697 (DG2)
[10:45:54] [PASSED] 0xB69 (PVC)
[10:45:54] [PASSED] 0xB6E (PVC)
[10:45:54] [PASSED] 0xBD4 (PVC)
[10:45:54] [PASSED] 0xBD5 (PVC)
[10:45:54] [PASSED] 0xBD6 (PVC)
[10:45:54] [PASSED] 0xBD7 (PVC)
[10:45:54] [PASSED] 0xBD8 (PVC)
[10:45:54] [PASSED] 0xBD9 (PVC)
[10:45:54] [PASSED] 0xBDA (PVC)
[10:45:54] [PASSED] 0xBDB (PVC)
[10:45:54] [PASSED] 0xBE0 (PVC)
[10:45:54] [PASSED] 0xBE1 (PVC)
[10:45:54] [PASSED] 0xBE5 (PVC)
[10:45:54] [PASSED] 0x7D40 (METEORLAKE)
[10:45:54] [PASSED] 0x7D45 (METEORLAKE)
[10:45:54] [PASSED] 0x7D55 (METEORLAKE)
[10:45:54] [PASSED] 0x7D60 (METEORLAKE)
[10:45:54] [PASSED] 0x7DD5 (METEORLAKE)
[10:45:54] [PASSED] 0x6420 (LUNARLAKE)
[10:45:54] [PASSED] 0x64A0 (LUNARLAKE)
[10:45:54] [PASSED] 0x64B0 (LUNARLAKE)
[10:45:54] [PASSED] 0xE202 (BATTLEMAGE)
[10:45:54] [PASSED] 0xE209 (BATTLEMAGE)
[10:45:54] [PASSED] 0xE20B (BATTLEMAGE)
[10:45:54] [PASSED] 0xE20C (BATTLEMAGE)
[10:45:54] [PASSED] 0xE20D (BATTLEMAGE)
[10:45:54] [PASSED] 0xE210 (BATTLEMAGE)
[10:45:54] [PASSED] 0xE211 (BATTLEMAGE)
[10:45:54] [PASSED] 0xE212 (BATTLEMAGE)
[10:45:54] [PASSED] 0xE216 (BATTLEMAGE)
[10:45:54] [PASSED] 0xE220 (BATTLEMAGE)
[10:45:54] [PASSED] 0xE221 (BATTLEMAGE)
[10:45:54] [PASSED] 0xE222 (BATTLEMAGE)
[10:45:54] [PASSED] 0xE223 (BATTLEMAGE)
[10:45:54] [PASSED] 0xB080 (PANTHERLAKE)
[10:45:54] [PASSED] 0xB081 (PANTHERLAKE)
[10:45:54] [PASSED] 0xB082 (PANTHERLAKE)
[10:45:54] [PASSED] 0xB083 (PANTHERLAKE)
[10:45:54] [PASSED] 0xB084 (PANTHERLAKE)
[10:45:54] [PASSED] 0xB085 (PANTHERLAKE)
[10:45:54] [PASSED] 0xB086 (PANTHERLAKE)
[10:45:54] [PASSED] 0xB087 (PANTHERLAKE)
[10:45:54] [PASSED] 0xB08F (PANTHERLAKE)
[10:45:54] [PASSED] 0xB090 (PANTHERLAKE)
[10:45:54] [PASSED] 0xB0A0 (PANTHERLAKE)
[10:45:54] [PASSED] 0xB0B0 (PANTHERLAKE)
[10:45:54] [PASSED] 0xFD80 (PANTHERLAKE)
[10:45:54] [PASSED] 0xFD81 (PANTHERLAKE)
[10:45:54] [PASSED] 0xD740 (NOVALAKE_S)
[10:45:54] [PASSED] 0xD741 (NOVALAKE_S)
[10:45:54] [PASSED] 0xD742 (NOVALAKE_S)
[10:45:54] [PASSED] 0xD743 (NOVALAKE_S)
[10:45:54] [PASSED] 0xD744 (NOVALAKE_S)
[10:45:54] [PASSED] 0xD745 (NOVALAKE_S)
[10:45:54] [PASSED] 0x674C (CRESCENTISLAND)
[10:45:54] [PASSED] 0xD750 (NOVALAKE_P)
[10:45:54] [PASSED] 0xD751 (NOVALAKE_P)
[10:45:54] [PASSED] 0xD752 (NOVALAKE_P)
[10:45:54] [PASSED] 0xD753 (NOVALAKE_P)
[10:45:54] [PASSED] 0xD754 (NOVALAKE_P)
[10:45:54] [PASSED] 0xD755 (NOVALAKE_P)
[10:45:54] [PASSED] 0xD756 (NOVALAKE_P)
[10:45:54] [PASSED] 0xD757 (NOVALAKE_P)
[10:45:54] [PASSED] 0xD75F (NOVALAKE_P)
[10:45:54] =============== [PASSED] check_platform_desc ===============
[10:45:54] ===================== [PASSED] xe_pci ======================
[10:45:54] =================== xe_rtp (2 subtests) ====================
[10:45:54] =============== xe_rtp_process_to_sr_tests ================
[10:45:54] [PASSED] coalesce-same-reg
[10:45:54] [PASSED] no-match-no-add
[10:45:54] [PASSED] match-or
[10:45:54] [PASSED] match-or-xfail
[10:45:54] [PASSED] no-match-no-add-multiple-rules
[10:45:54] [PASSED] two-regs-two-entries
[10:45:54] [PASSED] clr-one-set-other
[10:45:54] [PASSED] set-field
[10:45:54] [PASSED] conflict-duplicate
[10:45:54] [PASSED] conflict-not-disjoint
[10:45:54] [PASSED] conflict-reg-type
[10:45:54] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:45:54] ================== xe_rtp_process_tests ===================
[10:45:54] [PASSED] active1
[10:45:54] [PASSED] active2
[10:45:54] [PASSED] active-inactive
[10:45:54] [PASSED] inactive-active
[10:45:54] [PASSED] inactive-1st_or_active-inactive
[10:45:54] [PASSED] inactive-2nd_or_active-inactive
[10:45:54] [PASSED] inactive-last_or_active-inactive
[10:45:54] [PASSED] inactive-no_or_active-inactive
[10:45:54] ============== [PASSED] xe_rtp_process_tests ===============
[10:45:54] ===================== [PASSED] xe_rtp ======================
[10:45:54] ==================== xe_wa (1 subtest) =====================
[10:45:54] ======================== xe_wa_gt =========================
[10:45:54] [PASSED] TIGERLAKE B0
[10:45:54] [PASSED] DG1 A0
[10:45:54] [PASSED] DG1 B0
[10:45:54] [PASSED] ALDERLAKE_S A0
[10:45:54] [PASSED] ALDERLAKE_S B0
[10:45:54] [PASSED] ALDERLAKE_S C0
[10:45:54] [PASSED] ALDERLAKE_S D0
[10:45:54] [PASSED] ALDERLAKE_P A0
[10:45:54] [PASSED] ALDERLAKE_P B0
[10:45:54] [PASSED] ALDERLAKE_P C0
[10:45:54] [PASSED] ALDERLAKE_S RPLS D0
[10:45:54] [PASSED] ALDERLAKE_P RPLU E0
[10:45:54] [PASSED] DG2 G10 C0
[10:45:54] [PASSED] DG2 G11 B1
[10:45:54] [PASSED] DG2 G12 A1
[10:45:54] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:45:54] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:45:54] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[10:45:54] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[10:45:54] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[10:45:54] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[10:45:54] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[10:45:54] ==================== [PASSED] xe_wa_gt =====================
[10:45:54] ====================== [PASSED] xe_wa ======================
[10:45:54] ============================================================
[10:45:54] Testing complete. Ran 522 tests: passed: 504, skipped: 18
[10:45:54] Elapsed time: 36.460s total, 4.219s configuring, 31.724s building, 0.475s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:45:54] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:45:56] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:46:22] Starting KUnit Kernel (1/1)...
[10:46:22] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:46:22] ============ drm_test_pick_cmdline (2 subtests) ============
[10:46:22] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[10:46:22] =============== drm_test_pick_cmdline_named ===============
[10:46:22] [PASSED] NTSC
[10:46:22] [PASSED] NTSC-J
[10:46:22] [PASSED] PAL
[10:46:22] [PASSED] PAL-M
[10:46:22] =========== [PASSED] drm_test_pick_cmdline_named ===========
[10:46:22] ============== [PASSED] drm_test_pick_cmdline ==============
[10:46:22] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:46:22] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:46:22] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:46:22] =========== drm_validate_clone_mode (2 subtests) ===========
[10:46:22] ============== drm_test_check_in_clone_mode ===============
[10:46:22] [PASSED] in_clone_mode
[10:46:22] [PASSED] not_in_clone_mode
[10:46:22] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:46:22] =============== drm_test_check_valid_clones ===============
[10:46:22] [PASSED] not_in_clone_mode
[10:46:22] [PASSED] valid_clone
[10:46:22] [PASSED] invalid_clone
[10:46:22] =========== [PASSED] drm_test_check_valid_clones ===========
[10:46:22] ============= [PASSED] drm_validate_clone_mode =============
[10:46:22] ============= drm_validate_modeset (1 subtest) =============
[10:46:22] [PASSED] drm_test_check_connector_changed_modeset
[10:46:22] ============== [PASSED] drm_validate_modeset ===============
[10:46:22] ====== drm_test_bridge_get_current_state (2 subtests) ======
[10:46:22] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:46:22] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[10:46:22] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:46:22] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[10:46:22] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:46:22] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:46:22] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[10:46:22] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:46:22] ============== drm_bridge_alloc (2 subtests) ===============
[10:46:22] [PASSED] drm_test_drm_bridge_alloc_basic
[10:46:22] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:46:22] ================ [PASSED] drm_bridge_alloc =================
[10:46:22] ============= drm_cmdline_parser (40 subtests) =============
[10:46:22] [PASSED] drm_test_cmdline_force_d_only
[10:46:22] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:46:22] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:46:22] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:46:22] [PASSED] drm_test_cmdline_force_e_only
[10:46:22] [PASSED] drm_test_cmdline_res
[10:46:22] [PASSED] drm_test_cmdline_res_vesa
[10:46:22] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:46:22] [PASSED] drm_test_cmdline_res_rblank
[10:46:22] [PASSED] drm_test_cmdline_res_bpp
[10:46:22] [PASSED] drm_test_cmdline_res_refresh
[10:46:22] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:46:22] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:46:22] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:46:22] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:46:22] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:46:22] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:46:22] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:46:22] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:46:22] [PASSED] drm_test_cmdline_res_margins_force_on
[10:46:22] [PASSED] drm_test_cmdline_res_vesa_margins
[10:46:22] [PASSED] drm_test_cmdline_name
[10:46:22] [PASSED] drm_test_cmdline_name_bpp
[10:46:22] [PASSED] drm_test_cmdline_name_option
[10:46:22] [PASSED] drm_test_cmdline_name_bpp_option
[10:46:22] [PASSED] drm_test_cmdline_rotate_0
[10:46:22] [PASSED] drm_test_cmdline_rotate_90
[10:46:22] [PASSED] drm_test_cmdline_rotate_180
[10:46:22] [PASSED] drm_test_cmdline_rotate_270
[10:46:22] [PASSED] drm_test_cmdline_hmirror
[10:46:22] [PASSED] drm_test_cmdline_vmirror
[10:46:22] [PASSED] drm_test_cmdline_margin_options
[10:46:22] [PASSED] drm_test_cmdline_multiple_options
[10:46:22] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:46:22] [PASSED] drm_test_cmdline_extra_and_option
[10:46:22] [PASSED] drm_test_cmdline_freestanding_options
[10:46:22] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:46:22] [PASSED] drm_test_cmdline_panel_orientation
[10:46:22] ================ drm_test_cmdline_invalid =================
[10:46:22] [PASSED] margin_only
[10:46:22] [PASSED] interlace_only
[10:46:22] [PASSED] res_missing_x
[10:46:22] [PASSED] res_missing_y
[10:46:22] [PASSED] res_bad_y
[10:46:22] [PASSED] res_missing_y_bpp
[10:46:22] [PASSED] res_bad_bpp
[10:46:22] [PASSED] res_bad_refresh
[10:46:22] [PASSED] res_bpp_refresh_force_on_off
[10:46:22] [PASSED] res_invalid_mode
[10:46:22] [PASSED] res_bpp_wrong_place_mode
[10:46:22] [PASSED] name_bpp_refresh
[10:46:22] [PASSED] name_refresh
[10:46:22] [PASSED] name_refresh_wrong_mode
[10:46:22] [PASSED] name_refresh_invalid_mode
[10:46:22] [PASSED] rotate_multiple
[10:46:22] [PASSED] rotate_invalid_val
[10:46:22] [PASSED] rotate_truncated
[10:46:22] [PASSED] invalid_option
[10:46:22] [PASSED] invalid_tv_option
[10:46:22] [PASSED] truncated_tv_option
[10:46:22] ============ [PASSED] drm_test_cmdline_invalid =============
[10:46:22] =============== drm_test_cmdline_tv_options ===============
[10:46:22] [PASSED] NTSC
[10:46:22] [PASSED] NTSC_443
[10:46:22] [PASSED] NTSC_J
[10:46:22] [PASSED] PAL
[10:46:22] [PASSED] PAL_M
[10:46:22] [PASSED] PAL_N
[10:46:22] [PASSED] SECAM
[10:46:22] [PASSED] MONO_525
[10:46:22] [PASSED] MONO_625
[10:46:22] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:46:22] =============== [PASSED] drm_cmdline_parser ================
[10:46:22] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:46:22] [PASSED] drm_test_connector_hdmi_init_valid
[10:46:22] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:46:22] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:46:22] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:46:22] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:46:22] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:46:22] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:46:22] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:46:22] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:46:22] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:46:22] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:46:22] [PASSED] supported_formats=0x3 yuv420_allowed=1
[10:46:22] [PASSED] supported_formats=0x3 yuv420_allowed=0
[10:46:22] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:46:22] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:46:22] [PASSED] drm_test_connector_hdmi_init_null_product
[10:46:22] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:46:22] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:46:22] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:46:22] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:46:22] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:46:22] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:46:22] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:46:22] ========= drm_test_connector_hdmi_init_type_valid =========
[10:46:22] [PASSED] HDMI-A
[10:46:22] [PASSED] HDMI-B
[10:46:22] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:46:22] ======== drm_test_connector_hdmi_init_type_invalid ========
[10:46:22] [PASSED] Unknown
[10:46:22] [PASSED] VGA
[10:46:22] [PASSED] DVI-I
[10:46:22] [PASSED] DVI-D
[10:46:22] [PASSED] DVI-A
[10:46:22] [PASSED] Composite
[10:46:22] [PASSED] SVIDEO
[10:46:22] [PASSED] LVDS
[10:46:22] [PASSED] Component
[10:46:22] [PASSED] DIN
[10:46:22] [PASSED] DP
[10:46:22] [PASSED] TV
[10:46:22] [PASSED] eDP
[10:46:22] [PASSED] Virtual
[10:46:22] [PASSED] DSI
[10:46:22] [PASSED] DPI
[10:46:22] [PASSED] Writeback
[10:46:22] [PASSED] SPI
[10:46:22] [PASSED] USB
[10:46:22] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:46:22] ============ [PASSED] drmm_connector_hdmi_init =============
[10:46:22] ============= drmm_connector_init (3 subtests) =============
[10:46:22] [PASSED] drm_test_drmm_connector_init
[10:46:22] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:46:22] ========= drm_test_drmm_connector_init_type_valid =========
[10:46:22] [PASSED] Unknown
[10:46:22] [PASSED] VGA
[10:46:22] [PASSED] DVI-I
[10:46:22] [PASSED] DVI-D
[10:46:22] [PASSED] DVI-A
[10:46:22] [PASSED] Composite
[10:46:22] [PASSED] SVIDEO
[10:46:22] [PASSED] LVDS
[10:46:22] [PASSED] Component
[10:46:22] [PASSED] DIN
[10:46:22] [PASSED] DP
[10:46:22] [PASSED] HDMI-A
[10:46:22] [PASSED] HDMI-B
[10:46:22] [PASSED] TV
[10:46:22] [PASSED] eDP
[10:46:22] [PASSED] Virtual
[10:46:22] [PASSED] DSI
[10:46:22] [PASSED] DPI
[10:46:22] [PASSED] Writeback
[10:46:22] [PASSED] SPI
[10:46:22] [PASSED] USB
[10:46:22] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:46:22] =============== [PASSED] drmm_connector_init ===============
[10:46:22] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:46:22] [PASSED] drm_test_drm_connector_dynamic_init
[10:46:22] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:46:22] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:46:22] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:46:22] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[10:46:22] [PASSED] Unknown
[10:46:22] [PASSED] VGA
[10:46:22] [PASSED] DVI-I
[10:46:22] [PASSED] DVI-D
[10:46:22] [PASSED] DVI-A
[10:46:22] [PASSED] Composite
[10:46:22] [PASSED] SVIDEO
[10:46:22] [PASSED] LVDS
[10:46:22] [PASSED] Component
[10:46:22] [PASSED] DIN
[10:46:22] [PASSED] DP
[10:46:22] [PASSED] HDMI-A
[10:46:22] [PASSED] HDMI-B
[10:46:22] [PASSED] TV
[10:46:22] [PASSED] eDP
[10:46:22] [PASSED] Virtual
[10:46:22] [PASSED] DSI
[10:46:22] [PASSED] DPI
[10:46:22] [PASSED] Writeback
[10:46:22] [PASSED] SPI
[10:46:22] [PASSED] USB
[10:46:22] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:46:22] ======== drm_test_drm_connector_dynamic_init_name =========
[10:46:22] [PASSED] Unknown
[10:46:22] [PASSED] VGA
[10:46:22] [PASSED] DVI-I
[10:46:22] [PASSED] DVI-D
[10:46:22] [PASSED] DVI-A
[10:46:22] [PASSED] Composite
[10:46:22] [PASSED] SVIDEO
[10:46:22] [PASSED] LVDS
[10:46:22] [PASSED] Component
[10:46:22] [PASSED] DIN
[10:46:22] [PASSED] DP
[10:46:22] [PASSED] HDMI-A
[10:46:22] [PASSED] HDMI-B
[10:46:22] [PASSED] TV
[10:46:22] [PASSED] eDP
[10:46:22] [PASSED] Virtual
[10:46:22] [PASSED] DSI
[10:46:22] [PASSED] DPI
[10:46:22] [PASSED] Writeback
[10:46:22] [PASSED] SPI
[10:46:22] [PASSED] USB
[10:46:22] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:46:22] =========== [PASSED] drm_connector_dynamic_init ============
[10:46:22] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:46:22] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:46:22] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:46:22] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:46:22] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:46:22] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:46:22] ======= drm_connector_dynamic_register (7 subtests) ========
[10:46:22] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:46:22] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:46:22] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:46:22] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:46:22] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:46:22] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:46:22] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:46:22] ========= [PASSED] drm_connector_dynamic_register ==========
[10:46:22] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:46:22] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:46:22] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:46:22] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:46:22] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:46:22] ========== drm_test_get_tv_mode_from_name_valid ===========
[10:46:22] [PASSED] NTSC
[10:46:22] [PASSED] NTSC-443
[10:46:22] [PASSED] NTSC-J
[10:46:22] [PASSED] PAL
[10:46:22] [PASSED] PAL-M
[10:46:22] [PASSED] PAL-N
[10:46:22] [PASSED] SECAM
[10:46:22] [PASSED] Mono
[10:46:22] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:46:22] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:46:22] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:46:22] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:46:22] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:46:22] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:46:22] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:46:22] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:46:22] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:46:22] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:46:22] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[10:46:22] [PASSED] VIC 96
[10:46:22] [PASSED] VIC 97
[10:46:22] [PASSED] VIC 101
[10:46:22] [PASSED] VIC 102
[10:46:22] [PASSED] VIC 106
[10:46:22] [PASSED] VIC 107
[10:46:22] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:46:22] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:46:22] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:46:22] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:46:22] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:46:22] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:46:22] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:46:22] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:46:22] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[10:46:22] [PASSED] Automatic
[10:46:22] [PASSED] Full
[10:46:22] [PASSED] Limited 16:235
[10:46:22] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:46:22] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:46:22] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:46:22] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:46:22] === drm_test_drm_hdmi_connector_get_output_format_name ====
[10:46:22] [PASSED] RGB
[10:46:22] [PASSED] YUV 4:2:0
[10:46:22] [PASSED] YUV 4:2:2
[10:46:22] [PASSED] YUV 4:4:4
[10:46:22] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:46:22] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:46:22] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:46:22] ============= drm_damage_helper (21 subtests) ==============
[10:46:22] [PASSED] drm_test_damage_iter_no_damage
[10:46:22] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:46:22] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:46:22] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:46:22] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:46:22] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:46:22] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:46:22] [PASSED] drm_test_damage_iter_simple_damage
[10:46:22] [PASSED] drm_test_damage_iter_single_damage
[10:46:22] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:46:22] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:46:22] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:46:22] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:46:22] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:46:22] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:46:22] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:46:22] [PASSED] drm_test_damage_iter_damage
[10:46:22] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:46:22] [PASSED] drm_test_damage_iter_damage_one_outside
[10:46:22] [PASSED] drm_test_damage_iter_damage_src_moved
[10:46:22] [PASSED] drm_test_damage_iter_damage_not_visible
[10:46:22] ================ [PASSED] drm_damage_helper ================
[10:46:22] ============== drm_dp_mst_helper (3 subtests) ==============
[10:46:22] ============== drm_test_dp_mst_calc_pbn_mode ==============
[10:46:22] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:46:22] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:46:22] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:46:22] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:46:22] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:46:22] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:46:22] ============== drm_test_dp_mst_calc_pbn_div ===============
[10:46:22] [PASSED] Link rate 2000000 lane count 4
[10:46:22] [PASSED] Link rate 2000000 lane count 2
[10:46:22] [PASSED] Link rate 2000000 lane count 1
[10:46:22] [PASSED] Link rate 1350000 lane count 4
[10:46:22] [PASSED] Link rate 1350000 lane count 2
[10:46:22] [PASSED] Link rate 1350000 lane count 1
[10:46:22] [PASSED] Link rate 1000000 lane count 4
[10:46:22] [PASSED] Link rate 1000000 lane count 2
[10:46:22] [PASSED] Link rate 1000000 lane count 1
[10:46:22] [PASSED] Link rate 810000 lane count 4
[10:46:22] [PASSED] Link rate 810000 lane count 2
[10:46:22] [PASSED] Link rate 810000 lane count 1
[10:46:22] [PASSED] Link rate 540000 lane count 4
[10:46:22] [PASSED] Link rate 540000 lane count 2
[10:46:22] [PASSED] Link rate 540000 lane count 1
[10:46:22] [PASSED] Link rate 270000 lane count 4
[10:46:22] [PASSED] Link rate 270000 lane count 2
[10:46:22] [PASSED] Link rate 270000 lane count 1
[10:46:22] [PASSED] Link rate 162000 lane count 4
[10:46:22] [PASSED] Link rate 162000 lane count 2
[10:46:22] [PASSED] Link rate 162000 lane count 1
[10:46:22] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:46:22] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[10:46:22] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:46:22] [PASSED] DP_POWER_UP_PHY with port number
[10:46:22] [PASSED] DP_POWER_DOWN_PHY with port number
[10:46:22] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:46:22] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:46:22] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:46:22] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:46:22] [PASSED] DP_QUERY_PAYLOAD with port number
[10:46:22] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:46:22] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:46:22] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:46:22] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:46:22] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:46:22] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:46:22] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:46:22] [PASSED] DP_REMOTE_I2C_READ with port number
[10:46:22] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:46:22] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:46:22] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:46:22] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:46:22] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:46:22] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:46:22] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:46:22] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:46:22] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:46:22] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:46:22] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:46:22] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:46:22] ================ [PASSED] drm_dp_mst_helper ================
[10:46:22] ================== drm_exec (7 subtests) ===================
[10:46:22] [PASSED] sanitycheck
[10:46:22] [PASSED] test_lock
[10:46:22] [PASSED] test_lock_unlock
[10:46:22] [PASSED] test_duplicates
[10:46:22] [PASSED] test_prepare
[10:46:22] [PASSED] test_prepare_array
[10:46:22] [PASSED] test_multiple_loops
[10:46:22] ==================== [PASSED] drm_exec =====================
[10:46:22] =========== drm_format_helper_test (17 subtests) ===========
[10:46:22] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[10:46:22] [PASSED] single_pixel_source_buffer
[10:46:22] [PASSED] single_pixel_clip_rectangle
[10:46:22] [PASSED] well_known_colors
[10:46:22] [PASSED] destination_pitch
[10:46:22] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:46:22] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[10:46:22] [PASSED] single_pixel_source_buffer
[10:46:22] [PASSED] single_pixel_clip_rectangle
[10:46:22] [PASSED] well_known_colors
[10:46:22] [PASSED] destination_pitch
[10:46:22] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:46:22] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[10:46:22] [PASSED] single_pixel_source_buffer
[10:46:22] [PASSED] single_pixel_clip_rectangle
[10:46:22] [PASSED] well_known_colors
[10:46:22] [PASSED] destination_pitch
[10:46:22] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:46:22] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[10:46:22] [PASSED] single_pixel_source_buffer
[10:46:22] [PASSED] single_pixel_clip_rectangle
[10:46:22] [PASSED] well_known_colors
[10:46:22] [PASSED] destination_pitch
[10:46:22] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:46:22] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[10:46:22] [PASSED] single_pixel_source_buffer
[10:46:22] [PASSED] single_pixel_clip_rectangle
[10:46:22] [PASSED] well_known_colors
[10:46:22] [PASSED] destination_pitch
[10:46:22] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:46:22] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[10:46:22] [PASSED] single_pixel_source_buffer
[10:46:22] [PASSED] single_pixel_clip_rectangle
[10:46:22] [PASSED] well_known_colors
[10:46:22] [PASSED] destination_pitch
[10:46:22] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:46:22] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[10:46:22] [PASSED] single_pixel_source_buffer
[10:46:22] [PASSED] single_pixel_clip_rectangle
[10:46:22] [PASSED] well_known_colors
[10:46:22] [PASSED] destination_pitch
[10:46:22] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:46:22] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[10:46:22] [PASSED] single_pixel_source_buffer
[10:46:22] [PASSED] single_pixel_clip_rectangle
[10:46:22] [PASSED] well_known_colors
[10:46:22] [PASSED] destination_pitch
[10:46:22] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:46:22] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[10:46:22] [PASSED] single_pixel_source_buffer
[10:46:22] [PASSED] single_pixel_clip_rectangle
[10:46:22] [PASSED] well_known_colors
[10:46:22] [PASSED] destination_pitch
[10:46:22] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:46:22] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[10:46:22] [PASSED] single_pixel_source_buffer
[10:46:22] [PASSED] single_pixel_clip_rectangle
[10:46:22] [PASSED] well_known_colors
[10:46:22] [PASSED] destination_pitch
[10:46:22] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:46:22] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[10:46:22] [PASSED] single_pixel_source_buffer
[10:46:22] [PASSED] single_pixel_clip_rectangle
[10:46:22] [PASSED] well_known_colors
[10:46:22] [PASSED] destination_pitch
[10:46:22] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:46:22] ============== drm_test_fb_xrgb8888_to_mono ===============
[10:46:22] [PASSED] single_pixel_source_buffer
[10:46:22] [PASSED] single_pixel_clip_rectangle
[10:46:22] [PASSED] well_known_colors
[10:46:22] [PASSED] destination_pitch
[10:46:22] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:46:22] ==================== drm_test_fb_swab =====================
[10:46:22] [PASSED] single_pixel_source_buffer
[10:46:22] [PASSED] single_pixel_clip_rectangle
[10:46:22] [PASSED] well_known_colors
[10:46:22] [PASSED] destination_pitch
[10:46:22] ================ [PASSED] drm_test_fb_swab =================
[10:46:22] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[10:46:22] [PASSED] single_pixel_source_buffer
[10:46:22] [PASSED] single_pixel_clip_rectangle
[10:46:22] [PASSED] well_known_colors
[10:46:22] [PASSED] destination_pitch
[10:46:22] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:46:22] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[10:46:22] [PASSED] single_pixel_source_buffer
[10:46:22] [PASSED] single_pixel_clip_rectangle
[10:46:22] [PASSED] well_known_colors
[10:46:22] [PASSED] destination_pitch
[10:46:22] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:46:22] ================= drm_test_fb_clip_offset =================
[10:46:22] [PASSED] pass through
[10:46:22] [PASSED] horizontal offset
[10:46:22] [PASSED] vertical offset
[10:46:22] [PASSED] horizontal and vertical offset
[10:46:22] [PASSED] horizontal offset (custom pitch)
[10:46:22] [PASSED] vertical offset (custom pitch)
[10:46:22] [PASSED] horizontal and vertical offset (custom pitch)
[10:46:22] ============= [PASSED] drm_test_fb_clip_offset =============
[10:46:22] =================== drm_test_fb_memcpy ====================
[10:46:22] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:46:22] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:46:22] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:46:22] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:46:22] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:46:22] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:46:22] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:46:22] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:46:22] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:46:22] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:46:22] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:46:22] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:46:22] =============== [PASSED] drm_test_fb_memcpy ================
[10:46:22] ============= [PASSED] drm_format_helper_test ==============
[10:46:22] ================= drm_format (18 subtests) =================
[10:46:22] [PASSED] drm_test_format_block_width_invalid
[10:46:22] [PASSED] drm_test_format_block_width_one_plane
[10:46:22] [PASSED] drm_test_format_block_width_two_plane
[10:46:22] [PASSED] drm_test_format_block_width_three_plane
[10:46:22] [PASSED] drm_test_format_block_width_tiled
[10:46:22] [PASSED] drm_test_format_block_height_invalid
[10:46:22] [PASSED] drm_test_format_block_height_one_plane
[10:46:22] [PASSED] drm_test_format_block_height_two_plane
[10:46:22] [PASSED] drm_test_format_block_height_three_plane
[10:46:22] [PASSED] drm_test_format_block_height_tiled
[10:46:22] [PASSED] drm_test_format_min_pitch_invalid
[10:46:22] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:46:22] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:46:22] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:46:22] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:46:22] [PASSED] drm_test_format_min_pitch_two_plane
[10:46:22] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:46:22] [PASSED] drm_test_format_min_pitch_tiled
[10:46:22] =================== [PASSED] drm_format ====================
[10:46:22] ============== drm_framebuffer (10 subtests) ===============
[10:46:22] ========== drm_test_framebuffer_check_src_coords ==========
[10:46:22] [PASSED] Success: source fits into fb
[10:46:22] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:46:22] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:46:22] [PASSED] Fail: overflowing fb with source width
[10:46:22] [PASSED] Fail: overflowing fb with source height
[10:46:22] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:46:22] [PASSED] drm_test_framebuffer_cleanup
[10:46:22] =============== drm_test_framebuffer_create ===============
[10:46:22] [PASSED] ABGR8888 normal sizes
[10:46:22] [PASSED] ABGR8888 max sizes
[10:46:22] [PASSED] ABGR8888 pitch greater than min required
[10:46:22] [PASSED] ABGR8888 pitch less than min required
[10:46:22] [PASSED] ABGR8888 Invalid width
[10:46:22] [PASSED] ABGR8888 Invalid buffer handle
[10:46:22] [PASSED] No pixel format
[10:46:22] [PASSED] ABGR8888 Width 0
[10:46:22] [PASSED] ABGR8888 Height 0
[10:46:22] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:46:22] [PASSED] ABGR8888 Large buffer offset
[10:46:22] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:46:22] [PASSED] ABGR8888 Invalid flag
[10:46:22] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:46:22] [PASSED] ABGR8888 Valid buffer modifier
[10:46:22] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:46:22] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:46:22] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:46:22] [PASSED] NV12 Normal sizes
[10:46:22] [PASSED] NV12 Max sizes
[10:46:22] [PASSED] NV12 Invalid pitch
[10:46:22] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:46:22] [PASSED] NV12 different modifier per-plane
[10:46:22] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:46:22] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:46:22] [PASSED] NV12 Modifier for inexistent plane
[10:46:22] [PASSED] NV12 Handle for inexistent plane
[10:46:22] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:46:22] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:46:22] [PASSED] YVU420 Normal sizes
[10:46:22] [PASSED] YVU420 Max sizes
[10:46:22] [PASSED] YVU420 Invalid pitch
[10:46:22] [PASSED] YVU420 Different pitches
[10:46:22] [PASSED] YVU420 Different buffer offsets/pitches
[10:46:22] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:46:22] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:46:22] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:46:22] [PASSED] YVU420 Valid modifier
[10:46:22] [PASSED] YVU420 Different modifiers per plane
[10:46:22] [PASSED] YVU420 Modifier for inexistent plane
[10:46:22] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:46:22] [PASSED] X0L2 Normal sizes
[10:46:22] [PASSED] X0L2 Max sizes
[10:46:22] [PASSED] X0L2 Invalid pitch
[10:46:22] [PASSED] X0L2 Pitch greater than minimum required
[10:46:22] [PASSED] X0L2 Handle for inexistent plane
[10:46:22] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:46:22] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:46:22] [PASSED] X0L2 Valid modifier
[10:46:22] [PASSED] X0L2 Modifier for inexistent plane
[10:46:22] =========== [PASSED] drm_test_framebuffer_create ===========
[10:46:22] [PASSED] drm_test_framebuffer_free
[10:46:22] [PASSED] drm_test_framebuffer_init
[10:46:22] [PASSED] drm_test_framebuffer_init_bad_format
[10:46:22] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:46:22] [PASSED] drm_test_framebuffer_lookup
[10:46:22] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:46:22] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:46:22] ================= [PASSED] drm_framebuffer =================
[10:46:22] ================ drm_gem_shmem (8 subtests) ================
[10:46:22] [PASSED] drm_gem_shmem_test_obj_create
[10:46:22] [PASSED] drm_gem_shmem_test_obj_create_private
[10:46:22] [PASSED] drm_gem_shmem_test_pin_pages
[10:46:22] [PASSED] drm_gem_shmem_test_vmap
[10:46:22] [PASSED] drm_gem_shmem_test_get_sg_table
[10:46:22] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:46:22] [PASSED] drm_gem_shmem_test_madvise
[10:46:22] [PASSED] drm_gem_shmem_test_purge
[10:46:22] ================== [PASSED] drm_gem_shmem ==================
[10:46:22] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[10:46:22] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:46:22] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:46:22] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:46:22] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:46:22] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:46:22] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:46:22] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[10:46:22] [PASSED] Automatic
[10:46:22] [PASSED] Full
[10:46:22] [PASSED] Limited 16:235
[10:46:22] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:46:22] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:46:22] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:46:22] [PASSED] drm_test_check_disable_connector
[10:46:22] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:46:22] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:46:22] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:46:22] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:46:22] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:46:22] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:46:22] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:46:22] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:46:22] [PASSED] drm_test_check_output_bpc_dvi
[10:46:22] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:46:22] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:46:22] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:46:22] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:46:22] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:46:22] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:46:22] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:46:22] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:46:22] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:46:22] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:46:22] [PASSED] drm_test_check_broadcast_rgb_value
[10:46:22] [PASSED] drm_test_check_bpc_8_value
[10:46:22] [PASSED] drm_test_check_bpc_10_value
[10:46:22] [PASSED] drm_test_check_bpc_12_value
[10:46:22] [PASSED] drm_test_check_format_value
[10:46:22] [PASSED] drm_test_check_tmds_char_value
[10:46:22] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:46:22] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[10:46:22] [PASSED] drm_test_check_mode_valid
[10:46:22] [PASSED] drm_test_check_mode_valid_reject
[10:46:22] [PASSED] drm_test_check_mode_valid_reject_rate
[10:46:22] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:46:22] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:46:22] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[10:46:22] [PASSED] drm_test_check_infoframes
[10:46:22] [PASSED] drm_test_check_reject_avi_infoframe
[10:46:22] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[10:46:22] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[10:46:22] [PASSED] drm_test_check_reject_audio_infoframe
[10:46:22] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[10:46:22] ================= drm_managed (2 subtests) =================
[10:46:22] [PASSED] drm_test_managed_release_action
[10:46:22] [PASSED] drm_test_managed_run_action
[10:46:22] =================== [PASSED] drm_managed ===================
[10:46:22] =================== drm_mm (6 subtests) ====================
[10:46:22] [PASSED] drm_test_mm_init
[10:46:22] [PASSED] drm_test_mm_debug
[10:46:22] [PASSED] drm_test_mm_align32
[10:46:22] [PASSED] drm_test_mm_align64
[10:46:22] [PASSED] drm_test_mm_lowest
[10:46:22] [PASSED] drm_test_mm_highest
[10:46:22] ===================== [PASSED] drm_mm ======================
[10:46:22] ============= drm_modes_analog_tv (5 subtests) =============
[10:46:22] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:46:22] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:46:22] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:46:22] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:46:22] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:46:22] =============== [PASSED] drm_modes_analog_tv ===============
[10:46:22] ============== drm_plane_helper (2 subtests) ===============
[10:46:22] =============== drm_test_check_plane_state ================
[10:46:22] [PASSED] clipping_simple
[10:46:22] [PASSED] clipping_rotate_reflect
[10:46:22] [PASSED] positioning_simple
[10:46:22] [PASSED] upscaling
[10:46:22] [PASSED] downscaling
[10:46:22] [PASSED] rounding1
[10:46:22] [PASSED] rounding2
[10:46:22] [PASSED] rounding3
[10:46:22] [PASSED] rounding4
[10:46:22] =========== [PASSED] drm_test_check_plane_state ============
[10:46:22] =========== drm_test_check_invalid_plane_state ============
[10:46:22] [PASSED] positioning_invalid
[10:46:22] [PASSED] upscaling_invalid
[10:46:22] [PASSED] downscaling_invalid
[10:46:22] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:46:22] ================ [PASSED] drm_plane_helper =================
[10:46:22] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:46:22] ====== drm_test_connector_helper_tv_get_modes_check =======
[10:46:22] [PASSED] None
[10:46:22] [PASSED] PAL
[10:46:22] [PASSED] NTSC
[10:46:22] [PASSED] Both, NTSC Default
[10:46:22] [PASSED] Both, PAL Default
[10:46:22] [PASSED] Both, NTSC Default, with PAL on command-line
[10:46:22] [PASSED] Both, PAL Default, with NTSC on command-line
[10:46:22] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:46:22] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:46:22] ================== drm_rect (9 subtests) ===================
[10:46:22] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:46:22] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:46:22] [PASSED] drm_test_rect_clip_scaled_clipped
[10:46:22] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:46:22] ================= drm_test_rect_intersect =================
[10:46:22] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:46:22] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:46:22] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:46:22] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:46:22] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:46:22] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:46:22] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:46:22] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:46:22] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:46:22] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:46:22] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:46:22] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:46:22] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:46:22] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:46:22] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:46:22] ============= [PASSED] drm_test_rect_intersect =============
[10:46:22] ================ drm_test_rect_calc_hscale ================
[10:46:22] [PASSED] normal use
[10:46:22] [PASSED] out of max range
[10:46:22] [PASSED] out of min range
[10:46:22] [PASSED] zero dst
[10:46:22] [PASSED] negative src
[10:46:22] [PASSED] negative dst
[10:46:22] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:46:22] ================ drm_test_rect_calc_vscale ================
[10:46:22] [PASSED] normal use
[10:46:22] [PASSED] out of max range
[10:46:22] [PASSED] out of min range
[10:46:22] [PASSED] zero dst
[10:46:22] [PASSED] negative src
[10:46:22] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[10:46:22] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:46:22] ================== drm_test_rect_rotate ===================
[10:46:22] [PASSED] reflect-x
[10:46:22] [PASSED] reflect-y
[10:46:22] [PASSED] rotate-0
[10:46:22] [PASSED] rotate-90
[10:46:22] [PASSED] rotate-180
[10:46:22] [PASSED] rotate-270
[10:46:22] ============== [PASSED] drm_test_rect_rotate ===============
[10:46:22] ================ drm_test_rect_rotate_inv =================
[10:46:22] [PASSED] reflect-x
[10:46:22] [PASSED] reflect-y
[10:46:22] [PASSED] rotate-0
[10:46:22] [PASSED] rotate-90
[10:46:22] [PASSED] rotate-180
[10:46:22] [PASSED] rotate-270
[10:46:22] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:46:22] ==================== [PASSED] drm_rect =====================
[10:46:22] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:46:22] ============ drm_test_sysfb_build_fourcc_list =============
[10:46:22] [PASSED] no native formats
[10:46:22] [PASSED] XRGB8888 as native format
[10:46:22] [PASSED] remove duplicates
[10:46:22] [PASSED] convert alpha formats
[10:46:22] [PASSED] random formats
[10:46:22] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:46:22] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:46:22] ================== drm_fixp (2 subtests) ===================
[10:46:22] [PASSED] drm_test_int2fixp
[10:46:22] [PASSED] drm_test_sm2fixp
[10:46:22] ==================== [PASSED] drm_fixp =====================
[10:46:22] ============================================================
[10:46:22] Testing complete. Ran 621 tests: passed: 621
[10:46:22] Elapsed time: 27.324s total, 1.683s configuring, 25.473s building, 0.166s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:46:22] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:46:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:46:33] Starting KUnit Kernel (1/1)...
[10:46:33] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:46:33] ================= ttm_device (5 subtests) ==================
[10:46:33] [PASSED] ttm_device_init_basic
[10:46:33] [PASSED] ttm_device_init_multiple
[10:46:33] [PASSED] ttm_device_fini_basic
[10:46:33] [PASSED] ttm_device_init_no_vma_man
[10:46:33] ================== ttm_device_init_pools ==================
[10:46:33] [PASSED] No DMA allocations, no DMA32 required
[10:46:33] [PASSED] DMA allocations, DMA32 required
[10:46:33] [PASSED] No DMA allocations, DMA32 required
[10:46:33] [PASSED] DMA allocations, no DMA32 required
[10:46:33] ============== [PASSED] ttm_device_init_pools ==============
[10:46:33] =================== [PASSED] ttm_device ====================
[10:46:33] ================== ttm_pool (8 subtests) ===================
[10:46:33] ================== ttm_pool_alloc_basic ===================
[10:46:33] [PASSED] One page
[10:46:33] [PASSED] More than one page
[10:46:33] [PASSED] Above the allocation limit
[10:46:33] [PASSED] One page, with coherent DMA mappings enabled
[10:46:33] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:46:33] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:46:33] ============== ttm_pool_alloc_basic_dma_addr ==============
[10:46:33] [PASSED] One page
[10:46:33] [PASSED] More than one page
[10:46:33] [PASSED] Above the allocation limit
[10:46:33] [PASSED] One page, with coherent DMA mappings enabled
[10:46:33] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:46:33] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:46:33] [PASSED] ttm_pool_alloc_order_caching_match
[10:46:33] [PASSED] ttm_pool_alloc_caching_mismatch
[10:46:33] [PASSED] ttm_pool_alloc_order_mismatch
[10:46:33] [PASSED] ttm_pool_free_dma_alloc
[10:46:33] [PASSED] ttm_pool_free_no_dma_alloc
[10:46:33] [PASSED] ttm_pool_fini_basic
[10:46:33] ==================== [PASSED] ttm_pool =====================
[10:46:33] ================ ttm_resource (8 subtests) =================
[10:46:33] ================= ttm_resource_init_basic =================
[10:46:33] [PASSED] Init resource in TTM_PL_SYSTEM
[10:46:33] [PASSED] Init resource in TTM_PL_VRAM
[10:46:33] [PASSED] Init resource in a private placement
[10:46:33] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:46:33] ============= [PASSED] ttm_resource_init_basic =============
[10:46:33] [PASSED] ttm_resource_init_pinned
[10:46:33] [PASSED] ttm_resource_fini_basic
[10:46:33] [PASSED] ttm_resource_manager_init_basic
[10:46:33] [PASSED] ttm_resource_manager_usage_basic
[10:46:33] [PASSED] ttm_resource_manager_set_used_basic
[10:46:33] [PASSED] ttm_sys_man_alloc_basic
[10:46:33] [PASSED] ttm_sys_man_free_basic
[10:46:33] ================== [PASSED] ttm_resource ===================
[10:46:33] =================== ttm_tt (15 subtests) ===================
[10:46:33] ==================== ttm_tt_init_basic ====================
[10:46:33] [PASSED] Page-aligned size
[10:46:33] [PASSED] Extra pages requested
[10:46:33] ================ [PASSED] ttm_tt_init_basic ================
[10:46:33] [PASSED] ttm_tt_init_misaligned
[10:46:33] [PASSED] ttm_tt_fini_basic
[10:46:33] [PASSED] ttm_tt_fini_sg
[10:46:33] [PASSED] ttm_tt_fini_shmem
[10:46:33] [PASSED] ttm_tt_create_basic
[10:46:33] [PASSED] ttm_tt_create_invalid_bo_type
[10:46:33] [PASSED] ttm_tt_create_ttm_exists
[10:46:33] [PASSED] ttm_tt_create_failed
[10:46:33] [PASSED] ttm_tt_destroy_basic
[10:46:33] [PASSED] ttm_tt_populate_null_ttm
[10:46:33] [PASSED] ttm_tt_populate_populated_ttm
[10:46:33] [PASSED] ttm_tt_unpopulate_basic
[10:46:33] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:46:33] [PASSED] ttm_tt_swapin_basic
[10:46:33] ===================== [PASSED] ttm_tt ======================
[10:46:33] =================== ttm_bo (14 subtests) ===================
[10:46:33] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[10:46:33] [PASSED] Cannot be interrupted and sleeps
[10:46:33] [PASSED] Cannot be interrupted, locks straight away
[10:46:33] [PASSED] Can be interrupted, sleeps
[10:46:33] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:46:33] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:46:33] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:46:33] [PASSED] ttm_bo_reserve_double_resv
[10:46:33] [PASSED] ttm_bo_reserve_interrupted
[10:46:33] [PASSED] ttm_bo_reserve_deadlock
[10:46:33] [PASSED] ttm_bo_unreserve_basic
[10:46:33] [PASSED] ttm_bo_unreserve_pinned
[10:46:33] [PASSED] ttm_bo_unreserve_bulk
[10:46:33] [PASSED] ttm_bo_fini_basic
[10:46:33] [PASSED] ttm_bo_fini_shared_resv
[10:46:33] [PASSED] ttm_bo_pin_basic
[10:46:33] [PASSED] ttm_bo_pin_unpin_resource
[10:46:33] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:46:33] ===================== [PASSED] ttm_bo ======================
[10:46:33] ============== ttm_bo_validate (21 subtests) ===============
[10:46:33] ============== ttm_bo_init_reserved_sys_man ===============
[10:46:33] [PASSED] Buffer object for userspace
[10:46:33] [PASSED] Kernel buffer object
[10:46:33] [PASSED] Shared buffer object
[10:46:33] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:46:33] ============== ttm_bo_init_reserved_mock_man ==============
[10:46:33] [PASSED] Buffer object for userspace
[10:46:33] [PASSED] Kernel buffer object
[10:46:33] [PASSED] Shared buffer object
[10:46:33] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:46:33] [PASSED] ttm_bo_init_reserved_resv
[10:46:33] ================== ttm_bo_validate_basic ==================
[10:46:33] [PASSED] Buffer object for userspace
[10:46:33] [PASSED] Kernel buffer object
[10:46:33] [PASSED] Shared buffer object
[10:46:33] ============== [PASSED] ttm_bo_validate_basic ==============
[10:46:33] [PASSED] ttm_bo_validate_invalid_placement
[10:46:33] ============= ttm_bo_validate_same_placement ==============
[10:46:33] [PASSED] System manager
[10:46:33] [PASSED] VRAM manager
[10:46:33] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:46:33] [PASSED] ttm_bo_validate_failed_alloc
[10:46:33] [PASSED] ttm_bo_validate_pinned
[10:46:33] [PASSED] ttm_bo_validate_busy_placement
[10:46:33] ================ ttm_bo_validate_multihop =================
[10:46:33] [PASSED] Buffer object for userspace
[10:46:33] [PASSED] Kernel buffer object
[10:46:33] [PASSED] Shared buffer object
[10:46:33] ============ [PASSED] ttm_bo_validate_multihop =============
[10:46:33] ========== ttm_bo_validate_no_placement_signaled ==========
[10:46:33] [PASSED] Buffer object in system domain, no page vector
[10:46:33] [PASSED] Buffer object in system domain with an existing page vector
[10:46:33] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:46:33] ======== ttm_bo_validate_no_placement_not_signaled ========
[10:46:33] [PASSED] Buffer object for userspace
[10:46:33] [PASSED] Kernel buffer object
[10:46:33] [PASSED] Shared buffer object
[10:46:33] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:46:33] [PASSED] ttm_bo_validate_move_fence_signaled
[10:46:33] ========= ttm_bo_validate_move_fence_not_signaled =========
[10:46:33] [PASSED] Waits for GPU
[10:46:33] [PASSED] Tries to lock straight away
[10:46:33] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:46:33] [PASSED] ttm_bo_validate_happy_evict
[10:46:33] [PASSED] ttm_bo_validate_all_pinned_evict
[10:46:33] [PASSED] ttm_bo_validate_allowed_only_evict
[10:46:33] [PASSED] ttm_bo_validate_deleted_evict
[10:46:33] [PASSED] ttm_bo_validate_busy_domain_evict
[10:46:33] [PASSED] ttm_bo_validate_evict_gutting
[10:46:33] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[10:46:33] ================= [PASSED] ttm_bo_validate =================
[10:46:33] ============================================================
[10:46:33] Testing complete. Ran 101 tests: passed: 101
[10:46:33] Elapsed time: 11.192s total, 1.619s configuring, 9.357s building, 0.179s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915/dp: On DPCD init/caps wake the DPRx
2026-02-19 9:43 [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx Arun R Murthy
2026-02-19 10:45 ` ✗ CI.checkpatch: warning for " Patchwork
2026-02-19 10:46 ` ✓ CI.KUnit: success " Patchwork
@ 2026-02-19 11:22 ` Patchwork
2026-02-19 14:20 ` ✗ Xe.CI.FULL: failure " Patchwork
` (7 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2026-02-19 11:22 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 867 bytes --]
== Series Details ==
Series: drm/i915/dp: On DPCD init/caps wake the DPRx
URL : https://patchwork.freedesktop.org/series/161817/
State : success
== Summary ==
CI Bug Log - changes from xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f_BAT -> xe-pw-161817v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (14 -> 14)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f -> xe-pw-161817v1
IGT_8761: 8761
xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f: c81e41f7aca96f583296a2a875f0179484b7a81f
xe-pw-161817v1: 161817v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/index.html
[-- Attachment #2: Type: text/html, Size: 1415 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ Xe.CI.FULL: failure for drm/i915/dp: On DPCD init/caps wake the DPRx
2026-02-19 9:43 [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx Arun R Murthy
` (2 preceding siblings ...)
2026-02-19 11:22 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-02-19 14:20 ` Patchwork
2026-02-19 14:53 ` [PATCH] " Ville Syrjälä
` (6 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2026-02-19 14:20 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 35935 bytes --]
== Series Details ==
Series: drm/i915/dp: On DPCD init/caps wake the DPRx
URL : https://patchwork.freedesktop.org/series/161817/
State : failure
== Summary ==
CI Bug Log - changes from xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f_FULL -> xe-pw-161817v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-161817v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-161817v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-161817v1_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping:
- shard-bmg: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping.html
* igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
- shard-lnl: NOTRUN -> [SKIP][2]
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-lnl-3/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html
Known issues
------------
Here are the changes found in xe-pw-161817v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@4-tiled-8bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][3] ([Intel XE#2327]) +1 other test skip
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
- shard-lnl: NOTRUN -> [SKIP][4] ([Intel XE#1124])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-lnl-3/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][5] ([Intel XE#1124]) +2 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-8/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
* igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p:
- shard-bmg: NOTRUN -> [SKIP][6] ([Intel XE#2314] / [Intel XE#2894])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html
* igt@kms_bw@linear-tiling-4-displays-2160x1440p:
- shard-bmg: NOTRUN -> [SKIP][7] ([Intel XE#367])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-8/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html
* igt@kms_ccs@bad-rotation-90-yf-tiled-ccs:
- shard-lnl: NOTRUN -> [SKIP][8] ([Intel XE#2887])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-lnl-3/igt@kms_ccs@bad-rotation-90-yf-tiled-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#2652] / [Intel XE#787]) +8 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html
* igt@kms_chamelium_hpd@common-hpd-after-hibernate:
- shard-bmg: NOTRUN -> [SKIP][10] ([Intel XE#2252]) +3 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@kms_chamelium_hpd@common-hpd-after-hibernate.html
* igt@kms_content_protection@legacy-hdcp14@pipe-a-dp-1:
- shard-bmg: NOTRUN -> [FAIL][11] ([Intel XE#3304])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-5/igt@kms_content_protection@legacy-hdcp14@pipe-a-dp-1.html
* igt@kms_content_protection@uevent-hdcp14@pipe-a-dp-1:
- shard-bmg: NOTRUN -> [FAIL][12] ([Intel XE#6707])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-5/igt@kms_content_protection@uevent-hdcp14@pipe-a-dp-1.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#2321]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-6/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#2286])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#2244])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-bmg: NOTRUN -> [SKIP][16] ([Intel XE#4156])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: [PASS][17] -> [FAIL][18] ([Intel XE#301]) +3 other tests fail
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#7178])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt:
- shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#4141]) +2 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#2311]) +10 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][22] ([Intel XE#656])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#2313]) +10 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_joiner@invalid-modeset-big-joiner:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#6901])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-8/igt@kms_joiner@invalid-modeset-big-joiner.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#6886]) +3 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-bmg: NOTRUN -> [SKIP][26] ([Intel XE#2391])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-8/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
- shard-lnl: NOTRUN -> [SKIP][28] ([Intel XE#1406] / [Intel XE#2893])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-lnl-3/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html
* igt@kms_psr@psr2-sprite-blt:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +6 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-6/igt@kms_psr@psr2-sprite-blt.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
- shard-lnl: NOTRUN -> [SKIP][30] ([Intel XE#3414] / [Intel XE#3904])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-lnl-3/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-bmg: NOTRUN -> [SKIP][31] ([Intel XE#2330])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
* igt@kms_vrr@cmrr@pipe-a-edp-1:
- shard-lnl: [PASS][32] -> [FAIL][33] ([Intel XE#4459]) +1 other test fail
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-lnl-8/igt@kms_vrr@cmrr@pipe-a-edp-1.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-lnl-6/igt@kms_vrr@cmrr@pipe-a-edp-1.html
* igt@xe_eudebug@basic-vm-access-parameters-userptr:
- shard-lnl: NOTRUN -> [SKIP][34] ([Intel XE#4837])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-lnl-3/igt@xe_eudebug@basic-vm-access-parameters-userptr.html
* igt@xe_eudebug@basic-vm-bind-metadata-discovery:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#4837]) +2 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html
* igt@xe_eudebug_online@pagefault-read-stress:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#6665] / [Intel XE#6681])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@xe_eudebug_online@pagefault-read-stress.html
* igt@xe_eudebug_sriov@deny-eudebug:
- shard-bmg: NOTRUN -> [SKIP][37] ([Intel XE#5793])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@xe_eudebug_sriov@deny-eudebug.html
* igt@xe_evict@evict-small-multi-queue-cm:
- shard-bmg: NOTRUN -> [SKIP][38] ([Intel XE#7140]) +1 other test skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@xe_evict@evict-small-multi-queue-cm.html
* igt@xe_evict@evict-small-multi-queue-priority-cm:
- shard-lnl: NOTRUN -> [SKIP][39] ([Intel XE#688])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-lnl-3/igt@xe_evict@evict-small-multi-queue-priority-cm.html
* igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap:
- shard-bmg: NOTRUN -> [SKIP][40] ([Intel XE#2322]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap.html
* igt@xe_exec_fault_mode@many-multi-queue-imm:
- shard-bmg: NOTRUN -> [SKIP][41] ([Intel XE#7136]) +5 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-8/igt@xe_exec_fault_mode@many-multi-queue-imm.html
* igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-dyn-priority:
- shard-lnl: NOTRUN -> [SKIP][42] ([Intel XE#6874])
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-lnl-3/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-dyn-priority.html
* igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-userptr:
- shard-bmg: NOTRUN -> [SKIP][43] ([Intel XE#6874]) +7 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-userptr.html
* igt@xe_exec_system_allocator@many-stride-new-prefetch:
- shard-bmg: NOTRUN -> [INCOMPLETE][44] ([Intel XE#7098])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@xe_exec_system_allocator@many-stride-new-prefetch.html
* igt@xe_exec_system_allocator@process-many-large-execqueues-new-busy-nomemset:
- shard-bmg: [PASS][45] -> [INCOMPLETE][46] ([Intel XE#2594])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-10/igt@xe_exec_system_allocator@process-many-large-execqueues-new-busy-nomemset.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-7/igt@xe_exec_system_allocator@process-many-large-execqueues-new-busy-nomemset.html
* igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr:
- shard-bmg: NOTRUN -> [SKIP][47] ([Intel XE#7138])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr.html
* igt@xe_multigpu_svm@mgpu-coherency-prefetch:
- shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#6964])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@xe_multigpu_svm@mgpu-coherency-prefetch.html
* igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq:
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#4733])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq.html
#### Possible fixes ####
* igt@kms_async_flips@alternate-sync-async-flip-atomic:
- shard-bmg: [FAIL][50] ([Intel XE#3718] / [Intel XE#6078]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-3/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-9/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
* igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-dp-2:
- shard-bmg: [FAIL][52] ([Intel XE#6078]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-3/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-dp-2.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-9/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-dp-2.html
* igt@kms_async_flips@test-time-stamp:
- shard-bmg: [INCOMPLETE][54] ([Intel XE#1727] / [Intel XE#4912] / [Intel XE#6819]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-3/igt@kms_async_flips@test-time-stamp.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@kms_async_flips@test-time-stamp.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-bmg: [INCOMPLETE][56] ([Intel XE#7084]) -> [PASS][57] +1 other test pass
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-bmg: [DMESG-WARN][58] ([Intel XE#5354]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-9/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-8/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-bmg: [INCOMPLETE][60] -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-10/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [SKIP][62] ([Intel XE#1503]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-4/igt@kms_hdr@invalid-hdr.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-7/igt@kms_hdr@invalid-hdr.html
* igt@xe_exec_system_allocator@many-stride-mmap-remap-eocheck:
- shard-bmg: [SKIP][64] ([Intel XE#6703]) -> [PASS][65] +80 other tests pass
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@xe_exec_system_allocator@many-stride-mmap-remap-eocheck.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@xe_exec_system_allocator@many-stride-mmap-remap-eocheck.html
* igt@xe_exec_system_allocator@once-large-malloc-race:
- shard-bmg: [DMESG-FAIL][66] ([Intel XE#5213] / [Intel XE#5545] / [Intel XE#6652]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@xe_exec_system_allocator@once-large-malloc-race.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@xe_exec_system_allocator@once-large-malloc-race.html
* igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma:
- shard-lnl: [FAIL][68] ([Intel XE#5625]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-lnl-2/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-lnl-1/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
#### Warnings ####
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-bmg: [SKIP][70] ([Intel XE#6703]) -> [SKIP][71] ([Intel XE#2370])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-bmg: [SKIP][72] ([Intel XE#6703]) -> [SKIP][73] ([Intel XE#2327])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-180:
- shard-bmg: [SKIP][74] ([Intel XE#6703]) -> [SKIP][75] ([Intel XE#1124])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-addfb:
- shard-bmg: [SKIP][76] ([Intel XE#6703]) -> [SKIP][77] ([Intel XE#2328]) +1 other test skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_big_fb@y-tiled-addfb.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_big_fb@y-tiled-addfb.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-rc-ccs-cc:
- shard-bmg: [SKIP][78] ([Intel XE#6703]) -> [SKIP][79] ([Intel XE#2887]) +1 other test skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-rc-ccs-cc.html
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_chamelium_color@ctm-negative:
- shard-bmg: [SKIP][80] ([Intel XE#6703]) -> [SKIP][81] ([Intel XE#2325])
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_chamelium_color@ctm-negative.html
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_cursor_crc@cursor-offscreen-256x85:
- shard-bmg: [SKIP][82] ([Intel XE#6703]) -> [SKIP][83] ([Intel XE#2320])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_cursor_crc@cursor-offscreen-256x85.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_cursor_crc@cursor-offscreen-256x85.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-bmg: [SKIP][84] ([Intel XE#6703]) -> [SKIP][85] ([Intel XE#2321])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_dsc@dsc-basic:
- shard-bmg: [SKIP][86] ([Intel XE#6703]) -> [SKIP][87] ([Intel XE#2244])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_dsc@dsc-basic.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_dsc@dsc-basic.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][88] ([Intel XE#6703]) -> [SKIP][89] ([Intel XE#4141])
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-fullscreen:
- shard-bmg: [SKIP][90] ([Intel XE#6703]) -> [SKIP][91] ([Intel XE#2311]) +1 other test skip
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-fullscreen.html
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-render:
- shard-bmg: [SKIP][92] ([Intel XE#6703]) -> [SKIP][93] ([Intel XE#7061]) +1 other test skip
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-render.html
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-bmg: [SKIP][94] ([Intel XE#6703]) -> [SKIP][95] ([Intel XE#2313])
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_joiner@basic-force-ultra-joiner:
- shard-bmg: [SKIP][96] ([Intel XE#6703]) -> [SKIP][97] ([Intel XE#6911])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_joiner@basic-force-ultra-joiner.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_joiner@basic-force-ultra-joiner.html
* igt@kms_plane_lowres@tiling-y:
- shard-bmg: [SKIP][98] ([Intel XE#6703]) -> [SKIP][99] ([Intel XE#2393])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_plane_lowres@tiling-y.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_plane_lowres@tiling-y.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75:
- shard-bmg: [SKIP][100] ([Intel XE#6703]) -> [SKIP][101] ([Intel XE#6886])
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
- shard-bmg: [SKIP][102] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][103] ([Intel XE#1406] / [Intel XE#1489])
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
* igt@kms_psr@pr-cursor-plane-move:
- shard-bmg: [SKIP][104] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][105] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@kms_psr@pr-cursor-plane-move.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@kms_psr@pr-cursor-plane-move.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][106] ([Intel XE#2426]) -> [SKIP][107] ([Intel XE#2509])
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@xe_eudebug@vm-bind-clear-faultable:
- shard-bmg: [SKIP][108] ([Intel XE#6703]) -> [SKIP][109] ([Intel XE#4837])
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@xe_eudebug@vm-bind-clear-faultable.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@xe_eudebug@vm-bind-clear-faultable.html
* igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-vram:
- shard-bmg: [SKIP][110] ([Intel XE#6703]) -> [SKIP][111] ([Intel XE#4837] / [Intel XE#6665])
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-vram.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-vram.html
* igt@xe_exec_basic@multigpu-once-basic-defer-bind:
- shard-bmg: [SKIP][112] ([Intel XE#6703]) -> [SKIP][113] ([Intel XE#2322]) +2 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html
* igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate:
- shard-bmg: [SKIP][114] ([Intel XE#6703]) -> [SKIP][115] ([Intel XE#7136])
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate.html
* igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-basic:
- shard-bmg: [SKIP][116] ([Intel XE#6703]) -> [SKIP][117] ([Intel XE#6874]) +4 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-basic.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-basic.html
* igt@xe_exec_threads@threads-multi-queue-fd-userptr:
- shard-bmg: [SKIP][118] ([Intel XE#6703]) -> [SKIP][119] ([Intel XE#7138])
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-fd-userptr.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-3/igt@xe_exec_threads@threads-multi-queue-fd-userptr.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-bmg: [ABORT][120] ([Intel XE#5466]) -> [ABORT][121] ([Intel XE#5466] / [Intel XE#6652])
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f/shard-bmg-3/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/shard-bmg-9/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
[Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
[Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
[Intel XE#2391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2391
[Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2594
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
[Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4912
[Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
[Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
[Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
[Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
[Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
[Intel XE#5793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5793
[Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
[Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
[Intel XE#6681]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6681
[Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
[Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
[Intel XE#6819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6819
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
[Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
[Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
[Intel XE#7098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7098
[Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
[Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
[Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
[Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
Build changes
-------------
* Linux: xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f -> xe-pw-161817v1
IGT_8761: 8761
xe-4575-c81e41f7aca96f583296a2a875f0179484b7a81f: c81e41f7aca96f583296a2a875f0179484b7a81f
xe-pw-161817v1: 161817v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v1/index.html
[-- Attachment #2: Type: text/html, Size: 42137 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx
2026-02-19 9:43 [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx Arun R Murthy
` (3 preceding siblings ...)
2026-02-19 14:20 ` ✗ Xe.CI.FULL: failure " Patchwork
@ 2026-02-19 14:53 ` Ville Syrjälä
2026-02-19 15:12 ` Murthy, Arun R
2026-02-24 7:48 ` [PATCHv2] " Arun R Murthy
` (5 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2026-02-19 14:53 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-gfx, intel-xe, imre.deak, suraj.kandpal
On Thu, Feb 19, 2026 at 03:13:26PM +0530, Arun R Murthy wrote:
> Before reading the DPCD caps for eDP wake the sink device and for DP
> after reading the lttpr caps and before reading the dpcd caps wake up
> the sink device.
Why?
>
> Closes: https://issues.redhat.com/browse/RHEL-120913
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> .../drm/i915/display/intel_dp_link_training.c | 3 ++
> 3 files changed, 45 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 454e6144ee4e..2fbb947e6cc8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4705,6 +4705,45 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
> intel_edp_set_data_override_rates(intel_dp);
> }
>
> +void intel_dp_wake_sink(struct intel_dp *intel_dp)
> +{
> + u8 value = 0;
> + int ret = 0, try = 0;
> +
> + intel_dp_dpcd_set_probe(intel_dp, false);
> +
> + /*
> + * Wake the sink device
> + * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by writing 0x02
> + * to DP_SET_POWER dpcd reg, 1ms time would be required to wake it up
> + */
> + while (try < 10 && ret < 0) {
> + ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value);
> + /*
> + * If sink is in D3 then it may not respond to the AUX tx so
> + * wake it up to D3_AUX_ON state
> + */
> + if (value == DP_SET_POWER_D3) {
> + /* After setting to D0 need a min of 1ms to wake(Spec DP2.1 sec 2.3.1.2) */
> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> + DP_SET_POWER_D0);
> + fsleep(1000);
> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> + DP_SET_POWER_D3_AUX_ON);
> + break;
> + } else if ((value == DP_SET_POWER_D0) ||
> + (value == DP_SET_POWER_D3_AUX_ON)) {
> + /* if in D0 or D3_AUX_ON exit */
> + break;
> + }
> + /* Sink in D0 or even if read fails a minimum of 1ms is required to wake and respond */
> + fsleep(1000);
> + try++;
> + }
> +
> + intel_dp_dpcd_set_probe(intel_dp, true);
> +}
> +
> static bool
> intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
> {
> @@ -4713,6 +4752,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
> /* this function is meant to be called only once */
> drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
>
> + intel_dp_wake_sink(intel_dp);
> +
> if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
> return false;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index b0bbd5981f57..3f16077c0cc7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
> bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
> int hdisplay,
> int num_joined_pipes);
> +void intel_dp_wake_sink(struct intel_dp *intel_dp);
>
> #define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
> for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 54c585c59b90..cbb712ea9f60 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -270,6 +270,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
> lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
> }
>
> + /* After reading LTTPR wake up the sink before reading DPRX caps */
> + intel_dp_wake_sink(intel_dp);
> +
> /*
> * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
> * it here.
> --
> 2.25.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx
2026-02-19 14:53 ` [PATCH] " Ville Syrjälä
@ 2026-02-19 15:12 ` Murthy, Arun R
2026-02-20 3:11 ` Ville Syrjälä
0 siblings, 1 reply; 24+ messages in thread
From: Murthy, Arun R @ 2026-02-19 15:12 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe, imre.deak, suraj.kandpal
On 19-02-2026 20:23, Ville Syrjälä wrote:
> On Thu, Feb 19, 2026 at 03:13:26PM +0530, Arun R Murthy wrote:
>> Before reading the DPCD caps for eDP wake the sink device and for DP
>> after reading the lttpr caps and before reading the dpcd caps wake up
>> the sink device.
> Why?
Just to ensure that sink is awake.
On eDP init, as part of reading the DPCD caps during the AUX transaction
its sometimes observed that the AUX tx fails with timeout. In those
scenarios even if the retry is increased to 1000 AUX tx will not
succeed. May be that sink is in sleep or unknown state.
Spec DP2.1 sec 2.11.7.1.5.8 says if there is a NO REPLY for AUX tx this
can be due to illegal cmd or sink in low power state.
So in this patch we are trying to wake the sink device.
Thanks and Regards,
Arun R Murthy
-------------------
>
>> Closes: https://issues.redhat.com/browse/RHEL-120913
>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++++++
>> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
>> .../drm/i915/display/intel_dp_link_training.c | 3 ++
>> 3 files changed, 45 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 454e6144ee4e..2fbb947e6cc8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -4705,6 +4705,45 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
>> intel_edp_set_data_override_rates(intel_dp);
>> }
>>
>> +void intel_dp_wake_sink(struct intel_dp *intel_dp)
>> +{
>> + u8 value = 0;
>> + int ret = 0, try = 0;
>> +
>> + intel_dp_dpcd_set_probe(intel_dp, false);
>> +
>> + /*
>> + * Wake the sink device
>> + * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by writing 0x02
>> + * to DP_SET_POWER dpcd reg, 1ms time would be required to wake it up
>> + */
>> + while (try < 10 && ret < 0) {
>> + ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value);
>> + /*
>> + * If sink is in D3 then it may not respond to the AUX tx so
>> + * wake it up to D3_AUX_ON state
>> + */
>> + if (value == DP_SET_POWER_D3) {
>> + /* After setting to D0 need a min of 1ms to wake(Spec DP2.1 sec 2.3.1.2) */
>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>> + DP_SET_POWER_D0);
>> + fsleep(1000);
>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>> + DP_SET_POWER_D3_AUX_ON);
>> + break;
>> + } else if ((value == DP_SET_POWER_D0) ||
>> + (value == DP_SET_POWER_D3_AUX_ON)) {
>> + /* if in D0 or D3_AUX_ON exit */
>> + break;
>> + }
>> + /* Sink in D0 or even if read fails a minimum of 1ms is required to wake and respond */
>> + fsleep(1000);
>> + try++;
>> + }
>> +
>> + intel_dp_dpcd_set_probe(intel_dp, true);
>> +}
>> +
>> static bool
>> intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
>> {
>> @@ -4713,6 +4752,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
>> /* this function is meant to be called only once */
>> drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
>>
>> + intel_dp_wake_sink(intel_dp);
>> +
>> if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
>> return false;
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index b0bbd5981f57..3f16077c0cc7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
>> bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>> int hdisplay,
>> int num_joined_pipes);
>> +void intel_dp_wake_sink(struct intel_dp *intel_dp);
>>
>> #define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
>> for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index 54c585c59b90..cbb712ea9f60 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -270,6 +270,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
>> lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
>> }
>>
>> + /* After reading LTTPR wake up the sink before reading DPRX caps */
>> + intel_dp_wake_sink(intel_dp);
>> +
>> /*
>> * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
>> * it here.
>> --
>> 2.25.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx
2026-02-19 15:12 ` Murthy, Arun R
@ 2026-02-20 3:11 ` Ville Syrjälä
2026-02-20 5:01 ` Murthy, Arun R
0 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2026-02-20 3:11 UTC (permalink / raw)
To: Murthy, Arun R; +Cc: intel-gfx, intel-xe, imre.deak, suraj.kandpal
On Thu, Feb 19, 2026 at 08:42:49PM +0530, Murthy, Arun R wrote:
>
> On 19-02-2026 20:23, Ville Syrjälä wrote:
> > On Thu, Feb 19, 2026 at 03:13:26PM +0530, Arun R Murthy wrote:
> >> Before reading the DPCD caps for eDP wake the sink device and for DP
> >> after reading the lttpr caps and before reading the dpcd caps wake up
> >> the sink device.
> > Why?
> Just to ensure that sink is awake.
> On eDP init, as part of reading the DPCD caps during the AUX transaction
> its sometimes observed that the AUX tx fails with timeout. In those
> scenarios even if the retry is increased to 1000 AUX tx will not
> succeed. May be that sink is in sleep or unknown state.
> Spec DP2.1 sec 2.11.7.1.5.8 says if there is a NO REPLY for AUX tx this
> can be due to illegal cmd or sink in low power state.
That section is specifically about i2c-over-aux.
Generally we have retries and appropriate timeouts to deal with AUX
having to wake up from low power state.
Although, I suppose we might consider switching to D0 for eg. duration
of the detection to make sure none of the AUX transactions there take
too long. That *might* make things a bit faster (but we'd need actual
numbers to show that). And once we're done we should switch back to D3
to save power. Perhaps we could then also use a larger timeout just for
the DP_SET_POWER AUX accesses, and all other AUX accesses could assume
that the thing is awake and use a smaller timeout. Although the LTTPR
mess probably means we can't actually reduce the timeouts :/
Another slight snag in the current way of doing things is that IIRC
we never put a device into D3 after the initial detection, unless we
actually turned the main link on and off again. That's also something
that could get fixed by always putting the device into D3 after
detection. But to do that stuff safely we'd need some way to make sure
nothing else (eg. the main link) requires the D0 at that time. So some
kind of D0 vs. D3 reference counting scheme might be needed.
I did consider implementing something like that years ago, but dealing
with the reference counting seemed too messy at the time. And since I
never implemented it I never measured it either. Perhaps things are a
bit cleaner these days to make that easier. Dunno.
>
> So in this patch we are trying to wake the sink device.
Still the same question remains: Why? What *exactly* is the problem
you're trying to solve here?
>
> Thanks and Regards,
> Arun R Murthy
> -------------------
>
> >
> >> Closes: https://issues.redhat.com/browse/RHEL-120913
> >> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++++++
> >> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> >> .../drm/i915/display/intel_dp_link_training.c | 3 ++
> >> 3 files changed, 45 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> >> index 454e6144ee4e..2fbb947e6cc8 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> @@ -4705,6 +4705,45 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
> >> intel_edp_set_data_override_rates(intel_dp);
> >> }
> >>
> >> +void intel_dp_wake_sink(struct intel_dp *intel_dp)
> >> +{
> >> + u8 value = 0;
> >> + int ret = 0, try = 0;
> >> +
> >> + intel_dp_dpcd_set_probe(intel_dp, false);
> >> +
> >> + /*
> >> + * Wake the sink device
> >> + * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by writing 0x02
> >> + * to DP_SET_POWER dpcd reg, 1ms time would be required to wake it up
> >> + */
> >> + while (try < 10 && ret < 0) {
> >> + ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value);
> >> + /*
> >> + * If sink is in D3 then it may not respond to the AUX tx so
> >> + * wake it up to D3_AUX_ON state
> >> + */
> >> + if (value == DP_SET_POWER_D3) {
> >> + /* After setting to D0 need a min of 1ms to wake(Spec DP2.1 sec 2.3.1.2) */
> >> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> >> + DP_SET_POWER_D0);
> >> + fsleep(1000);
> >> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> >> + DP_SET_POWER_D3_AUX_ON);
> >> + break;
> >> + } else if ((value == DP_SET_POWER_D0) ||
> >> + (value == DP_SET_POWER_D3_AUX_ON)) {
> >> + /* if in D0 or D3_AUX_ON exit */
> >> + break;
> >> + }
> >> + /* Sink in D0 or even if read fails a minimum of 1ms is required to wake and respond */
> >> + fsleep(1000);
> >> + try++;
> >> + }
> >> +
> >> + intel_dp_dpcd_set_probe(intel_dp, true);
> >> +}
> >> +
> >> static bool
> >> intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
> >> {
> >> @@ -4713,6 +4752,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
> >> /* this function is meant to be called only once */
> >> drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
> >>
> >> + intel_dp_wake_sink(intel_dp);
> >> +
> >> if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
> >> return false;
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> >> index b0bbd5981f57..3f16077c0cc7 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> >> @@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
> >> bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
> >> int hdisplay,
> >> int num_joined_pipes);
> >> +void intel_dp_wake_sink(struct intel_dp *intel_dp);
> >>
> >> #define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
> >> for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> index 54c585c59b90..cbb712ea9f60 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> @@ -270,6 +270,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
> >> lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
> >> }
> >>
> >> + /* After reading LTTPR wake up the sink before reading DPRX caps */
> >> + intel_dp_wake_sink(intel_dp);
> >> +
> >> /*
> >> * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
> >> * it here.
> >> --
> >> 2.25.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx
2026-02-20 3:11 ` Ville Syrjälä
@ 2026-02-20 5:01 ` Murthy, Arun R
2026-02-24 8:24 ` Ville Syrjälä
0 siblings, 1 reply; 24+ messages in thread
From: Murthy, Arun R @ 2026-02-20 5:01 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe, imre.deak, suraj.kandpal
On 20-02-2026 08:41, Ville Syrjälä wrote:
> On Thu, Feb 19, 2026 at 08:42:49PM +0530, Murthy, Arun R wrote:
>> On 19-02-2026 20:23, Ville Syrjälä wrote:
>>> On Thu, Feb 19, 2026 at 03:13:26PM +0530, Arun R Murthy wrote:
>>>> Before reading the DPCD caps for eDP wake the sink device and for DP
>>>> after reading the lttpr caps and before reading the dpcd caps wake up
>>>> the sink device.
>>> Why?
>> Just to ensure that sink is awake.
>> On eDP init, as part of reading the DPCD caps during the AUX transaction
>> its sometimes observed that the AUX tx fails with timeout. In those
>> scenarios even if the retry is increased to 1000 AUX tx will not
>> succeed. May be that sink is in sleep or unknown state.
>> Spec DP2.1 sec 2.11.7.1.5.8 says if there is a NO REPLY for AUX tx this
>> can be due to illegal cmd or sink in low power state.
> That section is specifically about i2c-over-aux.
>
> Generally we have retries and appropriate timeouts to deal with AUX
> having to wake up from low power state.
We have tried this for 1000 times and didnt work.
This leaves a question as to why not replying even after 1000 trials.
Answer might be the command/request is wrong for which sink is not able
to understand. But its not the case.
So the other thinking is "is the sink in low power mode" ?
In link training sections of the spec it says before starting link
training ensure that sink is up and provides steps to wake the sink device.
Example: Section 3.5.2.16
> Although, I suppose we might consider switching to D0 for eg. duration
> of the detection to make sure none of the AUX transactions there take
> too long. That *might* make things a bit faster (but we'd need actual
> numbers to show that). And once we're done we should switch back to D3
> to save power.
I am doing that in the patch. I switch to D0 and then immediately switch
to D3_AUX_ON state.
The reason for reading DP_SET_POWER in a loop is the spec says that DPTX
should try for atleast 3 times as DPRX is waking from power saving state
which takes 1ms.
Section 2.3.5 explains the DPRX AUX_CH state and says that DPRX shall
avoid not issuing a reply when waking from a power saving state.
This section also explains the DPRX AUX_CH state on RESET. Usually this
is the state on power on, and in the issue that we are referring to can
also be co-related to this state as its during the kernel boot/driver
probe.
> Perhaps we could then also use a larger timeout just for
> the DP_SET_POWER AUX accesses,
spec mention on this time as 1ms, to allow sink to exit low power mode
or AUX_CH Receiver is monitoring differential signals (sec 2.3.1.2)
> and all other AUX accesses could assume
> that the thing is awake and use a smaller timeout. Although the LTTPR
> mess probably means we can't actually reduce the timeouts :/
>
> Another slight snag in the current way of doing things is that IIRC
> we never put a device into D3 after the initial detection, unless we
> actually turned the main link on and off again. That's also something
> that could get fixed by always putting the device into D3 after
> detection. But to do that stuff safely we'd need some way to make sure
> nothing else (eg. the main link) requires the D0 at that time. So some
> kind of D0 vs. D3 reference counting scheme might be needed.
>
> I did consider implementing something like that years ago, but dealing
> with the reference counting seemed too messy at the time. And since I
> never implemented it I never measured it either. Perhaps things are a
> bit cleaner these days to make that easier. Dunno.
>
>> So in this patch we are trying to wake the sink device.
> Still the same question remains: Why? What *exactly* is the problem
> you're trying to solve here?
The problem we are trying to solve is that the AUX_CH Requested is not
succeeding even after sending multiple AUX requests and fails to get a
response from the AUX_CH Replier.
Increasing the retry count to a large value (1000) is also not helping.
In order to solve this went through the spec in detail, able to get some
information scattered over multiple sections leaving us to a thinking
that may be AUX_CH Replier in low power state. Also in link training
section(3.5.2.16) it says source should wake the sink before starting
link training.
Thanks and Regards,
Arun R Murthy
-------------------
>> Thanks and Regards,
>> Arun R Murthy
>> -------------------
>>
>>>> Closes: https://issues.redhat.com/browse/RHEL-120913
>>>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++++++
>>>> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
>>>> .../drm/i915/display/intel_dp_link_training.c | 3 ++
>>>> 3 files changed, 45 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> index 454e6144ee4e..2fbb947e6cc8 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> @@ -4705,6 +4705,45 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
>>>> intel_edp_set_data_override_rates(intel_dp);
>>>> }
>>>>
>>>> +void intel_dp_wake_sink(struct intel_dp *intel_dp)
>>>> +{
>>>> + u8 value = 0;
>>>> + int ret = 0, try = 0;
>>>> +
>>>> + intel_dp_dpcd_set_probe(intel_dp, false);
>>>> +
>>>> + /*
>>>> + * Wake the sink device
>>>> + * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by writing 0x02
>>>> + * to DP_SET_POWER dpcd reg, 1ms time would be required to wake it up
>>>> + */
>>>> + while (try < 10 && ret < 0) {
>>>> + ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value);
>>>> + /*
>>>> + * If sink is in D3 then it may not respond to the AUX tx so
>>>> + * wake it up to D3_AUX_ON state
>>>> + */
>>>> + if (value == DP_SET_POWER_D3) {
>>>> + /* After setting to D0 need a min of 1ms to wake(Spec DP2.1 sec 2.3.1.2) */
>>>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>>>> + DP_SET_POWER_D0);
>>>> + fsleep(1000);
>>>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>>>> + DP_SET_POWER_D3_AUX_ON);
>>>> + break;
>>>> + } else if ((value == DP_SET_POWER_D0) ||
>>>> + (value == DP_SET_POWER_D3_AUX_ON)) {
>>>> + /* if in D0 or D3_AUX_ON exit */
>>>> + break;
>>>> + }
>>>> + /* Sink in D0 or even if read fails a minimum of 1ms is required to wake and respond */
>>>> + fsleep(1000);
>>>> + try++;
>>>> + }
>>>> +
>>>> + intel_dp_dpcd_set_probe(intel_dp, true);
>>>> +}
>>>> +
>>>> static bool
>>>> intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
>>>> {
>>>> @@ -4713,6 +4752,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
>>>> /* this function is meant to be called only once */
>>>> drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
>>>>
>>>> + intel_dp_wake_sink(intel_dp);
>>>> +
>>>> if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
>>>> return false;
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>>>> index b0bbd5981f57..3f16077c0cc7 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>>>> @@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
>>>> bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>>>> int hdisplay,
>>>> int num_joined_pipes);
>>>> +void intel_dp_wake_sink(struct intel_dp *intel_dp);
>>>>
>>>> #define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
>>>> for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>>> index 54c585c59b90..cbb712ea9f60 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>>> @@ -270,6 +270,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
>>>> lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
>>>> }
>>>>
>>>> + /* After reading LTTPR wake up the sink before reading DPRX caps */
>>>> + intel_dp_wake_sink(intel_dp);
>>>> +
>>>> /*
>>>> * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
>>>> * it here.
>>>> --
>>>> 2.25.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCHv2] drm/i915/dp: On DPCD init/caps wake the DPRx
2026-02-19 9:43 [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx Arun R Murthy
` (4 preceding siblings ...)
2026-02-19 14:53 ` [PATCH] " Ville Syrjälä
@ 2026-02-24 7:48 ` Arun R Murthy
2026-02-24 14:50 ` Imre Deak
2026-02-24 7:56 ` ✓ CI.KUnit: success for drm/i915/dp: On DPCD init/caps wake the DPRx (rev2) Patchwork
` (4 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Arun R Murthy @ 2026-02-24 7:48 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: imre.deak, suraj.kandpal, jani.nikula, ville.syrjala,
Arun R Murthy
Its observed that on AUX_CH failure, even if the retry is increased to
1000, it does not succeed. Either the command might be wrong or sink in
an unknown/sleep state can cause this. So try waking the sink device.
Before reading the DPCD caps wake the sink for eDP and for DP after
reading the lttpr caps if present and before reading the dpcd caps wake
up the sink device.
v2: Use poll_timeout_us (Jani N)
Add the reason, why this change is required (Ville)
Closes: https://issues.redhat.com/browse/RHEL-120913
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 38 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
.../drm/i915/display/intel_dp_link_training.c | 3 ++
3 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 025e906b63a9..fa0730f7b92a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4705,6 +4705,42 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
intel_edp_set_data_override_rates(intel_dp);
}
+/* Spec says to try for 3 times, its doubled to add the software overhead */
+#define AUX_CH_WAKE_RETRY 6
+
+void intel_dp_wake_sink(struct intel_dp *intel_dp)
+{
+ u8 value = 0;
+ int ret = 0;
+
+ intel_dp_dpcd_set_probe(intel_dp, false);
+
+ /*
+ * Wake the sink device
+ * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by writing 0x02
+ * to DP_SET_POWER dpcd reg, 1ms time would be required to wake it up
+ */
+ ret = poll_timeout_us(ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value),
+ ret > 0,
+ 1000, AUX_CH_WAKE_RETRY * 1000, true);
+
+ /*
+ * If sink is in D3 then it may not respond to the AUX tx so
+ * wake it up to D3_AUX_ON state
+ * If the above poll_timeout_us fails, try waking the sink.
+ */
+ if (value == DP_SET_POWER_D3 || ret < 0) {
+ /* After setting to D0 need a min of 1ms to wake(Spec DP2.1 sec 2.3.1.2) */
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
+ DP_SET_POWER_D0);
+ fsleep(1000);
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
+ DP_SET_POWER_D3_AUX_ON);
+ }
+
+ intel_dp_dpcd_set_probe(intel_dp, true);
+}
+
static bool
intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
{
@@ -4713,6 +4749,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
/* this function is meant to be called only once */
drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
+ intel_dp_wake_sink(intel_dp);
+
if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
return false;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index b0bbd5981f57..3f16077c0cc7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
int hdisplay,
int num_joined_pipes);
+void intel_dp_wake_sink(struct intel_dp *intel_dp);
#define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 54c585c59b90..cbb712ea9f60 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -270,6 +270,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
}
+ /* After reading LTTPR wake up the sink before reading DPRX caps */
+ intel_dp_wake_sink(intel_dp);
+
/*
* The DPTX shall read the DPRX caps after LTTPR detection, so re-read
* it here.
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* ✓ CI.KUnit: success for drm/i915/dp: On DPCD init/caps wake the DPRx (rev2)
2026-02-19 9:43 [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx Arun R Murthy
` (5 preceding siblings ...)
2026-02-24 7:48 ` [PATCHv2] " Arun R Murthy
@ 2026-02-24 7:56 ` Patchwork
2026-02-25 6:11 ` [PATCHv3] drm/i915/dp: On DPCD init wake the DPRx for eDP Arun R Murthy
` (3 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2026-02-24 7:56 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-xe
== Series Details ==
Series: drm/i915/dp: On DPCD init/caps wake the DPRx (rev2)
URL : https://patchwork.freedesktop.org/series/161817/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[07:55:06] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:55:10] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:55:40] Starting KUnit Kernel (1/1)...
[07:55:40] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:55:41] ================== guc_buf (11 subtests) ===================
[07:55:41] [PASSED] test_smallest
[07:55:41] [PASSED] test_largest
[07:55:41] [PASSED] test_granular
[07:55:41] [PASSED] test_unique
[07:55:41] [PASSED] test_overlap
[07:55:41] [PASSED] test_reusable
[07:55:41] [PASSED] test_too_big
[07:55:41] [PASSED] test_flush
[07:55:41] [PASSED] test_lookup
[07:55:41] [PASSED] test_data
[07:55:41] [PASSED] test_class
[07:55:41] ===================== [PASSED] guc_buf =====================
[07:55:41] =================== guc_dbm (7 subtests) ===================
[07:55:41] [PASSED] test_empty
[07:55:41] [PASSED] test_default
[07:55:41] ======================== test_size ========================
[07:55:41] [PASSED] 4
[07:55:41] [PASSED] 8
[07:55:41] [PASSED] 32
[07:55:41] [PASSED] 256
[07:55:41] ==================== [PASSED] test_size ====================
[07:55:41] ======================= test_reuse ========================
[07:55:41] [PASSED] 4
[07:55:41] [PASSED] 8
[07:55:41] [PASSED] 32
[07:55:41] [PASSED] 256
[07:55:41] =================== [PASSED] test_reuse ====================
[07:55:41] =================== test_range_overlap ====================
[07:55:41] [PASSED] 4
[07:55:41] [PASSED] 8
[07:55:41] [PASSED] 32
[07:55:41] [PASSED] 256
[07:55:41] =============== [PASSED] test_range_overlap ================
[07:55:41] =================== test_range_compact ====================
[07:55:41] [PASSED] 4
[07:55:41] [PASSED] 8
[07:55:41] [PASSED] 32
[07:55:41] [PASSED] 256
[07:55:41] =============== [PASSED] test_range_compact ================
[07:55:41] ==================== test_range_spare =====================
[07:55:41] [PASSED] 4
[07:55:41] [PASSED] 8
[07:55:41] [PASSED] 32
[07:55:41] [PASSED] 256
[07:55:41] ================ [PASSED] test_range_spare =================
[07:55:41] ===================== [PASSED] guc_dbm =====================
[07:55:41] =================== guc_idm (6 subtests) ===================
[07:55:41] [PASSED] bad_init
[07:55:41] [PASSED] no_init
[07:55:41] [PASSED] init_fini
[07:55:41] [PASSED] check_used
[07:55:41] [PASSED] check_quota
[07:55:41] [PASSED] check_all
[07:55:41] ===================== [PASSED] guc_idm =====================
[07:55:41] ================== no_relay (3 subtests) ===================
[07:55:41] [PASSED] xe_drops_guc2pf_if_not_ready
[07:55:41] [PASSED] xe_drops_guc2vf_if_not_ready
[07:55:41] [PASSED] xe_rejects_send_if_not_ready
[07:55:41] ==================== [PASSED] no_relay =====================
[07:55:41] ================== pf_relay (14 subtests) ==================
[07:55:41] [PASSED] pf_rejects_guc2pf_too_short
[07:55:41] [PASSED] pf_rejects_guc2pf_too_long
[07:55:41] [PASSED] pf_rejects_guc2pf_no_payload
[07:55:41] [PASSED] pf_fails_no_payload
[07:55:41] [PASSED] pf_fails_bad_origin
[07:55:41] [PASSED] pf_fails_bad_type
[07:55:41] [PASSED] pf_txn_reports_error
[07:55:41] [PASSED] pf_txn_sends_pf2guc
[07:55:41] [PASSED] pf_sends_pf2guc
[07:55:41] [SKIPPED] pf_loopback_nop
[07:55:41] [SKIPPED] pf_loopback_echo
[07:55:41] [SKIPPED] pf_loopback_fail
[07:55:41] [SKIPPED] pf_loopback_busy
[07:55:41] [SKIPPED] pf_loopback_retry
[07:55:41] ==================== [PASSED] pf_relay =====================
[07:55:41] ================== vf_relay (3 subtests) ===================
[07:55:41] [PASSED] vf_rejects_guc2vf_too_short
[07:55:41] [PASSED] vf_rejects_guc2vf_too_long
[07:55:41] [PASSED] vf_rejects_guc2vf_no_payload
[07:55:41] ==================== [PASSED] vf_relay =====================
[07:55:41] ================ pf_gt_config (9 subtests) =================
[07:55:41] [PASSED] fair_contexts_1vf
[07:55:41] [PASSED] fair_doorbells_1vf
[07:55:41] [PASSED] fair_ggtt_1vf
[07:55:41] ====================== fair_vram_1vf ======================
[07:55:41] [PASSED] 3.50 GiB
[07:55:41] [PASSED] 11.5 GiB
[07:55:41] [PASSED] 15.5 GiB
[07:55:41] [PASSED] 31.5 GiB
[07:55:41] [PASSED] 63.5 GiB
[07:55:41] [PASSED] 13.9 GiB
[07:55:41] ================== [PASSED] fair_vram_1vf ==================
[07:55:41] ================ fair_vram_1vf_admin_only =================
[07:55:41] [PASSED] 3.50 GiB
[07:55:41] [PASSED] 11.5 GiB
[07:55:41] [PASSED] 15.5 GiB
[07:55:41] [PASSED] 31.5 GiB
[07:55:41] [PASSED] 63.5 GiB
[07:55:41] [PASSED] 13.9 GiB
[07:55:41] ============ [PASSED] fair_vram_1vf_admin_only =============
[07:55:41] ====================== fair_contexts ======================
[07:55:41] [PASSED] 1 VF
[07:55:41] [PASSED] 2 VFs
[07:55:41] [PASSED] 3 VFs
[07:55:41] [PASSED] 4 VFs
[07:55:41] [PASSED] 5 VFs
[07:55:41] [PASSED] 6 VFs
[07:55:41] [PASSED] 7 VFs
[07:55:41] [PASSED] 8 VFs
[07:55:41] [PASSED] 9 VFs
[07:55:41] [PASSED] 10 VFs
[07:55:41] [PASSED] 11 VFs
[07:55:41] [PASSED] 12 VFs
[07:55:41] [PASSED] 13 VFs
[07:55:41] [PASSED] 14 VFs
[07:55:41] [PASSED] 15 VFs
[07:55:41] [PASSED] 16 VFs
[07:55:41] [PASSED] 17 VFs
[07:55:41] [PASSED] 18 VFs
[07:55:41] [PASSED] 19 VFs
[07:55:41] [PASSED] 20 VFs
[07:55:41] [PASSED] 21 VFs
[07:55:41] [PASSED] 22 VFs
[07:55:41] [PASSED] 23 VFs
[07:55:41] [PASSED] 24 VFs
[07:55:41] [PASSED] 25 VFs
[07:55:41] [PASSED] 26 VFs
[07:55:41] [PASSED] 27 VFs
[07:55:41] [PASSED] 28 VFs
[07:55:41] [PASSED] 29 VFs
[07:55:41] [PASSED] 30 VFs
[07:55:41] [PASSED] 31 VFs
[07:55:41] [PASSED] 32 VFs
[07:55:41] [PASSED] 33 VFs
[07:55:41] [PASSED] 34 VFs
[07:55:41] [PASSED] 35 VFs
[07:55:41] [PASSED] 36 VFs
[07:55:41] [PASSED] 37 VFs
[07:55:41] [PASSED] 38 VFs
[07:55:41] [PASSED] 39 VFs
[07:55:41] [PASSED] 40 VFs
[07:55:41] [PASSED] 41 VFs
[07:55:41] [PASSED] 42 VFs
[07:55:41] [PASSED] 43 VFs
[07:55:41] [PASSED] 44 VFs
[07:55:41] [PASSED] 45 VFs
[07:55:41] [PASSED] 46 VFs
[07:55:41] [PASSED] 47 VFs
[07:55:41] [PASSED] 48 VFs
[07:55:41] [PASSED] 49 VFs
[07:55:41] [PASSED] 50 VFs
[07:55:41] [PASSED] 51 VFs
[07:55:41] [PASSED] 52 VFs
[07:55:41] [PASSED] 53 VFs
[07:55:41] [PASSED] 54 VFs
[07:55:41] [PASSED] 55 VFs
[07:55:41] [PASSED] 56 VFs
[07:55:41] [PASSED] 57 VFs
[07:55:41] [PASSED] 58 VFs
[07:55:41] [PASSED] 59 VFs
[07:55:41] [PASSED] 60 VFs
[07:55:41] [PASSED] 61 VFs
[07:55:41] [PASSED] 62 VFs
[07:55:41] [PASSED] 63 VFs
[07:55:41] ================== [PASSED] fair_contexts ==================
[07:55:41] ===================== fair_doorbells ======================
[07:55:41] [PASSED] 1 VF
[07:55:41] [PASSED] 2 VFs
[07:55:41] [PASSED] 3 VFs
[07:55:41] [PASSED] 4 VFs
[07:55:41] [PASSED] 5 VFs
[07:55:41] [PASSED] 6 VFs
[07:55:41] [PASSED] 7 VFs
[07:55:41] [PASSED] 8 VFs
[07:55:41] [PASSED] 9 VFs
[07:55:41] [PASSED] 10 VFs
[07:55:41] [PASSED] 11 VFs
[07:55:41] [PASSED] 12 VFs
[07:55:41] [PASSED] 13 VFs
[07:55:41] [PASSED] 14 VFs
[07:55:41] [PASSED] 15 VFs
[07:55:41] [PASSED] 16 VFs
[07:55:41] [PASSED] 17 VFs
[07:55:41] [PASSED] 18 VFs
[07:55:41] [PASSED] 19 VFs
[07:55:41] [PASSED] 20 VFs
[07:55:41] [PASSED] 21 VFs
[07:55:41] [PASSED] 22 VFs
[07:55:41] [PASSED] 23 VFs
[07:55:41] [PASSED] 24 VFs
[07:55:41] [PASSED] 25 VFs
[07:55:41] [PASSED] 26 VFs
[07:55:41] [PASSED] 27 VFs
[07:55:41] [PASSED] 28 VFs
[07:55:41] [PASSED] 29 VFs
[07:55:41] [PASSED] 30 VFs
[07:55:41] [PASSED] 31 VFs
[07:55:41] [PASSED] 32 VFs
[07:55:41] [PASSED] 33 VFs
[07:55:41] [PASSED] 34 VFs
[07:55:41] [PASSED] 35 VFs
[07:55:41] [PASSED] 36 VFs
[07:55:41] [PASSED] 37 VFs
[07:55:41] [PASSED] 38 VFs
[07:55:41] [PASSED] 39 VFs
[07:55:41] [PASSED] 40 VFs
[07:55:41] [PASSED] 41 VFs
[07:55:41] [PASSED] 42 VFs
[07:55:41] [PASSED] 43 VFs
[07:55:41] [PASSED] 44 VFs
[07:55:41] [PASSED] 45 VFs
[07:55:41] [PASSED] 46 VFs
[07:55:41] [PASSED] 47 VFs
[07:55:41] [PASSED] 48 VFs
[07:55:41] [PASSED] 49 VFs
[07:55:41] [PASSED] 50 VFs
[07:55:41] [PASSED] 51 VFs
[07:55:41] [PASSED] 52 VFs
[07:55:41] [PASSED] 53 VFs
[07:55:41] [PASSED] 54 VFs
[07:55:41] [PASSED] 55 VFs
[07:55:41] [PASSED] 56 VFs
[07:55:41] [PASSED] 57 VFs
[07:55:41] [PASSED] 58 VFs
[07:55:41] [PASSED] 59 VFs
[07:55:41] [PASSED] 60 VFs
[07:55:41] [PASSED] 61 VFs
[07:55:41] [PASSED] 62 VFs
[07:55:41] [PASSED] 63 VFs
[07:55:41] ================= [PASSED] fair_doorbells ==================
[07:55:41] ======================== fair_ggtt ========================
[07:55:41] [PASSED] 1 VF
[07:55:41] [PASSED] 2 VFs
[07:55:41] [PASSED] 3 VFs
[07:55:41] [PASSED] 4 VFs
[07:55:41] [PASSED] 5 VFs
[07:55:41] [PASSED] 6 VFs
[07:55:41] [PASSED] 7 VFs
[07:55:41] [PASSED] 8 VFs
[07:55:41] [PASSED] 9 VFs
[07:55:41] [PASSED] 10 VFs
[07:55:41] [PASSED] 11 VFs
[07:55:41] [PASSED] 12 VFs
[07:55:41] [PASSED] 13 VFs
[07:55:41] [PASSED] 14 VFs
[07:55:41] [PASSED] 15 VFs
[07:55:41] [PASSED] 16 VFs
[07:55:41] [PASSED] 17 VFs
[07:55:41] [PASSED] 18 VFs
[07:55:41] [PASSED] 19 VFs
[07:55:41] [PASSED] 20 VFs
[07:55:41] [PASSED] 21 VFs
[07:55:41] [PASSED] 22 VFs
[07:55:41] [PASSED] 23 VFs
[07:55:41] [PASSED] 24 VFs
[07:55:41] [PASSED] 25 VFs
[07:55:41] [PASSED] 26 VFs
[07:55:41] [PASSED] 27 VFs
[07:55:41] [PASSED] 28 VFs
[07:55:41] [PASSED] 29 VFs
[07:55:41] [PASSED] 30 VFs
[07:55:41] [PASSED] 31 VFs
[07:55:41] [PASSED] 32 VFs
[07:55:41] [PASSED] 33 VFs
[07:55:41] [PASSED] 34 VFs
[07:55:41] [PASSED] 35 VFs
[07:55:41] [PASSED] 36 VFs
[07:55:41] [PASSED] 37 VFs
[07:55:41] [PASSED] 38 VFs
[07:55:41] [PASSED] 39 VFs
[07:55:41] [PASSED] 40 VFs
[07:55:41] [PASSED] 41 VFs
[07:55:41] [PASSED] 42 VFs
[07:55:41] [PASSED] 43 VFs
[07:55:41] [PASSED] 44 VFs
[07:55:41] [PASSED] 45 VFs
[07:55:41] [PASSED] 46 VFs
[07:55:41] [PASSED] 47 VFs
[07:55:41] [PASSED] 48 VFs
[07:55:41] [PASSED] 49 VFs
[07:55:41] [PASSED] 50 VFs
[07:55:41] [PASSED] 51 VFs
[07:55:41] [PASSED] 52 VFs
[07:55:41] [PASSED] 53 VFs
[07:55:41] [PASSED] 54 VFs
[07:55:41] [PASSED] 55 VFs
[07:55:41] [PASSED] 56 VFs
[07:55:41] [PASSED] 57 VFs
[07:55:41] [PASSED] 58 VFs
[07:55:41] [PASSED] 59 VFs
[07:55:41] [PASSED] 60 VFs
[07:55:41] [PASSED] 61 VFs
[07:55:41] [PASSED] 62 VFs
[07:55:41] [PASSED] 63 VFs
[07:55:41] ==================== [PASSED] fair_ggtt ====================
[07:55:41] ======================== fair_vram ========================
[07:55:41] [PASSED] 1 VF
[07:55:41] [PASSED] 2 VFs
[07:55:41] [PASSED] 3 VFs
[07:55:41] [PASSED] 4 VFs
[07:55:41] [PASSED] 5 VFs
[07:55:41] [PASSED] 6 VFs
[07:55:41] [PASSED] 7 VFs
[07:55:41] [PASSED] 8 VFs
[07:55:41] [PASSED] 9 VFs
[07:55:41] [PASSED] 10 VFs
[07:55:41] [PASSED] 11 VFs
[07:55:41] [PASSED] 12 VFs
[07:55:41] [PASSED] 13 VFs
[07:55:41] [PASSED] 14 VFs
[07:55:41] [PASSED] 15 VFs
[07:55:41] [PASSED] 16 VFs
[07:55:41] [PASSED] 17 VFs
[07:55:41] [PASSED] 18 VFs
[07:55:41] [PASSED] 19 VFs
[07:55:41] [PASSED] 20 VFs
[07:55:41] [PASSED] 21 VFs
[07:55:41] [PASSED] 22 VFs
[07:55:41] [PASSED] 23 VFs
[07:55:41] [PASSED] 24 VFs
[07:55:41] [PASSED] 25 VFs
[07:55:41] [PASSED] 26 VFs
[07:55:41] [PASSED] 27 VFs
[07:55:41] [PASSED] 28 VFs
[07:55:41] [PASSED] 29 VFs
[07:55:41] [PASSED] 30 VFs
[07:55:41] [PASSED] 31 VFs
[07:55:41] [PASSED] 32 VFs
[07:55:41] [PASSED] 33 VFs
[07:55:41] [PASSED] 34 VFs
[07:55:41] [PASSED] 35 VFs
[07:55:41] [PASSED] 36 VFs
[07:55:41] [PASSED] 37 VFs
[07:55:41] [PASSED] 38 VFs
[07:55:41] [PASSED] 39 VFs
[07:55:41] [PASSED] 40 VFs
[07:55:41] [PASSED] 41 VFs
[07:55:41] [PASSED] 42 VFs
[07:55:41] [PASSED] 43 VFs
[07:55:41] [PASSED] 44 VFs
[07:55:41] [PASSED] 45 VFs
[07:55:41] [PASSED] 46 VFs
[07:55:41] [PASSED] 47 VFs
[07:55:41] [PASSED] 48 VFs
[07:55:41] [PASSED] 49 VFs
[07:55:41] [PASSED] 50 VFs
[07:55:41] [PASSED] 51 VFs
[07:55:41] [PASSED] 52 VFs
[07:55:41] [PASSED] 53 VFs
[07:55:41] [PASSED] 54 VFs
[07:55:41] [PASSED] 55 VFs
[07:55:41] [PASSED] 56 VFs
[07:55:41] [PASSED] 57 VFs
[07:55:41] [PASSED] 58 VFs
[07:55:41] [PASSED] 59 VFs
[07:55:41] [PASSED] 60 VFs
[07:55:41] [PASSED] 61 VFs
[07:55:41] [PASSED] 62 VFs
[07:55:41] [PASSED] 63 VFs
[07:55:41] ==================== [PASSED] fair_vram ====================
[07:55:41] ================== [PASSED] pf_gt_config ===================
[07:55:41] ===================== lmtt (1 subtest) =====================
[07:55:41] ======================== test_ops =========================
[07:55:41] [PASSED] 2-level
[07:55:41] [PASSED] multi-level
[07:55:41] ==================== [PASSED] test_ops =====================
[07:55:41] ====================== [PASSED] lmtt =======================
[07:55:41] ================= pf_service (11 subtests) =================
[07:55:41] [PASSED] pf_negotiate_any
[07:55:41] [PASSED] pf_negotiate_base_match
[07:55:41] [PASSED] pf_negotiate_base_newer
[07:55:41] [PASSED] pf_negotiate_base_next
[07:55:41] [SKIPPED] pf_negotiate_base_older
[07:55:41] [PASSED] pf_negotiate_base_prev
[07:55:41] [PASSED] pf_negotiate_latest_match
[07:55:41] [PASSED] pf_negotiate_latest_newer
[07:55:41] [PASSED] pf_negotiate_latest_next
[07:55:41] [SKIPPED] pf_negotiate_latest_older
[07:55:41] [SKIPPED] pf_negotiate_latest_prev
[07:55:41] =================== [PASSED] pf_service ====================
[07:55:41] ================= xe_guc_g2g (2 subtests) ==================
[07:55:41] ============== xe_live_guc_g2g_kunit_default ==============
[07:55:41] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[07:55:41] ============== xe_live_guc_g2g_kunit_allmem ===============
[07:55:41] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[07:55:41] =================== [SKIPPED] xe_guc_g2g ===================
[07:55:41] =================== xe_mocs (2 subtests) ===================
[07:55:41] ================ xe_live_mocs_kernel_kunit ================
[07:55:41] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[07:55:41] ================ xe_live_mocs_reset_kunit =================
[07:55:41] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[07:55:41] ==================== [SKIPPED] xe_mocs =====================
[07:55:41] ================= xe_migrate (2 subtests) ==================
[07:55:41] ================= xe_migrate_sanity_kunit =================
[07:55:41] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[07:55:41] ================== xe_validate_ccs_kunit ==================
[07:55:41] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[07:55:41] =================== [SKIPPED] xe_migrate ===================
[07:55:41] ================== xe_dma_buf (1 subtest) ==================
[07:55:41] ==================== xe_dma_buf_kunit =====================
[07:55:41] ================ [SKIPPED] xe_dma_buf_kunit ================
[07:55:41] =================== [SKIPPED] xe_dma_buf ===================
[07:55:41] ================= xe_bo_shrink (1 subtest) =================
[07:55:41] =================== xe_bo_shrink_kunit ====================
[07:55:41] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[07:55:41] ================== [SKIPPED] xe_bo_shrink ==================
[07:55:41] ==================== xe_bo (2 subtests) ====================
[07:55:41] ================== xe_ccs_migrate_kunit ===================
[07:55:41] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[07:55:41] ==================== xe_bo_evict_kunit ====================
[07:55:41] =============== [SKIPPED] xe_bo_evict_kunit ================
[07:55:41] ===================== [SKIPPED] xe_bo ======================
[07:55:41] ==================== args (13 subtests) ====================
[07:55:41] [PASSED] count_args_test
[07:55:41] [PASSED] call_args_example
[07:55:41] [PASSED] call_args_test
[07:55:41] [PASSED] drop_first_arg_example
[07:55:41] [PASSED] drop_first_arg_test
[07:55:41] [PASSED] first_arg_example
[07:55:41] [PASSED] first_arg_test
[07:55:41] [PASSED] last_arg_example
[07:55:41] [PASSED] last_arg_test
[07:55:41] [PASSED] pick_arg_example
[07:55:41] [PASSED] if_args_example
[07:55:41] [PASSED] if_args_test
[07:55:41] [PASSED] sep_comma_example
[07:55:41] ====================== [PASSED] args =======================
[07:55:41] =================== xe_pci (3 subtests) ====================
[07:55:41] ==================== check_graphics_ip ====================
[07:55:41] [PASSED] 12.00 Xe_LP
[07:55:41] [PASSED] 12.10 Xe_LP+
[07:55:41] [PASSED] 12.55 Xe_HPG
[07:55:41] [PASSED] 12.60 Xe_HPC
[07:55:41] [PASSED] 12.70 Xe_LPG
[07:55:41] [PASSED] 12.71 Xe_LPG
[07:55:41] [PASSED] 12.74 Xe_LPG+
[07:55:41] [PASSED] 20.01 Xe2_HPG
[07:55:41] [PASSED] 20.02 Xe2_HPG
[07:55:41] [PASSED] 20.04 Xe2_LPG
[07:55:41] [PASSED] 30.00 Xe3_LPG
[07:55:41] [PASSED] 30.01 Xe3_LPG
[07:55:41] [PASSED] 30.03 Xe3_LPG
[07:55:41] [PASSED] 30.04 Xe3_LPG
[07:55:41] [PASSED] 30.05 Xe3_LPG
[07:55:41] [PASSED] 35.10 Xe3p_LPG
[07:55:41] [PASSED] 35.11 Xe3p_XPC
[07:55:41] ================ [PASSED] check_graphics_ip ================
[07:55:41] ===================== check_media_ip ======================
[07:55:41] [PASSED] 12.00 Xe_M
[07:55:41] [PASSED] 12.55 Xe_HPM
[07:55:41] [PASSED] 13.00 Xe_LPM+
[07:55:41] [PASSED] 13.01 Xe2_HPM
[07:55:41] [PASSED] 20.00 Xe2_LPM
[07:55:41] [PASSED] 30.00 Xe3_LPM
[07:55:41] [PASSED] 30.02 Xe3_LPM
[07:55:41] [PASSED] 35.00 Xe3p_LPM
[07:55:41] [PASSED] 35.03 Xe3p_HPM
[07:55:41] ================= [PASSED] check_media_ip ==================
[07:55:41] =================== check_platform_desc ===================
[07:55:41] [PASSED] 0x9A60 (TIGERLAKE)
[07:55:41] [PASSED] 0x9A68 (TIGERLAKE)
[07:55:41] [PASSED] 0x9A70 (TIGERLAKE)
[07:55:41] [PASSED] 0x9A40 (TIGERLAKE)
[07:55:41] [PASSED] 0x9A49 (TIGERLAKE)
[07:55:41] [PASSED] 0x9A59 (TIGERLAKE)
[07:55:41] [PASSED] 0x9A78 (TIGERLAKE)
[07:55:41] [PASSED] 0x9AC0 (TIGERLAKE)
[07:55:41] [PASSED] 0x9AC9 (TIGERLAKE)
[07:55:41] [PASSED] 0x9AD9 (TIGERLAKE)
[07:55:41] [PASSED] 0x9AF8 (TIGERLAKE)
[07:55:41] [PASSED] 0x4C80 (ROCKETLAKE)
[07:55:41] [PASSED] 0x4C8A (ROCKETLAKE)
[07:55:41] [PASSED] 0x4C8B (ROCKETLAKE)
[07:55:41] [PASSED] 0x4C8C (ROCKETLAKE)
[07:55:41] [PASSED] 0x4C90 (ROCKETLAKE)
[07:55:41] [PASSED] 0x4C9A (ROCKETLAKE)
[07:55:41] [PASSED] 0x4680 (ALDERLAKE_S)
[07:55:41] [PASSED] 0x4682 (ALDERLAKE_S)
[07:55:41] [PASSED] 0x4688 (ALDERLAKE_S)
[07:55:41] [PASSED] 0x468A (ALDERLAKE_S)
[07:55:41] [PASSED] 0x468B (ALDERLAKE_S)
[07:55:41] [PASSED] 0x4690 (ALDERLAKE_S)
[07:55:41] [PASSED] 0x4692 (ALDERLAKE_S)
[07:55:41] [PASSED] 0x4693 (ALDERLAKE_S)
[07:55:41] [PASSED] 0x46A0 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x46A1 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x46A2 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x46A3 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x46A6 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x46A8 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x46AA (ALDERLAKE_P)
[07:55:41] [PASSED] 0x462A (ALDERLAKE_P)
[07:55:41] [PASSED] 0x4626 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x4628 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x46B0 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x46B1 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x46B2 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x46B3 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x46C0 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x46C1 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x46C2 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x46C3 (ALDERLAKE_P)
[07:55:41] [PASSED] 0x46D0 (ALDERLAKE_N)
[07:55:41] [PASSED] 0x46D1 (ALDERLAKE_N)
[07:55:41] [PASSED] 0x46D2 (ALDERLAKE_N)
[07:55:41] [PASSED] 0x46D3 (ALDERLAKE_N)
[07:55:41] [PASSED] 0x46D4 (ALDERLAKE_N)
[07:55:41] [PASSED] 0xA721 (ALDERLAKE_P)
[07:55:41] [PASSED] 0xA7A1 (ALDERLAKE_P)
[07:55:41] [PASSED] 0xA7A9 (ALDERLAKE_P)
[07:55:41] [PASSED] 0xA7AC (ALDERLAKE_P)
[07:55:41] [PASSED] 0xA7AD (ALDERLAKE_P)
[07:55:41] [PASSED] 0xA720 (ALDERLAKE_P)
[07:55:41] [PASSED] 0xA7A0 (ALDERLAKE_P)
[07:55:41] [PASSED] 0xA7A8 (ALDERLAKE_P)
[07:55:41] [PASSED] 0xA7AA (ALDERLAKE_P)
[07:55:41] [PASSED] 0xA7AB (ALDERLAKE_P)
[07:55:41] [PASSED] 0xA780 (ALDERLAKE_S)
[07:55:41] [PASSED] 0xA781 (ALDERLAKE_S)
[07:55:41] [PASSED] 0xA782 (ALDERLAKE_S)
[07:55:41] [PASSED] 0xA783 (ALDERLAKE_S)
[07:55:41] [PASSED] 0xA788 (ALDERLAKE_S)
[07:55:41] [PASSED] 0xA789 (ALDERLAKE_S)
[07:55:41] [PASSED] 0xA78A (ALDERLAKE_S)
[07:55:41] [PASSED] 0xA78B (ALDERLAKE_S)
[07:55:41] [PASSED] 0x4905 (DG1)
[07:55:41] [PASSED] 0x4906 (DG1)
[07:55:41] [PASSED] 0x4907 (DG1)
[07:55:41] [PASSED] 0x4908 (DG1)
[07:55:41] [PASSED] 0x4909 (DG1)
[07:55:41] [PASSED] 0x56C0 (DG2)
[07:55:41] [PASSED] 0x56C2 (DG2)
[07:55:41] [PASSED] 0x56C1 (DG2)
[07:55:41] [PASSED] 0x7D51 (METEORLAKE)
[07:55:41] [PASSED] 0x7DD1 (METEORLAKE)
[07:55:41] [PASSED] 0x7D41 (METEORLAKE)
[07:55:41] [PASSED] 0x7D67 (METEORLAKE)
[07:55:41] [PASSED] 0xB640 (METEORLAKE)
[07:55:41] [PASSED] 0x56A0 (DG2)
[07:55:41] [PASSED] 0x56A1 (DG2)
[07:55:41] [PASSED] 0x56A2 (DG2)
[07:55:41] [PASSED] 0x56BE (DG2)
[07:55:41] [PASSED] 0x56BF (DG2)
[07:55:41] [PASSED] 0x5690 (DG2)
[07:55:41] [PASSED] 0x5691 (DG2)
[07:55:41] [PASSED] 0x5692 (DG2)
[07:55:41] [PASSED] 0x56A5 (DG2)
[07:55:41] [PASSED] 0x56A6 (DG2)
[07:55:41] [PASSED] 0x56B0 (DG2)
[07:55:41] [PASSED] 0x56B1 (DG2)
[07:55:41] [PASSED] 0x56BA (DG2)
[07:55:41] [PASSED] 0x56BB (DG2)
[07:55:41] [PASSED] 0x56BC (DG2)
[07:55:41] [PASSED] 0x56BD (DG2)
[07:55:41] [PASSED] 0x5693 (DG2)
[07:55:41] [PASSED] 0x5694 (DG2)
[07:55:41] [PASSED] 0x5695 (DG2)
[07:55:41] [PASSED] 0x56A3 (DG2)
[07:55:41] [PASSED] 0x56A4 (DG2)
[07:55:41] [PASSED] 0x56B2 (DG2)
[07:55:41] [PASSED] 0x56B3 (DG2)
[07:55:41] [PASSED] 0x5696 (DG2)
[07:55:41] [PASSED] 0x5697 (DG2)
[07:55:41] [PASSED] 0xB69 (PVC)
[07:55:41] [PASSED] 0xB6E (PVC)
[07:55:41] [PASSED] 0xBD4 (PVC)
[07:55:41] [PASSED] 0xBD5 (PVC)
[07:55:41] [PASSED] 0xBD6 (PVC)
[07:55:41] [PASSED] 0xBD7 (PVC)
[07:55:41] [PASSED] 0xBD8 (PVC)
[07:55:41] [PASSED] 0xBD9 (PVC)
[07:55:41] [PASSED] 0xBDA (PVC)
[07:55:41] [PASSED] 0xBDB (PVC)
[07:55:41] [PASSED] 0xBE0 (PVC)
[07:55:41] [PASSED] 0xBE1 (PVC)
[07:55:41] [PASSED] 0xBE5 (PVC)
[07:55:41] [PASSED] 0x7D40 (METEORLAKE)
[07:55:41] [PASSED] 0x7D45 (METEORLAKE)
[07:55:41] [PASSED] 0x7D55 (METEORLAKE)
[07:55:41] [PASSED] 0x7D60 (METEORLAKE)
[07:55:41] [PASSED] 0x7DD5 (METEORLAKE)
[07:55:41] [PASSED] 0x6420 (LUNARLAKE)
[07:55:41] [PASSED] 0x64A0 (LUNARLAKE)
[07:55:41] [PASSED] 0x64B0 (LUNARLAKE)
[07:55:41] [PASSED] 0xE202 (BATTLEMAGE)
[07:55:41] [PASSED] 0xE209 (BATTLEMAGE)
[07:55:41] [PASSED] 0xE20B (BATTLEMAGE)
[07:55:41] [PASSED] 0xE20C (BATTLEMAGE)
[07:55:41] [PASSED] 0xE20D (BATTLEMAGE)
[07:55:41] [PASSED] 0xE210 (BATTLEMAGE)
[07:55:41] [PASSED] 0xE211 (BATTLEMAGE)
[07:55:41] [PASSED] 0xE212 (BATTLEMAGE)
[07:55:41] [PASSED] 0xE216 (BATTLEMAGE)
[07:55:41] [PASSED] 0xE220 (BATTLEMAGE)
[07:55:41] [PASSED] 0xE221 (BATTLEMAGE)
[07:55:41] [PASSED] 0xE222 (BATTLEMAGE)
[07:55:41] [PASSED] 0xE223 (BATTLEMAGE)
[07:55:41] [PASSED] 0xB080 (PANTHERLAKE)
[07:55:41] [PASSED] 0xB081 (PANTHERLAKE)
[07:55:41] [PASSED] 0xB082 (PANTHERLAKE)
[07:55:41] [PASSED] 0xB083 (PANTHERLAKE)
[07:55:41] [PASSED] 0xB084 (PANTHERLAKE)
[07:55:41] [PASSED] 0xB085 (PANTHERLAKE)
[07:55:41] [PASSED] 0xB086 (PANTHERLAKE)
[07:55:41] [PASSED] 0xB087 (PANTHERLAKE)
[07:55:41] [PASSED] 0xB08F (PANTHERLAKE)
[07:55:41] [PASSED] 0xB090 (PANTHERLAKE)
[07:55:41] [PASSED] 0xB0A0 (PANTHERLAKE)
[07:55:41] [PASSED] 0xB0B0 (PANTHERLAKE)
[07:55:41] [PASSED] 0xFD80 (PANTHERLAKE)
[07:55:41] [PASSED] 0xFD81 (PANTHERLAKE)
[07:55:41] [PASSED] 0xD740 (NOVALAKE_S)
[07:55:41] [PASSED] 0xD741 (NOVALAKE_S)
[07:55:41] [PASSED] 0xD742 (NOVALAKE_S)
[07:55:41] [PASSED] 0xD743 (NOVALAKE_S)
[07:55:41] [PASSED] 0xD744 (NOVALAKE_S)
[07:55:41] [PASSED] 0xD745 (NOVALAKE_S)
[07:55:41] [PASSED] 0x674C (CRESCENTISLAND)
[07:55:41] [PASSED] 0xD750 (NOVALAKE_P)
[07:55:41] [PASSED] 0xD751 (NOVALAKE_P)
[07:55:41] [PASSED] 0xD752 (NOVALAKE_P)
[07:55:41] [PASSED] 0xD753 (NOVALAKE_P)
[07:55:41] [PASSED] 0xD754 (NOVALAKE_P)
[07:55:41] [PASSED] 0xD755 (NOVALAKE_P)
[07:55:41] [PASSED] 0xD756 (NOVALAKE_P)
[07:55:41] [PASSED] 0xD757 (NOVALAKE_P)
[07:55:41] [PASSED] 0xD75F (NOVALAKE_P)
[07:55:41] =============== [PASSED] check_platform_desc ===============
[07:55:41] ===================== [PASSED] xe_pci ======================
[07:55:41] =================== xe_rtp (2 subtests) ====================
[07:55:41] =============== xe_rtp_process_to_sr_tests ================
[07:55:41] [PASSED] coalesce-same-reg
[07:55:41] [PASSED] no-match-no-add
[07:55:41] [PASSED] match-or
[07:55:41] [PASSED] match-or-xfail
[07:55:41] [PASSED] no-match-no-add-multiple-rules
[07:55:41] [PASSED] two-regs-two-entries
[07:55:41] [PASSED] clr-one-set-other
[07:55:41] [PASSED] set-field
[07:55:41] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[07:55:41] [PASSED] conflict-not-disjoint
[07:55:41] [PASSED] conflict-reg-type
[07:55:41] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[07:55:41] ================== xe_rtp_process_tests ===================
[07:55:41] [PASSED] active1
[07:55:41] [PASSED] active2
[07:55:41] [PASSED] active-inactive
[07:55:41] [PASSED] inactive-active
[07:55:41] [PASSED] inactive-1st_or_active-inactive
[07:55:41] [PASSED] inactive-2nd_or_active-inactive
[07:55:41] [PASSED] inactive-last_or_active-inactive
[07:55:41] [PASSED] inactive-no_or_active-inactive
[07:55:41] ============== [PASSED] xe_rtp_process_tests ===============
[07:55:41] ===================== [PASSED] xe_rtp ======================
[07:55:41] ==================== xe_wa (1 subtest) =====================
[07:55:41] ======================== xe_wa_gt =========================
[07:55:41] [PASSED] TIGERLAKE B0
[07:55:41] [PASSED] DG1 A0
[07:55:41] [PASSED] DG1 B0
[07:55:41] [PASSED] ALDERLAKE_S A0
[07:55:41] [PASSED] ALDERLAKE_S B0
[07:55:41] [PASSED] ALDERLAKE_S C0
[07:55:41] [PASSED] ALDERLAKE_S D0
[07:55:41] [PASSED] ALDERLAKE_P A0
[07:55:41] [PASSED] ALDERLAKE_P B0
[07:55:41] [PASSED] ALDERLAKE_P C0
[07:55:41] [PASSED] ALDERLAKE_S RPLS D0
[07:55:41] [PASSED] ALDERLAKE_P RPLU E0
[07:55:41] [PASSED] DG2 G10 C0
[07:55:41] [PASSED] DG2 G11 B1
[07:55:41] [PASSED] DG2 G12 A1
[07:55:41] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:55:41] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:55:41] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[07:55:41] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[07:55:41] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[07:55:41] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[07:55:41] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[07:55:41] ==================== [PASSED] xe_wa_gt =====================
[07:55:41] ====================== [PASSED] xe_wa ======================
[07:55:41] ============================================================
[07:55:41] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[07:55:41] Elapsed time: 35.245s total, 4.193s configuring, 30.435s building, 0.600s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[07:55:41] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:55:43] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:56:07] Starting KUnit Kernel (1/1)...
[07:56:07] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:56:07] ============ drm_test_pick_cmdline (2 subtests) ============
[07:56:07] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[07:56:07] =============== drm_test_pick_cmdline_named ===============
[07:56:07] [PASSED] NTSC
[07:56:07] [PASSED] NTSC-J
[07:56:07] [PASSED] PAL
[07:56:07] [PASSED] PAL-M
[07:56:07] =========== [PASSED] drm_test_pick_cmdline_named ===========
[07:56:07] ============== [PASSED] drm_test_pick_cmdline ==============
[07:56:07] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[07:56:07] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[07:56:07] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[07:56:07] =========== drm_validate_clone_mode (2 subtests) ===========
[07:56:07] ============== drm_test_check_in_clone_mode ===============
[07:56:07] [PASSED] in_clone_mode
[07:56:07] [PASSED] not_in_clone_mode
[07:56:07] ========== [PASSED] drm_test_check_in_clone_mode ===========
[07:56:07] =============== drm_test_check_valid_clones ===============
[07:56:07] [PASSED] not_in_clone_mode
[07:56:07] [PASSED] valid_clone
[07:56:07] [PASSED] invalid_clone
[07:56:07] =========== [PASSED] drm_test_check_valid_clones ===========
[07:56:07] ============= [PASSED] drm_validate_clone_mode =============
[07:56:07] ============= drm_validate_modeset (1 subtest) =============
[07:56:07] [PASSED] drm_test_check_connector_changed_modeset
[07:56:07] ============== [PASSED] drm_validate_modeset ===============
[07:56:07] ====== drm_test_bridge_get_current_state (2 subtests) ======
[07:56:07] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[07:56:07] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[07:56:07] ======== [PASSED] drm_test_bridge_get_current_state ========
[07:56:07] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[07:56:07] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[07:56:07] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[07:56:07] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[07:56:07] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[07:56:07] ============== drm_bridge_alloc (2 subtests) ===============
[07:56:07] [PASSED] drm_test_drm_bridge_alloc_basic
[07:56:07] [PASSED] drm_test_drm_bridge_alloc_get_put
[07:56:07] ================ [PASSED] drm_bridge_alloc =================
[07:56:07] ============= drm_cmdline_parser (40 subtests) =============
[07:56:07] [PASSED] drm_test_cmdline_force_d_only
[07:56:07] [PASSED] drm_test_cmdline_force_D_only_dvi
[07:56:07] [PASSED] drm_test_cmdline_force_D_only_hdmi
[07:56:07] [PASSED] drm_test_cmdline_force_D_only_not_digital
[07:56:07] [PASSED] drm_test_cmdline_force_e_only
[07:56:07] [PASSED] drm_test_cmdline_res
[07:56:07] [PASSED] drm_test_cmdline_res_vesa
[07:56:07] [PASSED] drm_test_cmdline_res_vesa_rblank
[07:56:07] [PASSED] drm_test_cmdline_res_rblank
[07:56:07] [PASSED] drm_test_cmdline_res_bpp
[07:56:07] [PASSED] drm_test_cmdline_res_refresh
[07:56:07] [PASSED] drm_test_cmdline_res_bpp_refresh
[07:56:07] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[07:56:07] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[07:56:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[07:56:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[07:56:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[07:56:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[07:56:07] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[07:56:07] [PASSED] drm_test_cmdline_res_margins_force_on
[07:56:07] [PASSED] drm_test_cmdline_res_vesa_margins
[07:56:07] [PASSED] drm_test_cmdline_name
[07:56:07] [PASSED] drm_test_cmdline_name_bpp
[07:56:07] [PASSED] drm_test_cmdline_name_option
[07:56:07] [PASSED] drm_test_cmdline_name_bpp_option
[07:56:07] [PASSED] drm_test_cmdline_rotate_0
[07:56:07] [PASSED] drm_test_cmdline_rotate_90
[07:56:07] [PASSED] drm_test_cmdline_rotate_180
[07:56:07] [PASSED] drm_test_cmdline_rotate_270
[07:56:07] [PASSED] drm_test_cmdline_hmirror
[07:56:07] [PASSED] drm_test_cmdline_vmirror
[07:56:07] [PASSED] drm_test_cmdline_margin_options
[07:56:07] [PASSED] drm_test_cmdline_multiple_options
[07:56:07] [PASSED] drm_test_cmdline_bpp_extra_and_option
[07:56:07] [PASSED] drm_test_cmdline_extra_and_option
[07:56:07] [PASSED] drm_test_cmdline_freestanding_options
[07:56:07] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[07:56:07] [PASSED] drm_test_cmdline_panel_orientation
[07:56:07] ================ drm_test_cmdline_invalid =================
[07:56:07] [PASSED] margin_only
[07:56:07] [PASSED] interlace_only
[07:56:07] [PASSED] res_missing_x
[07:56:07] [PASSED] res_missing_y
[07:56:07] [PASSED] res_bad_y
[07:56:07] [PASSED] res_missing_y_bpp
[07:56:07] [PASSED] res_bad_bpp
[07:56:07] [PASSED] res_bad_refresh
[07:56:07] [PASSED] res_bpp_refresh_force_on_off
[07:56:07] [PASSED] res_invalid_mode
[07:56:07] [PASSED] res_bpp_wrong_place_mode
[07:56:07] [PASSED] name_bpp_refresh
[07:56:07] [PASSED] name_refresh
[07:56:07] [PASSED] name_refresh_wrong_mode
[07:56:07] [PASSED] name_refresh_invalid_mode
[07:56:07] [PASSED] rotate_multiple
[07:56:07] [PASSED] rotate_invalid_val
[07:56:07] [PASSED] rotate_truncated
[07:56:07] [PASSED] invalid_option
[07:56:07] [PASSED] invalid_tv_option
[07:56:07] [PASSED] truncated_tv_option
[07:56:07] ============ [PASSED] drm_test_cmdline_invalid =============
[07:56:07] =============== drm_test_cmdline_tv_options ===============
[07:56:07] [PASSED] NTSC
[07:56:07] [PASSED] NTSC_443
[07:56:07] [PASSED] NTSC_J
[07:56:07] [PASSED] PAL
[07:56:07] [PASSED] PAL_M
[07:56:07] [PASSED] PAL_N
[07:56:07] [PASSED] SECAM
[07:56:07] [PASSED] MONO_525
[07:56:07] [PASSED] MONO_625
[07:56:07] =========== [PASSED] drm_test_cmdline_tv_options ===========
[07:56:07] =============== [PASSED] drm_cmdline_parser ================
[07:56:07] ========== drmm_connector_hdmi_init (20 subtests) ==========
[07:56:07] [PASSED] drm_test_connector_hdmi_init_valid
[07:56:07] [PASSED] drm_test_connector_hdmi_init_bpc_8
[07:56:07] [PASSED] drm_test_connector_hdmi_init_bpc_10
[07:56:07] [PASSED] drm_test_connector_hdmi_init_bpc_12
[07:56:07] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[07:56:07] [PASSED] drm_test_connector_hdmi_init_bpc_null
[07:56:07] [PASSED] drm_test_connector_hdmi_init_formats_empty
[07:56:07] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[07:56:07] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[07:56:07] [PASSED] supported_formats=0x9 yuv420_allowed=1
[07:56:07] [PASSED] supported_formats=0x9 yuv420_allowed=0
[07:56:07] [PASSED] supported_formats=0x3 yuv420_allowed=1
[07:56:07] [PASSED] supported_formats=0x3 yuv420_allowed=0
[07:56:07] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[07:56:07] [PASSED] drm_test_connector_hdmi_init_null_ddc
[07:56:07] [PASSED] drm_test_connector_hdmi_init_null_product
[07:56:07] [PASSED] drm_test_connector_hdmi_init_null_vendor
[07:56:07] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[07:56:07] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[07:56:07] [PASSED] drm_test_connector_hdmi_init_product_valid
[07:56:07] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[07:56:07] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[07:56:07] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[07:56:07] ========= drm_test_connector_hdmi_init_type_valid =========
[07:56:07] [PASSED] HDMI-A
[07:56:07] [PASSED] HDMI-B
[07:56:07] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[07:56:07] ======== drm_test_connector_hdmi_init_type_invalid ========
[07:56:07] [PASSED] Unknown
[07:56:07] [PASSED] VGA
[07:56:07] [PASSED] DVI-I
[07:56:07] [PASSED] DVI-D
[07:56:07] [PASSED] DVI-A
[07:56:07] [PASSED] Composite
[07:56:07] [PASSED] SVIDEO
[07:56:07] [PASSED] LVDS
[07:56:07] [PASSED] Component
[07:56:07] [PASSED] DIN
[07:56:07] [PASSED] DP
[07:56:07] [PASSED] TV
[07:56:07] [PASSED] eDP
[07:56:07] [PASSED] Virtual
[07:56:07] [PASSED] DSI
[07:56:07] [PASSED] DPI
[07:56:07] [PASSED] Writeback
[07:56:07] [PASSED] SPI
[07:56:07] [PASSED] USB
[07:56:07] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[07:56:07] ============ [PASSED] drmm_connector_hdmi_init =============
[07:56:07] ============= drmm_connector_init (3 subtests) =============
[07:56:07] [PASSED] drm_test_drmm_connector_init
[07:56:07] [PASSED] drm_test_drmm_connector_init_null_ddc
[07:56:07] ========= drm_test_drmm_connector_init_type_valid =========
[07:56:07] [PASSED] Unknown
[07:56:07] [PASSED] VGA
[07:56:07] [PASSED] DVI-I
[07:56:07] [PASSED] DVI-D
[07:56:07] [PASSED] DVI-A
[07:56:07] [PASSED] Composite
[07:56:07] [PASSED] SVIDEO
[07:56:07] [PASSED] LVDS
[07:56:07] [PASSED] Component
[07:56:07] [PASSED] DIN
[07:56:07] [PASSED] DP
[07:56:07] [PASSED] HDMI-A
[07:56:07] [PASSED] HDMI-B
[07:56:07] [PASSED] TV
[07:56:07] [PASSED] eDP
[07:56:07] [PASSED] Virtual
[07:56:07] [PASSED] DSI
[07:56:07] [PASSED] DPI
[07:56:07] [PASSED] Writeback
[07:56:07] [PASSED] SPI
[07:56:07] [PASSED] USB
[07:56:07] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[07:56:07] =============== [PASSED] drmm_connector_init ===============
[07:56:07] ========= drm_connector_dynamic_init (6 subtests) ==========
[07:56:07] [PASSED] drm_test_drm_connector_dynamic_init
[07:56:07] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[07:56:07] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[07:56:07] [PASSED] drm_test_drm_connector_dynamic_init_properties
[07:56:07] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[07:56:07] [PASSED] Unknown
[07:56:07] [PASSED] VGA
[07:56:07] [PASSED] DVI-I
[07:56:07] [PASSED] DVI-D
[07:56:07] [PASSED] DVI-A
[07:56:07] [PASSED] Composite
[07:56:07] [PASSED] SVIDEO
[07:56:07] [PASSED] LVDS
[07:56:07] [PASSED] Component
[07:56:07] [PASSED] DIN
[07:56:07] [PASSED] DP
[07:56:07] [PASSED] HDMI-A
[07:56:07] [PASSED] HDMI-B
[07:56:07] [PASSED] TV
[07:56:07] [PASSED] eDP
[07:56:07] [PASSED] Virtual
[07:56:07] [PASSED] DSI
[07:56:07] [PASSED] DPI
[07:56:07] [PASSED] Writeback
[07:56:07] [PASSED] SPI
[07:56:07] [PASSED] USB
[07:56:07] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[07:56:07] ======== drm_test_drm_connector_dynamic_init_name =========
[07:56:07] [PASSED] Unknown
[07:56:07] [PASSED] VGA
[07:56:07] [PASSED] DVI-I
[07:56:07] [PASSED] DVI-D
[07:56:07] [PASSED] DVI-A
[07:56:07] [PASSED] Composite
[07:56:07] [PASSED] SVIDEO
[07:56:07] [PASSED] LVDS
[07:56:07] [PASSED] Component
[07:56:07] [PASSED] DIN
[07:56:07] [PASSED] DP
[07:56:07] [PASSED] HDMI-A
[07:56:07] [PASSED] HDMI-B
[07:56:07] [PASSED] TV
[07:56:07] [PASSED] eDP
[07:56:07] [PASSED] Virtual
[07:56:07] [PASSED] DSI
[07:56:07] [PASSED] DPI
[07:56:07] [PASSED] Writeback
[07:56:07] [PASSED] SPI
[07:56:07] [PASSED] USB
[07:56:07] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[07:56:07] =========== [PASSED] drm_connector_dynamic_init ============
[07:56:07] ==== drm_connector_dynamic_register_early (4 subtests) =====
[07:56:07] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[07:56:07] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[07:56:07] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[07:56:07] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[07:56:07] ====== [PASSED] drm_connector_dynamic_register_early =======
[07:56:07] ======= drm_connector_dynamic_register (7 subtests) ========
[07:56:07] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[07:56:07] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[07:56:07] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[07:56:07] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[07:56:07] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[07:56:07] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[07:56:07] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[07:56:07] ========= [PASSED] drm_connector_dynamic_register ==========
[07:56:07] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[07:56:07] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[07:56:07] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[07:56:07] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[07:56:07] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[07:56:07] ========== drm_test_get_tv_mode_from_name_valid ===========
[07:56:07] [PASSED] NTSC
[07:56:07] [PASSED] NTSC-443
[07:56:07] [PASSED] NTSC-J
[07:56:07] [PASSED] PAL
[07:56:07] [PASSED] PAL-M
[07:56:07] [PASSED] PAL-N
[07:56:07] [PASSED] SECAM
[07:56:07] [PASSED] Mono
[07:56:07] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[07:56:07] [PASSED] drm_test_get_tv_mode_from_name_truncated
[07:56:07] ============ [PASSED] drm_get_tv_mode_from_name ============
[07:56:07] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[07:56:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[07:56:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[07:56:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[07:56:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[07:56:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[07:56:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[07:56:07] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[07:56:07] [PASSED] VIC 96
[07:56:07] [PASSED] VIC 97
[07:56:07] [PASSED] VIC 101
[07:56:07] [PASSED] VIC 102
[07:56:07] [PASSED] VIC 106
[07:56:07] [PASSED] VIC 107
[07:56:07] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[07:56:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[07:56:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[07:56:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[07:56:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[07:56:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[07:56:07] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[07:56:07] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[07:56:07] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[07:56:07] [PASSED] Automatic
[07:56:07] [PASSED] Full
[07:56:07] [PASSED] Limited 16:235
[07:56:07] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[07:56:07] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[07:56:07] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[07:56:07] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[07:56:07] === drm_test_drm_hdmi_connector_get_output_format_name ====
[07:56:07] [PASSED] RGB
[07:56:07] [PASSED] YUV 4:2:0
[07:56:07] [PASSED] YUV 4:2:2
[07:56:07] [PASSED] YUV 4:4:4
[07:56:07] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[07:56:07] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[07:56:07] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[07:56:07] ============= drm_damage_helper (21 subtests) ==============
[07:56:07] [PASSED] drm_test_damage_iter_no_damage
[07:56:07] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[07:56:07] [PASSED] drm_test_damage_iter_no_damage_src_moved
[07:56:07] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[07:56:07] [PASSED] drm_test_damage_iter_no_damage_not_visible
[07:56:07] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[07:56:07] [PASSED] drm_test_damage_iter_no_damage_no_fb
[07:56:07] [PASSED] drm_test_damage_iter_simple_damage
[07:56:07] [PASSED] drm_test_damage_iter_single_damage
[07:56:07] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[07:56:07] [PASSED] drm_test_damage_iter_single_damage_outside_src
[07:56:07] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[07:56:07] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[07:56:07] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[07:56:07] [PASSED] drm_test_damage_iter_single_damage_src_moved
[07:56:07] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[07:56:07] [PASSED] drm_test_damage_iter_damage
[07:56:07] [PASSED] drm_test_damage_iter_damage_one_intersect
[07:56:07] [PASSED] drm_test_damage_iter_damage_one_outside
[07:56:07] [PASSED] drm_test_damage_iter_damage_src_moved
[07:56:07] [PASSED] drm_test_damage_iter_damage_not_visible
[07:56:07] ================ [PASSED] drm_damage_helper ================
[07:56:07] ============== drm_dp_mst_helper (3 subtests) ==============
[07:56:07] ============== drm_test_dp_mst_calc_pbn_mode ==============
[07:56:07] [PASSED] Clock 154000 BPP 30 DSC disabled
[07:56:07] [PASSED] Clock 234000 BPP 30 DSC disabled
[07:56:07] [PASSED] Clock 297000 BPP 24 DSC disabled
[07:56:07] [PASSED] Clock 332880 BPP 24 DSC enabled
[07:56:07] [PASSED] Clock 324540 BPP 24 DSC enabled
[07:56:07] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[07:56:07] ============== drm_test_dp_mst_calc_pbn_div ===============
[07:56:07] [PASSED] Link rate 2000000 lane count 4
[07:56:07] [PASSED] Link rate 2000000 lane count 2
[07:56:07] [PASSED] Link rate 2000000 lane count 1
[07:56:07] [PASSED] Link rate 1350000 lane count 4
[07:56:07] [PASSED] Link rate 1350000 lane count 2
[07:56:07] [PASSED] Link rate 1350000 lane count 1
[07:56:07] [PASSED] Link rate 1000000 lane count 4
[07:56:07] [PASSED] Link rate 1000000 lane count 2
[07:56:07] [PASSED] Link rate 1000000 lane count 1
[07:56:07] [PASSED] Link rate 810000 lane count 4
[07:56:07] [PASSED] Link rate 810000 lane count 2
[07:56:07] [PASSED] Link rate 810000 lane count 1
[07:56:07] [PASSED] Link rate 540000 lane count 4
[07:56:07] [PASSED] Link rate 540000 lane count 2
[07:56:07] [PASSED] Link rate 540000 lane count 1
[07:56:07] [PASSED] Link rate 270000 lane count 4
[07:56:07] [PASSED] Link rate 270000 lane count 2
[07:56:07] [PASSED] Link rate 270000 lane count 1
[07:56:07] [PASSED] Link rate 162000 lane count 4
[07:56:07] [PASSED] Link rate 162000 lane count 2
[07:56:07] [PASSED] Link rate 162000 lane count 1
[07:56:07] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[07:56:07] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[07:56:07] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[07:56:07] [PASSED] DP_POWER_UP_PHY with port number
[07:56:07] [PASSED] DP_POWER_DOWN_PHY with port number
[07:56:07] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[07:56:07] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[07:56:07] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[07:56:07] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[07:56:07] [PASSED] DP_QUERY_PAYLOAD with port number
[07:56:07] [PASSED] DP_QUERY_PAYLOAD with VCPI
[07:56:07] [PASSED] DP_REMOTE_DPCD_READ with port number
[07:56:07] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[07:56:07] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[07:56:07] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[07:56:07] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[07:56:07] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[07:56:07] [PASSED] DP_REMOTE_I2C_READ with port number
[07:56:07] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[07:56:07] [PASSED] DP_REMOTE_I2C_READ with transactions array
[07:56:07] [PASSED] DP_REMOTE_I2C_WRITE with port number
[07:56:07] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[07:56:07] [PASSED] DP_REMOTE_I2C_WRITE with data array
[07:56:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[07:56:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[07:56:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[07:56:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[07:56:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[07:56:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[07:56:07] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[07:56:07] ================ [PASSED] drm_dp_mst_helper ================
[07:56:07] ================== drm_exec (7 subtests) ===================
[07:56:07] [PASSED] sanitycheck
[07:56:07] [PASSED] test_lock
[07:56:07] [PASSED] test_lock_unlock
[07:56:07] [PASSED] test_duplicates
[07:56:07] [PASSED] test_prepare
[07:56:07] [PASSED] test_prepare_array
[07:56:07] [PASSED] test_multiple_loops
[07:56:07] ==================== [PASSED] drm_exec =====================
[07:56:07] =========== drm_format_helper_test (17 subtests) ===========
[07:56:07] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[07:56:07] [PASSED] single_pixel_source_buffer
[07:56:07] [PASSED] single_pixel_clip_rectangle
[07:56:07] [PASSED] well_known_colors
[07:56:07] [PASSED] destination_pitch
[07:56:07] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[07:56:07] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[07:56:07] [PASSED] single_pixel_source_buffer
[07:56:07] [PASSED] single_pixel_clip_rectangle
[07:56:07] [PASSED] well_known_colors
[07:56:07] [PASSED] destination_pitch
[07:56:07] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[07:56:07] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[07:56:07] [PASSED] single_pixel_source_buffer
[07:56:07] [PASSED] single_pixel_clip_rectangle
[07:56:07] [PASSED] well_known_colors
[07:56:07] [PASSED] destination_pitch
[07:56:07] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[07:56:07] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[07:56:07] [PASSED] single_pixel_source_buffer
[07:56:07] [PASSED] single_pixel_clip_rectangle
[07:56:07] [PASSED] well_known_colors
[07:56:07] [PASSED] destination_pitch
[07:56:07] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[07:56:07] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[07:56:07] [PASSED] single_pixel_source_buffer
[07:56:07] [PASSED] single_pixel_clip_rectangle
[07:56:07] [PASSED] well_known_colors
[07:56:07] [PASSED] destination_pitch
[07:56:07] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[07:56:07] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[07:56:07] [PASSED] single_pixel_source_buffer
[07:56:07] [PASSED] single_pixel_clip_rectangle
[07:56:07] [PASSED] well_known_colors
[07:56:07] [PASSED] destination_pitch
[07:56:07] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[07:56:07] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[07:56:07] [PASSED] single_pixel_source_buffer
[07:56:07] [PASSED] single_pixel_clip_rectangle
[07:56:07] [PASSED] well_known_colors
[07:56:07] [PASSED] destination_pitch
[07:56:07] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[07:56:07] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[07:56:07] [PASSED] single_pixel_source_buffer
[07:56:07] [PASSED] single_pixel_clip_rectangle
[07:56:07] [PASSED] well_known_colors
[07:56:07] [PASSED] destination_pitch
[07:56:07] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[07:56:07] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[07:56:07] [PASSED] single_pixel_source_buffer
[07:56:07] [PASSED] single_pixel_clip_rectangle
[07:56:07] [PASSED] well_known_colors
[07:56:07] [PASSED] destination_pitch
[07:56:07] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[07:56:07] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[07:56:07] [PASSED] single_pixel_source_buffer
[07:56:07] [PASSED] single_pixel_clip_rectangle
[07:56:07] [PASSED] well_known_colors
[07:56:07] [PASSED] destination_pitch
[07:56:07] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[07:56:07] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[07:56:07] [PASSED] single_pixel_source_buffer
[07:56:07] [PASSED] single_pixel_clip_rectangle
[07:56:07] [PASSED] well_known_colors
[07:56:07] [PASSED] destination_pitch
[07:56:07] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[07:56:07] ============== drm_test_fb_xrgb8888_to_mono ===============
[07:56:07] [PASSED] single_pixel_source_buffer
[07:56:07] [PASSED] single_pixel_clip_rectangle
[07:56:07] [PASSED] well_known_colors
[07:56:07] [PASSED] destination_pitch
[07:56:07] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[07:56:07] ==================== drm_test_fb_swab =====================
[07:56:07] [PASSED] single_pixel_source_buffer
[07:56:07] [PASSED] single_pixel_clip_rectangle
[07:56:07] [PASSED] well_known_colors
[07:56:07] [PASSED] destination_pitch
[07:56:07] ================ [PASSED] drm_test_fb_swab =================
[07:56:07] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[07:56:07] [PASSED] single_pixel_source_buffer
[07:56:07] [PASSED] single_pixel_clip_rectangle
[07:56:07] [PASSED] well_known_colors
[07:56:07] [PASSED] destination_pitch
[07:56:07] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[07:56:07] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[07:56:07] [PASSED] single_pixel_source_buffer
[07:56:07] [PASSED] single_pixel_clip_rectangle
[07:56:07] [PASSED] well_known_colors
[07:56:07] [PASSED] destination_pitch
[07:56:07] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[07:56:07] ================= drm_test_fb_clip_offset =================
[07:56:07] [PASSED] pass through
[07:56:07] [PASSED] horizontal offset
[07:56:07] [PASSED] vertical offset
[07:56:07] [PASSED] horizontal and vertical offset
[07:56:07] [PASSED] horizontal offset (custom pitch)
[07:56:07] [PASSED] vertical offset (custom pitch)
[07:56:07] [PASSED] horizontal and vertical offset (custom pitch)
[07:56:07] ============= [PASSED] drm_test_fb_clip_offset =============
[07:56:07] =================== drm_test_fb_memcpy ====================
[07:56:07] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[07:56:07] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[07:56:07] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[07:56:07] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[07:56:07] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[07:56:07] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[07:56:07] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[07:56:07] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[07:56:07] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[07:56:07] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[07:56:07] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[07:56:07] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[07:56:07] =============== [PASSED] drm_test_fb_memcpy ================
[07:56:07] ============= [PASSED] drm_format_helper_test ==============
[07:56:07] ================= drm_format (18 subtests) =================
[07:56:07] [PASSED] drm_test_format_block_width_invalid
[07:56:07] [PASSED] drm_test_format_block_width_one_plane
[07:56:07] [PASSED] drm_test_format_block_width_two_plane
[07:56:07] [PASSED] drm_test_format_block_width_three_plane
[07:56:07] [PASSED] drm_test_format_block_width_tiled
[07:56:07] [PASSED] drm_test_format_block_height_invalid
[07:56:07] [PASSED] drm_test_format_block_height_one_plane
[07:56:07] [PASSED] drm_test_format_block_height_two_plane
[07:56:07] [PASSED] drm_test_format_block_height_three_plane
[07:56:07] [PASSED] drm_test_format_block_height_tiled
[07:56:07] [PASSED] drm_test_format_min_pitch_invalid
[07:56:07] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[07:56:07] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[07:56:07] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[07:56:07] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[07:56:07] [PASSED] drm_test_format_min_pitch_two_plane
[07:56:07] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[07:56:07] [PASSED] drm_test_format_min_pitch_tiled
[07:56:07] =================== [PASSED] drm_format ====================
[07:56:07] ============== drm_framebuffer (10 subtests) ===============
[07:56:07] ========== drm_test_framebuffer_check_src_coords ==========
[07:56:07] [PASSED] Success: source fits into fb
[07:56:07] [PASSED] Fail: overflowing fb with x-axis coordinate
[07:56:07] [PASSED] Fail: overflowing fb with y-axis coordinate
[07:56:07] [PASSED] Fail: overflowing fb with source width
[07:56:07] [PASSED] Fail: overflowing fb with source height
[07:56:07] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[07:56:07] [PASSED] drm_test_framebuffer_cleanup
[07:56:07] =============== drm_test_framebuffer_create ===============
[07:56:07] [PASSED] ABGR8888 normal sizes
[07:56:07] [PASSED] ABGR8888 max sizes
[07:56:07] [PASSED] ABGR8888 pitch greater than min required
[07:56:07] [PASSED] ABGR8888 pitch less than min required
[07:56:07] [PASSED] ABGR8888 Invalid width
[07:56:07] [PASSED] ABGR8888 Invalid buffer handle
[07:56:07] [PASSED] No pixel format
[07:56:07] [PASSED] ABGR8888 Width 0
[07:56:07] [PASSED] ABGR8888 Height 0
[07:56:07] [PASSED] ABGR8888 Out of bound height * pitch combination
[07:56:07] [PASSED] ABGR8888 Large buffer offset
[07:56:07] [PASSED] ABGR8888 Buffer offset for inexistent plane
[07:56:07] [PASSED] ABGR8888 Invalid flag
[07:56:07] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[07:56:07] [PASSED] ABGR8888 Valid buffer modifier
[07:56:07] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[07:56:07] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[07:56:07] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[07:56:07] [PASSED] NV12 Normal sizes
[07:56:07] [PASSED] NV12 Max sizes
[07:56:07] [PASSED] NV12 Invalid pitch
[07:56:07] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[07:56:07] [PASSED] NV12 different modifier per-plane
[07:56:07] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[07:56:07] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[07:56:07] [PASSED] NV12 Modifier for inexistent plane
[07:56:07] [PASSED] NV12 Handle for inexistent plane
[07:56:07] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[07:56:07] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[07:56:07] [PASSED] YVU420 Normal sizes
[07:56:07] [PASSED] YVU420 Max sizes
[07:56:07] [PASSED] YVU420 Invalid pitch
[07:56:07] [PASSED] YVU420 Different pitches
[07:56:07] [PASSED] YVU420 Different buffer offsets/pitches
[07:56:07] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[07:56:07] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[07:56:07] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[07:56:07] [PASSED] YVU420 Valid modifier
[07:56:07] [PASSED] YVU420 Different modifiers per plane
[07:56:07] [PASSED] YVU420 Modifier for inexistent plane
[07:56:07] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[07:56:07] [PASSED] X0L2 Normal sizes
[07:56:07] [PASSED] X0L2 Max sizes
[07:56:07] [PASSED] X0L2 Invalid pitch
[07:56:07] [PASSED] X0L2 Pitch greater than minimum required
[07:56:07] [PASSED] X0L2 Handle for inexistent plane
[07:56:07] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[07:56:07] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[07:56:07] [PASSED] X0L2 Valid modifier
[07:56:07] [PASSED] X0L2 Modifier for inexistent plane
[07:56:07] =========== [PASSED] drm_test_framebuffer_create ===========
[07:56:07] [PASSED] drm_test_framebuffer_free
[07:56:07] [PASSED] drm_test_framebuffer_init
[07:56:07] [PASSED] drm_test_framebuffer_init_bad_format
[07:56:07] [PASSED] drm_test_framebuffer_init_dev_mismatch
[07:56:07] [PASSED] drm_test_framebuffer_lookup
[07:56:07] [PASSED] drm_test_framebuffer_lookup_inexistent
[07:56:07] [PASSED] drm_test_framebuffer_modifiers_not_supported
[07:56:07] ================= [PASSED] drm_framebuffer =================
[07:56:07] ================ drm_gem_shmem (8 subtests) ================
[07:56:07] [PASSED] drm_gem_shmem_test_obj_create
[07:56:07] [PASSED] drm_gem_shmem_test_obj_create_private
[07:56:07] [PASSED] drm_gem_shmem_test_pin_pages
[07:56:07] [PASSED] drm_gem_shmem_test_vmap
[07:56:07] [PASSED] drm_gem_shmem_test_get_sg_table
[07:56:07] [PASSED] drm_gem_shmem_test_get_pages_sgt
[07:56:07] [PASSED] drm_gem_shmem_test_madvise
[07:56:07] [PASSED] drm_gem_shmem_test_purge
[07:56:07] ================== [PASSED] drm_gem_shmem ==================
[07:56:07] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[07:56:07] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[07:56:07] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[07:56:07] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[07:56:07] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[07:56:07] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[07:56:07] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[07:56:07] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[07:56:07] [PASSED] Automatic
[07:56:07] [PASSED] Full
[07:56:07] [PASSED] Limited 16:235
[07:56:07] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[07:56:07] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[07:56:07] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[07:56:07] [PASSED] drm_test_check_disable_connector
[07:56:07] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[07:56:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[07:56:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[07:56:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[07:56:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[07:56:07] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[07:56:07] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[07:56:07] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[07:56:07] [PASSED] drm_test_check_output_bpc_dvi
[07:56:07] [PASSED] drm_test_check_output_bpc_format_vic_1
[07:56:07] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[07:56:07] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[07:56:07] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[07:56:07] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[07:56:07] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[07:56:07] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[07:56:07] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[07:56:07] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[07:56:07] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[07:56:07] [PASSED] drm_test_check_broadcast_rgb_value
[07:56:07] [PASSED] drm_test_check_bpc_8_value
[07:56:07] [PASSED] drm_test_check_bpc_10_value
[07:56:07] [PASSED] drm_test_check_bpc_12_value
[07:56:07] [PASSED] drm_test_check_format_value
[07:56:07] [PASSED] drm_test_check_tmds_char_value
[07:56:07] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[07:56:07] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[07:56:07] [PASSED] drm_test_check_mode_valid
[07:56:07] [PASSED] drm_test_check_mode_valid_reject
[07:56:07] [PASSED] drm_test_check_mode_valid_reject_rate
[07:56:07] [PASSED] drm_test_check_mode_valid_reject_max_clock
[07:56:07] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[07:56:07] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[07:56:07] [PASSED] drm_test_check_infoframes
[07:56:07] [PASSED] drm_test_check_reject_avi_infoframe
[07:56:07] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[07:56:07] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[07:56:07] [PASSED] drm_test_check_reject_audio_infoframe
[07:56:07] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[07:56:07] ================= drm_managed (2 subtests) =================
[07:56:07] [PASSED] drm_test_managed_release_action
[07:56:07] [PASSED] drm_test_managed_run_action
[07:56:07] =================== [PASSED] drm_managed ===================
[07:56:07] =================== drm_mm (6 subtests) ====================
[07:56:07] [PASSED] drm_test_mm_init
[07:56:07] [PASSED] drm_test_mm_debug
[07:56:07] [PASSED] drm_test_mm_align32
[07:56:07] [PASSED] drm_test_mm_align64
[07:56:07] [PASSED] drm_test_mm_lowest
[07:56:07] [PASSED] drm_test_mm_highest
[07:56:07] ===================== [PASSED] drm_mm ======================
[07:56:07] ============= drm_modes_analog_tv (5 subtests) =============
[07:56:07] [PASSED] drm_test_modes_analog_tv_mono_576i
[07:56:07] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[07:56:07] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[07:56:07] [PASSED] drm_test_modes_analog_tv_pal_576i
[07:56:07] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[07:56:07] =============== [PASSED] drm_modes_analog_tv ===============
[07:56:07] ============== drm_plane_helper (2 subtests) ===============
[07:56:07] =============== drm_test_check_plane_state ================
[07:56:07] [PASSED] clipping_simple
[07:56:07] [PASSED] clipping_rotate_reflect
[07:56:07] [PASSED] positioning_simple
[07:56:07] [PASSED] upscaling
[07:56:07] [PASSED] downscaling
[07:56:07] [PASSED] rounding1
[07:56:07] [PASSED] rounding2
[07:56:07] [PASSED] rounding3
[07:56:07] [PASSED] rounding4
[07:56:07] =========== [PASSED] drm_test_check_plane_state ============
[07:56:07] =========== drm_test_check_invalid_plane_state ============
[07:56:07] [PASSED] positioning_invalid
[07:56:07] [PASSED] upscaling_invalid
[07:56:07] [PASSED] downscaling_invalid
[07:56:07] ======= [PASSED] drm_test_check_invalid_plane_state ========
[07:56:07] ================ [PASSED] drm_plane_helper =================
[07:56:07] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[07:56:07] ====== drm_test_connector_helper_tv_get_modes_check =======
[07:56:07] [PASSED] None
[07:56:07] [PASSED] PAL
[07:56:07] [PASSED] NTSC
[07:56:07] [PASSED] Both, NTSC Default
[07:56:07] [PASSED] Both, PAL Default
[07:56:07] [PASSED] Both, NTSC Default, with PAL on command-line
[07:56:07] [PASSED] Both, PAL Default, with NTSC on command-line
[07:56:07] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[07:56:07] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[07:56:07] ================== drm_rect (9 subtests) ===================
[07:56:07] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[07:56:07] [PASSED] drm_test_rect_clip_scaled_not_clipped
[07:56:07] [PASSED] drm_test_rect_clip_scaled_clipped
[07:56:07] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[07:56:07] ================= drm_test_rect_intersect =================
[07:56:07] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[07:56:07] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[07:56:07] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[07:56:07] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[07:56:07] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[07:56:07] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[07:56:07] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[07:56:07] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[07:56:07] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[07:56:07] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[07:56:07] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[07:56:07] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[07:56:07] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[07:56:07] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[07:56:07] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[07:56:07] ============= [PASSED] drm_test_rect_intersect =============
[07:56:07] ================ drm_test_rect_calc_hscale ================
[07:56:07] [PASSED] normal use
[07:56:07] [PASSED] out of max range
[07:56:07] [PASSED] out of min range
[07:56:07] [PASSED] zero dst
[07:56:07] [PASSED] negative src
[07:56:07] [PASSED] negative dst
[07:56:07] ============ [PASSED] drm_test_rect_calc_hscale ============
[07:56:07] ================ drm_test_rect_calc_vscale ================
[07:56:07] [PASSED] normal use
[07:56:07] [PASSED] out of max range
[07:56:07] [PASSED] out of min range
[07:56:07] [PASSED] zero dst
[07:56:07] [PASSED] negative src
[07:56:07] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[07:56:07] ============ [PASSED] drm_test_rect_calc_vscale ============
[07:56:07] ================== drm_test_rect_rotate ===================
[07:56:07] [PASSED] reflect-x
[07:56:07] [PASSED] reflect-y
[07:56:07] [PASSED] rotate-0
[07:56:07] [PASSED] rotate-90
[07:56:07] [PASSED] rotate-180
[07:56:07] [PASSED] rotate-270
[07:56:07] ============== [PASSED] drm_test_rect_rotate ===============
[07:56:07] ================ drm_test_rect_rotate_inv =================
[07:56:07] [PASSED] reflect-x
[07:56:07] [PASSED] reflect-y
[07:56:07] [PASSED] rotate-0
[07:56:07] [PASSED] rotate-90
[07:56:07] [PASSED] rotate-180
[07:56:07] [PASSED] rotate-270
[07:56:07] ============ [PASSED] drm_test_rect_rotate_inv =============
[07:56:07] ==================== [PASSED] drm_rect =====================
[07:56:07] ============ drm_sysfb_modeset_test (1 subtest) ============
[07:56:07] ============ drm_test_sysfb_build_fourcc_list =============
[07:56:07] [PASSED] no native formats
[07:56:07] [PASSED] XRGB8888 as native format
[07:56:07] [PASSED] remove duplicates
[07:56:07] [PASSED] convert alpha formats
[07:56:07] [PASSED] random formats
[07:56:07] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[07:56:07] ============= [PASSED] drm_sysfb_modeset_test ==============
[07:56:07] ================== drm_fixp (2 subtests) ===================
[07:56:07] [PASSED] drm_test_int2fixp
[07:56:07] [PASSED] drm_test_sm2fixp
[07:56:07] ==================== [PASSED] drm_fixp =====================
[07:56:07] ============================================================
[07:56:07] Testing complete. Ran 621 tests: passed: 621
[07:56:07] Elapsed time: 25.929s total, 1.733s configuring, 24.028s building, 0.118s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[07:56:07] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:56:09] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:56:18] Starting KUnit Kernel (1/1)...
[07:56:18] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:56:18] ================= ttm_device (5 subtests) ==================
[07:56:18] [PASSED] ttm_device_init_basic
[07:56:18] [PASSED] ttm_device_init_multiple
[07:56:18] [PASSED] ttm_device_fini_basic
[07:56:18] [PASSED] ttm_device_init_no_vma_man
[07:56:18] ================== ttm_device_init_pools ==================
[07:56:18] [PASSED] No DMA allocations, no DMA32 required
[07:56:18] [PASSED] DMA allocations, DMA32 required
[07:56:18] [PASSED] No DMA allocations, DMA32 required
[07:56:18] [PASSED] DMA allocations, no DMA32 required
[07:56:18] ============== [PASSED] ttm_device_init_pools ==============
[07:56:18] =================== [PASSED] ttm_device ====================
[07:56:18] ================== ttm_pool (8 subtests) ===================
[07:56:18] ================== ttm_pool_alloc_basic ===================
[07:56:18] [PASSED] One page
[07:56:18] [PASSED] More than one page
[07:56:18] [PASSED] Above the allocation limit
[07:56:18] [PASSED] One page, with coherent DMA mappings enabled
[07:56:18] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:56:18] ============== [PASSED] ttm_pool_alloc_basic ===============
[07:56:18] ============== ttm_pool_alloc_basic_dma_addr ==============
[07:56:18] [PASSED] One page
[07:56:18] [PASSED] More than one page
[07:56:18] [PASSED] Above the allocation limit
[07:56:18] [PASSED] One page, with coherent DMA mappings enabled
[07:56:18] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:56:18] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[07:56:18] [PASSED] ttm_pool_alloc_order_caching_match
[07:56:18] [PASSED] ttm_pool_alloc_caching_mismatch
[07:56:18] [PASSED] ttm_pool_alloc_order_mismatch
[07:56:18] [PASSED] ttm_pool_free_dma_alloc
[07:56:18] [PASSED] ttm_pool_free_no_dma_alloc
[07:56:18] [PASSED] ttm_pool_fini_basic
[07:56:18] ==================== [PASSED] ttm_pool =====================
[07:56:18] ================ ttm_resource (8 subtests) =================
[07:56:18] ================= ttm_resource_init_basic =================
[07:56:18] [PASSED] Init resource in TTM_PL_SYSTEM
[07:56:18] [PASSED] Init resource in TTM_PL_VRAM
[07:56:18] [PASSED] Init resource in a private placement
[07:56:18] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[07:56:18] ============= [PASSED] ttm_resource_init_basic =============
[07:56:18] [PASSED] ttm_resource_init_pinned
[07:56:18] [PASSED] ttm_resource_fini_basic
[07:56:18] [PASSED] ttm_resource_manager_init_basic
[07:56:18] [PASSED] ttm_resource_manager_usage_basic
[07:56:18] [PASSED] ttm_resource_manager_set_used_basic
[07:56:18] [PASSED] ttm_sys_man_alloc_basic
[07:56:18] [PASSED] ttm_sys_man_free_basic
[07:56:18] ================== [PASSED] ttm_resource ===================
[07:56:18] =================== ttm_tt (15 subtests) ===================
[07:56:18] ==================== ttm_tt_init_basic ====================
[07:56:18] [PASSED] Page-aligned size
[07:56:18] [PASSED] Extra pages requested
[07:56:18] ================ [PASSED] ttm_tt_init_basic ================
[07:56:18] [PASSED] ttm_tt_init_misaligned
[07:56:18] [PASSED] ttm_tt_fini_basic
[07:56:18] [PASSED] ttm_tt_fini_sg
[07:56:18] [PASSED] ttm_tt_fini_shmem
[07:56:18] [PASSED] ttm_tt_create_basic
[07:56:18] [PASSED] ttm_tt_create_invalid_bo_type
[07:56:18] [PASSED] ttm_tt_create_ttm_exists
[07:56:18] [PASSED] ttm_tt_create_failed
[07:56:18] [PASSED] ttm_tt_destroy_basic
[07:56:18] [PASSED] ttm_tt_populate_null_ttm
[07:56:18] [PASSED] ttm_tt_populate_populated_ttm
[07:56:18] [PASSED] ttm_tt_unpopulate_basic
[07:56:18] [PASSED] ttm_tt_unpopulate_empty_ttm
[07:56:18] [PASSED] ttm_tt_swapin_basic
[07:56:18] ===================== [PASSED] ttm_tt ======================
[07:56:18] =================== ttm_bo (14 subtests) ===================
[07:56:18] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[07:56:18] [PASSED] Cannot be interrupted and sleeps
[07:56:18] [PASSED] Cannot be interrupted, locks straight away
[07:56:18] [PASSED] Can be interrupted, sleeps
[07:56:18] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[07:56:18] [PASSED] ttm_bo_reserve_locked_no_sleep
[07:56:18] [PASSED] ttm_bo_reserve_no_wait_ticket
[07:56:18] [PASSED] ttm_bo_reserve_double_resv
[07:56:18] [PASSED] ttm_bo_reserve_interrupted
[07:56:18] [PASSED] ttm_bo_reserve_deadlock
[07:56:18] [PASSED] ttm_bo_unreserve_basic
[07:56:18] [PASSED] ttm_bo_unreserve_pinned
[07:56:18] [PASSED] ttm_bo_unreserve_bulk
[07:56:18] [PASSED] ttm_bo_fini_basic
[07:56:18] [PASSED] ttm_bo_fini_shared_resv
[07:56:18] [PASSED] ttm_bo_pin_basic
[07:56:18] [PASSED] ttm_bo_pin_unpin_resource
[07:56:18] [PASSED] ttm_bo_multiple_pin_one_unpin
[07:56:18] ===================== [PASSED] ttm_bo ======================
[07:56:18] ============== ttm_bo_validate (21 subtests) ===============
[07:56:18] ============== ttm_bo_init_reserved_sys_man ===============
[07:56:18] [PASSED] Buffer object for userspace
[07:56:18] [PASSED] Kernel buffer object
[07:56:18] [PASSED] Shared buffer object
[07:56:18] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[07:56:18] ============== ttm_bo_init_reserved_mock_man ==============
[07:56:18] [PASSED] Buffer object for userspace
[07:56:18] [PASSED] Kernel buffer object
[07:56:18] [PASSED] Shared buffer object
[07:56:18] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[07:56:18] [PASSED] ttm_bo_init_reserved_resv
[07:56:18] ================== ttm_bo_validate_basic ==================
[07:56:18] [PASSED] Buffer object for userspace
[07:56:18] [PASSED] Kernel buffer object
[07:56:18] [PASSED] Shared buffer object
[07:56:18] ============== [PASSED] ttm_bo_validate_basic ==============
[07:56:18] [PASSED] ttm_bo_validate_invalid_placement
[07:56:18] ============= ttm_bo_validate_same_placement ==============
[07:56:18] [PASSED] System manager
[07:56:18] [PASSED] VRAM manager
[07:56:18] ========= [PASSED] ttm_bo_validate_same_placement ==========
[07:56:18] [PASSED] ttm_bo_validate_failed_alloc
[07:56:18] [PASSED] ttm_bo_validate_pinned
[07:56:18] [PASSED] ttm_bo_validate_busy_placement
[07:56:18] ================ ttm_bo_validate_multihop =================
[07:56:18] [PASSED] Buffer object for userspace
[07:56:18] [PASSED] Kernel buffer object
[07:56:18] [PASSED] Shared buffer object
[07:56:18] ============ [PASSED] ttm_bo_validate_multihop =============
[07:56:18] ========== ttm_bo_validate_no_placement_signaled ==========
[07:56:18] [PASSED] Buffer object in system domain, no page vector
[07:56:18] [PASSED] Buffer object in system domain with an existing page vector
[07:56:18] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[07:56:18] ======== ttm_bo_validate_no_placement_not_signaled ========
[07:56:18] [PASSED] Buffer object for userspace
[07:56:18] [PASSED] Kernel buffer object
[07:56:18] [PASSED] Shared buffer object
[07:56:18] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[07:56:18] [PASSED] ttm_bo_validate_move_fence_signaled
[07:56:19] ========= ttm_bo_validate_move_fence_not_signaled =========
[07:56:19] [PASSED] Waits for GPU
[07:56:19] [PASSED] Tries to lock straight away
[07:56:19] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[07:56:19] [PASSED] ttm_bo_validate_happy_evict
[07:56:19] [PASSED] ttm_bo_validate_all_pinned_evict
[07:56:19] [PASSED] ttm_bo_validate_allowed_only_evict
[07:56:19] [PASSED] ttm_bo_validate_deleted_evict
[07:56:19] [PASSED] ttm_bo_validate_busy_domain_evict
[07:56:19] [PASSED] ttm_bo_validate_evict_gutting
[07:56:19] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[07:56:19] ================= [PASSED] ttm_bo_validate =================
[07:56:19] ============================================================
[07:56:19] Testing complete. Ran 101 tests: passed: 101
[07:56:19] Elapsed time: 11.402s total, 1.692s configuring, 9.493s building, 0.177s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx
2026-02-20 5:01 ` Murthy, Arun R
@ 2026-02-24 8:24 ` Ville Syrjälä
2026-02-24 8:48 ` Murthy, Arun R
0 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2026-02-24 8:24 UTC (permalink / raw)
To: Murthy, Arun R; +Cc: intel-gfx, intel-xe, imre.deak, suraj.kandpal
On Fri, Feb 20, 2026 at 10:31:10AM +0530, Murthy, Arun R wrote:
>
> On 20-02-2026 08:41, Ville Syrjälä wrote:
> > On Thu, Feb 19, 2026 at 08:42:49PM +0530, Murthy, Arun R wrote:
> >> On 19-02-2026 20:23, Ville Syrjälä wrote:
> >>> On Thu, Feb 19, 2026 at 03:13:26PM +0530, Arun R Murthy wrote:
> >>>> Before reading the DPCD caps for eDP wake the sink device and for DP
> >>>> after reading the lttpr caps and before reading the dpcd caps wake up
> >>>> the sink device.
> >>> Why?
> >> Just to ensure that sink is awake.
> >> On eDP init, as part of reading the DPCD caps during the AUX transaction
> >> its sometimes observed that the AUX tx fails with timeout. In those
> >> scenarios even if the retry is increased to 1000 AUX tx will not
> >> succeed. May be that sink is in sleep or unknown state.
> >> Spec DP2.1 sec 2.11.7.1.5.8 says if there is a NO REPLY for AUX tx this
> >> can be due to illegal cmd or sink in low power state.
> > That section is specifically about i2c-over-aux.
> >
> > Generally we have retries and appropriate timeouts to deal with AUX
> > having to wake up from low power state.
> We have tried this for 1000 times and didnt work.
Tried it where/when/what? I still have no idea what you're trying to
solve here.
> This leaves a question as to why not replying even after 1000 trials.
> Answer might be the command/request is wrong for which sink is not able
> to understand. But its not the case.
> So the other thinking is "is the sink in low power mode" ?
> In link training sections of the spec it says before starting link
> training ensure that sink is up and provides steps to wake the sink device.
> Example: Section 3.5.2.16
We already do that (intel_dp_set_power()). Though even then we seem
to doing the OUI DPCD stuff before the D3->D0 transition. So that still
assumes that any random DPCD accesses work while in D3. Why we do it in
that order I have no idea.
>
> > Although, I suppose we might consider switching to D0 for eg. duration
> > of the detection to make sure none of the AUX transactions there take
> > too long. That *might* make things a bit faster (but we'd need actual
> > numbers to show that). And once we're done we should switch back to D3
> > to save power.
> I am doing that in the patch. I switch to D0 and then immediately switch
> to D3_AUX_ON state.
D3_AUX_ON isn't even a thing in the older DP versions.
> The reason for reading DP_SET_POWER in a loop is the spec says that DPTX
> should try for atleast 3 times as DPRX is waking from power saving state
> which takes 1ms.
> Section 2.3.5 explains the DPRX AUX_CH state and says that DPRX shall
> avoid not issuing a reply when waking from a power saving state.
> This section also explains the DPRX AUX_CH state on RESET. Usually this
> is the state on power on, and in the issue that we are referring to can
> also be co-related to this state as its during the kernel boot/driver
> probe.
> > Perhaps we could then also use a larger timeout just for
> > the DP_SET_POWER AUX accesses,
> spec mention on this time as 1ms, to allow sink to exit low power mode
> or AUX_CH Receiver is monitoring differential signals (sec 2.3.1.2)
> > and all other AUX accesses could assume
> > that the thing is awake and use a smaller timeout. Although the LTTPR
> > mess probably means we can't actually reduce the timeouts :/
> >
> > Another slight snag in the current way of doing things is that IIRC
> > we never put a device into D3 after the initial detection, unless we
> > actually turned the main link on and off again. That's also something
> > that could get fixed by always putting the device into D3 after
> > detection. But to do that stuff safely we'd need some way to make sure
> > nothing else (eg. the main link) requires the D0 at that time. So some
> > kind of D0 vs. D3 reference counting scheme might be needed.
> >
> > I did consider implementing something like that years ago, but dealing
> > with the reference counting seemed too messy at the time. And since I
> > never implemented it I never measured it either. Perhaps things are a
> > bit cleaner these days to make that easier. Dunno.
> >
> >> So in this patch we are trying to wake the sink device.
> > Still the same question remains: Why? What *exactly* is the problem
> > you're trying to solve here?
> The problem we are trying to solve is that the AUX_CH Requested is not
> succeeding even after sending multiple AUX requests and fails to get a
> response from the AUX_CH Replier.
> Increasing the retry count to a large value (1000) is also not helping.
>
> In order to solve this went through the spec in detail, able to get some
> information scattered over multiple sections leaving us to a thinking
> that may be AUX_CH Replier in low power state. Also in link training
> section(3.5.2.16) it says source should wake the sink before starting
> link training.
>
> Thanks and Regards,
> Arun R Murthy
> -------------------
>
> >> Thanks and Regards,
> >> Arun R Murthy
> >> -------------------
> >>
> >>>> Closes: https://issues.redhat.com/browse/RHEL-120913
> >>>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> >>>> ---
> >>>> drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++++++
> >>>> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> >>>> .../drm/i915/display/intel_dp_link_training.c | 3 ++
> >>>> 3 files changed, 45 insertions(+)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> >>>> index 454e6144ee4e..2fbb947e6cc8 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >>>> @@ -4705,6 +4705,45 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
> >>>> intel_edp_set_data_override_rates(intel_dp);
> >>>> }
> >>>>
> >>>> +void intel_dp_wake_sink(struct intel_dp *intel_dp)
> >>>> +{
> >>>> + u8 value = 0;
> >>>> + int ret = 0, try = 0;
> >>>> +
> >>>> + intel_dp_dpcd_set_probe(intel_dp, false);
> >>>> +
> >>>> + /*
> >>>> + * Wake the sink device
> >>>> + * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by writing 0x02
> >>>> + * to DP_SET_POWER dpcd reg, 1ms time would be required to wake it up
> >>>> + */
> >>>> + while (try < 10 && ret < 0) {
> >>>> + ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value);
> >>>> + /*
> >>>> + * If sink is in D3 then it may not respond to the AUX tx so
> >>>> + * wake it up to D3_AUX_ON state
> >>>> + */
> >>>> + if (value == DP_SET_POWER_D3) {
> >>>> + /* After setting to D0 need a min of 1ms to wake(Spec DP2.1 sec 2.3.1.2) */
> >>>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> >>>> + DP_SET_POWER_D0);
> >>>> + fsleep(1000);
> >>>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> >>>> + DP_SET_POWER_D3_AUX_ON);
> >>>> + break;
> >>>> + } else if ((value == DP_SET_POWER_D0) ||
> >>>> + (value == DP_SET_POWER_D3_AUX_ON)) {
> >>>> + /* if in D0 or D3_AUX_ON exit */
> >>>> + break;
> >>>> + }
> >>>> + /* Sink in D0 or even if read fails a minimum of 1ms is required to wake and respond */
> >>>> + fsleep(1000);
> >>>> + try++;
> >>>> + }
> >>>> +
> >>>> + intel_dp_dpcd_set_probe(intel_dp, true);
> >>>> +}
> >>>> +
> >>>> static bool
> >>>> intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
> >>>> {
> >>>> @@ -4713,6 +4752,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
> >>>> /* this function is meant to be called only once */
> >>>> drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
> >>>>
> >>>> + intel_dp_wake_sink(intel_dp);
> >>>> +
> >>>> if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
> >>>> return false;
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> >>>> index b0bbd5981f57..3f16077c0cc7 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> >>>> @@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
> >>>> bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
> >>>> int hdisplay,
> >>>> int num_joined_pipes);
> >>>> +void intel_dp_wake_sink(struct intel_dp *intel_dp);
> >>>>
> >>>> #define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
> >>>> for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >>>> index 54c585c59b90..cbb712ea9f60 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >>>> @@ -270,6 +270,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
> >>>> lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
> >>>> }
> >>>>
> >>>> + /* After reading LTTPR wake up the sink before reading DPRX caps */
> >>>> + intel_dp_wake_sink(intel_dp);
> >>>> +
> >>>> /*
> >>>> * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
> >>>> * it here.
> >>>> --
> >>>> 2.25.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx
2026-02-24 8:24 ` Ville Syrjälä
@ 2026-02-24 8:48 ` Murthy, Arun R
0 siblings, 0 replies; 24+ messages in thread
From: Murthy, Arun R @ 2026-02-24 8:48 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe, imre.deak, suraj.kandpal
[-- Attachment #1: Type: text/plain, Size: 9878 bytes --]
On 24-02-2026 13:54, Ville Syrjälä wrote:
> On Fri, Feb 20, 2026 at 10:31:10AM +0530, Murthy, Arun R wrote:
>> On 20-02-2026 08:41, Ville Syrjälä wrote:
>>> On Thu, Feb 19, 2026 at 08:42:49PM +0530, Murthy, Arun R wrote:
>>>> On 19-02-2026 20:23, Ville Syrjälä wrote:
>>>>> On Thu, Feb 19, 2026 at 03:13:26PM +0530, Arun R Murthy wrote:
>>>>>> Before reading the DPCD caps for eDP wake the sink device and for DP
>>>>>> after reading the lttpr caps and before reading the dpcd caps wake up
>>>>>> the sink device.
>>>>> Why?
>>>> Just to ensure that sink is awake.
>>>> On eDP init, as part of reading the DPCD caps during the AUX transaction
>>>> its sometimes observed that the AUX tx fails with timeout. In those
>>>> scenarios even if the retry is increased to 1000 AUX tx will not
>>>> succeed. May be that sink is in sleep or unknown state.
>>>> Spec DP2.1 sec 2.11.7.1.5.8 says if there is a NO REPLY for AUX tx this
>>>> can be due to illegal cmd or sink in low power state.
>>> That section is specifically about i2c-over-aux.
>>>
>>> Generally we have retries and appropriate timeouts to deal with AUX
>>> having to wake up from low power state.
>> We have tried this for 1000 times and didnt work.
> Tried it where/when/what? I still have no idea what you're trying to
> solve here.
The issue is https://issues.redhat.com/browse/RHEL-120913 In aux_xfer
function intel_dp_aux_wait_done times out and fails. The retry count is
5. eDP is plugged in and powered-up, so should respond.
We tried to increase the retry count to 1000, even that didnt help,
issue is still reproduced. The solution to this issue is what we are
trying to fix in this issue, explained below.
Thanks and Regards, Arun R Murthy -------------------
>> This leaves a question as to why not replying even after 1000 trials.
>> Answer might be the command/request is wrong for which sink is not able
>> to understand. But its not the case.
>> So the other thinking is "is the sink in low power mode" ?
>> In link training sections of the spec it says before starting link
>> training ensure that sink is up and provides steps to wake the sink device.
>> Example: Section 3.5.2.16
> We already do that (intel_dp_set_power()). Though even then we seem
> to doing the OUI DPCD stuff before the D3->D0 transition. So that still
> assumes that any random DPCD accesses work while in D3. Why we do it in
> that order I have no idea.
>
>>> Although, I suppose we might consider switching to D0 for eg. duration
>>> of the detection to make sure none of the AUX transactions there take
>>> too long. That *might* make things a bit faster (but we'd need actual
>>> numbers to show that). And once we're done we should switch back to D3
>>> to save power.
>> I am doing that in the patch. I switch to D0 and then immediately switch
>> to D3_AUX_ON state.
> D3_AUX_ON isn't even a thing in the older DP versions.
>
>> The reason for reading DP_SET_POWER in a loop is the spec says that DPTX
>> should try for atleast 3 times as DPRX is waking from power saving state
>> which takes 1ms.
>> Section 2.3.5 explains the DPRX AUX_CH state and says that DPRX shall
>> avoid not issuing a reply when waking from a power saving state.
>> This section also explains the DPRX AUX_CH state on RESET. Usually this
>> is the state on power on, and in the issue that we are referring to can
>> also be co-related to this state as its during the kernel boot/driver
>> probe.
>>> Perhaps we could then also use a larger timeout just for
>>> the DP_SET_POWER AUX accesses,
>> spec mention on this time as 1ms, to allow sink to exit low power mode
>> or AUX_CH Receiver is monitoring differential signals (sec 2.3.1.2)
>>> and all other AUX accesses could assume
>>> that the thing is awake and use a smaller timeout. Although the LTTPR
>>> mess probably means we can't actually reduce the timeouts :/
>>>
>>> Another slight snag in the current way of doing things is that IIRC
>>> we never put a device into D3 after the initial detection, unless we
>>> actually turned the main link on and off again. That's also something
>>> that could get fixed by always putting the device into D3 after
>>> detection. But to do that stuff safely we'd need some way to make sure
>>> nothing else (eg. the main link) requires the D0 at that time. So some
>>> kind of D0 vs. D3 reference counting scheme might be needed.
>>>
>>> I did consider implementing something like that years ago, but dealing
>>> with the reference counting seemed too messy at the time. And since I
>>> never implemented it I never measured it either. Perhaps things are a
>>> bit cleaner these days to make that easier. Dunno.
>>>
>>>> So in this patch we are trying to wake the sink device.
>>> Still the same question remains: Why? What *exactly* is the problem
>>> you're trying to solve here?
>> The problem we are trying to solve is that the AUX_CH Requested is not
>> succeeding even after sending multiple AUX requests and fails to get a
>> response from the AUX_CH Replier.
>> Increasing the retry count to a large value (1000) is also not helping.
>>
>> In order to solve this went through the spec in detail, able to get some
>> information scattered over multiple sections leaving us to a thinking
>> that may be AUX_CH Replier in low power state. Also in link training
>> section(3.5.2.16) it says source should wake the sink before starting
>> link training.
>>
>> Thanks and Regards,
>> Arun R Murthy
>> -------------------
>>
>>>> Thanks and Regards,
>>>> Arun R Murthy
>>>> -------------------
>>>>
>>>>>> Closes:https://issues.redhat.com/browse/RHEL-120913
>>>>>> Signed-off-by: Arun R Murthy<arun.r.murthy@intel.com>
>>>>>> ---
>>>>>> drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++++++
>>>>>> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
>>>>>> .../drm/i915/display/intel_dp_link_training.c | 3 ++
>>>>>> 3 files changed, 45 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>>>>> index 454e6144ee4e..2fbb947e6cc8 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>>>> @@ -4705,6 +4705,45 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
>>>>>> intel_edp_set_data_override_rates(intel_dp);
>>>>>> }
>>>>>>
>>>>>> +void intel_dp_wake_sink(struct intel_dp *intel_dp)
>>>>>> +{
>>>>>> + u8 value = 0;
>>>>>> + int ret = 0, try = 0;
>>>>>> +
>>>>>> + intel_dp_dpcd_set_probe(intel_dp, false);
>>>>>> +
>>>>>> + /*
>>>>>> + * Wake the sink device
>>>>>> + * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by writing 0x02
>>>>>> + * to DP_SET_POWER dpcd reg, 1ms time would be required to wake it up
>>>>>> + */
>>>>>> + while (try < 10 && ret < 0) {
>>>>>> + ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value);
>>>>>> + /*
>>>>>> + * If sink is in D3 then it may not respond to the AUX tx so
>>>>>> + * wake it up to D3_AUX_ON state
>>>>>> + */
>>>>>> + if (value == DP_SET_POWER_D3) {
>>>>>> + /* After setting to D0 need a min of 1ms to wake(Spec DP2.1 sec 2.3.1.2) */
>>>>>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>>>>>> + DP_SET_POWER_D0);
>>>>>> + fsleep(1000);
>>>>>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>>>>>> + DP_SET_POWER_D3_AUX_ON);
>>>>>> + break;
>>>>>> + } else if ((value == DP_SET_POWER_D0) ||
>>>>>> + (value == DP_SET_POWER_D3_AUX_ON)) {
>>>>>> + /* if in D0 or D3_AUX_ON exit */
>>>>>> + break;
>>>>>> + }
>>>>>> + /* Sink in D0 or even if read fails a minimum of 1ms is required to wake and respond */
>>>>>> + fsleep(1000);
>>>>>> + try++;
>>>>>> + }
>>>>>> +
>>>>>> + intel_dp_dpcd_set_probe(intel_dp, true);
>>>>>> +}
>>>>>> +
>>>>>> static bool
>>>>>> intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
>>>>>> {
>>>>>> @@ -4713,6 +4752,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
>>>>>> /* this function is meant to be called only once */
>>>>>> drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
>>>>>>
>>>>>> + intel_dp_wake_sink(intel_dp);
>>>>>> +
>>>>>> if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
>>>>>> return false;
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>>>>>> index b0bbd5981f57..3f16077c0cc7 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>>>>>> @@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
>>>>>> bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>>>>>> int hdisplay,
>>>>>> int num_joined_pipes);
>>>>>> +void intel_dp_wake_sink(struct intel_dp *intel_dp);
>>>>>>
>>>>>> #define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
>>>>>> for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>>>>> index 54c585c59b90..cbb712ea9f60 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>>>>> @@ -270,6 +270,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
>>>>>> lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
>>>>>> }
>>>>>>
>>>>>> + /* After reading LTTPR wake up the sink before reading DPRX caps */
>>>>>> + intel_dp_wake_sink(intel_dp);
>>>>>> +
>>>>>> /*
>>>>>> * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
>>>>>> * it here.
>>>>>> --
>>>>>> 2.25.1
[-- Attachment #2: Type: text/html, Size: 12095 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCHv2] drm/i915/dp: On DPCD init/caps wake the DPRx
2026-02-24 7:48 ` [PATCHv2] " Arun R Murthy
@ 2026-02-24 14:50 ` Imre Deak
2026-02-25 3:33 ` Murthy, Arun R
0 siblings, 1 reply; 24+ messages in thread
From: Imre Deak @ 2026-02-24 14:50 UTC (permalink / raw)
To: Arun R Murthy
Cc: intel-gfx, intel-xe, suraj.kandpal, jani.nikula, ville.syrjala
On Tue, Feb 24, 2026 at 01:18:30PM +0530, Arun R Murthy wrote:
> Its observed that on AUX_CH failure, even if the retry is increased to
> 1000, it does not succeed. Either the command might be wrong or sink in
> an unknown/sleep state can cause this. So try waking the sink device.
> Before reading the DPCD caps wake the sink for eDP and for DP after
> reading the lttpr caps if present and before reading the dpcd caps wake
> up the sink device.
>
> v2: Use poll_timeout_us (Jani N)
> Add the reason, why this change is required (Ville)
>
> Closes: https://issues.redhat.com/browse/RHEL-120913
I wonder what should be the rule with non-public links like the above.
For instance, we do not put VLK-xxx links exactly because those are
non-public. Should/could we demand that RedHat opens a public ticket?
Jani?
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 38 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> .../drm/i915/display/intel_dp_link_training.c | 3 ++
> 3 files changed, 42 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 025e906b63a9..fa0730f7b92a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4705,6 +4705,42 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
> intel_edp_set_data_override_rates(intel_dp);
> }
>
> +/* Spec says to try for 3 times, its doubled to add the software overhead */
> +#define AUX_CH_WAKE_RETRY 6
> +
> +void intel_dp_wake_sink(struct intel_dp *intel_dp)
> +{
> + u8 value = 0;
> + int ret = 0;
> +
> + intel_dp_dpcd_set_probe(intel_dp, false);
Is there any particular reason to turn off/on the probing? I don't see
any reason why the DP_SET_POWER polling would need that. In any case
turning it off/on this way is not ok: reading the DPRX caps, which would
call this function, could happen at any time after a sink gets
connected, so turning probing back on at the end of this function would
re-enable it incorrectly for sinks where it's been already established
that the probing workaround is not needed and should stay disabled.
> +
> + /*
> + * Wake the sink device
> + * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by writing 0x02
> + * to DP_SET_POWER dpcd reg, 1ms time would be required to wake it up
> + */
> + ret = poll_timeout_us(ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value),
> + ret > 0,
> + 1000, AUX_CH_WAKE_RETRY * 1000, true);
> +
> + /*
> + * If sink is in D3 then it may not respond to the AUX tx so
> + * wake it up to D3_AUX_ON state
> + * If the above poll_timeout_us fails, try waking the sink.
> + */
> + if (value == DP_SET_POWER_D3 || ret < 0) {
> + /* After setting to D0 need a min of 1ms to wake(Spec DP2.1 sec 2.3.1.2) */
> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> + DP_SET_POWER_D0);
> + fsleep(1000);
> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> + DP_SET_POWER_D3_AUX_ON);
> + }
> +
> + intel_dp_dpcd_set_probe(intel_dp, true);
> +}
> +
> static bool
> intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
> {
> @@ -4713,6 +4749,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
> /* this function is meant to be called only once */
> drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
>
> + intel_dp_wake_sink(intel_dp);
> +
> if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
> return false;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index b0bbd5981f57..3f16077c0cc7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
> bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
> int hdisplay,
> int num_joined_pipes);
> +void intel_dp_wake_sink(struct intel_dp *intel_dp);
>
> #define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
> for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 54c585c59b90..cbb712ea9f60 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -270,6 +270,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
> lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
> }
>
> + /* After reading LTTPR wake up the sink before reading DPRX caps */
> + intel_dp_wake_sink(intel_dp);
> +
> /*
> * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
> * it here.
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCHv2] drm/i915/dp: On DPCD init/caps wake the DPRx
2026-02-24 14:50 ` Imre Deak
@ 2026-02-25 3:33 ` Murthy, Arun R
2026-02-25 5:58 ` Murthy, Arun R
2026-03-02 7:57 ` Imre Deak
0 siblings, 2 replies; 24+ messages in thread
From: Murthy, Arun R @ 2026-02-25 3:33 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx, intel-xe, suraj.kandpal, jani.nikula, ville.syrjala
On 24-02-2026 20:20, Imre Deak wrote:
> On Tue, Feb 24, 2026 at 01:18:30PM +0530, Arun R Murthy wrote:
>> Its observed that on AUX_CH failure, even if the retry is increased to
>> 1000, it does not succeed. Either the command might be wrong or sink in
>> an unknown/sleep state can cause this. So try waking the sink device.
>> Before reading the DPCD caps wake the sink for eDP and for DP after
>> reading the lttpr caps if present and before reading the dpcd caps wake
>> up the sink device.
>>
>> v2: Use poll_timeout_us (Jani N)
>> Add the reason, why this change is required (Ville)
>>
>> Closes: https://issues.redhat.com/browse/RHEL-120913
> I wonder what should be the rule with non-public links like the above.
> For instance, we do not put VLK-xxx links exactly because those are
> non-public. Should/could we demand that RedHat opens a public ticket?
> Jani?
There is a JIRA as well
https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 38 +++++++++++++++++++
>> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
>> .../drm/i915/display/intel_dp_link_training.c | 3 ++
>> 3 files changed, 42 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 025e906b63a9..fa0730f7b92a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -4705,6 +4705,42 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
>> intel_edp_set_data_override_rates(intel_dp);
>> }
>>
>> +/* Spec says to try for 3 times, its doubled to add the software overhead */
>> +#define AUX_CH_WAKE_RETRY 6
>> +
>> +void intel_dp_wake_sink(struct intel_dp *intel_dp)
>> +{
>> + u8 value = 0;
>> + int ret = 0;
>> +
>> + intel_dp_dpcd_set_probe(intel_dp, false);
> Is there any particular reason to turn off/on the probing? I don't see
> any reason why the DP_SET_POWER polling would need that. In any case
> turning it off/on this way is not ok: reading the DPRX caps, which would
> call this function, could happen at any time after a sink gets
> connected, so turning probing back on at the end of this function would
> re-enable it incorrectly for sinks where it's been already established
> that the probing workaround is not needed and should stay disabled.
This function intel_dp_wake_sink() is called from edp_init_dpcd and
dp_init_lttpr_dprx_caps.
dpcd_set_probe is set to true in dp_aux_init which is called before
calling intel_edp_init_connector.
Probe is set to true, hence in this function I am setting it to false
and then setting back to true.
But there can be a possibility of reading lttpr_dprx_caps being called
later as well.
Will correct this to check if probe is already being set to true, will
then disable before waking the sink and restore the probe status at the end.
Will get this corrected in the next revision.
Thanks and Regards,
Arun R Murthy
-------------------
>> +
>> + /*
>> + * Wake the sink device
>> + * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by writing 0x02
>> + * to DP_SET_POWER dpcd reg, 1ms time would be required to wake it up
>> + */
>> + ret = poll_timeout_us(ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value),
>> + ret > 0,
>> + 1000, AUX_CH_WAKE_RETRY * 1000, true);
>> +
>> + /*
>> + * If sink is in D3 then it may not respond to the AUX tx so
>> + * wake it up to D3_AUX_ON state
>> + * If the above poll_timeout_us fails, try waking the sink.
>> + */
>> + if (value == DP_SET_POWER_D3 || ret < 0) {
>> + /* After setting to D0 need a min of 1ms to wake(Spec DP2.1 sec 2.3.1.2) */
>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>> + DP_SET_POWER_D0);
>> + fsleep(1000);
>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>> + DP_SET_POWER_D3_AUX_ON);
>> + }
>> +
>> + intel_dp_dpcd_set_probe(intel_dp, true);
>> +}
>> +
>> static bool
>> intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
>> {
>> @@ -4713,6 +4749,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
>> /* this function is meant to be called only once */
>> drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
>>
>> + intel_dp_wake_sink(intel_dp);
>> +
>> if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
>> return false;
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index b0bbd5981f57..3f16077c0cc7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
>> bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>> int hdisplay,
>> int num_joined_pipes);
>> +void intel_dp_wake_sink(struct intel_dp *intel_dp);
>>
>> #define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
>> for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index 54c585c59b90..cbb712ea9f60 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -270,6 +270,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
>> lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
>> }
>>
>> + /* After reading LTTPR wake up the sink before reading DPRX caps */
>> + intel_dp_wake_sink(intel_dp);
>> +
>> /*
>> * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
>> * it here.
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCHv2] drm/i915/dp: On DPCD init/caps wake the DPRx
2026-02-25 3:33 ` Murthy, Arun R
@ 2026-02-25 5:58 ` Murthy, Arun R
2026-03-02 7:57 ` Imre Deak
1 sibling, 0 replies; 24+ messages in thread
From: Murthy, Arun R @ 2026-02-25 5:58 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx, intel-xe, suraj.kandpal, jani.nikula, ville.syrjala
On 25-02-2026 09:03, Murthy, Arun R wrote:
>
> On 24-02-2026 20:20, Imre Deak wrote:
>> On Tue, Feb 24, 2026 at 01:18:30PM +0530, Arun R Murthy wrote:
>>> Its observed that on AUX_CH failure, even if the retry is increased to
>>> 1000, it does not succeed. Either the command might be wrong or sink in
>>> an unknown/sleep state can cause this. So try waking the sink device.
>>> Before reading the DPCD caps wake the sink for eDP and for DP after
>>> reading the lttpr caps if present and before reading the dpcd caps wake
>>> up the sink device.
>>>
>>> v2: Use poll_timeout_us (Jani N)
>>> Add the reason, why this change is required (Ville)
>>>
>>> Closes: https://issues.redhat.com/browse/RHEL-120913
>> I wonder what should be the rule with non-public links like the above.
>> For instance, we do not put VLK-xxx links exactly because those are
>> non-public. Should/could we demand that RedHat opens a public ticket?
>> Jani?
> There is a JIRA as well
> https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
>>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_dp.c | 38
>>> +++++++++++++++++++
>>> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
>>> .../drm/i915/display/intel_dp_link_training.c | 3 ++
>>> 3 files changed, 42 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>>> b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index 025e906b63a9..fa0730f7b92a 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -4705,6 +4705,42 @@ intel_edp_set_sink_rates(struct intel_dp
>>> *intel_dp)
>>> intel_edp_set_data_override_rates(intel_dp);
>>> }
>>> +/* Spec says to try for 3 times, its doubled to add the software
>>> overhead */
>>> +#define AUX_CH_WAKE_RETRY 6
>>> +
>>> +void intel_dp_wake_sink(struct intel_dp *intel_dp)
>>> +{
>>> + u8 value = 0;
>>> + int ret = 0;
>>> +
>>> + intel_dp_dpcd_set_probe(intel_dp, false);
>> Is there any particular reason to turn off/on the probing? I don't see
>> any reason why the DP_SET_POWER polling would need that. In any case
>> turning it off/on this way is not ok: reading the DPRX caps, which would
>> call this function, could happen at any time after a sink gets
>> connected, so turning probing back on at the end of this function would
>> re-enable it incorrectly for sinks where it's been already established
>> that the probing workaround is not needed and should stay disabled.
> This function intel_dp_wake_sink() is called from edp_init_dpcd and
> dp_init_lttpr_dprx_caps.
> dpcd_set_probe is set to true in dp_aux_init which is called before
> calling intel_edp_init_connector.
>
> Probe is set to true, hence in this function I am setting it to false
> and then setting back to true.
> But there can be a possibility of reading lttpr_dprx_caps being called
> later as well.
>
> Will correct this to check if probe is already being set to true, will
> then disable before waking the sink and restore the probe status at
> the end.
>
> Will get this corrected in the next revision.
>
I will drop the fix for DP from this patch and take it up later.
In this patch will only target fix for eDP for which dpcd probe will not
be required as per intel_dp_needs_dpcd_probe()
Thanks and Regards,
Arun R Murthy
-------------------
> Thanks and Regards,
> Arun R Murthy
> -------------------
>
>>> +
>>> + /*
>>> + * Wake the sink device
>>> + * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by
>>> writing 0x02
>>> + * to DP_SET_POWER dpcd reg, 1ms time would be required to wake
>>> it up
>>> + */
>>> + ret = poll_timeout_us(ret = drm_dp_dpcd_readb(&intel_dp->aux,
>>> DP_SET_POWER, &value),
>>> + ret > 0,
>>> + 1000, AUX_CH_WAKE_RETRY * 1000, true);
>>> +
>>> + /*
>>> + * If sink is in D3 then it may not respond to the AUX tx so
>>> + * wake it up to D3_AUX_ON state
>>> + * If the above poll_timeout_us fails, try waking the sink.
>>> + */
>>> + if (value == DP_SET_POWER_D3 || ret < 0) {
>>> + /* After setting to D0 need a min of 1ms to wake(Spec DP2.1
>>> sec 2.3.1.2) */
>>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>>> + DP_SET_POWER_D0);
>>> + fsleep(1000);
>>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>>> + DP_SET_POWER_D3_AUX_ON);
>>> + }
>>> +
>>> + intel_dp_dpcd_set_probe(intel_dp, true);
>>> +}
>>> +
>>> static bool
>>> intel_edp_init_dpcd(struct intel_dp *intel_dp, struct
>>> intel_connector *connector)
>>> {
>>> @@ -4713,6 +4749,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp,
>>> struct intel_connector *connector
>>> /* this function is meant to be called only once */
>>> drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
>>> + intel_dp_wake_sink(intel_dp);
>>> +
>>> if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
>>> return false;
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
>>> b/drivers/gpu/drm/i915/display/intel_dp.h
>>> index b0bbd5981f57..3f16077c0cc7 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>>> @@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display
>>> *display,
>>> bool intel_dp_joiner_candidate_valid(struct intel_connector
>>> *connector,
>>> int hdisplay,
>>> int num_joined_pipes);
>>> +void intel_dp_wake_sink(struct intel_dp *intel_dp);
>>> #define for_each_joiner_candidate(__connector, __mode,
>>> __num_joined_pipes) \
>>> for ((__num_joined_pipes) = 1; (__num_joined_pipes) <=
>>> (I915_MAX_PIPES); (__num_joined_pipes)++) \
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>> index 54c585c59b90..cbb712ea9f60 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>> @@ -270,6 +270,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct
>>> intel_dp *intel_dp)
>>> lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
>>> }
>>> + /* After reading LTTPR wake up the sink before reading DPRX
>>> caps */
>>> + intel_dp_wake_sink(intel_dp);
>>> +
>>> /*
>>> * The DPTX shall read the DPRX caps after LTTPR detection, so
>>> re-read
>>> * it here.
>>> --
>>> 2.25.1
>>>
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCHv3] drm/i915/dp: On DPCD init wake the DPRx for eDP
2026-02-19 9:43 [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx Arun R Murthy
` (6 preceding siblings ...)
2026-02-24 7:56 ` ✓ CI.KUnit: success for drm/i915/dp: On DPCD init/caps wake the DPRx (rev2) Patchwork
@ 2026-02-25 6:11 ` Arun R Murthy
2026-02-25 6:19 ` ✓ CI.KUnit: success for drm/i915/dp: On DPCD init/caps wake the DPRx (rev3) Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Arun R Murthy @ 2026-02-25 6:11 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: imre.deak, suraj.kandpal, jani.nikula, ville.syrjala,
Arun R Murthy
Its observed that on AUX_CH failure, even if the retry is increased to
1000, it does not succeed. Either the command might be wrong or sink in
an unknown/sleep state can cause this. So try waking the sink device.
Before reading the DPCD caps wake the sink for eDP.
v2: Use poll_timeout_us (Jani N)
Add the reason, why this change is required (Ville)
v3: Wake sink only for eDP
Remove the dpcd probe set to true/false in wake_sink (Imre)
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
2 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 025e906b63a9..38ea4aad74de 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4705,6 +4705,38 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
intel_edp_set_data_override_rates(intel_dp);
}
+/* Spec says to try for 3 times, its doubled to add the software overhead */
+#define AUX_CH_WAKE_RETRY 6
+
+void intel_dp_wake_sink(struct intel_dp *intel_dp)
+{
+ u8 value = 0;
+ int ret = 0;
+
+ /*
+ * Wake the sink device
+ * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by writing 0x02
+ * to DP_SET_POWER dpcd reg, 1ms time would be required to wake it up
+ */
+ ret = poll_timeout_us(ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value),
+ ret > 0,
+ 1000, AUX_CH_WAKE_RETRY * 1000, true);
+
+ /*
+ * If sink is in D3 then it may not respond to the AUX tx so
+ * wake it up to D3_AUX_ON state
+ * If the above poll_timeout_us fails, try waking the sink.
+ */
+ if (value == DP_SET_POWER_D3 || ret < 0) {
+ /* After setting to D0 need a min of 1ms to wake(Spec DP2.1 sec 2.3.1.2) */
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
+ DP_SET_POWER_D0);
+ fsleep(1000);
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
+ DP_SET_POWER_D3_AUX_ON);
+ }
+}
+
static bool
intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
{
@@ -4713,6 +4745,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
/* this function is meant to be called only once */
drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
+ intel_dp_wake_sink(intel_dp);
+
if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
return false;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index b0bbd5981f57..3f16077c0cc7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
int hdisplay,
int num_joined_pipes);
+void intel_dp_wake_sink(struct intel_dp *intel_dp);
#define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* ✓ CI.KUnit: success for drm/i915/dp: On DPCD init/caps wake the DPRx (rev3)
2026-02-19 9:43 [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx Arun R Murthy
` (7 preceding siblings ...)
2026-02-25 6:11 ` [PATCHv3] drm/i915/dp: On DPCD init wake the DPRx for eDP Arun R Murthy
@ 2026-02-25 6:19 ` Patchwork
2026-02-25 6:56 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-25 11:20 ` ✗ Xe.CI.FULL: failure " Patchwork
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2026-02-25 6:19 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-xe
== Series Details ==
Series: drm/i915/dp: On DPCD init/caps wake the DPRx (rev3)
URL : https://patchwork.freedesktop.org/series/161817/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[06:18:04] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:18:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:18:39] Starting KUnit Kernel (1/1)...
[06:18:39] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:18:39] ================== guc_buf (11 subtests) ===================
[06:18:39] [PASSED] test_smallest
[06:18:39] [PASSED] test_largest
[06:18:39] [PASSED] test_granular
[06:18:39] [PASSED] test_unique
[06:18:39] [PASSED] test_overlap
[06:18:39] [PASSED] test_reusable
[06:18:39] [PASSED] test_too_big
[06:18:39] [PASSED] test_flush
[06:18:39] [PASSED] test_lookup
[06:18:39] [PASSED] test_data
[06:18:39] [PASSED] test_class
[06:18:39] ===================== [PASSED] guc_buf =====================
[06:18:39] =================== guc_dbm (7 subtests) ===================
[06:18:39] [PASSED] test_empty
[06:18:39] [PASSED] test_default
[06:18:39] ======================== test_size ========================
[06:18:39] [PASSED] 4
[06:18:39] [PASSED] 8
[06:18:39] [PASSED] 32
[06:18:39] [PASSED] 256
[06:18:39] ==================== [PASSED] test_size ====================
[06:18:39] ======================= test_reuse ========================
[06:18:39] [PASSED] 4
[06:18:39] [PASSED] 8
[06:18:39] [PASSED] 32
[06:18:39] [PASSED] 256
[06:18:39] =================== [PASSED] test_reuse ====================
[06:18:39] =================== test_range_overlap ====================
[06:18:39] [PASSED] 4
[06:18:39] [PASSED] 8
[06:18:39] [PASSED] 32
[06:18:39] [PASSED] 256
[06:18:39] =============== [PASSED] test_range_overlap ================
[06:18:39] =================== test_range_compact ====================
[06:18:39] [PASSED] 4
[06:18:39] [PASSED] 8
[06:18:39] [PASSED] 32
[06:18:39] [PASSED] 256
[06:18:39] =============== [PASSED] test_range_compact ================
[06:18:39] ==================== test_range_spare =====================
[06:18:39] [PASSED] 4
[06:18:39] [PASSED] 8
[06:18:39] [PASSED] 32
[06:18:39] [PASSED] 256
[06:18:39] ================ [PASSED] test_range_spare =================
[06:18:39] ===================== [PASSED] guc_dbm =====================
[06:18:39] =================== guc_idm (6 subtests) ===================
[06:18:39] [PASSED] bad_init
[06:18:39] [PASSED] no_init
[06:18:39] [PASSED] init_fini
[06:18:39] [PASSED] check_used
[06:18:39] [PASSED] check_quota
[06:18:39] [PASSED] check_all
[06:18:39] ===================== [PASSED] guc_idm =====================
[06:18:39] ================== no_relay (3 subtests) ===================
[06:18:39] [PASSED] xe_drops_guc2pf_if_not_ready
[06:18:39] [PASSED] xe_drops_guc2vf_if_not_ready
[06:18:39] [PASSED] xe_rejects_send_if_not_ready
[06:18:39] ==================== [PASSED] no_relay =====================
[06:18:39] ================== pf_relay (14 subtests) ==================
[06:18:39] [PASSED] pf_rejects_guc2pf_too_short
[06:18:39] [PASSED] pf_rejects_guc2pf_too_long
[06:18:39] [PASSED] pf_rejects_guc2pf_no_payload
[06:18:39] [PASSED] pf_fails_no_payload
[06:18:39] [PASSED] pf_fails_bad_origin
[06:18:39] [PASSED] pf_fails_bad_type
[06:18:39] [PASSED] pf_txn_reports_error
[06:18:39] [PASSED] pf_txn_sends_pf2guc
[06:18:39] [PASSED] pf_sends_pf2guc
[06:18:39] [SKIPPED] pf_loopback_nop
[06:18:39] [SKIPPED] pf_loopback_echo
[06:18:39] [SKIPPED] pf_loopback_fail
[06:18:39] [SKIPPED] pf_loopback_busy
[06:18:39] [SKIPPED] pf_loopback_retry
[06:18:39] ==================== [PASSED] pf_relay =====================
[06:18:39] ================== vf_relay (3 subtests) ===================
[06:18:39] [PASSED] vf_rejects_guc2vf_too_short
[06:18:39] [PASSED] vf_rejects_guc2vf_too_long
[06:18:39] [PASSED] vf_rejects_guc2vf_no_payload
[06:18:39] ==================== [PASSED] vf_relay =====================
[06:18:39] ================ pf_gt_config (9 subtests) =================
[06:18:39] [PASSED] fair_contexts_1vf
[06:18:39] [PASSED] fair_doorbells_1vf
[06:18:39] [PASSED] fair_ggtt_1vf
[06:18:39] ====================== fair_vram_1vf ======================
[06:18:39] [PASSED] 3.50 GiB
[06:18:39] [PASSED] 11.5 GiB
[06:18:39] [PASSED] 15.5 GiB
[06:18:39] [PASSED] 31.5 GiB
[06:18:39] [PASSED] 63.5 GiB
[06:18:39] [PASSED] 13.9 GiB
[06:18:39] ================== [PASSED] fair_vram_1vf ==================
[06:18:39] ================ fair_vram_1vf_admin_only =================
[06:18:39] [PASSED] 3.50 GiB
[06:18:39] [PASSED] 11.5 GiB
[06:18:39] [PASSED] 15.5 GiB
[06:18:39] [PASSED] 31.5 GiB
[06:18:39] [PASSED] 63.5 GiB
[06:18:39] [PASSED] 13.9 GiB
[06:18:39] ============ [PASSED] fair_vram_1vf_admin_only =============
[06:18:39] ====================== fair_contexts ======================
[06:18:39] [PASSED] 1 VF
[06:18:39] [PASSED] 2 VFs
[06:18:39] [PASSED] 3 VFs
[06:18:39] [PASSED] 4 VFs
[06:18:39] [PASSED] 5 VFs
[06:18:39] [PASSED] 6 VFs
[06:18:39] [PASSED] 7 VFs
[06:18:39] [PASSED] 8 VFs
[06:18:39] [PASSED] 9 VFs
[06:18:39] [PASSED] 10 VFs
[06:18:39] [PASSED] 11 VFs
[06:18:39] [PASSED] 12 VFs
[06:18:39] [PASSED] 13 VFs
[06:18:39] [PASSED] 14 VFs
[06:18:39] [PASSED] 15 VFs
[06:18:39] [PASSED] 16 VFs
[06:18:39] [PASSED] 17 VFs
[06:18:39] [PASSED] 18 VFs
[06:18:39] [PASSED] 19 VFs
[06:18:39] [PASSED] 20 VFs
[06:18:39] [PASSED] 21 VFs
[06:18:39] [PASSED] 22 VFs
[06:18:39] [PASSED] 23 VFs
[06:18:39] [PASSED] 24 VFs
[06:18:39] [PASSED] 25 VFs
[06:18:39] [PASSED] 26 VFs
[06:18:39] [PASSED] 27 VFs
[06:18:39] [PASSED] 28 VFs
[06:18:39] [PASSED] 29 VFs
[06:18:39] [PASSED] 30 VFs
[06:18:39] [PASSED] 31 VFs
[06:18:39] [PASSED] 32 VFs
[06:18:39] [PASSED] 33 VFs
[06:18:39] [PASSED] 34 VFs
[06:18:39] [PASSED] 35 VFs
[06:18:39] [PASSED] 36 VFs
[06:18:39] [PASSED] 37 VFs
[06:18:39] [PASSED] 38 VFs
[06:18:39] [PASSED] 39 VFs
[06:18:39] [PASSED] 40 VFs
[06:18:39] [PASSED] 41 VFs
[06:18:39] [PASSED] 42 VFs
[06:18:39] [PASSED] 43 VFs
[06:18:39] [PASSED] 44 VFs
[06:18:39] [PASSED] 45 VFs
[06:18:39] [PASSED] 46 VFs
[06:18:39] [PASSED] 47 VFs
[06:18:39] [PASSED] 48 VFs
[06:18:39] [PASSED] 49 VFs
[06:18:39] [PASSED] 50 VFs
[06:18:39] [PASSED] 51 VFs
[06:18:39] [PASSED] 52 VFs
[06:18:39] [PASSED] 53 VFs
[06:18:39] [PASSED] 54 VFs
[06:18:39] [PASSED] 55 VFs
[06:18:39] [PASSED] 56 VFs
[06:18:39] [PASSED] 57 VFs
[06:18:39] [PASSED] 58 VFs
[06:18:39] [PASSED] 59 VFs
[06:18:39] [PASSED] 60 VFs
[06:18:39] [PASSED] 61 VFs
[06:18:39] [PASSED] 62 VFs
[06:18:39] [PASSED] 63 VFs
[06:18:39] ================== [PASSED] fair_contexts ==================
[06:18:39] ===================== fair_doorbells ======================
[06:18:39] [PASSED] 1 VF
[06:18:39] [PASSED] 2 VFs
[06:18:39] [PASSED] 3 VFs
[06:18:39] [PASSED] 4 VFs
[06:18:39] [PASSED] 5 VFs
[06:18:39] [PASSED] 6 VFs
[06:18:39] [PASSED] 7 VFs
[06:18:39] [PASSED] 8 VFs
[06:18:39] [PASSED] 9 VFs
[06:18:39] [PASSED] 10 VFs
[06:18:39] [PASSED] 11 VFs
[06:18:39] [PASSED] 12 VFs
[06:18:39] [PASSED] 13 VFs
[06:18:39] [PASSED] 14 VFs
[06:18:39] [PASSED] 15 VFs
[06:18:39] [PASSED] 16 VFs
[06:18:39] [PASSED] 17 VFs
[06:18:39] [PASSED] 18 VFs
[06:18:39] [PASSED] 19 VFs
[06:18:39] [PASSED] 20 VFs
[06:18:39] [PASSED] 21 VFs
[06:18:39] [PASSED] 22 VFs
[06:18:39] [PASSED] 23 VFs
[06:18:39] [PASSED] 24 VFs
[06:18:39] [PASSED] 25 VFs
[06:18:39] [PASSED] 26 VFs
[06:18:39] [PASSED] 27 VFs
[06:18:39] [PASSED] 28 VFs
[06:18:39] [PASSED] 29 VFs
[06:18:39] [PASSED] 30 VFs
[06:18:39] [PASSED] 31 VFs
[06:18:39] [PASSED] 32 VFs
[06:18:39] [PASSED] 33 VFs
[06:18:39] [PASSED] 34 VFs
[06:18:39] [PASSED] 35 VFs
[06:18:39] [PASSED] 36 VFs
[06:18:39] [PASSED] 37 VFs
[06:18:39] [PASSED] 38 VFs
[06:18:39] [PASSED] 39 VFs
[06:18:39] [PASSED] 40 VFs
[06:18:39] [PASSED] 41 VFs
[06:18:39] [PASSED] 42 VFs
[06:18:39] [PASSED] 43 VFs
[06:18:39] [PASSED] 44 VFs
[06:18:39] [PASSED] 45 VFs
[06:18:39] [PASSED] 46 VFs
[06:18:39] [PASSED] 47 VFs
[06:18:39] [PASSED] 48 VFs
[06:18:39] [PASSED] 49 VFs
[06:18:39] [PASSED] 50 VFs
[06:18:39] [PASSED] 51 VFs
[06:18:39] [PASSED] 52 VFs
[06:18:39] [PASSED] 53 VFs
[06:18:39] [PASSED] 54 VFs
[06:18:39] [PASSED] 55 VFs
[06:18:39] [PASSED] 56 VFs
[06:18:39] [PASSED] 57 VFs
[06:18:39] [PASSED] 58 VFs
[06:18:39] [PASSED] 59 VFs
[06:18:39] [PASSED] 60 VFs
[06:18:39] [PASSED] 61 VFs
[06:18:39] [PASSED] 62 VFs
[06:18:39] [PASSED] 63 VFs
[06:18:39] ================= [PASSED] fair_doorbells ==================
[06:18:39] ======================== fair_ggtt ========================
[06:18:39] [PASSED] 1 VF
[06:18:39] [PASSED] 2 VFs
[06:18:39] [PASSED] 3 VFs
[06:18:39] [PASSED] 4 VFs
[06:18:39] [PASSED] 5 VFs
[06:18:39] [PASSED] 6 VFs
[06:18:39] [PASSED] 7 VFs
[06:18:39] [PASSED] 8 VFs
[06:18:39] [PASSED] 9 VFs
[06:18:39] [PASSED] 10 VFs
[06:18:39] [PASSED] 11 VFs
[06:18:39] [PASSED] 12 VFs
[06:18:39] [PASSED] 13 VFs
[06:18:39] [PASSED] 14 VFs
[06:18:39] [PASSED] 15 VFs
[06:18:39] [PASSED] 16 VFs
[06:18:39] [PASSED] 17 VFs
[06:18:39] [PASSED] 18 VFs
[06:18:39] [PASSED] 19 VFs
[06:18:39] [PASSED] 20 VFs
[06:18:39] [PASSED] 21 VFs
[06:18:39] [PASSED] 22 VFs
[06:18:39] [PASSED] 23 VFs
[06:18:39] [PASSED] 24 VFs
[06:18:39] [PASSED] 25 VFs
[06:18:39] [PASSED] 26 VFs
[06:18:39] [PASSED] 27 VFs
[06:18:39] [PASSED] 28 VFs
[06:18:39] [PASSED] 29 VFs
[06:18:39] [PASSED] 30 VFs
[06:18:39] [PASSED] 31 VFs
[06:18:39] [PASSED] 32 VFs
[06:18:39] [PASSED] 33 VFs
[06:18:39] [PASSED] 34 VFs
[06:18:39] [PASSED] 35 VFs
[06:18:39] [PASSED] 36 VFs
[06:18:39] [PASSED] 37 VFs
[06:18:39] [PASSED] 38 VFs
[06:18:39] [PASSED] 39 VFs
[06:18:39] [PASSED] 40 VFs
[06:18:39] [PASSED] 41 VFs
[06:18:39] [PASSED] 42 VFs
[06:18:39] [PASSED] 43 VFs
[06:18:39] [PASSED] 44 VFs
[06:18:39] [PASSED] 45 VFs
[06:18:39] [PASSED] 46 VFs
[06:18:39] [PASSED] 47 VFs
[06:18:39] [PASSED] 48 VFs
[06:18:39] [PASSED] 49 VFs
[06:18:39] [PASSED] 50 VFs
[06:18:39] [PASSED] 51 VFs
[06:18:39] [PASSED] 52 VFs
[06:18:39] [PASSED] 53 VFs
[06:18:39] [PASSED] 54 VFs
[06:18:39] [PASSED] 55 VFs
[06:18:39] [PASSED] 56 VFs
[06:18:39] [PASSED] 57 VFs
[06:18:39] [PASSED] 58 VFs
[06:18:39] [PASSED] 59 VFs
[06:18:39] [PASSED] 60 VFs
[06:18:39] [PASSED] 61 VFs
[06:18:39] [PASSED] 62 VFs
[06:18:39] [PASSED] 63 VFs
[06:18:39] ==================== [PASSED] fair_ggtt ====================
[06:18:39] ======================== fair_vram ========================
[06:18:39] [PASSED] 1 VF
[06:18:39] [PASSED] 2 VFs
[06:18:39] [PASSED] 3 VFs
[06:18:39] [PASSED] 4 VFs
[06:18:39] [PASSED] 5 VFs
[06:18:39] [PASSED] 6 VFs
[06:18:39] [PASSED] 7 VFs
[06:18:39] [PASSED] 8 VFs
[06:18:39] [PASSED] 9 VFs
[06:18:39] [PASSED] 10 VFs
[06:18:39] [PASSED] 11 VFs
[06:18:39] [PASSED] 12 VFs
[06:18:39] [PASSED] 13 VFs
[06:18:39] [PASSED] 14 VFs
[06:18:39] [PASSED] 15 VFs
[06:18:39] [PASSED] 16 VFs
[06:18:39] [PASSED] 17 VFs
[06:18:39] [PASSED] 18 VFs
[06:18:39] [PASSED] 19 VFs
[06:18:39] [PASSED] 20 VFs
[06:18:39] [PASSED] 21 VFs
[06:18:39] [PASSED] 22 VFs
[06:18:39] [PASSED] 23 VFs
[06:18:39] [PASSED] 24 VFs
[06:18:39] [PASSED] 25 VFs
[06:18:39] [PASSED] 26 VFs
[06:18:39] [PASSED] 27 VFs
[06:18:39] [PASSED] 28 VFs
[06:18:39] [PASSED] 29 VFs
[06:18:39] [PASSED] 30 VFs
[06:18:39] [PASSED] 31 VFs
[06:18:39] [PASSED] 32 VFs
[06:18:39] [PASSED] 33 VFs
[06:18:39] [PASSED] 34 VFs
[06:18:39] [PASSED] 35 VFs
[06:18:39] [PASSED] 36 VFs
[06:18:39] [PASSED] 37 VFs
[06:18:39] [PASSED] 38 VFs
[06:18:39] [PASSED] 39 VFs
[06:18:39] [PASSED] 40 VFs
[06:18:39] [PASSED] 41 VFs
[06:18:39] [PASSED] 42 VFs
[06:18:39] [PASSED] 43 VFs
[06:18:39] [PASSED] 44 VFs
[06:18:39] [PASSED] 45 VFs
[06:18:39] [PASSED] 46 VFs
[06:18:39] [PASSED] 47 VFs
[06:18:39] [PASSED] 48 VFs
[06:18:39] [PASSED] 49 VFs
[06:18:39] [PASSED] 50 VFs
[06:18:39] [PASSED] 51 VFs
[06:18:39] [PASSED] 52 VFs
[06:18:39] [PASSED] 53 VFs
[06:18:39] [PASSED] 54 VFs
[06:18:39] [PASSED] 55 VFs
[06:18:39] [PASSED] 56 VFs
[06:18:39] [PASSED] 57 VFs
[06:18:39] [PASSED] 58 VFs
[06:18:39] [PASSED] 59 VFs
[06:18:39] [PASSED] 60 VFs
[06:18:39] [PASSED] 61 VFs
[06:18:39] [PASSED] 62 VFs
[06:18:39] [PASSED] 63 VFs
[06:18:39] ==================== [PASSED] fair_vram ====================
[06:18:39] ================== [PASSED] pf_gt_config ===================
[06:18:39] ===================== lmtt (1 subtest) =====================
[06:18:39] ======================== test_ops =========================
[06:18:39] [PASSED] 2-level
[06:18:39] [PASSED] multi-level
[06:18:39] ==================== [PASSED] test_ops =====================
[06:18:39] ====================== [PASSED] lmtt =======================
[06:18:39] ================= pf_service (11 subtests) =================
[06:18:39] [PASSED] pf_negotiate_any
[06:18:39] [PASSED] pf_negotiate_base_match
[06:18:39] [PASSED] pf_negotiate_base_newer
[06:18:39] [PASSED] pf_negotiate_base_next
[06:18:39] [SKIPPED] pf_negotiate_base_older
[06:18:39] [PASSED] pf_negotiate_base_prev
[06:18:39] [PASSED] pf_negotiate_latest_match
[06:18:39] [PASSED] pf_negotiate_latest_newer
[06:18:39] [PASSED] pf_negotiate_latest_next
[06:18:39] [SKIPPED] pf_negotiate_latest_older
[06:18:39] [SKIPPED] pf_negotiate_latest_prev
[06:18:39] =================== [PASSED] pf_service ====================
[06:18:39] ================= xe_guc_g2g (2 subtests) ==================
[06:18:39] ============== xe_live_guc_g2g_kunit_default ==============
[06:18:39] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[06:18:39] ============== xe_live_guc_g2g_kunit_allmem ===============
[06:18:39] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[06:18:39] =================== [SKIPPED] xe_guc_g2g ===================
[06:18:39] =================== xe_mocs (2 subtests) ===================
[06:18:39] ================ xe_live_mocs_kernel_kunit ================
[06:18:39] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[06:18:39] ================ xe_live_mocs_reset_kunit =================
[06:18:39] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[06:18:39] ==================== [SKIPPED] xe_mocs =====================
[06:18:39] ================= xe_migrate (2 subtests) ==================
[06:18:39] ================= xe_migrate_sanity_kunit =================
[06:18:39] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[06:18:39] ================== xe_validate_ccs_kunit ==================
[06:18:39] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[06:18:39] =================== [SKIPPED] xe_migrate ===================
[06:18:39] ================== xe_dma_buf (1 subtest) ==================
[06:18:39] ==================== xe_dma_buf_kunit =====================
[06:18:39] ================ [SKIPPED] xe_dma_buf_kunit ================
[06:18:39] =================== [SKIPPED] xe_dma_buf ===================
[06:18:39] ================= xe_bo_shrink (1 subtest) =================
[06:18:39] =================== xe_bo_shrink_kunit ====================
[06:18:39] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[06:18:39] ================== [SKIPPED] xe_bo_shrink ==================
[06:18:39] ==================== xe_bo (2 subtests) ====================
[06:18:39] ================== xe_ccs_migrate_kunit ===================
[06:18:39] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[06:18:39] ==================== xe_bo_evict_kunit ====================
[06:18:39] =============== [SKIPPED] xe_bo_evict_kunit ================
[06:18:39] ===================== [SKIPPED] xe_bo ======================
[06:18:39] ==================== args (13 subtests) ====================
[06:18:39] [PASSED] count_args_test
[06:18:39] [PASSED] call_args_example
[06:18:39] [PASSED] call_args_test
[06:18:39] [PASSED] drop_first_arg_example
[06:18:39] [PASSED] drop_first_arg_test
[06:18:39] [PASSED] first_arg_example
[06:18:39] [PASSED] first_arg_test
[06:18:39] [PASSED] last_arg_example
[06:18:39] [PASSED] last_arg_test
[06:18:39] [PASSED] pick_arg_example
[06:18:39] [PASSED] if_args_example
[06:18:39] [PASSED] if_args_test
[06:18:39] [PASSED] sep_comma_example
[06:18:39] ====================== [PASSED] args =======================
[06:18:39] =================== xe_pci (3 subtests) ====================
[06:18:39] ==================== check_graphics_ip ====================
[06:18:39] [PASSED] 12.00 Xe_LP
[06:18:39] [PASSED] 12.10 Xe_LP+
[06:18:39] [PASSED] 12.55 Xe_HPG
[06:18:39] [PASSED] 12.60 Xe_HPC
[06:18:39] [PASSED] 12.70 Xe_LPG
[06:18:39] [PASSED] 12.71 Xe_LPG
[06:18:39] [PASSED] 12.74 Xe_LPG+
[06:18:39] [PASSED] 20.01 Xe2_HPG
[06:18:39] [PASSED] 20.02 Xe2_HPG
[06:18:39] [PASSED] 20.04 Xe2_LPG
[06:18:39] [PASSED] 30.00 Xe3_LPG
[06:18:39] [PASSED] 30.01 Xe3_LPG
[06:18:39] [PASSED] 30.03 Xe3_LPG
[06:18:39] [PASSED] 30.04 Xe3_LPG
[06:18:39] [PASSED] 30.05 Xe3_LPG
[06:18:39] [PASSED] 35.10 Xe3p_LPG
[06:18:39] [PASSED] 35.11 Xe3p_XPC
[06:18:39] ================ [PASSED] check_graphics_ip ================
[06:18:39] ===================== check_media_ip ======================
[06:18:39] [PASSED] 12.00 Xe_M
[06:18:39] [PASSED] 12.55 Xe_HPM
[06:18:39] [PASSED] 13.00 Xe_LPM+
[06:18:39] [PASSED] 13.01 Xe2_HPM
[06:18:39] [PASSED] 20.00 Xe2_LPM
[06:18:39] [PASSED] 30.00 Xe3_LPM
[06:18:39] [PASSED] 30.02 Xe3_LPM
[06:18:39] [PASSED] 35.00 Xe3p_LPM
[06:18:39] [PASSED] 35.03 Xe3p_HPM
[06:18:39] ================= [PASSED] check_media_ip ==================
[06:18:39] =================== check_platform_desc ===================
[06:18:39] [PASSED] 0x9A60 (TIGERLAKE)
[06:18:39] [PASSED] 0x9A68 (TIGERLAKE)
[06:18:39] [PASSED] 0x9A70 (TIGERLAKE)
[06:18:39] [PASSED] 0x9A40 (TIGERLAKE)
[06:18:39] [PASSED] 0x9A49 (TIGERLAKE)
[06:18:39] [PASSED] 0x9A59 (TIGERLAKE)
[06:18:39] [PASSED] 0x9A78 (TIGERLAKE)
[06:18:39] [PASSED] 0x9AC0 (TIGERLAKE)
[06:18:39] [PASSED] 0x9AC9 (TIGERLAKE)
[06:18:39] [PASSED] 0x9AD9 (TIGERLAKE)
[06:18:39] [PASSED] 0x9AF8 (TIGERLAKE)
[06:18:39] [PASSED] 0x4C80 (ROCKETLAKE)
[06:18:39] [PASSED] 0x4C8A (ROCKETLAKE)
[06:18:39] [PASSED] 0x4C8B (ROCKETLAKE)
[06:18:39] [PASSED] 0x4C8C (ROCKETLAKE)
[06:18:39] [PASSED] 0x4C90 (ROCKETLAKE)
[06:18:39] [PASSED] 0x4C9A (ROCKETLAKE)
[06:18:39] [PASSED] 0x4680 (ALDERLAKE_S)
[06:18:39] [PASSED] 0x4682 (ALDERLAKE_S)
[06:18:39] [PASSED] 0x4688 (ALDERLAKE_S)
[06:18:39] [PASSED] 0x468A (ALDERLAKE_S)
[06:18:39] [PASSED] 0x468B (ALDERLAKE_S)
[06:18:39] [PASSED] 0x4690 (ALDERLAKE_S)
[06:18:39] [PASSED] 0x4692 (ALDERLAKE_S)
[06:18:39] [PASSED] 0x4693 (ALDERLAKE_S)
[06:18:39] [PASSED] 0x46A0 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x46A1 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x46A2 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x46A3 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x46A6 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x46A8 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x46AA (ALDERLAKE_P)
[06:18:39] [PASSED] 0x462A (ALDERLAKE_P)
[06:18:39] [PASSED] 0x4626 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x4628 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x46B0 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x46B1 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x46B2 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x46B3 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x46C0 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x46C1 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x46C2 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x46C3 (ALDERLAKE_P)
[06:18:39] [PASSED] 0x46D0 (ALDERLAKE_N)
[06:18:39] [PASSED] 0x46D1 (ALDERLAKE_N)
[06:18:39] [PASSED] 0x46D2 (ALDERLAKE_N)
[06:18:39] [PASSED] 0x46D3 (ALDERLAKE_N)
[06:18:39] [PASSED] 0x46D4 (ALDERLAKE_N)
[06:18:39] [PASSED] 0xA721 (ALDERLAKE_P)
[06:18:39] [PASSED] 0xA7A1 (ALDERLAKE_P)
[06:18:39] [PASSED] 0xA7A9 (ALDERLAKE_P)
[06:18:39] [PASSED] 0xA7AC (ALDERLAKE_P)
[06:18:39] [PASSED] 0xA7AD (ALDERLAKE_P)
[06:18:39] [PASSED] 0xA720 (ALDERLAKE_P)
[06:18:39] [PASSED] 0xA7A0 (ALDERLAKE_P)
[06:18:39] [PASSED] 0xA7A8 (ALDERLAKE_P)
[06:18:39] [PASSED] 0xA7AA (ALDERLAKE_P)
[06:18:39] [PASSED] 0xA7AB (ALDERLAKE_P)
[06:18:39] [PASSED] 0xA780 (ALDERLAKE_S)
[06:18:39] [PASSED] 0xA781 (ALDERLAKE_S)
[06:18:39] [PASSED] 0xA782 (ALDERLAKE_S)
[06:18:39] [PASSED] 0xA783 (ALDERLAKE_S)
[06:18:39] [PASSED] 0xA788 (ALDERLAKE_S)
[06:18:39] [PASSED] 0xA789 (ALDERLAKE_S)
[06:18:39] [PASSED] 0xA78A (ALDERLAKE_S)
[06:18:39] [PASSED] 0xA78B (ALDERLAKE_S)
[06:18:39] [PASSED] 0x4905 (DG1)
[06:18:39] [PASSED] 0x4906 (DG1)
[06:18:39] [PASSED] 0x4907 (DG1)
[06:18:39] [PASSED] 0x4908 (DG1)
[06:18:39] [PASSED] 0x4909 (DG1)
[06:18:39] [PASSED] 0x56C0 (DG2)
[06:18:39] [PASSED] 0x56C2 (DG2)
[06:18:39] [PASSED] 0x56C1 (DG2)
[06:18:39] [PASSED] 0x7D51 (METEORLAKE)
[06:18:39] [PASSED] 0x7DD1 (METEORLAKE)
[06:18:39] [PASSED] 0x7D41 (METEORLAKE)
[06:18:39] [PASSED] 0x7D67 (METEORLAKE)
[06:18:39] [PASSED] 0xB640 (METEORLAKE)
[06:18:39] [PASSED] 0x56A0 (DG2)
[06:18:39] [PASSED] 0x56A1 (DG2)
[06:18:39] [PASSED] 0x56A2 (DG2)
[06:18:39] [PASSED] 0x56BE (DG2)
[06:18:39] [PASSED] 0x56BF (DG2)
[06:18:39] [PASSED] 0x5690 (DG2)
[06:18:39] [PASSED] 0x5691 (DG2)
[06:18:39] [PASSED] 0x5692 (DG2)
[06:18:39] [PASSED] 0x56A5 (DG2)
[06:18:39] [PASSED] 0x56A6 (DG2)
[06:18:39] [PASSED] 0x56B0 (DG2)
[06:18:39] [PASSED] 0x56B1 (DG2)
[06:18:39] [PASSED] 0x56BA (DG2)
[06:18:39] [PASSED] 0x56BB (DG2)
[06:18:39] [PASSED] 0x56BC (DG2)
[06:18:39] [PASSED] 0x56BD (DG2)
[06:18:39] [PASSED] 0x5693 (DG2)
[06:18:39] [PASSED] 0x5694 (DG2)
[06:18:39] [PASSED] 0x5695 (DG2)
[06:18:39] [PASSED] 0x56A3 (DG2)
[06:18:39] [PASSED] 0x56A4 (DG2)
[06:18:39] [PASSED] 0x56B2 (DG2)
[06:18:39] [PASSED] 0x56B3 (DG2)
[06:18:39] [PASSED] 0x5696 (DG2)
[06:18:39] [PASSED] 0x5697 (DG2)
[06:18:39] [PASSED] 0xB69 (PVC)
[06:18:39] [PASSED] 0xB6E (PVC)
[06:18:39] [PASSED] 0xBD4 (PVC)
[06:18:39] [PASSED] 0xBD5 (PVC)
[06:18:39] [PASSED] 0xBD6 (PVC)
[06:18:39] [PASSED] 0xBD7 (PVC)
[06:18:39] [PASSED] 0xBD8 (PVC)
[06:18:39] [PASSED] 0xBD9 (PVC)
[06:18:39] [PASSED] 0xBDA (PVC)
[06:18:39] [PASSED] 0xBDB (PVC)
[06:18:39] [PASSED] 0xBE0 (PVC)
[06:18:39] [PASSED] 0xBE1 (PVC)
[06:18:39] [PASSED] 0xBE5 (PVC)
[06:18:39] [PASSED] 0x7D40 (METEORLAKE)
[06:18:39] [PASSED] 0x7D45 (METEORLAKE)
[06:18:39] [PASSED] 0x7D55 (METEORLAKE)
[06:18:39] [PASSED] 0x7D60 (METEORLAKE)
[06:18:39] [PASSED] 0x7DD5 (METEORLAKE)
[06:18:39] [PASSED] 0x6420 (LUNARLAKE)
[06:18:39] [PASSED] 0x64A0 (LUNARLAKE)
[06:18:39] [PASSED] 0x64B0 (LUNARLAKE)
[06:18:39] [PASSED] 0xE202 (BATTLEMAGE)
[06:18:39] [PASSED] 0xE209 (BATTLEMAGE)
[06:18:39] [PASSED] 0xE20B (BATTLEMAGE)
[06:18:39] [PASSED] 0xE20C (BATTLEMAGE)
[06:18:39] [PASSED] 0xE20D (BATTLEMAGE)
[06:18:39] [PASSED] 0xE210 (BATTLEMAGE)
[06:18:39] [PASSED] 0xE211 (BATTLEMAGE)
[06:18:39] [PASSED] 0xE212 (BATTLEMAGE)
[06:18:39] [PASSED] 0xE216 (BATTLEMAGE)
[06:18:39] [PASSED] 0xE220 (BATTLEMAGE)
[06:18:39] [PASSED] 0xE221 (BATTLEMAGE)
[06:18:39] [PASSED] 0xE222 (BATTLEMAGE)
[06:18:39] [PASSED] 0xE223 (BATTLEMAGE)
[06:18:39] [PASSED] 0xB080 (PANTHERLAKE)
[06:18:39] [PASSED] 0xB081 (PANTHERLAKE)
[06:18:39] [PASSED] 0xB082 (PANTHERLAKE)
[06:18:39] [PASSED] 0xB083 (PANTHERLAKE)
[06:18:39] [PASSED] 0xB084 (PANTHERLAKE)
[06:18:39] [PASSED] 0xB085 (PANTHERLAKE)
[06:18:39] [PASSED] 0xB086 (PANTHERLAKE)
[06:18:39] [PASSED] 0xB087 (PANTHERLAKE)
[06:18:39] [PASSED] 0xB08F (PANTHERLAKE)
[06:18:39] [PASSED] 0xB090 (PANTHERLAKE)
[06:18:39] [PASSED] 0xB0A0 (PANTHERLAKE)
[06:18:39] [PASSED] 0xB0B0 (PANTHERLAKE)
[06:18:39] [PASSED] 0xFD80 (PANTHERLAKE)
[06:18:39] [PASSED] 0xFD81 (PANTHERLAKE)
[06:18:39] [PASSED] 0xD740 (NOVALAKE_S)
[06:18:39] [PASSED] 0xD741 (NOVALAKE_S)
[06:18:39] [PASSED] 0xD742 (NOVALAKE_S)
[06:18:39] [PASSED] 0xD743 (NOVALAKE_S)
[06:18:39] [PASSED] 0xD744 (NOVALAKE_S)
[06:18:39] [PASSED] 0xD745 (NOVALAKE_S)
[06:18:39] [PASSED] 0x674C (CRESCENTISLAND)
[06:18:39] [PASSED] 0xD750 (NOVALAKE_P)
[06:18:39] [PASSED] 0xD751 (NOVALAKE_P)
[06:18:39] [PASSED] 0xD752 (NOVALAKE_P)
[06:18:39] [PASSED] 0xD753 (NOVALAKE_P)
[06:18:39] [PASSED] 0xD754 (NOVALAKE_P)
[06:18:39] [PASSED] 0xD755 (NOVALAKE_P)
[06:18:39] [PASSED] 0xD756 (NOVALAKE_P)
[06:18:39] [PASSED] 0xD757 (NOVALAKE_P)
[06:18:39] [PASSED] 0xD75F (NOVALAKE_P)
[06:18:39] =============== [PASSED] check_platform_desc ===============
[06:18:39] ===================== [PASSED] xe_pci ======================
[06:18:39] =================== xe_rtp (2 subtests) ====================
[06:18:39] =============== xe_rtp_process_to_sr_tests ================
[06:18:39] [PASSED] coalesce-same-reg
[06:18:39] [PASSED] no-match-no-add
[06:18:39] [PASSED] match-or
[06:18:39] [PASSED] match-or-xfail
[06:18:39] [PASSED] no-match-no-add-multiple-rules
[06:18:39] [PASSED] two-regs-two-entries
[06:18:39] [PASSED] clr-one-set-other
[06:18:39] [PASSED] set-field
[06:18:39] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[06:18:39] [PASSED] conflict-not-disjoint
[06:18:39] [PASSED] conflict-reg-type
[06:18:39] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[06:18:39] ================== xe_rtp_process_tests ===================
[06:18:39] [PASSED] active1
[06:18:39] [PASSED] active2
[06:18:39] [PASSED] active-inactive
[06:18:39] [PASSED] inactive-active
[06:18:39] [PASSED] inactive-1st_or_active-inactive
[06:18:39] [PASSED] inactive-2nd_or_active-inactive
[06:18:39] [PASSED] inactive-last_or_active-inactive
[06:18:39] [PASSED] inactive-no_or_active-inactive
[06:18:39] ============== [PASSED] xe_rtp_process_tests ===============
[06:18:39] ===================== [PASSED] xe_rtp ======================
[06:18:39] ==================== xe_wa (1 subtest) =====================
[06:18:39] ======================== xe_wa_gt =========================
[06:18:39] [PASSED] TIGERLAKE B0
[06:18:39] [PASSED] DG1 A0
[06:18:39] [PASSED] DG1 B0
[06:18:39] [PASSED] ALDERLAKE_S A0
[06:18:39] [PASSED] ALDERLAKE_S B0
[06:18:39] [PASSED] ALDERLAKE_S C0
[06:18:39] [PASSED] ALDERLAKE_S D0
[06:18:39] [PASSED] ALDERLAKE_P A0
[06:18:39] [PASSED] ALDERLAKE_P B0
[06:18:39] [PASSED] ALDERLAKE_P C0
[06:18:39] [PASSED] ALDERLAKE_S RPLS D0
[06:18:39] [PASSED] ALDERLAKE_P RPLU E0
[06:18:39] [PASSED] DG2 G10 C0
[06:18:39] [PASSED] DG2 G11 B1
[06:18:39] [PASSED] DG2 G12 A1
[06:18:39] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:18:39] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:18:39] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[06:18:39] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[06:18:39] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[06:18:39] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[06:18:39] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[06:18:39] ==================== [PASSED] xe_wa_gt =====================
[06:18:39] ====================== [PASSED] xe_wa ======================
[06:18:39] ============================================================
[06:18:39] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[06:18:39] Elapsed time: 35.293s total, 4.259s configuring, 30.417s building, 0.605s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[06:18:39] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:18:41] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:19:05] Starting KUnit Kernel (1/1)...
[06:19:05] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:19:05] ============ drm_test_pick_cmdline (2 subtests) ============
[06:19:05] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[06:19:05] =============== drm_test_pick_cmdline_named ===============
[06:19:05] [PASSED] NTSC
[06:19:05] [PASSED] NTSC-J
[06:19:05] [PASSED] PAL
[06:19:05] [PASSED] PAL-M
[06:19:05] =========== [PASSED] drm_test_pick_cmdline_named ===========
[06:19:05] ============== [PASSED] drm_test_pick_cmdline ==============
[06:19:05] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[06:19:05] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[06:19:05] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[06:19:05] =========== drm_validate_clone_mode (2 subtests) ===========
[06:19:05] ============== drm_test_check_in_clone_mode ===============
[06:19:05] [PASSED] in_clone_mode
[06:19:05] [PASSED] not_in_clone_mode
[06:19:05] ========== [PASSED] drm_test_check_in_clone_mode ===========
[06:19:05] =============== drm_test_check_valid_clones ===============
[06:19:05] [PASSED] not_in_clone_mode
[06:19:05] [PASSED] valid_clone
[06:19:05] [PASSED] invalid_clone
[06:19:05] =========== [PASSED] drm_test_check_valid_clones ===========
[06:19:05] ============= [PASSED] drm_validate_clone_mode =============
[06:19:05] ============= drm_validate_modeset (1 subtest) =============
[06:19:05] [PASSED] drm_test_check_connector_changed_modeset
[06:19:05] ============== [PASSED] drm_validate_modeset ===============
[06:19:05] ====== drm_test_bridge_get_current_state (2 subtests) ======
[06:19:05] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[06:19:05] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[06:19:05] ======== [PASSED] drm_test_bridge_get_current_state ========
[06:19:05] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[06:19:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[06:19:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[06:19:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[06:19:05] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[06:19:05] ============== drm_bridge_alloc (2 subtests) ===============
[06:19:05] [PASSED] drm_test_drm_bridge_alloc_basic
[06:19:05] [PASSED] drm_test_drm_bridge_alloc_get_put
[06:19:05] ================ [PASSED] drm_bridge_alloc =================
[06:19:05] ============= drm_cmdline_parser (40 subtests) =============
[06:19:05] [PASSED] drm_test_cmdline_force_d_only
[06:19:05] [PASSED] drm_test_cmdline_force_D_only_dvi
[06:19:05] [PASSED] drm_test_cmdline_force_D_only_hdmi
[06:19:05] [PASSED] drm_test_cmdline_force_D_only_not_digital
[06:19:05] [PASSED] drm_test_cmdline_force_e_only
[06:19:05] [PASSED] drm_test_cmdline_res
[06:19:05] [PASSED] drm_test_cmdline_res_vesa
[06:19:05] [PASSED] drm_test_cmdline_res_vesa_rblank
[06:19:05] [PASSED] drm_test_cmdline_res_rblank
[06:19:05] [PASSED] drm_test_cmdline_res_bpp
[06:19:05] [PASSED] drm_test_cmdline_res_refresh
[06:19:05] [PASSED] drm_test_cmdline_res_bpp_refresh
[06:19:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[06:19:05] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[06:19:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[06:19:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[06:19:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[06:19:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[06:19:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[06:19:05] [PASSED] drm_test_cmdline_res_margins_force_on
[06:19:05] [PASSED] drm_test_cmdline_res_vesa_margins
[06:19:05] [PASSED] drm_test_cmdline_name
[06:19:05] [PASSED] drm_test_cmdline_name_bpp
[06:19:05] [PASSED] drm_test_cmdline_name_option
[06:19:05] [PASSED] drm_test_cmdline_name_bpp_option
[06:19:05] [PASSED] drm_test_cmdline_rotate_0
[06:19:05] [PASSED] drm_test_cmdline_rotate_90
[06:19:05] [PASSED] drm_test_cmdline_rotate_180
[06:19:05] [PASSED] drm_test_cmdline_rotate_270
[06:19:05] [PASSED] drm_test_cmdline_hmirror
[06:19:05] [PASSED] drm_test_cmdline_vmirror
[06:19:05] [PASSED] drm_test_cmdline_margin_options
[06:19:05] [PASSED] drm_test_cmdline_multiple_options
[06:19:05] [PASSED] drm_test_cmdline_bpp_extra_and_option
[06:19:05] [PASSED] drm_test_cmdline_extra_and_option
[06:19:05] [PASSED] drm_test_cmdline_freestanding_options
[06:19:05] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[06:19:05] [PASSED] drm_test_cmdline_panel_orientation
[06:19:05] ================ drm_test_cmdline_invalid =================
[06:19:05] [PASSED] margin_only
[06:19:05] [PASSED] interlace_only
[06:19:05] [PASSED] res_missing_x
[06:19:05] [PASSED] res_missing_y
[06:19:05] [PASSED] res_bad_y
[06:19:05] [PASSED] res_missing_y_bpp
[06:19:05] [PASSED] res_bad_bpp
[06:19:05] [PASSED] res_bad_refresh
[06:19:05] [PASSED] res_bpp_refresh_force_on_off
[06:19:05] [PASSED] res_invalid_mode
[06:19:05] [PASSED] res_bpp_wrong_place_mode
[06:19:05] [PASSED] name_bpp_refresh
[06:19:05] [PASSED] name_refresh
[06:19:05] [PASSED] name_refresh_wrong_mode
[06:19:05] [PASSED] name_refresh_invalid_mode
[06:19:05] [PASSED] rotate_multiple
[06:19:05] [PASSED] rotate_invalid_val
[06:19:05] [PASSED] rotate_truncated
[06:19:05] [PASSED] invalid_option
[06:19:05] [PASSED] invalid_tv_option
[06:19:05] [PASSED] truncated_tv_option
[06:19:05] ============ [PASSED] drm_test_cmdline_invalid =============
[06:19:05] =============== drm_test_cmdline_tv_options ===============
[06:19:05] [PASSED] NTSC
[06:19:05] [PASSED] NTSC_443
[06:19:05] [PASSED] NTSC_J
[06:19:05] [PASSED] PAL
[06:19:05] [PASSED] PAL_M
[06:19:05] [PASSED] PAL_N
[06:19:05] [PASSED] SECAM
[06:19:05] [PASSED] MONO_525
[06:19:05] [PASSED] MONO_625
[06:19:05] =========== [PASSED] drm_test_cmdline_tv_options ===========
[06:19:05] =============== [PASSED] drm_cmdline_parser ================
[06:19:05] ========== drmm_connector_hdmi_init (20 subtests) ==========
[06:19:05] [PASSED] drm_test_connector_hdmi_init_valid
[06:19:05] [PASSED] drm_test_connector_hdmi_init_bpc_8
[06:19:05] [PASSED] drm_test_connector_hdmi_init_bpc_10
[06:19:05] [PASSED] drm_test_connector_hdmi_init_bpc_12
[06:19:05] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[06:19:05] [PASSED] drm_test_connector_hdmi_init_bpc_null
[06:19:05] [PASSED] drm_test_connector_hdmi_init_formats_empty
[06:19:05] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[06:19:05] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:19:05] [PASSED] supported_formats=0x9 yuv420_allowed=1
[06:19:05] [PASSED] supported_formats=0x9 yuv420_allowed=0
[06:19:05] [PASSED] supported_formats=0x3 yuv420_allowed=1
[06:19:05] [PASSED] supported_formats=0x3 yuv420_allowed=0
[06:19:05] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:19:05] [PASSED] drm_test_connector_hdmi_init_null_ddc
[06:19:05] [PASSED] drm_test_connector_hdmi_init_null_product
[06:19:05] [PASSED] drm_test_connector_hdmi_init_null_vendor
[06:19:05] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[06:19:05] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[06:19:05] [PASSED] drm_test_connector_hdmi_init_product_valid
[06:19:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[06:19:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[06:19:05] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[06:19:05] ========= drm_test_connector_hdmi_init_type_valid =========
[06:19:05] [PASSED] HDMI-A
[06:19:05] [PASSED] HDMI-B
[06:19:05] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[06:19:05] ======== drm_test_connector_hdmi_init_type_invalid ========
[06:19:05] [PASSED] Unknown
[06:19:05] [PASSED] VGA
[06:19:05] [PASSED] DVI-I
[06:19:05] [PASSED] DVI-D
[06:19:05] [PASSED] DVI-A
[06:19:05] [PASSED] Composite
[06:19:05] [PASSED] SVIDEO
[06:19:05] [PASSED] LVDS
[06:19:05] [PASSED] Component
[06:19:05] [PASSED] DIN
[06:19:05] [PASSED] DP
[06:19:05] [PASSED] TV
[06:19:05] [PASSED] eDP
[06:19:05] [PASSED] Virtual
[06:19:05] [PASSED] DSI
[06:19:05] [PASSED] DPI
[06:19:05] [PASSED] Writeback
[06:19:05] [PASSED] SPI
[06:19:05] [PASSED] USB
[06:19:05] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[06:19:05] ============ [PASSED] drmm_connector_hdmi_init =============
[06:19:05] ============= drmm_connector_init (3 subtests) =============
[06:19:05] [PASSED] drm_test_drmm_connector_init
[06:19:05] [PASSED] drm_test_drmm_connector_init_null_ddc
[06:19:05] ========= drm_test_drmm_connector_init_type_valid =========
[06:19:05] [PASSED] Unknown
[06:19:05] [PASSED] VGA
[06:19:05] [PASSED] DVI-I
[06:19:05] [PASSED] DVI-D
[06:19:05] [PASSED] DVI-A
[06:19:05] [PASSED] Composite
[06:19:05] [PASSED] SVIDEO
[06:19:05] [PASSED] LVDS
[06:19:05] [PASSED] Component
[06:19:05] [PASSED] DIN
[06:19:05] [PASSED] DP
[06:19:05] [PASSED] HDMI-A
[06:19:05] [PASSED] HDMI-B
[06:19:05] [PASSED] TV
[06:19:05] [PASSED] eDP
[06:19:05] [PASSED] Virtual
[06:19:05] [PASSED] DSI
[06:19:05] [PASSED] DPI
[06:19:05] [PASSED] Writeback
[06:19:05] [PASSED] SPI
[06:19:05] [PASSED] USB
[06:19:05] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[06:19:05] =============== [PASSED] drmm_connector_init ===============
[06:19:05] ========= drm_connector_dynamic_init (6 subtests) ==========
[06:19:05] [PASSED] drm_test_drm_connector_dynamic_init
[06:19:05] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[06:19:05] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[06:19:05] [PASSED] drm_test_drm_connector_dynamic_init_properties
[06:19:05] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[06:19:05] [PASSED] Unknown
[06:19:05] [PASSED] VGA
[06:19:05] [PASSED] DVI-I
[06:19:05] [PASSED] DVI-D
[06:19:05] [PASSED] DVI-A
[06:19:05] [PASSED] Composite
[06:19:05] [PASSED] SVIDEO
[06:19:05] [PASSED] LVDS
[06:19:05] [PASSED] Component
[06:19:05] [PASSED] DIN
[06:19:05] [PASSED] DP
[06:19:05] [PASSED] HDMI-A
[06:19:05] [PASSED] HDMI-B
[06:19:05] [PASSED] TV
[06:19:05] [PASSED] eDP
[06:19:05] [PASSED] Virtual
[06:19:05] [PASSED] DSI
[06:19:05] [PASSED] DPI
[06:19:05] [PASSED] Writeback
[06:19:05] [PASSED] SPI
[06:19:05] [PASSED] USB
[06:19:05] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[06:19:05] ======== drm_test_drm_connector_dynamic_init_name =========
[06:19:05] [PASSED] Unknown
[06:19:05] [PASSED] VGA
[06:19:05] [PASSED] DVI-I
[06:19:05] [PASSED] DVI-D
[06:19:05] [PASSED] DVI-A
[06:19:05] [PASSED] Composite
[06:19:05] [PASSED] SVIDEO
[06:19:05] [PASSED] LVDS
[06:19:05] [PASSED] Component
[06:19:05] [PASSED] DIN
[06:19:05] [PASSED] DP
[06:19:05] [PASSED] HDMI-A
[06:19:05] [PASSED] HDMI-B
[06:19:05] [PASSED] TV
[06:19:05] [PASSED] eDP
[06:19:05] [PASSED] Virtual
[06:19:05] [PASSED] DSI
[06:19:05] [PASSED] DPI
[06:19:05] [PASSED] Writeback
[06:19:05] [PASSED] SPI
[06:19:05] [PASSED] USB
[06:19:05] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[06:19:05] =========== [PASSED] drm_connector_dynamic_init ============
[06:19:05] ==== drm_connector_dynamic_register_early (4 subtests) =====
[06:19:05] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[06:19:05] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[06:19:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[06:19:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[06:19:05] ====== [PASSED] drm_connector_dynamic_register_early =======
[06:19:05] ======= drm_connector_dynamic_register (7 subtests) ========
[06:19:05] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[06:19:05] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[06:19:05] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[06:19:05] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[06:19:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[06:19:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[06:19:05] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[06:19:05] ========= [PASSED] drm_connector_dynamic_register ==========
[06:19:05] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[06:19:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[06:19:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[06:19:05] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[06:19:05] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[06:19:05] ========== drm_test_get_tv_mode_from_name_valid ===========
[06:19:05] [PASSED] NTSC
[06:19:05] [PASSED] NTSC-443
[06:19:05] [PASSED] NTSC-J
[06:19:05] [PASSED] PAL
[06:19:05] [PASSED] PAL-M
[06:19:05] [PASSED] PAL-N
[06:19:05] [PASSED] SECAM
[06:19:05] [PASSED] Mono
[06:19:05] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[06:19:05] [PASSED] drm_test_get_tv_mode_from_name_truncated
[06:19:05] ============ [PASSED] drm_get_tv_mode_from_name ============
[06:19:05] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[06:19:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[06:19:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[06:19:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[06:19:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[06:19:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[06:19:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[06:19:05] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[06:19:05] [PASSED] VIC 96
[06:19:05] [PASSED] VIC 97
[06:19:05] [PASSED] VIC 101
[06:19:05] [PASSED] VIC 102
[06:19:05] [PASSED] VIC 106
[06:19:05] [PASSED] VIC 107
[06:19:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[06:19:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[06:19:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[06:19:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[06:19:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[06:19:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[06:19:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[06:19:05] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[06:19:05] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[06:19:05] [PASSED] Automatic
[06:19:05] [PASSED] Full
[06:19:05] [PASSED] Limited 16:235
[06:19:05] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[06:19:05] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[06:19:05] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[06:19:05] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[06:19:05] === drm_test_drm_hdmi_connector_get_output_format_name ====
[06:19:05] [PASSED] RGB
[06:19:05] [PASSED] YUV 4:2:0
[06:19:05] [PASSED] YUV 4:2:2
[06:19:05] [PASSED] YUV 4:4:4
[06:19:05] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[06:19:05] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[06:19:05] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[06:19:05] ============= drm_damage_helper (21 subtests) ==============
[06:19:05] [PASSED] drm_test_damage_iter_no_damage
[06:19:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[06:19:05] [PASSED] drm_test_damage_iter_no_damage_src_moved
[06:19:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[06:19:05] [PASSED] drm_test_damage_iter_no_damage_not_visible
[06:19:05] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[06:19:05] [PASSED] drm_test_damage_iter_no_damage_no_fb
[06:19:05] [PASSED] drm_test_damage_iter_simple_damage
[06:19:05] [PASSED] drm_test_damage_iter_single_damage
[06:19:05] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[06:19:05] [PASSED] drm_test_damage_iter_single_damage_outside_src
[06:19:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[06:19:05] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[06:19:05] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[06:19:05] [PASSED] drm_test_damage_iter_single_damage_src_moved
[06:19:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[06:19:05] [PASSED] drm_test_damage_iter_damage
[06:19:05] [PASSED] drm_test_damage_iter_damage_one_intersect
[06:19:05] [PASSED] drm_test_damage_iter_damage_one_outside
[06:19:05] [PASSED] drm_test_damage_iter_damage_src_moved
[06:19:05] [PASSED] drm_test_damage_iter_damage_not_visible
[06:19:05] ================ [PASSED] drm_damage_helper ================
[06:19:05] ============== drm_dp_mst_helper (3 subtests) ==============
[06:19:05] ============== drm_test_dp_mst_calc_pbn_mode ==============
[06:19:05] [PASSED] Clock 154000 BPP 30 DSC disabled
[06:19:05] [PASSED] Clock 234000 BPP 30 DSC disabled
[06:19:05] [PASSED] Clock 297000 BPP 24 DSC disabled
[06:19:05] [PASSED] Clock 332880 BPP 24 DSC enabled
[06:19:05] [PASSED] Clock 324540 BPP 24 DSC enabled
[06:19:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[06:19:05] ============== drm_test_dp_mst_calc_pbn_div ===============
[06:19:05] [PASSED] Link rate 2000000 lane count 4
[06:19:05] [PASSED] Link rate 2000000 lane count 2
[06:19:05] [PASSED] Link rate 2000000 lane count 1
[06:19:05] [PASSED] Link rate 1350000 lane count 4
[06:19:05] [PASSED] Link rate 1350000 lane count 2
[06:19:05] [PASSED] Link rate 1350000 lane count 1
[06:19:05] [PASSED] Link rate 1000000 lane count 4
[06:19:05] [PASSED] Link rate 1000000 lane count 2
[06:19:05] [PASSED] Link rate 1000000 lane count 1
[06:19:05] [PASSED] Link rate 810000 lane count 4
[06:19:05] [PASSED] Link rate 810000 lane count 2
[06:19:05] [PASSED] Link rate 810000 lane count 1
[06:19:05] [PASSED] Link rate 540000 lane count 4
[06:19:05] [PASSED] Link rate 540000 lane count 2
[06:19:05] [PASSED] Link rate 540000 lane count 1
[06:19:05] [PASSED] Link rate 270000 lane count 4
[06:19:05] [PASSED] Link rate 270000 lane count 2
[06:19:05] [PASSED] Link rate 270000 lane count 1
[06:19:05] [PASSED] Link rate 162000 lane count 4
[06:19:05] [PASSED] Link rate 162000 lane count 2
[06:19:05] [PASSED] Link rate 162000 lane count 1
[06:19:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[06:19:05] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[06:19:05] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[06:19:05] [PASSED] DP_POWER_UP_PHY with port number
[06:19:05] [PASSED] DP_POWER_DOWN_PHY with port number
[06:19:05] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[06:19:05] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[06:19:05] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[06:19:05] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[06:19:05] [PASSED] DP_QUERY_PAYLOAD with port number
[06:19:05] [PASSED] DP_QUERY_PAYLOAD with VCPI
[06:19:05] [PASSED] DP_REMOTE_DPCD_READ with port number
[06:19:05] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[06:19:05] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[06:19:05] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[06:19:05] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[06:19:05] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[06:19:05] [PASSED] DP_REMOTE_I2C_READ with port number
[06:19:05] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[06:19:05] [PASSED] DP_REMOTE_I2C_READ with transactions array
[06:19:05] [PASSED] DP_REMOTE_I2C_WRITE with port number
[06:19:05] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[06:19:05] [PASSED] DP_REMOTE_I2C_WRITE with data array
[06:19:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[06:19:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[06:19:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[06:19:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[06:19:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[06:19:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[06:19:05] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[06:19:05] ================ [PASSED] drm_dp_mst_helper ================
[06:19:05] ================== drm_exec (7 subtests) ===================
[06:19:05] [PASSED] sanitycheck
[06:19:05] [PASSED] test_lock
[06:19:05] [PASSED] test_lock_unlock
[06:19:05] [PASSED] test_duplicates
[06:19:05] [PASSED] test_prepare
[06:19:05] [PASSED] test_prepare_array
[06:19:05] [PASSED] test_multiple_loops
[06:19:05] ==================== [PASSED] drm_exec =====================
[06:19:05] =========== drm_format_helper_test (17 subtests) ===========
[06:19:05] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[06:19:05] [PASSED] single_pixel_source_buffer
[06:19:05] [PASSED] single_pixel_clip_rectangle
[06:19:05] [PASSED] well_known_colors
[06:19:05] [PASSED] destination_pitch
[06:19:05] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[06:19:05] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[06:19:05] [PASSED] single_pixel_source_buffer
[06:19:05] [PASSED] single_pixel_clip_rectangle
[06:19:05] [PASSED] well_known_colors
[06:19:05] [PASSED] destination_pitch
[06:19:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[06:19:05] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[06:19:05] [PASSED] single_pixel_source_buffer
[06:19:05] [PASSED] single_pixel_clip_rectangle
[06:19:05] [PASSED] well_known_colors
[06:19:05] [PASSED] destination_pitch
[06:19:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[06:19:05] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[06:19:05] [PASSED] single_pixel_source_buffer
[06:19:05] [PASSED] single_pixel_clip_rectangle
[06:19:05] [PASSED] well_known_colors
[06:19:05] [PASSED] destination_pitch
[06:19:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[06:19:05] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[06:19:05] [PASSED] single_pixel_source_buffer
[06:19:05] [PASSED] single_pixel_clip_rectangle
[06:19:05] [PASSED] well_known_colors
[06:19:05] [PASSED] destination_pitch
[06:19:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[06:19:05] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[06:19:05] [PASSED] single_pixel_source_buffer
[06:19:05] [PASSED] single_pixel_clip_rectangle
[06:19:05] [PASSED] well_known_colors
[06:19:05] [PASSED] destination_pitch
[06:19:05] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[06:19:05] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[06:19:05] [PASSED] single_pixel_source_buffer
[06:19:05] [PASSED] single_pixel_clip_rectangle
[06:19:05] [PASSED] well_known_colors
[06:19:05] [PASSED] destination_pitch
[06:19:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[06:19:05] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[06:19:05] [PASSED] single_pixel_source_buffer
[06:19:05] [PASSED] single_pixel_clip_rectangle
[06:19:05] [PASSED] well_known_colors
[06:19:05] [PASSED] destination_pitch
[06:19:05] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[06:19:05] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[06:19:05] [PASSED] single_pixel_source_buffer
[06:19:05] [PASSED] single_pixel_clip_rectangle
[06:19:05] [PASSED] well_known_colors
[06:19:05] [PASSED] destination_pitch
[06:19:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[06:19:05] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[06:19:05] [PASSED] single_pixel_source_buffer
[06:19:05] [PASSED] single_pixel_clip_rectangle
[06:19:05] [PASSED] well_known_colors
[06:19:05] [PASSED] destination_pitch
[06:19:05] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[06:19:05] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[06:19:05] [PASSED] single_pixel_source_buffer
[06:19:05] [PASSED] single_pixel_clip_rectangle
[06:19:05] [PASSED] well_known_colors
[06:19:05] [PASSED] destination_pitch
[06:19:05] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[06:19:05] ============== drm_test_fb_xrgb8888_to_mono ===============
[06:19:05] [PASSED] single_pixel_source_buffer
[06:19:05] [PASSED] single_pixel_clip_rectangle
[06:19:05] [PASSED] well_known_colors
[06:19:05] [PASSED] destination_pitch
[06:19:05] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[06:19:05] ==================== drm_test_fb_swab =====================
[06:19:05] [PASSED] single_pixel_source_buffer
[06:19:05] [PASSED] single_pixel_clip_rectangle
[06:19:05] [PASSED] well_known_colors
[06:19:05] [PASSED] destination_pitch
[06:19:05] ================ [PASSED] drm_test_fb_swab =================
[06:19:05] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[06:19:05] [PASSED] single_pixel_source_buffer
[06:19:05] [PASSED] single_pixel_clip_rectangle
[06:19:05] [PASSED] well_known_colors
[06:19:05] [PASSED] destination_pitch
[06:19:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[06:19:05] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[06:19:05] [PASSED] single_pixel_source_buffer
[06:19:05] [PASSED] single_pixel_clip_rectangle
[06:19:05] [PASSED] well_known_colors
[06:19:05] [PASSED] destination_pitch
[06:19:05] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[06:19:05] ================= drm_test_fb_clip_offset =================
[06:19:05] [PASSED] pass through
[06:19:05] [PASSED] horizontal offset
[06:19:05] [PASSED] vertical offset
[06:19:05] [PASSED] horizontal and vertical offset
[06:19:05] [PASSED] horizontal offset (custom pitch)
[06:19:05] [PASSED] vertical offset (custom pitch)
[06:19:05] [PASSED] horizontal and vertical offset (custom pitch)
[06:19:05] ============= [PASSED] drm_test_fb_clip_offset =============
[06:19:05] =================== drm_test_fb_memcpy ====================
[06:19:05] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[06:19:05] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[06:19:05] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[06:19:05] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[06:19:05] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[06:19:05] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[06:19:05] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[06:19:05] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[06:19:05] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[06:19:05] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[06:19:05] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[06:19:05] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[06:19:05] =============== [PASSED] drm_test_fb_memcpy ================
[06:19:05] ============= [PASSED] drm_format_helper_test ==============
[06:19:05] ================= drm_format (18 subtests) =================
[06:19:05] [PASSED] drm_test_format_block_width_invalid
[06:19:05] [PASSED] drm_test_format_block_width_one_plane
[06:19:05] [PASSED] drm_test_format_block_width_two_plane
[06:19:05] [PASSED] drm_test_format_block_width_three_plane
[06:19:05] [PASSED] drm_test_format_block_width_tiled
[06:19:05] [PASSED] drm_test_format_block_height_invalid
[06:19:05] [PASSED] drm_test_format_block_height_one_plane
[06:19:05] [PASSED] drm_test_format_block_height_two_plane
[06:19:05] [PASSED] drm_test_format_block_height_three_plane
[06:19:05] [PASSED] drm_test_format_block_height_tiled
[06:19:05] [PASSED] drm_test_format_min_pitch_invalid
[06:19:05] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[06:19:05] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[06:19:05] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[06:19:05] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[06:19:05] [PASSED] drm_test_format_min_pitch_two_plane
[06:19:05] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[06:19:05] [PASSED] drm_test_format_min_pitch_tiled
[06:19:05] =================== [PASSED] drm_format ====================
[06:19:05] ============== drm_framebuffer (10 subtests) ===============
[06:19:05] ========== drm_test_framebuffer_check_src_coords ==========
[06:19:05] [PASSED] Success: source fits into fb
[06:19:05] [PASSED] Fail: overflowing fb with x-axis coordinate
[06:19:05] [PASSED] Fail: overflowing fb with y-axis coordinate
[06:19:05] [PASSED] Fail: overflowing fb with source width
[06:19:05] [PASSED] Fail: overflowing fb with source height
[06:19:05] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[06:19:05] [PASSED] drm_test_framebuffer_cleanup
[06:19:05] =============== drm_test_framebuffer_create ===============
[06:19:05] [PASSED] ABGR8888 normal sizes
[06:19:05] [PASSED] ABGR8888 max sizes
[06:19:05] [PASSED] ABGR8888 pitch greater than min required
[06:19:05] [PASSED] ABGR8888 pitch less than min required
[06:19:05] [PASSED] ABGR8888 Invalid width
[06:19:05] [PASSED] ABGR8888 Invalid buffer handle
[06:19:05] [PASSED] No pixel format
[06:19:05] [PASSED] ABGR8888 Width 0
[06:19:05] [PASSED] ABGR8888 Height 0
[06:19:05] [PASSED] ABGR8888 Out of bound height * pitch combination
[06:19:05] [PASSED] ABGR8888 Large buffer offset
[06:19:05] [PASSED] ABGR8888 Buffer offset for inexistent plane
[06:19:05] [PASSED] ABGR8888 Invalid flag
[06:19:05] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[06:19:05] [PASSED] ABGR8888 Valid buffer modifier
[06:19:05] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[06:19:05] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[06:19:05] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[06:19:05] [PASSED] NV12 Normal sizes
[06:19:05] [PASSED] NV12 Max sizes
[06:19:05] [PASSED] NV12 Invalid pitch
[06:19:05] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[06:19:05] [PASSED] NV12 different modifier per-plane
[06:19:05] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[06:19:05] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[06:19:05] [PASSED] NV12 Modifier for inexistent plane
[06:19:05] [PASSED] NV12 Handle for inexistent plane
[06:19:05] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[06:19:05] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[06:19:05] [PASSED] YVU420 Normal sizes
[06:19:05] [PASSED] YVU420 Max sizes
[06:19:05] [PASSED] YVU420 Invalid pitch
[06:19:05] [PASSED] YVU420 Different pitches
[06:19:05] [PASSED] YVU420 Different buffer offsets/pitches
[06:19:05] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[06:19:05] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[06:19:05] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[06:19:05] [PASSED] YVU420 Valid modifier
[06:19:05] [PASSED] YVU420 Different modifiers per plane
[06:19:05] [PASSED] YVU420 Modifier for inexistent plane
[06:19:05] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[06:19:05] [PASSED] X0L2 Normal sizes
[06:19:05] [PASSED] X0L2 Max sizes
[06:19:05] [PASSED] X0L2 Invalid pitch
[06:19:05] [PASSED] X0L2 Pitch greater than minimum required
[06:19:05] [PASSED] X0L2 Handle for inexistent plane
[06:19:05] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[06:19:05] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[06:19:05] [PASSED] X0L2 Valid modifier
[06:19:05] [PASSED] X0L2 Modifier for inexistent plane
[06:19:05] =========== [PASSED] drm_test_framebuffer_create ===========
[06:19:05] [PASSED] drm_test_framebuffer_free
[06:19:05] [PASSED] drm_test_framebuffer_init
[06:19:05] [PASSED] drm_test_framebuffer_init_bad_format
[06:19:05] [PASSED] drm_test_framebuffer_init_dev_mismatch
[06:19:05] [PASSED] drm_test_framebuffer_lookup
[06:19:05] [PASSED] drm_test_framebuffer_lookup_inexistent
[06:19:05] [PASSED] drm_test_framebuffer_modifiers_not_supported
[06:19:05] ================= [PASSED] drm_framebuffer =================
[06:19:05] ================ drm_gem_shmem (8 subtests) ================
[06:19:05] [PASSED] drm_gem_shmem_test_obj_create
[06:19:05] [PASSED] drm_gem_shmem_test_obj_create_private
[06:19:05] [PASSED] drm_gem_shmem_test_pin_pages
[06:19:05] [PASSED] drm_gem_shmem_test_vmap
[06:19:05] [PASSED] drm_gem_shmem_test_get_sg_table
[06:19:05] [PASSED] drm_gem_shmem_test_get_pages_sgt
[06:19:05] [PASSED] drm_gem_shmem_test_madvise
[06:19:05] [PASSED] drm_gem_shmem_test_purge
[06:19:05] ================== [PASSED] drm_gem_shmem ==================
[06:19:05] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[06:19:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[06:19:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[06:19:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[06:19:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[06:19:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[06:19:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[06:19:05] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[06:19:05] [PASSED] Automatic
[06:19:05] [PASSED] Full
[06:19:05] [PASSED] Limited 16:235
[06:19:05] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[06:19:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[06:19:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[06:19:05] [PASSED] drm_test_check_disable_connector
[06:19:05] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[06:19:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[06:19:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[06:19:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[06:19:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[06:19:05] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[06:19:05] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[06:19:05] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[06:19:05] [PASSED] drm_test_check_output_bpc_dvi
[06:19:05] [PASSED] drm_test_check_output_bpc_format_vic_1
[06:19:05] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[06:19:05] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[06:19:05] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[06:19:05] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[06:19:05] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[06:19:05] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[06:19:05] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[06:19:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[06:19:05] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[06:19:05] [PASSED] drm_test_check_broadcast_rgb_value
[06:19:05] [PASSED] drm_test_check_bpc_8_value
[06:19:05] [PASSED] drm_test_check_bpc_10_value
[06:19:05] [PASSED] drm_test_check_bpc_12_value
[06:19:05] [PASSED] drm_test_check_format_value
[06:19:05] [PASSED] drm_test_check_tmds_char_value
[06:19:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[06:19:05] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[06:19:05] [PASSED] drm_test_check_mode_valid
[06:19:05] [PASSED] drm_test_check_mode_valid_reject
[06:19:05] [PASSED] drm_test_check_mode_valid_reject_rate
[06:19:05] [PASSED] drm_test_check_mode_valid_reject_max_clock
[06:19:05] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[06:19:05] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[06:19:05] [PASSED] drm_test_check_infoframes
[06:19:05] [PASSED] drm_test_check_reject_avi_infoframe
[06:19:05] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[06:19:05] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[06:19:05] [PASSED] drm_test_check_reject_audio_infoframe
[06:19:05] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[06:19:05] ================= drm_managed (2 subtests) =================
[06:19:05] [PASSED] drm_test_managed_release_action
[06:19:05] [PASSED] drm_test_managed_run_action
[06:19:05] =================== [PASSED] drm_managed ===================
[06:19:05] =================== drm_mm (6 subtests) ====================
[06:19:05] [PASSED] drm_test_mm_init
[06:19:05] [PASSED] drm_test_mm_debug
[06:19:05] [PASSED] drm_test_mm_align32
[06:19:05] [PASSED] drm_test_mm_align64
[06:19:05] [PASSED] drm_test_mm_lowest
[06:19:05] [PASSED] drm_test_mm_highest
[06:19:05] ===================== [PASSED] drm_mm ======================
[06:19:05] ============= drm_modes_analog_tv (5 subtests) =============
[06:19:05] [PASSED] drm_test_modes_analog_tv_mono_576i
[06:19:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[06:19:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[06:19:05] [PASSED] drm_test_modes_analog_tv_pal_576i
[06:19:05] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[06:19:05] =============== [PASSED] drm_modes_analog_tv ===============
[06:19:05] ============== drm_plane_helper (2 subtests) ===============
[06:19:05] =============== drm_test_check_plane_state ================
[06:19:05] [PASSED] clipping_simple
[06:19:05] [PASSED] clipping_rotate_reflect
[06:19:05] [PASSED] positioning_simple
[06:19:05] [PASSED] upscaling
[06:19:05] [PASSED] downscaling
[06:19:05] [PASSED] rounding1
[06:19:05] [PASSED] rounding2
[06:19:05] [PASSED] rounding3
[06:19:05] [PASSED] rounding4
[06:19:05] =========== [PASSED] drm_test_check_plane_state ============
[06:19:05] =========== drm_test_check_invalid_plane_state ============
[06:19:05] [PASSED] positioning_invalid
[06:19:05] [PASSED] upscaling_invalid
[06:19:05] [PASSED] downscaling_invalid
[06:19:05] ======= [PASSED] drm_test_check_invalid_plane_state ========
[06:19:05] ================ [PASSED] drm_plane_helper =================
[06:19:05] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[06:19:05] ====== drm_test_connector_helper_tv_get_modes_check =======
[06:19:05] [PASSED] None
[06:19:05] [PASSED] PAL
[06:19:05] [PASSED] NTSC
[06:19:05] [PASSED] Both, NTSC Default
[06:19:05] [PASSED] Both, PAL Default
[06:19:05] [PASSED] Both, NTSC Default, with PAL on command-line
[06:19:05] [PASSED] Both, PAL Default, with NTSC on command-line
[06:19:05] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[06:19:05] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[06:19:05] ================== drm_rect (9 subtests) ===================
[06:19:05] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[06:19:05] [PASSED] drm_test_rect_clip_scaled_not_clipped
[06:19:05] [PASSED] drm_test_rect_clip_scaled_clipped
[06:19:05] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[06:19:05] ================= drm_test_rect_intersect =================
[06:19:05] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[06:19:05] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[06:19:05] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[06:19:05] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[06:19:05] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[06:19:05] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[06:19:05] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[06:19:05] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[06:19:05] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[06:19:05] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[06:19:05] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[06:19:05] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[06:19:05] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[06:19:05] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[06:19:05] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[06:19:05] ============= [PASSED] drm_test_rect_intersect =============
[06:19:05] ================ drm_test_rect_calc_hscale ================
[06:19:05] [PASSED] normal use
[06:19:05] [PASSED] out of max range
[06:19:05] [PASSED] out of min range
[06:19:05] [PASSED] zero dst
[06:19:05] [PASSED] negative src
[06:19:05] [PASSED] negative dst
[06:19:05] ============ [PASSED] drm_test_rect_calc_hscale ============
[06:19:05] ================ drm_test_rect_calc_vscale ================
[06:19:05] [PASSED] normal use
[06:19:05] [PASSED] out of max range
[06:19:05] [PASSED] out of min range
[06:19:05] [PASSED] zero dst
[06:19:05] [PASSED] negative src
[06:19:05] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[06:19:05] ============ [PASSED] drm_test_rect_calc_vscale ============
[06:19:05] ================== drm_test_rect_rotate ===================
[06:19:05] [PASSED] reflect-x
[06:19:05] [PASSED] reflect-y
[06:19:05] [PASSED] rotate-0
[06:19:05] [PASSED] rotate-90
[06:19:05] [PASSED] rotate-180
[06:19:05] [PASSED] rotate-270
[06:19:05] ============== [PASSED] drm_test_rect_rotate ===============
[06:19:05] ================ drm_test_rect_rotate_inv =================
[06:19:05] [PASSED] reflect-x
[06:19:05] [PASSED] reflect-y
[06:19:05] [PASSED] rotate-0
[06:19:05] [PASSED] rotate-90
[06:19:05] [PASSED] rotate-180
[06:19:05] [PASSED] rotate-270
[06:19:05] ============ [PASSED] drm_test_rect_rotate_inv =============
[06:19:05] ==================== [PASSED] drm_rect =====================
[06:19:05] ============ drm_sysfb_modeset_test (1 subtest) ============
[06:19:05] ============ drm_test_sysfb_build_fourcc_list =============
[06:19:05] [PASSED] no native formats
[06:19:05] [PASSED] XRGB8888 as native format
[06:19:05] [PASSED] remove duplicates
[06:19:05] [PASSED] convert alpha formats
[06:19:05] [PASSED] random formats
[06:19:05] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[06:19:05] ============= [PASSED] drm_sysfb_modeset_test ==============
[06:19:05] ================== drm_fixp (2 subtests) ===================
[06:19:05] [PASSED] drm_test_int2fixp
[06:19:05] [PASSED] drm_test_sm2fixp
[06:19:05] ==================== [PASSED] drm_fixp =====================
[06:19:05] ============================================================
[06:19:05] Testing complete. Ran 621 tests: passed: 621
[06:19:05] Elapsed time: 26.030s total, 1.706s configuring, 24.143s building, 0.180s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[06:19:05] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:19:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:19:17] Starting KUnit Kernel (1/1)...
[06:19:17] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:19:17] ================= ttm_device (5 subtests) ==================
[06:19:17] [PASSED] ttm_device_init_basic
[06:19:17] [PASSED] ttm_device_init_multiple
[06:19:17] [PASSED] ttm_device_fini_basic
[06:19:17] [PASSED] ttm_device_init_no_vma_man
[06:19:17] ================== ttm_device_init_pools ==================
[06:19:17] [PASSED] No DMA allocations, no DMA32 required
[06:19:17] [PASSED] DMA allocations, DMA32 required
[06:19:17] [PASSED] No DMA allocations, DMA32 required
[06:19:17] [PASSED] DMA allocations, no DMA32 required
[06:19:17] ============== [PASSED] ttm_device_init_pools ==============
[06:19:17] =================== [PASSED] ttm_device ====================
[06:19:17] ================== ttm_pool (8 subtests) ===================
[06:19:17] ================== ttm_pool_alloc_basic ===================
[06:19:17] [PASSED] One page
[06:19:17] [PASSED] More than one page
[06:19:17] [PASSED] Above the allocation limit
[06:19:17] [PASSED] One page, with coherent DMA mappings enabled
[06:19:17] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:19:17] ============== [PASSED] ttm_pool_alloc_basic ===============
[06:19:17] ============== ttm_pool_alloc_basic_dma_addr ==============
[06:19:17] [PASSED] One page
[06:19:17] [PASSED] More than one page
[06:19:17] [PASSED] Above the allocation limit
[06:19:17] [PASSED] One page, with coherent DMA mappings enabled
[06:19:17] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:19:17] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[06:19:17] [PASSED] ttm_pool_alloc_order_caching_match
[06:19:17] [PASSED] ttm_pool_alloc_caching_mismatch
[06:19:17] [PASSED] ttm_pool_alloc_order_mismatch
[06:19:17] [PASSED] ttm_pool_free_dma_alloc
[06:19:17] [PASSED] ttm_pool_free_no_dma_alloc
[06:19:17] [PASSED] ttm_pool_fini_basic
[06:19:17] ==================== [PASSED] ttm_pool =====================
[06:19:17] ================ ttm_resource (8 subtests) =================
[06:19:17] ================= ttm_resource_init_basic =================
[06:19:17] [PASSED] Init resource in TTM_PL_SYSTEM
[06:19:17] [PASSED] Init resource in TTM_PL_VRAM
[06:19:17] [PASSED] Init resource in a private placement
[06:19:17] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[06:19:17] ============= [PASSED] ttm_resource_init_basic =============
[06:19:17] [PASSED] ttm_resource_init_pinned
[06:19:17] [PASSED] ttm_resource_fini_basic
[06:19:17] [PASSED] ttm_resource_manager_init_basic
[06:19:17] [PASSED] ttm_resource_manager_usage_basic
[06:19:17] [PASSED] ttm_resource_manager_set_used_basic
[06:19:17] [PASSED] ttm_sys_man_alloc_basic
[06:19:17] [PASSED] ttm_sys_man_free_basic
[06:19:17] ================== [PASSED] ttm_resource ===================
[06:19:17] =================== ttm_tt (15 subtests) ===================
[06:19:17] ==================== ttm_tt_init_basic ====================
[06:19:17] [PASSED] Page-aligned size
[06:19:17] [PASSED] Extra pages requested
[06:19:17] ================ [PASSED] ttm_tt_init_basic ================
[06:19:17] [PASSED] ttm_tt_init_misaligned
[06:19:17] [PASSED] ttm_tt_fini_basic
[06:19:17] [PASSED] ttm_tt_fini_sg
[06:19:17] [PASSED] ttm_tt_fini_shmem
[06:19:17] [PASSED] ttm_tt_create_basic
[06:19:17] [PASSED] ttm_tt_create_invalid_bo_type
[06:19:17] [PASSED] ttm_tt_create_ttm_exists
[06:19:17] [PASSED] ttm_tt_create_failed
[06:19:17] [PASSED] ttm_tt_destroy_basic
[06:19:17] [PASSED] ttm_tt_populate_null_ttm
[06:19:17] [PASSED] ttm_tt_populate_populated_ttm
[06:19:17] [PASSED] ttm_tt_unpopulate_basic
[06:19:17] [PASSED] ttm_tt_unpopulate_empty_ttm
[06:19:17] [PASSED] ttm_tt_swapin_basic
[06:19:17] ===================== [PASSED] ttm_tt ======================
[06:19:17] =================== ttm_bo (14 subtests) ===================
[06:19:17] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[06:19:17] [PASSED] Cannot be interrupted and sleeps
[06:19:17] [PASSED] Cannot be interrupted, locks straight away
[06:19:17] [PASSED] Can be interrupted, sleeps
[06:19:17] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[06:19:17] [PASSED] ttm_bo_reserve_locked_no_sleep
[06:19:17] [PASSED] ttm_bo_reserve_no_wait_ticket
[06:19:17] [PASSED] ttm_bo_reserve_double_resv
[06:19:17] [PASSED] ttm_bo_reserve_interrupted
[06:19:17] [PASSED] ttm_bo_reserve_deadlock
[06:19:17] [PASSED] ttm_bo_unreserve_basic
[06:19:17] [PASSED] ttm_bo_unreserve_pinned
[06:19:17] [PASSED] ttm_bo_unreserve_bulk
[06:19:17] [PASSED] ttm_bo_fini_basic
[06:19:17] [PASSED] ttm_bo_fini_shared_resv
[06:19:17] [PASSED] ttm_bo_pin_basic
[06:19:17] [PASSED] ttm_bo_pin_unpin_resource
[06:19:17] [PASSED] ttm_bo_multiple_pin_one_unpin
[06:19:17] ===================== [PASSED] ttm_bo ======================
[06:19:17] ============== ttm_bo_validate (21 subtests) ===============
[06:19:17] ============== ttm_bo_init_reserved_sys_man ===============
[06:19:17] [PASSED] Buffer object for userspace
[06:19:17] [PASSED] Kernel buffer object
[06:19:17] [PASSED] Shared buffer object
[06:19:17] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[06:19:17] ============== ttm_bo_init_reserved_mock_man ==============
[06:19:17] [PASSED] Buffer object for userspace
[06:19:17] [PASSED] Kernel buffer object
[06:19:17] [PASSED] Shared buffer object
[06:19:17] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[06:19:17] [PASSED] ttm_bo_init_reserved_resv
[06:19:17] ================== ttm_bo_validate_basic ==================
[06:19:17] [PASSED] Buffer object for userspace
[06:19:17] [PASSED] Kernel buffer object
[06:19:17] [PASSED] Shared buffer object
[06:19:17] ============== [PASSED] ttm_bo_validate_basic ==============
[06:19:17] [PASSED] ttm_bo_validate_invalid_placement
[06:19:17] ============= ttm_bo_validate_same_placement ==============
[06:19:17] [PASSED] System manager
[06:19:17] [PASSED] VRAM manager
[06:19:17] ========= [PASSED] ttm_bo_validate_same_placement ==========
[06:19:17] [PASSED] ttm_bo_validate_failed_alloc
[06:19:17] [PASSED] ttm_bo_validate_pinned
[06:19:17] [PASSED] ttm_bo_validate_busy_placement
[06:19:17] ================ ttm_bo_validate_multihop =================
[06:19:17] [PASSED] Buffer object for userspace
[06:19:17] [PASSED] Kernel buffer object
[06:19:17] [PASSED] Shared buffer object
[06:19:17] ============ [PASSED] ttm_bo_validate_multihop =============
[06:19:17] ========== ttm_bo_validate_no_placement_signaled ==========
[06:19:17] [PASSED] Buffer object in system domain, no page vector
[06:19:17] [PASSED] Buffer object in system domain with an existing page vector
[06:19:17] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[06:19:17] ======== ttm_bo_validate_no_placement_not_signaled ========
[06:19:17] [PASSED] Buffer object for userspace
[06:19:17] [PASSED] Kernel buffer object
[06:19:17] [PASSED] Shared buffer object
[06:19:17] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[06:19:17] [PASSED] ttm_bo_validate_move_fence_signaled
[06:19:17] ========= ttm_bo_validate_move_fence_not_signaled =========
[06:19:17] [PASSED] Waits for GPU
[06:19:17] [PASSED] Tries to lock straight away
[06:19:17] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[06:19:17] [PASSED] ttm_bo_validate_happy_evict
[06:19:17] [PASSED] ttm_bo_validate_all_pinned_evict
[06:19:17] [PASSED] ttm_bo_validate_allowed_only_evict
[06:19:17] [PASSED] ttm_bo_validate_deleted_evict
[06:19:17] [PASSED] ttm_bo_validate_busy_domain_evict
[06:19:17] [PASSED] ttm_bo_validate_evict_gutting
[06:19:17] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[06:19:17] ================= [PASSED] ttm_bo_validate =================
[06:19:17] ============================================================
[06:19:17] Testing complete. Ran 101 tests: passed: 101
[06:19:17] Elapsed time: 11.328s total, 1.693s configuring, 9.419s building, 0.175s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915/dp: On DPCD init/caps wake the DPRx (rev3)
2026-02-19 9:43 [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx Arun R Murthy
` (8 preceding siblings ...)
2026-02-25 6:19 ` ✓ CI.KUnit: success for drm/i915/dp: On DPCD init/caps wake the DPRx (rev3) Patchwork
@ 2026-02-25 6:56 ` Patchwork
2026-02-25 11:20 ` ✗ Xe.CI.FULL: failure " Patchwork
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2026-02-25 6:56 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 867 bytes --]
== Series Details ==
Series: drm/i915/dp: On DPCD init/caps wake the DPRx (rev3)
URL : https://patchwork.freedesktop.org/series/161817/
State : success
== Summary ==
CI Bug Log - changes from xe-4610-4a8ef58307bfc096873745fbb27d0bbc5454676d_BAT -> xe-pw-161817v3_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (14 -> 13)
------------------------------
Missing (1): bat-bmg-3
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-4610-4a8ef58307bfc096873745fbb27d0bbc5454676d -> xe-pw-161817v3
IGT_8770: 8770
xe-4610-4a8ef58307bfc096873745fbb27d0bbc5454676d: 4a8ef58307bfc096873745fbb27d0bbc5454676d
xe-pw-161817v3: 161817v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v3/index.html
[-- Attachment #2: Type: text/html, Size: 1415 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ Xe.CI.FULL: failure for drm/i915/dp: On DPCD init/caps wake the DPRx (rev3)
2026-02-19 9:43 [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx Arun R Murthy
` (9 preceding siblings ...)
2026-02-25 6:56 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-02-25 11:20 ` Patchwork
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2026-02-25 11:20 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 2133 bytes --]
== Series Details ==
Series: drm/i915/dp: On DPCD init/caps wake the DPRx (rev3)
URL : https://patchwork.freedesktop.org/series/161817/
State : failure
== Summary ==
CI Bug Log - changes from xe-4610-4a8ef58307bfc096873745fbb27d0bbc5454676d_FULL -> xe-pw-161817v3_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-161817v3_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-161817v3_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-161817v3_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-free-race-nomemset:
- shard-lnl: NOTRUN -> [ABORT][1]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v3/shard-lnl-5/igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-free-race-nomemset.html
Known issues
------------
Here are the changes found in xe-pw-161817v3_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-lnl: NOTRUN -> [SKIP][2] ([Intel XE#1124])
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v3/shard-lnl-5/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
Build changes
-------------
* Linux: xe-4610-4a8ef58307bfc096873745fbb27d0bbc5454676d -> xe-pw-161817v3
IGT_8770: 8770
xe-4610-4a8ef58307bfc096873745fbb27d0bbc5454676d: 4a8ef58307bfc096873745fbb27d0bbc5454676d
xe-pw-161817v3: 161817v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161817v3/index.html
[-- Attachment #2: Type: text/html, Size: 2737 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCHv2] drm/i915/dp: On DPCD init/caps wake the DPRx
2026-02-25 3:33 ` Murthy, Arun R
2026-02-25 5:58 ` Murthy, Arun R
@ 2026-03-02 7:57 ` Imre Deak
2026-03-02 9:04 ` Murthy, Arun R
1 sibling, 1 reply; 24+ messages in thread
From: Imre Deak @ 2026-03-02 7:57 UTC (permalink / raw)
To: Murthy, Arun R
Cc: intel-gfx, intel-xe, suraj.kandpal, jani.nikula, ville.syrjala
On Wed, Feb 25, 2026 at 09:03:06AM +0530, Murthy, Arun R wrote:
>
> On 24-02-2026 20:20, Imre Deak wrote:
> > On Tue, Feb 24, 2026 at 01:18:30PM +0530, Arun R Murthy wrote:
> > > Its observed that on AUX_CH failure, even if the retry is increased to
> > > 1000, it does not succeed. Either the command might be wrong or sink in
> > > an unknown/sleep state can cause this. So try waking the sink device.
> > > Before reading the DPCD caps wake the sink for eDP and for DP after
> > > reading the lttpr caps if present and before reading the dpcd caps wake
> > > up the sink device.
> > >
> > > v2: Use poll_timeout_us (Jani N)
> > > Add the reason, why this change is required (Ville)
> > >
> > > Closes: https://issues.redhat.com/browse/RHEL-120913
> > I wonder what should be the rule with non-public links like the above.
> > For instance, we do not put VLK-xxx links exactly because those are
> > non-public. Should/could we demand that RedHat opens a public ticket?
> > Jani?
> There is a JIRA as well
> https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
The above ticket is about an
"AUX x did not complete or timeout within 10ms"
error, which means the DPTX didn't complete the transfer. A transfer is
completed either (a) in response to a DPRX reply (AUX ACK,NAK,DEFER
reply) or (b) in case the DPRX is not replying at all. The above error
indicates that DPTX observed/signaled neither a or b. That's a problem
in the DPTX not in the DPRX which this patch is trying to fix (by
setting the DPRX power state to D0).
Please open a separate public ticket for the actually reported
RHEL-120913 issue - which based on the changes in this patch must have a
separate root cause than issues/4391 - and attach a dmesg log having the
AUX logging enabled (drm.debug=0x10e) and reporducing the problem. Also
please ask the reporter to provide the details of the connected eDP
panel model and wiring to the CPU (is there any retimer, mux etc. HW
component between the CPU and the panel?).
> > > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp.c | 38 +++++++++++++++++++
> > > drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> > > .../drm/i915/display/intel_dp_link_training.c | 3 ++
> > > 3 files changed, 42 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 025e906b63a9..fa0730f7b92a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -4705,6 +4705,42 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
> > > intel_edp_set_data_override_rates(intel_dp);
> > > }
> > > +/* Spec says to try for 3 times, its doubled to add the software overhead */
> > > +#define AUX_CH_WAKE_RETRY 6
> > > +
> > > +void intel_dp_wake_sink(struct intel_dp *intel_dp)
> > > +{
> > > + u8 value = 0;
> > > + int ret = 0;
> > > +
> > > + intel_dp_dpcd_set_probe(intel_dp, false);
> > Is there any particular reason to turn off/on the probing? I don't see
> > any reason why the DP_SET_POWER polling would need that. In any case
> > turning it off/on this way is not ok: reading the DPRX caps, which would
> > call this function, could happen at any time after a sink gets
> > connected, so turning probing back on at the end of this function would
> > re-enable it incorrectly for sinks where it's been already established
> > that the probing workaround is not needed and should stay disabled.
> This function intel_dp_wake_sink() is called from edp_init_dpcd and
> dp_init_lttpr_dprx_caps.
> dpcd_set_probe is set to true in dp_aux_init which is called before calling
> intel_edp_init_connector.
>
> Probe is set to true, hence in this function I am setting it to false and
> then setting back to true.
> But there can be a possibility of reading lttpr_dprx_caps being called later
> as well.
>
> Will correct this to check if probe is already being set to true, will then
> disable before waking the sink and restore the probe status at the end.
>
> Will get this corrected in the next revision.
>
> Thanks and Regards,
> Arun R Murthy
> -------------------
>
> > > +
> > > + /*
> > > + * Wake the sink device
> > > + * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by writing 0x02
> > > + * to DP_SET_POWER dpcd reg, 1ms time would be required to wake it up
> > > + */
> > > + ret = poll_timeout_us(ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value),
> > > + ret > 0,
> > > + 1000, AUX_CH_WAKE_RETRY * 1000, true);
> > > +
> > > + /*
> > > + * If sink is in D3 then it may not respond to the AUX tx so
> > > + * wake it up to D3_AUX_ON state
> > > + * If the above poll_timeout_us fails, try waking the sink.
> > > + */
> > > + if (value == DP_SET_POWER_D3 || ret < 0) {
> > > + /* After setting to D0 need a min of 1ms to wake(Spec DP2.1 sec 2.3.1.2) */
> > > + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> > > + DP_SET_POWER_D0);
> > > + fsleep(1000);
> > > + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> > > + DP_SET_POWER_D3_AUX_ON);
> > > + }
> > > +
> > > + intel_dp_dpcd_set_probe(intel_dp, true);
> > > +}
> > > +
> > > static bool
> > > intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
> > > {
> > > @@ -4713,6 +4749,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
> > > /* this function is meant to be called only once */
> > > drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
> > > + intel_dp_wake_sink(intel_dp);
> > > +
> > > if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
> > > return false;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > > index b0bbd5981f57..3f16077c0cc7 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > > @@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
> > > bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
> > > int hdisplay,
> > > int num_joined_pipes);
> > > +void intel_dp_wake_sink(struct intel_dp *intel_dp);
> > > #define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
> > > for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > index 54c585c59b90..cbb712ea9f60 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > @@ -270,6 +270,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
> > > lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
> > > }
> > > + /* After reading LTTPR wake up the sink before reading DPRX caps */
> > > + intel_dp_wake_sink(intel_dp);
> > > +
> > > /*
> > > * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
> > > * it here.
> > > --
> > > 2.25.1
> > >
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCHv2] drm/i915/dp: On DPCD init/caps wake the DPRx
2026-03-02 7:57 ` Imre Deak
@ 2026-03-02 9:04 ` Murthy, Arun R
2026-03-02 9:20 ` Imre Deak
0 siblings, 1 reply; 24+ messages in thread
From: Murthy, Arun R @ 2026-03-02 9:04 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx, intel-xe, suraj.kandpal, jani.nikula, ville.syrjala
On 02-03-2026 13:27, Imre Deak wrote:
> On Wed, Feb 25, 2026 at 09:03:06AM +0530, Murthy, Arun R wrote:
>> On 24-02-2026 20:20, Imre Deak wrote:
>>> On Tue, Feb 24, 2026 at 01:18:30PM +0530, Arun R Murthy wrote:
>>>> Its observed that on AUX_CH failure, even if the retry is increased to
>>>> 1000, it does not succeed. Either the command might be wrong or sink in
>>>> an unknown/sleep state can cause this. So try waking the sink device.
>>>> Before reading the DPCD caps wake the sink for eDP and for DP after
>>>> reading the lttpr caps if present and before reading the dpcd caps wake
>>>> up the sink device.
>>>>
>>>> v2: Use poll_timeout_us (Jani N)
>>>> Add the reason, why this change is required (Ville)
>>>>
>>>> Closes: https://issues.redhat.com/browse/RHEL-120913
>>> I wonder what should be the rule with non-public links like the above.
>>> For instance, we do not put VLK-xxx links exactly because those are
>>> non-public. Should/could we demand that RedHat opens a public ticket?
>>> Jani?
>> There is a JIRA as well
>> https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
> The above ticket is about an
>
> "AUX x did not complete or timeout within 10ms"
>
> error, which means the DPTX didn't complete the transfer. A transfer is
> completed either (a) in response to a DPRX reply (AUX ACK,NAK,DEFER
> reply) or (b) in case the DPRX is not replying at all. The above error
> indicates that DPTX observed/signaled neither a or b. That's a problem
> in the DPTX not in the DPRX which this patch is trying to fix (by
> setting the DPRX power state to D0).
On a Native AUX_CH transaction DPRX can reply with AUX_ACK/NACK/DEFER as
per Table2-177 in the Spec DP2.1.
In the error from the above ticker, we are getting a timeout for a
AUX_CH initiated by DPTX.
Section 2.3.4 of Spec DP2.1 says timeout can be due to No Reply and the
reason for No Reply is either sending invalid command or DPRX in sleep
state or waking up from sleep state.
As part of this state, this patch is trying to wake the DPRX by setting
to D0.
Thanks and Regards,
Arun R Murthy
--------------------
> Please open a separate public ticket for the actually reported
> RHEL-120913 issue - which based on the changes in this patch must have a
> separate root cause than issues/4391 - and attach a dmesg log having the
> AUX logging enabled (drm.debug=0x10e) and reporducing the problem. Also
> please ask the reporter to provide the details of the connected eDP
> panel model and wiring to the CPU (is there any retimer, mux etc. HW
> component between the CPU and the panel?).
>
>>>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_dp.c | 38 +++++++++++++++++++
>>>> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
>>>> .../drm/i915/display/intel_dp_link_training.c | 3 ++
>>>> 3 files changed, 42 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> index 025e906b63a9..fa0730f7b92a 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> @@ -4705,6 +4705,42 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
>>>> intel_edp_set_data_override_rates(intel_dp);
>>>> }
>>>> +/* Spec says to try for 3 times, its doubled to add the software overhead */
>>>> +#define AUX_CH_WAKE_RETRY 6
>>>> +
>>>> +void intel_dp_wake_sink(struct intel_dp *intel_dp)
>>>> +{
>>>> + u8 value = 0;
>>>> + int ret = 0;
>>>> +
>>>> + intel_dp_dpcd_set_probe(intel_dp, false);
>>> Is there any particular reason to turn off/on the probing? I don't see
>>> any reason why the DP_SET_POWER polling would need that. In any case
>>> turning it off/on this way is not ok: reading the DPRX caps, which would
>>> call this function, could happen at any time after a sink gets
>>> connected, so turning probing back on at the end of this function would
>>> re-enable it incorrectly for sinks where it's been already established
>>> that the probing workaround is not needed and should stay disabled.
>> This function intel_dp_wake_sink() is called from edp_init_dpcd and
>> dp_init_lttpr_dprx_caps.
>> dpcd_set_probe is set to true in dp_aux_init which is called before calling
>> intel_edp_init_connector.
>>
>> Probe is set to true, hence in this function I am setting it to false and
>> then setting back to true.
>> But there can be a possibility of reading lttpr_dprx_caps being called later
>> as well.
>>
>> Will correct this to check if probe is already being set to true, will then
>> disable before waking the sink and restore the probe status at the end.
>>
>> Will get this corrected in the next revision.
>>
>> Thanks and Regards,
>> Arun R Murthy
>> -------------------
>>
>>>> +
>>>> + /*
>>>> + * Wake the sink device
>>>> + * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by writing 0x02
>>>> + * to DP_SET_POWER dpcd reg, 1ms time would be required to wake it up
>>>> + */
>>>> + ret = poll_timeout_us(ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value),
>>>> + ret > 0,
>>>> + 1000, AUX_CH_WAKE_RETRY * 1000, true);
>>>> +
>>>> + /*
>>>> + * If sink is in D3 then it may not respond to the AUX tx so
>>>> + * wake it up to D3_AUX_ON state
>>>> + * If the above poll_timeout_us fails, try waking the sink.
>>>> + */
>>>> + if (value == DP_SET_POWER_D3 || ret < 0) {
>>>> + /* After setting to D0 need a min of 1ms to wake(Spec DP2.1 sec 2.3.1.2) */
>>>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>>>> + DP_SET_POWER_D0);
>>>> + fsleep(1000);
>>>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>>>> + DP_SET_POWER_D3_AUX_ON);
>>>> + }
>>>> +
>>>> + intel_dp_dpcd_set_probe(intel_dp, true);
>>>> +}
>>>> +
>>>> static bool
>>>> intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
>>>> {
>>>> @@ -4713,6 +4749,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
>>>> /* this function is meant to be called only once */
>>>> drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
>>>> + intel_dp_wake_sink(intel_dp);
>>>> +
>>>> if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
>>>> return false;
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>>>> index b0bbd5981f57..3f16077c0cc7 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>>>> @@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
>>>> bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>>>> int hdisplay,
>>>> int num_joined_pipes);
>>>> +void intel_dp_wake_sink(struct intel_dp *intel_dp);
>>>> #define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
>>>> for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>>> index 54c585c59b90..cbb712ea9f60 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>>> @@ -270,6 +270,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
>>>> lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
>>>> }
>>>> + /* After reading LTTPR wake up the sink before reading DPRX caps */
>>>> + intel_dp_wake_sink(intel_dp);
>>>> +
>>>> /*
>>>> * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
>>>> * it here.
>>>> --
>>>> 2.25.1
>>>>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCHv2] drm/i915/dp: On DPCD init/caps wake the DPRx
2026-03-02 9:04 ` Murthy, Arun R
@ 2026-03-02 9:20 ` Imre Deak
2026-03-10 8:52 ` Murthy, Arun R
0 siblings, 1 reply; 24+ messages in thread
From: Imre Deak @ 2026-03-02 9:20 UTC (permalink / raw)
To: Murthy, Arun R
Cc: intel-gfx, intel-xe, suraj.kandpal, jani.nikula, ville.syrjala
On Mon, Mar 02, 2026 at 02:34:45PM +0530, Murthy, Arun R wrote:
> On 02-03-2026 13:27, Imre Deak wrote:
> > On Wed, Feb 25, 2026 at 09:03:06AM +0530, Murthy, Arun R wrote:
> > > On 24-02-2026 20:20, Imre Deak wrote:
> > > > On Tue, Feb 24, 2026 at 01:18:30PM +0530, Arun R Murthy wrote:
> > > > > Its observed that on AUX_CH failure, even if the retry is increased to
> > > > > 1000, it does not succeed. Either the command might be wrong or sink in
> > > > > an unknown/sleep state can cause this. So try waking the sink device.
> > > > > Before reading the DPCD caps wake the sink for eDP and for DP after
> > > > > reading the lttpr caps if present and before reading the dpcd caps wake
> > > > > up the sink device.
> > > > >
> > > > > v2: Use poll_timeout_us (Jani N)
> > > > > Add the reason, why this change is required (Ville)
> > > > >
> > > > > Closes: https://issues.redhat.com/browse/RHEL-120913
> > > > I wonder what should be the rule with non-public links like the above.
> > > > For instance, we do not put VLK-xxx links exactly because those are
> > > > non-public. Should/could we demand that RedHat opens a public ticket?
> > > > Jani?
> > > There is a JIRA as well
> > > https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
> > The above ticket is about an
> >
> > "AUX x did not complete or timeout within 10ms"
> >
> > error, which means the DPTX didn't complete the transfer. A transfer is
> > completed either (a) in response to a DPRX reply (AUX ACK,NAK,DEFER
> > reply) or (b) in case the DPRX is not replying at all. The above error
> > indicates that DPTX observed/signaled neither a or b. That's a problem
> > in the DPTX not in the DPRX which this patch is trying to fix (by
> > setting the DPRX power state to D0).
> On a Native AUX_CH transaction DPRX can reply with AUX_ACK/NACK/DEFER as per
> Table2-177 in the Spec DP2.1.
> In the error from the above ticker, we are getting a timeout for a AUX_CH
> initiated by DPTX.
No, we are not getting a timeout from the DPTX AUX HW in the unrelated
ticket you refer to. The error message in the unrelated issues/4391
ticket you refer to merely indicates that the _SW polling_ for
completion times out, which is a completely different thing.
Please open a public ticket with the information I asked, from my side
any workaround like the one suggested in this patch is not acceptable
until that info is available.
> Section 2.3.4 of Spec DP2.1 says timeout can be due to No Reply and the
> reason for No Reply is either sending invalid command or DPRX in sleep state
> or waking up from sleep state.
>
> As part of this state, this patch is trying to wake the DPRX by setting to
> D0.
>
> Thanks and Regards,
> Arun R Murthy
> --------------------
>
> > Please open a separate public ticket for the actually reported
> > RHEL-120913 issue - which based on the changes in this patch must have a
> > separate root cause than issues/4391 - and attach a dmesg log having the
> > AUX logging enabled (drm.debug=0x10e) and reporducing the problem. Also
> > please ask the reporter to provide the details of the connected eDP
> > panel model and wiring to the CPU (is there any retimer, mux etc. HW
> > component between the CPU and the panel?).
> >
> > > > > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_dp.c | 38 +++++++++++++++++++
> > > > > drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> > > > > .../drm/i915/display/intel_dp_link_training.c | 3 ++
> > > > > 3 files changed, 42 insertions(+)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > index 025e906b63a9..fa0730f7b92a 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > @@ -4705,6 +4705,42 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
> > > > > intel_edp_set_data_override_rates(intel_dp);
> > > > > }
> > > > > +/* Spec says to try for 3 times, its doubled to add the software overhead */
> > > > > +#define AUX_CH_WAKE_RETRY 6
> > > > > +
> > > > > +void intel_dp_wake_sink(struct intel_dp *intel_dp)
> > > > > +{
> > > > > + u8 value = 0;
> > > > > + int ret = 0;
> > > > > +
> > > > > + intel_dp_dpcd_set_probe(intel_dp, false);
> > > > Is there any particular reason to turn off/on the probing? I don't see
> > > > any reason why the DP_SET_POWER polling would need that. In any case
> > > > turning it off/on this way is not ok: reading the DPRX caps, which would
> > > > call this function, could happen at any time after a sink gets
> > > > connected, so turning probing back on at the end of this function would
> > > > re-enable it incorrectly for sinks where it's been already established
> > > > that the probing workaround is not needed and should stay disabled.
> > > This function intel_dp_wake_sink() is called from edp_init_dpcd and
> > > dp_init_lttpr_dprx_caps.
> > > dpcd_set_probe is set to true in dp_aux_init which is called before calling
> > > intel_edp_init_connector.
> > >
> > > Probe is set to true, hence in this function I am setting it to false and
> > > then setting back to true.
> > > But there can be a possibility of reading lttpr_dprx_caps being called later
> > > as well.
> > >
> > > Will correct this to check if probe is already being set to true, will then
> > > disable before waking the sink and restore the probe status at the end.
> > >
> > > Will get this corrected in the next revision.
> > >
> > > Thanks and Regards,
> > > Arun R Murthy
> > > -------------------
> > >
> > > > > +
> > > > > + /*
> > > > > + * Wake the sink device
> > > > > + * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by writing 0x02
> > > > > + * to DP_SET_POWER dpcd reg, 1ms time would be required to wake it up
> > > > > + */
> > > > > + ret = poll_timeout_us(ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value),
> > > > > + ret > 0,
> > > > > + 1000, AUX_CH_WAKE_RETRY * 1000, true);
> > > > > +
> > > > > + /*
> > > > > + * If sink is in D3 then it may not respond to the AUX tx so
> > > > > + * wake it up to D3_AUX_ON state
> > > > > + * If the above poll_timeout_us fails, try waking the sink.
> > > > > + */
> > > > > + if (value == DP_SET_POWER_D3 || ret < 0) {
> > > > > + /* After setting to D0 need a min of 1ms to wake(Spec DP2.1 sec 2.3.1.2) */
> > > > > + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> > > > > + DP_SET_POWER_D0);
> > > > > + fsleep(1000);
> > > > > + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> > > > > + DP_SET_POWER_D3_AUX_ON);
> > > > > + }
> > > > > +
> > > > > + intel_dp_dpcd_set_probe(intel_dp, true);
> > > > > +}
> > > > > +
> > > > > static bool
> > > > > intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
> > > > > {
> > > > > @@ -4713,6 +4749,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
> > > > > /* this function is meant to be called only once */
> > > > > drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
> > > > > + intel_dp_wake_sink(intel_dp);
> > > > > +
> > > > > if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
> > > > > return false;
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > > > > index b0bbd5981f57..3f16077c0cc7 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > > > > @@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
> > > > > bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
> > > > > int hdisplay,
> > > > > int num_joined_pipes);
> > > > > +void intel_dp_wake_sink(struct intel_dp *intel_dp);
> > > > > #define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
> > > > > for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > > > index 54c585c59b90..cbb712ea9f60 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > > > @@ -270,6 +270,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
> > > > > lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
> > > > > }
> > > > > + /* After reading LTTPR wake up the sink before reading DPRX caps */
> > > > > + intel_dp_wake_sink(intel_dp);
> > > > > +
> > > > > /*
> > > > > * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
> > > > > * it here.
> > > > > --
> > > > > 2.25.1
> > > > >
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCHv2] drm/i915/dp: On DPCD init/caps wake the DPRx
2026-03-02 9:20 ` Imre Deak
@ 2026-03-10 8:52 ` Murthy, Arun R
0 siblings, 0 replies; 24+ messages in thread
From: Murthy, Arun R @ 2026-03-10 8:52 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx, intel-xe, suraj.kandpal, jani.nikula, ville.syrjala
On 02-03-2026 14:50, Imre Deak wrote:
> On Mon, Mar 02, 2026 at 02:34:45PM +0530, Murthy, Arun R wrote:
>> On 02-03-2026 13:27, Imre Deak wrote:
>>> On Wed, Feb 25, 2026 at 09:03:06AM +0530, Murthy, Arun R wrote:
>>>> On 24-02-2026 20:20, Imre Deak wrote:
>>>>> On Tue, Feb 24, 2026 at 01:18:30PM +0530, Arun R Murthy wrote:
>>>>>> Its observed that on AUX_CH failure, even if the retry is increased to
>>>>>> 1000, it does not succeed. Either the command might be wrong or sink in
>>>>>> an unknown/sleep state can cause this. So try waking the sink device.
>>>>>> Before reading the DPCD caps wake the sink for eDP and for DP after
>>>>>> reading the lttpr caps if present and before reading the dpcd caps wake
>>>>>> up the sink device.
>>>>>>
>>>>>> v2: Use poll_timeout_us (Jani N)
>>>>>> Add the reason, why this change is required (Ville)
>>>>>>
>>>>>> Closes: https://issues.redhat.com/browse/RHEL-120913
>>>>> I wonder what should be the rule with non-public links like the above.
>>>>> For instance, we do not put VLK-xxx links exactly because those are
>>>>> non-public. Should/could we demand that RedHat opens a public ticket?
>>>>> Jani?
>>>> There is a JIRA as well
>>>> https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
>>> The above ticket is about an
>>>
>>> "AUX x did not complete or timeout within 10ms"
>>>
>>> error, which means the DPTX didn't complete the transfer. A transfer is
>>> completed either (a) in response to a DPRX reply (AUX ACK,NAK,DEFER
>>> reply) or (b) in case the DPRX is not replying at all. The above error
>>> indicates that DPTX observed/signaled neither a or b. That's a problem
>>> in the DPTX not in the DPRX which this patch is trying to fix (by
>>> setting the DPRX power state to D0).
>> On a Native AUX_CH transaction DPRX can reply with AUX_ACK/NACK/DEFER as per
>> Table2-177 in the Spec DP2.1.
>> In the error from the above ticker, we are getting a timeout for a AUX_CH
>> initiated by DPTX.
> No, we are not getting a timeout from the DPTX AUX HW in the unrelated
> ticket you refer to. The error message in the unrelated issues/4391
> ticket you refer to merely indicates that the _SW polling_ for
> completion times out, which is a completely different thing.
>
> Please open a public ticket with the information I asked, from my side
> any workaround like the one suggested in this patch is not acceptable
> until that info is available.
Thanks for the clarification on HW and SW timeout.
Unfortunately on this issue, based on the update from the issue creator
it seems that the eDP is not connected and in that case these timeouts
are expected.
Hence closing this thread!
Thanks and Regards,
Arun R Murthy
--------------------
>> Section 2.3.4 of Spec DP2.1 says timeout can be due to No Reply and the
>> reason for No Reply is either sending invalid command or DPRX in sleep state
>> or waking up from sleep state.
>>
>> As part of this state, this patch is trying to wake the DPRX by setting to
>> D0.
>>
>> Thanks and Regards,
>> Arun R Murthy
>> --------------------
>>
>>> Please open a separate public ticket for the actually reported
>>> RHEL-120913 issue - which based on the changes in this patch must have a
>>> separate root cause than issues/4391 - and attach a dmesg log having the
>>> AUX logging enabled (drm.debug=0x10e) and reporducing the problem. Also
>>> please ask the reporter to provide the details of the connected eDP
>>> panel model and wiring to the CPU (is there any retimer, mux etc. HW
>>> component between the CPU and the panel?).
>>>
>>>>>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>>>>>> ---
>>>>>> drivers/gpu/drm/i915/display/intel_dp.c | 38 +++++++++++++++++++
>>>>>> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
>>>>>> .../drm/i915/display/intel_dp_link_training.c | 3 ++
>>>>>> 3 files changed, 42 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>>>>> index 025e906b63a9..fa0730f7b92a 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>>>> @@ -4705,6 +4705,42 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
>>>>>> intel_edp_set_data_override_rates(intel_dp);
>>>>>> }
>>>>>> +/* Spec says to try for 3 times, its doubled to add the software overhead */
>>>>>> +#define AUX_CH_WAKE_RETRY 6
>>>>>> +
>>>>>> +void intel_dp_wake_sink(struct intel_dp *intel_dp)
>>>>>> +{
>>>>>> + u8 value = 0;
>>>>>> + int ret = 0;
>>>>>> +
>>>>>> + intel_dp_dpcd_set_probe(intel_dp, false);
>>>>> Is there any particular reason to turn off/on the probing? I don't see
>>>>> any reason why the DP_SET_POWER polling would need that. In any case
>>>>> turning it off/on this way is not ok: reading the DPRX caps, which would
>>>>> call this function, could happen at any time after a sink gets
>>>>> connected, so turning probing back on at the end of this function would
>>>>> re-enable it incorrectly for sinks where it's been already established
>>>>> that the probing workaround is not needed and should stay disabled.
>>>> This function intel_dp_wake_sink() is called from edp_init_dpcd and
>>>> dp_init_lttpr_dprx_caps.
>>>> dpcd_set_probe is set to true in dp_aux_init which is called before calling
>>>> intel_edp_init_connector.
>>>>
>>>> Probe is set to true, hence in this function I am setting it to false and
>>>> then setting back to true.
>>>> But there can be a possibility of reading lttpr_dprx_caps being called later
>>>> as well.
>>>>
>>>> Will correct this to check if probe is already being set to true, will then
>>>> disable before waking the sink and restore the probe status at the end.
>>>>
>>>> Will get this corrected in the next revision.
>>>>
>>>> Thanks and Regards,
>>>> Arun R Murthy
>>>> -------------------
>>>>
>>>>>> +
>>>>>> + /*
>>>>>> + * Wake the sink device
>>>>>> + * Spec DP2.1 section 2.3.1.2 if AUX CH is powered down by writing 0x02
>>>>>> + * to DP_SET_POWER dpcd reg, 1ms time would be required to wake it up
>>>>>> + */
>>>>>> + ret = poll_timeout_us(ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value),
>>>>>> + ret > 0,
>>>>>> + 1000, AUX_CH_WAKE_RETRY * 1000, true);
>>>>>> +
>>>>>> + /*
>>>>>> + * If sink is in D3 then it may not respond to the AUX tx so
>>>>>> + * wake it up to D3_AUX_ON state
>>>>>> + * If the above poll_timeout_us fails, try waking the sink.
>>>>>> + */
>>>>>> + if (value == DP_SET_POWER_D3 || ret < 0) {
>>>>>> + /* After setting to D0 need a min of 1ms to wake(Spec DP2.1 sec 2.3.1.2) */
>>>>>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>>>>>> + DP_SET_POWER_D0);
>>>>>> + fsleep(1000);
>>>>>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>>>>>> + DP_SET_POWER_D3_AUX_ON);
>>>>>> + }
>>>>>> +
>>>>>> + intel_dp_dpcd_set_probe(intel_dp, true);
>>>>>> +}
>>>>>> +
>>>>>> static bool
>>>>>> intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
>>>>>> {
>>>>>> @@ -4713,6 +4749,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
>>>>>> /* this function is meant to be called only once */
>>>>>> drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
>>>>>> + intel_dp_wake_sink(intel_dp);
>>>>>> +
>>>>>> if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
>>>>>> return false;
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>>>>>> index b0bbd5981f57..3f16077c0cc7 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>>>>>> @@ -232,6 +232,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
>>>>>> bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>>>>>> int hdisplay,
>>>>>> int num_joined_pipes);
>>>>>> +void intel_dp_wake_sink(struct intel_dp *intel_dp);
>>>>>> #define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
>>>>>> for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>>>>> index 54c585c59b90..cbb712ea9f60 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>>>>> @@ -270,6 +270,9 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
>>>>>> lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
>>>>>> }
>>>>>> + /* After reading LTTPR wake up the sink before reading DPRX caps */
>>>>>> + intel_dp_wake_sink(intel_dp);
>>>>>> +
>>>>>> /*
>>>>>> * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
>>>>>> * it here.
>>>>>> --
>>>>>> 2.25.1
>>>>>>
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2026-03-10 8:53 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-02-19 9:43 [PATCH] drm/i915/dp: On DPCD init/caps wake the DPRx Arun R Murthy
2026-02-19 10:45 ` ✗ CI.checkpatch: warning for " Patchwork
2026-02-19 10:46 ` ✓ CI.KUnit: success " Patchwork
2026-02-19 11:22 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-19 14:20 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-02-19 14:53 ` [PATCH] " Ville Syrjälä
2026-02-19 15:12 ` Murthy, Arun R
2026-02-20 3:11 ` Ville Syrjälä
2026-02-20 5:01 ` Murthy, Arun R
2026-02-24 8:24 ` Ville Syrjälä
2026-02-24 8:48 ` Murthy, Arun R
2026-02-24 7:48 ` [PATCHv2] " Arun R Murthy
2026-02-24 14:50 ` Imre Deak
2026-02-25 3:33 ` Murthy, Arun R
2026-02-25 5:58 ` Murthy, Arun R
2026-03-02 7:57 ` Imre Deak
2026-03-02 9:04 ` Murthy, Arun R
2026-03-02 9:20 ` Imre Deak
2026-03-10 8:52 ` Murthy, Arun R
2026-02-24 7:56 ` ✓ CI.KUnit: success for drm/i915/dp: On DPCD init/caps wake the DPRx (rev2) Patchwork
2026-02-25 6:11 ` [PATCHv3] drm/i915/dp: On DPCD init wake the DPRx for eDP Arun R Murthy
2026-02-25 6:19 ` ✓ CI.KUnit: success for drm/i915/dp: On DPCD init/caps wake the DPRx (rev3) Patchwork
2026-02-25 6:56 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-25 11:20 ` ✗ Xe.CI.FULL: failure " Patchwork
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox