[PATCH v2 00/23] Workaround cleanup & simplification

[PATCH v2 00/23] Workaround cleanup & simplification

[Matt Roper]

The majority of the patches in this series relate to the new policy of
allowing GRAPHICS_VERSION_RANGE() and MEDIA_VERSION_RANGE() to extend
across currently-unused version numbers.  Obviously there are a lot of
unused numbers between major IP generations (e.g., Xe2's 20.xx to Xe3's
30.xx), but there are also cases where random version numbers in the
middle of a bunch of other versions go unused (for example, we currently
have variants of Xe3_LPG IP using every version number from 30.00 to
30.05 *except* for 30.02).  Allowing ranges to cover currently-unused IP
numbers allows simpler RTP matching rules and cleaner code.  The price
for this is that additional work and review will be required if an
intermediate IP version like 30.02 shows up in the future --- we'll need
to analyze each range that covers the new version to determine whether
the workaround also applies to the new IP, or whether we need to split
the existing range into two separate ranges.  The platform enabling
engineers are willing to take on this extra review burden. [1]

Aside from RTP rule consolidation according to the new policy, this
series also drops some Xe1 workarounds that were only relevant to
pre-production platforms (the Xe KMD doesn't officially support Xe1
platforms since i915 should be used instead, but pre-production Xe1
hardware is especially out of scope).  There's also one BMG workaround
(Wa_15010599737) which was invalid and is dropped completely.

[1] https://lore.kernel.org/all/20260203233600.GT458797@mdroper-desk1.amr.corp.intel.com/

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
Changes in v2:
- Also remove an unused flag and two functions that are now dead code
  when dropping PVC pre-production workaround 1509372804.
- Consolidate the newly-added entry for Wa_18041344222 on graphics
  version 20.04.
- Consolidate OR'd ranges for Wa_14023061436.
- Link to v1: https://lore.kernel.org/r/20260213-forupstream-wa_cleanup-v1-0-961f2dd3a8e9@intel.com

---
Matt Roper (23):
      drm/xe/mtl: Drop pre-prod workarounds Wa_14015795083 & Wa_14014475959
      drm/xe/pvc: Drop pre-prod workarounds
      drm/xe/wa: Document new policy regarding workaround IP ranges
      drm/xe: Consolidate workaround entries for Wa_16021867713
      drm/xe: Consolidate workaround entries for Wa_14019449301
      drm/xe: Consolidate workaround entries for Wa_16028005424
      drm/xe: Consolidate workaround entries for Wa_16021865536
      drm/xe: Consolidate workaround entries for Wa_18032247524
      drm/xe: Consolidate workaround entries for Wa_16018712365
      drm/xe: Consolidate workaround entries for Wa_14020338487
      drm/xe: Consolidate workaround entries for Wa_14018471104
      drm/xe: Consolidate workaround entries for Wa_16021639441
      drm/xe: Consolidate workaround entries for Wa_14021402888
      drm/xe: Consolidate workaround entries for Wa_13012615864
      drm/xe: Consolidate workaround entries for Wa_18041344222
      drm/xe: Consolidate workaround entries for Wa_14019877138
      drm/xe: Consolidate workaround entries for Wa_14019386621
      drm/xe: Consolidate workaround entries for Wa_14019988906
      drm/xe: Consolidate workaround entries for Wa_18033852989
      drm/xe: Consolidate workaround entries for Wa_15016589081
      drm/xe/xe2_hpg: Drop invalid workaround Wa_15010599737
      drm/xe/wa_oob: Consolidate some OOB rules
      drm/xe: Consolidate workaround entries for Wa_14023061436

 drivers/gpu/drm/xe/xe_guc.c        |   3 -
 drivers/gpu/drm/xe/xe_guc_rc.c     |  29 ---
 drivers/gpu/drm/xe/xe_guc_rc.h     |   2 -
 drivers/gpu/drm/xe/xe_oa.c         |  19 --
 drivers/gpu/drm/xe/xe_oa_types.h   |   3 -
 drivers/gpu/drm/xe/xe_wa.c         | 374 ++++++++++---------------------------
 drivers/gpu/drm/xe/xe_wa_oob.rules |  36 +---
 7 files changed, 112 insertions(+), 354 deletions(-)
---
base-commit: 5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13
change-id: 20260213-forupstream-wa_cleanup-490f5a899404

Best regards,
-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH v2 01/23] drm/xe/mtl: Drop pre-prod workarounds Wa_14015795083 & Wa_14014475959

[Matt Roper]

Wa_14015795083 and Wa_14014475959 only apply to early steppings of
Xe_LPG that appeared only in pre-production hardware (in fact
Wa_14014475959 wasn't supposed to apply to _any_ steppings of version
12.71).  Xe1 platforms already aren't officially supported by the Xe
driver, but pre-production steppings are especially out of scope (and
'has_pre_prod_wa' is not set in the device descriptor).  Drop both
workarounds.

Bspec: 55420
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c         | 4 ----
 drivers/gpu/drm/xe/xe_wa_oob.rules | 3 +--
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 76fa6d510aadb91169170ba35f65390c477a569e..aa5755bcdc04a3ec2569ab9676a9dd95516f1711 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -191,10 +191,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 
 	/* Xe_LPG */
 
-	{ XE_RTP_NAME("14015795083"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)),
-	  XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
-	},
 	{ XE_RTP_NAME("14018575942"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
 	  XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index ac08f94f90a142629545c4964ca0fd3f9cad6aa9..cc988f2a18d33365dc09d32f4e85ced01b823877 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -2,8 +2,7 @@
 16010904313	GRAPHICS_VERSION_RANGE(1200, 1210)
 18022495364	GRAPHICS_VERSION_RANGE(1200, 1210)
 22012773006	GRAPHICS_VERSION_RANGE(1200, 1250)
-14014475959	GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)
-		PLATFORM(DG2)
+14014475959	PLATFORM(DG2)
 22011391025	PLATFORM(DG2)
 22012727170	SUBPLATFORM(DG2, G11)
 22012727685	SUBPLATFORM(DG2, G11)

-- 
2.53.0

[PATCH v2 02/23] drm/xe/pvc: Drop pre-prod workarounds

[Matt Roper]

Production PVC hardware had a graphics stepping of C0.  Xe1 platforms
already aren't officially supported by the Xe driver, but pre-production
steppings are especially out of scope (and 'has_pre_prod_wa' is not set
in the device descriptor).  Drop the workarounds that aren't relevant to
production hardware.

v2:
 - Drop the stream->override_gucrc which is no longer set anywhere after
   the removal of Wa_1509372804.  (Bala)
 - Drop xe_guc_rc_set_mode / xe_guc_rc_unset_mode which are no longer
   used after the removal of Wa_1509372804.

Bspec: 44484
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_guc.c        |  3 ---
 drivers/gpu/drm/xe/xe_guc_rc.c     | 29 -----------------------------
 drivers/gpu/drm/xe/xe_guc_rc.h     |  2 --
 drivers/gpu/drm/xe/xe_oa.c         | 19 -------------------
 drivers/gpu/drm/xe/xe_oa_types.h   |  3 ---
 drivers/gpu/drm/xe/xe_wa.c         |  5 -----
 drivers/gpu/drm/xe/xe_wa_oob.rules |  2 --
 7 files changed, 63 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index cbbb4d665b8fe66105727e83cfc59a13624d259e..54d2fc780127742e2e152da438c7d3e8332f3cbc 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -213,9 +213,6 @@ static u32 guc_ctl_wa_flags(struct xe_guc *guc)
 	    !xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER))
 		flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
 
-	if (XE_GT_WA(gt, 1509372804))
-		flags |= GUC_WA_RENDER_RST_RC6_EXIT;
-
 	if (XE_GT_WA(gt, 14018913170))
 		flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6;
 
diff --git a/drivers/gpu/drm/xe/xe_guc_rc.c b/drivers/gpu/drm/xe/xe_guc_rc.c
index 427a889b2a1e04b1d01bd7db8add20ce41f60ce5..99fa127b261ffb0fe7bdae5fcbc78258f67529a8 100644
--- a/drivers/gpu/drm/xe/xe_guc_rc.c
+++ b/drivers/gpu/drm/xe/xe_guc_rc.c
@@ -129,32 +129,3 @@ int xe_guc_rc_enable(struct xe_guc *guc)
 
 	return guc_action_setup_gucrc(guc, GUCRC_FIRMWARE_CONTROL);
 }
-
-/**
- * xe_guc_rc_set_mode() - set new GUCRC mode
- * @guc: Xe GuC instance
- * @mode: new value of the mode.
- *
- * Function to set GuC RC mode to one of the enum values.
- *
- * Returns: 0 on success, negative error code on error
- */
-int xe_guc_rc_set_mode(struct xe_guc *guc, enum slpc_gucrc_mode mode)
-{
-	guard(xe_pm_runtime_noresume)(guc_to_xe(guc));
-	return xe_guc_pc_action_set_param(&guc->pc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
-}
-
-/**
- * xe_guc_rc_unset_mode() - revert to default mode
- * @guc: Xe GuC instance
- *
- * Function to revert GuC RC mode to platform defaults.
- *
- * Returns: 0 on success, negative error code on error
- */
-int xe_guc_rc_unset_mode(struct xe_guc *guc)
-{
-	guard(xe_pm_runtime_noresume)(guc_to_xe(guc));
-	return xe_guc_pc_action_unset_param(&guc->pc, SLPC_PARAM_PWRGATE_RC_MODE);
-}
diff --git a/drivers/gpu/drm/xe/xe_guc_rc.h b/drivers/gpu/drm/xe/xe_guc_rc.h
index f1f949e7ecc0c6afab3eaeb616fe49d0437d710c..b083fc364dd430e5868a4e6da62b5777f5a6f1e1 100644
--- a/drivers/gpu/drm/xe/xe_guc_rc.h
+++ b/drivers/gpu/drm/xe/xe_guc_rc.h
@@ -12,7 +12,5 @@ enum slpc_gucrc_mode;
 int xe_guc_rc_init(struct xe_guc *guc);
 int xe_guc_rc_enable(struct xe_guc *guc);
 void xe_guc_rc_disable(struct xe_guc *guc);
-int xe_guc_rc_set_mode(struct xe_guc *guc, enum slpc_gucrc_mode mode);
-int xe_guc_rc_unset_mode(struct xe_guc *guc);
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index a462d6983d8d6daf74beaf6fef5bfe2ab779179d..72fc4424017bf8fb7a42e3a3ae3f6adfe91cf21d 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -873,10 +873,6 @@ static void xe_oa_stream_destroy(struct xe_oa_stream *stream)
 	xe_force_wake_put(gt_to_fw(gt), stream->fw_ref);
 	xe_pm_runtime_put(stream->oa->xe);
 
-	/* Wa_1509372804:pvc: Unset the override of GUCRC mode to enable rc6 */
-	if (stream->override_gucrc)
-		xe_gt_WARN_ON(gt, xe_guc_rc_unset_mode(&gt->uc.guc));
-
 	xe_oa_free_configs(stream);
 	xe_file_put(stream->xef);
 }
@@ -1760,18 +1756,6 @@ static int xe_oa_stream_init(struct xe_oa_stream *stream,
 		goto exit;
 	}
 
-	/*
-	 * GuC reset of engines causes OA to lose configuration
-	 * state. Prevent this by overriding GUCRC mode.
-	 */
-	if (XE_GT_WA(stream->gt, 1509372804)) {
-		ret = xe_guc_rc_set_mode(&gt->uc.guc, SLPC_GUCRC_MODE_GUCRC_NO_RC6);
-		if (ret)
-			goto err_free_configs;
-
-		stream->override_gucrc = true;
-	}
-
 	/* Take runtime pm ref and forcewake to disable RC6 */
 	xe_pm_runtime_get(stream->oa->xe);
 	stream->fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
@@ -1822,9 +1806,6 @@ static int xe_oa_stream_init(struct xe_oa_stream *stream,
 err_fw_put:
 	xe_force_wake_put(gt_to_fw(gt), stream->fw_ref);
 	xe_pm_runtime_put(stream->oa->xe);
-	if (stream->override_gucrc)
-		xe_gt_WARN_ON(gt, xe_guc_rc_unset_mode(&gt->uc.guc));
-err_free_configs:
 	xe_oa_free_configs(stream);
 exit:
 	xe_file_put(stream->xef);
diff --git a/drivers/gpu/drm/xe/xe_oa_types.h b/drivers/gpu/drm/xe/xe_oa_types.h
index 08cc8d7c221582662abff9397e27fbb8ccca468a..b03ffd513483449adc6b2937c0707e5bfc619a5b 100644
--- a/drivers/gpu/drm/xe/xe_oa_types.h
+++ b/drivers/gpu/drm/xe/xe_oa_types.h
@@ -239,9 +239,6 @@ struct xe_oa_stream {
 	/** @poll_period_ns: hrtimer period for checking OA buffer for available data */
 	u64 poll_period_ns;
 
-	/** @override_gucrc: GuC RC has been overridden for the OA stream */
-	bool override_gucrc;
-
 	/** @oa_status: temporary storage for oa_status register value */
 	u32 oa_status;
 
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index aa5755bcdc04a3ec2569ab9676a9dd95516f1711..4b2c77f51fd830fe2439708865fb0b966545bc71 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -499,11 +499,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       ENGINE_CLASS(COMPUTE)),
 	  XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0))
 	},
-	{ XE_RTP_NAME("14014999345"),
-	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE),
-		       GRAPHICS_STEP(B0, C0)),
-	  XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
-	},
 
 	/* Xe_LPG */
 
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index cc988f2a18d33365dc09d32f4e85ced01b823877..c3222d9504889b5175fdfa73db0bf4e9910a277d 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -8,7 +8,6 @@
 22012727685	SUBPLATFORM(DG2, G11)
 22016596838	PLATFORM(PVC)
 18020744125	PLATFORM(PVC)
-1509372804	PLATFORM(PVC), GRAPHICS_STEP(A0, C0)
 1409600907	GRAPHICS_VERSION_RANGE(1200, 1250)
 22014953428	SUBPLATFORM(DG2, G10)
 		SUBPLATFORM(DG2, G12)
@@ -53,7 +52,6 @@
 18013179988	GRAPHICS_VERSION(1255)
 		GRAPHICS_VERSION_RANGE(1270, 1274)
 1508761755	GRAPHICS_VERSION(1255)
-		GRAPHICS_VERSION(1260), GRAPHICS_STEP(A0, B0)
 16023105232	GRAPHICS_VERSION_RANGE(2001, 3001)
 		MEDIA_VERSION_RANGE(1301, 3000)
 		MEDIA_VERSION(3002)

-- 
2.53.0

[PATCH v2 03/23] drm/xe/wa: Document new policy regarding workaround IP ranges

[Matt Roper]

During early Xe driver development, our policy for applying workarounds
to ranges of IP versions was to only use GRAPHICS_VERSION_RANGE and
MEDIA_VERSION_RANGE rules when all of the affected IP versions had
consecutive version numbers; otherwise separate RTP entries should be
used.  For example, a workaround that applies to all Xe2-based platforms
would be implemented in the driver with two RTP entries:  one using
GRAPHICS_VERSION_RANGE(2001, 2002) and the other using
GRAPHICS_VERSION(2004).  This ensured that if a new IP variant showed up
in the future with currently unused version 20.03, an old workaround
entry wouldn't automatically apply to it by accident (and we could
always consolidate those two distinct entries in the future if the
workaround database did explicitly indicate that 20.03 also needed the
workaround).

Now that we're a couple years down the road with this driver, the number
of IP versions supported is much larger (several Xe2 20.xx versions,
several Xe3 30.xx versions, and a couple Xe3p 35.xx versions).  When new
workarounds are discovered that need to apply to a wide range of IPs,
it's becoming more of a pain to create independent entries for each
non-contiguous range of versions, and the general consensus is that we
should revisit our previous policy and start allowing use of
VERSION_RANGE constructs for non-contiguous version ranges.

Note that allowing ranges that cover currently unused versions will
require additional care if/when some of those intermediate version
numbers start being used in the future.  We'll need to re-check every
workaround that has a range including the new IP version and check the
hardware database to see whether the workaround also applies to the new
version (no code change required) or whether we need to split the
existing range into two separate ranges that don't cover the new
version.  The platform enabling engineers are willing to take on this
extra review burden at the time we first enable a new IP in the driver
(see lore link below for one recent discussion).

Update the kerneldoc for the workaround file to make the new policy
official.

Link: https://lore.kernel.org/all/20260203233600.GT458797@mdroper-desk1.amr.corp.intel.com/
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 4b2c77f51fd830fe2439708865fb0b966545bc71..c3d694947bd5d2b178e9da08bb937dc6a171b326 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -111,6 +111,17 @@
  *    difference of how they are maintained in the code. In xe it uses the
  *    xe_rtp infrastructure so the workarounds can be kept in tables, following
  *    a more declarative approach rather than procedural.
+ *
+ * .. note::
+ *    When a workaround applies to every single known IP version in a range,
+ *    the preferred handling is to use a single range-based RTP entry rather
+ *    than individual entries for each version, even if some of the intermediate
+ *    version numbers are currently unused.  If a new intermediate IP version
+ *    appears in the future and is enabled in the driver, any existing
+ *    range-based entries that contain the new version number will need to be
+ *    analyzed to determine whether their workarounds should apply to the new
+ *    version, or whether any existing range based entries needs to be split
+ *    into two entries that do not include the new intermediate version.
  */
 
 #undef XE_REG_MCR

-- 
2.53.0

[PATCH v2 04/23] drm/xe: Consolidate workaround entries for Wa_16021867713

[Matt Roper]

Wa_16021867713 applies to every single media IP from 13.00 to 30.02
(inclusive).  We can consolidate the multiple per-version entries down
to a single range entry.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 38 ++++++++------------------------------
 1 file changed, 8 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index c3d694947bd5d2b178e9da08bb937dc6a171b326..4a8685f2ea985cb67b21bdf8a043ad1dfdfc816d 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -131,6 +131,8 @@ __diag_push();
 __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
 
 static const struct xe_rtp_entry_sr gt_was[] = {
+	/* Workarounds applying over a range of IPs */
+
 	{ XE_RTP_NAME("14011060649"),
 	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
 		       ENGINE_CLASS(VIDEO_DECODE),
@@ -146,6 +148,12 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),
 	  XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
 	},
+	{ XE_RTP_NAME("16021867713"),
+	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1300, 3002),
+		       ENGINE_CLASS(VIDEO_DECODE)),
+	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
+	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
+	},
 
 	/* DG1 */
 
@@ -213,12 +221,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 
 	/* Xe_LPM+ */
 
-	{ XE_RTP_NAME("16021867713"),
-	  XE_RTP_RULES(MEDIA_VERSION(1300),
-		       ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
 	{ XE_RTP_NAME("22016670082"),
 	  XE_RTP_RULES(MEDIA_VERSION(1300)),
 	  XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
@@ -232,12 +234,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
 	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
 	},
-	{ XE_RTP_NAME("16021867713"),
-	  XE_RTP_RULES(MEDIA_VERSION(2000),
-		       ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
 	{ XE_RTP_NAME("14019449301"),
 	  XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),
 	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
@@ -262,12 +258,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 
 	/* Xe2_HPM */
 
-	{ XE_RTP_NAME("16021867713"),
-	  XE_RTP_RULES(MEDIA_VERSION(1301),
-		       ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
 	{ XE_RTP_NAME("14019449301"),
 	  XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
 	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
@@ -291,12 +281,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 
 	/* Xe3_LPM */
 
-	{ XE_RTP_NAME("16021867713"),
-	  XE_RTP_RULES(MEDIA_VERSION(3000),
-		       ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
 	{ XE_RTP_NAME("16021865536"),
 	  XE_RTP_RULES(MEDIA_VERSION(3000),
 		       ENGINE_CLASS(VIDEO_DECODE)),
@@ -309,12 +293,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
 	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
 	},
-	{ XE_RTP_NAME("16021867713"),
-	  XE_RTP_RULES(MEDIA_VERSION(3002),
-		       ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
 	{ XE_RTP_NAME("14021486841"),
 	  XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),
 		       ENGINE_CLASS(VIDEO_DECODE)),

-- 
2.53.0

[PATCH v2 05/23] drm/xe: Consolidate workaround entries for Wa_14019449301

[Matt Roper]

Wa_14019449301 applies to both media IP 13.01 and 20.00 and none of the
version numbers between those are used.  Conslidate the two entries into
a single range entry.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 4a8685f2ea985cb67b21bdf8a043ad1dfdfc816d..33e7e33db83175953361ee13dd40af8954c6d838 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -154,6 +154,11 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
 	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
 	},
+	{ XE_RTP_NAME("14019449301"),
+	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 2000), ENGINE_CLASS(VIDEO_DECODE)),
+	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
+	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
+	},
 
 	/* DG1 */
 
@@ -234,11 +239,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
 	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
 	},
-	{ XE_RTP_NAME("14019449301"),
-	  XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
 	{ XE_RTP_NAME("16028005424"),
 	  XE_RTP_RULES(MEDIA_VERSION(2000)),
 	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
@@ -258,11 +258,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 
 	/* Xe2_HPM */
 
-	{ XE_RTP_NAME("14019449301"),
-	  XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
 	{ XE_RTP_NAME("16028005424"),
 	  XE_RTP_RULES(MEDIA_VERSION(1301)),
 	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))

-- 
2.53.0

[PATCH v2 06/23] drm/xe: Consolidate workaround entries for Wa_16028005424

[Matt Roper]

Wa_16028005424 applies to all media IPs from 13.01 to 35.00 (inclusive)
and all graphics IPs from 30.00 and 30.05 (inclusive).  Conslidate the
multiple RTP entries into a single range-based entry.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 31 +++++--------------------------
 1 file changed, 5 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 33e7e33db83175953361ee13dd40af8954c6d838..4009323da8021cf5791a96e119b7b71b64eb4431 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -159,6 +159,11 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
 	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
 	},
+	{ XE_RTP_NAME("16028005424"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), OR,
+		       MEDIA_VERSION_RANGE(1301, 3500)),
+	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
+	},
 
 	/* DG1 */
 
@@ -239,10 +244,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
 	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
 	},
-	{ XE_RTP_NAME("16028005424"),
-	  XE_RTP_RULES(MEDIA_VERSION(2000)),
-	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
-	},
 
 	/* Xe2_HPG */
 
@@ -256,23 +257,12 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 			     LSN_DIM_Z_WGT(1)))
 	},
 
-	/* Xe2_HPM */
-
-	{ XE_RTP_NAME("16028005424"),
-	  XE_RTP_RULES(MEDIA_VERSION(1301)),
-	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
-	},
-
 	/* Xe3_LPG */
 
 	{ XE_RTP_NAME("14021871409"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)),
 	  XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS))
 	},
-	{ XE_RTP_NAME("16028005424"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005)),
-	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
-	},
 
 	/* Xe3_LPM */
 
@@ -294,17 +284,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)),
 	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
 	},
-	{ XE_RTP_NAME("16028005424"),
-	  XE_RTP_RULES(MEDIA_VERSION_RANGE(3000, 3002)),
-	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
-	},
-
-	/* Xe3p_LPM */
-
-	{ XE_RTP_NAME("16028005424"),
-	  XE_RTP_RULES(MEDIA_VERSION(3500)),
-	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
-	},
 
 	/* Xe3P_LPG */
 

-- 
2.53.0

[PATCH v2 07/23] drm/xe: Consolidate workaround entries for Wa_16021865536

[Matt Roper]

Wa_16021865536 applies to both media versions 30.00 and 30.02; since
version 30.01 is currently unused we can consolidate the two RTP entries
into a single range-based entry.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 4009323da8021cf5791a96e119b7b71b64eb4431..092d46f48165d17b0ab4bf2a7e4550b97e137aad 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -267,13 +267,7 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 	/* Xe3_LPM */
 
 	{ XE_RTP_NAME("16021865536"),
-	  XE_RTP_RULES(MEDIA_VERSION(3000),
-		       ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
-	{ XE_RTP_NAME("16021865536"),
-	  XE_RTP_RULES(MEDIA_VERSION(3002),
+	  XE_RTP_RULES(MEDIA_VERSION_RANGE(3000, 3002),
 		       ENGINE_CLASS(VIDEO_DECODE)),
 	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
 	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),

-- 
2.53.0

[PATCH v2 08/23] drm/xe: Consolidate workaround entries for Wa_18032247524

[Matt Roper]

Wa_18032247524 applies to all graphics versions from 20.01 through 20.04
(inclusive).  Consolidate the two RTP entries into a single range-based
entry.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 092d46f48165d17b0ab4bf2a7e4550b97e137aad..a483a76c7665eba1c6a87a18bab1a31d11a01f4d 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -306,6 +306,8 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 };
 
 static const struct xe_rtp_entry_sr engine_was[] = {
+	/* Workarounds applying over a range of IPs */
+
 	{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
@@ -341,6 +343,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 	  XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),
 			     FFSC_PERCTX_PREEMPT_CTRL))
 	},
+	{ XE_RTP_NAME("18032247524"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
+		       FUNC(xe_rtp_match_first_render_or_compute)),
+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
+	},
 
 	/* TGL */
 
@@ -478,11 +485,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 
 	/* Xe2_LPG */
 
-	{ XE_RTP_NAME("18032247524"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
-	},
 	{ XE_RTP_NAME("16018712365"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
@@ -551,11 +553,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
 	},
-	{ XE_RTP_NAME("18032247524"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
-	},
 	{ XE_RTP_NAME("14018471104"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
 		       FUNC(xe_rtp_match_first_render_or_compute)),

-- 
2.53.0

[PATCH v2 09/23] drm/xe: Consolidate workaround entries for Wa_16018712365

[Matt Roper]

Wa_16018712365 applies to all graphics versions from 20.01 through 20.04
(inclusive).  Consolidate the two RTP entries into a single range-based
entry.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 14 +++++---------
 1 file changed, 5 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index a483a76c7665eba1c6a87a18bab1a31d11a01f4d..f99f1fbe3aee016d8a8aa19d62f6fd503e6e19f2 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -348,6 +348,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
 	},
+	{ XE_RTP_NAME("16018712365"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
+		       FUNC(xe_rtp_match_first_render_or_compute)),
+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
+	},
 
 	/* TGL */
 
@@ -485,10 +490,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 
 	/* Xe2_LPG */
 
-	{ XE_RTP_NAME("16018712365"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
-	},
 	{ XE_RTP_NAME("14020338487"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
@@ -538,11 +539,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 
 	/* Xe2_HPG */
 
-	{ XE_RTP_NAME("16018712365"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
-	},
 	{ XE_RTP_NAME("16018737384"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2999),
 		       FUNC(xe_rtp_match_first_render_or_compute)),

-- 
2.53.0

[PATCH v2 10/23] drm/xe: Consolidate workaround entries for Wa_14020338487

[Matt Roper]

Wa_14020338487 applies to all graphics versions from 20.01 through 20.04
(inclusive).  Consolidate the two RTP entries into a single range-based
entry.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 14 +++++---------
 1 file changed, 5 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index f99f1fbe3aee016d8a8aa19d62f6fd503e6e19f2..4809166ba8ec69fc913fe2ca0103fe54e345dd14 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -353,6 +353,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
 	},
+	{ XE_RTP_NAME("14020338487"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
+		       FUNC(xe_rtp_match_first_render_or_compute)),
+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
+	},
 
 	/* TGL */
 
@@ -490,10 +495,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 
 	/* Xe2_LPG */
 
-	{ XE_RTP_NAME("14020338487"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
-	},
 	{ XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
 		       FUNC(xe_rtp_match_first_render_or_compute)),
@@ -544,11 +545,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
 	},
-	{ XE_RTP_NAME("14020338487"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
-	},
 	{ XE_RTP_NAME("14018471104"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
 		       FUNC(xe_rtp_match_first_render_or_compute)),

-- 
2.53.0

[PATCH v2 11/23] drm/xe: Consolidate workaround entries for Wa_14018471104

[Matt Roper]

Wa_14018471104 applies to all graphics versions from 20.01 through 20.04
(inclusive).  Consolidate the two RTP entries into a single range-based
entry.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 14 +++++---------
 1 file changed, 5 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 4809166ba8ec69fc913fe2ca0103fe54e345dd14..9119ca9ba1031d9180b44c13a702e1bb04fd0ca6 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -358,6 +358,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
 	},
+	{ XE_RTP_NAME("14018471104"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
+		       FUNC(xe_rtp_match_first_render_or_compute)),
+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
+	},
 
 	/* TGL */
 
@@ -500,10 +505,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
 	},
-	{ XE_RTP_NAME("14018471104"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
-	},
 	/*
 	 * These two workarounds are the same, just applying to different
 	 * engines.  Although Wa_18032095049 (for the RCS) isn't required on
@@ -545,11 +546,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
 	},
-	{ XE_RTP_NAME("14018471104"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
-	},
 	/*
 	 * Although this workaround isn't required for the RCS, disabling these
 	 * reports has no impact for our driver or the GuC, so we go ahead and

-- 
2.53.0

[PATCH v2 12/23] drm/xe: Consolidate workaround entries for Wa_16021639441

[Matt Roper]

Wa_16021639441 applies to all graphics versions from 20.01 through 20.04
(inclusive) and all media versions from 13.01 to 20.00 (inclusive).
Consolidate the RTP entries into a single range-based entry.
Also drop the reference to Wa_18032095049 which was only relevant to
pre-production platforms that we no longer support.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 59 ++++++++++------------------------------------
 1 file changed, 13 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 9119ca9ba1031d9180b44c13a702e1bb04fd0ca6..f0c42be062146837e6ba40621af54fcafa34f8e8 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -363,6 +363,19 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
 	},
+	/*
+	 * Although this workaround isn't required for the RCS, disabling these
+	 * reports has no impact for our driver or the GuC, so we go ahead and
+	 * apply this to all engines for simplicity.
+	 */
+	{ XE_RTP_NAME("16021639441"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), OR,
+		       MEDIA_VERSION_RANGE(1301, 2000)),
+	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
+			     GHWSP_CSB_REPORT_DIS |
+			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
+			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+	},
 
 	/* TGL */
 
@@ -505,20 +518,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
 	},
-	/*
-	 * These two workarounds are the same, just applying to different
-	 * engines.  Although Wa_18032095049 (for the RCS) isn't required on
-	 * all steppings, disabling these reports has no impact for our
-	 * driver or the GuC, so we go ahead and treat it the same as
-	 * Wa_16021639441 which does apply to all steppings.
-	 */
-	{ XE_RTP_NAME("18032095049, 16021639441"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004)),
-	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
-			     GHWSP_CSB_REPORT_DIS |
-			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
-			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
-	},
 	{ XE_RTP_NAME("16018610683"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
@@ -546,18 +545,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
 	},
-	/*
-	 * Although this workaround isn't required for the RCS, disabling these
-	 * reports has no impact for our driver or the GuC, so we go ahead and
-	 * apply this to all engines for simplicity.
-	 */
-	{ XE_RTP_NAME("16021639441"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002)),
-	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
-			     GHWSP_CSB_REPORT_DIS |
-			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
-			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
-	},
 	{ XE_RTP_NAME("14019811474"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(2001),
 		       FUNC(xe_rtp_match_first_render_or_compute)),
@@ -584,26 +571,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
 	},
 
-	/* Xe2_LPM */
-
-	{ XE_RTP_NAME("16021639441"),
-	  XE_RTP_RULES(MEDIA_VERSION(2000)),
-	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
-			     GHWSP_CSB_REPORT_DIS |
-			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
-			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
-	},
-
-	/* Xe2_HPM */
-
-	{ XE_RTP_NAME("16021639441"),
-	  XE_RTP_RULES(MEDIA_VERSION(1301)),
-	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
-			     GHWSP_CSB_REPORT_DIS |
-			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
-			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
-	},
-
 	/* Xe3_LPG */
 
 	{ XE_RTP_NAME("14021402888"),

-- 
2.53.0

[PATCH v2 13/23] drm/xe: Consolidate workaround entries for Wa_14021402888

[Matt Roper]

Wa_14021402888 applies to all graphics versions from 20.01 through 30.05
(inclusive).  Consolidate the RTP entries into a single range-based
entry.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 21 ++++-----------------
 1 file changed, 4 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index f0c42be062146837e6ba40621af54fcafa34f8e8..5d71cb9dca513803274ec1d5b766c2cbb0c31987 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -376,6 +376,10 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
 			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 	},
+	{ XE_RTP_NAME("14021402888"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3005), ENGINE_CLASS(RENDER)),
+	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
+	},
 
 	/* TGL */
 
@@ -522,10 +526,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
 	},
-	{ XE_RTP_NAME("14021402888"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
-	},
 	{ XE_RTP_NAME("13012615864"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
 		       FUNC(xe_rtp_match_first_render_or_compute)),
@@ -550,10 +550,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
 	},
-	{ XE_RTP_NAME("14021402888"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
-	},
 	{ XE_RTP_NAME("14021821874, 14022954250"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
 		       FUNC(xe_rtp_match_first_render_or_compute)),
@@ -573,11 +569,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 
 	/* Xe3_LPG */
 
-	{ XE_RTP_NAME("14021402888"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
-	},
 	{ XE_RTP_NAME("18034896535"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
 		       FUNC(xe_rtp_match_first_render_or_compute)),
@@ -608,10 +599,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE,
 			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 	},
-	{ XE_RTP_NAME("14021402888"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3003, 3005), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
-	},
 	{ XE_RTP_NAME("18041344222"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(3000),
 		       FUNC(xe_rtp_match_first_render_or_compute),

-- 
2.53.0

[PATCH v2 14/23] drm/xe: Consolidate workaround entries for Wa_13012615864

[Matt Roper]

Wa_13012615864 applies to all graphics versions from 20.01 through 30.05
(inclusive).  Consolidate the RTP entries into a single range-based
entry.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 21 +++++----------------
 1 file changed, 5 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 5d71cb9dca513803274ec1d5b766c2cbb0c31987..190b31a9d49d33e7fb80174be7ba9cbf726a8224 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -380,6 +380,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3005), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
 	},
+	{ XE_RTP_NAME("13012615864"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3005),
+		       FUNC(xe_rtp_match_first_render_or_compute)),
+	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
+	},
 
 	/* TGL */
 
@@ -526,11 +531,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
 	},
-	{ XE_RTP_NAME("13012615864"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
-	},
 	{ XE_RTP_NAME("18041344222"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
 		       FUNC(xe_rtp_match_first_render_or_compute),
@@ -555,11 +555,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
 	},
-	{ XE_RTP_NAME("13012615864"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
-	},
 	{ XE_RTP_NAME("18041344222"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
 		       FUNC(xe_rtp_match_first_render_or_compute),
@@ -587,12 +582,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE))
 	},
-	{ XE_RTP_NAME("13012615864"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), OR,
-		       GRAPHICS_VERSION_RANGE(3003, 3005),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
-	},
 	{ XE_RTP_NAME("16023105232"),
 	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR,
 		       GRAPHICS_VERSION_RANGE(2001, 3001)),

-- 
2.53.0

[PATCH v2 15/23] drm/xe: Consolidate workaround entries for Wa_18041344222

[Matt Roper]

Wa_18041344222 applies to all graphics versions from 20.01 through 30.00
(inclusive).  Consolidate the RTP entries into a single range-based
entry.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 25 +++++++------------------
 1 file changed, 7 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 190b31a9d49d33e7fb80174be7ba9cbf726a8224..83318a4ebcb51e004497e2cb9460e95691b5d9ff 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -385,6 +385,13 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
 	},
+	{ XE_RTP_NAME("18041344222"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3000),
+		       FUNC(xe_rtp_match_first_render_or_compute),
+		       FUNC(xe_rtp_match_not_sriov_vf),
+		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
+	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
+	},
 
 	/* TGL */
 
@@ -531,12 +538,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
 	},
-	{ XE_RTP_NAME("18041344222"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
-		       FUNC(xe_rtp_match_first_render_or_compute),
-		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
-	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
-	},
 
 	/* Xe2_HPG */
 
@@ -555,12 +556,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
 	},
-	{ XE_RTP_NAME("18041344222"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
-		       FUNC(xe_rtp_match_first_render_or_compute),
-		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
-	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
-	},
 
 	/* Xe3_LPG */
 
@@ -588,12 +583,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE,
 			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 	},
-	{ XE_RTP_NAME("18041344222"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(3000),
-		       FUNC(xe_rtp_match_first_render_or_compute),
-		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
-	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
-	},
 
 	/* Xe3p_LPG*/
 

-- 
2.53.0

[PATCH v2 16/23] drm/xe: Consolidate workaround entries for Wa_14019877138

[Matt Roper]

Wa_14019877138 applies to all graphics versions from 12.55 through 20.04
(inclusive) that have a render engine.  Consolidate the RTP entries into
a single range-based entry.

Note that the DG2 entry for this workaround was missing an
ENGINE_CLASS(RENDER) rule; that mistake is fixed by this consolidation.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 20 ++++----------------
 1 file changed, 4 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 83318a4ebcb51e004497e2cb9460e95691b5d9ff..21af997447e78951dd6d40c87454e8ef69343006 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -637,6 +637,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION(1200)),
 	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
 	},
+	{ XE_RTP_NAME("14019877138"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, 2004), ENGINE_CLASS(RENDER)),
+	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
+	},
 
 	/* DG1 */
 
@@ -673,10 +677,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 	  XE_RTP_RULES(PLATFORM(DG2)),
 	  XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
 	},
-	{ XE_RTP_NAME("14019877138"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
-	},
 
 	/* PVC */
 
@@ -694,10 +694,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
 	  XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
 	},
-	{ XE_RTP_NAME("14019877138"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
-	},
 
 	/* Xe2_LPG */
 
@@ -705,10 +701,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
 	},
-	{ XE_RTP_NAME("14019877138"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
-	},
 	{ XE_RTP_NAME("14019988906"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
@@ -758,10 +750,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
 	},
-	{ XE_RTP_NAME("14019877138"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
-	},
 	{ XE_RTP_NAME("14021490052"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(FF_MODE,

-- 
2.53.0

[PATCH v2 17/23] drm/xe: Consolidate workaround entries for Wa_14019386621

[Matt Roper]

Wa_14019386621 applies to all graphics versions from 20.01 through 20.04
(inclusive).  Consolidate the RTP entries into a single range-based entry.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 21af997447e78951dd6d40c87454e8ef69343006..03bef11370ae589d1035cf2cb7b022fd173d37b5 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -641,6 +641,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, 2004), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
 	},
+	{ XE_RTP_NAME("14019386621"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
+	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
+	},
 
 	/* DG1 */
 
@@ -697,10 +701,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 
 	/* Xe2_LPG */
 
-	{ XE_RTP_NAME("14019386621"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
-	},
 	{ XE_RTP_NAME("14019988906"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
@@ -738,10 +738,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN))
 	},
-	{ XE_RTP_NAME("14019386621"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
-	},
 	{ XE_RTP_NAME("14020756599"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))

-- 
2.53.0

[PATCH v2 18/23] drm/xe: Consolidate workaround entries for Wa_14019988906

[Matt Roper]

Wa_14019988906 applies to all graphics versions from 20.01 through 20.04
(inclusive).  Consolidate the RTP entries into a single range-based entry.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 03bef11370ae589d1035cf2cb7b022fd173d37b5..0a0f94ef5c68c2e583f28ab48eb4f96b2896b665 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -645,6 +645,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
 	},
+	{ XE_RTP_NAME("14019988906"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
+	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
+	},
 
 	/* DG1 */
 
@@ -701,10 +705,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 
 	/* Xe2_LPG */
 
-	{ XE_RTP_NAME("14019988906"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
-	},
 	{ XE_RTP_NAME("18033852989"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
@@ -742,10 +742,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
 	},
-	{ XE_RTP_NAME("14019988906"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
-	},
 	{ XE_RTP_NAME("14021490052"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(FF_MODE,

-- 
2.53.0

[PATCH v2 19/23] drm/xe: Consolidate workaround entries for Wa_18033852989

[Matt Roper]

Wa_18033852989 applies to all graphics versions from 20.01 through 20.04
(inclusive).  Consolidate the RTP entries into a single range-based entry.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 0a0f94ef5c68c2e583f28ab48eb4f96b2896b665..5aa404c0cbfbc8d11c93d820b1a192ab4776def8 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -649,6 +649,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
 	},
+	{ XE_RTP_NAME("18033852989"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
+	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
+	},
 
 	/* DG1 */
 
@@ -705,10 +709,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 
 	/* Xe2_LPG */
 
-	{ XE_RTP_NAME("18033852989"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
-	},
 	{ XE_RTP_NAME("14021567978"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
 		       ENGINE_CLASS(RENDER)),
@@ -759,10 +759,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
 	},
-	{ XE_RTP_NAME("18033852989"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
-	},
 
 	/* Xe3_LPG */
 	{ XE_RTP_NAME("14021490052"),

-- 
2.53.0

[PATCH v2 20/23] drm/xe: Consolidate workaround entries for Wa_15016589081

[Matt Roper]

Wa_15016589081 applies to all graphics versions from 20.01 through 20.04
(inclusive).  Consolidate the RTP entries into a single range-based entry.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 5aa404c0cbfbc8d11c93d820b1a192ab4776def8..fa5dce4ead48bae424a49c62142683dbf1971376 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -653,6 +653,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
 	},
+	{ XE_RTP_NAME("15016589081"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
+	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
+	},
 
 	/* DG1 */
 
@@ -728,10 +732,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 			     DIS_PARTIAL_AUTOSTRIP |
 			     DIS_AUTOSTRIP))
 	},
-	{ XE_RTP_NAME("15016589081"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
-	},
 
 	/* Xe2_HPG */
 	{ XE_RTP_NAME("15010599737"),
@@ -751,10 +751,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 			     DIS_PARTIAL_AUTOSTRIP |
 			     DIS_AUTOSTRIP))
 	},
-	{ XE_RTP_NAME("15016589081"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
-	},
 	{ XE_RTP_NAME("22021007897"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))

-- 
2.53.0

[PATCH v2 21/23] drm/xe/xe2_hpg: Drop invalid workaround Wa_15010599737

[Matt Roper]

Wa_15010599737 was a workaround originally proposed (and ultimately
rejected) for DG2-G10.  There's no record of it ever being relevant or
even considered for any other platforms.

The specific bit this workaround was setting is documented as "This bit
should be set to 1 for the DX9 API and 0 for all other APIs" which means
that it should almost always be left at the default value of 0 on Linux.
The register itself is directly accessible from userspace, so in the
special cases where it might be relevant (e.g., Wine/Proton running
Windows DX9 apps), the userspace drivers already have the ability to
change the setting without involvement of the kernel.

Fixes: 7f3ee7d88058 ("drm/xe/xe2hpg: Add initial GT workarounds")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index fa5dce4ead48bae424a49c62142683dbf1971376..105ccd8115f09993b7ef82e70cb87d74008f267f 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -734,10 +734,7 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 	},
 
 	/* Xe2_HPG */
-	{ XE_RTP_NAME("15010599737"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN))
-	},
+
 	{ XE_RTP_NAME("14020756599"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))

-- 
2.53.0

[PATCH v2 22/23] drm/xe/wa_oob: Consolidate some OOB rules

[Matt Roper]

Given the new policy of allowing graphics/media IP ranges to extend over
unused IP versions, we can consolidate some of the OOB workaround rules
and simplify the table.  If new IP variants eventually show up that use
these unused versions (e.g., media version 30.01, graphics versions
20.03 / 30.02, etc.), and if an existing workaround does not extend to
that new intermediate version, the ranges will be split back apart as
part of the enablement work for that new IP version.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa_oob.rules | 31 ++++++++-----------------------
 1 file changed, 8 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index c3222d9504889b5175fdfa73db0bf4e9910a277d..80b54b195f20c372a6816ce988b5e7e0b75270c2 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -24,18 +24,9 @@
 		MEDIA_VERSION(2000)
 16022287689	GRAPHICS_VERSION(2001)
 		GRAPHICS_VERSION(2004)
-13011645652	GRAPHICS_VERSION(2004)
-		GRAPHICS_VERSION_RANGE(3000, 3001)
-		GRAPHICS_VERSION(3003)
-		GRAPHICS_VERSION_RANGE(3004, 3005)
-14022293748	GRAPHICS_VERSION_RANGE(2001, 2002)
-		GRAPHICS_VERSION(2004)
-		GRAPHICS_VERSION_RANGE(3000, 3005)
-22019794406	GRAPHICS_VERSION_RANGE(2001, 2002)
-		GRAPHICS_VERSION(2004)
-		GRAPHICS_VERSION_RANGE(3000, 3001)
-		GRAPHICS_VERSION(3003)
-		GRAPHICS_VERSION_RANGE(3004, 3005)
+13011645652	GRAPHICS_VERSION_RANGE(2004, 3005)
+14022293748	GRAPHICS_VERSION_RANGE(2001, 3005)
+22019794406	GRAPHICS_VERSION_RANGE(2001, 3005)
 22019338487	MEDIA_VERSION(2000)
 		GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_not_sriov_vf)
 		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), FUNC(xe_rtp_match_not_sriov_vf)
@@ -52,18 +43,12 @@
 18013179988	GRAPHICS_VERSION(1255)
 		GRAPHICS_VERSION_RANGE(1270, 1274)
 1508761755	GRAPHICS_VERSION(1255)
-16023105232	GRAPHICS_VERSION_RANGE(2001, 3001)
-		MEDIA_VERSION_RANGE(1301, 3000)
-		MEDIA_VERSION(3002)
-		GRAPHICS_VERSION_RANGE(3003, 3005)
-16026508708	GRAPHICS_VERSION_RANGE(1200, 3001)
-		MEDIA_VERSION_RANGE(1300, 3000)
-		MEDIA_VERSION(3002)
-		GRAPHICS_VERSION_RANGE(3003, 3005)
+16023105232	GRAPHICS_VERSION_RANGE(2001, 3005)
+		MEDIA_VERSION_RANGE(1301, 3002)
+16026508708	GRAPHICS_VERSION_RANGE(1200, 3005)
+		MEDIA_VERSION_RANGE(1300, 3002)
 14020001231	GRAPHICS_VERSION_RANGE(2001,2004), FUNC(xe_rtp_match_psmi_enabled)
-		MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled)
-		MEDIA_VERSION(3000), FUNC(xe_rtp_match_psmi_enabled)
-		MEDIA_VERSION(3002), FUNC(xe_rtp_match_psmi_enabled)
+		MEDIA_VERSION_RANGE(2000, 3002), FUNC(xe_rtp_match_psmi_enabled)
 16023683509	MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled)
 		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), FUNC(xe_rtp_match_psmi_enabled)
 

-- 
2.53.0

[PATCH v2 23/23] drm/xe: Consolidate workaround entries for Wa_14023061436

[Matt Roper]

Wa_14023061436 applies to all graphics versions from 30.00 through 30.05
(inclusive) since there is currently no IP that uses version 30.02.
Consolidate the RTP rules into a single range.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 105ccd8115f09993b7ef82e70cb87d74008f267f..6bee245286abb674cc3089257c979e37ea51760b 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -571,9 +571,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 				   SMP_FORCE_128B_OVERFETCH))
 	},
 	{ XE_RTP_NAME("14023061436"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
-		       FUNC(xe_rtp_match_first_render_or_compute), OR,
-		       GRAPHICS_VERSION_RANGE(3003, 3005),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005),
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE))
 	},

-- 
2.53.0

✓ CI.KUnit: success for Workaround cleanup & simplification (rev2)

[Patchwork]

== Series Details ==

Series: Workaround cleanup & simplification (rev2)
URL   : https://patchwork.freedesktop.org/series/161606/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[19:04:28] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:04:32] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:05:04] Starting KUnit Kernel (1/1)...
[19:05:04] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:05:04] ================== guc_buf (11 subtests) ===================
[19:05:04] [PASSED] test_smallest
[19:05:04] [PASSED] test_largest
[19:05:04] [PASSED] test_granular
[19:05:04] [PASSED] test_unique
[19:05:04] [PASSED] test_overlap
[19:05:04] [PASSED] test_reusable
[19:05:04] [PASSED] test_too_big
[19:05:04] [PASSED] test_flush
[19:05:04] [PASSED] test_lookup
[19:05:04] [PASSED] test_data
[19:05:04] [PASSED] test_class
[19:05:04] ===================== [PASSED] guc_buf =====================
[19:05:04] =================== guc_dbm (7 subtests) ===================
[19:05:04] [PASSED] test_empty
[19:05:04] [PASSED] test_default
[19:05:04] ======================== test_size  ========================
[19:05:04] [PASSED] 4
[19:05:04] [PASSED] 8
[19:05:04] [PASSED] 32
[19:05:04] [PASSED] 256
[19:05:04] ==================== [PASSED] test_size ====================
[19:05:04] ======================= test_reuse  ========================
[19:05:04] [PASSED] 4
[19:05:04] [PASSED] 8
[19:05:04] [PASSED] 32
[19:05:04] [PASSED] 256
[19:05:04] =================== [PASSED] test_reuse ====================
[19:05:04] =================== test_range_overlap  ====================
[19:05:04] [PASSED] 4
[19:05:04] [PASSED] 8
[19:05:04] [PASSED] 32
[19:05:04] [PASSED] 256
[19:05:04] =============== [PASSED] test_range_overlap ================
[19:05:04] =================== test_range_compact  ====================
[19:05:04] [PASSED] 4
[19:05:04] [PASSED] 8
[19:05:04] [PASSED] 32
[19:05:04] [PASSED] 256
[19:05:04] =============== [PASSED] test_range_compact ================
[19:05:04] ==================== test_range_spare  =====================
[19:05:04] [PASSED] 4
[19:05:04] [PASSED] 8
[19:05:04] [PASSED] 32
[19:05:04] [PASSED] 256
[19:05:04] ================ [PASSED] test_range_spare =================
[19:05:04] ===================== [PASSED] guc_dbm =====================
[19:05:04] =================== guc_idm (6 subtests) ===================
[19:05:04] [PASSED] bad_init
[19:05:04] [PASSED] no_init
[19:05:04] [PASSED] init_fini
[19:05:04] [PASSED] check_used
[19:05:04] [PASSED] check_quota
[19:05:04] [PASSED] check_all
[19:05:04] ===================== [PASSED] guc_idm =====================
[19:05:04] ================== no_relay (3 subtests) ===================
[19:05:04] [PASSED] xe_drops_guc2pf_if_not_ready
[19:05:04] [PASSED] xe_drops_guc2vf_if_not_ready
[19:05:04] [PASSED] xe_rejects_send_if_not_ready
[19:05:04] ==================== [PASSED] no_relay =====================
[19:05:04] ================== pf_relay (14 subtests) ==================
[19:05:04] [PASSED] pf_rejects_guc2pf_too_short
[19:05:04] [PASSED] pf_rejects_guc2pf_too_long
[19:05:04] [PASSED] pf_rejects_guc2pf_no_payload
[19:05:04] [PASSED] pf_fails_no_payload
[19:05:04] [PASSED] pf_fails_bad_origin
[19:05:04] [PASSED] pf_fails_bad_type
[19:05:04] [PASSED] pf_txn_reports_error
[19:05:04] [PASSED] pf_txn_sends_pf2guc
[19:05:04] [PASSED] pf_sends_pf2guc
[19:05:04] [SKIPPED] pf_loopback_nop
[19:05:04] [SKIPPED] pf_loopback_echo
[19:05:04] [SKIPPED] pf_loopback_fail
[19:05:04] [SKIPPED] pf_loopback_busy
[19:05:04] [SKIPPED] pf_loopback_retry
[19:05:04] ==================== [PASSED] pf_relay =====================
[19:05:04] ================== vf_relay (3 subtests) ===================
[19:05:04] [PASSED] vf_rejects_guc2vf_too_short
[19:05:04] [PASSED] vf_rejects_guc2vf_too_long
[19:05:04] [PASSED] vf_rejects_guc2vf_no_payload
[19:05:04] ==================== [PASSED] vf_relay =====================
[19:05:04] ================ pf_gt_config (9 subtests) =================
[19:05:04] [PASSED] fair_contexts_1vf
[19:05:04] [PASSED] fair_doorbells_1vf
[19:05:04] [PASSED] fair_ggtt_1vf
[19:05:04] ====================== fair_vram_1vf  ======================
[19:05:04] [PASSED] 3.50 GiB
[19:05:04] [PASSED] 11.5 GiB
[19:05:04] [PASSED] 15.5 GiB
[19:05:04] [PASSED] 31.5 GiB
[19:05:04] [PASSED] 63.5 GiB
[19:05:04] [PASSED] 13.9 GiB
[19:05:04] ================== [PASSED] fair_vram_1vf ==================
[19:05:04] ================ fair_vram_1vf_admin_only  =================
[19:05:04] [PASSED] 3.50 GiB
[19:05:04] [PASSED] 11.5 GiB
[19:05:04] [PASSED] 15.5 GiB
[19:05:04] [PASSED] 31.5 GiB
[19:05:04] [PASSED] 63.5 GiB
[19:05:04] [PASSED] 13.9 GiB
[19:05:04] ============ [PASSED] fair_vram_1vf_admin_only =============
[19:05:04] ====================== fair_contexts  ======================
[19:05:04] [PASSED] 1 VF
[19:05:04] [PASSED] 2 VFs
[19:05:04] [PASSED] 3 VFs
[19:05:04] [PASSED] 4 VFs
[19:05:04] [PASSED] 5 VFs
[19:05:04] [PASSED] 6 VFs
[19:05:04] [PASSED] 7 VFs
[19:05:04] [PASSED] 8 VFs
[19:05:04] [PASSED] 9 VFs
[19:05:04] [PASSED] 10 VFs
[19:05:04] [PASSED] 11 VFs
[19:05:04] [PASSED] 12 VFs
[19:05:04] [PASSED] 13 VFs
[19:05:04] [PASSED] 14 VFs
[19:05:04] [PASSED] 15 VFs
[19:05:04] [PASSED] 16 VFs
[19:05:04] [PASSED] 17 VFs
[19:05:04] [PASSED] 18 VFs
[19:05:04] [PASSED] 19 VFs
[19:05:04] [PASSED] 20 VFs
[19:05:04] [PASSED] 21 VFs
[19:05:04] [PASSED] 22 VFs
[19:05:04] [PASSED] 23 VFs
[19:05:04] [PASSED] 24 VFs
[19:05:04] [PASSED] 25 VFs
[19:05:04] [PASSED] 26 VFs
[19:05:04] [PASSED] 27 VFs
[19:05:04] [PASSED] 28 VFs
[19:05:04] [PASSED] 29 VFs
[19:05:04] [PASSED] 30 VFs
[19:05:04] [PASSED] 31 VFs
[19:05:04] [PASSED] 32 VFs
[19:05:04] [PASSED] 33 VFs
[19:05:04] [PASSED] 34 VFs
[19:05:04] [PASSED] 35 VFs
[19:05:04] [PASSED] 36 VFs
[19:05:04] [PASSED] 37 VFs
[19:05:04] [PASSED] 38 VFs
[19:05:04] [PASSED] 39 VFs
[19:05:04] [PASSED] 40 VFs
[19:05:04] [PASSED] 41 VFs
[19:05:04] [PASSED] 42 VFs
[19:05:04] [PASSED] 43 VFs
[19:05:04] [PASSED] 44 VFs
[19:05:04] [PASSED] 45 VFs
[19:05:04] [PASSED] 46 VFs
[19:05:04] [PASSED] 47 VFs
[19:05:04] [PASSED] 48 VFs
[19:05:04] [PASSED] 49 VFs
[19:05:04] [PASSED] 50 VFs
[19:05:04] [PASSED] 51 VFs
[19:05:04] [PASSED] 52 VFs
[19:05:04] [PASSED] 53 VFs
[19:05:04] [PASSED] 54 VFs
[19:05:04] [PASSED] 55 VFs
[19:05:04] [PASSED] 56 VFs
[19:05:04] [PASSED] 57 VFs
[19:05:04] [PASSED] 58 VFs
[19:05:04] [PASSED] 59 VFs
[19:05:04] [PASSED] 60 VFs
[19:05:04] [PASSED] 61 VFs
[19:05:04] [PASSED] 62 VFs
[19:05:04] [PASSED] 63 VFs
[19:05:04] ================== [PASSED] fair_contexts ==================
[19:05:04] ===================== fair_doorbells  ======================
[19:05:04] [PASSED] 1 VF
[19:05:04] [PASSED] 2 VFs
[19:05:04] [PASSED] 3 VFs
[19:05:04] [PASSED] 4 VFs
[19:05:04] [PASSED] 5 VFs
[19:05:04] [PASSED] 6 VFs
[19:05:04] [PASSED] 7 VFs
[19:05:04] [PASSED] 8 VFs
[19:05:04] [PASSED] 9 VFs
[19:05:04] [PASSED] 10 VFs
[19:05:04] [PASSED] 11 VFs
[19:05:04] [PASSED] 12 VFs
[19:05:04] [PASSED] 13 VFs
[19:05:04] [PASSED] 14 VFs
[19:05:04] [PASSED] 15 VFs
[19:05:04] [PASSED] 16 VFs
[19:05:04] [PASSED] 17 VFs
[19:05:04] [PASSED] 18 VFs
[19:05:04] [PASSED] 19 VFs
[19:05:04] [PASSED] 20 VFs
[19:05:04] [PASSED] 21 VFs
[19:05:04] [PASSED] 22 VFs
[19:05:04] [PASSED] 23 VFs
[19:05:04] [PASSED] 24 VFs
[19:05:04] [PASSED] 25 VFs
[19:05:04] [PASSED] 26 VFs
[19:05:04] [PASSED] 27 VFs
[19:05:04] [PASSED] 28 VFs
[19:05:04] [PASSED] 29 VFs
[19:05:04] [PASSED] 30 VFs
[19:05:04] [PASSED] 31 VFs
[19:05:04] [PASSED] 32 VFs
[19:05:04] [PASSED] 33 VFs
[19:05:04] [PASSED] 34 VFs
[19:05:04] [PASSED] 35 VFs
[19:05:04] [PASSED] 36 VFs
[19:05:04] [PASSED] 37 VFs
[19:05:04] [PASSED] 38 VFs
[19:05:04] [PASSED] 39 VFs
[19:05:04] [PASSED] 40 VFs
[19:05:04] [PASSED] 41 VFs
[19:05:04] [PASSED] 42 VFs
[19:05:04] [PASSED] 43 VFs
[19:05:04] [PASSED] 44 VFs
[19:05:04] [PASSED] 45 VFs
[19:05:04] [PASSED] 46 VFs
[19:05:04] [PASSED] 47 VFs
[19:05:04] [PASSED] 48 VFs
[19:05:04] [PASSED] 49 VFs
[19:05:04] [PASSED] 50 VFs
[19:05:04] [PASSED] 51 VFs
[19:05:04] [PASSED] 52 VFs
[19:05:04] [PASSED] 53 VFs
[19:05:04] [PASSED] 54 VFs
[19:05:04] [PASSED] 55 VFs
[19:05:04] [PASSED] 56 VFs
[19:05:04] [PASSED] 57 VFs
[19:05:04] [PASSED] 58 VFs
[19:05:04] [PASSED] 59 VFs
[19:05:04] [PASSED] 60 VFs
[19:05:04] [PASSED] 61 VFs
[19:05:04] [PASSED] 62 VFs
[19:05:04] [PASSED] 63 VFs
[19:05:04] ================= [PASSED] fair_doorbells ==================
[19:05:04] ======================== fair_ggtt  ========================
[19:05:04] [PASSED] 1 VF
[19:05:04] [PASSED] 2 VFs
[19:05:04] [PASSED] 3 VFs
[19:05:04] [PASSED] 4 VFs
[19:05:04] [PASSED] 5 VFs
[19:05:04] [PASSED] 6 VFs
[19:05:04] [PASSED] 7 VFs
[19:05:04] [PASSED] 8 VFs
[19:05:05] [PASSED] 9 VFs
[19:05:05] [PASSED] 10 VFs
[19:05:05] [PASSED] 11 VFs
[19:05:05] [PASSED] 12 VFs
[19:05:05] [PASSED] 13 VFs
[19:05:05] [PASSED] 14 VFs
[19:05:05] [PASSED] 15 VFs
[19:05:05] [PASSED] 16 VFs
[19:05:05] [PASSED] 17 VFs
[19:05:05] [PASSED] 18 VFs
[19:05:05] [PASSED] 19 VFs
[19:05:05] [PASSED] 20 VFs
[19:05:05] [PASSED] 21 VFs
[19:05:05] [PASSED] 22 VFs
[19:05:05] [PASSED] 23 VFs
[19:05:05] [PASSED] 24 VFs
[19:05:05] [PASSED] 25 VFs
[19:05:05] [PASSED] 26 VFs
[19:05:05] [PASSED] 27 VFs
[19:05:05] [PASSED] 28 VFs
[19:05:05] [PASSED] 29 VFs
[19:05:05] [PASSED] 30 VFs
[19:05:05] [PASSED] 31 VFs
[19:05:05] [PASSED] 32 VFs
[19:05:05] [PASSED] 33 VFs
[19:05:05] [PASSED] 34 VFs
[19:05:05] [PASSED] 35 VFs
[19:05:05] [PASSED] 36 VFs
[19:05:05] [PASSED] 37 VFs
[19:05:05] [PASSED] 38 VFs
[19:05:05] [PASSED] 39 VFs
[19:05:05] [PASSED] 40 VFs
[19:05:05] [PASSED] 41 VFs
[19:05:05] [PASSED] 42 VFs
[19:05:05] [PASSED] 43 VFs
[19:05:05] [PASSED] 44 VFs
[19:05:05] [PASSED] 45 VFs
[19:05:05] [PASSED] 46 VFs
[19:05:05] [PASSED] 47 VFs
[19:05:05] [PASSED] 48 VFs
[19:05:05] [PASSED] 49 VFs
[19:05:05] [PASSED] 50 VFs
[19:05:05] [PASSED] 51 VFs
[19:05:05] [PASSED] 52 VFs
[19:05:05] [PASSED] 53 VFs
[19:05:05] [PASSED] 54 VFs
[19:05:05] [PASSED] 55 VFs
[19:05:05] [PASSED] 56 VFs
[19:05:05] [PASSED] 57 VFs
[19:05:05] [PASSED] 58 VFs
[19:05:05] [PASSED] 59 VFs
[19:05:05] [PASSED] 60 VFs
[19:05:05] [PASSED] 61 VFs
[19:05:05] [PASSED] 62 VFs
[19:05:05] [PASSED] 63 VFs
[19:05:05] ==================== [PASSED] fair_ggtt ====================
[19:05:05] ======================== fair_vram  ========================
[19:05:05] [PASSED] 1 VF
[19:05:05] [PASSED] 2 VFs
[19:05:05] [PASSED] 3 VFs
[19:05:05] [PASSED] 4 VFs
[19:05:05] [PASSED] 5 VFs
[19:05:05] [PASSED] 6 VFs
[19:05:05] [PASSED] 7 VFs
[19:05:05] [PASSED] 8 VFs
[19:05:05] [PASSED] 9 VFs
[19:05:05] [PASSED] 10 VFs
[19:05:05] [PASSED] 11 VFs
[19:05:05] [PASSED] 12 VFs
[19:05:05] [PASSED] 13 VFs
[19:05:05] [PASSED] 14 VFs
[19:05:05] [PASSED] 15 VFs
[19:05:05] [PASSED] 16 VFs
[19:05:05] [PASSED] 17 VFs
[19:05:05] [PASSED] 18 VFs
[19:05:05] [PASSED] 19 VFs
[19:05:05] [PASSED] 20 VFs
[19:05:05] [PASSED] 21 VFs
[19:05:05] [PASSED] 22 VFs
[19:05:05] [PASSED] 23 VFs
[19:05:05] [PASSED] 24 VFs
[19:05:05] [PASSED] 25 VFs
[19:05:05] [PASSED] 26 VFs
[19:05:05] [PASSED] 27 VFs
[19:05:05] [PASSED] 28 VFs
[19:05:05] [PASSED] 29 VFs
[19:05:05] [PASSED] 30 VFs
[19:05:05] [PASSED] 31 VFs
[19:05:05] [PASSED] 32 VFs
[19:05:05] [PASSED] 33 VFs
[19:05:05] [PASSED] 34 VFs
[19:05:05] [PASSED] 35 VFs
[19:05:05] [PASSED] 36 VFs
[19:05:05] [PASSED] 37 VFs
[19:05:05] [PASSED] 38 VFs
[19:05:05] [PASSED] 39 VFs
[19:05:05] [PASSED] 40 VFs
[19:05:05] [PASSED] 41 VFs
[19:05:05] [PASSED] 42 VFs
[19:05:05] [PASSED] 43 VFs
[19:05:05] [PASSED] 44 VFs
[19:05:05] [PASSED] 45 VFs
[19:05:05] [PASSED] 46 VFs
[19:05:05] [PASSED] 47 VFs
[19:05:05] [PASSED] 48 VFs
[19:05:05] [PASSED] 49 VFs
[19:05:05] [PASSED] 50 VFs
[19:05:05] [PASSED] 51 VFs
[19:05:05] [PASSED] 52 VFs
[19:05:05] [PASSED] 53 VFs
[19:05:05] [PASSED] 54 VFs
[19:05:05] [PASSED] 55 VFs
[19:05:05] [PASSED] 56 VFs
[19:05:05] [PASSED] 57 VFs
[19:05:05] [PASSED] 58 VFs
[19:05:05] [PASSED] 59 VFs
[19:05:05] [PASSED] 60 VFs
[19:05:05] [PASSED] 61 VFs
[19:05:05] [PASSED] 62 VFs
[19:05:05] [PASSED] 63 VFs
[19:05:05] ==================== [PASSED] fair_vram ====================
[19:05:05] ================== [PASSED] pf_gt_config ===================
[19:05:05] ===================== lmtt (1 subtest) =====================
[19:05:05] ======================== test_ops  =========================
[19:05:05] [PASSED] 2-level
[19:05:05] [PASSED] multi-level
[19:05:05] ==================== [PASSED] test_ops =====================
[19:05:05] ====================== [PASSED] lmtt =======================
[19:05:05] ================= pf_service (11 subtests) =================
[19:05:05] [PASSED] pf_negotiate_any
[19:05:05] [PASSED] pf_negotiate_base_match
[19:05:05] [PASSED] pf_negotiate_base_newer
[19:05:05] [PASSED] pf_negotiate_base_next
[19:05:05] [SKIPPED] pf_negotiate_base_older
[19:05:05] [PASSED] pf_negotiate_base_prev
[19:05:05] [PASSED] pf_negotiate_latest_match
[19:05:05] [PASSED] pf_negotiate_latest_newer
[19:05:05] [PASSED] pf_negotiate_latest_next
[19:05:05] [SKIPPED] pf_negotiate_latest_older
[19:05:05] [SKIPPED] pf_negotiate_latest_prev
[19:05:05] =================== [PASSED] pf_service ====================
[19:05:05] ================= xe_guc_g2g (2 subtests) ==================
[19:05:05] ============== xe_live_guc_g2g_kunit_default  ==============
[19:05:05] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[19:05:05] ============== xe_live_guc_g2g_kunit_allmem  ===============
[19:05:05] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[19:05:05] =================== [SKIPPED] xe_guc_g2g ===================
[19:05:05] =================== xe_mocs (2 subtests) ===================
[19:05:05] ================ xe_live_mocs_kernel_kunit  ================
[19:05:05] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[19:05:05] ================ xe_live_mocs_reset_kunit  =================
[19:05:05] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[19:05:05] ==================== [SKIPPED] xe_mocs =====================
[19:05:05] ================= xe_migrate (2 subtests) ==================
[19:05:05] ================= xe_migrate_sanity_kunit  =================
[19:05:05] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[19:05:05] ================== xe_validate_ccs_kunit  ==================
[19:05:05] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[19:05:05] =================== [SKIPPED] xe_migrate ===================
[19:05:05] ================== xe_dma_buf (1 subtest) ==================
[19:05:05] ==================== xe_dma_buf_kunit  =====================
[19:05:05] ================ [SKIPPED] xe_dma_buf_kunit ================
[19:05:05] =================== [SKIPPED] xe_dma_buf ===================
[19:05:05] ================= xe_bo_shrink (1 subtest) =================
[19:05:05] =================== xe_bo_shrink_kunit  ====================
[19:05:05] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[19:05:05] ================== [SKIPPED] xe_bo_shrink ==================
[19:05:05] ==================== xe_bo (2 subtests) ====================
[19:05:05] ================== xe_ccs_migrate_kunit  ===================
[19:05:05] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[19:05:05] ==================== xe_bo_evict_kunit  ====================
[19:05:05] =============== [SKIPPED] xe_bo_evict_kunit ================
[19:05:05] ===================== [SKIPPED] xe_bo ======================
[19:05:05] ==================== args (13 subtests) ====================
[19:05:05] [PASSED] count_args_test
[19:05:05] [PASSED] call_args_example
[19:05:05] [PASSED] call_args_test
[19:05:05] [PASSED] drop_first_arg_example
[19:05:05] [PASSED] drop_first_arg_test
[19:05:05] [PASSED] first_arg_example
[19:05:05] [PASSED] first_arg_test
[19:05:05] [PASSED] last_arg_example
[19:05:05] [PASSED] last_arg_test
[19:05:05] [PASSED] pick_arg_example
[19:05:05] [PASSED] if_args_example
[19:05:05] [PASSED] if_args_test
[19:05:05] [PASSED] sep_comma_example
[19:05:05] ====================== [PASSED] args =======================
[19:05:05] =================== xe_pci (3 subtests) ====================
[19:05:05] ==================== check_graphics_ip  ====================
[19:05:05] [PASSED] 12.00 Xe_LP
[19:05:05] [PASSED] 12.10 Xe_LP+
[19:05:05] [PASSED] 12.55 Xe_HPG
[19:05:05] [PASSED] 12.60 Xe_HPC
[19:05:05] [PASSED] 12.70 Xe_LPG
[19:05:05] [PASSED] 12.71 Xe_LPG
[19:05:05] [PASSED] 12.74 Xe_LPG+
[19:05:05] [PASSED] 20.01 Xe2_HPG
[19:05:05] [PASSED] 20.02 Xe2_HPG
[19:05:05] [PASSED] 20.04 Xe2_LPG
[19:05:05] [PASSED] 30.00 Xe3_LPG
[19:05:05] [PASSED] 30.01 Xe3_LPG
[19:05:05] [PASSED] 30.03 Xe3_LPG
[19:05:05] [PASSED] 30.04 Xe3_LPG
[19:05:05] [PASSED] 30.05 Xe3_LPG
[19:05:05] [PASSED] 35.10 Xe3p_LPG
[19:05:05] [PASSED] 35.11 Xe3p_XPC
[19:05:05] ================ [PASSED] check_graphics_ip ================
[19:05:05] ===================== check_media_ip  ======================
[19:05:05] [PASSED] 12.00 Xe_M
[19:05:05] [PASSED] 12.55 Xe_HPM
[19:05:05] [PASSED] 13.00 Xe_LPM+
[19:05:05] [PASSED] 13.01 Xe2_HPM
[19:05:05] [PASSED] 20.00 Xe2_LPM
[19:05:05] [PASSED] 30.00 Xe3_LPM
[19:05:05] [PASSED] 30.02 Xe3_LPM
[19:05:05] [PASSED] 35.00 Xe3p_LPM
[19:05:05] [PASSED] 35.03 Xe3p_HPM
[19:05:05] ================= [PASSED] check_media_ip ==================
[19:05:05] =================== check_platform_desc  ===================
[19:05:05] [PASSED] 0x9A60 (TIGERLAKE)
[19:05:05] [PASSED] 0x9A68 (TIGERLAKE)
[19:05:05] [PASSED] 0x9A70 (TIGERLAKE)
[19:05:05] [PASSED] 0x9A40 (TIGERLAKE)
[19:05:05] [PASSED] 0x9A49 (TIGERLAKE)
[19:05:05] [PASSED] 0x9A59 (TIGERLAKE)
[19:05:05] [PASSED] 0x9A78 (TIGERLAKE)
[19:05:05] [PASSED] 0x9AC0 (TIGERLAKE)
[19:05:05] [PASSED] 0x9AC9 (TIGERLAKE)
[19:05:05] [PASSED] 0x9AD9 (TIGERLAKE)
[19:05:05] [PASSED] 0x9AF8 (TIGERLAKE)
[19:05:05] [PASSED] 0x4C80 (ROCKETLAKE)
[19:05:05] [PASSED] 0x4C8A (ROCKETLAKE)
[19:05:05] [PASSED] 0x4C8B (ROCKETLAKE)
[19:05:05] [PASSED] 0x4C8C (ROCKETLAKE)
[19:05:05] [PASSED] 0x4C90 (ROCKETLAKE)
[19:05:05] [PASSED] 0x4C9A (ROCKETLAKE)
[19:05:05] [PASSED] 0x4680 (ALDERLAKE_S)
[19:05:05] [PASSED] 0x4682 (ALDERLAKE_S)
[19:05:05] [PASSED] 0x4688 (ALDERLAKE_S)
[19:05:05] [PASSED] 0x468A (ALDERLAKE_S)
[19:05:05] [PASSED] 0x468B (ALDERLAKE_S)
[19:05:05] [PASSED] 0x4690 (ALDERLAKE_S)
[19:05:05] [PASSED] 0x4692 (ALDERLAKE_S)
[19:05:05] [PASSED] 0x4693 (ALDERLAKE_S)
[19:05:05] [PASSED] 0x46A0 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x46A1 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x46A2 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x46A3 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x46A6 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x46A8 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x46AA (ALDERLAKE_P)
[19:05:05] [PASSED] 0x462A (ALDERLAKE_P)
[19:05:05] [PASSED] 0x4626 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x4628 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x46B0 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x46B1 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x46B2 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x46B3 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x46C0 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x46C1 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x46C2 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x46C3 (ALDERLAKE_P)
[19:05:05] [PASSED] 0x46D0 (ALDERLAKE_N)
[19:05:05] [PASSED] 0x46D1 (ALDERLAKE_N)
[19:05:05] [PASSED] 0x46D2 (ALDERLAKE_N)
[19:05:05] [PASSED] 0x46D3 (ALDERLAKE_N)
[19:05:05] [PASSED] 0x46D4 (ALDERLAKE_N)
[19:05:05] [PASSED] 0xA721 (ALDERLAKE_P)
[19:05:05] [PASSED] 0xA7A1 (ALDERLAKE_P)
[19:05:05] [PASSED] 0xA7A9 (ALDERLAKE_P)
[19:05:05] [PASSED] 0xA7AC (ALDERLAKE_P)
[19:05:05] [PASSED] 0xA7AD (ALDERLAKE_P)
[19:05:05] [PASSED] 0xA720 (ALDERLAKE_P)
[19:05:05] [PASSED] 0xA7A0 (ALDERLAKE_P)
[19:05:05] [PASSED] 0xA7A8 (ALDERLAKE_P)
[19:05:05] [PASSED] 0xA7AA (ALDERLAKE_P)
[19:05:05] [PASSED] 0xA7AB (ALDERLAKE_P)
[19:05:05] [PASSED] 0xA780 (ALDERLAKE_S)
[19:05:05] [PASSED] 0xA781 (ALDERLAKE_S)
[19:05:05] [PASSED] 0xA782 (ALDERLAKE_S)
[19:05:05] [PASSED] 0xA783 (ALDERLAKE_S)
[19:05:05] [PASSED] 0xA788 (ALDERLAKE_S)
[19:05:05] [PASSED] 0xA789 (ALDERLAKE_S)
[19:05:05] [PASSED] 0xA78A (ALDERLAKE_S)
[19:05:05] [PASSED] 0xA78B (ALDERLAKE_S)
[19:05:05] [PASSED] 0x4905 (DG1)
[19:05:05] [PASSED] 0x4906 (DG1)
[19:05:05] [PASSED] 0x4907 (DG1)
[19:05:05] [PASSED] 0x4908 (DG1)
[19:05:05] [PASSED] 0x4909 (DG1)
[19:05:05] [PASSED] 0x56C0 (DG2)
[19:05:05] [PASSED] 0x56C2 (DG2)
[19:05:05] [PASSED] 0x56C1 (DG2)
[19:05:05] [PASSED] 0x7D51 (METEORLAKE)
[19:05:05] [PASSED] 0x7DD1 (METEORLAKE)
[19:05:05] [PASSED] 0x7D41 (METEORLAKE)
[19:05:05] [PASSED] 0x7D67 (METEORLAKE)
[19:05:05] [PASSED] 0xB640 (METEORLAKE)
[19:05:05] [PASSED] 0x56A0 (DG2)
[19:05:05] [PASSED] 0x56A1 (DG2)
[19:05:05] [PASSED] 0x56A2 (DG2)
[19:05:05] [PASSED] 0x56BE (DG2)
[19:05:05] [PASSED] 0x56BF (DG2)
[19:05:05] [PASSED] 0x5690 (DG2)
[19:05:05] [PASSED] 0x5691 (DG2)
[19:05:05] [PASSED] 0x5692 (DG2)
[19:05:05] [PASSED] 0x56A5 (DG2)
[19:05:05] [PASSED] 0x56A6 (DG2)
[19:05:05] [PASSED] 0x56B0 (DG2)
[19:05:05] [PASSED] 0x56B1 (DG2)
[19:05:05] [PASSED] 0x56BA (DG2)
[19:05:05] [PASSED] 0x56BB (DG2)
[19:05:05] [PASSED] 0x56BC (DG2)
[19:05:05] [PASSED] 0x56BD (DG2)
[19:05:05] [PASSED] 0x5693 (DG2)
[19:05:05] [PASSED] 0x5694 (DG2)
[19:05:05] [PASSED] 0x5695 (DG2)
[19:05:05] [PASSED] 0x56A3 (DG2)
[19:05:05] [PASSED] 0x56A4 (DG2)
[19:05:05] [PASSED] 0x56B2 (DG2)
[19:05:05] [PASSED] 0x56B3 (DG2)
[19:05:05] [PASSED] 0x5696 (DG2)
[19:05:05] [PASSED] 0x5697 (DG2)
[19:05:05] [PASSED] 0xB69 (PVC)
[19:05:05] [PASSED] 0xB6E (PVC)
[19:05:05] [PASSED] 0xBD4 (PVC)
[19:05:05] [PASSED] 0xBD5 (PVC)
[19:05:05] [PASSED] 0xBD6 (PVC)
[19:05:05] [PASSED] 0xBD7 (PVC)
[19:05:05] [PASSED] 0xBD8 (PVC)
[19:05:05] [PASSED] 0xBD9 (PVC)
[19:05:05] [PASSED] 0xBDA (PVC)
[19:05:05] [PASSED] 0xBDB (PVC)
[19:05:05] [PASSED] 0xBE0 (PVC)
[19:05:05] [PASSED] 0xBE1 (PVC)
[19:05:05] [PASSED] 0xBE5 (PVC)
[19:05:05] [PASSED] 0x7D40 (METEORLAKE)
[19:05:05] [PASSED] 0x7D45 (METEORLAKE)
[19:05:05] [PASSED] 0x7D55 (METEORLAKE)
[19:05:05] [PASSED] 0x7D60 (METEORLAKE)
[19:05:05] [PASSED] 0x7DD5 (METEORLAKE)
[19:05:05] [PASSED] 0x6420 (LUNARLAKE)
[19:05:05] [PASSED] 0x64A0 (LUNARLAKE)
[19:05:05] [PASSED] 0x64B0 (LUNARLAKE)
[19:05:05] [PASSED] 0xE202 (BATTLEMAGE)
[19:05:05] [PASSED] 0xE209 (BATTLEMAGE)
[19:05:05] [PASSED] 0xE20B (BATTLEMAGE)
[19:05:05] [PASSED] 0xE20C (BATTLEMAGE)
[19:05:05] [PASSED] 0xE20D (BATTLEMAGE)
[19:05:05] [PASSED] 0xE210 (BATTLEMAGE)
[19:05:05] [PASSED] 0xE211 (BATTLEMAGE)
[19:05:05] [PASSED] 0xE212 (BATTLEMAGE)
[19:05:05] [PASSED] 0xE216 (BATTLEMAGE)
[19:05:05] [PASSED] 0xE220 (BATTLEMAGE)
[19:05:05] [PASSED] 0xE221 (BATTLEMAGE)
[19:05:05] [PASSED] 0xE222 (BATTLEMAGE)
[19:05:05] [PASSED] 0xE223 (BATTLEMAGE)
[19:05:05] [PASSED] 0xB080 (PANTHERLAKE)
[19:05:05] [PASSED] 0xB081 (PANTHERLAKE)
[19:05:05] [PASSED] 0xB082 (PANTHERLAKE)
[19:05:05] [PASSED] 0xB083 (PANTHERLAKE)
[19:05:05] [PASSED] 0xB084 (PANTHERLAKE)
[19:05:05] [PASSED] 0xB085 (PANTHERLAKE)
[19:05:05] [PASSED] 0xB086 (PANTHERLAKE)
[19:05:05] [PASSED] 0xB087 (PANTHERLAKE)
[19:05:05] [PASSED] 0xB08F (PANTHERLAKE)
[19:05:05] [PASSED] 0xB090 (PANTHERLAKE)
[19:05:05] [PASSED] 0xB0A0 (PANTHERLAKE)
[19:05:05] [PASSED] 0xB0B0 (PANTHERLAKE)
[19:05:05] [PASSED] 0xFD80 (PANTHERLAKE)
[19:05:05] [PASSED] 0xFD81 (PANTHERLAKE)
[19:05:05] [PASSED] 0xD740 (NOVALAKE_S)
[19:05:05] [PASSED] 0xD741 (NOVALAKE_S)
[19:05:05] [PASSED] 0xD742 (NOVALAKE_S)
[19:05:05] [PASSED] 0xD743 (NOVALAKE_S)
[19:05:05] [PASSED] 0xD744 (NOVALAKE_S)
[19:05:05] [PASSED] 0xD745 (NOVALAKE_S)
[19:05:05] [PASSED] 0x674C (CRESCENTISLAND)
[19:05:05] [PASSED] 0xD750 (NOVALAKE_P)
[19:05:05] [PASSED] 0xD751 (NOVALAKE_P)
[19:05:05] [PASSED] 0xD752 (NOVALAKE_P)
[19:05:05] [PASSED] 0xD753 (NOVALAKE_P)
[19:05:05] [PASSED] 0xD754 (NOVALAKE_P)
[19:05:05] [PASSED] 0xD755 (NOVALAKE_P)
[19:05:05] [PASSED] 0xD756 (NOVALAKE_P)
[19:05:05] [PASSED] 0xD757 (NOVALAKE_P)
[19:05:05] [PASSED] 0xD75F (NOVALAKE_P)
[19:05:05] =============== [PASSED] check_platform_desc ===============
[19:05:05] ===================== [PASSED] xe_pci ======================
[19:05:05] =================== xe_rtp (2 subtests) ====================
[19:05:05] =============== xe_rtp_process_to_sr_tests  ================
[19:05:05] [PASSED] coalesce-same-reg
[19:05:05] [PASSED] no-match-no-add
[19:05:05] [PASSED] match-or
[19:05:05] [PASSED] match-or-xfail
[19:05:05] [PASSED] no-match-no-add-multiple-rules
[19:05:05] [PASSED] two-regs-two-entries
[19:05:05] [PASSED] clr-one-set-other
[19:05:05] [PASSED] set-field
[19:05:05] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[19:05:05] [PASSED] conflict-not-disjoint
[19:05:05] [PASSED] conflict-reg-type
[19:05:05] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[19:05:05] ================== xe_rtp_process_tests  ===================
[19:05:05] [PASSED] active1
[19:05:05] [PASSED] active2
[19:05:05] [PASSED] active-inactive
[19:05:05] [PASSED] inactive-active
[19:05:05] [PASSED] inactive-1st_or_active-inactive
[19:05:05] [PASSED] inactive-2nd_or_active-inactive
[19:05:05] [PASSED] inactive-last_or_active-inactive
[19:05:05] [PASSED] inactive-no_or_active-inactive
[19:05:05] ============== [PASSED] xe_rtp_process_tests ===============
[19:05:05] ===================== [PASSED] xe_rtp ======================
[19:05:05] ==================== xe_wa (1 subtest) =====================
[19:05:05] ======================== xe_wa_gt  =========================
[19:05:05] [PASSED] TIGERLAKE B0
[19:05:05] [PASSED] DG1 A0
[19:05:05] [PASSED] DG1 B0
[19:05:05] [PASSED] ALDERLAKE_S A0
[19:05:05] [PASSED] ALDERLAKE_S B0
[19:05:05] [PASSED] ALDERLAKE_S C0
[19:05:05] [PASSED] ALDERLAKE_S D0
[19:05:05] [PASSED] ALDERLAKE_P A0
[19:05:05] [PASSED] ALDERLAKE_P B0
[19:05:05] [PASSED] ALDERLAKE_P C0
[19:05:05] [PASSED] ALDERLAKE_S RPLS D0
[19:05:05] [PASSED] ALDERLAKE_P RPLU E0
[19:05:05] [PASSED] DG2 G10 C0
[19:05:05] [PASSED] DG2 G11 B1
[19:05:05] [PASSED] DG2 G12 A1
[19:05:05] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[19:05:05] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[19:05:05] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[19:05:05] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[19:05:05] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[19:05:05] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[19:05:05] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[19:05:05] ==================== [PASSED] xe_wa_gt =====================
[19:05:05] ====================== [PASSED] xe_wa ======================
[19:05:05] ============================================================
[19:05:05] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[19:05:05] Elapsed time: 36.641s total, 4.214s configuring, 31.861s building, 0.543s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[19:05:05] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:05:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:05:32] Starting KUnit Kernel (1/1)...
[19:05:32] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:05:32] ============ drm_test_pick_cmdline (2 subtests) ============
[19:05:32] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[19:05:32] =============== drm_test_pick_cmdline_named  ===============
[19:05:32] [PASSED] NTSC
[19:05:32] [PASSED] NTSC-J
[19:05:32] [PASSED] PAL
[19:05:32] [PASSED] PAL-M
[19:05:32] =========== [PASSED] drm_test_pick_cmdline_named ===========
[19:05:32] ============== [PASSED] drm_test_pick_cmdline ==============
[19:05:32] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[19:05:32] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[19:05:32] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[19:05:32] =========== drm_validate_clone_mode (2 subtests) ===========
[19:05:32] ============== drm_test_check_in_clone_mode  ===============
[19:05:32] [PASSED] in_clone_mode
[19:05:32] [PASSED] not_in_clone_mode
[19:05:32] ========== [PASSED] drm_test_check_in_clone_mode ===========
[19:05:32] =============== drm_test_check_valid_clones  ===============
[19:05:32] [PASSED] not_in_clone_mode
[19:05:32] [PASSED] valid_clone
[19:05:32] [PASSED] invalid_clone
[19:05:32] =========== [PASSED] drm_test_check_valid_clones ===========
[19:05:32] ============= [PASSED] drm_validate_clone_mode =============
[19:05:32] ============= drm_validate_modeset (1 subtest) =============
[19:05:32] [PASSED] drm_test_check_connector_changed_modeset
[19:05:32] ============== [PASSED] drm_validate_modeset ===============
[19:05:32] ====== drm_test_bridge_get_current_state (2 subtests) ======
[19:05:32] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[19:05:32] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[19:05:32] ======== [PASSED] drm_test_bridge_get_current_state ========
[19:05:32] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[19:05:32] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[19:05:32] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[19:05:32] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[19:05:32] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[19:05:32] ============== drm_bridge_alloc (2 subtests) ===============
[19:05:32] [PASSED] drm_test_drm_bridge_alloc_basic
[19:05:32] [PASSED] drm_test_drm_bridge_alloc_get_put
[19:05:32] ================ [PASSED] drm_bridge_alloc =================
[19:05:32] ============= drm_cmdline_parser (40 subtests) =============
[19:05:32] [PASSED] drm_test_cmdline_force_d_only
[19:05:32] [PASSED] drm_test_cmdline_force_D_only_dvi
[19:05:32] [PASSED] drm_test_cmdline_force_D_only_hdmi
[19:05:32] [PASSED] drm_test_cmdline_force_D_only_not_digital
[19:05:32] [PASSED] drm_test_cmdline_force_e_only
[19:05:32] [PASSED] drm_test_cmdline_res
[19:05:32] [PASSED] drm_test_cmdline_res_vesa
[19:05:32] [PASSED] drm_test_cmdline_res_vesa_rblank
[19:05:32] [PASSED] drm_test_cmdline_res_rblank
[19:05:32] [PASSED] drm_test_cmdline_res_bpp
[19:05:32] [PASSED] drm_test_cmdline_res_refresh
[19:05:32] [PASSED] drm_test_cmdline_res_bpp_refresh
[19:05:32] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[19:05:32] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[19:05:32] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[19:05:32] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[19:05:32] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[19:05:32] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[19:05:32] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[19:05:32] [PASSED] drm_test_cmdline_res_margins_force_on
[19:05:32] [PASSED] drm_test_cmdline_res_vesa_margins
[19:05:32] [PASSED] drm_test_cmdline_name
[19:05:32] [PASSED] drm_test_cmdline_name_bpp
[19:05:32] [PASSED] drm_test_cmdline_name_option
[19:05:32] [PASSED] drm_test_cmdline_name_bpp_option
[19:05:32] [PASSED] drm_test_cmdline_rotate_0
[19:05:32] [PASSED] drm_test_cmdline_rotate_90
[19:05:32] [PASSED] drm_test_cmdline_rotate_180
[19:05:32] [PASSED] drm_test_cmdline_rotate_270
[19:05:32] [PASSED] drm_test_cmdline_hmirror
[19:05:32] [PASSED] drm_test_cmdline_vmirror
[19:05:32] [PASSED] drm_test_cmdline_margin_options
[19:05:32] [PASSED] drm_test_cmdline_multiple_options
[19:05:32] [PASSED] drm_test_cmdline_bpp_extra_and_option
[19:05:32] [PASSED] drm_test_cmdline_extra_and_option
[19:05:32] [PASSED] drm_test_cmdline_freestanding_options
[19:05:32] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[19:05:32] [PASSED] drm_test_cmdline_panel_orientation
[19:05:32] ================ drm_test_cmdline_invalid  =================
[19:05:32] [PASSED] margin_only
[19:05:32] [PASSED] interlace_only
[19:05:32] [PASSED] res_missing_x
[19:05:32] [PASSED] res_missing_y
[19:05:32] [PASSED] res_bad_y
[19:05:32] [PASSED] res_missing_y_bpp
[19:05:32] [PASSED] res_bad_bpp
[19:05:32] [PASSED] res_bad_refresh
[19:05:32] [PASSED] res_bpp_refresh_force_on_off
[19:05:32] [PASSED] res_invalid_mode
[19:05:32] [PASSED] res_bpp_wrong_place_mode
[19:05:32] [PASSED] name_bpp_refresh
[19:05:32] [PASSED] name_refresh
[19:05:32] [PASSED] name_refresh_wrong_mode
[19:05:32] [PASSED] name_refresh_invalid_mode
[19:05:32] [PASSED] rotate_multiple
[19:05:32] [PASSED] rotate_invalid_val
[19:05:32] [PASSED] rotate_truncated
[19:05:32] [PASSED] invalid_option
[19:05:32] [PASSED] invalid_tv_option
[19:05:32] [PASSED] truncated_tv_option
[19:05:32] ============ [PASSED] drm_test_cmdline_invalid =============
[19:05:32] =============== drm_test_cmdline_tv_options  ===============
[19:05:32] [PASSED] NTSC
[19:05:32] [PASSED] NTSC_443
[19:05:32] [PASSED] NTSC_J
[19:05:32] [PASSED] PAL
[19:05:32] [PASSED] PAL_M
[19:05:32] [PASSED] PAL_N
[19:05:32] [PASSED] SECAM
[19:05:32] [PASSED] MONO_525
[19:05:32] [PASSED] MONO_625
[19:05:32] =========== [PASSED] drm_test_cmdline_tv_options ===========
[19:05:32] =============== [PASSED] drm_cmdline_parser ================
[19:05:32] ========== drmm_connector_hdmi_init (20 subtests) ==========
[19:05:32] [PASSED] drm_test_connector_hdmi_init_valid
[19:05:32] [PASSED] drm_test_connector_hdmi_init_bpc_8
[19:05:32] [PASSED] drm_test_connector_hdmi_init_bpc_10
[19:05:32] [PASSED] drm_test_connector_hdmi_init_bpc_12
[19:05:32] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[19:05:32] [PASSED] drm_test_connector_hdmi_init_bpc_null
[19:05:32] [PASSED] drm_test_connector_hdmi_init_formats_empty
[19:05:32] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[19:05:32] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[19:05:32] [PASSED] supported_formats=0x9 yuv420_allowed=1
[19:05:32] [PASSED] supported_formats=0x9 yuv420_allowed=0
[19:05:32] [PASSED] supported_formats=0x3 yuv420_allowed=1
[19:05:32] [PASSED] supported_formats=0x3 yuv420_allowed=0
[19:05:32] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[19:05:32] [PASSED] drm_test_connector_hdmi_init_null_ddc
[19:05:32] [PASSED] drm_test_connector_hdmi_init_null_product
[19:05:32] [PASSED] drm_test_connector_hdmi_init_null_vendor
[19:05:32] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[19:05:32] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[19:05:32] [PASSED] drm_test_connector_hdmi_init_product_valid
[19:05:32] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[19:05:32] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[19:05:32] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[19:05:32] ========= drm_test_connector_hdmi_init_type_valid  =========
[19:05:32] [PASSED] HDMI-A
[19:05:32] [PASSED] HDMI-B
[19:05:32] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[19:05:32] ======== drm_test_connector_hdmi_init_type_invalid  ========
[19:05:32] [PASSED] Unknown
[19:05:32] [PASSED] VGA
[19:05:32] [PASSED] DVI-I
[19:05:32] [PASSED] DVI-D
[19:05:32] [PASSED] DVI-A
[19:05:32] [PASSED] Composite
[19:05:32] [PASSED] SVIDEO
[19:05:32] [PASSED] LVDS
[19:05:32] [PASSED] Component
[19:05:32] [PASSED] DIN
[19:05:32] [PASSED] DP
[19:05:32] [PASSED] TV
[19:05:32] [PASSED] eDP
[19:05:32] [PASSED] Virtual
[19:05:32] [PASSED] DSI
[19:05:32] [PASSED] DPI
[19:05:32] [PASSED] Writeback
[19:05:32] [PASSED] SPI
[19:05:32] [PASSED] USB
[19:05:32] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[19:05:32] ============ [PASSED] drmm_connector_hdmi_init =============
[19:05:32] ============= drmm_connector_init (3 subtests) =============
[19:05:32] [PASSED] drm_test_drmm_connector_init
[19:05:32] [PASSED] drm_test_drmm_connector_init_null_ddc
[19:05:32] ========= drm_test_drmm_connector_init_type_valid  =========
[19:05:32] [PASSED] Unknown
[19:05:32] [PASSED] VGA
[19:05:32] [PASSED] DVI-I
[19:05:32] [PASSED] DVI-D
[19:05:32] [PASSED] DVI-A
[19:05:32] [PASSED] Composite
[19:05:32] [PASSED] SVIDEO
[19:05:32] [PASSED] LVDS
[19:05:32] [PASSED] Component
[19:05:32] [PASSED] DIN
[19:05:32] [PASSED] DP
[19:05:32] [PASSED] HDMI-A
[19:05:32] [PASSED] HDMI-B
[19:05:32] [PASSED] TV
[19:05:32] [PASSED] eDP
[19:05:32] [PASSED] Virtual
[19:05:32] [PASSED] DSI
[19:05:32] [PASSED] DPI
[19:05:32] [PASSED] Writeback
[19:05:32] [PASSED] SPI
[19:05:32] [PASSED] USB
[19:05:32] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[19:05:32] =============== [PASSED] drmm_connector_init ===============
[19:05:32] ========= drm_connector_dynamic_init (6 subtests) ==========
[19:05:32] [PASSED] drm_test_drm_connector_dynamic_init
[19:05:32] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[19:05:32] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[19:05:32] [PASSED] drm_test_drm_connector_dynamic_init_properties
[19:05:32] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[19:05:32] [PASSED] Unknown
[19:05:32] [PASSED] VGA
[19:05:32] [PASSED] DVI-I
[19:05:32] [PASSED] DVI-D
[19:05:32] [PASSED] DVI-A
[19:05:32] [PASSED] Composite
[19:05:32] [PASSED] SVIDEO
[19:05:32] [PASSED] LVDS
[19:05:32] [PASSED] Component
[19:05:32] [PASSED] DIN
[19:05:32] [PASSED] DP
[19:05:32] [PASSED] HDMI-A
[19:05:32] [PASSED] HDMI-B
[19:05:32] [PASSED] TV
[19:05:32] [PASSED] eDP
[19:05:32] [PASSED] Virtual
[19:05:32] [PASSED] DSI
[19:05:32] [PASSED] DPI
[19:05:32] [PASSED] Writeback
[19:05:32] [PASSED] SPI
[19:05:32] [PASSED] USB
[19:05:32] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[19:05:32] ======== drm_test_drm_connector_dynamic_init_name  =========
[19:05:32] [PASSED] Unknown
[19:05:32] [PASSED] VGA
[19:05:32] [PASSED] DVI-I
[19:05:32] [PASSED] DVI-D
[19:05:32] [PASSED] DVI-A
[19:05:32] [PASSED] Composite
[19:05:32] [PASSED] SVIDEO
[19:05:32] [PASSED] LVDS
[19:05:32] [PASSED] Component
[19:05:32] [PASSED] DIN
[19:05:32] [PASSED] DP
[19:05:32] [PASSED] HDMI-A
[19:05:32] [PASSED] HDMI-B
[19:05:32] [PASSED] TV
[19:05:32] [PASSED] eDP
[19:05:32] [PASSED] Virtual
[19:05:32] [PASSED] DSI
[19:05:32] [PASSED] DPI
[19:05:32] [PASSED] Writeback
[19:05:32] [PASSED] SPI
[19:05:32] [PASSED] USB
[19:05:32] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[19:05:32] =========== [PASSED] drm_connector_dynamic_init ============
[19:05:32] ==== drm_connector_dynamic_register_early (4 subtests) =====
[19:05:32] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[19:05:32] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[19:05:32] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[19:05:32] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[19:05:32] ====== [PASSED] drm_connector_dynamic_register_early =======
[19:05:32] ======= drm_connector_dynamic_register (7 subtests) ========
[19:05:32] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[19:05:32] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[19:05:32] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[19:05:32] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[19:05:32] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[19:05:32] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[19:05:32] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[19:05:32] ========= [PASSED] drm_connector_dynamic_register ==========
[19:05:32] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[19:05:32] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[19:05:32] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[19:05:32] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[19:05:32] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[19:05:32] ========== drm_test_get_tv_mode_from_name_valid  ===========
[19:05:32] [PASSED] NTSC
[19:05:32] [PASSED] NTSC-443
[19:05:32] [PASSED] NTSC-J
[19:05:32] [PASSED] PAL
[19:05:32] [PASSED] PAL-M
[19:05:32] [PASSED] PAL-N
[19:05:32] [PASSED] SECAM
[19:05:32] [PASSED] Mono
[19:05:32] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[19:05:32] [PASSED] drm_test_get_tv_mode_from_name_truncated
[19:05:32] ============ [PASSED] drm_get_tv_mode_from_name ============
[19:05:32] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[19:05:32] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[19:05:32] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[19:05:32] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[19:05:32] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[19:05:32] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[19:05:32] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[19:05:32] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[19:05:32] [PASSED] VIC 96
[19:05:32] [PASSED] VIC 97
[19:05:32] [PASSED] VIC 101
[19:05:32] [PASSED] VIC 102
[19:05:32] [PASSED] VIC 106
[19:05:32] [PASSED] VIC 107
[19:05:32] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[19:05:32] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[19:05:32] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[19:05:32] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[19:05:32] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[19:05:32] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[19:05:32] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[19:05:32] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[19:05:32] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[19:05:32] [PASSED] Automatic
[19:05:32] [PASSED] Full
[19:05:32] [PASSED] Limited 16:235
[19:05:32] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[19:05:32] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[19:05:32] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[19:05:32] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[19:05:32] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[19:05:32] [PASSED] RGB
[19:05:32] [PASSED] YUV 4:2:0
[19:05:32] [PASSED] YUV 4:2:2
[19:05:32] [PASSED] YUV 4:4:4
[19:05:32] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[19:05:32] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[19:05:32] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[19:05:32] ============= drm_damage_helper (21 subtests) ==============
[19:05:32] [PASSED] drm_test_damage_iter_no_damage
[19:05:32] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[19:05:32] [PASSED] drm_test_damage_iter_no_damage_src_moved
[19:05:32] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[19:05:32] [PASSED] drm_test_damage_iter_no_damage_not_visible
[19:05:32] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[19:05:32] [PASSED] drm_test_damage_iter_no_damage_no_fb
[19:05:32] [PASSED] drm_test_damage_iter_simple_damage
[19:05:32] [PASSED] drm_test_damage_iter_single_damage
[19:05:32] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[19:05:32] [PASSED] drm_test_damage_iter_single_damage_outside_src
[19:05:32] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[19:05:32] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[19:05:32] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[19:05:32] [PASSED] drm_test_damage_iter_single_damage_src_moved
[19:05:32] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[19:05:32] [PASSED] drm_test_damage_iter_damage
[19:05:32] [PASSED] drm_test_damage_iter_damage_one_intersect
[19:05:32] [PASSED] drm_test_damage_iter_damage_one_outside
[19:05:32] [PASSED] drm_test_damage_iter_damage_src_moved
[19:05:32] [PASSED] drm_test_damage_iter_damage_not_visible
[19:05:32] ================ [PASSED] drm_damage_helper ================
[19:05:32] ============== drm_dp_mst_helper (3 subtests) ==============
[19:05:32] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[19:05:32] [PASSED] Clock 154000 BPP 30 DSC disabled
[19:05:32] [PASSED] Clock 234000 BPP 30 DSC disabled
[19:05:32] [PASSED] Clock 297000 BPP 24 DSC disabled
[19:05:32] [PASSED] Clock 332880 BPP 24 DSC enabled
[19:05:32] [PASSED] Clock 324540 BPP 24 DSC enabled
[19:05:32] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[19:05:32] ============== drm_test_dp_mst_calc_pbn_div  ===============
[19:05:32] [PASSED] Link rate 2000000 lane count 4
[19:05:32] [PASSED] Link rate 2000000 lane count 2
[19:05:32] [PASSED] Link rate 2000000 lane count 1
[19:05:32] [PASSED] Link rate 1350000 lane count 4
[19:05:32] [PASSED] Link rate 1350000 lane count 2
[19:05:32] [PASSED] Link rate 1350000 lane count 1
[19:05:32] [PASSED] Link rate 1000000 lane count 4
[19:05:32] [PASSED] Link rate 1000000 lane count 2
[19:05:32] [PASSED] Link rate 1000000 lane count 1
[19:05:32] [PASSED] Link rate 810000 lane count 4
[19:05:32] [PASSED] Link rate 810000 lane count 2
[19:05:32] [PASSED] Link rate 810000 lane count 1
[19:05:32] [PASSED] Link rate 540000 lane count 4
[19:05:32] [PASSED] Link rate 540000 lane count 2
[19:05:32] [PASSED] Link rate 540000 lane count 1
[19:05:32] [PASSED] Link rate 270000 lane count 4
[19:05:32] [PASSED] Link rate 270000 lane count 2
[19:05:32] [PASSED] Link rate 270000 lane count 1
[19:05:32] [PASSED] Link rate 162000 lane count 4
[19:05:32] [PASSED] Link rate 162000 lane count 2
[19:05:32] [PASSED] Link rate 162000 lane count 1
[19:05:32] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[19:05:32] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[19:05:32] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[19:05:32] [PASSED] DP_POWER_UP_PHY with port number
[19:05:32] [PASSED] DP_POWER_DOWN_PHY with port number
[19:05:32] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[19:05:32] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[19:05:32] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[19:05:32] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[19:05:32] [PASSED] DP_QUERY_PAYLOAD with port number
[19:05:32] [PASSED] DP_QUERY_PAYLOAD with VCPI
[19:05:32] [PASSED] DP_REMOTE_DPCD_READ with port number
[19:05:32] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[19:05:32] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[19:05:32] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[19:05:32] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[19:05:32] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[19:05:32] [PASSED] DP_REMOTE_I2C_READ with port number
[19:05:32] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[19:05:32] [PASSED] DP_REMOTE_I2C_READ with transactions array
[19:05:32] [PASSED] DP_REMOTE_I2C_WRITE with port number
[19:05:32] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[19:05:32] [PASSED] DP_REMOTE_I2C_WRITE with data array
[19:05:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[19:05:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[19:05:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[19:05:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[19:05:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[19:05:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[19:05:32] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[19:05:32] ================ [PASSED] drm_dp_mst_helper ================
[19:05:32] ================== drm_exec (7 subtests) ===================
[19:05:32] [PASSED] sanitycheck
[19:05:32] [PASSED] test_lock
[19:05:32] [PASSED] test_lock_unlock
[19:05:32] [PASSED] test_duplicates
[19:05:32] [PASSED] test_prepare
[19:05:32] [PASSED] test_prepare_array
[19:05:32] [PASSED] test_multiple_loops
[19:05:32] ==================== [PASSED] drm_exec =====================
[19:05:32] =========== drm_format_helper_test (17 subtests) ===========
[19:05:32] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[19:05:32] [PASSED] single_pixel_source_buffer
[19:05:32] [PASSED] single_pixel_clip_rectangle
[19:05:32] [PASSED] well_known_colors
[19:05:32] [PASSED] destination_pitch
[19:05:32] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[19:05:32] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[19:05:32] [PASSED] single_pixel_source_buffer
[19:05:32] [PASSED] single_pixel_clip_rectangle
[19:05:32] [PASSED] well_known_colors
[19:05:32] [PASSED] destination_pitch
[19:05:32] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[19:05:32] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[19:05:32] [PASSED] single_pixel_source_buffer
[19:05:32] [PASSED] single_pixel_clip_rectangle
[19:05:32] [PASSED] well_known_colors
[19:05:32] [PASSED] destination_pitch
[19:05:32] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[19:05:32] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[19:05:32] [PASSED] single_pixel_source_buffer
[19:05:32] [PASSED] single_pixel_clip_rectangle
[19:05:32] [PASSED] well_known_colors
[19:05:32] [PASSED] destination_pitch
[19:05:32] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[19:05:32] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[19:05:32] [PASSED] single_pixel_source_buffer
[19:05:32] [PASSED] single_pixel_clip_rectangle
[19:05:32] [PASSED] well_known_colors
[19:05:32] [PASSED] destination_pitch
[19:05:32] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[19:05:32] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[19:05:32] [PASSED] single_pixel_source_buffer
[19:05:32] [PASSED] single_pixel_clip_rectangle
[19:05:32] [PASSED] well_known_colors
[19:05:32] [PASSED] destination_pitch
[19:05:32] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[19:05:32] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[19:05:32] [PASSED] single_pixel_source_buffer
[19:05:32] [PASSED] single_pixel_clip_rectangle
[19:05:32] [PASSED] well_known_colors
[19:05:32] [PASSED] destination_pitch
[19:05:32] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[19:05:32] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[19:05:32] [PASSED] single_pixel_source_buffer
[19:05:32] [PASSED] single_pixel_clip_rectangle
[19:05:32] [PASSED] well_known_colors
[19:05:32] [PASSED] destination_pitch
[19:05:32] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[19:05:32] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[19:05:32] [PASSED] single_pixel_source_buffer
[19:05:32] [PASSED] single_pixel_clip_rectangle
[19:05:32] [PASSED] well_known_colors
[19:05:32] [PASSED] destination_pitch
[19:05:32] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[19:05:32] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[19:05:32] [PASSED] single_pixel_source_buffer
[19:05:32] [PASSED] single_pixel_clip_rectangle
[19:05:32] [PASSED] well_known_colors
[19:05:32] [PASSED] destination_pitch
[19:05:32] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[19:05:32] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[19:05:32] [PASSED] single_pixel_source_buffer
[19:05:32] [PASSED] single_pixel_clip_rectangle
[19:05:32] [PASSED] well_known_colors
[19:05:32] [PASSED] destination_pitch
[19:05:32] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[19:05:32] ============== drm_test_fb_xrgb8888_to_mono  ===============
[19:05:32] [PASSED] single_pixel_source_buffer
[19:05:32] [PASSED] single_pixel_clip_rectangle
[19:05:32] [PASSED] well_known_colors
[19:05:32] [PASSED] destination_pitch
[19:05:32] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[19:05:32] ==================== drm_test_fb_swab  =====================
[19:05:32] [PASSED] single_pixel_source_buffer
[19:05:32] [PASSED] single_pixel_clip_rectangle
[19:05:32] [PASSED] well_known_colors
[19:05:32] [PASSED] destination_pitch
[19:05:32] ================ [PASSED] drm_test_fb_swab =================
[19:05:32] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[19:05:32] [PASSED] single_pixel_source_buffer
[19:05:32] [PASSED] single_pixel_clip_rectangle
[19:05:32] [PASSED] well_known_colors
[19:05:32] [PASSED] destination_pitch
[19:05:32] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[19:05:32] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[19:05:32] [PASSED] single_pixel_source_buffer
[19:05:32] [PASSED] single_pixel_clip_rectangle
[19:05:32] [PASSED] well_known_colors
[19:05:32] [PASSED] destination_pitch
[19:05:32] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[19:05:32] ================= drm_test_fb_clip_offset  =================
[19:05:32] [PASSED] pass through
[19:05:32] [PASSED] horizontal offset
[19:05:32] [PASSED] vertical offset
[19:05:32] [PASSED] horizontal and vertical offset
[19:05:32] [PASSED] horizontal offset (custom pitch)
[19:05:32] [PASSED] vertical offset (custom pitch)
[19:05:32] [PASSED] horizontal and vertical offset (custom pitch)
[19:05:32] ============= [PASSED] drm_test_fb_clip_offset =============
[19:05:32] =================== drm_test_fb_memcpy  ====================
[19:05:32] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[19:05:32] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[19:05:32] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[19:05:32] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[19:05:32] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[19:05:32] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[19:05:32] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[19:05:32] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[19:05:32] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[19:05:32] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[19:05:32] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[19:05:32] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[19:05:32] =============== [PASSED] drm_test_fb_memcpy ================
[19:05:32] ============= [PASSED] drm_format_helper_test ==============
[19:05:32] ================= drm_format (18 subtests) =================
[19:05:32] [PASSED] drm_test_format_block_width_invalid
[19:05:32] [PASSED] drm_test_format_block_width_one_plane
[19:05:32] [PASSED] drm_test_format_block_width_two_plane
[19:05:32] [PASSED] drm_test_format_block_width_three_plane
[19:05:32] [PASSED] drm_test_format_block_width_tiled
[19:05:32] [PASSED] drm_test_format_block_height_invalid
[19:05:32] [PASSED] drm_test_format_block_height_one_plane
[19:05:32] [PASSED] drm_test_format_block_height_two_plane
[19:05:32] [PASSED] drm_test_format_block_height_three_plane
[19:05:32] [PASSED] drm_test_format_block_height_tiled
[19:05:32] [PASSED] drm_test_format_min_pitch_invalid
[19:05:32] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[19:05:32] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[19:05:32] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[19:05:32] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[19:05:32] [PASSED] drm_test_format_min_pitch_two_plane
[19:05:32] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[19:05:32] [PASSED] drm_test_format_min_pitch_tiled
[19:05:32] =================== [PASSED] drm_format ====================
[19:05:32] ============== drm_framebuffer (10 subtests) ===============
[19:05:32] ========== drm_test_framebuffer_check_src_coords  ==========
[19:05:32] [PASSED] Success: source fits into fb
[19:05:32] [PASSED] Fail: overflowing fb with x-axis coordinate
[19:05:32] [PASSED] Fail: overflowing fb with y-axis coordinate
[19:05:32] [PASSED] Fail: overflowing fb with source width
[19:05:32] [PASSED] Fail: overflowing fb with source height
[19:05:32] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[19:05:32] [PASSED] drm_test_framebuffer_cleanup
[19:05:32] =============== drm_test_framebuffer_create  ===============
[19:05:32] [PASSED] ABGR8888 normal sizes
[19:05:32] [PASSED] ABGR8888 max sizes
[19:05:32] [PASSED] ABGR8888 pitch greater than min required
[19:05:32] [PASSED] ABGR8888 pitch less than min required
[19:05:32] [PASSED] ABGR8888 Invalid width
[19:05:32] [PASSED] ABGR8888 Invalid buffer handle
[19:05:32] [PASSED] No pixel format
[19:05:32] [PASSED] ABGR8888 Width 0
[19:05:32] [PASSED] ABGR8888 Height 0
[19:05:32] [PASSED] ABGR8888 Out of bound height * pitch combination
[19:05:32] [PASSED] ABGR8888 Large buffer offset
[19:05:32] [PASSED] ABGR8888 Buffer offset for inexistent plane
[19:05:32] [PASSED] ABGR8888 Invalid flag
[19:05:32] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[19:05:32] [PASSED] ABGR8888 Valid buffer modifier
[19:05:32] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[19:05:32] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[19:05:32] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[19:05:32] [PASSED] NV12 Normal sizes
[19:05:32] [PASSED] NV12 Max sizes
[19:05:32] [PASSED] NV12 Invalid pitch
[19:05:32] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[19:05:32] [PASSED] NV12 different  modifier per-plane
[19:05:32] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[19:05:32] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[19:05:32] [PASSED] NV12 Modifier for inexistent plane
[19:05:32] [PASSED] NV12 Handle for inexistent plane
[19:05:32] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[19:05:32] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[19:05:32] [PASSED] YVU420 Normal sizes
[19:05:32] [PASSED] YVU420 Max sizes
[19:05:32] [PASSED] YVU420 Invalid pitch
[19:05:32] [PASSED] YVU420 Different pitches
[19:05:32] [PASSED] YVU420 Different buffer offsets/pitches
[19:05:32] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[19:05:32] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[19:05:32] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[19:05:32] [PASSED] YVU420 Valid modifier
[19:05:32] [PASSED] YVU420 Different modifiers per plane
[19:05:32] [PASSED] YVU420 Modifier for inexistent plane
[19:05:32] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[19:05:32] [PASSED] X0L2 Normal sizes
[19:05:32] [PASSED] X0L2 Max sizes
[19:05:32] [PASSED] X0L2 Invalid pitch
[19:05:32] [PASSED] X0L2 Pitch greater than minimum required
[19:05:32] [PASSED] X0L2 Handle for inexistent plane
[19:05:32] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[19:05:32] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[19:05:32] [PASSED] X0L2 Valid modifier
[19:05:32] [PASSED] X0L2 Modifier for inexistent plane
[19:05:32] =========== [PASSED] drm_test_framebuffer_create ===========
[19:05:32] [PASSED] drm_test_framebuffer_free
[19:05:32] [PASSED] drm_test_framebuffer_init
[19:05:32] [PASSED] drm_test_framebuffer_init_bad_format
[19:05:32] [PASSED] drm_test_framebuffer_init_dev_mismatch
[19:05:32] [PASSED] drm_test_framebuffer_lookup
[19:05:32] [PASSED] drm_test_framebuffer_lookup_inexistent
[19:05:32] [PASSED] drm_test_framebuffer_modifiers_not_supported
[19:05:32] ================= [PASSED] drm_framebuffer =================
[19:05:32] ================ drm_gem_shmem (8 subtests) ================
[19:05:32] [PASSED] drm_gem_shmem_test_obj_create
[19:05:32] [PASSED] drm_gem_shmem_test_obj_create_private
[19:05:32] [PASSED] drm_gem_shmem_test_pin_pages
[19:05:32] [PASSED] drm_gem_shmem_test_vmap
[19:05:32] [PASSED] drm_gem_shmem_test_get_sg_table
[19:05:32] [PASSED] drm_gem_shmem_test_get_pages_sgt
[19:05:32] [PASSED] drm_gem_shmem_test_madvise
[19:05:32] [PASSED] drm_gem_shmem_test_purge
[19:05:32] ================== [PASSED] drm_gem_shmem ==================
[19:05:32] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[19:05:32] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[19:05:32] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[19:05:32] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[19:05:32] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[19:05:32] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[19:05:32] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[19:05:32] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[19:05:32] [PASSED] Automatic
[19:05:32] [PASSED] Full
[19:05:32] [PASSED] Limited 16:235
[19:05:32] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[19:05:32] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[19:05:32] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[19:05:32] [PASSED] drm_test_check_disable_connector
[19:05:32] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[19:05:32] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[19:05:32] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[19:05:32] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[19:05:32] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[19:05:32] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[19:05:32] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[19:05:32] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[19:05:32] [PASSED] drm_test_check_output_bpc_dvi
[19:05:32] [PASSED] drm_test_check_output_bpc_format_vic_1
[19:05:32] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[19:05:32] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[19:05:32] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[19:05:32] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[19:05:32] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[19:05:32] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[19:05:32] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[19:05:32] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[19:05:32] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[19:05:32] [PASSED] drm_test_check_broadcast_rgb_value
[19:05:32] [PASSED] drm_test_check_bpc_8_value
[19:05:32] [PASSED] drm_test_check_bpc_10_value
[19:05:32] [PASSED] drm_test_check_bpc_12_value
[19:05:32] [PASSED] drm_test_check_format_value
[19:05:32] [PASSED] drm_test_check_tmds_char_value
[19:05:32] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[19:05:32] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[19:05:32] [PASSED] drm_test_check_mode_valid
[19:05:32] [PASSED] drm_test_check_mode_valid_reject
[19:05:32] [PASSED] drm_test_check_mode_valid_reject_rate
[19:05:32] [PASSED] drm_test_check_mode_valid_reject_max_clock
[19:05:32] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[19:05:32] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[19:05:32] [PASSED] drm_test_check_infoframes
[19:05:32] [PASSED] drm_test_check_reject_avi_infoframe
[19:05:32] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[19:05:32] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[19:05:32] [PASSED] drm_test_check_reject_audio_infoframe
[19:05:32] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[19:05:32] ================= drm_managed (2 subtests) =================
[19:05:32] [PASSED] drm_test_managed_release_action
[19:05:32] [PASSED] drm_test_managed_run_action
[19:05:32] =================== [PASSED] drm_managed ===================
[19:05:32] =================== drm_mm (6 subtests) ====================
[19:05:32] [PASSED] drm_test_mm_init
[19:05:32] [PASSED] drm_test_mm_debug
[19:05:32] [PASSED] drm_test_mm_align32
[19:05:32] [PASSED] drm_test_mm_align64
[19:05:32] [PASSED] drm_test_mm_lowest
[19:05:32] [PASSED] drm_test_mm_highest
[19:05:32] ===================== [PASSED] drm_mm ======================
[19:05:32] ============= drm_modes_analog_tv (5 subtests) =============
[19:05:32] [PASSED] drm_test_modes_analog_tv_mono_576i
[19:05:32] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[19:05:32] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[19:05:32] [PASSED] drm_test_modes_analog_tv_pal_576i
[19:05:32] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[19:05:32] =============== [PASSED] drm_modes_analog_tv ===============
[19:05:32] ============== drm_plane_helper (2 subtests) ===============
[19:05:32] =============== drm_test_check_plane_state  ================
[19:05:32] [PASSED] clipping_simple
[19:05:32] [PASSED] clipping_rotate_reflect
[19:05:32] [PASSED] positioning_simple
[19:05:32] [PASSED] upscaling
[19:05:32] [PASSED] downscaling
[19:05:32] [PASSED] rounding1
[19:05:32] [PASSED] rounding2
[19:05:32] [PASSED] rounding3
[19:05:32] [PASSED] rounding4
[19:05:32] =========== [PASSED] drm_test_check_plane_state ============
[19:05:32] =========== drm_test_check_invalid_plane_state  ============
[19:05:32] [PASSED] positioning_invalid
[19:05:32] [PASSED] upscaling_invalid
[19:05:32] [PASSED] downscaling_invalid
[19:05:32] ======= [PASSED] drm_test_check_invalid_plane_state ========
[19:05:32] ================ [PASSED] drm_plane_helper =================
[19:05:32] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[19:05:32] ====== drm_test_connector_helper_tv_get_modes_check  =======
[19:05:32] [PASSED] None
[19:05:32] [PASSED] PAL
[19:05:32] [PASSED] NTSC
[19:05:32] [PASSED] Both, NTSC Default
[19:05:32] [PASSED] Both, PAL Default
[19:05:32] [PASSED] Both, NTSC Default, with PAL on command-line
[19:05:32] [PASSED] Both, PAL Default, with NTSC on command-line
[19:05:32] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[19:05:32] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[19:05:32] ================== drm_rect (9 subtests) ===================
[19:05:32] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[19:05:32] [PASSED] drm_test_rect_clip_scaled_not_clipped
[19:05:32] [PASSED] drm_test_rect_clip_scaled_clipped
[19:05:32] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[19:05:32] ================= drm_test_rect_intersect  =================
[19:05:32] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[19:05:32] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[19:05:32] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[19:05:32] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[19:05:32] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[19:05:32] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[19:05:32] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[19:05:32] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[19:05:32] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[19:05:32] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[19:05:32] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[19:05:32] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[19:05:32] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[19:05:32] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[19:05:32] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[19:05:32] ============= [PASSED] drm_test_rect_intersect =============
[19:05:32] ================ drm_test_rect_calc_hscale  ================
[19:05:32] [PASSED] normal use
[19:05:32] [PASSED] out of max range
[19:05:32] [PASSED] out of min range
[19:05:32] [PASSED] zero dst
[19:05:32] [PASSED] negative src
[19:05:32] [PASSED] negative dst
[19:05:32] ============ [PASSED] drm_test_rect_calc_hscale ============
[19:05:32] ================ drm_test_rect_calc_vscale  ================
[19:05:32] [PASSED] normal use
[19:05:32] [PASSED] out of max range
[19:05:32] [PASSED] out of min range
[19:05:32] [PASSED] zero dst
[19:05:32] [PASSED] negative src
[19:05:32] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[19:05:32] ============ [PASSED] drm_test_rect_calc_vscale ============
[19:05:32] ================== drm_test_rect_rotate  ===================
[19:05:32] [PASSED] reflect-x
[19:05:32] [PASSED] reflect-y
[19:05:32] [PASSED] rotate-0
[19:05:32] [PASSED] rotate-90
[19:05:32] [PASSED] rotate-180
[19:05:32] [PASSED] rotate-270
[19:05:32] ============== [PASSED] drm_test_rect_rotate ===============
[19:05:32] ================ drm_test_rect_rotate_inv  =================
[19:05:32] [PASSED] reflect-x
[19:05:32] [PASSED] reflect-y
[19:05:32] [PASSED] rotate-0
[19:05:32] [PASSED] rotate-90
[19:05:32] [PASSED] rotate-180
[19:05:32] [PASSED] rotate-270
[19:05:32] ============ [PASSED] drm_test_rect_rotate_inv =============
[19:05:32] ==================== [PASSED] drm_rect =====================
[19:05:32] ============ drm_sysfb_modeset_test (1 subtest) ============
[19:05:32] ============ drm_test_sysfb_build_fourcc_list  =============
[19:05:32] [PASSED] no native formats
[19:05:32] [PASSED] XRGB8888 as native format
[19:05:32] [PASSED] remove duplicates
[19:05:32] [PASSED] convert alpha formats
[19:05:32] [PASSED] random formats
[19:05:32] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[19:05:32] ============= [PASSED] drm_sysfb_modeset_test ==============
[19:05:32] ================== drm_fixp (2 subtests) ===================
[19:05:32] [PASSED] drm_test_int2fixp
[19:05:32] [PASSED] drm_test_sm2fixp
[19:05:32] ==================== [PASSED] drm_fixp =====================
[19:05:32] ============================================================
[19:05:32] Testing complete. Ran 621 tests: passed: 621
[19:05:32] Elapsed time: 27.210s total, 1.673s configuring, 25.368s building, 0.128s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[19:05:32] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:05:34] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:05:43] Starting KUnit Kernel (1/1)...
[19:05:43] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:05:44] ================= ttm_device (5 subtests) ==================
[19:05:44] [PASSED] ttm_device_init_basic
[19:05:44] [PASSED] ttm_device_init_multiple
[19:05:44] [PASSED] ttm_device_fini_basic
[19:05:44] [PASSED] ttm_device_init_no_vma_man
[19:05:44] ================== ttm_device_init_pools  ==================
[19:05:44] [PASSED] No DMA allocations, no DMA32 required
[19:05:44] [PASSED] DMA allocations, DMA32 required
[19:05:44] [PASSED] No DMA allocations, DMA32 required
[19:05:44] [PASSED] DMA allocations, no DMA32 required
[19:05:44] ============== [PASSED] ttm_device_init_pools ==============
[19:05:44] =================== [PASSED] ttm_device ====================
[19:05:44] ================== ttm_pool (8 subtests) ===================
[19:05:44] ================== ttm_pool_alloc_basic  ===================
[19:05:44] [PASSED] One page
[19:05:44] [PASSED] More than one page
[19:05:44] [PASSED] Above the allocation limit
[19:05:44] [PASSED] One page, with coherent DMA mappings enabled
[19:05:44] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:05:44] ============== [PASSED] ttm_pool_alloc_basic ===============
[19:05:44] ============== ttm_pool_alloc_basic_dma_addr  ==============
[19:05:44] [PASSED] One page
[19:05:44] [PASSED] More than one page
[19:05:44] [PASSED] Above the allocation limit
[19:05:44] [PASSED] One page, with coherent DMA mappings enabled
[19:05:44] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:05:44] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[19:05:44] [PASSED] ttm_pool_alloc_order_caching_match
[19:05:44] [PASSED] ttm_pool_alloc_caching_mismatch
[19:05:44] [PASSED] ttm_pool_alloc_order_mismatch
[19:05:44] [PASSED] ttm_pool_free_dma_alloc
[19:05:44] [PASSED] ttm_pool_free_no_dma_alloc
[19:05:44] [PASSED] ttm_pool_fini_basic
[19:05:44] ==================== [PASSED] ttm_pool =====================
[19:05:44] ================ ttm_resource (8 subtests) =================
[19:05:44] ================= ttm_resource_init_basic  =================
[19:05:44] [PASSED] Init resource in TTM_PL_SYSTEM
[19:05:44] [PASSED] Init resource in TTM_PL_VRAM
[19:05:44] [PASSED] Init resource in a private placement
[19:05:44] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[19:05:44] ============= [PASSED] ttm_resource_init_basic =============
[19:05:44] [PASSED] ttm_resource_init_pinned
[19:05:44] [PASSED] ttm_resource_fini_basic
[19:05:44] [PASSED] ttm_resource_manager_init_basic
[19:05:44] [PASSED] ttm_resource_manager_usage_basic
[19:05:44] [PASSED] ttm_resource_manager_set_used_basic
[19:05:44] [PASSED] ttm_sys_man_alloc_basic
[19:05:44] [PASSED] ttm_sys_man_free_basic
[19:05:44] ================== [PASSED] ttm_resource ===================
[19:05:44] =================== ttm_tt (15 subtests) ===================
[19:05:44] ==================== ttm_tt_init_basic  ====================
[19:05:44] [PASSED] Page-aligned size
[19:05:44] [PASSED] Extra pages requested
[19:05:44] ================ [PASSED] ttm_tt_init_basic ================
[19:05:44] [PASSED] ttm_tt_init_misaligned
[19:05:44] [PASSED] ttm_tt_fini_basic
[19:05:44] [PASSED] ttm_tt_fini_sg
[19:05:44] [PASSED] ttm_tt_fini_shmem
[19:05:44] [PASSED] ttm_tt_create_basic
[19:05:44] [PASSED] ttm_tt_create_invalid_bo_type
[19:05:44] [PASSED] ttm_tt_create_ttm_exists
[19:05:44] [PASSED] ttm_tt_create_failed
[19:05:44] [PASSED] ttm_tt_destroy_basic
[19:05:44] [PASSED] ttm_tt_populate_null_ttm
[19:05:44] [PASSED] ttm_tt_populate_populated_ttm
[19:05:44] [PASSED] ttm_tt_unpopulate_basic
[19:05:44] [PASSED] ttm_tt_unpopulate_empty_ttm
[19:05:44] [PASSED] ttm_tt_swapin_basic
[19:05:44] ===================== [PASSED] ttm_tt ======================
[19:05:44] =================== ttm_bo (14 subtests) ===================
[19:05:44] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[19:05:44] [PASSED] Cannot be interrupted and sleeps
[19:05:44] [PASSED] Cannot be interrupted, locks straight away
[19:05:44] [PASSED] Can be interrupted, sleeps
[19:05:44] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[19:05:44] [PASSED] ttm_bo_reserve_locked_no_sleep
[19:05:44] [PASSED] ttm_bo_reserve_no_wait_ticket
[19:05:44] [PASSED] ttm_bo_reserve_double_resv
[19:05:44] [PASSED] ttm_bo_reserve_interrupted
[19:05:44] [PASSED] ttm_bo_reserve_deadlock
[19:05:44] [PASSED] ttm_bo_unreserve_basic
[19:05:44] [PASSED] ttm_bo_unreserve_pinned
[19:05:44] [PASSED] ttm_bo_unreserve_bulk
[19:05:44] [PASSED] ttm_bo_fini_basic
[19:05:44] [PASSED] ttm_bo_fini_shared_resv
[19:05:44] [PASSED] ttm_bo_pin_basic
[19:05:44] [PASSED] ttm_bo_pin_unpin_resource
[19:05:44] [PASSED] ttm_bo_multiple_pin_one_unpin
[19:05:44] ===================== [PASSED] ttm_bo ======================
[19:05:44] ============== ttm_bo_validate (21 subtests) ===============
[19:05:44] ============== ttm_bo_init_reserved_sys_man  ===============
[19:05:44] [PASSED] Buffer object for userspace
[19:05:44] [PASSED] Kernel buffer object
[19:05:44] [PASSED] Shared buffer object
[19:05:44] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[19:05:44] ============== ttm_bo_init_reserved_mock_man  ==============
[19:05:44] [PASSED] Buffer object for userspace
[19:05:44] [PASSED] Kernel buffer object
[19:05:44] [PASSED] Shared buffer object
[19:05:44] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[19:05:44] [PASSED] ttm_bo_init_reserved_resv
[19:05:44] ================== ttm_bo_validate_basic  ==================
[19:05:44] [PASSED] Buffer object for userspace
[19:05:44] [PASSED] Kernel buffer object
[19:05:44] [PASSED] Shared buffer object
[19:05:44] ============== [PASSED] ttm_bo_validate_basic ==============
[19:05:44] [PASSED] ttm_bo_validate_invalid_placement
[19:05:44] ============= ttm_bo_validate_same_placement  ==============
[19:05:44] [PASSED] System manager
[19:05:44] [PASSED] VRAM manager
[19:05:44] ========= [PASSED] ttm_bo_validate_same_placement ==========
[19:05:44] [PASSED] ttm_bo_validate_failed_alloc
[19:05:44] [PASSED] ttm_bo_validate_pinned
[19:05:44] [PASSED] ttm_bo_validate_busy_placement
[19:05:44] ================ ttm_bo_validate_multihop  =================
[19:05:44] [PASSED] Buffer object for userspace
[19:05:44] [PASSED] Kernel buffer object
[19:05:44] [PASSED] Shared buffer object
[19:05:44] ============ [PASSED] ttm_bo_validate_multihop =============
[19:05:44] ========== ttm_bo_validate_no_placement_signaled  ==========
[19:05:44] [PASSED] Buffer object in system domain, no page vector
[19:05:44] [PASSED] Buffer object in system domain with an existing page vector
[19:05:44] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[19:05:44] ======== ttm_bo_validate_no_placement_not_signaled  ========
[19:05:44] [PASSED] Buffer object for userspace
[19:05:44] [PASSED] Kernel buffer object
[19:05:44] [PASSED] Shared buffer object
[19:05:44] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[19:05:44] [PASSED] ttm_bo_validate_move_fence_signaled
[19:05:44] ========= ttm_bo_validate_move_fence_not_signaled  =========
[19:05:44] [PASSED] Waits for GPU
[19:05:44] [PASSED] Tries to lock straight away
[19:05:44] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[19:05:44] [PASSED] ttm_bo_validate_happy_evict
[19:05:44] [PASSED] ttm_bo_validate_all_pinned_evict
[19:05:44] [PASSED] ttm_bo_validate_allowed_only_evict
[19:05:44] [PASSED] ttm_bo_validate_deleted_evict
[19:05:44] [PASSED] ttm_bo_validate_busy_domain_evict
[19:05:44] [PASSED] ttm_bo_validate_evict_gutting
[19:05:44] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[19:05:44] ================= [PASSED] ttm_bo_validate =================
[19:05:44] ============================================================
[19:05:44] Testing complete. Ran 101 tests: passed: 101
[19:05:44] Elapsed time: 11.610s total, 1.713s configuring, 9.681s building, 0.183s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Workaround cleanup & simplification (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1406 bytes --]

== Series Details ==

Series: Workaround cleanup & simplification (rev2)
URL   : https://patchwork.freedesktop.org/series/161606/
State : success

== Summary ==

CI Bug Log - changes from xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13_BAT -> xe-pw-161606v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-161606v2_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@reltime:
    - bat-dg2-oem2:       [PASS][1] -> [FAIL][2] ([Intel XE#6520])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/bat-dg2-oem2/igt@xe_waitfence@reltime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/bat-dg2-oem2/igt@xe_waitfence@reltime.html

  
  [Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520


Build changes
-------------

  * Linux: xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13 -> xe-pw-161606v2

  IGT_8764: 8764
  xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13: 5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13
  xe-pw-161606v2: 161606v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/index.html

[-- Attachment #2: Type: text/html, Size: 1975 bytes --]

✗ Xe.CI.FULL: failure for Workaround cleanup & simplification (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 31679 bytes --]

== Series Details ==

Series: Workaround cleanup & simplification (rev2)
URL   : https://patchwork.freedesktop.org/series/161606/
State : failure

== Summary ==

CI Bug Log - changes from xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13_FULL -> xe-pw-161606v2_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-161606v2_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-161606v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-161606v2_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-dp-2:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-dp-2.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][2] -> [FAIL][3]
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-9/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  
New tests
---------

  New tests have been introduced between xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13_FULL and xe-pw-161606v2_FULL:

### New IGT tests (90) ###

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-aux-stride-y-tiled-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-pixel-format-y-tiled-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-rotation-90-y-tiled-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@bad-rotation-90-yf-tiled-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-basic-y-tiled-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-basic-yf-tiled-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@random-ccs-data-y-tiled-ccs:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@random-ccs-data-yf-tiled-ccs:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in xe-pw-161606v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#7059])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2327])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#1124]) +2 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2314] / [Intel XE#2894])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs (NEW):
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2887]) +4 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][9] -> [INCOMPLETE][10] ([Intel XE#7084])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-b-dp-1:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2652]) +3 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-b-dp-1.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2325])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2252])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html

  * igt@kms_color_pipeline@plane-lut3d-green-only@pipe-c-dp-1:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#6969]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-5/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-c-dp-1.html

  * igt@kms_color_pipeline@plane-lut3d-green-only@pipe-d-dp-1:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#6969] / [Intel XE#7006])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-5/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-d-dp-1.html

  * igt@kms_content_protection@uevent@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][16] ([Intel XE#6707])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-2/igt@kms_content_protection@uevent@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-onscreen-max-size:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2320]) +2 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_cursor_crc@cursor-onscreen-max-size.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#1424])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#309])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-dp2-hdmi-a3:
    - shard-bmg:          [PASS][20] -> [FAIL][21] ([Intel XE#6266]) +1 other test fail
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-dp2-hdmi-a3.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-8/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-dp2-hdmi-a3.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-bmg:          [PASS][22] -> [INCOMPLETE][23] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-3/igt@kms_flip@flip-vs-suspend.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-4/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#4141]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2311]) +8 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-msflip-blt.html
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#656])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#7061])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2313]) +8 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][29] -> [SKIP][30] ([Intel XE#1503])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-8/igt@kms_hdr@invalid-hdr.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-9/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#4090])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#7283])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2763] / [Intel XE#6886]) +4 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#1406] / [Intel XE#2893] / [Intel XE#4608])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#1406] / [Intel XE#4608]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@psr2-primary-page-flip:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_psr@psr2-primary-page-flip.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#2426])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [PASS][40] -> [FAIL][41] ([Intel XE#4459]) +1 other test fail
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-lnl-6/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-4/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@xe_eudebug@vm-bind-clear:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#4837]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@xe_eudebug@vm-bind-clear.html

  * igt@xe_eudebug_online@breakpoint-not-in-debug-mode:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#4837] / [Intel XE#6665]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@xe_eudebug_online@breakpoint-not-in-debug-mode.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#2322]) +2 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm:
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#7136])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm.html
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#7136]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-8/igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-close-fd:
    - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#6874])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@xe_exec_multi_queue@many-queues-preempt-mode-close-fd.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-priority-smem:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#6874]) +13 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@xe_exec_multi_queue@many-queues-preempt-mode-priority-smem.html

  * igt@xe_exec_threads@threads-multi-queue-cm-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#7138])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@xe_exec_threads@threads-multi-queue-cm-userptr-invalidate-race.html

  * igt@xe_pm@d3cold-mocs:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#2284])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@xe_pm@d3cold-mocs.html

  
#### Possible fixes ####

  * igt@kms_bw@linear-tiling-1-displays-2560x1440p:
    - shard-bmg:          [SKIP][51] ([Intel XE#367]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-2/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-5/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [FAIL][53] -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][55] ([Intel XE#6321]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-8/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-5/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create:
    - shard-lnl:          [ABORT][57] -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-lnl-4/igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create.html

  * igt@xe_fault_injection@vm-create-fail-xe_exec_queue_create_bind:
    - shard-bmg:          [ABORT][59] -> [PASS][60] +1 other test pass
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-7/igt@xe_fault_injection@vm-create-fail-xe_exec_queue_create_bind.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@xe_fault_injection@vm-create-fail-xe_exec_queue_create_bind.html

  
#### Warnings ####

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][61] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][62] ([Intel XE#3544])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-8/igt@kms_hdr@brightness-with-hdr.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-9/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][63] ([Intel XE#2509]) -> [SKIP][64] ([Intel XE#2426])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-bmg:          [ABORT][65] ([Intel XE#5466]) -> [ABORT][66] ([Intel XE#5466] / [Intel XE#6652])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-9/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-7/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4090]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4090
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
  [Intel XE#7006]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7006
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283


Build changes
-------------

  * Linux: xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13 -> xe-pw-161606v2

  IGT_8764: 8764
  xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13: 5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13
  xe-pw-161606v2: 161606v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/index.html

[-- Attachment #2: Type: text/html, Size: 36826 bytes --]

Re: [PATCH v2 01/23] drm/xe/mtl: Drop pre-prod workarounds Wa_14015795083 & Wa_14014475959

[Vivekanandan, Balasubramani]

On 20.02.2026 09:27, Matt Roper wrote:
> Wa_14015795083 and Wa_14014475959 only apply to early steppings of
> Xe_LPG that appeared only in pre-production hardware (in fact
> Wa_14014475959 wasn't supposed to apply to _any_ steppings of version
> 12.71).  Xe1 platforms already aren't officially supported by the Xe
> driver, but pre-production steppings are especially out of scope (and
> 'has_pre_prod_wa' is not set in the device descriptor).  Drop both
> workarounds.
> 
> Bspec: 55420
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_wa.c         | 4 ----
>  drivers/gpu/drm/xe/xe_wa_oob.rules | 3 +--
>  2 files changed, 1 insertion(+), 6 deletions(-)

LGTM,

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Regards,
Bala

> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 76fa6d510aadb91169170ba35f65390c477a569e..aa5755bcdc04a3ec2569ab9676a9dd95516f1711 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -191,10 +191,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  
>  	/* Xe_LPG */
>  
> -	{ XE_RTP_NAME("14015795083"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)),
> -	  XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
> -	},
>  	{ XE_RTP_NAME("14018575942"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
>  	  XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index ac08f94f90a142629545c4964ca0fd3f9cad6aa9..cc988f2a18d33365dc09d32f4e85ced01b823877 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -2,8 +2,7 @@
>  16010904313	GRAPHICS_VERSION_RANGE(1200, 1210)
>  18022495364	GRAPHICS_VERSION_RANGE(1200, 1210)
>  22012773006	GRAPHICS_VERSION_RANGE(1200, 1250)
> -14014475959	GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)
> -		PLATFORM(DG2)
> +14014475959	PLATFORM(DG2)
>  22011391025	PLATFORM(DG2)
>  22012727170	SUBPLATFORM(DG2, G11)
>  22012727685	SUBPLATFORM(DG2, G11)
> 
> -- 
> 2.53.0
> 

Re: [PATCH v2 02/23] drm/xe/pvc: Drop pre-prod workarounds

[Vivekanandan, Balasubramani]

On 20.02.2026 09:27, Matt Roper wrote:
> Production PVC hardware had a graphics stepping of C0.  Xe1 platforms
> already aren't officially supported by the Xe driver, but pre-production
> steppings are especially out of scope (and 'has_pre_prod_wa' is not set
> in the device descriptor).  Drop the workarounds that aren't relevant to
> production hardware.
> 
> v2:
>  - Drop the stream->override_gucrc which is no longer set anywhere after
>    the removal of Wa_1509372804.  (Bala)
>  - Drop xe_guc_rc_set_mode / xe_guc_rc_unset_mode which are no longer
>    used after the removal of Wa_1509372804.
> 
> Bspec: 44484
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc.c        |  3 ---
>  drivers/gpu/drm/xe/xe_guc_rc.c     | 29 -----------------------------
>  drivers/gpu/drm/xe/xe_guc_rc.h     |  2 --
>  drivers/gpu/drm/xe/xe_oa.c         | 19 -------------------
>  drivers/gpu/drm/xe/xe_oa_types.h   |  3 ---
>  drivers/gpu/drm/xe/xe_wa.c         |  5 -----
>  drivers/gpu/drm/xe/xe_wa_oob.rules |  2 --
>  7 files changed, 63 deletions(-)

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> 

Regards,
Bala

> 
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index cbbb4d665b8fe66105727e83cfc59a13624d259e..54d2fc780127742e2e152da438c7d3e8332f3cbc 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -213,9 +213,6 @@ static u32 guc_ctl_wa_flags(struct xe_guc *guc)
>  	    !xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER))
>  		flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
>  
> -	if (XE_GT_WA(gt, 1509372804))
> -		flags |= GUC_WA_RENDER_RST_RC6_EXIT;
> -
>  	if (XE_GT_WA(gt, 14018913170))
>  		flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6;
>  
> diff --git a/drivers/gpu/drm/xe/xe_guc_rc.c b/drivers/gpu/drm/xe/xe_guc_rc.c
> index 427a889b2a1e04b1d01bd7db8add20ce41f60ce5..99fa127b261ffb0fe7bdae5fcbc78258f67529a8 100644
> --- a/drivers/gpu/drm/xe/xe_guc_rc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_rc.c
> @@ -129,32 +129,3 @@ int xe_guc_rc_enable(struct xe_guc *guc)
>  
>  	return guc_action_setup_gucrc(guc, GUCRC_FIRMWARE_CONTROL);
>  }
> -
> -/**
> - * xe_guc_rc_set_mode() - set new GUCRC mode
> - * @guc: Xe GuC instance
> - * @mode: new value of the mode.
> - *
> - * Function to set GuC RC mode to one of the enum values.
> - *
> - * Returns: 0 on success, negative error code on error
> - */
> -int xe_guc_rc_set_mode(struct xe_guc *guc, enum slpc_gucrc_mode mode)
> -{
> -	guard(xe_pm_runtime_noresume)(guc_to_xe(guc));
> -	return xe_guc_pc_action_set_param(&guc->pc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
> -}
> -
> -/**
> - * xe_guc_rc_unset_mode() - revert to default mode
> - * @guc: Xe GuC instance
> - *
> - * Function to revert GuC RC mode to platform defaults.
> - *
> - * Returns: 0 on success, negative error code on error
> - */
> -int xe_guc_rc_unset_mode(struct xe_guc *guc)
> -{
> -	guard(xe_pm_runtime_noresume)(guc_to_xe(guc));
> -	return xe_guc_pc_action_unset_param(&guc->pc, SLPC_PARAM_PWRGATE_RC_MODE);
> -}
> diff --git a/drivers/gpu/drm/xe/xe_guc_rc.h b/drivers/gpu/drm/xe/xe_guc_rc.h
> index f1f949e7ecc0c6afab3eaeb616fe49d0437d710c..b083fc364dd430e5868a4e6da62b5777f5a6f1e1 100644
> --- a/drivers/gpu/drm/xe/xe_guc_rc.h
> +++ b/drivers/gpu/drm/xe/xe_guc_rc.h
> @@ -12,7 +12,5 @@ enum slpc_gucrc_mode;
>  int xe_guc_rc_init(struct xe_guc *guc);
>  int xe_guc_rc_enable(struct xe_guc *guc);
>  void xe_guc_rc_disable(struct xe_guc *guc);
> -int xe_guc_rc_set_mode(struct xe_guc *guc, enum slpc_gucrc_mode mode);
> -int xe_guc_rc_unset_mode(struct xe_guc *guc);
>  
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
> index a462d6983d8d6daf74beaf6fef5bfe2ab779179d..72fc4424017bf8fb7a42e3a3ae3f6adfe91cf21d 100644
> --- a/drivers/gpu/drm/xe/xe_oa.c
> +++ b/drivers/gpu/drm/xe/xe_oa.c
> @@ -873,10 +873,6 @@ static void xe_oa_stream_destroy(struct xe_oa_stream *stream)
>  	xe_force_wake_put(gt_to_fw(gt), stream->fw_ref);
>  	xe_pm_runtime_put(stream->oa->xe);
>  
> -	/* Wa_1509372804:pvc: Unset the override of GUCRC mode to enable rc6 */
> -	if (stream->override_gucrc)
> -		xe_gt_WARN_ON(gt, xe_guc_rc_unset_mode(&gt->uc.guc));
> -
>  	xe_oa_free_configs(stream);
>  	xe_file_put(stream->xef);
>  }
> @@ -1760,18 +1756,6 @@ static int xe_oa_stream_init(struct xe_oa_stream *stream,
>  		goto exit;
>  	}
>  
> -	/*
> -	 * GuC reset of engines causes OA to lose configuration
> -	 * state. Prevent this by overriding GUCRC mode.
> -	 */
> -	if (XE_GT_WA(stream->gt, 1509372804)) {
> -		ret = xe_guc_rc_set_mode(&gt->uc.guc, SLPC_GUCRC_MODE_GUCRC_NO_RC6);
> -		if (ret)
> -			goto err_free_configs;
> -
> -		stream->override_gucrc = true;
> -	}
> -
>  	/* Take runtime pm ref and forcewake to disable RC6 */
>  	xe_pm_runtime_get(stream->oa->xe);
>  	stream->fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
> @@ -1822,9 +1806,6 @@ static int xe_oa_stream_init(struct xe_oa_stream *stream,
>  err_fw_put:
>  	xe_force_wake_put(gt_to_fw(gt), stream->fw_ref);
>  	xe_pm_runtime_put(stream->oa->xe);
> -	if (stream->override_gucrc)
> -		xe_gt_WARN_ON(gt, xe_guc_rc_unset_mode(&gt->uc.guc));
> -err_free_configs:
>  	xe_oa_free_configs(stream);
>  exit:
>  	xe_file_put(stream->xef);
> diff --git a/drivers/gpu/drm/xe/xe_oa_types.h b/drivers/gpu/drm/xe/xe_oa_types.h
> index 08cc8d7c221582662abff9397e27fbb8ccca468a..b03ffd513483449adc6b2937c0707e5bfc619a5b 100644
> --- a/drivers/gpu/drm/xe/xe_oa_types.h
> +++ b/drivers/gpu/drm/xe/xe_oa_types.h
> @@ -239,9 +239,6 @@ struct xe_oa_stream {
>  	/** @poll_period_ns: hrtimer period for checking OA buffer for available data */
>  	u64 poll_period_ns;
>  
> -	/** @override_gucrc: GuC RC has been overridden for the OA stream */
> -	bool override_gucrc;
> -
>  	/** @oa_status: temporary storage for oa_status register value */
>  	u32 oa_status;
>  
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index aa5755bcdc04a3ec2569ab9676a9dd95516f1711..4b2c77f51fd830fe2439708865fb0b966545bc71 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -499,11 +499,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       ENGINE_CLASS(COMPUTE)),
>  	  XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0))
>  	},
> -	{ XE_RTP_NAME("14014999345"),
> -	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE),
> -		       GRAPHICS_STEP(B0, C0)),
> -	  XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
> -	},
>  
>  	/* Xe_LPG */
>  
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index cc988f2a18d33365dc09d32f4e85ced01b823877..c3222d9504889b5175fdfa73db0bf4e9910a277d 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -8,7 +8,6 @@
>  22012727685	SUBPLATFORM(DG2, G11)
>  22016596838	PLATFORM(PVC)
>  18020744125	PLATFORM(PVC)
> -1509372804	PLATFORM(PVC), GRAPHICS_STEP(A0, C0)
>  1409600907	GRAPHICS_VERSION_RANGE(1200, 1250)
>  22014953428	SUBPLATFORM(DG2, G10)
>  		SUBPLATFORM(DG2, G12)
> @@ -53,7 +52,6 @@
>  18013179988	GRAPHICS_VERSION(1255)
>  		GRAPHICS_VERSION_RANGE(1270, 1274)
>  1508761755	GRAPHICS_VERSION(1255)
> -		GRAPHICS_VERSION(1260), GRAPHICS_STEP(A0, B0)
>  16023105232	GRAPHICS_VERSION_RANGE(2001, 3001)
>  		MEDIA_VERSION_RANGE(1301, 3000)
>  		MEDIA_VERSION(3002)
> 
> -- 
> 2.53.0
> 

Re: [PATCH v2 04/23] drm/xe: Consolidate workaround entries for Wa_16021867713

[Vivekanandan, Balasubramani]

On 20.02.2026 09:27, Matt Roper wrote:
> Wa_16021867713 applies to every single media IP from 13.00 to 30.02
> (inclusive).  We can consolidate the multiple per-version entries down
> to a single range entry.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_wa.c | 38 ++++++++------------------------------
>  1 file changed, 8 insertions(+), 30 deletions(-)

LGTM.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> 

Regards,
Bala

> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index c3d694947bd5d2b178e9da08bb937dc6a171b326..4a8685f2ea985cb67b21bdf8a043ad1dfdfc816d 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -131,6 +131,8 @@ __diag_push();
>  __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
>  
>  static const struct xe_rtp_entry_sr gt_was[] = {
> +	/* Workarounds applying over a range of IPs */
> +
>  	{ XE_RTP_NAME("14011060649"),
>  	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
>  		       ENGINE_CLASS(VIDEO_DECODE),
> @@ -146,6 +148,12 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),
>  	  XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
>  	},
> +	{ XE_RTP_NAME("16021867713"),
> +	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1300, 3002),
> +		       ENGINE_CLASS(VIDEO_DECODE)),
> +	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
> +	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> +	},
>  
>  	/* DG1 */
>  
> @@ -213,12 +221,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  
>  	/* Xe_LPM+ */
>  
> -	{ XE_RTP_NAME("16021867713"),
> -	  XE_RTP_RULES(MEDIA_VERSION(1300),
> -		       ENGINE_CLASS(VIDEO_DECODE)),
> -	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
> -	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> -	},
>  	{ XE_RTP_NAME("22016670082"),
>  	  XE_RTP_RULES(MEDIA_VERSION(1300)),
>  	  XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
> @@ -232,12 +234,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
>  	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
>  	},
> -	{ XE_RTP_NAME("16021867713"),
> -	  XE_RTP_RULES(MEDIA_VERSION(2000),
> -		       ENGINE_CLASS(VIDEO_DECODE)),
> -	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
> -	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> -	},
>  	{ XE_RTP_NAME("14019449301"),
>  	  XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),
>  	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
> @@ -262,12 +258,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  
>  	/* Xe2_HPM */
>  
> -	{ XE_RTP_NAME("16021867713"),
> -	  XE_RTP_RULES(MEDIA_VERSION(1301),
> -		       ENGINE_CLASS(VIDEO_DECODE)),
> -	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
> -	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> -	},
>  	{ XE_RTP_NAME("14019449301"),
>  	  XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
>  	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
> @@ -291,12 +281,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  
>  	/* Xe3_LPM */
>  
> -	{ XE_RTP_NAME("16021867713"),
> -	  XE_RTP_RULES(MEDIA_VERSION(3000),
> -		       ENGINE_CLASS(VIDEO_DECODE)),
> -	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
> -	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> -	},
>  	{ XE_RTP_NAME("16021865536"),
>  	  XE_RTP_RULES(MEDIA_VERSION(3000),
>  		       ENGINE_CLASS(VIDEO_DECODE)),
> @@ -309,12 +293,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
>  	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
>  	},
> -	{ XE_RTP_NAME("16021867713"),
> -	  XE_RTP_RULES(MEDIA_VERSION(3002),
> -		       ENGINE_CLASS(VIDEO_DECODE)),
> -	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
> -	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> -	},
>  	{ XE_RTP_NAME("14021486841"),
>  	  XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),
>  		       ENGINE_CLASS(VIDEO_DECODE)),
> 
> -- 
> 2.53.0
> 

Re: [PATCH v2 05/23] drm/xe: Consolidate workaround entries for Wa_14019449301

[Vivekanandan, Balasubramani]

On 20.02.2026 09:27, Matt Roper wrote:
> Wa_14019449301 applies to both media IP 13.01 and 20.00 and none of the
> version numbers between those are used.  Conslidate the two entries into
> a single range entry.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_wa.c | 15 +++++----------
>  1 file changed, 5 insertions(+), 10 deletions(-)

LGTM.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> 

Regards,
Bala

> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 4a8685f2ea985cb67b21bdf8a043ad1dfdfc816d..33e7e33db83175953361ee13dd40af8954c6d838 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -154,6 +154,11 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
>  	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
>  	},
> +	{ XE_RTP_NAME("14019449301"),
> +	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 2000), ENGINE_CLASS(VIDEO_DECODE)),
> +	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
> +	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> +	},
>  
>  	/* DG1 */
>  
> @@ -234,11 +239,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
>  	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
>  	},
> -	{ XE_RTP_NAME("14019449301"),
> -	  XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),
> -	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
> -	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> -	},
>  	{ XE_RTP_NAME("16028005424"),
>  	  XE_RTP_RULES(MEDIA_VERSION(2000)),
>  	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
> @@ -258,11 +258,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  
>  	/* Xe2_HPM */
>  
> -	{ XE_RTP_NAME("14019449301"),
> -	  XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
> -	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
> -	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> -	},
>  	{ XE_RTP_NAME("16028005424"),
>  	  XE_RTP_RULES(MEDIA_VERSION(1301)),
>  	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
> 
> -- 
> 2.53.0
> 

Re: [PATCH v2 06/23] drm/xe: Consolidate workaround entries for Wa_16028005424

[Vivekanandan, Balasubramani]

On 20.02.2026 09:27, Matt Roper wrote:
> Wa_16028005424 applies to all media IPs from 13.01 to 35.00 (inclusive)
> and all graphics IPs from 30.00 and 30.05 (inclusive).  Conslidate the
> multiple RTP entries into a single range-based entry.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_wa.c | 31 +++++--------------------------
>  1 file changed, 5 insertions(+), 26 deletions(-)

LGTM.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> 

Regards,
Bala

> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 33e7e33db83175953361ee13dd40af8954c6d838..4009323da8021cf5791a96e119b7b71b64eb4431 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -159,6 +159,11 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
>  	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
>  	},
> +	{ XE_RTP_NAME("16028005424"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), OR,
> +		       MEDIA_VERSION_RANGE(1301, 3500)),
> +	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
> +	},
>  
>  	/* DG1 */
>  
> @@ -239,10 +244,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
>  	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
>  	},
> -	{ XE_RTP_NAME("16028005424"),
> -	  XE_RTP_RULES(MEDIA_VERSION(2000)),
> -	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
> -	},
>  
>  	/* Xe2_HPG */
>  
> @@ -256,23 +257,12 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  			     LSN_DIM_Z_WGT(1)))
>  	},
>  
> -	/* Xe2_HPM */
> -
> -	{ XE_RTP_NAME("16028005424"),
> -	  XE_RTP_RULES(MEDIA_VERSION(1301)),
> -	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
> -	},
> -
>  	/* Xe3_LPG */
>  
>  	{ XE_RTP_NAME("14021871409"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)),
>  	  XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS))
>  	},
> -	{ XE_RTP_NAME("16028005424"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005)),
> -	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
> -	},
>  
>  	/* Xe3_LPM */
>  
> @@ -294,17 +284,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)),
>  	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
>  	},
> -	{ XE_RTP_NAME("16028005424"),
> -	  XE_RTP_RULES(MEDIA_VERSION_RANGE(3000, 3002)),
> -	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
> -	},
> -
> -	/* Xe3p_LPM */
> -
> -	{ XE_RTP_NAME("16028005424"),
> -	  XE_RTP_RULES(MEDIA_VERSION(3500)),
> -	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
> -	},
>  
>  	/* Xe3P_LPG */
>  
> 
> -- 
> 2.53.0
> 

Re: [PATCH v2 07/23] drm/xe: Consolidate workaround entries for Wa_16021865536

[Vivekanandan, Balasubramani]

On 20.02.2026 09:27, Matt Roper wrote:
> Wa_16021865536 applies to both media versions 30.00 and 30.02; since
> version 30.01 is currently unused we can consolidate the two RTP entries
> into a single range-based entry.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_wa.c | 8 +-------
>  1 file changed, 1 insertion(+), 7 deletions(-)

LGTM.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> 

Regards,
Bala

> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 4009323da8021cf5791a96e119b7b71b64eb4431..092d46f48165d17b0ab4bf2a7e4550b97e137aad 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -267,13 +267,7 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	/* Xe3_LPM */
>  
>  	{ XE_RTP_NAME("16021865536"),
> -	  XE_RTP_RULES(MEDIA_VERSION(3000),
> -		       ENGINE_CLASS(VIDEO_DECODE)),
> -	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
> -	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> -	},
> -	{ XE_RTP_NAME("16021865536"),
> -	  XE_RTP_RULES(MEDIA_VERSION(3002),
> +	  XE_RTP_RULES(MEDIA_VERSION_RANGE(3000, 3002),
>  		       ENGINE_CLASS(VIDEO_DECODE)),
>  	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
>  	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> 
> -- 
> 2.53.0
> 

Re: [PATCH v2 08/23] drm/xe: Consolidate workaround entries for Wa_18032247524

[Vivekanandan, Balasubramani]

On 20.02.2026 09:27, Matt Roper wrote:
> Wa_18032247524 applies to all graphics versions from 20.01 through 20.04
> (inclusive).  Consolidate the two RTP entries into a single range-based
> entry.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_wa.c | 17 +++++++----------
>  1 file changed, 7 insertions(+), 10 deletions(-)

LGTM.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> 

Regards,
Bala

> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 092d46f48165d17b0ab4bf2a7e4550b97e137aad..a483a76c7665eba1c6a87a18bab1a31d11a01f4d 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -306,6 +306,8 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  };
>  
>  static const struct xe_rtp_entry_sr engine_was[] = {
> +	/* Workarounds applying over a range of IPs */
> +
>  	{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
> @@ -341,6 +343,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  	  XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),
>  			     FFSC_PERCTX_PREEMPT_CTRL))
>  	},
> +	{ XE_RTP_NAME("18032247524"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
> +		       FUNC(xe_rtp_match_first_render_or_compute)),
> +	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
> +	},
>  
>  	/* TGL */
>  
> @@ -478,11 +485,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  
>  	/* Xe2_LPG */
>  
> -	{ XE_RTP_NAME("18032247524"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> -		       FUNC(xe_rtp_match_first_render_or_compute)),
> -	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
> -	},
>  	{ XE_RTP_NAME("16018712365"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
> @@ -551,11 +553,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
>  	},
> -	{ XE_RTP_NAME("18032247524"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> -		       FUNC(xe_rtp_match_first_render_or_compute)),
> -	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
> -	},
>  	{ XE_RTP_NAME("14018471104"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
> 
> -- 
> 2.53.0
> 

Re: [PATCH v2 09/23] drm/xe: Consolidate workaround entries for Wa_16018712365

[Vivekanandan, Balasubramani]

On 20.02.2026 09:27, Matt Roper wrote:
> Wa_16018712365 applies to all graphics versions from 20.01 through 20.04
> (inclusive).  Consolidate the two RTP entries into a single range-based
> entry.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_wa.c | 14 +++++---------
>  1 file changed, 5 insertions(+), 9 deletions(-)

LGTM.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Regards,
Bala 
> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index a483a76c7665eba1c6a87a18bab1a31d11a01f4d..f99f1fbe3aee016d8a8aa19d62f6fd503e6e19f2 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -348,6 +348,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
>  	},
> +	{ XE_RTP_NAME("16018712365"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
> +		       FUNC(xe_rtp_match_first_render_or_compute)),
> +	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
> +	},
>  
>  	/* TGL */
>  
> @@ -485,10 +490,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  
>  	/* Xe2_LPG */
>  
> -	{ XE_RTP_NAME("16018712365"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
> -	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
> -	},
>  	{ XE_RTP_NAME("14020338487"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
> @@ -538,11 +539,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  
>  	/* Xe2_HPG */
>  
> -	{ XE_RTP_NAME("16018712365"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> -		       FUNC(xe_rtp_match_first_render_or_compute)),
> -	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
> -	},
>  	{ XE_RTP_NAME("16018737384"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2999),
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
> 
> -- 
> 2.53.0
> 

Re: [PATCH v2 10/23] drm/xe: Consolidate workaround entries for Wa_14020338487

[Vivekanandan, Balasubramani]

On 20.02.2026 09:27, Matt Roper wrote:
> Wa_14020338487 applies to all graphics versions from 20.01 through 20.04
> (inclusive).  Consolidate the two RTP entries into a single range-based
> entry.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_wa.c | 14 +++++---------
>  1 file changed, 5 insertions(+), 9 deletions(-)

LGTM.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Regards,
Bala 

> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index f99f1fbe3aee016d8a8aa19d62f6fd503e6e19f2..4809166ba8ec69fc913fe2ca0103fe54e345dd14 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -353,6 +353,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
>  	},
> +	{ XE_RTP_NAME("14020338487"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
> +		       FUNC(xe_rtp_match_first_render_or_compute)),
> +	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
> +	},
>  
>  	/* TGL */
>  
> @@ -490,10 +495,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  
>  	/* Xe2_LPG */
>  
> -	{ XE_RTP_NAME("14020338487"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
> -	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
> -	},
>  	{ XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
> @@ -544,11 +545,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
>  	},
> -	{ XE_RTP_NAME("14020338487"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> -		       FUNC(xe_rtp_match_first_render_or_compute)),
> -	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
> -	},
>  	{ XE_RTP_NAME("14018471104"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
> 
> -- 
> 2.53.0
> 

Re: [PATCH v2 11/23] drm/xe: Consolidate workaround entries for Wa_14018471104

[Vivekanandan, Balasubramani]

On 20.02.2026 09:27, Matt Roper wrote:
> Wa_14018471104 applies to all graphics versions from 20.01 through 20.04
> (inclusive).  Consolidate the two RTP entries into a single range-based
> entry.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_wa.c | 14 +++++---------
>  1 file changed, 5 insertions(+), 9 deletions(-)

LGTM.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Regards,
Bala 

> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 4809166ba8ec69fc913fe2ca0103fe54e345dd14..9119ca9ba1031d9180b44c13a702e1bb04fd0ca6 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -358,6 +358,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
>  	},
> +	{ XE_RTP_NAME("14018471104"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
> +		       FUNC(xe_rtp_match_first_render_or_compute)),
> +	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
> +	},
>  
>  	/* TGL */
>  
> @@ -500,10 +505,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
>  	},
> -	{ XE_RTP_NAME("14018471104"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
> -	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
> -	},
>  	/*
>  	 * These two workarounds are the same, just applying to different
>  	 * engines.  Although Wa_18032095049 (for the RCS) isn't required on
> @@ -545,11 +546,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
>  	},
> -	{ XE_RTP_NAME("14018471104"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> -		       FUNC(xe_rtp_match_first_render_or_compute)),
> -	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
> -	},
>  	/*
>  	 * Although this workaround isn't required for the RCS, disabling these
>  	 * reports has no impact for our driver or the GuC, so we go ahead and
> 
> -- 
> 2.53.0
> 

Re: [PATCH v2 12/23] drm/xe: Consolidate workaround entries for Wa_16021639441

[Vivekanandan, Balasubramani]

On 20.02.2026 09:27, Matt Roper wrote:
> Wa_16021639441 applies to all graphics versions from 20.01 through 20.04
> (inclusive) and all media versions from 13.01 to 20.00 (inclusive).
> Consolidate the RTP entries into a single range-based entry.
> Also drop the reference to Wa_18032095049 which was only relevant to
> pre-production platforms that we no longer support.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_wa.c | 59 ++++++++++------------------------------------
>  1 file changed, 13 insertions(+), 46 deletions(-)

LGTM.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Regards,
Bala 

> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 9119ca9ba1031d9180b44c13a702e1bb04fd0ca6..f0c42be062146837e6ba40621af54fcafa34f8e8 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -363,6 +363,19 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
>  	},
> +	/*
> +	 * Although this workaround isn't required for the RCS, disabling these
> +	 * reports has no impact for our driver or the GuC, so we go ahead and
> +	 * apply this to all engines for simplicity.
> +	 */
> +	{ XE_RTP_NAME("16021639441"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), OR,
> +		       MEDIA_VERSION_RANGE(1301, 2000)),
> +	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
> +			     GHWSP_CSB_REPORT_DIS |
> +			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
> +			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> +	},
>  
>  	/* TGL */
>  
> @@ -505,20 +518,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
>  	},
> -	/*
> -	 * These two workarounds are the same, just applying to different
> -	 * engines.  Although Wa_18032095049 (for the RCS) isn't required on
> -	 * all steppings, disabling these reports has no impact for our
> -	 * driver or the GuC, so we go ahead and treat it the same as
> -	 * Wa_16021639441 which does apply to all steppings.
> -	 */
> -	{ XE_RTP_NAME("18032095049, 16021639441"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(2004)),
> -	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
> -			     GHWSP_CSB_REPORT_DIS |
> -			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
> -			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> -	},
>  	{ XE_RTP_NAME("16018610683"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
> @@ -546,18 +545,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
>  	},
> -	/*
> -	 * Although this workaround isn't required for the RCS, disabling these
> -	 * reports has no impact for our driver or the GuC, so we go ahead and
> -	 * apply this to all engines for simplicity.
> -	 */
> -	{ XE_RTP_NAME("16021639441"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002)),
> -	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
> -			     GHWSP_CSB_REPORT_DIS |
> -			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
> -			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> -	},
>  	{ XE_RTP_NAME("14019811474"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2001),
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
> @@ -584,26 +571,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
>  	},
>  
> -	/* Xe2_LPM */
> -
> -	{ XE_RTP_NAME("16021639441"),
> -	  XE_RTP_RULES(MEDIA_VERSION(2000)),
> -	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
> -			     GHWSP_CSB_REPORT_DIS |
> -			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
> -			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> -	},
> -
> -	/* Xe2_HPM */
> -
> -	{ XE_RTP_NAME("16021639441"),
> -	  XE_RTP_RULES(MEDIA_VERSION(1301)),
> -	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
> -			     GHWSP_CSB_REPORT_DIS |
> -			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
> -			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> -	},
> -
>  	/* Xe3_LPG */
>  
>  	{ XE_RTP_NAME("14021402888"),
> 
> -- 
> 2.53.0
> 

RE: [PATCH v2 20/23] drm/xe: Consolidate workaround entries for Wa_15016589081

[Lin, Shuicheng]

On Fri, Feb 20, 2026 9:28 AM Matt Roper wrote:
> Wa_15016589081 applies to all graphics versions from 20.01 through 20.04
> (inclusive).  Consolidate the RTP entries into a single range-based entry.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

LGTM.
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_wa.c | 12 ++++--------
>  1 file changed, 4 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index
> 5aa404c0cbfbc8d11c93d820b1a192ab4776def8..fa5dce4ead48bae424a49c
> 62142683dbf1971376 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -653,6 +653,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1,
> DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
>  	},
> +	{ XE_RTP_NAME("15016589081"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
> ENGINE_CLASS(RENDER)),
> +	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1,
> DIS_CLIP_NEGATIVE_BOUNDING_BOX))
> +	},
> 
>  	/* DG1 */
> 
> @@ -728,10 +732,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  			     DIS_PARTIAL_AUTOSTRIP |
>  			     DIS_AUTOSTRIP))
>  	},
> -	{ XE_RTP_NAME("15016589081"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> ENGINE_CLASS(RENDER)),
> -	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1,
> DIS_CLIP_NEGATIVE_BOUNDING_BOX))
> -	},
> 
>  	/* Xe2_HPG */
>  	{ XE_RTP_NAME("15010599737"),
> @@ -751,10 +751,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  			     DIS_PARTIAL_AUTOSTRIP |
>  			     DIS_AUTOSTRIP))
>  	},
> -	{ XE_RTP_NAME("15016589081"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> ENGINE_CLASS(RENDER)),
> -	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1,
> DIS_CLIP_NEGATIVE_BOUNDING_BOX))
> -	},
>  	{ XE_RTP_NAME("22021007897"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4,
> SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
> 
> --
> 2.53.0

RE: [PATCH v2 17/23] drm/xe: Consolidate workaround entries for Wa_14019386621

[Lin, Shuicheng]

On Fri, Feb 20, 2026 9:28 AM Matt Roper wrote:
> Wa_14019386621 applies to all graphics versions from 20.01 through 20.04
> (inclusive).  Consolidate the RTP entries into a single range-based entry.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

LGTM.
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_wa.c | 12 ++++--------
>  1 file changed, 4 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index
> 21af997447e78951dd6d40c87454e8ef69343006..03bef11370ae589d1035
> cf2cb7b022fd173d37b5 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -641,6 +641,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, 2004),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
>  	},
> +	{ XE_RTP_NAME("14019386621"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
> ENGINE_CLASS(RENDER)),
> +	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD,
> XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
> +	},
> 
>  	/* DG1 */
> 
> @@ -697,10 +701,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> 
>  	/* Xe2_LPG */
> 
> -	{ XE_RTP_NAME("14019386621"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> ENGINE_CLASS(RENDER)),
> -	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD,
> XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
> -	},
>  	{ XE_RTP_NAME("14019988906"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
> @@ -738,10 +738,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2001),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1,
> DIS_SF_ROUND_NEAREST_EVEN))
>  	},
> -	{ XE_RTP_NAME("14019386621"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> ENGINE_CLASS(RENDER)),
> -	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD,
> XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
> -	},
>  	{ XE_RTP_NAME("14020756599"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2001),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(WM_CHICKEN3,
> HIZ_PLANE_COMPRESSION_DIS))
> 
> --
> 2.53.0

RE: [PATCH v2 19/23] drm/xe: Consolidate workaround entries for Wa_18033852989

[Lin, Shuicheng]

On Fri, Feb 20, 2026 9:28 AM Matt Roper wrote:
> Wa_18033852989 applies to all graphics versions from 20.01 through 20.04
> (inclusive).  Consolidate the RTP entries into a single range-based entry.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

LGTM.
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_wa.c | 12 ++++--------
>  1 file changed, 4 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index
> 0a0f94ef5c68c2e583f28ab48eb4f96b2896b665..5aa404c0cbfbc8d11c93d8
> 20b1a192ab4776def8 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -649,6 +649,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
>  	},
> +	{ XE_RTP_NAME("18033852989"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
> ENGINE_CLASS(RENDER)),
> +	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1,
> DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
> +	},
> 
>  	/* DG1 */
> 
> @@ -705,10 +709,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> 
>  	/* Xe2_LPG */
> 
> -	{ XE_RTP_NAME("18033852989"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> ENGINE_CLASS(RENDER)),
> -	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1,
> DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
> -	},
>  	{ XE_RTP_NAME("14021567978"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001,
> XE_RTP_END_VERSION_UNDEFINED),
>  		       ENGINE_CLASS(RENDER)),
> @@ -759,10 +759,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4,
> SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
>  	},
> -	{ XE_RTP_NAME("18033852989"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(2001),
> ENGINE_CLASS(RENDER)),
> -	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1,
> DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
> -	},
> 
>  	/* Xe3_LPG */
>  	{ XE_RTP_NAME("14021490052"),
> 
> --
> 2.53.0

RE: [PATCH v2 16/23] drm/xe: Consolidate workaround entries for Wa_14019877138

[Lin, Shuicheng]

On Fri, Feb 20, 2026 9:28 AM Matt Roper wrote:
> Wa_14019877138 applies to all graphics versions from 12.55 through 20.04
> (inclusive) that have a render engine.  Consolidate the RTP entries into a single
> range-based entry.

12.60 is included in this range, which is for PVC that doesn't have render engine.
LGTM.
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>

> 
> Note that the DG2 entry for this workaround was missing an
> ENGINE_CLASS(RENDER) rule; that mistake is fixed by this consolidation.

Should we fix it in the stable kernel also? 
This is a pixel shader related register; the setting should not affect other engines. 
So it seems this mistake should not have side effects. 
Is my understanding correct? 
Thanks.

Shuicheng

> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_wa.c | 20 ++++----------------
>  1 file changed, 4 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index
> 83318a4ebcb51e004497e2cb9460e95691b5d9ff..21af997447e78951dd6d
> 40c87454e8ef69343006 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -637,6 +637,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION(1200)),
>  	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4,
> DISABLE_TDC_LOAD_BALANCING_CALC))
>  	},
> +	{ XE_RTP_NAME("14019877138"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, 2004),
> ENGINE_CLASS(RENDER)),
> +	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
> +	},
> 
>  	/* DG1 */
> 
> @@ -673,10 +677,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  	  XE_RTP_RULES(PLATFORM(DG2)),
>  	  XE_RTP_ACTIONS(SET(CACHE_MODE_1,
> MSAA_OPTIMIZATION_REDUC_DISABLE))
>  	},
> -	{ XE_RTP_NAME("14019877138"),
> -	  XE_RTP_RULES(PLATFORM(DG2)),
> -	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
> -	},
> 
>  	/* PVC */
> 
> @@ -694,10 +694,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
>  	  XE_RTP_ACTIONS(SET(CACHE_MODE_1,
> MSAA_OPTIMIZATION_REDUC_DISABLE))
>  	},
> -	{ XE_RTP_NAME("14019877138"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
> ENGINE_CLASS(RENDER)),
> -	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
> -	},
> 
>  	/* Xe2_LPG */
> 
> @@ -705,10 +701,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD,
> XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
>  	},
> -	{ XE_RTP_NAME("14019877138"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> ENGINE_CLASS(RENDER)),
> -	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
> -	},
>  	{ XE_RTP_NAME("14019988906"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
> @@ -758,10 +750,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
>  	},
> -	{ XE_RTP_NAME("14019877138"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> ENGINE_CLASS(RENDER)),
> -	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
> -	},
>  	{ XE_RTP_NAME("14021490052"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2001),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(FF_MODE,
> 
> --
> 2.53.0

Re: [PATCH v2 16/23] drm/xe: Consolidate workaround entries for Wa_14019877138

[Matt Roper]

On Mon, Feb 23, 2026 at 01:33:37PM -0800, Lin, Shuicheng wrote:
> On Fri, Feb 20, 2026 9:28 AM Matt Roper wrote:
> > Wa_14019877138 applies to all graphics versions from 12.55 through 20.04
> > (inclusive) that have a render engine.  Consolidate the RTP entries into a single
> > range-based entry.
> 
> 12.60 is included in this range, which is for PVC that doesn't have render engine.
> LGTM.
> Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
> 
> > 
> > Note that the DG2 entry for this workaround was missing an
> > ENGINE_CLASS(RENDER) rule; that mistake is fixed by this consolidation.
> 
> Should we fix it in the stable kernel also? 
> This is a pixel shader related register; the setting should not affect other engines. 
> So it seems this mistake should not have side effects. 
> Is my understanding correct? 

Missing the ENGINE_CLASS(RENDER) rule will cause us to emit the register
as part of the LRI setup for the default context on other engines, but
since the register isn't part of those engines' LRCs, when the LRC is
saved out to memory at context switch it won't have any effect on the
context that gets saved.  So it's a bug, but a harmless one.  The
documentation in Documentation/process/stable-kernel-rules.rst indicates
that only important problems should go to the stable kernel, not
theoretical/harmless ones, so this wouldn't qualify.

Also, the Xe driver doesn't officially support DG2 anyway (the support
we have is just for driver developers, and will taint the kernel if an
end user tries to force the driver to load on DG2), so it's especially
not relevant to the stable kernel.


Matt

> Thanks.
> 
> Shuicheng
> 
> > 
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_wa.c | 20 ++++----------------
> >  1 file changed, 4 insertions(+), 16 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index
> > 83318a4ebcb51e004497e2cb9460e95691b5d9ff..21af997447e78951dd6d
> > 40c87454e8ef69343006 100644
> > --- a/drivers/gpu/drm/xe/xe_wa.c
> > +++ b/drivers/gpu/drm/xe/xe_wa.c
> > @@ -637,6 +637,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> >  	  XE_RTP_RULES(GRAPHICS_VERSION(1200)),
> >  	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4,
> > DISABLE_TDC_LOAD_BALANCING_CALC))
> >  	},
> > +	{ XE_RTP_NAME("14019877138"),
> > +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, 2004),
> > ENGINE_CLASS(RENDER)),
> > +	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
> > +	},
> > 
> >  	/* DG1 */
> > 
> > @@ -673,10 +677,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> >  	  XE_RTP_RULES(PLATFORM(DG2)),
> >  	  XE_RTP_ACTIONS(SET(CACHE_MODE_1,
> > MSAA_OPTIMIZATION_REDUC_DISABLE))
> >  	},
> > -	{ XE_RTP_NAME("14019877138"),
> > -	  XE_RTP_RULES(PLATFORM(DG2)),
> > -	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
> > -	},
> > 
> >  	/* PVC */
> > 
> > @@ -694,10 +694,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> >  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
> >  	  XE_RTP_ACTIONS(SET(CACHE_MODE_1,
> > MSAA_OPTIMIZATION_REDUC_DISABLE))
> >  	},
> > -	{ XE_RTP_NAME("14019877138"),
> > -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
> > ENGINE_CLASS(RENDER)),
> > -	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
> > -	},
> > 
> >  	/* Xe2_LPG */
> > 
> > @@ -705,10 +701,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> >  	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> > ENGINE_CLASS(RENDER)),
> >  	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD,
> > XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
> >  	},
> > -	{ XE_RTP_NAME("14019877138"),
> > -	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> > ENGINE_CLASS(RENDER)),
> > -	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
> > -	},
> >  	{ XE_RTP_NAME("14019988906"),
> >  	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> > ENGINE_CLASS(RENDER)),
> >  	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
> > @@ -758,10 +750,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> >  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> > ENGINE_CLASS(RENDER)),
> >  	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
> >  	},
> > -	{ XE_RTP_NAME("14019877138"),
> > -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> > ENGINE_CLASS(RENDER)),
> > -	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
> > -	},
> >  	{ XE_RTP_NAME("14021490052"),
> >  	  XE_RTP_RULES(GRAPHICS_VERSION(2001),
> > ENGINE_CLASS(RENDER)),
> >  	  XE_RTP_ACTIONS(SET(FF_MODE,
> > 
> > --
> > 2.53.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

RE: [PATCH v2 15/23] drm/xe: Consolidate workaround entries for Wa_18041344222

[Lin, Shuicheng]

On Fri, Feb 20, 2026 9:28 AM Matt Roper wrote:
> Wa_18041344222 applies to all graphics versions from 20.01 through 30.00
> (inclusive).  Consolidate the RTP entries into a single range-based entry.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_wa.c | 25 +++++++------------------
>  1 file changed, 7 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index
> 190b31a9d49d33e7fb80174be7ba9cbf726a8224..83318a4ebcb51e004497
> e2cb9460e95691b5d9ff 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -385,6 +385,13 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
>  	},
> +	{ XE_RTP_NAME("18041344222"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3000),
> +		       FUNC(xe_rtp_match_first_render_or_compute),
> +		       FUNC(xe_rtp_match_not_sriov_vf),

I don't see this func in the removed rules. Is it intended? 
If yes, could you explain it in the commit message? 
Thanks.

Shuicheng

> +		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
> +	  XE_RTP_ACTIONS(SET(TDL_CHICKEN,
> EUSTALL_PERF_SAMPLING_DISABLE))
> +	},
> 
>  	/* TGL */
> 
> @@ -531,12 +538,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
>  	},
> -	{ XE_RTP_NAME("18041344222"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> -		       FUNC(xe_rtp_match_first_render_or_compute),
> -		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
> -	  XE_RTP_ACTIONS(SET(TDL_CHICKEN,
> EUSTALL_PERF_SAMPLING_DISABLE))
> -	},
> 
>  	/* Xe2_HPG */
> 
> @@ -555,12 +556,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
>  	},
> -	{ XE_RTP_NAME("18041344222"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> -		       FUNC(xe_rtp_match_first_render_or_compute),
> -		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
> -	  XE_RTP_ACTIONS(SET(TDL_CHICKEN,
> EUSTALL_PERF_SAMPLING_DISABLE))
> -	},
> 
>  	/* Xe3_LPG */
> 
> @@ -588,12 +583,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0),
> RC_SEMA_IDLE_MSG_DISABLE,
>  			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
>  	},
> -	{ XE_RTP_NAME("18041344222"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(3000),
> -		       FUNC(xe_rtp_match_first_render_or_compute),
> -		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
> -	  XE_RTP_ACTIONS(SET(TDL_CHICKEN,
> EUSTALL_PERF_SAMPLING_DISABLE))
> -	},
> 
>  	/* Xe3p_LPG*/
> 
> 
> --
> 2.53.0

Re: [PATCH v2 15/23] drm/xe: Consolidate workaround entries for Wa_18041344222

[Matt Roper]

On Mon, Feb 23, 2026 at 01:47:57PM -0800, Lin, Shuicheng wrote:
> On Fri, Feb 20, 2026 9:28 AM Matt Roper wrote:
> > Wa_18041344222 applies to all graphics versions from 20.01 through 30.00
> > (inclusive).  Consolidate the RTP entries into a single range-based entry.
> > 
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_wa.c | 25 +++++++------------------
> >  1 file changed, 7 insertions(+), 18 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index
> > 190b31a9d49d33e7fb80174be7ba9cbf726a8224..83318a4ebcb51e004497
> > e2cb9460e95691b5d9ff 100644
> > --- a/drivers/gpu/drm/xe/xe_wa.c
> > +++ b/drivers/gpu/drm/xe/xe_wa.c
> > @@ -385,6 +385,13 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> >  		       FUNC(xe_rtp_match_first_render_or_compute)),
> >  	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
> >  	},
> > +	{ XE_RTP_NAME("18041344222"),
> > +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3000),
> > +		       FUNC(xe_rtp_match_first_render_or_compute),
> > +		       FUNC(xe_rtp_match_not_sriov_vf),
> 
> I don't see this func in the removed rules. Is it intended? 
> If yes, could you explain it in the commit message? 
> Thanks.

v2 of this patch got sent just after 0ffe9dcf260b ("drm/xe/xe3: Remove
SRIOV VF check for Wa_18041344222") landed upstream and I missed
adjusting this during the rebase.  I'll drop that line to match the new
upstream code.


Matt

> 
> Shuicheng
> 
> > +		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
> > +	  XE_RTP_ACTIONS(SET(TDL_CHICKEN,
> > EUSTALL_PERF_SAMPLING_DISABLE))
> > +	},
> > 
> >  	/* TGL */
> > 
> > @@ -531,12 +538,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> >  	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> > FUNC(xe_rtp_match_first_render_or_compute)),
> >  	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
> >  	},
> > -	{ XE_RTP_NAME("18041344222"),
> > -	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> > -		       FUNC(xe_rtp_match_first_render_or_compute),
> > -		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
> > -	  XE_RTP_ACTIONS(SET(TDL_CHICKEN,
> > EUSTALL_PERF_SAMPLING_DISABLE))
> > -	},
> > 
> >  	/* Xe2_HPG */
> > 
> > @@ -555,12 +556,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> >  		       FUNC(xe_rtp_match_first_render_or_compute)),
> >  	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
> >  	},
> > -	{ XE_RTP_NAME("18041344222"),
> > -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> > -		       FUNC(xe_rtp_match_first_render_or_compute),
> > -		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
> > -	  XE_RTP_ACTIONS(SET(TDL_CHICKEN,
> > EUSTALL_PERF_SAMPLING_DISABLE))
> > -	},
> > 
> >  	/* Xe3_LPG */
> > 
> > @@ -588,12 +583,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> >  	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0),
> > RC_SEMA_IDLE_MSG_DISABLE,
> >  			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> >  	},
> > -	{ XE_RTP_NAME("18041344222"),
> > -	  XE_RTP_RULES(GRAPHICS_VERSION(3000),
> > -		       FUNC(xe_rtp_match_first_render_or_compute),
> > -		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
> > -	  XE_RTP_ACTIONS(SET(TDL_CHICKEN,
> > EUSTALL_PERF_SAMPLING_DISABLE))
> > -	},
> > 
> >  	/* Xe3p_LPG*/
> > 
> > 
> > --
> > 2.53.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

RE: [PATCH v2 14/23] drm/xe: Consolidate workaround entries for Wa_13012615864

[Lin, Shuicheng]

On Fri, Feb 20, 2026 9:28 AM Matt Roper wrote:
> Wa_13012615864 applies to all graphics versions from 20.01 through 30.05
> (inclusive).  Consolidate the RTP entries into a single range-based entry.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

LGTM.
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_wa.c | 21 +++++----------------
>  1 file changed, 5 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index
> 5d71cb9dca513803274ec1d5b766c2cbb0c31987..190b31a9d49d33e7fb80
> 174be7ba9cbf726a8224 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -380,6 +380,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3005),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
> CLEAR_OPTIMIZATION_DISABLE))
>  	},
> +	{ XE_RTP_NAME("13012615864"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3005),
> +		       FUNC(xe_rtp_match_first_render_or_compute)),
> +	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
> +	},
> 
>  	/* TGL */
> 
> @@ -526,11 +531,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
>  	},
> -	{ XE_RTP_NAME("13012615864"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> -		       FUNC(xe_rtp_match_first_render_or_compute)),
> -	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
> -	},
>  	{ XE_RTP_NAME("18041344222"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
>  		       FUNC(xe_rtp_match_first_render_or_compute),
> @@ -555,11 +555,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
>  	},
> -	{ XE_RTP_NAME("13012615864"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> -		       FUNC(xe_rtp_match_first_render_or_compute)),
> -	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
> -	},
>  	{ XE_RTP_NAME("18041344222"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
>  		       FUNC(xe_rtp_match_first_render_or_compute),
> @@ -587,12 +582,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_CHICKEN,
> QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE))
>  	},
> -	{ XE_RTP_NAME("13012615864"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), OR,
> -		       GRAPHICS_VERSION_RANGE(3003, 3005),
> -		       FUNC(xe_rtp_match_first_render_or_compute)),
> -	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
> -	},
>  	{ XE_RTP_NAME("16023105232"),
>  	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR,
>  		       GRAPHICS_VERSION_RANGE(2001, 3001)),
> 
> --
> 2.53.0

RE: [PATCH v2 18/23] drm/xe: Consolidate workaround entries for Wa_14019988906

[Lin, Shuicheng]

On Fri, Feb 20, 2026 9:28 AM Matt Roper wrote:
> Wa_14019988906 applies to all graphics versions from 20.01 through 20.04
> (inclusive).  Consolidate the RTP entries into a single range-based entry.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

LGTM.
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_wa.c | 12 ++++--------
>  1 file changed, 4 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index
> 03bef11370ae589d1035cf2cb7b022fd173d37b5..0a0f94ef5c68c2e583f28a
> b48eb4f96b2896b665 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -645,6 +645,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD,
> XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
>  	},
> +	{ XE_RTP_NAME("14019988906"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
> ENGINE_CLASS(RENDER)),
> +	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
> +	},
> 
>  	/* DG1 */
> 
> @@ -701,10 +705,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> 
>  	/* Xe2_LPG */
> 
> -	{ XE_RTP_NAME("14019988906"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> ENGINE_CLASS(RENDER)),
> -	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
> -	},
>  	{ XE_RTP_NAME("18033852989"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1,
> DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
> @@ -742,10 +742,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2001),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(WM_CHICKEN3,
> HIZ_PLANE_COMPRESSION_DIS))
>  	},
> -	{ XE_RTP_NAME("14019988906"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> ENGINE_CLASS(RENDER)),
> -	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
> -	},
>  	{ XE_RTP_NAME("14021490052"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2001),
> ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(FF_MODE,
> 
> --
> 2.53.0

RE: [PATCH v2 13/23] drm/xe: Consolidate workaround entries for Wa_14021402888

[Lin, Shuicheng]

On Fri, Feb 20, 2026 9:28 AM Matt Roper wrote:
> Wa_14021402888 applies to all graphics versions from 20.01 through 30.05
> (inclusive).  Consolidate the RTP entries into a single range-based entry.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_wa.c | 21 ++++-----------------
>  1 file changed, 4 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index
> f0c42be062146837e6ba40621af54fcafa34f8e8..5d71cb9dca513803274ec1
> d5b766c2cbb0c31987 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -376,6 +376,10 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
>  			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
>  	},
> +	{ XE_RTP_NAME("14021402888"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3005),
> ENGINE_CLASS(RENDER)),

The rule is changed from " xe_rtp_match_first_render_or_compute" to " ENGINE_CLASS(RENDER)" for 
graphics version 3000 to 3005.
It should have the same result, as these graphics version all have RCS0.

LGTM.
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com> 

> +	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
> CLEAR_OPTIMIZATION_DISABLE))
> +	},
> 
>  	/* TGL */
> 
> @@ -522,10 +526,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
>  	},
> -	{ XE_RTP_NAME("14021402888"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> ENGINE_CLASS(RENDER)),
> -	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
> CLEAR_OPTIMIZATION_DISABLE))
> -	},
>  	{ XE_RTP_NAME("13012615864"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
> @@ -550,10 +550,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0,
> WR_REQ_CHAINING_DIS))
>  	},
> -	{ XE_RTP_NAME("14021402888"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> ENGINE_CLASS(RENDER)),
> -	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
> CLEAR_OPTIMIZATION_DISABLE))
> -	},
>  	{ XE_RTP_NAME("14021821874, 14022954250"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
> @@ -573,11 +569,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> 
>  	/* Xe3_LPG */
> 
> -	{ XE_RTP_NAME("14021402888"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
> -		       FUNC(xe_rtp_match_first_render_or_compute)),
> -	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
> CLEAR_OPTIMIZATION_DISABLE))
> -	},
>  	{ XE_RTP_NAME("18034896535"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0,
> B0),
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
> @@ -608,10 +599,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0),
> RC_SEMA_IDLE_MSG_DISABLE,
>  			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
>  	},
> -	{ XE_RTP_NAME("14021402888"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3003, 3005),
> FUNC(xe_rtp_match_first_render_or_compute)),
> -	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
> CLEAR_OPTIMIZATION_DISABLE))
> -	},
>  	{ XE_RTP_NAME("18041344222"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(3000),
>  		       FUNC(xe_rtp_match_first_render_or_compute),
> 
> --
> 2.53.0

RE: [PATCH v2 16/23] drm/xe: Consolidate workaround entries for Wa_14019877138

[Lin, Shuicheng]

On Mon, Feb 23, 2026 1:41 PM Matt Roper wrote:
> On Mon, Feb 23, 2026 at 01:33:37PM -0800, Lin, Shuicheng wrote:
> > On Fri, Feb 20, 2026 9:28 AM Matt Roper wrote:
> > > Wa_14019877138 applies to all graphics versions from 12.55 through
> > > 20.04
> > > (inclusive) that have a render engine.  Consolidate the RTP entries
> > > into a single range-based entry.
> >
> > 12.60 is included in this range, which is for PVC that doesn't have render
> engine.
> > LGTM.
> > Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
> >
> > >
> > > Note that the DG2 entry for this workaround was missing an
> > > ENGINE_CLASS(RENDER) rule; that mistake is fixed by this consolidation.
> >
> > Should we fix it in the stable kernel also?
> > This is a pixel shader related register; the setting should not affect other
> engines.
> > So it seems this mistake should not have side effects.
> > Is my understanding correct?
> 
> Missing the ENGINE_CLASS(RENDER) rule will cause us to emit the register as
> part of the LRI setup for the default context on other engines, but since the
> register isn't part of those engines' LRCs, when the LRC is saved out to memory
> at context switch it won't have any effect on the context that gets saved.  So
> it's a bug, but a harmless one.  The documentation in
> Documentation/process/stable-kernel-rules.rst indicates that only important
> problems should go to the stable kernel, not theoretical/harmless ones, so this
> wouldn't qualify.
> 
> Also, the Xe driver doesn't officially support DG2 anyway (the support we
> have is just for driver developers, and will taint the kernel if an end user tries to
> force the driver to load on DG2), so it's especially not relevant to the stable
> kernel.

Yes. Got it.
Thanks for the detail explanation.

Shuicheng

> 
> 
> Matt
> 
> > Thanks.
> >
> > Shuicheng
> >
> > >
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> > >  drivers/gpu/drm/xe/xe_wa.c | 20 ++++----------------
> > >  1 file changed, 4 insertions(+), 16 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> > > index
> 83318a4ebcb51e004497e2cb9460e95691b5d9ff..21af997447e78951dd6d
> > > 40c87454e8ef69343006 100644
> > > --- a/drivers/gpu/drm/xe/xe_wa.c
> > > +++ b/drivers/gpu/drm/xe/xe_wa.c
> > > @@ -637,6 +637,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> > >  	  XE_RTP_RULES(GRAPHICS_VERSION(1200)),
> > >  	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4,
> > > DISABLE_TDC_LOAD_BALANCING_CALC))
> > >  	},
> > > +	{ XE_RTP_NAME("14019877138"),
> > > +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, 2004),
> > > ENGINE_CLASS(RENDER)),
> > > +	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
> > > +	},
> > >
> > >  	/* DG1 */
> > >
> > > @@ -673,10 +677,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> > >  	  XE_RTP_RULES(PLATFORM(DG2)),
> > >  	  XE_RTP_ACTIONS(SET(CACHE_MODE_1,
> > > MSAA_OPTIMIZATION_REDUC_DISABLE))
> > >  	},
> > > -	{ XE_RTP_NAME("14019877138"),
> > > -	  XE_RTP_RULES(PLATFORM(DG2)),
> > > -	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
> > > -	},
> > >
> > >  	/* PVC */
> > >
> > > @@ -694,10 +694,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> > >  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
> > >  	  XE_RTP_ACTIONS(SET(CACHE_MODE_1,
> > > MSAA_OPTIMIZATION_REDUC_DISABLE))
> > >  	},
> > > -	{ XE_RTP_NAME("14019877138"),
> > > -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
> > > ENGINE_CLASS(RENDER)),
> > > -	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
> > > -	},
> > >
> > >  	/* Xe2_LPG */
> > >
> > > @@ -705,10 +701,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> > >  	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> > > ENGINE_CLASS(RENDER)),
> > >  	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD,
> > > XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
> > >  	},
> > > -	{ XE_RTP_NAME("14019877138"),
> > > -	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> > > ENGINE_CLASS(RENDER)),
> > > -	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
> > > -	},
> > >  	{ XE_RTP_NAME("14019988906"),
> > >  	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
> > > ENGINE_CLASS(RENDER)),
> > >  	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
> @@
> > > -758,10 +750,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> > >  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> > > ENGINE_CLASS(RENDER)),
> > >  	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
> > >  	},
> > > -	{ XE_RTP_NAME("14019877138"),
> > > -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> > > ENGINE_CLASS(RENDER)),
> > > -	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
> > > -	},
> > >  	{ XE_RTP_NAME("14021490052"),
> > >  	  XE_RTP_RULES(GRAPHICS_VERSION(2001),
> > > ENGINE_CLASS(RENDER)),
> > >  	  XE_RTP_ACTIONS(SET(FF_MODE,
> > >
> > > --
> > > 2.53.0
> >
> 
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

RE: [PATCH v2 22/23] drm/xe/wa_oob: Consolidate some OOB rules

[Lin, Shuicheng]

On Fri, Feb 20, 2026 9:28 AM Matt Roper wrote:
> Given the new policy of allowing graphics/media IP ranges to extend over
> unused IP versions, we can consolidate some of the OOB workaround rules
> and simplify the table.  If new IP variants eventually show up that use these
> unused versions (e.g., media version 30.01, graphics versions
> 20.03 / 30.02, etc.), and if an existing workaround does not extend to that
> new intermediate version, the ranges will be split back apart as part of the
> enablement work for that new IP version.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

LGTM.
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_wa_oob.rules | 31 ++++++++-----------------------
>  1 file changed, 8 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules
> b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index
> c3222d9504889b5175fdfa73db0bf4e9910a277d..80b54b195f20c372a681
> 6ce988b5e7e0b75270c2 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -24,18 +24,9 @@
>  		MEDIA_VERSION(2000)
>  16022287689	GRAPHICS_VERSION(2001)
>  		GRAPHICS_VERSION(2004)
> -13011645652	GRAPHICS_VERSION(2004)
> -		GRAPHICS_VERSION_RANGE(3000, 3001)
> -		GRAPHICS_VERSION(3003)
> -		GRAPHICS_VERSION_RANGE(3004, 3005)
> -14022293748	GRAPHICS_VERSION_RANGE(2001, 2002)
> -		GRAPHICS_VERSION(2004)
> -		GRAPHICS_VERSION_RANGE(3000, 3005)
> -22019794406	GRAPHICS_VERSION_RANGE(2001, 2002)
> -		GRAPHICS_VERSION(2004)
> -		GRAPHICS_VERSION_RANGE(3000, 3001)
> -		GRAPHICS_VERSION(3003)
> -		GRAPHICS_VERSION_RANGE(3004, 3005)
> +13011645652	GRAPHICS_VERSION_RANGE(2004, 3005)
> +14022293748	GRAPHICS_VERSION_RANGE(2001, 3005)
> +22019794406	GRAPHICS_VERSION_RANGE(2001, 3005)
>  22019338487	MEDIA_VERSION(2000)
>  		GRAPHICS_VERSION(2001),
> FUNC(xe_rtp_match_not_sriov_vf)
>  		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),
> FUNC(xe_rtp_match_not_sriov_vf) @@ -52,18 +43,12 @@
>  18013179988	GRAPHICS_VERSION(1255)
>  		GRAPHICS_VERSION_RANGE(1270, 1274)
>  1508761755	GRAPHICS_VERSION(1255)
> -16023105232	GRAPHICS_VERSION_RANGE(2001, 3001)
> -		MEDIA_VERSION_RANGE(1301, 3000)
> -		MEDIA_VERSION(3002)
> -		GRAPHICS_VERSION_RANGE(3003, 3005)
> -16026508708	GRAPHICS_VERSION_RANGE(1200, 3001)
> -		MEDIA_VERSION_RANGE(1300, 3000)
> -		MEDIA_VERSION(3002)
> -		GRAPHICS_VERSION_RANGE(3003, 3005)
> +16023105232	GRAPHICS_VERSION_RANGE(2001, 3005)
> +		MEDIA_VERSION_RANGE(1301, 3002)
> +16026508708	GRAPHICS_VERSION_RANGE(1200, 3005)
> +		MEDIA_VERSION_RANGE(1300, 3002)
>  14020001231	GRAPHICS_VERSION_RANGE(2001,2004),
> FUNC(xe_rtp_match_psmi_enabled)
> -		MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled)
> -		MEDIA_VERSION(3000), FUNC(xe_rtp_match_psmi_enabled)
> -		MEDIA_VERSION(3002), FUNC(xe_rtp_match_psmi_enabled)
> +		MEDIA_VERSION_RANGE(2000, 3002),
> FUNC(xe_rtp_match_psmi_enabled)
>  16023683509	MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled)
>  		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),
> FUNC(xe_rtp_match_psmi_enabled)
> 
> 
> --
> 2.53.0

RE: [PATCH v2 23/23] drm/xe: Consolidate workaround entries for Wa_14023061436

[Lin, Shuicheng]

On Fri, Feb 20, 2026 9:28 AM Matt Roper wrote:
> Wa_14023061436 applies to all graphics versions from 30.00 through 30.05
> (inclusive) since there is currently no IP that uses version 30.02.
> Consolidate the RTP rules into a single range.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

LGTM.
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_wa.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index
> 105ccd8115f09993b7ef82e70cb87d74008f267f..6bee245286abb674cc308
> 9257c979e37ea51760b 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -571,9 +571,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  				   SMP_FORCE_128B_OVERFETCH))
>  	},
>  	{ XE_RTP_NAME("14023061436"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
> -		       FUNC(xe_rtp_match_first_render_or_compute), OR,
> -		       GRAPHICS_VERSION_RANGE(3003, 3005),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005),
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_CHICKEN,
> QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE))
>  	},
> 
> --
> 2.53.0

Re: ✗ Xe.CI.FULL: failure for Workaround cleanup & simplification (rev2)

[Matt Roper]

On Mon, Feb 23, 2026 at 07:23:50AM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: Workaround cleanup & simplification (rev2)
> URL   : https://patchwork.freedesktop.org/series/161606/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13_FULL -> xe-pw-161606v2_FULL
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with xe-pw-161606v2_FULL absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in xe-pw-161606v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (2 -> 2)
> ------------------------------
> 
>   No changes in participating hosts
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in xe-pw-161606v2_FULL:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-dp-2:
>     - shard-bmg:          NOTRUN -> [INCOMPLETE][1]
>    [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-dp-2.html

System never came back from runtime suspend.  Not related to these
workaround changes.

> 
>   * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
>     - shard-bmg:          [PASS][2] -> [FAIL][3]
>    [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
>    [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-9/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/5299


Neither failure is related to this series.  All patches _except_ for:

 - drm/xe: Consolidate workaround entries for Wa_18041344222
 - drm/xe/xe2_hpg: Drop invalid workaround Wa_15010599737

are applied to drm-xe-next.  Thanks Bala and Shuicheng for the reviews.


Matt

> 
>   
> New tests
> ---------
> 
>   New tests have been introduced between xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13_FULL and xe-pw-161606v2_FULL:
> 
> ### New IGT tests (90) ###
> 
>   * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-aux-stride-y-tiled-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs:
>     - Statuses :
>     - Exec time: [None] s
> 
>   * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-pixel-format-y-tiled-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs:
>     - Statuses :
>     - Exec time: [None] s
> 
>   * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-rotation-90-y-tiled-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@bad-rotation-90-yf-tiled-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc:
>     - Statuses :
>     - Exec time: [None] s
> 
>   * igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-basic-y-tiled-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-basic-yf-tiled-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs:
>     - Statuses :
>     - Exec time: [None] s
> 
>   * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs:
>     - Statuses :
>     - Exec time: [None] s
> 
>   * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs:
>     - Statuses :
>     - Exec time: [None] s
> 
>   * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@random-ccs-data-y-tiled-ccs:
>     - Statuses :
>     - Exec time: [None] s
> 
>   * igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs:
>     - Statuses : 1 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   * igt@kms_ccs@random-ccs-data-yf-tiled-ccs:
>     - Statuses : 2 skip(s)
>     - Exec time: [0.0] s
> 
>   
> 
> Known issues
> ------------
> 
>   Here are the changes found in xe-pw-161606v2_FULL that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip:
>     - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#7059])
>    [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html
> 
>   * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
>     - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2327])
>    [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
> 
>   * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
>     - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#1124]) +2 other tests skip
>    [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
> 
>   * igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
>     - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2314] / [Intel XE#2894])
>    [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
> 
>   * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs (NEW):
>     - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2887]) +4 other tests skip
>    [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html
> 
>   * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
>     - shard-bmg:          [PASS][9] -> [INCOMPLETE][10] ([Intel XE#7084])
>    [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
>    [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
> 
>   * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-b-dp-1:
>     - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2652]) +3 other tests skip
>    [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-b-dp-1.html
> 
>   * igt@kms_chamelium_color@ctm-blue-to-red:
>     - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2325])
>    [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_chamelium_color@ctm-blue-to-red.html
> 
>   * igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode:
>     - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2252])
>    [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html
> 
>   * igt@kms_color_pipeline@plane-lut3d-green-only@pipe-c-dp-1:
>     - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#6969]) +1 other test skip
>    [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-5/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-c-dp-1.html
> 
>   * igt@kms_color_pipeline@plane-lut3d-green-only@pipe-d-dp-1:
>     - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#6969] / [Intel XE#7006])
>    [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-5/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-d-dp-1.html
> 
>   * igt@kms_content_protection@uevent@pipe-a-dp-2:
>     - shard-bmg:          NOTRUN -> [FAIL][16] ([Intel XE#6707])
>    [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-2/igt@kms_content_protection@uevent@pipe-a-dp-2.html
> 
>   * igt@kms_cursor_crc@cursor-onscreen-max-size:
>     - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2320]) +2 other tests skip
>    [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_cursor_crc@cursor-onscreen-max-size.html
> 
>   * igt@kms_cursor_crc@cursor-sliding-32x10:
>     - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#1424])
>    [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@kms_cursor_crc@cursor-sliding-32x10.html
> 
>   * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
>     - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#309])
>    [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
> 
>   * igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-dp2-hdmi-a3:
>     - shard-bmg:          [PASS][20] -> [FAIL][21] ([Intel XE#6266]) +1 other test fail
>    [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-dp2-hdmi-a3.html
>    [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-8/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-dp2-hdmi-a3.html
> 
>   * igt@kms_flip@flip-vs-suspend:
>     - shard-bmg:          [PASS][22] -> [INCOMPLETE][23] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
>    [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-3/igt@kms_flip@flip-vs-suspend.html
>    [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-4/igt@kms_flip@flip-vs-suspend.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt:
>     - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#4141]) +3 other tests skip
>    [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt.html
> 
>   * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-msflip-blt:
>     - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2311]) +8 other tests skip
>    [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-msflip-blt.html
>     - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#656])
>    [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-msflip-blt.html
> 
>   * igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-blt:
>     - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#7061])
>    [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-blt.html
> 
>   * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move:
>     - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2313]) +8 other tests skip
>    [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html
> 
>   * igt@kms_hdr@invalid-hdr:
>     - shard-bmg:          [PASS][29] -> [SKIP][30] ([Intel XE#1503])
>    [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-8/igt@kms_hdr@invalid-hdr.html
>    [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-9/igt@kms_hdr@invalid-hdr.html
> 
>   * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
>     - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#4090])
>    [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
> 
>   * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier:
>     - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#7283])
>    [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier.html
> 
>   * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b:
>     - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2763] / [Intel XE#6886]) +4 other tests skip
>    [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html
> 
>   * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf:
>     - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#1406] / [Intel XE#2893] / [Intel XE#4608])
>    [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html
> 
>   * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-a-edp-1:
>     - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#1406] / [Intel XE#4608]) +1 other test skip
>    [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-a-edp-1.html
> 
>   * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
>     - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
>    [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html
> 
>   * igt@kms_psr@psr2-primary-page-flip:
>     - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
>    [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_psr@psr2-primary-page-flip.html
> 
>   * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
>     - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
>    [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
> 
>   * igt@kms_tiled_display@basic-test-pattern:
>     - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#2426])
>    [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html
> 
>   * igt@kms_vrr@cmrr@pipe-a-edp-1:
>     - shard-lnl:          [PASS][40] -> [FAIL][41] ([Intel XE#4459]) +1 other test fail
>    [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-lnl-6/igt@kms_vrr@cmrr@pipe-a-edp-1.html
>    [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-4/igt@kms_vrr@cmrr@pipe-a-edp-1.html
> 
>   * igt@xe_eudebug@vm-bind-clear:
>     - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#4837]) +1 other test skip
>    [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@xe_eudebug@vm-bind-clear.html
> 
>   * igt@xe_eudebug_online@breakpoint-not-in-debug-mode:
>     - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#4837] / [Intel XE#6665]) +1 other test skip
>    [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@xe_eudebug_online@breakpoint-not-in-debug-mode.html
> 
>   * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind:
>     - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#2322]) +2 other tests skip
>    [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind.html
> 
>   * igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm:
>     - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#7136])
>    [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm.html
>     - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#7136]) +2 other tests skip
>    [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-8/igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm.html
> 
>   * igt@xe_exec_multi_queue@many-queues-preempt-mode-close-fd:
>     - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#6874])
>    [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@xe_exec_multi_queue@many-queues-preempt-mode-close-fd.html
> 
>   * igt@xe_exec_multi_queue@many-queues-preempt-mode-priority-smem:
>     - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#6874]) +13 other tests skip
>    [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@xe_exec_multi_queue@many-queues-preempt-mode-priority-smem.html
> 
>   * igt@xe_exec_threads@threads-multi-queue-cm-userptr-invalidate-race:
>     - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#7138])
>    [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@xe_exec_threads@threads-multi-queue-cm-userptr-invalidate-race.html
> 
>   * igt@xe_pm@d3cold-mocs:
>     - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#2284])
>    [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@xe_pm@d3cold-mocs.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@kms_bw@linear-tiling-1-displays-2560x1440p:
>     - shard-bmg:          [SKIP][51] ([Intel XE#367]) -> [PASS][52]
>    [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-2/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
>    [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-5/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
> 
>   * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
>     - shard-bmg:          [FAIL][53] -> [PASS][54]
>    [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
>    [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
> 
>   * igt@xe_evict@evict-beng-mixed-many-threads-small:
>     - shard-bmg:          [INCOMPLETE][55] ([Intel XE#6321]) -> [PASS][56]
>    [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-8/igt@xe_evict@evict-beng-mixed-many-threads-small.html
>    [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-5/igt@xe_evict@evict-beng-mixed-many-threads-small.html
> 
>   * igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create:
>     - shard-lnl:          [ABORT][57] -> [PASS][58]
>    [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-lnl-4/igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create.html
>    [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-lnl-8/igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create.html
> 
>   * igt@xe_fault_injection@vm-create-fail-xe_exec_queue_create_bind:
>     - shard-bmg:          [ABORT][59] -> [PASS][60] +1 other test pass
>    [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-7/igt@xe_fault_injection@vm-create-fail-xe_exec_queue_create_bind.html
>    [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-3/igt@xe_fault_injection@vm-create-fail-xe_exec_queue_create_bind.html
> 
>   
> #### Warnings ####
> 
>   * igt@kms_hdr@brightness-with-hdr:
>     - shard-bmg:          [SKIP][61] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][62] ([Intel XE#3544])
>    [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-8/igt@kms_hdr@brightness-with-hdr.html
>    [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-9/igt@kms_hdr@brightness-with-hdr.html
> 
>   * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
>     - shard-bmg:          [SKIP][63] ([Intel XE#2509]) -> [SKIP][64] ([Intel XE#2426])
>    [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
>    [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
> 
>   * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
>     - shard-bmg:          [ABORT][65] ([Intel XE#5466]) -> [ABORT][66] ([Intel XE#5466] / [Intel XE#6652])
>    [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13/shard-bmg-9/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
>    [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/shard-bmg-7/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
> 
>   
>   [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
>   [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
>   [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
>   [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
>   [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
>   [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
>   [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
>   [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
>   [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
>   [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
>   [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
>   [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
>   [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
>   [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
>   [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
>   [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
>   [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
>   [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
>   [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
>   [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
>   [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
>   [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
>   [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
>   [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
>   [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
>   [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
>   [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
>   [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
>   [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
>   [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
>   [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
>   [Intel XE#4090]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4090
>   [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
>   [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
>   [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
>   [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
>   [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
>   [Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
>   [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
>   [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
>   [Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
>   [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
>   [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
>   [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
>   [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
>   [Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
>   [Intel XE#7006]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7006
>   [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
>   [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
>   [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
>   [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
>   [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
>   [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
> 
> 
> Build changes
> -------------
> 
>   * Linux: xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13 -> xe-pw-161606v2
> 
>   IGT_8764: 8764
>   xe-4582-5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13: 5e550d0427ca648b0bc6fc8fba4e01f47cdb9e13
>   xe-pw-161606v2: 161606v2
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161606v2/index.html

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2 21/23] drm/xe/xe2_hpg: Drop invalid workaround Wa_15010599737

[Vivekanandan, Balasubramani]

On 20.02.2026 09:27, Matt Roper wrote:
> Wa_15010599737 was a workaround originally proposed (and ultimately
> rejected) for DG2-G10.  There's no record of it ever being relevant or
> even considered for any other platforms.
> 
> The specific bit this workaround was setting is documented as "This bit
> should be set to 1 for the DX9 API and 0 for all other APIs" which means
> that it should almost always be left at the default value of 0 on Linux.
> The register itself is directly accessible from userspace, so in the
> special cases where it might be relevant (e.g., Wine/Proton running
> Windows DX9 apps), the userspace drivers already have the ability to
> change the setting without involvement of the kernel.
> 
> Fixes: 7f3ee7d88058 ("drm/xe/xe2hpg: Add initial GT workarounds")
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

LGTM.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Regards,
Bala 

> ---
>  drivers/gpu/drm/xe/xe_wa.c | 5 +----
>  1 file changed, 1 insertion(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index fa5dce4ead48bae424a49c62142683dbf1971376..105ccd8115f09993b7ef82e70cb87d74008f267f 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -734,10 +734,7 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  	},
>  
>  	/* Xe2_HPG */
> -	{ XE_RTP_NAME("15010599737"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
> -	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN))
> -	},
> +
>  	{ XE_RTP_NAME("14020756599"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
> 
> -- 
> 2.53.0
>