* [PATCH v2 1/2] drm/i915/dsb: shift delayed-vblank DSL wait start by one scanline
2026-06-08 12:37 [PATCH v2 0/2] Extend VRR safe window wait for VRR TG Ankit Nautiyal
@ 2026-06-08 12:37 ` Ankit Nautiyal
2026-06-16 18:02 ` Ville Syrjälä
2026-06-08 12:37 ` [PATCH v2 2/2] drm/i915/dsb: Use safe window path when VRR TG is used Ankit Nautiyal
2026-06-08 13:44 ` ✓ CI.KUnit: success for Extend VRR safe window wait for VRR TG Patchwork
2 siblings, 1 reply; 8+ messages in thread
From: Ankit Nautiyal @ 2026-06-08 12:37 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal
In intel_dsb_wait_for_delayed_vblank() the VRR path issues a
WAIT_DSL_OUT(safe_window_start, vmin_safe_window_end) followed by a
WAIT_USEC for SCL+1 scanlines to land on the delayed vblank.
Experimentally, DSB appears to observe a slightly stale PIPEDSL value.
When the actual scanline has just reached safe_window_start, the DSB
may still see a value at or before that boundary when WAIT_DSL_OUT is
evaluated, causing the wait to complete immediately.
As a result, the subsequent WAIT_USEC executes too early, and the
flip-done interrupt fires roughly one frame ahead of the delayed vblank.
Shift the scanline start back by one to ensure the wait window is
entered reliably.
v2: Replace explicit one-scanline delay with scanline boundary
adjustment (safe_window_start - 1). (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index fec8a56e21ea..07dd6318d9cc 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -902,9 +902,17 @@ void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
* the hardware itself guarantees that we're SCL lines
* away from the delayed vblank, and we won't be inside
* the vmin safe window so this extra wait does nothing.
+ *
+ * Experimentally, DSB may observe a slightly stale
+ * PIPEDSL value. When the actual scanline has just reached
+ * safe_window_start, WAIT_DSL_OUT may complete immediately
+ * due to the stale value.
+ *
+ * Shift the start back by one scanline to ensure the wait
+ * window is entered reliably.
*/
intel_dsb_wait_scanline_out(state, dsb,
- intel_vrr_safe_window_start(crtc_state),
+ intel_vrr_safe_window_start(crtc_state) - 1,
intel_vrr_vmin_safe_window_end(crtc_state));
/*
* When the push is sent during vblank it will trigger
--
2.45.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 1/2] drm/i915/dsb: shift delayed-vblank DSL wait start by one scanline
2026-06-08 12:37 ` [PATCH v2 1/2] drm/i915/dsb: shift delayed-vblank DSL wait start by one scanline Ankit Nautiyal
@ 2026-06-16 18:02 ` Ville Syrjälä
0 siblings, 0 replies; 8+ messages in thread
From: Ville Syrjälä @ 2026-06-16 18:02 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe
On Mon, Jun 08, 2026 at 06:07:09PM +0530, Ankit Nautiyal wrote:
> In intel_dsb_wait_for_delayed_vblank() the VRR path issues a
> WAIT_DSL_OUT(safe_window_start, vmin_safe_window_end) followed by a
> WAIT_USEC for SCL+1 scanlines to land on the delayed vblank.
>
> Experimentally, DSB appears to observe a slightly stale PIPEDSL value.
> When the actual scanline has just reached safe_window_start, the DSB
> may still see a value at or before that boundary when WAIT_DSL_OUT is
> evaluated, causing the wait to complete immediately.
>
> As a result, the subsequent WAIT_USEC executes too early, and the
> flip-done interrupt fires roughly one frame ahead of the delayed vblank.
>
> Shift the scanline start back by one to ensure the wait window is
> entered reliably.
>
> v2: Replace explicit one-scanline delay with scanline boundary
> adjustment (safe_window_start - 1). (Ville)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dsb.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index fec8a56e21ea..07dd6318d9cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -902,9 +902,17 @@ void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
> * the hardware itself guarantees that we're SCL lines
> * away from the delayed vblank, and we won't be inside
> * the vmin safe window so this extra wait does nothing.
> + *
> + * Experimentally, DSB may observe a slightly stale
> + * PIPEDSL value. When the actual scanline has just reached
> + * safe_window_start, WAIT_DSL_OUT may complete immediately
> + * due to the stale value.
> + *
> + * Shift the start back by one scanline to ensure the wait
> + * window is entered reliably.
> */
> intel_dsb_wait_scanline_out(state, dsb,
> - intel_vrr_safe_window_start(crtc_state),
> + intel_vrr_safe_window_start(crtc_state) - 1,
> intel_vrr_vmin_safe_window_end(crtc_state));
> /*
> * When the push is sent during vblank it will trigger
> --
> 2.45.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/2] drm/i915/dsb: Use safe window path when VRR TG is used
2026-06-08 12:37 [PATCH v2 0/2] Extend VRR safe window wait for VRR TG Ankit Nautiyal
2026-06-08 12:37 ` [PATCH v2 1/2] drm/i915/dsb: shift delayed-vblank DSL wait start by one scanline Ankit Nautiyal
@ 2026-06-08 12:37 ` Ankit Nautiyal
2026-06-16 18:02 ` Ville Syrjälä
2026-06-17 5:14 ` [PATCH v3 " Ankit Nautiyal
2026-06-08 13:44 ` ✓ CI.KUnit: success for Extend VRR safe window wait for VRR TG Patchwork
2 siblings, 2 replies; 8+ messages in thread
From: Ankit Nautiyal @ 2026-06-08 12:37 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal
When the VRR timing generator is always used, the hardware behaves
as VRR-active regardless of crtc_state->vrr.enable.
The DSB paths that depend on the VRR safe window therefore need to follow
the VRR code paths in that case too:
- dsb_chicken(): program the SAFE_WINDOW chicken bits,
- intel_dsb_vblank_evade(): use vmin/vmax vblank starts for the
wait window,
- intel_dsb_wait_for_delayed_vblank(): wait inside the vmin safe window
before the scanline-based delayed vblank wait.
Introduce helper pre_commit_use_safe_window() and use it in the three sites
v2: Instead of modifying pre_commit_is_vrr_active() use a new helper and
use it only in the required places. (Ville).
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 07dd6318d9cc..d1441a86d1cc 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -210,6 +210,18 @@ static int dsb_scanline_to_hw(struct intel_atomic_state *state,
return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal;
}
+static
+bool pre_commit_use_safe_window(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct intel_display *display = to_intel_display(crtc->base.dev);
+
+ if (intel_vrr_always_use_vrr_tg(display))
+ return true;
+
+ return pre_commit_is_vrr_active(state, crtc);
+}
+
/*
* Bspec suggests that we should always set DSB_SKIP_WAITS_EN. We have approach
* different from what is explained in Bspec on how flip is considered being
@@ -229,7 +241,7 @@ static u32 dsb_chicken(struct intel_atomic_state *state,
u32 chicken = intel_psr_use_trans_push(new_crtc_state) ?
DSB_SKIP_WAITS_EN : 0;
- if (pre_commit_is_vrr_active(state, crtc))
+ if (pre_commit_use_safe_window(state, crtc))
chicken |= DSB_CTRL_WAIT_SAFE_WINDOW |
DSB_CTRL_NO_WAIT_VBLANK |
DSB_INST_WAIT_SAFE_WINDOW |
@@ -759,7 +771,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
if (crtc_state->has_psr)
intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
- if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) {
+ if (pre_commit_use_safe_window(state, crtc) && crtc_state->vrr.dc_balance.enable) {
int vblank_delay = crtc_state->set_context_latency;
int vmin_vblank_start, vmax_vblank_start;
@@ -788,7 +800,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
end = vmax_vblank_start;
start = end - vblank_delay - latency;
intel_dsb_wait_scanline_out(state, dsb, start, end);
- } else if (pre_commit_is_vrr_active(state, crtc)) {
+ } else if (pre_commit_use_safe_window(state, crtc)) {
int vblank_delay = crtc_state->set_context_latency;
end = intel_vrr_vmin_vblank_start(crtc_state);
@@ -891,7 +903,7 @@ void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
&crtc_state->hw.adjusted_mode;
int wait_scanlines;
- if (pre_commit_is_vrr_active(state, crtc)) {
+ if (pre_commit_use_safe_window(state, crtc)) {
/*
* If the push happened before the vmin decision boundary
* we don't know how far we are from the undelayed vblank.
--
2.45.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/2] drm/i915/dsb: Use safe window path when VRR TG is used
2026-06-08 12:37 ` [PATCH v2 2/2] drm/i915/dsb: Use safe window path when VRR TG is used Ankit Nautiyal
@ 2026-06-16 18:02 ` Ville Syrjälä
2026-06-17 4:59 ` Nautiyal, Ankit K
2026-06-17 5:14 ` [PATCH v3 " Ankit Nautiyal
1 sibling, 1 reply; 8+ messages in thread
From: Ville Syrjälä @ 2026-06-16 18:02 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe
On Mon, Jun 08, 2026 at 06:07:10PM +0530, Ankit Nautiyal wrote:
> When the VRR timing generator is always used, the hardware behaves
> as VRR-active regardless of crtc_state->vrr.enable.
>
> The DSB paths that depend on the VRR safe window therefore need to follow
> the VRR code paths in that case too:
> - dsb_chicken(): program the SAFE_WINDOW chicken bits,
> - intel_dsb_vblank_evade(): use vmin/vmax vblank starts for the
> wait window,
> - intel_dsb_wait_for_delayed_vblank(): wait inside the vmin safe window
> before the scanline-based delayed vblank wait.
>
> Introduce helper pre_commit_use_safe_window() and use it in the three sites
>
> v2: Instead of modifying pre_commit_is_vrr_active() use a new helper and
> use it only in the required places. (Ville).
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dsb.c | 20 ++++++++++++++++----
> 1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 07dd6318d9cc..d1441a86d1cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -210,6 +210,18 @@ static int dsb_scanline_to_hw(struct intel_atomic_state *state,
> return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal;
> }
>
> +static
> +bool pre_commit_use_safe_window(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + struct intel_display *display = to_intel_display(crtc->base.dev);
> +
> + if (intel_vrr_always_use_vrr_tg(display))
> + return true;
> +
> + return pre_commit_is_vrr_active(state, crtc);
> +}
> +
> /*
> * Bspec suggests that we should always set DSB_SKIP_WAITS_EN. We have approach
> * different from what is explained in Bspec on how flip is considered being
> @@ -229,7 +241,7 @@ static u32 dsb_chicken(struct intel_atomic_state *state,
> u32 chicken = intel_psr_use_trans_push(new_crtc_state) ?
> DSB_SKIP_WAITS_EN : 0;
>
> - if (pre_commit_is_vrr_active(state, crtc))
> + if (pre_commit_use_safe_window(state, crtc))
> chicken |= DSB_CTRL_WAIT_SAFE_WINDOW |
> DSB_CTRL_NO_WAIT_VBLANK |
> DSB_INST_WAIT_SAFE_WINDOW |
> @@ -759,7 +771,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
> if (crtc_state->has_psr)
> intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
>
> - if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) {
> + if (pre_commit_use_safe_window(state, crtc) && crtc_state->vrr.dc_balance.enable) {
This one I think should keep using pre_commit_is_vrr_active().
> int vblank_delay = crtc_state->set_context_latency;
> int vmin_vblank_start, vmax_vblank_start;
>
> @@ -788,7 +800,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
> end = vmax_vblank_start;
> start = end - vblank_delay - latency;
> intel_dsb_wait_scanline_out(state, dsb, start, end);
> - } else if (pre_commit_is_vrr_active(state, crtc)) {
> + } else if (pre_commit_use_safe_window(state, crtc)) {
> int vblank_delay = crtc_state->set_context_latency;
>
> end = intel_vrr_vmin_vblank_start(crtc_state);
This will now emit two WAIT_DSL commands, which may be a bit confusing.
Might be better to add a completely separate branch to the if ladder
for this situation. And for consistency it should perhaps use
intel_mode_vblank_start() rather than intel_vrr_*_vblank_start()
since we're dealing with fixed refresh rate timings here.
> @@ -891,7 +903,7 @@ void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
> &crtc_state->hw.adjusted_mode;
> int wait_scanlines;
>
> - if (pre_commit_is_vrr_active(state, crtc)) {
> + if (pre_commit_use_safe_window(state, crtc)) {
> /*
> * If the push happened before the vmin decision boundary
> * we don't know how far we are from the undelayed vblank.
> --
> 2.45.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/2] drm/i915/dsb: Use safe window path when VRR TG is used
2026-06-16 18:02 ` Ville Syrjälä
@ 2026-06-17 4:59 ` Nautiyal, Ankit K
0 siblings, 0 replies; 8+ messages in thread
From: Nautiyal, Ankit K @ 2026-06-17 4:59 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe
On 6/16/2026 11:32 PM, Ville Syrjälä wrote:
> On Mon, Jun 08, 2026 at 06:07:10PM +0530, Ankit Nautiyal wrote:
>> When the VRR timing generator is always used, the hardware behaves
>> as VRR-active regardless of crtc_state->vrr.enable.
>>
>> The DSB paths that depend on the VRR safe window therefore need to follow
>> the VRR code paths in that case too:
>> - dsb_chicken(): program the SAFE_WINDOW chicken bits,
>> - intel_dsb_vblank_evade(): use vmin/vmax vblank starts for the
>> wait window,
>> - intel_dsb_wait_for_delayed_vblank(): wait inside the vmin safe window
>> before the scanline-based delayed vblank wait.
>>
>> Introduce helper pre_commit_use_safe_window() and use it in the three sites
>>
>> v2: Instead of modifying pre_commit_is_vrr_active() use a new helper and
>> use it only in the required places. (Ville).
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dsb.c | 20 ++++++++++++++++----
>> 1 file changed, 16 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
>> index 07dd6318d9cc..d1441a86d1cc 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>> @@ -210,6 +210,18 @@ static int dsb_scanline_to_hw(struct intel_atomic_state *state,
>> return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal;
>> }
>>
>> +static
>> +bool pre_commit_use_safe_window(struct intel_atomic_state *state,
>> + struct intel_crtc *crtc)
>> +{
>> + struct intel_display *display = to_intel_display(crtc->base.dev);
>> +
>> + if (intel_vrr_always_use_vrr_tg(display))
>> + return true;
>> +
>> + return pre_commit_is_vrr_active(state, crtc);
>> +}
>> +
>> /*
>> * Bspec suggests that we should always set DSB_SKIP_WAITS_EN. We have approach
>> * different from what is explained in Bspec on how flip is considered being
>> @@ -229,7 +241,7 @@ static u32 dsb_chicken(struct intel_atomic_state *state,
>> u32 chicken = intel_psr_use_trans_push(new_crtc_state) ?
>> DSB_SKIP_WAITS_EN : 0;
>>
>> - if (pre_commit_is_vrr_active(state, crtc))
>> + if (pre_commit_use_safe_window(state, crtc))
>> chicken |= DSB_CTRL_WAIT_SAFE_WINDOW |
>> DSB_CTRL_NO_WAIT_VBLANK |
>> DSB_INST_WAIT_SAFE_WINDOW |
>> @@ -759,7 +771,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
>> if (crtc_state->has_psr)
>> intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
>>
>> - if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) {
>> + if (pre_commit_use_safe_window(state, crtc) && crtc_state->vrr.dc_balance.enable) {
> This one I think should keep using pre_commit_is_vrr_active().
Yes you are right DC balance is always with VRR so
pre_commit_is_vrr_active() makes sense.
>
>> int vblank_delay = crtc_state->set_context_latency;
>> int vmin_vblank_start, vmax_vblank_start;
>>
>> @@ -788,7 +800,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
>> end = vmax_vblank_start;
>> start = end - vblank_delay - latency;
>> intel_dsb_wait_scanline_out(state, dsb, start, end);
>> - } else if (pre_commit_is_vrr_active(state, crtc)) {
>> + } else if (pre_commit_use_safe_window(state, crtc)) {
>> int vblank_delay = crtc_state->set_context_latency;
>>
>> end = intel_vrr_vmin_vblank_start(crtc_state);
> This will now emit two WAIT_DSL commands, which may be a bit confusing.
> Might be better to add a completely separate branch to the if ladder
> for this situation. And for consistency it should perhaps use
> intel_mode_vblank_start() rather than intel_vrr_*_vblank_start()
> since we're dealing with fixed refresh rate timings here.
Oh ok. Right.
I will add one more branches as suggested.
This will now have 4 branches:
-DC Balance + VRR [Needs pre_commit_is_vrr_active()]
-VRR without DC Balance [Needs pre_commit_is_vrr_active()]
-Fixed RR (always use VRR TG, NA for other platforms) [ Needs
pre_commit_use_safe_window()]
-Fixed RR (for other platforms (not always using VRR TG) [else]
I will fix this and re-send this patch.
Thanks for the guidance here. Its clearer to me now.
Regards,
Ankit
>
>> @@ -891,7 +903,7 @@ void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
>> &crtc_state->hw.adjusted_mode;
>> int wait_scanlines;
>>
>> - if (pre_commit_is_vrr_active(state, crtc)) {
>> + if (pre_commit_use_safe_window(state, crtc)) {
>> /*
>> * If the push happened before the vmin decision boundary
>> * we don't know how far we are from the undelayed vblank.
>> --
>> 2.45.2
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 2/2] drm/i915/dsb: Use safe window path when VRR TG is used
2026-06-08 12:37 ` [PATCH v2 2/2] drm/i915/dsb: Use safe window path when VRR TG is used Ankit Nautiyal
2026-06-16 18:02 ` Ville Syrjälä
@ 2026-06-17 5:14 ` Ankit Nautiyal
1 sibling, 0 replies; 8+ messages in thread
From: Ankit Nautiyal @ 2026-06-17 5:14 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal
When the VRR timing generator is always used, the hardware behaves
as VRR-active regardless of crtc_state->vrr.enable.
The DSB paths that depend on the VRR safe window therefore need to follow
the VRR code paths in that case too:
- dsb_chicken(): program the SAFE_WINDOW chicken bits,
- intel_dsb_vblank_evade(): use vmin/vmax vblank starts for the
wait window,
- intel_dsb_wait_for_delayed_vblank(): wait inside the vmin safe window
before the scanline-based delayed vblank wait.
Introduce helper pre_commit_use_safe_window() and use it in the three sites
v2: Instead of modifying pre_commit_is_vrr_active() use a new helper and
use it only in the required places. (Ville).
v3: -Keep using pre_commit_is_vrr_active() for DCB path. (Ville)
-Add a separate check for fixed RR with VRR TG and use
fixed mode vblank start there. (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 07dd6318d9cc..d9a270362a82 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -210,6 +210,18 @@ static int dsb_scanline_to_hw(struct intel_atomic_state *state,
return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal;
}
+static
+bool pre_commit_use_safe_window(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct intel_display *display = to_intel_display(crtc->base.dev);
+
+ if (intel_vrr_always_use_vrr_tg(display))
+ return true;
+
+ return pre_commit_is_vrr_active(state, crtc);
+}
+
/*
* Bspec suggests that we should always set DSB_SKIP_WAITS_EN. We have approach
* different from what is explained in Bspec on how flip is considered being
@@ -229,7 +241,7 @@ static u32 dsb_chicken(struct intel_atomic_state *state,
u32 chicken = intel_psr_use_trans_push(new_crtc_state) ?
DSB_SKIP_WAITS_EN : 0;
- if (pre_commit_is_vrr_active(state, crtc))
+ if (pre_commit_use_safe_window(state, crtc))
chicken |= DSB_CTRL_WAIT_SAFE_WINDOW |
DSB_CTRL_NO_WAIT_VBLANK |
DSB_INST_WAIT_SAFE_WINDOW |
@@ -798,6 +810,12 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
end = intel_vrr_vmax_vblank_start(crtc_state);
start = end - vblank_delay - latency;
intel_dsb_wait_scanline_out(state, dsb, start, end);
+ } else if (pre_commit_use_safe_window(state, crtc)) {
+ int vblank_delay = crtc_state->set_context_latency;
+
+ end = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode);
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
} else {
int vblank_delay = intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
@@ -891,7 +909,7 @@ void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
&crtc_state->hw.adjusted_mode;
int wait_scanlines;
- if (pre_commit_is_vrr_active(state, crtc)) {
+ if (pre_commit_use_safe_window(state, crtc)) {
/*
* If the push happened before the vmin decision boundary
* we don't know how far we are from the undelayed vblank.
--
2.45.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✓ CI.KUnit: success for Extend VRR safe window wait for VRR TG
2026-06-08 12:37 [PATCH v2 0/2] Extend VRR safe window wait for VRR TG Ankit Nautiyal
2026-06-08 12:37 ` [PATCH v2 1/2] drm/i915/dsb: shift delayed-vblank DSL wait start by one scanline Ankit Nautiyal
2026-06-08 12:37 ` [PATCH v2 2/2] drm/i915/dsb: Use safe window path when VRR TG is used Ankit Nautiyal
@ 2026-06-08 13:44 ` Patchwork
2 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-06-08 13:44 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
== Series Details ==
Series: Extend VRR safe window wait for VRR TG
URL : https://patchwork.freedesktop.org/series/168082/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[13:43:09] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:43:14] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:43:46] Starting KUnit Kernel (1/1)...
[13:43:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:43:46] ================== guc_buf (11 subtests) ===================
[13:43:46] [PASSED] test_smallest
[13:43:46] [PASSED] test_largest
[13:43:46] [PASSED] test_granular
[13:43:46] [PASSED] test_unique
[13:43:46] [PASSED] test_overlap
[13:43:46] [PASSED] test_reusable
[13:43:46] [PASSED] test_too_big
[13:43:46] [PASSED] test_flush
[13:43:46] [PASSED] test_lookup
[13:43:46] [PASSED] test_data
[13:43:46] [PASSED] test_class
[13:43:46] ===================== [PASSED] guc_buf =====================
[13:43:46] =================== guc_dbm (7 subtests) ===================
[13:43:46] [PASSED] test_empty
[13:43:46] [PASSED] test_default
[13:43:46] ======================== test_size ========================
[13:43:46] [PASSED] 4
[13:43:46] [PASSED] 8
[13:43:46] [PASSED] 32
[13:43:46] [PASSED] 256
[13:43:46] ==================== [PASSED] test_size ====================
[13:43:46] ======================= test_reuse ========================
[13:43:46] [PASSED] 4
[13:43:46] [PASSED] 8
[13:43:46] [PASSED] 32
[13:43:46] [PASSED] 256
[13:43:46] =================== [PASSED] test_reuse ====================
[13:43:46] =================== test_range_overlap ====================
[13:43:46] [PASSED] 4
[13:43:46] [PASSED] 8
[13:43:46] [PASSED] 32
[13:43:46] [PASSED] 256
[13:43:46] =============== [PASSED] test_range_overlap ================
[13:43:46] =================== test_range_compact ====================
[13:43:46] [PASSED] 4
[13:43:46] [PASSED] 8
[13:43:46] [PASSED] 32
[13:43:46] [PASSED] 256
[13:43:46] =============== [PASSED] test_range_compact ================
[13:43:46] ==================== test_range_spare =====================
[13:43:46] [PASSED] 4
[13:43:46] [PASSED] 8
[13:43:46] [PASSED] 32
[13:43:46] [PASSED] 256
[13:43:46] ================ [PASSED] test_range_spare =================
[13:43:46] ===================== [PASSED] guc_dbm =====================
[13:43:46] =================== guc_idm (6 subtests) ===================
[13:43:46] [PASSED] bad_init
[13:43:46] [PASSED] no_init
[13:43:46] [PASSED] init_fini
[13:43:46] [PASSED] check_used
[13:43:46] [PASSED] check_quota
[13:43:46] [PASSED] check_all
[13:43:46] ===================== [PASSED] guc_idm =====================
[13:43:46] ================== no_relay (3 subtests) ===================
[13:43:46] [PASSED] xe_drops_guc2pf_if_not_ready
[13:43:46] [PASSED] xe_drops_guc2vf_if_not_ready
[13:43:46] [PASSED] xe_rejects_send_if_not_ready
[13:43:46] ==================== [PASSED] no_relay =====================
[13:43:46] ================== pf_relay (14 subtests) ==================
[13:43:46] [PASSED] pf_rejects_guc2pf_too_short
[13:43:46] [PASSED] pf_rejects_guc2pf_too_long
[13:43:46] [PASSED] pf_rejects_guc2pf_no_payload
[13:43:46] [PASSED] pf_fails_no_payload
[13:43:46] [PASSED] pf_fails_bad_origin
[13:43:46] [PASSED] pf_fails_bad_type
[13:43:46] [PASSED] pf_txn_reports_error
[13:43:46] [PASSED] pf_txn_sends_pf2guc
[13:43:46] [PASSED] pf_sends_pf2guc
[13:43:46] [SKIPPED] pf_loopback_nop
[13:43:46] [SKIPPED] pf_loopback_echo
[13:43:46] [SKIPPED] pf_loopback_fail
[13:43:46] [SKIPPED] pf_loopback_busy
[13:43:46] [SKIPPED] pf_loopback_retry
[13:43:46] ==================== [PASSED] pf_relay =====================
[13:43:46] ================== vf_relay (3 subtests) ===================
[13:43:46] [PASSED] vf_rejects_guc2vf_too_short
[13:43:46] [PASSED] vf_rejects_guc2vf_too_long
[13:43:46] [PASSED] vf_rejects_guc2vf_no_payload
[13:43:46] ==================== [PASSED] vf_relay =====================
[13:43:46] ================ pf_gt_config (9 subtests) =================
[13:43:46] [PASSED] fair_contexts_1vf
[13:43:46] [PASSED] fair_doorbells_1vf
[13:43:46] [PASSED] fair_ggtt_1vf
[13:43:46] ====================== fair_vram_1vf ======================
[13:43:46] [PASSED] 3.50 GiB
[13:43:46] [PASSED] 11.5 GiB
[13:43:46] [PASSED] 15.5 GiB
[13:43:46] [PASSED] 31.5 GiB
[13:43:46] [PASSED] 63.5 GiB
[13:43:46] [PASSED] 1.91 GiB
[13:43:46] ================== [PASSED] fair_vram_1vf ==================
[13:43:46] ================ fair_vram_1vf_admin_only =================
[13:43:46] [PASSED] 3.50 GiB
[13:43:46] [PASSED] 11.5 GiB
[13:43:46] [PASSED] 15.5 GiB
[13:43:46] [PASSED] 31.5 GiB
[13:43:46] [PASSED] 63.5 GiB
[13:43:46] [PASSED] 1.91 GiB
[13:43:46] ============ [PASSED] fair_vram_1vf_admin_only =============
[13:43:46] ====================== fair_contexts ======================
[13:43:46] [PASSED] 1 VF
[13:43:46] [PASSED] 2 VFs
[13:43:46] [PASSED] 3 VFs
[13:43:46] [PASSED] 4 VFs
[13:43:46] [PASSED] 5 VFs
[13:43:46] [PASSED] 6 VFs
[13:43:46] [PASSED] 7 VFs
[13:43:46] [PASSED] 8 VFs
[13:43:46] [PASSED] 9 VFs
[13:43:46] [PASSED] 10 VFs
[13:43:46] [PASSED] 11 VFs
[13:43:46] [PASSED] 12 VFs
[13:43:46] [PASSED] 13 VFs
[13:43:46] [PASSED] 14 VFs
[13:43:46] [PASSED] 15 VFs
[13:43:46] [PASSED] 16 VFs
[13:43:46] [PASSED] 17 VFs
[13:43:46] [PASSED] 18 VFs
[13:43:46] [PASSED] 19 VFs
[13:43:46] [PASSED] 20 VFs
[13:43:46] [PASSED] 21 VFs
[13:43:46] [PASSED] 22 VFs
[13:43:46] [PASSED] 23 VFs
[13:43:46] [PASSED] 24 VFs
[13:43:46] [PASSED] 25 VFs
[13:43:46] [PASSED] 26 VFs
[13:43:46] [PASSED] 27 VFs
[13:43:46] [PASSED] 28 VFs
[13:43:46] [PASSED] 29 VFs
[13:43:46] [PASSED] 30 VFs
[13:43:46] [PASSED] 31 VFs
[13:43:46] [PASSED] 32 VFs
[13:43:46] [PASSED] 33 VFs
[13:43:46] [PASSED] 34 VFs
[13:43:46] [PASSED] 35 VFs
[13:43:46] [PASSED] 36 VFs
[13:43:46] [PASSED] 37 VFs
[13:43:46] [PASSED] 38 VFs
[13:43:46] [PASSED] 39 VFs
[13:43:46] [PASSED] 40 VFs
[13:43:46] [PASSED] 41 VFs
[13:43:46] [PASSED] 42 VFs
[13:43:46] [PASSED] 43 VFs
[13:43:46] [PASSED] 44 VFs
[13:43:46] [PASSED] 45 VFs
[13:43:46] [PASSED] 46 VFs
[13:43:46] [PASSED] 47 VFs
[13:43:46] [PASSED] 48 VFs
[13:43:46] [PASSED] 49 VFs
[13:43:46] [PASSED] 50 VFs
[13:43:46] [PASSED] 51 VFs
[13:43:46] [PASSED] 52 VFs
[13:43:46] [PASSED] 53 VFs
[13:43:46] [PASSED] 54 VFs
[13:43:46] [PASSED] 55 VFs
[13:43:46] [PASSED] 56 VFs
[13:43:46] [PASSED] 57 VFs
[13:43:46] [PASSED] 58 VFs
[13:43:46] [PASSED] 59 VFs
[13:43:46] [PASSED] 60 VFs
[13:43:46] [PASSED] 61 VFs
[13:43:46] [PASSED] 62 VFs
[13:43:46] [PASSED] 63 VFs
[13:43:46] ================== [PASSED] fair_contexts ==================
[13:43:46] ===================== fair_doorbells ======================
[13:43:46] [PASSED] 1 VF
[13:43:46] [PASSED] 2 VFs
[13:43:46] [PASSED] 3 VFs
[13:43:46] [PASSED] 4 VFs
[13:43:46] [PASSED] 5 VFs
[13:43:46] [PASSED] 6 VFs
[13:43:46] [PASSED] 7 VFs
[13:43:46] [PASSED] 8 VFs
[13:43:46] [PASSED] 9 VFs
[13:43:46] [PASSED] 10 VFs
[13:43:46] [PASSED] 11 VFs
[13:43:46] [PASSED] 12 VFs
[13:43:46] [PASSED] 13 VFs
[13:43:46] [PASSED] 14 VFs
[13:43:46] [PASSED] 15 VFs
[13:43:46] [PASSED] 16 VFs
[13:43:46] [PASSED] 17 VFs
[13:43:46] [PASSED] 18 VFs
[13:43:46] [PASSED] 19 VFs
[13:43:46] [PASSED] 20 VFs
[13:43:46] [PASSED] 21 VFs
[13:43:46] [PASSED] 22 VFs
[13:43:46] [PASSED] 23 VFs
[13:43:46] [PASSED] 24 VFs
[13:43:46] [PASSED] 25 VFs
[13:43:46] [PASSED] 26 VFs
[13:43:46] [PASSED] 27 VFs
[13:43:46] [PASSED] 28 VFs
[13:43:46] [PASSED] 29 VFs
[13:43:46] [PASSED] 30 VFs
[13:43:46] [PASSED] 31 VFs
[13:43:46] [PASSED] 32 VFs
[13:43:46] [PASSED] 33 VFs
[13:43:46] [PASSED] 34 VFs
[13:43:46] [PASSED] 35 VFs
[13:43:46] [PASSED] 36 VFs
[13:43:46] [PASSED] 37 VFs
[13:43:46] [PASSED] 38 VFs
[13:43:46] [PASSED] 39 VFs
[13:43:46] [PASSED] 40 VFs
[13:43:46] [PASSED] 41 VFs
[13:43:46] [PASSED] 42 VFs
[13:43:46] [PASSED] 43 VFs
[13:43:46] [PASSED] 44 VFs
[13:43:46] [PASSED] 45 VFs
[13:43:46] [PASSED] 46 VFs
[13:43:46] [PASSED] 47 VFs
[13:43:46] [PASSED] 48 VFs
[13:43:46] [PASSED] 49 VFs
[13:43:46] [PASSED] 50 VFs
[13:43:46] [PASSED] 51 VFs
[13:43:46] [PASSED] 52 VFs
[13:43:46] [PASSED] 53 VFs
[13:43:46] [PASSED] 54 VFs
[13:43:46] [PASSED] 55 VFs
[13:43:46] [PASSED] 56 VFs
[13:43:46] [PASSED] 57 VFs
[13:43:46] [PASSED] 58 VFs
[13:43:46] [PASSED] 59 VFs
[13:43:46] [PASSED] 60 VFs
[13:43:46] [PASSED] 61 VFs
[13:43:46] [PASSED] 62 VFs
[13:43:46] [PASSED] 63 VFs
[13:43:46] ================= [PASSED] fair_doorbells ==================
[13:43:46] ======================== fair_ggtt ========================
[13:43:46] [PASSED] 1 VF
[13:43:46] [PASSED] 2 VFs
[13:43:46] [PASSED] 3 VFs
[13:43:46] [PASSED] 4 VFs
[13:43:46] [PASSED] 5 VFs
[13:43:46] [PASSED] 6 VFs
[13:43:46] [PASSED] 7 VFs
[13:43:46] [PASSED] 8 VFs
[13:43:46] [PASSED] 9 VFs
[13:43:46] [PASSED] 10 VFs
[13:43:46] [PASSED] 11 VFs
[13:43:46] [PASSED] 12 VFs
[13:43:46] [PASSED] 13 VFs
[13:43:46] [PASSED] 14 VFs
[13:43:46] [PASSED] 15 VFs
[13:43:46] [PASSED] 16 VFs
[13:43:46] [PASSED] 17 VFs
[13:43:46] [PASSED] 18 VFs
[13:43:46] [PASSED] 19 VFs
[13:43:46] [PASSED] 20 VFs
[13:43:46] [PASSED] 21 VFs
[13:43:46] [PASSED] 22 VFs
[13:43:46] [PASSED] 23 VFs
[13:43:46] [PASSED] 24 VFs
[13:43:46] [PASSED] 25 VFs
[13:43:46] [PASSED] 26 VFs
[13:43:46] [PASSED] 27 VFs
[13:43:46] [PASSED] 28 VFs
[13:43:46] [PASSED] 29 VFs
[13:43:46] [PASSED] 30 VFs
[13:43:46] [PASSED] 31 VFs
[13:43:46] [PASSED] 32 VFs
[13:43:46] [PASSED] 33 VFs
[13:43:46] [PASSED] 34 VFs
[13:43:46] [PASSED] 35 VFs
[13:43:46] [PASSED] 36 VFs
[13:43:46] [PASSED] 37 VFs
[13:43:46] [PASSED] 38 VFs
[13:43:46] [PASSED] 39 VFs
[13:43:46] [PASSED] 40 VFs
[13:43:46] [PASSED] 41 VFs
[13:43:46] [PASSED] 42 VFs
[13:43:46] [PASSED] 43 VFs
[13:43:46] [PASSED] 44 VFs
[13:43:46] [PASSED] 45 VFs
[13:43:46] [PASSED] 46 VFs
[13:43:46] [PASSED] 47 VFs
[13:43:46] [PASSED] 48 VFs
[13:43:46] [PASSED] 49 VFs
[13:43:46] [PASSED] 50 VFs
[13:43:46] [PASSED] 51 VFs
[13:43:46] [PASSED] 52 VFs
[13:43:46] [PASSED] 53 VFs
[13:43:46] [PASSED] 54 VFs
[13:43:46] [PASSED] 55 VFs
[13:43:46] [PASSED] 56 VFs
[13:43:46] [PASSED] 57 VFs
[13:43:46] [PASSED] 58 VFs
[13:43:46] [PASSED] 59 VFs
[13:43:46] [PASSED] 60 VFs
[13:43:46] [PASSED] 61 VFs
[13:43:46] [PASSED] 62 VFs
[13:43:46] [PASSED] 63 VFs
[13:43:46] ==================== [PASSED] fair_ggtt ====================
[13:43:46] ======================== fair_vram ========================
[13:43:46] [PASSED] 1 VF
[13:43:46] [PASSED] 2 VFs
[13:43:46] [PASSED] 3 VFs
[13:43:46] [PASSED] 4 VFs
[13:43:46] [PASSED] 5 VFs
[13:43:46] [PASSED] 6 VFs
[13:43:46] [PASSED] 7 VFs
[13:43:46] [PASSED] 8 VFs
[13:43:46] [PASSED] 9 VFs
[13:43:46] [PASSED] 10 VFs
[13:43:46] [PASSED] 11 VFs
[13:43:46] [PASSED] 12 VFs
[13:43:46] [PASSED] 13 VFs
[13:43:46] [PASSED] 14 VFs
[13:43:46] [PASSED] 15 VFs
[13:43:46] [PASSED] 16 VFs
[13:43:46] [PASSED] 17 VFs
[13:43:46] [PASSED] 18 VFs
[13:43:46] [PASSED] 19 VFs
[13:43:46] [PASSED] 20 VFs
[13:43:46] [PASSED] 21 VFs
[13:43:46] [PASSED] 22 VFs
[13:43:46] [PASSED] 23 VFs
[13:43:46] [PASSED] 24 VFs
[13:43:46] [PASSED] 25 VFs
[13:43:46] [PASSED] 26 VFs
[13:43:46] [PASSED] 27 VFs
[13:43:46] [PASSED] 28 VFs
[13:43:46] [PASSED] 29 VFs
[13:43:46] [PASSED] 30 VFs
[13:43:46] [PASSED] 31 VFs
[13:43:46] [PASSED] 32 VFs
[13:43:46] [PASSED] 33 VFs
[13:43:46] [PASSED] 34 VFs
[13:43:46] [PASSED] 35 VFs
[13:43:46] [PASSED] 36 VFs
[13:43:46] [PASSED] 37 VFs
[13:43:46] [PASSED] 38 VFs
[13:43:46] [PASSED] 39 VFs
[13:43:46] [PASSED] 40 VFs
[13:43:46] [PASSED] 41 VFs
[13:43:46] [PASSED] 42 VFs
[13:43:46] [PASSED] 43 VFs
[13:43:46] [PASSED] 44 VFs
[13:43:46] [PASSED] 45 VFs
[13:43:46] [PASSED] 46 VFs
[13:43:46] [PASSED] 47 VFs
[13:43:46] [PASSED] 48 VFs
[13:43:46] [PASSED] 49 VFs
[13:43:46] [PASSED] 50 VFs
[13:43:46] [PASSED] 51 VFs
[13:43:46] [PASSED] 52 VFs
[13:43:46] [PASSED] 53 VFs
[13:43:46] [PASSED] 54 VFs
[13:43:46] [PASSED] 55 VFs
[13:43:46] [PASSED] 56 VFs
[13:43:46] [PASSED] 57 VFs
[13:43:46] [PASSED] 58 VFs
[13:43:46] [PASSED] 59 VFs
[13:43:46] [PASSED] 60 VFs
[13:43:46] [PASSED] 61 VFs
[13:43:46] [PASSED] 62 VFs
[13:43:46] [PASSED] 63 VFs
[13:43:46] ==================== [PASSED] fair_vram ====================
[13:43:46] ================== [PASSED] pf_gt_config ===================
[13:43:46] ===================== lmtt (1 subtest) =====================
[13:43:46] ======================== test_ops =========================
[13:43:46] [PASSED] 2-level
[13:43:46] [PASSED] multi-level
[13:43:46] ==================== [PASSED] test_ops =====================
[13:43:46] ====================== [PASSED] lmtt =======================
[13:43:46] ================= pf_service (11 subtests) =================
[13:43:46] [PASSED] pf_negotiate_any
[13:43:46] [PASSED] pf_negotiate_base_match
[13:43:46] [PASSED] pf_negotiate_base_newer
[13:43:46] [PASSED] pf_negotiate_base_next
[13:43:46] [SKIPPED] pf_negotiate_base_older
[13:43:46] [PASSED] pf_negotiate_base_prev
[13:43:46] [PASSED] pf_negotiate_latest_match
[13:43:46] [PASSED] pf_negotiate_latest_newer
[13:43:46] [PASSED] pf_negotiate_latest_next
[13:43:46] [SKIPPED] pf_negotiate_latest_older
[13:43:46] [SKIPPED] pf_negotiate_latest_prev
[13:43:46] =================== [PASSED] pf_service ====================
[13:43:46] ================= xe_guc_g2g (2 subtests) ==================
[13:43:46] ============== xe_live_guc_g2g_kunit_default ==============
[13:43:46] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[13:43:46] ============== xe_live_guc_g2g_kunit_allmem ===============
[13:43:46] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[13:43:46] =================== [SKIPPED] xe_guc_g2g ===================
[13:43:46] =================== xe_mocs (2 subtests) ===================
[13:43:46] ================ xe_live_mocs_kernel_kunit ================
[13:43:46] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[13:43:46] ================ xe_live_mocs_reset_kunit =================
[13:43:46] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[13:43:46] ==================== [SKIPPED] xe_mocs =====================
[13:43:46] ================= xe_migrate (2 subtests) ==================
[13:43:46] ================= xe_migrate_sanity_kunit =================
[13:43:46] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[13:43:46] ================== xe_validate_ccs_kunit ==================
[13:43:46] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[13:43:46] =================== [SKIPPED] xe_migrate ===================
[13:43:46] ================== xe_dma_buf (1 subtest) ==================
[13:43:46] ==================== xe_dma_buf_kunit =====================
[13:43:46] ================ [SKIPPED] xe_dma_buf_kunit ================
[13:43:46] =================== [SKIPPED] xe_dma_buf ===================
[13:43:46] ================= xe_bo_shrink (1 subtest) =================
[13:43:46] =================== xe_bo_shrink_kunit ====================
[13:43:46] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[13:43:46] ================== [SKIPPED] xe_bo_shrink ==================
[13:43:46] ==================== xe_bo (2 subtests) ====================
[13:43:46] ================== xe_ccs_migrate_kunit ===================
[13:43:46] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[13:43:46] ==================== xe_bo_evict_kunit ====================
[13:43:46] =============== [SKIPPED] xe_bo_evict_kunit ================
[13:43:46] ===================== [SKIPPED] xe_bo ======================
[13:43:46] ==================== args (13 subtests) ====================
[13:43:46] [PASSED] count_args_test
[13:43:46] [PASSED] call_args_example
[13:43:46] [PASSED] call_args_test
[13:43:46] [PASSED] drop_first_arg_example
[13:43:46] [PASSED] drop_first_arg_test
[13:43:46] [PASSED] first_arg_example
[13:43:46] [PASSED] first_arg_test
[13:43:46] [PASSED] last_arg_example
[13:43:46] [PASSED] last_arg_test
[13:43:46] [PASSED] pick_arg_example
[13:43:46] [PASSED] if_args_example
[13:43:46] [PASSED] if_args_test
[13:43:46] [PASSED] sep_comma_example
[13:43:46] ====================== [PASSED] args =======================
[13:43:46] =================== xe_pci (3 subtests) ====================
[13:43:46] ==================== check_graphics_ip ====================
[13:43:46] [PASSED] 12.00 Xe_LP
[13:43:46] [PASSED] 12.10 Xe_LP+
[13:43:46] [PASSED] 12.55 Xe_HPG
[13:43:46] [PASSED] 12.60 Xe_HPC
[13:43:46] [PASSED] 12.70 Xe_LPG
[13:43:46] [PASSED] 12.71 Xe_LPG
[13:43:46] [PASSED] 12.74 Xe_LPG+
[13:43:46] [PASSED] 20.01 Xe2_HPG
[13:43:46] [PASSED] 20.02 Xe2_HPG
[13:43:46] [PASSED] 20.04 Xe2_LPG
[13:43:46] [PASSED] 30.00 Xe3_LPG
[13:43:46] [PASSED] 30.01 Xe3_LPG
[13:43:46] [PASSED] 30.03 Xe3_LPG
[13:43:46] [PASSED] 30.04 Xe3_LPG
[13:43:46] [PASSED] 30.05 Xe3_LPG
[13:43:46] [PASSED] 35.10 Xe3p_LPG
[13:43:46] [PASSED] 35.11 Xe3p_XPC
[13:43:46] ================ [PASSED] check_graphics_ip ================
[13:43:46] ===================== check_media_ip ======================
[13:43:46] [PASSED] 12.00 Xe_M
[13:43:46] [PASSED] 12.55 Xe_HPM
[13:43:46] [PASSED] 13.00 Xe_LPM+
[13:43:46] [PASSED] 13.01 Xe2_HPM
[13:43:46] [PASSED] 20.00 Xe2_LPM
[13:43:46] [PASSED] 30.00 Xe3_LPM
[13:43:46] [PASSED] 30.02 Xe3_LPM
[13:43:46] [PASSED] 35.00 Xe3p_LPM
[13:43:46] [PASSED] 35.03 Xe3p_HPM
[13:43:46] ================= [PASSED] check_media_ip ==================
[13:43:46] =================== check_platform_desc ===================
[13:43:46] [PASSED] 0x9A60 (TIGERLAKE)
[13:43:46] [PASSED] 0x9A68 (TIGERLAKE)
[13:43:46] [PASSED] 0x9A70 (TIGERLAKE)
[13:43:46] [PASSED] 0x9A40 (TIGERLAKE)
[13:43:46] [PASSED] 0x9A49 (TIGERLAKE)
[13:43:46] [PASSED] 0x9A59 (TIGERLAKE)
[13:43:46] [PASSED] 0x9A78 (TIGERLAKE)
[13:43:46] [PASSED] 0x9AC0 (TIGERLAKE)
[13:43:46] [PASSED] 0x9AC9 (TIGERLAKE)
[13:43:46] [PASSED] 0x9AD9 (TIGERLAKE)
[13:43:46] [PASSED] 0x9AF8 (TIGERLAKE)
[13:43:46] [PASSED] 0x4C80 (ROCKETLAKE)
[13:43:46] [PASSED] 0x4C8A (ROCKETLAKE)
[13:43:46] [PASSED] 0x4C8B (ROCKETLAKE)
[13:43:46] [PASSED] 0x4C8C (ROCKETLAKE)
[13:43:46] [PASSED] 0x4C90 (ROCKETLAKE)
[13:43:46] [PASSED] 0x4C9A (ROCKETLAKE)
[13:43:46] [PASSED] 0x4680 (ALDERLAKE_S)
[13:43:46] [PASSED] 0x4682 (ALDERLAKE_S)
[13:43:46] [PASSED] 0x4688 (ALDERLAKE_S)
[13:43:46] [PASSED] 0x468A (ALDERLAKE_S)
[13:43:46] [PASSED] 0x468B (ALDERLAKE_S)
[13:43:46] [PASSED] 0x4690 (ALDERLAKE_S)
[13:43:46] [PASSED] 0x4692 (ALDERLAKE_S)
[13:43:46] [PASSED] 0x4693 (ALDERLAKE_S)
[13:43:46] [PASSED] 0x46A0 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x46A1 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x46A2 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x46A3 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x46A6 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x46A8 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x46AA (ALDERLAKE_P)
[13:43:46] [PASSED] 0x462A (ALDERLAKE_P)
[13:43:46] [PASSED] 0x4626 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x4628 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x46B0 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x46B1 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x46B2 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x46B3 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x46C0 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x46C1 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x46C2 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x46C3 (ALDERLAKE_P)
[13:43:46] [PASSED] 0x46D0 (ALDERLAKE_N)
[13:43:46] [PASSED] 0x46D1 (ALDERLAKE_N)
[13:43:46] [PASSED] 0x46D2 (ALDERLAKE_N)
[13:43:46] [PASSED] 0x46D3 (ALDERLAKE_N)
[13:43:46] [PASSED] 0x46D4 (ALDERLAKE_N)
[13:43:46] [PASSED] 0xA721 (ALDERLAKE_P)
[13:43:46] [PASSED] 0xA7A1 (ALDERLAKE_P)
[13:43:46] [PASSED] 0xA7A9 (ALDERLAKE_P)
[13:43:46] [PASSED] 0xA7AC (ALDERLAKE_P)
[13:43:46] [PASSED] 0xA7AD (ALDERLAKE_P)
[13:43:46] [PASSED] 0xA720 (ALDERLAKE_P)
[13:43:46] [PASSED] 0xA7A0 (ALDERLAKE_P)
[13:43:46] [PASSED] 0xA7A8 (ALDERLAKE_P)
[13:43:46] [PASSED] 0xA7AA (ALDERLAKE_P)
[13:43:46] [PASSED] 0xA7AB (ALDERLAKE_P)
[13:43:46] [PASSED] 0xA780 (ALDERLAKE_S)
[13:43:46] [PASSED] 0xA781 (ALDERLAKE_S)
[13:43:46] [PASSED] 0xA782 (ALDERLAKE_S)
[13:43:46] [PASSED] 0xA783 (ALDERLAKE_S)
[13:43:46] [PASSED] 0xA788 (ALDERLAKE_S)
[13:43:46] [PASSED] 0xA789 (ALDERLAKE_S)
[13:43:46] [PASSED] 0xA78A (ALDERLAKE_S)
[13:43:46] [PASSED] 0xA78B (ALDERLAKE_S)
[13:43:46] [PASSED] 0x4905 (DG1)
[13:43:46] [PASSED] 0x4906 (DG1)
[13:43:46] [PASSED] 0x4907 (DG1)
[13:43:46] [PASSED] 0x4908 (DG1)
[13:43:46] [PASSED] 0x4909 (DG1)
[13:43:46] [PASSED] 0x56C0 (DG2)
[13:43:46] [PASSED] 0x56C2 (DG2)
[13:43:46] [PASSED] 0x56C1 (DG2)
[13:43:46] [PASSED] 0x7D51 (METEORLAKE)
[13:43:46] [PASSED] 0x7DD1 (METEORLAKE)
[13:43:46] [PASSED] 0x7D41 (METEORLAKE)
[13:43:46] [PASSED] 0x7D67 (METEORLAKE)
[13:43:46] [PASSED] 0xB640 (METEORLAKE)
[13:43:46] [PASSED] 0x56A0 (DG2)
[13:43:46] [PASSED] 0x56A1 (DG2)
[13:43:46] [PASSED] 0x56A2 (DG2)
[13:43:46] [PASSED] 0x56BE (DG2)
[13:43:46] [PASSED] 0x56BF (DG2)
[13:43:46] [PASSED] 0x5690 (DG2)
[13:43:46] [PASSED] 0x5691 (DG2)
[13:43:46] [PASSED] 0x5692 (DG2)
[13:43:46] [PASSED] 0x56A5 (DG2)
[13:43:46] [PASSED] 0x56A6 (DG2)
[13:43:46] [PASSED] 0x56B0 (DG2)
[13:43:46] [PASSED] 0x56B1 (DG2)
[13:43:46] [PASSED] 0x56BA (DG2)
[13:43:46] [PASSED] 0x56BB (DG2)
[13:43:46] [PASSED] 0x56BC (DG2)
[13:43:46] [PASSED] 0x56BD (DG2)
[13:43:46] [PASSED] 0x5693 (DG2)
[13:43:46] [PASSED] 0x5694 (DG2)
[13:43:46] [PASSED] 0x5695 (DG2)
[13:43:46] [PASSED] 0x56A3 (DG2)
[13:43:46] [PASSED] 0x56A4 (DG2)
[13:43:46] [PASSED] 0x56B2 (DG2)
[13:43:46] [PASSED] 0x56B3 (DG2)
[13:43:46] [PASSED] 0x5696 (DG2)
[13:43:46] [PASSED] 0x5697 (DG2)
[13:43:46] [PASSED] 0xB69 (PVC)
[13:43:46] [PASSED] 0xB6E (PVC)
[13:43:46] [PASSED] 0xBD4 (PVC)
[13:43:46] [PASSED] 0xBD5 (PVC)
[13:43:46] [PASSED] 0xBD6 (PVC)
[13:43:46] [PASSED] 0xBD7 (PVC)
[13:43:46] [PASSED] 0xBD8 (PVC)
[13:43:46] [PASSED] 0xBD9 (PVC)
[13:43:46] [PASSED] 0xBDA (PVC)
[13:43:46] [PASSED] 0xBDB (PVC)
[13:43:46] [PASSED] 0xBE0 (PVC)
[13:43:46] [PASSED] 0xBE1 (PVC)
[13:43:46] [PASSED] 0xBE5 (PVC)
[13:43:46] [PASSED] 0x7D40 (METEORLAKE)
[13:43:46] [PASSED] 0x7D45 (METEORLAKE)
[13:43:46] [PASSED] 0x7D55 (METEORLAKE)
[13:43:46] [PASSED] 0x7D60 (METEORLAKE)
[13:43:46] [PASSED] 0x7DD5 (METEORLAKE)
[13:43:46] [PASSED] 0x6420 (LUNARLAKE)
[13:43:46] [PASSED] 0x64A0 (LUNARLAKE)
[13:43:46] [PASSED] 0x64B0 (LUNARLAKE)
[13:43:46] [PASSED] 0xE202 (BATTLEMAGE)
[13:43:46] [PASSED] 0xE209 (BATTLEMAGE)
[13:43:46] [PASSED] 0xE20B (BATTLEMAGE)
[13:43:46] [PASSED] 0xE20C (BATTLEMAGE)
[13:43:46] [PASSED] 0xE20D (BATTLEMAGE)
[13:43:46] [PASSED] 0xE210 (BATTLEMAGE)
[13:43:46] [PASSED] 0xE211 (BATTLEMAGE)
[13:43:46] [PASSED] 0xE212 (BATTLEMAGE)
[13:43:46] [PASSED] 0xE216 (BATTLEMAGE)
[13:43:46] [PASSED] 0xE220 (BATTLEMAGE)
[13:43:46] [PASSED] 0xE221 (BATTLEMAGE)
[13:43:46] [PASSED] 0xE222 (BATTLEMAGE)
[13:43:46] [PASSED] 0xE223 (BATTLEMAGE)
[13:43:46] [PASSED] 0xB080 (PANTHERLAKE)
[13:43:46] [PASSED] 0xB081 (PANTHERLAKE)
[13:43:46] [PASSED] 0xB082 (PANTHERLAKE)
[13:43:46] [PASSED] 0xB083 (PANTHERLAKE)
[13:43:46] [PASSED] 0xB084 (PANTHERLAKE)
[13:43:46] [PASSED] 0xB085 (PANTHERLAKE)
[13:43:46] [PASSED] 0xB086 (PANTHERLAKE)
[13:43:46] [PASSED] 0xB087 (PANTHERLAKE)
[13:43:46] [PASSED] 0xB08F (PANTHERLAKE)
[13:43:46] [PASSED] 0xB090 (PANTHERLAKE)
[13:43:46] [PASSED] 0xB0A0 (PANTHERLAKE)
[13:43:46] [PASSED] 0xB0B0 (PANTHERLAKE)
[13:43:46] [PASSED] 0xFD80 (PANTHERLAKE)
[13:43:46] [PASSED] 0xFD81 (PANTHERLAKE)
[13:43:46] [PASSED] 0xD740 (NOVALAKE_S)
[13:43:46] [PASSED] 0xD741 (NOVALAKE_S)
[13:43:46] [PASSED] 0xD742 (NOVALAKE_S)
[13:43:46] [PASSED] 0xD743 (NOVALAKE_S)
[13:43:46] [PASSED] 0xD744 (NOVALAKE_S)
[13:43:46] [PASSED] 0xD745 (NOVALAKE_S)
[13:43:46] [PASSED] 0x674C (CRESCENTISLAND)
[13:43:46] [PASSED] 0x674D (CRESCENTISLAND)
[13:43:46] [PASSED] 0x674E (CRESCENTISLAND)
[13:43:46] [PASSED] 0x674F (CRESCENTISLAND)
[13:43:46] [PASSED] 0x6750 (CRESCENTISLAND)
[13:43:46] [PASSED] 0xD750 (NOVALAKE_P)
[13:43:46] [PASSED] 0xD751 (NOVALAKE_P)
[13:43:46] [PASSED] 0xD752 (NOVALAKE_P)
[13:43:46] [PASSED] 0xD753 (NOVALAKE_P)
[13:43:46] [PASSED] 0xD754 (NOVALAKE_P)
[13:43:46] [PASSED] 0xD755 (NOVALAKE_P)
[13:43:46] [PASSED] 0xD756 (NOVALAKE_P)
[13:43:46] [PASSED] 0xD757 (NOVALAKE_P)
[13:43:46] [PASSED] 0xD75F (NOVALAKE_P)
[13:43:46] =============== [PASSED] check_platform_desc ===============
[13:43:46] ===================== [PASSED] xe_pci ======================
[13:43:46] ============= xe_rtp_tables_test (4 subtests) ==============
[13:43:46] ================== xe_rtp_table_gt_test ===================
[13:43:46] [PASSED] gt_was/14011060649
[13:43:46] [PASSED] gt_was/14011059788
[13:43:46] [PASSED] gt_was/14015795083
[13:43:46] [PASSED] gt_was/16021867713
[13:43:46] [PASSED] gt_was/14019449301
[13:43:46] [PASSED] gt_was/16028005424
[13:43:46] [PASSED] gt_was/14026578760
[13:43:46] [PASSED] gt_was/1409420604
[13:43:46] [PASSED] gt_was/1408615072
[13:43:46] [PASSED] gt_was/22010523718
[13:43:46] [PASSED] gt_was/14011006942
[13:43:46] [PASSED] gt_was/14014830051
[13:43:46] [PASSED] gt_was/18018781329
[13:43:46] [PASSED] gt_was/1509235366
[13:43:46] [PASSED] gt_was/18018781329
[13:43:46] [PASSED] gt_was/16016694945
[13:43:46] [PASSED] gt_was/14018575942
[13:43:46] [PASSED] gt_was/22016670082
[13:43:46] [PASSED] gt_was/22016670082
[13:43:46] [PASSED] gt_was/14017421178
[13:43:46] [PASSED] gt_was/16025250150
[13:43:46] [PASSED] gt_was/14021871409
[13:43:46] [PASSED] gt_was/16021865536
[13:43:46] [PASSED] gt_was/14021486841
[13:43:46] [PASSED] gt_was/14025160223
[13:43:46] [PASSED] gt_was/14026144927, 16029437861
[13:43:46] [PASSED] gt_was/14025635424
[13:43:46] [PASSED] gt_was/16028005424
[13:43:46] ============== [PASSED] xe_rtp_table_gt_test ===============
[13:43:46] ================== xe_rtp_table_gt_test ===================
[13:43:46] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[13:43:46] [PASSED] gt_tunings/Tuning: 32B Access Enable
[13:43:46] [PASSED] gt_tunings/Tuning: L3 cache
[13:43:46] [PASSED] gt_tunings/Tuning: L3 cache - media
[13:43:46] [PASSED] gt_tunings/Tuning: Compression Overfetch
[13:43:46] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[13:43:46] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[13:43:46] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[13:43:46] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[13:43:46] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[13:43:46] [PASSED] gt_tunings/Tuning: Stateless compression control
[13:43:46] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[13:43:46] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[13:43:46] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[13:43:46] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[13:43:46] ============== [PASSED] xe_rtp_table_gt_test ===============
[13:43:46] ================== xe_rtp_table_oob_test ==================
[13:43:46] [PASSED] oob_was/1607983814
[13:43:46] [PASSED] oob_was/16010904313
[13:43:46] [PASSED] oob_was/18022495364
[13:43:46] [PASSED] oob_was/22012773006
[13:43:46] [PASSED] oob_was/14014475959
[13:43:46] [PASSED] oob_was/22011391025
[13:43:46] [PASSED] oob_was/22012727170
[13:43:46] [PASSED] oob_was/22012727685
[13:43:46] [PASSED] oob_was/22016596838
[13:43:46] [PASSED] oob_was/18020744125
[13:43:46] [PASSED] oob_was/1409600907
[13:43:46] [PASSED] oob_was/22014953428
[13:43:46] [PASSED] oob_was/16017236439
[13:43:46] [PASSED] oob_was/14019821291
[13:43:46] [PASSED] oob_was/14015076503
[13:43:46] [PASSED] oob_was/14018913170
[13:43:46] [PASSED] oob_was/14018094691
[13:43:46] [PASSED] oob_was/18024947630
[13:43:46] [PASSED] oob_was/16022287689
[13:43:46] [PASSED] oob_was/13011645652
[13:43:46] [PASSED] oob_was/14022293748
[13:43:46] [PASSED] oob_was/22019794406
[13:43:46] [PASSED] oob_was/22019338487
[13:43:46] [PASSED] oob_was/16023588340
[13:43:46] [PASSED] oob_was/14019789679
[13:43:46] [PASSED] oob_was/14022866841
[13:43:46] [PASSED] oob_was/16021333562
[13:43:46] [PASSED] oob_was/14016712196
[13:43:46] [PASSED] oob_was/14015568240
[13:43:46] [PASSED] oob_was/18013179988
[13:43:46] [PASSED] oob_was/1508761755
[13:43:46] [PASSED] oob_was/16023105232
[13:43:46] [PASSED] oob_was/16026508708
[13:43:46] [PASSED] oob_was/14020001231
[13:43:46] [PASSED] oob_was/16023683509
[13:43:46] [PASSED] oob_was/14025515070
[13:43:46] [PASSED] oob_was/15015404425_disable
[13:43:46] [PASSED] oob_was/16026007364
[13:43:46] [PASSED] oob_was/14020316580
[13:43:46] [PASSED] oob_was/14025883347
[13:43:46] ============== [PASSED] xe_rtp_table_oob_test ==============
[13:43:46] ================ xe_rtp_table_dev_oob_test ================
[13:43:46] [PASSED] device_oob_was/22010954014
[13:43:46] [PASSED] device_oob_was/15015404425
[13:43:46] [PASSED] device_oob_was/22019338487_display
[13:43:46] [PASSED] device_oob_was/14022085890
[13:43:46] [PASSED] device_oob_was/14026539277
[13:43:46] [PASSED] device_oob_was/14026633728
[13:43:46] [PASSED] device_oob_was/14026746987
[13:43:46] [PASSED] device_oob_was/14026779378
[13:43:46] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[13:43:46] =============== [PASSED] xe_rtp_tables_test ================
[13:43:46] =================== xe_rtp (3 subtests) ====================
[13:43:46] =================== xe_rtp_rules_tests ====================
[13:43:46] [PASSED] no
[13:43:46] [PASSED] yes
[13:43:46] [PASSED] no-and-no
[13:43:46] [PASSED] no-and-yes
[13:43:46] [PASSED] yes-and-no
[13:43:46] [PASSED] yes-and-yes
[13:43:46] [PASSED] no-or-no
[13:43:46] [PASSED] no-or-yes
[13:43:46] [PASSED] yes-or-no
[13:43:46] [PASSED] yes-or-yes
[13:43:46] [PASSED] no-yes-or-yes-no
[13:43:46] [PASSED] no-yes-or-yes-yes
[13:43:46] [PASSED] yes-yes-or-no-yes
[13:43:46] [PASSED] yes-yes-or-yes-yes
[13:43:46] [PASSED] no-no-or-yes-or-no
[13:43:46] [PASSED] or
[13:43:46] [PASSED] or-yes
[13:43:46] [PASSED] or-no
[13:43:46] [PASSED] yes-or
[13:43:46] [PASSED] no-or
[13:43:46] [PASSED] no-or-or-yes
[13:43:46] [PASSED] yes-or-or-no
[13:43:46] [PASSED] no-or-or-no
[13:43:46] [PASSED] missing-context-engine-class
[13:43:46] [PASSED] missing-context-engine-class-or-yes
[13:43:46] [PASSED] missing-context-engine-class-or-or-yes
[13:43:46] =============== [PASSED] xe_rtp_rules_tests ================
[13:43:46] =============== xe_rtp_process_to_sr_tests ================
[13:43:46] [PASSED] coalesce-same-reg
[13:43:46] [PASSED] no-match-no-add
[13:43:46] [PASSED] two-regs-two-entries
[13:43:46] [PASSED] clr-one-set-other
[13:43:46] [PASSED] set-field
[13:43:46] [PASSED] conflict-duplicate
[13:43:46] [PASSED] conflict-not-disjoint
[13:43:46] [PASSED] conflict-reg-type
[13:43:46] [PASSED] bad-mcr-reg-forced-to-regular
[13:43:46] [PASSED] bad-regular-reg-forced-to-mcr
[13:43:46] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[13:43:46] ================== xe_rtp_process_tests ===================
[13:43:46] [PASSED] active1
[13:43:46] [PASSED] active2
[13:43:46] [PASSED] active-inactive
[13:43:46] [PASSED] inactive-active
[13:43:46] [PASSED] inactive-active-inactive
[13:43:46] [PASSED] inactive-inactive-inactive
[13:43:46] ============== [PASSED] xe_rtp_process_tests ===============
[13:43:46] ===================== [PASSED] xe_rtp ======================
[13:43:46] ==================== xe_wa (1 subtest) =====================
[13:43:46] ======================== xe_wa_gt =========================
[13:43:46] [PASSED] TIGERLAKE B0
[13:43:46] [PASSED] DG1 A0
[13:43:46] [PASSED] DG1 B0
[13:43:46] [PASSED] ALDERLAKE_S A0
[13:43:46] [PASSED] ALDERLAKE_S B0
[13:43:46] [PASSED] ALDERLAKE_S C0
[13:43:46] [PASSED] ALDERLAKE_S D0
[13:43:46] [PASSED] ALDERLAKE_P A0
[13:43:46] [PASSED] ALDERLAKE_P B0
[13:43:46] [PASSED] ALDERLAKE_P C0
[13:43:46] [PASSED] ALDERLAKE_S RPLS D0
[13:43:46] [PASSED] ALDERLAKE_P RPLU E0
[13:43:46] [PASSED] DG2 G10 C0
[13:43:46] [PASSED] DG2 G11 B1
[13:43:46] [PASSED] DG2 G12 A1
[13:43:46] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[13:43:46] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[13:43:46] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[13:43:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[13:43:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[13:43:46] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[13:43:46] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[13:43:46] ==================== [PASSED] xe_wa_gt =====================
[13:43:46] ====================== [PASSED] xe_wa ======================
[13:43:46] ============================================================
[13:43:46] Testing complete. Ran 715 tests: passed: 697, skipped: 18
[13:43:46] Elapsed time: 36.813s total, 4.273s configuring, 31.873s building, 0.635s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[13:43:46] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:43:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:44:14] Starting KUnit Kernel (1/1)...
[13:44:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:44:14] ============ drm_test_pick_cmdline (2 subtests) ============
[13:44:14] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[13:44:14] =============== drm_test_pick_cmdline_named ===============
[13:44:14] [PASSED] NTSC
[13:44:14] [PASSED] NTSC-J
[13:44:14] [PASSED] PAL
[13:44:14] [PASSED] PAL-M
[13:44:14] =========== [PASSED] drm_test_pick_cmdline_named ===========
[13:44:14] ============== [PASSED] drm_test_pick_cmdline ==============
[13:44:14] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[13:44:14] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[13:44:14] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[13:44:14] =========== drm_validate_clone_mode (2 subtests) ===========
[13:44:14] ============== drm_test_check_in_clone_mode ===============
[13:44:14] [PASSED] in_clone_mode
[13:44:14] [PASSED] not_in_clone_mode
[13:44:14] ========== [PASSED] drm_test_check_in_clone_mode ===========
[13:44:14] =============== drm_test_check_valid_clones ===============
[13:44:14] [PASSED] not_in_clone_mode
[13:44:14] [PASSED] valid_clone
[13:44:14] [PASSED] invalid_clone
[13:44:14] =========== [PASSED] drm_test_check_valid_clones ===========
[13:44:14] ============= [PASSED] drm_validate_clone_mode =============
[13:44:14] ============= drm_validate_modeset (1 subtest) =============
[13:44:14] [PASSED] drm_test_check_connector_changed_modeset
[13:44:14] ============== [PASSED] drm_validate_modeset ===============
[13:44:14] ====== drm_test_bridge_get_current_state (2 subtests) ======
[13:44:14] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[13:44:14] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[13:44:14] ======== [PASSED] drm_test_bridge_get_current_state ========
[13:44:14] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[13:44:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[13:44:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[13:44:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[13:44:14] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[13:44:14] ============== drm_bridge_alloc (2 subtests) ===============
[13:44:14] [PASSED] drm_test_drm_bridge_alloc_basic
[13:44:14] [PASSED] drm_test_drm_bridge_alloc_get_put
[13:44:14] ================ [PASSED] drm_bridge_alloc =================
[13:44:14] ============= drm_cmdline_parser (40 subtests) =============
[13:44:14] [PASSED] drm_test_cmdline_force_d_only
[13:44:14] [PASSED] drm_test_cmdline_force_D_only_dvi
[13:44:14] [PASSED] drm_test_cmdline_force_D_only_hdmi
[13:44:14] [PASSED] drm_test_cmdline_force_D_only_not_digital
[13:44:14] [PASSED] drm_test_cmdline_force_e_only
[13:44:14] [PASSED] drm_test_cmdline_res
[13:44:14] [PASSED] drm_test_cmdline_res_vesa
[13:44:14] [PASSED] drm_test_cmdline_res_vesa_rblank
[13:44:14] [PASSED] drm_test_cmdline_res_rblank
[13:44:14] [PASSED] drm_test_cmdline_res_bpp
[13:44:14] [PASSED] drm_test_cmdline_res_refresh
[13:44:14] [PASSED] drm_test_cmdline_res_bpp_refresh
[13:44:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[13:44:14] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[13:44:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[13:44:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[13:44:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[13:44:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[13:44:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[13:44:14] [PASSED] drm_test_cmdline_res_margins_force_on
[13:44:14] [PASSED] drm_test_cmdline_res_vesa_margins
[13:44:14] [PASSED] drm_test_cmdline_name
[13:44:14] [PASSED] drm_test_cmdline_name_bpp
[13:44:14] [PASSED] drm_test_cmdline_name_option
[13:44:14] [PASSED] drm_test_cmdline_name_bpp_option
[13:44:14] [PASSED] drm_test_cmdline_rotate_0
[13:44:14] [PASSED] drm_test_cmdline_rotate_90
[13:44:14] [PASSED] drm_test_cmdline_rotate_180
[13:44:14] [PASSED] drm_test_cmdline_rotate_270
[13:44:14] [PASSED] drm_test_cmdline_hmirror
[13:44:14] [PASSED] drm_test_cmdline_vmirror
[13:44:14] [PASSED] drm_test_cmdline_margin_options
[13:44:14] [PASSED] drm_test_cmdline_multiple_options
[13:44:14] [PASSED] drm_test_cmdline_bpp_extra_and_option
[13:44:14] [PASSED] drm_test_cmdline_extra_and_option
[13:44:14] [PASSED] drm_test_cmdline_freestanding_options
[13:44:14] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[13:44:14] [PASSED] drm_test_cmdline_panel_orientation
[13:44:14] ================ drm_test_cmdline_invalid =================
[13:44:14] [PASSED] margin_only
[13:44:14] [PASSED] interlace_only
[13:44:14] [PASSED] res_missing_x
[13:44:14] [PASSED] res_missing_y
[13:44:14] [PASSED] res_bad_y
[13:44:14] [PASSED] res_missing_y_bpp
[13:44:14] [PASSED] res_bad_bpp
[13:44:14] [PASSED] res_bad_refresh
[13:44:14] [PASSED] res_bpp_refresh_force_on_off
[13:44:14] [PASSED] res_invalid_mode
[13:44:14] [PASSED] res_bpp_wrong_place_mode
[13:44:14] [PASSED] name_bpp_refresh
[13:44:14] [PASSED] name_refresh
[13:44:14] [PASSED] name_refresh_wrong_mode
[13:44:14] [PASSED] name_refresh_invalid_mode
[13:44:14] [PASSED] rotate_multiple
[13:44:14] [PASSED] rotate_invalid_val
[13:44:14] [PASSED] rotate_truncated
[13:44:14] [PASSED] invalid_option
[13:44:14] [PASSED] invalid_tv_option
[13:44:14] [PASSED] truncated_tv_option
[13:44:14] ============ [PASSED] drm_test_cmdline_invalid =============
[13:44:14] =============== drm_test_cmdline_tv_options ===============
[13:44:14] [PASSED] NTSC
[13:44:14] [PASSED] NTSC_443
[13:44:14] [PASSED] NTSC_J
[13:44:14] [PASSED] PAL
[13:44:14] [PASSED] PAL_M
[13:44:14] [PASSED] PAL_N
[13:44:14] [PASSED] SECAM
[13:44:14] [PASSED] MONO_525
[13:44:14] [PASSED] MONO_625
[13:44:14] =========== [PASSED] drm_test_cmdline_tv_options ===========
[13:44:14] =============== [PASSED] drm_cmdline_parser ================
[13:44:14] ========== drmm_connector_hdmi_init (20 subtests) ==========
[13:44:14] [PASSED] drm_test_connector_hdmi_init_valid
[13:44:14] [PASSED] drm_test_connector_hdmi_init_bpc_8
[13:44:14] [PASSED] drm_test_connector_hdmi_init_bpc_10
[13:44:14] [PASSED] drm_test_connector_hdmi_init_bpc_12
[13:44:14] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[13:44:14] [PASSED] drm_test_connector_hdmi_init_bpc_null
[13:44:14] [PASSED] drm_test_connector_hdmi_init_formats_empty
[13:44:14] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[13:44:14] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[13:44:14] [PASSED] supported_formats=0x9 yuv420_allowed=1
[13:44:14] [PASSED] supported_formats=0x9 yuv420_allowed=0
[13:44:14] [PASSED] supported_formats=0x5 yuv420_allowed=1
[13:44:14] [PASSED] supported_formats=0x5 yuv420_allowed=0
[13:44:14] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[13:44:14] [PASSED] drm_test_connector_hdmi_init_null_ddc
[13:44:14] [PASSED] drm_test_connector_hdmi_init_null_product
[13:44:14] [PASSED] drm_test_connector_hdmi_init_null_vendor
[13:44:14] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[13:44:14] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[13:44:14] [PASSED] drm_test_connector_hdmi_init_product_valid
[13:44:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[13:44:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[13:44:14] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[13:44:14] ========= drm_test_connector_hdmi_init_type_valid =========
[13:44:14] [PASSED] HDMI-A
[13:44:14] [PASSED] HDMI-B
[13:44:14] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[13:44:14] ======== drm_test_connector_hdmi_init_type_invalid ========
[13:44:14] [PASSED] Unknown
[13:44:14] [PASSED] VGA
[13:44:14] [PASSED] DVI-I
[13:44:14] [PASSED] DVI-D
[13:44:14] [PASSED] DVI-A
[13:44:14] [PASSED] Composite
[13:44:14] [PASSED] SVIDEO
[13:44:14] [PASSED] LVDS
[13:44:14] [PASSED] Component
[13:44:14] [PASSED] DIN
[13:44:14] [PASSED] DP
[13:44:14] [PASSED] TV
[13:44:14] [PASSED] eDP
[13:44:14] [PASSED] Virtual
[13:44:14] [PASSED] DSI
[13:44:14] [PASSED] DPI
[13:44:14] [PASSED] Writeback
[13:44:14] [PASSED] SPI
[13:44:14] [PASSED] USB
[13:44:14] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[13:44:14] ============ [PASSED] drmm_connector_hdmi_init =============
[13:44:14] ============= drmm_connector_init (3 subtests) =============
[13:44:14] [PASSED] drm_test_drmm_connector_init
[13:44:14] [PASSED] drm_test_drmm_connector_init_null_ddc
[13:44:14] ========= drm_test_drmm_connector_init_type_valid =========
[13:44:14] [PASSED] Unknown
[13:44:14] [PASSED] VGA
[13:44:14] [PASSED] DVI-I
[13:44:14] [PASSED] DVI-D
[13:44:14] [PASSED] DVI-A
[13:44:14] [PASSED] Composite
[13:44:14] [PASSED] SVIDEO
[13:44:14] [PASSED] LVDS
[13:44:14] [PASSED] Component
[13:44:14] [PASSED] DIN
[13:44:14] [PASSED] DP
[13:44:14] [PASSED] HDMI-A
[13:44:14] [PASSED] HDMI-B
[13:44:14] [PASSED] TV
[13:44:14] [PASSED] eDP
[13:44:14] [PASSED] Virtual
[13:44:14] [PASSED] DSI
[13:44:14] [PASSED] DPI
[13:44:14] [PASSED] Writeback
[13:44:14] [PASSED] SPI
[13:44:14] [PASSED] USB
[13:44:14] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[13:44:14] =============== [PASSED] drmm_connector_init ===============
[13:44:14] ========= drm_connector_dynamic_init (6 subtests) ==========
[13:44:14] [PASSED] drm_test_drm_connector_dynamic_init
[13:44:14] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[13:44:14] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[13:44:14] [PASSED] drm_test_drm_connector_dynamic_init_properties
[13:44:14] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[13:44:14] [PASSED] Unknown
[13:44:14] [PASSED] VGA
[13:44:14] [PASSED] DVI-I
[13:44:14] [PASSED] DVI-D
[13:44:14] [PASSED] DVI-A
[13:44:14] [PASSED] Composite
[13:44:14] [PASSED] SVIDEO
[13:44:14] [PASSED] LVDS
[13:44:14] [PASSED] Component
[13:44:14] [PASSED] DIN
[13:44:14] [PASSED] DP
[13:44:14] [PASSED] HDMI-A
[13:44:14] [PASSED] HDMI-B
[13:44:14] [PASSED] TV
[13:44:14] [PASSED] eDP
[13:44:14] [PASSED] Virtual
[13:44:14] [PASSED] DSI
[13:44:14] [PASSED] DPI
[13:44:14] [PASSED] Writeback
[13:44:14] [PASSED] SPI
[13:44:14] [PASSED] USB
[13:44:14] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[13:44:14] ======== drm_test_drm_connector_dynamic_init_name =========
[13:44:14] [PASSED] Unknown
[13:44:14] [PASSED] VGA
[13:44:14] [PASSED] DVI-I
[13:44:14] [PASSED] DVI-D
[13:44:14] [PASSED] DVI-A
[13:44:14] [PASSED] Composite
[13:44:14] [PASSED] SVIDEO
[13:44:14] [PASSED] LVDS
[13:44:14] [PASSED] Component
[13:44:14] [PASSED] DIN
[13:44:14] [PASSED] DP
[13:44:14] [PASSED] HDMI-A
[13:44:14] [PASSED] HDMI-B
[13:44:14] [PASSED] TV
[13:44:14] [PASSED] eDP
[13:44:14] [PASSED] Virtual
[13:44:14] [PASSED] DSI
[13:44:14] [PASSED] DPI
[13:44:14] [PASSED] Writeback
[13:44:14] [PASSED] SPI
[13:44:14] [PASSED] USB
[13:44:14] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[13:44:14] =========== [PASSED] drm_connector_dynamic_init ============
[13:44:14] ==== drm_connector_dynamic_register_early (4 subtests) =====
[13:44:14] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[13:44:14] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[13:44:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[13:44:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[13:44:14] ====== [PASSED] drm_connector_dynamic_register_early =======
[13:44:14] ======= drm_connector_dynamic_register (7 subtests) ========
[13:44:14] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[13:44:14] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[13:44:14] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[13:44:14] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[13:44:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[13:44:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[13:44:14] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[13:44:14] ========= [PASSED] drm_connector_dynamic_register ==========
[13:44:14] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[13:44:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[13:44:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[13:44:14] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[13:44:14] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[13:44:14] ========== drm_test_get_tv_mode_from_name_valid ===========
[13:44:14] [PASSED] NTSC
[13:44:14] [PASSED] NTSC-443
[13:44:14] [PASSED] NTSC-J
[13:44:14] [PASSED] PAL
[13:44:14] [PASSED] PAL-M
[13:44:14] [PASSED] PAL-N
[13:44:14] [PASSED] SECAM
[13:44:14] [PASSED] Mono
[13:44:14] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[13:44:14] [PASSED] drm_test_get_tv_mode_from_name_truncated
[13:44:14] ============ [PASSED] drm_get_tv_mode_from_name ============
[13:44:14] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[13:44:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[13:44:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[13:44:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[13:44:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[13:44:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[13:44:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[13:44:14] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[13:44:14] [PASSED] VIC 96
[13:44:14] [PASSED] VIC 97
[13:44:14] [PASSED] VIC 101
[13:44:14] [PASSED] VIC 102
[13:44:14] [PASSED] VIC 106
[13:44:14] [PASSED] VIC 107
[13:44:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[13:44:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[13:44:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[13:44:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[13:44:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[13:44:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[13:44:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[13:44:14] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[13:44:14] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[13:44:14] [PASSED] Automatic
[13:44:14] [PASSED] Full
[13:44:14] [PASSED] Limited 16:235
[13:44:14] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[13:44:14] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[13:44:14] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[13:44:14] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[13:44:14] === drm_test_drm_hdmi_connector_get_output_format_name ====
[13:44:14] [PASSED] RGB
[13:44:14] [PASSED] YUV 4:2:0
[13:44:14] [PASSED] YUV 4:2:2
[13:44:14] [PASSED] YUV 4:4:4
[13:44:14] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[13:44:14] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[13:44:14] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[13:44:14] ============= drm_damage_helper (21 subtests) ==============
[13:44:14] [PASSED] drm_test_damage_iter_no_damage
[13:44:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[13:44:14] [PASSED] drm_test_damage_iter_no_damage_src_moved
[13:44:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[13:44:14] [PASSED] drm_test_damage_iter_no_damage_not_visible
[13:44:14] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[13:44:14] [PASSED] drm_test_damage_iter_no_damage_no_fb
[13:44:14] [PASSED] drm_test_damage_iter_simple_damage
[13:44:14] [PASSED] drm_test_damage_iter_single_damage
[13:44:14] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[13:44:14] [PASSED] drm_test_damage_iter_single_damage_outside_src
[13:44:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[13:44:14] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[13:44:14] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[13:44:14] [PASSED] drm_test_damage_iter_single_damage_src_moved
[13:44:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[13:44:14] [PASSED] drm_test_damage_iter_damage
[13:44:14] [PASSED] drm_test_damage_iter_damage_one_intersect
[13:44:14] [PASSED] drm_test_damage_iter_damage_one_outside
[13:44:14] [PASSED] drm_test_damage_iter_damage_src_moved
[13:44:14] [PASSED] drm_test_damage_iter_damage_not_visible
[13:44:14] ================ [PASSED] drm_damage_helper ================
[13:44:14] ============== drm_dp_mst_helper (3 subtests) ==============
[13:44:14] ============== drm_test_dp_mst_calc_pbn_mode ==============
[13:44:14] [PASSED] Clock 154000 BPP 30 DSC disabled
[13:44:14] [PASSED] Clock 234000 BPP 30 DSC disabled
[13:44:14] [PASSED] Clock 297000 BPP 24 DSC disabled
[13:44:14] [PASSED] Clock 332880 BPP 24 DSC enabled
[13:44:14] [PASSED] Clock 324540 BPP 24 DSC enabled
[13:44:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[13:44:14] ============== drm_test_dp_mst_calc_pbn_div ===============
[13:44:14] [PASSED] Link rate 2000000 lane count 4
[13:44:14] [PASSED] Link rate 2000000 lane count 2
[13:44:14] [PASSED] Link rate 2000000 lane count 1
[13:44:14] [PASSED] Link rate 1350000 lane count 4
[13:44:14] [PASSED] Link rate 1350000 lane count 2
[13:44:14] [PASSED] Link rate 1350000 lane count 1
[13:44:14] [PASSED] Link rate 1000000 lane count 4
[13:44:14] [PASSED] Link rate 1000000 lane count 2
[13:44:14] [PASSED] Link rate 1000000 lane count 1
[13:44:14] [PASSED] Link rate 810000 lane count 4
[13:44:14] [PASSED] Link rate 810000 lane count 2
[13:44:14] [PASSED] Link rate 810000 lane count 1
[13:44:14] [PASSED] Link rate 540000 lane count 4
[13:44:14] [PASSED] Link rate 540000 lane count 2
[13:44:14] [PASSED] Link rate 540000 lane count 1
[13:44:14] [PASSED] Link rate 270000 lane count 4
[13:44:14] [PASSED] Link rate 270000 lane count 2
[13:44:14] [PASSED] Link rate 270000 lane count 1
[13:44:14] [PASSED] Link rate 162000 lane count 4
[13:44:14] [PASSED] Link rate 162000 lane count 2
[13:44:14] [PASSED] Link rate 162000 lane count 1
[13:44:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[13:44:14] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[13:44:14] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[13:44:14] [PASSED] DP_POWER_UP_PHY with port number
[13:44:14] [PASSED] DP_POWER_DOWN_PHY with port number
[13:44:14] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[13:44:14] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[13:44:14] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[13:44:14] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[13:44:14] [PASSED] DP_QUERY_PAYLOAD with port number
[13:44:14] [PASSED] DP_QUERY_PAYLOAD with VCPI
[13:44:14] [PASSED] DP_REMOTE_DPCD_READ with port number
[13:44:14] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[13:44:14] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[13:44:14] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[13:44:14] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[13:44:14] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[13:44:14] [PASSED] DP_REMOTE_I2C_READ with port number
[13:44:14] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[13:44:14] [PASSED] DP_REMOTE_I2C_READ with transactions array
[13:44:14] [PASSED] DP_REMOTE_I2C_WRITE with port number
[13:44:14] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[13:44:14] [PASSED] DP_REMOTE_I2C_WRITE with data array
[13:44:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[13:44:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[13:44:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[13:44:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[13:44:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[13:44:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[13:44:14] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[13:44:14] ================ [PASSED] drm_dp_mst_helper ================
[13:44:14] ================== drm_exec (7 subtests) ===================
[13:44:14] [PASSED] sanitycheck
[13:44:14] [PASSED] test_lock
[13:44:14] [PASSED] test_lock_unlock
[13:44:14] [PASSED] test_duplicates
[13:44:14] [PASSED] test_prepare
[13:44:14] [PASSED] test_prepare_array
[13:44:14] [PASSED] test_multiple_loops
[13:44:14] ==================== [PASSED] drm_exec =====================
[13:44:14] =========== drm_format_helper_test (17 subtests) ===========
[13:44:14] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[13:44:14] [PASSED] single_pixel_source_buffer
[13:44:14] [PASSED] single_pixel_clip_rectangle
[13:44:14] [PASSED] well_known_colors
[13:44:14] [PASSED] destination_pitch
[13:44:14] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[13:44:14] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[13:44:14] [PASSED] single_pixel_source_buffer
[13:44:14] [PASSED] single_pixel_clip_rectangle
[13:44:14] [PASSED] well_known_colors
[13:44:14] [PASSED] destination_pitch
[13:44:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[13:44:14] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[13:44:14] [PASSED] single_pixel_source_buffer
[13:44:14] [PASSED] single_pixel_clip_rectangle
[13:44:14] [PASSED] well_known_colors
[13:44:14] [PASSED] destination_pitch
[13:44:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[13:44:14] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[13:44:14] [PASSED] single_pixel_source_buffer
[13:44:14] [PASSED] single_pixel_clip_rectangle
[13:44:14] [PASSED] well_known_colors
[13:44:14] [PASSED] destination_pitch
[13:44:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[13:44:14] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[13:44:14] [PASSED] single_pixel_source_buffer
[13:44:14] [PASSED] single_pixel_clip_rectangle
[13:44:14] [PASSED] well_known_colors
[13:44:14] [PASSED] destination_pitch
[13:44:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[13:44:14] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[13:44:14] [PASSED] single_pixel_source_buffer
[13:44:14] [PASSED] single_pixel_clip_rectangle
[13:44:14] [PASSED] well_known_colors
[13:44:14] [PASSED] destination_pitch
[13:44:14] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[13:44:14] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[13:44:14] [PASSED] single_pixel_source_buffer
[13:44:14] [PASSED] single_pixel_clip_rectangle
[13:44:14] [PASSED] well_known_colors
[13:44:14] [PASSED] destination_pitch
[13:44:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[13:44:14] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[13:44:14] [PASSED] single_pixel_source_buffer
[13:44:14] [PASSED] single_pixel_clip_rectangle
[13:44:14] [PASSED] well_known_colors
[13:44:14] [PASSED] destination_pitch
[13:44:14] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[13:44:14] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[13:44:14] [PASSED] single_pixel_source_buffer
[13:44:14] [PASSED] single_pixel_clip_rectangle
[13:44:14] [PASSED] well_known_colors
[13:44:14] [PASSED] destination_pitch
[13:44:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[13:44:14] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[13:44:14] [PASSED] single_pixel_source_buffer
[13:44:14] [PASSED] single_pixel_clip_rectangle
[13:44:14] [PASSED] well_known_colors
[13:44:14] [PASSED] destination_pitch
[13:44:14] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[13:44:14] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[13:44:14] [PASSED] single_pixel_source_buffer
[13:44:14] [PASSED] single_pixel_clip_rectangle
[13:44:14] [PASSED] well_known_colors
[13:44:14] [PASSED] destination_pitch
[13:44:14] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[13:44:14] ============== drm_test_fb_xrgb8888_to_mono ===============
[13:44:14] [PASSED] single_pixel_source_buffer
[13:44:14] [PASSED] single_pixel_clip_rectangle
[13:44:14] [PASSED] well_known_colors
[13:44:14] [PASSED] destination_pitch
[13:44:14] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[13:44:14] ==================== drm_test_fb_swab =====================
[13:44:14] [PASSED] single_pixel_source_buffer
[13:44:14] [PASSED] single_pixel_clip_rectangle
[13:44:14] [PASSED] well_known_colors
[13:44:14] [PASSED] destination_pitch
[13:44:14] ================ [PASSED] drm_test_fb_swab =================
[13:44:14] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[13:44:14] [PASSED] single_pixel_source_buffer
[13:44:14] [PASSED] single_pixel_clip_rectangle
[13:44:14] [PASSED] well_known_colors
[13:44:14] [PASSED] destination_pitch
[13:44:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[13:44:14] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[13:44:14] [PASSED] single_pixel_source_buffer
[13:44:14] [PASSED] single_pixel_clip_rectangle
[13:44:14] [PASSED] well_known_colors
[13:44:14] [PASSED] destination_pitch
[13:44:14] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[13:44:14] ================= drm_test_fb_clip_offset =================
[13:44:14] [PASSED] pass through
[13:44:14] [PASSED] horizontal offset
[13:44:14] [PASSED] vertical offset
[13:44:14] [PASSED] horizontal and vertical offset
[13:44:14] [PASSED] horizontal offset (custom pitch)
[13:44:14] [PASSED] vertical offset (custom pitch)
[13:44:14] [PASSED] horizontal and vertical offset (custom pitch)
[13:44:14] ============= [PASSED] drm_test_fb_clip_offset =============
[13:44:14] =================== drm_test_fb_memcpy ====================
[13:44:14] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[13:44:14] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[13:44:14] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[13:44:14] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[13:44:14] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[13:44:14] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[13:44:14] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[13:44:14] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[13:44:14] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[13:44:14] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[13:44:14] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[13:44:14] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[13:44:14] =============== [PASSED] drm_test_fb_memcpy ================
[13:44:14] ============= [PASSED] drm_format_helper_test ==============
[13:44:14] ================= drm_format (18 subtests) =================
[13:44:14] [PASSED] drm_test_format_block_width_invalid
[13:44:14] [PASSED] drm_test_format_block_width_one_plane
[13:44:14] [PASSED] drm_test_format_block_width_two_plane
[13:44:14] [PASSED] drm_test_format_block_width_three_plane
[13:44:14] [PASSED] drm_test_format_block_width_tiled
[13:44:14] [PASSED] drm_test_format_block_height_invalid
[13:44:14] [PASSED] drm_test_format_block_height_one_plane
[13:44:14] [PASSED] drm_test_format_block_height_two_plane
[13:44:14] [PASSED] drm_test_format_block_height_three_plane
[13:44:14] [PASSED] drm_test_format_block_height_tiled
[13:44:14] [PASSED] drm_test_format_min_pitch_invalid
[13:44:14] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[13:44:14] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[13:44:14] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[13:44:14] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[13:44:14] [PASSED] drm_test_format_min_pitch_two_plane
[13:44:14] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[13:44:14] [PASSED] drm_test_format_min_pitch_tiled
[13:44:14] =================== [PASSED] drm_format ====================
[13:44:14] ============== drm_framebuffer (10 subtests) ===============
[13:44:14] ========== drm_test_framebuffer_check_src_coords ==========
[13:44:14] [PASSED] Success: source fits into fb
[13:44:14] [PASSED] Fail: overflowing fb with x-axis coordinate
[13:44:14] [PASSED] Fail: overflowing fb with y-axis coordinate
[13:44:14] [PASSED] Fail: overflowing fb with source width
[13:44:14] [PASSED] Fail: overflowing fb with source height
[13:44:14] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[13:44:14] [PASSED] drm_test_framebuffer_cleanup
[13:44:14] =============== drm_test_framebuffer_create ===============
[13:44:14] [PASSED] ABGR8888 normal sizes
[13:44:14] [PASSED] ABGR8888 max sizes
[13:44:14] [PASSED] ABGR8888 pitch greater than min required
[13:44:14] [PASSED] ABGR8888 pitch less than min required
[13:44:14] [PASSED] ABGR8888 Invalid width
[13:44:14] [PASSED] ABGR8888 Invalid buffer handle
[13:44:14] [PASSED] No pixel format
[13:44:14] [PASSED] ABGR8888 Width 0
[13:44:14] [PASSED] ABGR8888 Height 0
[13:44:14] [PASSED] ABGR8888 Out of bound height * pitch combination
[13:44:14] [PASSED] ABGR8888 Large buffer offset
[13:44:14] [PASSED] ABGR8888 Buffer offset for inexistent plane
[13:44:14] [PASSED] ABGR8888 Invalid flag
[13:44:14] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[13:44:14] [PASSED] ABGR8888 Valid buffer modifier
[13:44:14] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[13:44:14] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[13:44:14] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[13:44:14] [PASSED] NV12 Normal sizes
[13:44:14] [PASSED] NV12 Max sizes
[13:44:14] [PASSED] NV12 Invalid pitch
[13:44:14] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[13:44:14] [PASSED] NV12 different modifier per-plane
[13:44:14] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[13:44:14] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[13:44:14] [PASSED] NV12 Modifier for inexistent plane
[13:44:14] [PASSED] NV12 Handle for inexistent plane
[13:44:14] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[13:44:14] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[13:44:14] [PASSED] YVU420 Normal sizes
[13:44:14] [PASSED] YVU420 Max sizes
[13:44:14] [PASSED] YVU420 Invalid pitch
[13:44:14] [PASSED] YVU420 Different pitches
[13:44:14] [PASSED] YVU420 Different buffer offsets/pitches
[13:44:14] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[13:44:14] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[13:44:14] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[13:44:14] [PASSED] YVU420 Valid modifier
[13:44:14] [PASSED] YVU420 Different modifiers per plane
[13:44:14] [PASSED] YVU420 Modifier for inexistent plane
[13:44:14] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[13:44:14] [PASSED] X0L2 Normal sizes
[13:44:14] [PASSED] X0L2 Max sizes
[13:44:14] [PASSED] X0L2 Invalid pitch
[13:44:14] [PASSED] X0L2 Pitch greater than minimum required
[13:44:14] [PASSED] X0L2 Handle for inexistent plane
[13:44:14] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[13:44:14] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[13:44:14] [PASSED] X0L2 Valid modifier
[13:44:14] [PASSED] X0L2 Modifier for inexistent plane
[13:44:14] =========== [PASSED] drm_test_framebuffer_create ===========
[13:44:14] [PASSED] drm_test_framebuffer_free
[13:44:14] [PASSED] drm_test_framebuffer_init
[13:44:14] [PASSED] drm_test_framebuffer_init_bad_format
[13:44:14] [PASSED] drm_test_framebuffer_init_dev_mismatch
[13:44:14] [PASSED] drm_test_framebuffer_lookup
[13:44:14] [PASSED] drm_test_framebuffer_lookup_inexistent
[13:44:14] [PASSED] drm_test_framebuffer_modifiers_not_supported
[13:44:14] ================= [PASSED] drm_framebuffer =================
[13:44:14] ================ drm_gem_shmem (8 subtests) ================
[13:44:14] [PASSED] drm_gem_shmem_test_obj_create
[13:44:14] [PASSED] drm_gem_shmem_test_obj_create_private
[13:44:14] [PASSED] drm_gem_shmem_test_pin_pages
[13:44:14] [PASSED] drm_gem_shmem_test_vmap
[13:44:14] [PASSED] drm_gem_shmem_test_get_sg_table
[13:44:14] [PASSED] drm_gem_shmem_test_get_pages_sgt
[13:44:14] [PASSED] drm_gem_shmem_test_madvise
[13:44:14] [PASSED] drm_gem_shmem_test_purge
[13:44:14] ================== [PASSED] drm_gem_shmem ==================
[13:44:14] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[13:44:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[13:44:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[13:44:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[13:44:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[13:44:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[13:44:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[13:44:14] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[13:44:14] [PASSED] Automatic
[13:44:14] [PASSED] Full
[13:44:14] [PASSED] Limited 16:235
[13:44:14] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[13:44:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[13:44:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[13:44:14] [PASSED] drm_test_check_disable_connector
[13:44:14] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[13:44:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[13:44:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[13:44:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[13:44:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[13:44:14] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[13:44:14] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[13:44:14] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[13:44:14] [PASSED] drm_test_check_output_bpc_dvi
[13:44:14] [PASSED] drm_test_check_output_bpc_format_vic_1
[13:44:14] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[13:44:14] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[13:44:14] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[13:44:14] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[13:44:14] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[13:44:14] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[13:44:14] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[13:44:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[13:44:14] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[13:44:14] [PASSED] drm_test_check_broadcast_rgb_value
[13:44:14] [PASSED] drm_test_check_bpc_8_value
[13:44:14] [PASSED] drm_test_check_bpc_10_value
[13:44:14] [PASSED] drm_test_check_bpc_12_value
[13:44:14] [PASSED] drm_test_check_format_value
[13:44:14] [PASSED] drm_test_check_tmds_char_value
[13:44:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[13:44:14] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[13:44:14] [PASSED] drm_test_check_mode_valid
[13:44:14] [PASSED] drm_test_check_mode_valid_reject
[13:44:14] [PASSED] drm_test_check_mode_valid_reject_rate
[13:44:14] [PASSED] drm_test_check_mode_valid_reject_max_clock
[13:44:14] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[13:44:14] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[13:44:14] [PASSED] drm_test_check_infoframes
[13:44:14] [PASSED] drm_test_check_reject_avi_infoframe
[13:44:14] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[13:44:14] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[13:44:14] [PASSED] drm_test_check_reject_audio_infoframe
[13:44:14] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[13:44:14] ================= drm_managed (2 subtests) =================
[13:44:14] [PASSED] drm_test_managed_release_action
[13:44:14] [PASSED] drm_test_managed_run_action
[13:44:14] =================== [PASSED] drm_managed ===================
[13:44:14] =================== drm_mm (6 subtests) ====================
[13:44:14] [PASSED] drm_test_mm_init
[13:44:14] [PASSED] drm_test_mm_debug
[13:44:14] [PASSED] drm_test_mm_align32
[13:44:14] [PASSED] drm_test_mm_align64
[13:44:14] [PASSED] drm_test_mm_lowest
[13:44:14] [PASSED] drm_test_mm_highest
[13:44:14] ===================== [PASSED] drm_mm ======================
[13:44:14] ============= drm_modes_analog_tv (5 subtests) =============
[13:44:14] [PASSED] drm_test_modes_analog_tv_mono_576i
[13:44:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[13:44:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[13:44:14] [PASSED] drm_test_modes_analog_tv_pal_576i
[13:44:14] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[13:44:14] =============== [PASSED] drm_modes_analog_tv ===============
[13:44:14] ============== drm_plane_helper (2 subtests) ===============
[13:44:14] =============== drm_test_check_plane_state ================
[13:44:14] [PASSED] clipping_simple
[13:44:14] [PASSED] clipping_rotate_reflect
[13:44:14] [PASSED] positioning_simple
[13:44:14] [PASSED] upscaling
[13:44:14] [PASSED] downscaling
[13:44:14] [PASSED] rounding1
[13:44:14] [PASSED] rounding2
[13:44:14] [PASSED] rounding3
[13:44:14] [PASSED] rounding4
[13:44:14] =========== [PASSED] drm_test_check_plane_state ============
[13:44:14] =========== drm_test_check_invalid_plane_state ============
[13:44:14] [PASSED] positioning_invalid
[13:44:14] [PASSED] upscaling_invalid
[13:44:14] [PASSED] downscaling_invalid
[13:44:14] ======= [PASSED] drm_test_check_invalid_plane_state ========
[13:44:14] ================ [PASSED] drm_plane_helper =================
[13:44:14] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[13:44:14] ====== drm_test_connector_helper_tv_get_modes_check =======
[13:44:14] [PASSED] None
[13:44:14] [PASSED] PAL
[13:44:14] [PASSED] NTSC
[13:44:14] [PASSED] Both, NTSC Default
[13:44:14] [PASSED] Both, PAL Default
[13:44:14] [PASSED] Both, NTSC Default, with PAL on command-line
[13:44:14] [PASSED] Both, PAL Default, with NTSC on command-line
[13:44:14] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[13:44:14] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[13:44:14] ================== drm_rect (9 subtests) ===================
[13:44:14] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[13:44:14] [PASSED] drm_test_rect_clip_scaled_not_clipped
[13:44:14] [PASSED] drm_test_rect_clip_scaled_clipped
[13:44:14] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[13:44:14] ================= drm_test_rect_intersect =================
[13:44:14] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[13:44:14] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[13:44:14] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[13:44:14] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[13:44:14] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[13:44:14] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[13:44:14] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[13:44:14] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[13:44:14] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[13:44:14] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[13:44:14] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[13:44:14] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[13:44:14] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[13:44:14] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[13:44:14] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[13:44:14] ============= [PASSED] drm_test_rect_intersect =============
[13:44:14] ================ drm_test_rect_calc_hscale ================
[13:44:14] [PASSED] normal use
[13:44:14] [PASSED] out of max range
[13:44:14] [PASSED] out of min range
[13:44:14] [PASSED] zero dst
[13:44:14] [PASSED] negative src
[13:44:14] [PASSED] negative dst
[13:44:14] ============ [PASSED] drm_test_rect_calc_hscale ============
[13:44:14] ================ drm_test_rect_calc_vscale ================
[13:44:14] [PASSED] normal use
[13:44:14] [PASSED] out of max range
[13:44:14] [PASSED] out of min range
[13:44:14] [PASSED] zero dst
[13:44:14] [PASSED] negative src
[13:44:14] [PASSED] negative dst
[13:44:14] ============ [PASSED] drm_test_rect_calc_vscale ============
[13:44:14] ================== drm_test_rect_rotate ===================
[13:44:14] [PASSED] reflect-x
[13:44:14] [PASSED] reflect-y
[13:44:14] [PASSED] rotate-0
[13:44:14] [PASSED] rotate-90
[13:44:14] [PASSED] rotate-180
[13:44:14] [PASSED] rotate-270
[13:44:14] ============== [PASSED] drm_test_rect_rotate ===============
[13:44:14] ================ drm_test_rect_rotate_inv =================
[13:44:14] [PASSED] reflect-x
[13:44:14] [PASSED] reflect-y
[13:44:14] [PASSED] rotate-0
[13:44:14] [PASSED] rotate-90
[13:44:14] [PASSED] rotate-180
[13:44:14] [PASSED] rotate-270
[13:44:14] ============ [PASSED] drm_test_rect_rotate_inv =============
[13:44:14] ==================== [PASSED] drm_rect =====================
[13:44:14] ============ drm_sysfb_modeset_test (1 subtest) ============
[13:44:14] ============ drm_test_sysfb_build_fourcc_list =============
[13:44:14] [PASSED] no native formats
[13:44:14] [PASSED] XRGB8888 as native format
[13:44:14] [PASSED] remove duplicates
[13:44:14] [PASSED] convert alpha formats
[13:44:14] [PASSED] random formats
[13:44:14] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[13:44:14] ============= [PASSED] drm_sysfb_modeset_test ==============
[13:44:14] ================== drm_fixp (2 subtests) ===================
[13:44:14] [PASSED] drm_test_int2fixp
[13:44:14] [PASSED] drm_test_sm2fixp
[13:44:14] ==================== [PASSED] drm_fixp =====================
[13:44:14] ============================================================
[13:44:14] Testing complete. Ran 621 tests: passed: 621
[13:44:14] Elapsed time: 27.551s total, 1.727s configuring, 25.598s building, 0.178s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[13:44:14] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:44:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:44:25] Starting KUnit Kernel (1/1)...
[13:44:25] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:44:25] ================= ttm_device (5 subtests) ==================
[13:44:25] [PASSED] ttm_device_init_basic
[13:44:25] [PASSED] ttm_device_init_multiple
[13:44:25] [PASSED] ttm_device_fini_basic
[13:44:25] [PASSED] ttm_device_init_no_vma_man
[13:44:25] ================== ttm_device_init_pools ==================
[13:44:25] [PASSED] No DMA allocations, no DMA32 required
[13:44:25] [PASSED] DMA allocations, DMA32 required
[13:44:25] [PASSED] No DMA allocations, DMA32 required
[13:44:25] [PASSED] DMA allocations, no DMA32 required
[13:44:25] ============== [PASSED] ttm_device_init_pools ==============
[13:44:25] =================== [PASSED] ttm_device ====================
[13:44:25] ================== ttm_pool (8 subtests) ===================
[13:44:25] ================== ttm_pool_alloc_basic ===================
[13:44:25] [PASSED] One page
[13:44:25] [PASSED] More than one page
[13:44:25] [PASSED] Above the allocation limit
[13:44:25] [PASSED] One page, with coherent DMA mappings enabled
[13:44:25] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[13:44:25] ============== [PASSED] ttm_pool_alloc_basic ===============
[13:44:25] ============== ttm_pool_alloc_basic_dma_addr ==============
[13:44:25] [PASSED] One page
[13:44:25] [PASSED] More than one page
[13:44:25] [PASSED] Above the allocation limit
[13:44:25] [PASSED] One page, with coherent DMA mappings enabled
[13:44:25] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[13:44:25] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[13:44:25] [PASSED] ttm_pool_alloc_order_caching_match
[13:44:25] [PASSED] ttm_pool_alloc_caching_mismatch
[13:44:25] [PASSED] ttm_pool_alloc_order_mismatch
[13:44:25] [PASSED] ttm_pool_free_dma_alloc
[13:44:25] [PASSED] ttm_pool_free_no_dma_alloc
[13:44:25] [PASSED] ttm_pool_fini_basic
[13:44:25] ==================== [PASSED] ttm_pool =====================
[13:44:25] ================ ttm_resource (8 subtests) =================
[13:44:25] ================= ttm_resource_init_basic =================
[13:44:25] [PASSED] Init resource in TTM_PL_SYSTEM
[13:44:25] [PASSED] Init resource in TTM_PL_VRAM
[13:44:25] [PASSED] Init resource in a private placement
[13:44:25] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[13:44:25] ============= [PASSED] ttm_resource_init_basic =============
[13:44:25] [PASSED] ttm_resource_init_pinned
[13:44:25] [PASSED] ttm_resource_fini_basic
[13:44:25] [PASSED] ttm_resource_manager_init_basic
[13:44:25] [PASSED] ttm_resource_manager_usage_basic
[13:44:25] [PASSED] ttm_resource_manager_set_used_basic
[13:44:25] [PASSED] ttm_sys_man_alloc_basic
[13:44:25] [PASSED] ttm_sys_man_free_basic
[13:44:25] ================== [PASSED] ttm_resource ===================
[13:44:25] =================== ttm_tt (15 subtests) ===================
[13:44:25] ==================== ttm_tt_init_basic ====================
[13:44:25] [PASSED] Page-aligned size
[13:44:25] [PASSED] Extra pages requested
[13:44:25] ================ [PASSED] ttm_tt_init_basic ================
[13:44:25] [PASSED] ttm_tt_init_misaligned
[13:44:25] [PASSED] ttm_tt_fini_basic
[13:44:25] [PASSED] ttm_tt_fini_sg
[13:44:25] [PASSED] ttm_tt_fini_shmem
[13:44:25] [PASSED] ttm_tt_create_basic
[13:44:25] [PASSED] ttm_tt_create_invalid_bo_type
[13:44:25] [PASSED] ttm_tt_create_ttm_exists
[13:44:25] [PASSED] ttm_tt_create_failed
[13:44:25] [PASSED] ttm_tt_destroy_basic
[13:44:25] [PASSED] ttm_tt_populate_null_ttm
[13:44:25] [PASSED] ttm_tt_populate_populated_ttm
[13:44:25] [PASSED] ttm_tt_unpopulate_basic
[13:44:25] [PASSED] ttm_tt_unpopulate_empty_ttm
[13:44:25] [PASSED] ttm_tt_swapin_basic
[13:44:25] ===================== [PASSED] ttm_tt ======================
[13:44:25] =================== ttm_bo (14 subtests) ===================
[13:44:25] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[13:44:25] [PASSED] Cannot be interrupted and sleeps
[13:44:25] [PASSED] Cannot be interrupted, locks straight away
[13:44:25] [PASSED] Can be interrupted, sleeps
[13:44:25] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[13:44:25] [PASSED] ttm_bo_reserve_locked_no_sleep
[13:44:25] [PASSED] ttm_bo_reserve_no_wait_ticket
[13:44:25] [PASSED] ttm_bo_reserve_double_resv
[13:44:25] [PASSED] ttm_bo_reserve_interrupted
[13:44:25] [PASSED] ttm_bo_reserve_deadlock
[13:44:25] [PASSED] ttm_bo_unreserve_basic
[13:44:25] [PASSED] ttm_bo_unreserve_pinned
[13:44:25] [PASSED] ttm_bo_unreserve_bulk
[13:44:25] [PASSED] ttm_bo_fini_basic
[13:44:25] [PASSED] ttm_bo_fini_shared_resv
[13:44:25] [PASSED] ttm_bo_pin_basic
[13:44:25] [PASSED] ttm_bo_pin_unpin_resource
[13:44:25] [PASSED] ttm_bo_multiple_pin_one_unpin
[13:44:25] ===================== [PASSED] ttm_bo ======================
[13:44:25] ============== ttm_bo_validate (22 subtests) ===============
[13:44:25] ============== ttm_bo_init_reserved_sys_man ===============
[13:44:25] [PASSED] Buffer object for userspace
[13:44:25] [PASSED] Kernel buffer object
[13:44:25] [PASSED] Shared buffer object
[13:44:25] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[13:44:25] ============== ttm_bo_init_reserved_mock_man ==============
[13:44:25] [PASSED] Buffer object for userspace
[13:44:25] [PASSED] Kernel buffer object
[13:44:25] [PASSED] Shared buffer object
[13:44:25] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[13:44:25] [PASSED] ttm_bo_init_reserved_resv
[13:44:25] ================== ttm_bo_validate_basic ==================
[13:44:25] [PASSED] Buffer object for userspace
[13:44:25] [PASSED] Kernel buffer object
[13:44:25] [PASSED] Shared buffer object
[13:44:25] ============== [PASSED] ttm_bo_validate_basic ==============
[13:44:25] [PASSED] ttm_bo_validate_invalid_placement
[13:44:25] ============= ttm_bo_validate_same_placement ==============
[13:44:25] [PASSED] System manager
[13:44:25] [PASSED] VRAM manager
[13:44:25] ========= [PASSED] ttm_bo_validate_same_placement ==========
[13:44:25] [PASSED] ttm_bo_validate_failed_alloc
[13:44:25] [PASSED] ttm_bo_validate_pinned
[13:44:25] [PASSED] ttm_bo_validate_busy_placement
[13:44:25] ================ ttm_bo_validate_multihop =================
[13:44:25] [PASSED] Buffer object for userspace
[13:44:25] [PASSED] Kernel buffer object
[13:44:25] [PASSED] Shared buffer object
[13:44:25] ============ [PASSED] ttm_bo_validate_multihop =============
[13:44:25] ========== ttm_bo_validate_no_placement_signaled ==========
[13:44:25] [PASSED] Buffer object in system domain, no page vector
[13:44:25] [PASSED] Buffer object in system domain with an existing page vector
[13:44:25] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[13:44:25] ======== ttm_bo_validate_no_placement_not_signaled ========
[13:44:25] [PASSED] Buffer object for userspace
[13:44:25] [PASSED] Kernel buffer object
[13:44:25] [PASSED] Shared buffer object
[13:44:25] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[13:44:25] [PASSED] ttm_bo_validate_move_fence_signaled
[13:44:25] ========= ttm_bo_validate_move_fence_not_signaled =========
[13:44:25] [PASSED] Waits for GPU
[13:44:25] [PASSED] Tries to lock straight away
[13:44:25] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[13:44:25] [PASSED] ttm_bo_validate_swapout
[13:44:25] [PASSED] ttm_bo_validate_happy_evict
[13:44:25] [PASSED] ttm_bo_validate_all_pinned_evict
[13:44:25] [PASSED] ttm_bo_validate_allowed_only_evict
[13:44:25] [PASSED] ttm_bo_validate_deleted_evict
[13:44:25] [PASSED] ttm_bo_validate_busy_domain_evict
[13:44:25] [PASSED] ttm_bo_validate_evict_gutting
[13:44:25] [PASSED] ttm_bo_validate_recrusive_evict
[13:44:25] ================= [PASSED] ttm_bo_validate =================
[13:44:25] ============================================================
[13:44:25] Testing complete. Ran 102 tests: passed: 102
[13:44:25] Elapsed time: 11.264s total, 1.682s configuring, 9.367s building, 0.180s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 8+ messages in thread