* [PATCH v2 0/3] Fix value being written to DDI_CLK_VALFREQ
@ 2026-08-11 17:58 Suraj Kandpal
2026-08-11 17:58 ` [PATCH v2 1/3] drm/i915/ddi: add helper to compute DDI clock frequency Suraj Kandpal
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Suraj Kandpal @ 2026-08-11 17:58 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
Currently we write the portclock as is into DDI_CLK_VALFREQ register.
Which is fine for HDMI TMDS and DP 8b/10b encoding but for DP
128b/132b and HDMI FRL port clock needs to be modified to the
appropriate symbol clock and then be written into this register.
H/w has not thrown a bug yet because this is a validation register
and has no functional impact on H/w.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Suraj Kandpal (3):
drm/i915/ddi: add helper to compute DDI clock frequency
drm/i915/cx0: program DDI_CLK_VALFREQ with DDI clock frequency
drm/i915/lt_phy: program DDI_CLK_VALFREQ with DDI clock frequency
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 5 +++--
drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++++++++
drivers/gpu/drm/i915/display/intel_ddi.h | 1 +
drivers/gpu/drm/i915/display/intel_lt_phy.c | 6 ++++--
4 files changed, 19 insertions(+), 4 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 1/3] drm/i915/ddi: add helper to compute DDI clock frequency
2026-08-11 17:58 [PATCH v2 0/3] Fix value being written to DDI_CLK_VALFREQ Suraj Kandpal
@ 2026-08-11 17:58 ` Suraj Kandpal
2026-08-12 3:43 ` Nautiyal, Ankit K
2026-08-11 17:58 ` [PATCH v2 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ with " Suraj Kandpal
` (2 subsequent siblings)
3 siblings, 1 reply; 12+ messages in thread
From: Suraj Kandpal @ 2026-08-11 17:58 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
Add intel_ddi_link_symbol_clock() to return the DDI clock frequency for
a given port clock:
DP 8b/10b : rate
DP 128b/132b (UHBR) : (10 / 32) * rate
HDMI FRL : (10 / 18) * rate
HDMI TMDS : rate
The DP case reuses intel_dp_link_symbol_clock().
This will help in upcoming commits to decide value to be written
in DDI_CLK_VALFREQ.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
v1 -> v2
-Update commit message with correct formula (Jani)
drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++++++++
drivers/gpu/drm/i915/display/intel_ddi.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bf5788c5bbd3..dd9064592ec9 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1529,6 +1529,17 @@ int intel_ddi_level(struct intel_encoder *encoder,
return level;
}
+int intel_ddi_link_symbol_clock(struct intel_encoder *encoder, int clock)
+{
+ if (intel_encoder_is_dp(encoder))
+ return intel_dp_link_symbol_clock(clock);
+
+ if (intel_hdmi_is_frl(clock))
+ return DIV_ROUND_CLOSEST(clock * 10, 18);
+
+ return clock;
+}
+
static void
hsw_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 580ecb09b8b6..239d5a403f91 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -81,6 +81,7 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
int intel_ddi_level(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int lane);
+int intel_ddi_link_symbol_clock(struct intel_encoder *encoder, int clock);
void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
struct intel_encoder *encoder,
struct intel_crtc *crtc);
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ with DDI clock frequency
2026-08-11 17:58 [PATCH v2 0/3] Fix value being written to DDI_CLK_VALFREQ Suraj Kandpal
2026-08-11 17:58 ` [PATCH v2 1/3] drm/i915/ddi: add helper to compute DDI clock frequency Suraj Kandpal
@ 2026-08-11 17:58 ` Suraj Kandpal
2026-08-12 3:49 ` Nautiyal, Ankit K
2026-08-11 17:58 ` [PATCH v2 3/3] drm/i915/lt_phy: " Suraj Kandpal
2026-08-11 18:05 ` ✓ CI.KUnit: success for Fix value being written to DDI_CLK_VALFREQ (rev2) Patchwork
3 siblings, 1 reply; 12+ messages in thread
From: Suraj Kandpal @ 2026-08-11 17:58 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
DDI_CLK_VALFREQ is programmed with the port clock, which for DP is the
symbol clock computed assuming 8b/10b encoding (link_rate / 10). For
DP 128b/132b (UHBR) rates and for HDMI FRL the port clock needs to
be modfied.
On silicon DDI_CLK_VALFREQ is a scratch register with no
functional impact, so the bug is not observed.
Use intel_ddi_link_symbol_clock() to write the correct DDI clock in
kHz.
Fixes: 51390cc0e00a ("drm/i915/mtl: Add Support for C10 PHY message bus and pll programming")
Fixes: 73fc3abcb797 ("drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll")
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 452062417ce9..dbebd7210848 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3233,7 +3233,8 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
* 8. Program DDI_CLK_VALFREQ to match intended DDI
* clock frequency.
*/
- intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
+ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
+ intel_ddi_link_symbol_clock(encoder, port_clock));
/*
* 9. Set PORT_CLOCK_CTL register PCLK PLL Request
@@ -3406,7 +3407,7 @@ void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder, int port_cloc
* clock frequency.
*/
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
- port_clock);
+ intel_ddi_link_symbol_clock(encoder, port_clock));
}
void intel_mtl_pll_enable(struct intel_encoder *encoder,
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 3/3] drm/i915/lt_phy: program DDI_CLK_VALFREQ with DDI clock frequency
2026-08-11 17:58 [PATCH v2 0/3] Fix value being written to DDI_CLK_VALFREQ Suraj Kandpal
2026-08-11 17:58 ` [PATCH v2 1/3] drm/i915/ddi: add helper to compute DDI clock frequency Suraj Kandpal
2026-08-11 17:58 ` [PATCH v2 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ with " Suraj Kandpal
@ 2026-08-11 17:58 ` Suraj Kandpal
2026-08-12 3:50 ` Nautiyal, Ankit K
2026-08-11 18:05 ` ✓ CI.KUnit: success for Fix value being written to DDI_CLK_VALFREQ (rev2) Patchwork
3 siblings, 1 reply; 12+ messages in thread
From: Suraj Kandpal @ 2026-08-11 17:58 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
DDI_CLK_VALFREQ is programmed with the port clock, which for DP is the
symbol clock computed assuming 8b/10b encoding (link_rate / 10). For
DP 128b/132b (UHBR) rates and for HDMI FRL the port clock needs to
be modified.
On silicon DDI_CLK_VALFREQ is a scratch register with no
functional impact, so the bug is not observed.
Use intel_ddi_link_symbol_clock() to write the correct DDI clock in
kHz
Fixes: 5ec58d714935 ("drm/i915/lt_phy: Add .enable_clock hook on DDI")
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_lt_phy.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 8fc6d230493f..86492651b01d 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1976,7 +1976,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
* Change. We handle this step in bxt_set_cdclk().
*/
/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
- intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
+ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
+ intel_ddi_link_symbol_clock(encoder, port_clock));
/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
@@ -2023,7 +2024,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
lane_phy_pulse_status,
lane_phy_pulse_status);
} else {
- intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
+ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
+ intel_ddi_link_symbol_clock(encoder, port_clock));
}
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✓ CI.KUnit: success for Fix value being written to DDI_CLK_VALFREQ (rev2)
2026-08-11 17:58 [PATCH v2 0/3] Fix value being written to DDI_CLK_VALFREQ Suraj Kandpal
` (2 preceding siblings ...)
2026-08-11 17:58 ` [PATCH v2 3/3] drm/i915/lt_phy: " Suraj Kandpal
@ 2026-08-11 18:05 ` Patchwork
3 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2026-08-11 18:05 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-xe
== Series Details ==
Series: Fix value being written to DDI_CLK_VALFREQ (rev2)
URL : https://patchwork.freedesktop.org/series/171961/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[18:04:12] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:04:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:04:48] Starting KUnit Kernel (1/1)...
[18:04:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:04:48] ================== guc_buf (11 subtests) ===================
[18:04:48] [PASSED] test_smallest
[18:04:48] [PASSED] test_largest
[18:04:48] [PASSED] test_granular
[18:04:48] [PASSED] test_unique
[18:04:48] [PASSED] test_overlap
[18:04:48] [PASSED] test_reusable
[18:04:48] [PASSED] test_too_big
[18:04:48] [PASSED] test_flush
[18:04:48] [PASSED] test_lookup
[18:04:48] [PASSED] test_data
[18:04:48] [PASSED] test_class
[18:04:48] ===================== [PASSED] guc_buf =====================
[18:04:48] =================== guc_dbm (7 subtests) ===================
[18:04:48] [PASSED] test_empty
[18:04:48] [PASSED] test_default
[18:04:48] ======================== test_size ========================
[18:04:48] [PASSED] 4
[18:04:48] [PASSED] 8
[18:04:48] [PASSED] 32
[18:04:48] [PASSED] 256
[18:04:48] ==================== [PASSED] test_size ====================
[18:04:48] ======================= test_reuse ========================
[18:04:48] [PASSED] 4
[18:04:48] [PASSED] 8
[18:04:48] [PASSED] 32
[18:04:48] [PASSED] 256
[18:04:48] =================== [PASSED] test_reuse ====================
[18:04:48] =================== test_range_overlap ====================
[18:04:48] [PASSED] 4
[18:04:48] [PASSED] 8
[18:04:48] [PASSED] 32
[18:04:48] [PASSED] 256
[18:04:48] =============== [PASSED] test_range_overlap ================
[18:04:48] =================== test_range_compact ====================
[18:04:48] [PASSED] 4
[18:04:48] [PASSED] 8
[18:04:48] [PASSED] 32
[18:04:48] [PASSED] 256
[18:04:48] =============== [PASSED] test_range_compact ================
[18:04:48] ==================== test_range_spare =====================
[18:04:48] [PASSED] 4
[18:04:48] [PASSED] 8
[18:04:48] [PASSED] 32
[18:04:48] [PASSED] 256
[18:04:48] ================ [PASSED] test_range_spare =================
[18:04:48] ===================== [PASSED] guc_dbm =====================
[18:04:48] =================== guc_idm (6 subtests) ===================
[18:04:48] [PASSED] bad_init
[18:04:48] [PASSED] no_init
[18:04:48] [PASSED] init_fini
[18:04:48] [PASSED] check_used
[18:04:48] [PASSED] check_quota
[18:04:48] [PASSED] check_all
[18:04:48] ===================== [PASSED] guc_idm =====================
[18:04:48] =============== guc_klv_helpers (9 subtests) ===============
[18:04:48] [PASSED] test_count
[18:04:48] [PASSED] test_encode_u32
[18:04:48] [PASSED] test_encode_u64
[18:04:48] [PASSED] test_encode_string
[18:04:48] [PASSED] test_encode_object_raw
[18:04:48] [PASSED] test_encode_object_klv
[18:04:48] [PASSED] test_encode_object_nested
[18:04:48] [PASSED] test_encode_object_basic
[18:04:48] [PASSED] test_print
[18:04:48] ================= [PASSED] guc_klv_helpers =================
[18:04:48] ================== no_relay (3 subtests) ===================
[18:04:48] [PASSED] xe_drops_guc2pf_if_not_ready
[18:04:48] [PASSED] xe_drops_guc2vf_if_not_ready
[18:04:48] [PASSED] xe_rejects_send_if_not_ready
[18:04:48] ==================== [PASSED] no_relay =====================
[18:04:48] ================== pf_relay (14 subtests) ==================
[18:04:48] [PASSED] pf_rejects_guc2pf_too_short
[18:04:48] [PASSED] pf_rejects_guc2pf_too_long
[18:04:48] [PASSED] pf_rejects_guc2pf_no_payload
[18:04:48] [PASSED] pf_fails_no_payload
[18:04:48] [PASSED] pf_fails_bad_origin
[18:04:48] [PASSED] pf_fails_bad_type
[18:04:48] [PASSED] pf_txn_reports_error
[18:04:48] [PASSED] pf_txn_sends_pf2guc
[18:04:48] [PASSED] pf_sends_pf2guc
[18:04:48] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:04:48] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:04:48] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:04:48] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:04:48] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:04:48] ==================== [PASSED] pf_relay =====================
[18:04:48] ================== vf_relay (3 subtests) ===================
[18:04:48] [PASSED] vf_rejects_guc2vf_too_short
[18:04:48] [PASSED] vf_rejects_guc2vf_too_long
[18:04:48] [PASSED] vf_rejects_guc2vf_no_payload
[18:04:48] ==================== [PASSED] vf_relay =====================
[18:04:48] ================ pf_gt_config (9 subtests) =================
[18:04:48] [PASSED] fair_contexts_1vf
[18:04:48] [PASSED] fair_doorbells_1vf
[18:04:48] [PASSED] fair_ggtt_1vf
[18:04:48] ====================== fair_vram_1vf ======================
[18:04:48] [PASSED] 3.50 GiB
[18:04:48] [PASSED] 11.5 GiB
[18:04:48] [PASSED] 15.5 GiB
[18:04:48] [PASSED] 31.5 GiB
[18:04:48] [PASSED] 63.5 GiB
[18:04:48] [PASSED] 1.91 GiB
[18:04:48] ================== [PASSED] fair_vram_1vf ==================
[18:04:48] ================ fair_vram_1vf_admin_only =================
[18:04:48] [PASSED] 3.50 GiB
[18:04:48] [PASSED] 11.5 GiB
[18:04:48] [PASSED] 15.5 GiB
[18:04:48] [PASSED] 31.5 GiB
[18:04:48] [PASSED] 63.5 GiB
[18:04:48] [PASSED] 1.91 GiB
[18:04:48] ============ [PASSED] fair_vram_1vf_admin_only =============
[18:04:48] ====================== fair_contexts ======================
[18:04:48] [PASSED] 1 VF
[18:04:48] [PASSED] 2 VFs
[18:04:48] [PASSED] 3 VFs
[18:04:48] [PASSED] 4 VFs
[18:04:48] [PASSED] 5 VFs
[18:04:48] [PASSED] 6 VFs
[18:04:48] [PASSED] 7 VFs
[18:04:48] [PASSED] 8 VFs
[18:04:48] [PASSED] 9 VFs
[18:04:48] [PASSED] 10 VFs
[18:04:48] [PASSED] 11 VFs
[18:04:48] [PASSED] 12 VFs
[18:04:48] [PASSED] 13 VFs
[18:04:48] [PASSED] 14 VFs
[18:04:48] [PASSED] 15 VFs
[18:04:48] [PASSED] 16 VFs
[18:04:48] [PASSED] 17 VFs
[18:04:48] [PASSED] 18 VFs
[18:04:48] [PASSED] 19 VFs
[18:04:48] [PASSED] 20 VFs
[18:04:48] [PASSED] 21 VFs
[18:04:48] [PASSED] 22 VFs
[18:04:48] [PASSED] 23 VFs
[18:04:48] [PASSED] 24 VFs
[18:04:48] [PASSED] 25 VFs
[18:04:48] [PASSED] 26 VFs
[18:04:48] [PASSED] 27 VFs
[18:04:48] [PASSED] 28 VFs
[18:04:48] [PASSED] 29 VFs
[18:04:48] [PASSED] 30 VFs
[18:04:48] [PASSED] 31 VFs
[18:04:48] [PASSED] 32 VFs
[18:04:48] [PASSED] 33 VFs
[18:04:48] [PASSED] 34 VFs
[18:04:48] [PASSED] 35 VFs
[18:04:48] [PASSED] 36 VFs
[18:04:48] [PASSED] 37 VFs
[18:04:48] [PASSED] 38 VFs
[18:04:48] [PASSED] 39 VFs
[18:04:48] [PASSED] 40 VFs
[18:04:48] [PASSED] 41 VFs
[18:04:48] [PASSED] 42 VFs
[18:04:48] [PASSED] 43 VFs
[18:04:48] [PASSED] 44 VFs
[18:04:48] [PASSED] 45 VFs
[18:04:48] [PASSED] 46 VFs
[18:04:48] [PASSED] 47 VFs
[18:04:48] [PASSED] 48 VFs
[18:04:48] [PASSED] 49 VFs
[18:04:48] [PASSED] 50 VFs
[18:04:48] [PASSED] 51 VFs
[18:04:48] [PASSED] 52 VFs
[18:04:48] [PASSED] 53 VFs
[18:04:48] [PASSED] 54 VFs
[18:04:48] [PASSED] 55 VFs
[18:04:48] [PASSED] 56 VFs
[18:04:48] [PASSED] 57 VFs
[18:04:48] [PASSED] 58 VFs
[18:04:48] [PASSED] 59 VFs
[18:04:48] [PASSED] 60 VFs
[18:04:48] [PASSED] 61 VFs
[18:04:48] [PASSED] 62 VFs
[18:04:48] [PASSED] 63 VFs
[18:04:48] ================== [PASSED] fair_contexts ==================
[18:04:48] ===================== fair_doorbells ======================
[18:04:48] [PASSED] 1 VF
[18:04:48] [PASSED] 2 VFs
[18:04:48] [PASSED] 3 VFs
[18:04:48] [PASSED] 4 VFs
[18:04:48] [PASSED] 5 VFs
[18:04:48] [PASSED] 6 VFs
[18:04:48] [PASSED] 7 VFs
[18:04:48] [PASSED] 8 VFs
[18:04:48] [PASSED] 9 VFs
[18:04:48] [PASSED] 10 VFs
[18:04:48] [PASSED] 11 VFs
[18:04:48] [PASSED] 12 VFs
[18:04:48] [PASSED] 13 VFs
[18:04:48] [PASSED] 14 VFs
[18:04:48] [PASSED] 15 VFs
[18:04:48] [PASSED] 16 VFs
[18:04:48] [PASSED] 17 VFs
[18:04:48] [PASSED] 18 VFs
[18:04:48] [PASSED] 19 VFs
[18:04:48] [PASSED] 20 VFs
[18:04:48] [PASSED] 21 VFs
[18:04:48] [PASSED] 22 VFs
[18:04:48] [PASSED] 23 VFs
[18:04:48] [PASSED] 24 VFs
[18:04:48] [PASSED] 25 VFs
[18:04:48] [PASSED] 26 VFs
[18:04:48] [PASSED] 27 VFs
[18:04:48] [PASSED] 28 VFs
[18:04:48] [PASSED] 29 VFs
[18:04:48] [PASSED] 30 VFs
[18:04:48] [PASSED] 31 VFs
[18:04:48] [PASSED] 32 VFs
[18:04:48] [PASSED] 33 VFs
[18:04:48] [PASSED] 34 VFs
[18:04:48] [PASSED] 35 VFs
[18:04:48] [PASSED] 36 VFs
[18:04:48] [PASSED] 37 VFs
[18:04:48] [PASSED] 38 VFs
[18:04:48] [PASSED] 39 VFs
[18:04:48] [PASSED] 40 VFs
[18:04:48] [PASSED] 41 VFs
[18:04:48] [PASSED] 42 VFs
[18:04:48] [PASSED] 43 VFs
[18:04:48] [PASSED] 44 VFs
[18:04:48] [PASSED] 45 VFs
[18:04:48] [PASSED] 46 VFs
[18:04:48] [PASSED] 47 VFs
[18:04:48] [PASSED] 48 VFs
[18:04:48] [PASSED] 49 VFs
[18:04:48] [PASSED] 50 VFs
[18:04:48] [PASSED] 51 VFs
[18:04:48] [PASSED] 52 VFs
[18:04:48] [PASSED] 53 VFs
[18:04:48] [PASSED] 54 VFs
[18:04:48] [PASSED] 55 VFs
[18:04:48] [PASSED] 56 VFs
[18:04:48] [PASSED] 57 VFs
[18:04:48] [PASSED] 58 VFs
[18:04:48] [PASSED] 59 VFs
[18:04:48] [PASSED] 60 VFs
[18:04:48] [PASSED] 61 VFs
[18:04:48] [PASSED] 62 VFs
[18:04:48] [PASSED] 63 VFs
[18:04:48] ================= [PASSED] fair_doorbells ==================
[18:04:48] ======================== fair_ggtt ========================
[18:04:48] [PASSED] 1 VF
[18:04:48] [PASSED] 2 VFs
[18:04:48] [PASSED] 3 VFs
[18:04:48] [PASSED] 4 VFs
[18:04:48] [PASSED] 5 VFs
[18:04:48] [PASSED] 6 VFs
[18:04:48] [PASSED] 7 VFs
[18:04:48] [PASSED] 8 VFs
[18:04:48] [PASSED] 9 VFs
[18:04:48] [PASSED] 10 VFs
[18:04:48] [PASSED] 11 VFs
[18:04:48] [PASSED] 12 VFs
[18:04:48] [PASSED] 13 VFs
[18:04:48] [PASSED] 14 VFs
[18:04:48] [PASSED] 15 VFs
[18:04:48] [PASSED] 16 VFs
[18:04:48] [PASSED] 17 VFs
[18:04:48] [PASSED] 18 VFs
[18:04:48] [PASSED] 19 VFs
[18:04:48] [PASSED] 20 VFs
[18:04:48] [PASSED] 21 VFs
[18:04:48] [PASSED] 22 VFs
[18:04:48] [PASSED] 23 VFs
[18:04:48] [PASSED] 24 VFs
[18:04:48] [PASSED] 25 VFs
[18:04:48] [PASSED] 26 VFs
[18:04:48] [PASSED] 27 VFs
[18:04:48] [PASSED] 28 VFs
[18:04:48] [PASSED] 29 VFs
[18:04:48] [PASSED] 30 VFs
[18:04:48] [PASSED] 31 VFs
[18:04:48] [PASSED] 32 VFs
[18:04:48] [PASSED] 33 VFs
[18:04:48] [PASSED] 34 VFs
[18:04:48] [PASSED] 35 VFs
[18:04:48] [PASSED] 36 VFs
[18:04:48] [PASSED] 37 VFs
[18:04:48] [PASSED] 38 VFs
[18:04:48] [PASSED] 39 VFs
[18:04:48] [PASSED] 40 VFs
[18:04:48] [PASSED] 41 VFs
[18:04:48] [PASSED] 42 VFs
[18:04:48] [PASSED] 43 VFs
[18:04:48] [PASSED] 44 VFs
[18:04:48] [PASSED] 45 VFs
[18:04:48] [PASSED] 46 VFs
[18:04:48] [PASSED] 47 VFs
[18:04:48] [PASSED] 48 VFs
[18:04:48] [PASSED] 49 VFs
[18:04:48] [PASSED] 50 VFs
[18:04:48] [PASSED] 51 VFs
[18:04:48] [PASSED] 52 VFs
[18:04:48] [PASSED] 53 VFs
[18:04:48] [PASSED] 54 VFs
[18:04:48] [PASSED] 55 VFs
[18:04:48] [PASSED] 56 VFs
[18:04:48] [PASSED] 57 VFs
[18:04:48] [PASSED] 58 VFs
[18:04:48] [PASSED] 59 VFs
[18:04:48] [PASSED] 60 VFs
[18:04:48] [PASSED] 61 VFs
[18:04:48] [PASSED] 62 VFs
[18:04:48] [PASSED] 63 VFs
[18:04:48] ==================== [PASSED] fair_ggtt ====================
[18:04:48] ======================== fair_vram ========================
[18:04:48] [PASSED] 1 VF
[18:04:48] [PASSED] 2 VFs
[18:04:48] [PASSED] 3 VFs
[18:04:48] [PASSED] 4 VFs
[18:04:48] [PASSED] 5 VFs
[18:04:48] [PASSED] 6 VFs
[18:04:48] [PASSED] 7 VFs
[18:04:48] [PASSED] 8 VFs
[18:04:48] [PASSED] 9 VFs
[18:04:48] [PASSED] 10 VFs
[18:04:48] [PASSED] 11 VFs
[18:04:48] [PASSED] 12 VFs
[18:04:48] [PASSED] 13 VFs
[18:04:48] [PASSED] 14 VFs
[18:04:48] [PASSED] 15 VFs
[18:04:48] [PASSED] 16 VFs
[18:04:48] [PASSED] 17 VFs
[18:04:48] [PASSED] 18 VFs
[18:04:48] [PASSED] 19 VFs
[18:04:48] [PASSED] 20 VFs
[18:04:48] [PASSED] 21 VFs
[18:04:48] [PASSED] 22 VFs
[18:04:48] [PASSED] 23 VFs
[18:04:48] [PASSED] 24 VFs
[18:04:48] [PASSED] 25 VFs
[18:04:48] [PASSED] 26 VFs
[18:04:48] [PASSED] 27 VFs
[18:04:48] [PASSED] 28 VFs
[18:04:48] [PASSED] 29 VFs
[18:04:48] [PASSED] 30 VFs
[18:04:48] [PASSED] 31 VFs
[18:04:48] [PASSED] 32 VFs
[18:04:48] [PASSED] 33 VFs
[18:04:48] [PASSED] 34 VFs
[18:04:48] [PASSED] 35 VFs
[18:04:48] [PASSED] 36 VFs
[18:04:48] [PASSED] 37 VFs
[18:04:48] [PASSED] 38 VFs
[18:04:48] [PASSED] 39 VFs
[18:04:48] [PASSED] 40 VFs
[18:04:48] [PASSED] 41 VFs
[18:04:48] [PASSED] 42 VFs
[18:04:48] [PASSED] 43 VFs
[18:04:48] [PASSED] 44 VFs
[18:04:48] [PASSED] 45 VFs
[18:04:48] [PASSED] 46 VFs
[18:04:48] [PASSED] 47 VFs
[18:04:48] [PASSED] 48 VFs
[18:04:48] [PASSED] 49 VFs
[18:04:48] [PASSED] 50 VFs
[18:04:48] [PASSED] 51 VFs
[18:04:48] [PASSED] 52 VFs
[18:04:48] [PASSED] 53 VFs
[18:04:48] [PASSED] 54 VFs
[18:04:48] [PASSED] 55 VFs
[18:04:48] [PASSED] 56 VFs
[18:04:48] [PASSED] 57 VFs
[18:04:48] [PASSED] 58 VFs
[18:04:48] [PASSED] 59 VFs
[18:04:48] [PASSED] 60 VFs
[18:04:48] [PASSED] 61 VFs
[18:04:48] [PASSED] 62 VFs
[18:04:48] [PASSED] 63 VFs
[18:04:48] ==================== [PASSED] fair_vram ====================
[18:04:48] ================== [PASSED] pf_gt_config ===================
[18:04:48] ===================== lmtt (1 subtest) =====================
[18:04:48] ======================== test_ops =========================
[18:04:48] [PASSED] 2-level
[18:04:48] [PASSED] multi-level
[18:04:48] ==================== [PASSED] test_ops =====================
[18:04:48] ====================== [PASSED] lmtt =======================
[18:04:48] ================= sriov_packet (1 subtest) =================
[18:04:48] [PASSED] test_descriptor_init
[18:04:48] ================== [PASSED] sriov_packet ===================
[18:04:48] ================= pf_service (11 subtests) =================
[18:04:48] [PASSED] pf_negotiate_any
[18:04:48] [PASSED] pf_negotiate_base_match
[18:04:48] [PASSED] pf_negotiate_base_newer
[18:04:48] [PASSED] pf_negotiate_base_next
[18:04:48] [SKIPPED] pf_negotiate_base_older (no older minor)
[18:04:48] [PASSED] pf_negotiate_base_prev
[18:04:48] [PASSED] pf_negotiate_latest_match
[18:04:48] [PASSED] pf_negotiate_latest_newer
[18:04:48] [PASSED] pf_negotiate_latest_next
[18:04:48] [SKIPPED] pf_negotiate_latest_older (no older minor)
[18:04:48] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[18:04:48] =================== [PASSED] pf_service ====================
[18:04:48] ================= xe_guc_g2g (2 subtests) ==================
[18:04:48] ============== xe_live_guc_g2g_kunit_default ==============
[18:04:48] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[18:04:48] ============== xe_live_guc_g2g_kunit_allmem ===============
[18:04:48] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[18:04:48] =================== [SKIPPED] xe_guc_g2g ===================
[18:04:48] =================== xe_mocs (2 subtests) ===================
[18:04:48] ================ xe_live_mocs_kernel_kunit ================
[18:04:48] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[18:04:48] ================ xe_live_mocs_reset_kunit =================
[18:04:48] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[18:04:48] ==================== [SKIPPED] xe_mocs =====================
[18:04:48] ================= xe_migrate (2 subtests) ==================
[18:04:48] ================= xe_migrate_sanity_kunit =================
[18:04:48] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[18:04:48] ================== xe_validate_ccs_kunit ==================
[18:04:48] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[18:04:48] =================== [SKIPPED] xe_migrate ===================
[18:04:48] ================== xe_dma_buf (1 subtest) ==================
[18:04:48] ==================== xe_dma_buf_kunit =====================
[18:04:48] ================ [SKIPPED] xe_dma_buf_kunit ================
[18:04:48] =================== [SKIPPED] xe_dma_buf ===================
[18:04:48] ================= xe_bo_shrink (1 subtest) =================
[18:04:48] =================== xe_bo_shrink_kunit ====================
[18:04:48] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[18:04:48] ================== [SKIPPED] xe_bo_shrink ==================
[18:04:48] ==================== xe_bo (2 subtests) ====================
[18:04:48] ================== xe_ccs_migrate_kunit ===================
[18:04:48] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[18:04:48] ==================== xe_bo_evict_kunit ====================
[18:04:48] =============== [SKIPPED] xe_bo_evict_kunit ================
[18:04:48] ===================== [SKIPPED] xe_bo ======================
[18:04:48] ==================== args (13 subtests) ====================
[18:04:48] [PASSED] count_args_test
[18:04:48] [PASSED] call_args_example
[18:04:48] [PASSED] call_args_test
[18:04:48] [PASSED] drop_first_arg_example
[18:04:48] [PASSED] drop_first_arg_test
[18:04:48] [PASSED] first_arg_example
[18:04:48] [PASSED] first_arg_test
[18:04:48] [PASSED] last_arg_example
[18:04:48] [PASSED] last_arg_test
[18:04:48] [PASSED] pick_arg_example
[18:04:48] [PASSED] if_args_example
[18:04:48] [PASSED] if_args_test
[18:04:48] [PASSED] sep_comma_example
[18:04:48] ====================== [PASSED] args =======================
[18:04:48] =================== xe_pci (3 subtests) ====================
[18:04:48] ==================== check_graphics_ip ====================
[18:04:48] [PASSED] 12.00 Xe_LP
[18:04:48] [PASSED] 12.10 Xe_LP+
[18:04:48] [PASSED] 12.55 Xe_HPG
[18:04:48] [PASSED] 12.60 Xe_HPC
[18:04:48] [PASSED] 12.70 Xe_LPG
[18:04:48] [PASSED] 12.71 Xe_LPG
[18:04:48] [PASSED] 12.74 Xe_LPG+
[18:04:48] [PASSED] 20.01 Xe2_HPG
[18:04:48] [PASSED] 20.02 Xe2_HPG
[18:04:48] [PASSED] 20.04 Xe2_LPG
[18:04:48] [PASSED] 30.00 Xe3_LPG
[18:04:48] [PASSED] 30.01 Xe3_LPG
[18:04:48] [PASSED] 30.03 Xe3_LPG
[18:04:48] [PASSED] 30.04 Xe3_LPG
[18:04:48] [PASSED] 30.05 Xe3_LPG
[18:04:48] [PASSED] 35.10 Xe3p_LPG
[18:04:48] [PASSED] 35.11 Xe3p_XPC
[18:04:48] ================ [PASSED] check_graphics_ip ================
[18:04:48] ===================== check_media_ip ======================
[18:04:48] [PASSED] 12.00 Xe_M
[18:04:48] [PASSED] 12.55 Xe_HPM
[18:04:48] [PASSED] 13.00 Xe_LPM+
[18:04:48] [PASSED] 13.01 Xe2_HPM
[18:04:48] [PASSED] 20.00 Xe2_LPM
[18:04:48] [PASSED] 30.00 Xe3_LPM
[18:04:48] [PASSED] 30.02 Xe3_LPM
[18:04:48] [PASSED] 35.00 Xe3p_LPM
[18:04:48] [PASSED] 35.03 Xe3p_HPM
[18:04:48] ================= [PASSED] check_media_ip ==================
[18:04:48] =================== check_platform_desc ===================
[18:04:48] [PASSED] 0x9A60 (TIGERLAKE)
[18:04:48] [PASSED] 0x9A68 (TIGERLAKE)
[18:04:48] [PASSED] 0x9A70 (TIGERLAKE)
[18:04:48] [PASSED] 0x9A40 (TIGERLAKE)
[18:04:48] [PASSED] 0x9A49 (TIGERLAKE)
[18:04:48] [PASSED] 0x9A59 (TIGERLAKE)
[18:04:48] [PASSED] 0x9A78 (TIGERLAKE)
[18:04:48] [PASSED] 0x9AC0 (TIGERLAKE)
[18:04:48] [PASSED] 0x9AC9 (TIGERLAKE)
[18:04:48] [PASSED] 0x9AD9 (TIGERLAKE)
[18:04:48] [PASSED] 0x9AF8 (TIGERLAKE)
[18:04:48] [PASSED] 0x4C80 (ROCKETLAKE)
[18:04:48] [PASSED] 0x4C8A (ROCKETLAKE)
[18:04:48] [PASSED] 0x4C8B (ROCKETLAKE)
[18:04:48] [PASSED] 0x4C8C (ROCKETLAKE)
[18:04:48] [PASSED] 0x4C90 (ROCKETLAKE)
[18:04:48] [PASSED] 0x4C9A (ROCKETLAKE)
[18:04:48] [PASSED] 0x4680 (ALDERLAKE_S)
[18:04:48] [PASSED] 0x4682 (ALDERLAKE_S)
[18:04:48] [PASSED] 0x4688 (ALDERLAKE_S)
[18:04:48] [PASSED] 0x468A (ALDERLAKE_S)
[18:04:48] [PASSED] 0x468B (ALDERLAKE_S)
[18:04:48] [PASSED] 0x4690 (ALDERLAKE_S)
[18:04:48] [PASSED] 0x4692 (ALDERLAKE_S)
[18:04:48] [PASSED] 0x4693 (ALDERLAKE_S)
[18:04:48] [PASSED] 0x46A0 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x46A1 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x46A2 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x46A3 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x46A6 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x46A8 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x46AA (ALDERLAKE_P)
[18:04:48] [PASSED] 0x462A (ALDERLAKE_P)
[18:04:48] [PASSED] 0x4626 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x4628 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x46B0 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x46B1 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x46B2 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x46B3 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x46C0 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x46C1 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x46C2 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x46C3 (ALDERLAKE_P)
[18:04:48] [PASSED] 0x46D0 (ALDERLAKE_N)
[18:04:48] [PASSED] 0x46D1 (ALDERLAKE_N)
[18:04:48] [PASSED] 0x46D2 (ALDERLAKE_N)
[18:04:48] [PASSED] 0x46D3 (ALDERLAKE_N)
[18:04:48] [PASSED] 0x46D4 (ALDERLAKE_N)
[18:04:48] [PASSED] 0xA721 (ALDERLAKE_P)
[18:04:48] [PASSED] 0xA7A1 (ALDERLAKE_P)
[18:04:48] [PASSED] 0xA7A9 (ALDERLAKE_P)
[18:04:48] [PASSED] 0xA7AC (ALDERLAKE_P)
[18:04:48] [PASSED] 0xA7AD (ALDERLAKE_P)
[18:04:48] [PASSED] 0xA720 (ALDERLAKE_P)
[18:04:48] [PASSED] 0xA7A0 (ALDERLAKE_P)
[18:04:48] [PASSED] 0xA7A8 (ALDERLAKE_P)
[18:04:48] [PASSED] 0xA7AA (ALDERLAKE_P)
[18:04:48] [PASSED] 0xA7AB (ALDERLAKE_P)
[18:04:48] [PASSED] 0xA780 (ALDERLAKE_S)
[18:04:48] [PASSED] 0xA781 (ALDERLAKE_S)
[18:04:48] [PASSED] 0xA782 (ALDERLAKE_S)
[18:04:48] [PASSED] 0xA783 (ALDERLAKE_S)
[18:04:48] [PASSED] 0xA788 (ALDERLAKE_S)
[18:04:48] [PASSED] 0xA789 (ALDERLAKE_S)
[18:04:48] [PASSED] 0xA78A (ALDERLAKE_S)
[18:04:48] [PASSED] 0xA78B (ALDERLAKE_S)
[18:04:48] [PASSED] 0x4905 (DG1)
[18:04:48] [PASSED] 0x4906 (DG1)
[18:04:48] [PASSED] 0x4907 (DG1)
[18:04:48] [PASSED] 0x4908 (DG1)
[18:04:48] [PASSED] 0x4909 (DG1)
[18:04:48] [PASSED] 0x56C0 (DG2)
[18:04:48] [PASSED] 0x56C2 (DG2)
[18:04:48] [PASSED] 0x56C1 (DG2)
[18:04:48] [PASSED] 0x7D51 (METEORLAKE)
[18:04:48] [PASSED] 0x7DD1 (METEORLAKE)
[18:04:48] [PASSED] 0x7D41 (METEORLAKE)
[18:04:48] [PASSED] 0x7D67 (METEORLAKE)
[18:04:48] [PASSED] 0xB640 (METEORLAKE)
[18:04:48] [PASSED] 0x56A0 (DG2)
[18:04:48] [PASSED] 0x56A1 (DG2)
[18:04:48] [PASSED] 0x56A2 (DG2)
[18:04:48] [PASSED] 0x56BE (DG2)
[18:04:48] [PASSED] 0x56BF (DG2)
[18:04:48] [PASSED] 0x5690 (DG2)
[18:04:48] [PASSED] 0x5691 (DG2)
[18:04:48] [PASSED] 0x5692 (DG2)
[18:04:48] [PASSED] 0x56A5 (DG2)
[18:04:48] [PASSED] 0x56A6 (DG2)
[18:04:48] [PASSED] 0x56B0 (DG2)
[18:04:48] [PASSED] 0x56B1 (DG2)
[18:04:48] [PASSED] 0x56BA (DG2)
[18:04:48] [PASSED] 0x56BB (DG2)
[18:04:48] [PASSED] 0x56BC (DG2)
[18:04:48] [PASSED] 0x56BD (DG2)
[18:04:48] [PASSED] 0x5693 (DG2)
[18:04:48] [PASSED] 0x5694 (DG2)
[18:04:48] [PASSED] 0x5695 (DG2)
[18:04:48] [PASSED] 0x56A3 (DG2)
[18:04:48] [PASSED] 0x56A4 (DG2)
[18:04:48] [PASSED] 0x56B2 (DG2)
[18:04:48] [PASSED] 0x56B3 (DG2)
[18:04:48] [PASSED] 0x5696 (DG2)
[18:04:48] [PASSED] 0x5697 (DG2)
[18:04:48] [PASSED] 0xB69 (PVC)
[18:04:48] [PASSED] 0xB6E (PVC)
[18:04:48] [PASSED] 0xBD4 (PVC)
[18:04:48] [PASSED] 0xBD5 (PVC)
[18:04:48] [PASSED] 0xBD6 (PVC)
[18:04:48] [PASSED] 0xBD7 (PVC)
[18:04:48] [PASSED] 0xBD8 (PVC)
[18:04:48] [PASSED] 0xBD9 (PVC)
[18:04:48] [PASSED] 0xBDA (PVC)
[18:04:48] [PASSED] 0xBDB (PVC)
[18:04:48] [PASSED] 0xBE0 (PVC)
[18:04:48] [PASSED] 0xBE1 (PVC)
[18:04:48] [PASSED] 0xBE5 (PVC)
[18:04:48] [PASSED] 0x7D40 (METEORLAKE)
[18:04:48] [PASSED] 0x7D45 (METEORLAKE)
[18:04:48] [PASSED] 0x7D55 (METEORLAKE)
[18:04:48] [PASSED] 0x7D60 (METEORLAKE)
[18:04:48] [PASSED] 0x7DD5 (METEORLAKE)
[18:04:48] [PASSED] 0x6420 (LUNARLAKE)
[18:04:48] [PASSED] 0x64A0 (LUNARLAKE)
[18:04:48] [PASSED] 0x64B0 (LUNARLAKE)
[18:04:48] [PASSED] 0xE202 (BATTLEMAGE)
[18:04:48] [PASSED] 0xE209 (BATTLEMAGE)
[18:04:48] [PASSED] 0xE20B (BATTLEMAGE)
[18:04:48] [PASSED] 0xE20C (BATTLEMAGE)
[18:04:48] [PASSED] 0xE20D (BATTLEMAGE)
[18:04:48] [PASSED] 0xE210 (BATTLEMAGE)
[18:04:48] [PASSED] 0xE211 (BATTLEMAGE)
[18:04:48] [PASSED] 0xE212 (BATTLEMAGE)
[18:04:48] [PASSED] 0xE216 (BATTLEMAGE)
[18:04:48] [PASSED] 0xE220 (BATTLEMAGE)
[18:04:48] [PASSED] 0xE221 (BATTLEMAGE)
[18:04:48] [PASSED] 0xE222 (BATTLEMAGE)
[18:04:48] [PASSED] 0xE223 (BATTLEMAGE)
[18:04:48] [PASSED] 0xB080 (PANTHERLAKE)
[18:04:48] [PASSED] 0xB081 (PANTHERLAKE)
[18:04:48] [PASSED] 0xB082 (PANTHERLAKE)
[18:04:48] [PASSED] 0xB083 (PANTHERLAKE)
[18:04:48] [PASSED] 0xB084 (PANTHERLAKE)
[18:04:48] [PASSED] 0xB085 (PANTHERLAKE)
[18:04:48] [PASSED] 0xB086 (PANTHERLAKE)
[18:04:48] [PASSED] 0xB087 (PANTHERLAKE)
[18:04:48] [PASSED] 0xB08F (PANTHERLAKE)
[18:04:48] [PASSED] 0xB090 (PANTHERLAKE)
[18:04:48] [PASSED] 0xB0A0 (PANTHERLAKE)
[18:04:48] [PASSED] 0xB0B0 (PANTHERLAKE)
[18:04:48] [PASSED] 0xFD80 (PANTHERLAKE)
[18:04:48] [PASSED] 0xFD81 (PANTHERLAKE)
[18:04:48] [PASSED] 0xD740 (NOVALAKE_S)
[18:04:48] [PASSED] 0xD741 (NOVALAKE_S)
[18:04:48] [PASSED] 0xD742 (NOVALAKE_S)
[18:04:48] [PASSED] 0xD743 (NOVALAKE_S)
[18:04:48] [PASSED] 0xD745 (NOVALAKE_S)
[18:04:48] [PASSED] 0xD74A (NOVALAKE_S)
[18:04:48] [PASSED] 0xD74B (NOVALAKE_S)
[18:04:48] [PASSED] 0x674C (CRESCENTISLAND)
[18:04:48] [PASSED] 0x674D (CRESCENTISLAND)
[18:04:48] [PASSED] 0x674E (CRESCENTISLAND)
[18:04:48] [PASSED] 0x674F (CRESCENTISLAND)
[18:04:48] [PASSED] 0x6750 (CRESCENTISLAND)
[18:04:48] [PASSED] 0xD750 (NOVALAKE_P)
[18:04:48] [PASSED] 0xD751 (NOVALAKE_P)
[18:04:48] [PASSED] 0xD752 (NOVALAKE_P)
[18:04:48] [PASSED] 0xD753 (NOVALAKE_P)
[18:04:48] [PASSED] 0xD754 (NOVALAKE_P)
[18:04:48] [PASSED] 0xD755 (NOVALAKE_P)
[18:04:48] [PASSED] 0xD756 (NOVALAKE_P)
[18:04:48] [PASSED] 0xD757 (NOVALAKE_P)
[18:04:48] [PASSED] 0xD75F (NOVALAKE_P)
[18:04:48] =============== [PASSED] check_platform_desc ===============
[18:04:48] ===================== [PASSED] xe_pci ======================
[18:04:48] ============= xe_rtp_tables_test (5 subtests) ==============
[18:04:48] ================== xe_rtp_table_gt_test ===================
[18:04:48] [PASSED] gt_was/14011060649
[18:04:48] [PASSED] gt_was/14011059788
[18:04:48] [PASSED] gt_was/14015795083
[18:04:48] [PASSED] gt_was/16021867713
[18:04:48] [PASSED] gt_was/14019449301
[18:04:48] [PASSED] gt_was/16028005424
[18:04:48] [PASSED] gt_was/14026578760
[18:04:48] [PASSED] gt_was/1409420604
[18:04:48] [PASSED] gt_was/1408615072
[18:04:48] [PASSED] gt_was/22010523718
[18:04:48] [PASSED] gt_was/14011006942
[18:04:48] [PASSED] gt_was/14014830051
[18:04:48] [PASSED] gt_was/18018781329
[18:04:48] [PASSED] gt_was/1509235366
[18:04:48] [PASSED] gt_was/18018781329
[18:04:48] [PASSED] gt_was/16016694945
[18:04:48] [PASSED] gt_was/14018575942
[18:04:48] [PASSED] gt_was/22016670082
[18:04:48] [PASSED] gt_was/22016670082
[18:04:48] [PASSED] gt_was/14017421178
[18:04:48] [PASSED] gt_was/16025250150
[18:04:48] [PASSED] gt_was/14021871409
[18:04:48] [PASSED] gt_was/16021865536
[18:04:48] [PASSED] gt_was/14021486841
[18:04:48] [PASSED] gt_was/14025160223
[18:04:48] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[18:04:48] [PASSED] gt_was/14025635424
[18:04:48] [PASSED] gt_was/16028005424
[18:04:48] ============== [PASSED] xe_rtp_table_gt_test ===============
[18:04:48] ================== xe_rtp_table_gt_test ===================
[18:04:48] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[18:04:48] [PASSED] gt_tunings/Tuning: 32B Access Enable
[18:04:48] [PASSED] gt_tunings/Tuning: L3 cache
[18:04:48] [PASSED] gt_tunings/Tuning: L3 cache - media
[18:04:48] [PASSED] gt_tunings/Tuning: Compression Overfetch
[18:04:48] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[18:04:48] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[18:04:48] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[18:04:48] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[18:04:48] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[18:04:48] [PASSED] gt_tunings/Tuning: Stateless compression control
[18:04:48] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[18:04:48] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[18:04:48] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[18:04:48] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[18:04:48] ============== [PASSED] xe_rtp_table_gt_test ===============
[18:04:48] ================== xe_rtp_table_oob_test ==================
[18:04:48] [PASSED] oob_was/1607983814
[18:04:48] [PASSED] oob_was/16010904313
[18:04:48] [PASSED] oob_was/18022495364
[18:04:48] [PASSED] oob_was/22012773006
[18:04:48] [PASSED] oob_was/14014475959
[18:04:48] [PASSED] oob_was/22011391025
[18:04:48] [PASSED] oob_was/22012727170
[18:04:48] [PASSED] oob_was/22012727685
[18:04:48] [PASSED] oob_was/22016596838
[18:04:48] [PASSED] oob_was/18020744125
[18:04:48] [PASSED] oob_was/1409600907
[18:04:48] [PASSED] oob_was/22014953428
[18:04:48] [PASSED] oob_was/16017236439
[18:04:48] [PASSED] oob_was/14019821291
[18:04:48] [PASSED] oob_was/14015076503
[18:04:48] [PASSED] oob_was/14018913170
[18:04:48] [PASSED] oob_was/14018094691
[18:04:48] [PASSED] oob_was/18024947630
[18:04:48] [PASSED] oob_was/16022287689
[18:04:48] [PASSED] oob_was/13011645652
[18:04:48] [PASSED] oob_was/14022293748
[18:04:48] [PASSED] oob_was/22019794406
[18:04:48] [PASSED] oob_was/22019338487
[18:04:48] [PASSED] oob_was/16023588340
[18:04:48] [PASSED] oob_was/14019789679
[18:04:48] [PASSED] oob_was/14022866841
[18:04:48] [PASSED] oob_was/16021333562
[18:04:48] [PASSED] oob_was/14016712196
[18:04:48] [PASSED] oob_was/14015568240
[18:04:48] [PASSED] oob_was/18013179988
[18:04:48] [PASSED] oob_was/1508761755
[18:04:48] [PASSED] oob_was/16023105232
[18:04:48] [PASSED] oob_was/16026508708
[18:04:48] [PASSED] oob_was/14020001231
[18:04:48] [PASSED] oob_was/16023683509
[18:04:48] [PASSED] oob_was/14025515070
[18:04:48] [PASSED] oob_was/15015404425_disable
[18:04:48] [PASSED] oob_was/16026007364
[18:04:48] [PASSED] oob_was/14020316580
[18:04:48] [PASSED] oob_was/14025883347
[18:04:48] [PASSED] oob_was/16029380221
[18:04:48] [PASSED] oob_was/22022079272
[18:04:48] [PASSED] oob_was/16029897822
[18:04:48] [PASSED] oob_was/14027054324
[18:04:48] ============== [PASSED] xe_rtp_table_oob_test ==============
[18:04:48] ================ xe_rtp_table_dev_oob_test ================
[18:04:48] [PASSED] device_oob_was/22010954014
[18:04:48] [PASSED] device_oob_was/15015404425
[18:04:48] [PASSED] device_oob_was/22019338487_display
[18:04:48] [PASSED] device_oob_was/14022085890
[18:04:48] [PASSED] device_oob_was/14026539277
[18:04:48] [PASSED] device_oob_was/14026633728
[18:04:48] [PASSED] device_oob_was/14026746987
[18:04:48] [PASSED] device_oob_was/14026779378
[18:04:48] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[18:04:48] ========== xe_rtp_table_missing_upper_bound_test ==========
[18:04:48] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[18:04:48] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[18:04:48] [PASSED] register_whitelist/1806527549
[18:04:48] [PASSED] register_whitelist/allow_read_ctx_timestamp
[18:04:48] [PASSED] register_whitelist/allow_read_queue_timestamp
[18:04:48] [PASSED] register_whitelist/16014440446
[18:04:48] [PASSED] register_whitelist/16017236439
[18:04:48] [PASSED] register_whitelist/16020183090
[18:04:48] [PASSED] register_whitelist/14024997852
[18:04:48] [PASSED] register_whitelist/14024997852
[18:04:48] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[18:04:48] =============== [PASSED] xe_rtp_tables_test ================
[18:04:48] =================== xe_rtp (3 subtests) ====================
[18:04:48] =================== xe_rtp_rules_tests ====================
[18:04:48] [PASSED] no
[18:04:48] [PASSED] yes
[18:04:48] [PASSED] no-and-no
[18:04:48] [PASSED] no-and-yes
[18:04:48] [PASSED] yes-and-no
[18:04:48] [PASSED] yes-and-yes
[18:04:48] [PASSED] no-or-no
[18:04:48] [PASSED] no-or-yes
[18:04:48] [PASSED] yes-or-no
[18:04:48] [PASSED] yes-or-yes
[18:04:48] [PASSED] no-yes-or-yes-no
[18:04:48] [PASSED] no-yes-or-yes-yes
[18:04:48] [PASSED] yes-yes-or-no-yes
[18:04:48] [PASSED] yes-yes-or-yes-yes
[18:04:48] [PASSED] no-no-or-yes-or-no
[18:04:48] [PASSED] or
[18:04:48] [PASSED] or-yes
[18:04:48] [PASSED] or-no
[18:04:48] [PASSED] yes-or
[18:04:48] [PASSED] no-or
[18:04:48] [PASSED] no-or-or-yes
[18:04:48] [PASSED] yes-or-or-no
[18:04:48] [PASSED] no-or-or-no
[18:04:48] [PASSED] missing-context-engine-class
[18:04:48] [PASSED] missing-context-engine-class-or-yes
[18:04:49] [PASSED] missing-context-engine-class-or-or-yes
[18:04:49] =============== [PASSED] xe_rtp_rules_tests ================
[18:04:49] =============== xe_rtp_process_to_sr_tests ================
[18:04:49] [PASSED] coalesce-same-reg
[18:04:49] [PASSED] coalesce-same-reg-literal-and-func
[18:04:49] [PASSED] no-match-no-add
[18:04:49] [PASSED] two-regs-two-entries
[18:04:49] [PASSED] clr-one-set-other
[18:04:49] [PASSED] set-field
[18:04:49] [PASSED] conflict-duplicate
[18:04:49] [PASSED] conflict-not-disjoint
[18:04:49] [PASSED] conflict-not-disjoint-literal-and-func
[18:04:49] [PASSED] conflict-reg-type
[18:04:49] [PASSED] bad-mcr-reg-forced-to-regular
[18:04:49] [PASSED] bad-regular-reg-forced-to-mcr
[18:04:49] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[18:04:49] ================== xe_rtp_process_tests ===================
[18:04:49] [PASSED] active1
[18:04:49] [PASSED] active2
[18:04:49] [PASSED] active-inactive
[18:04:49] [PASSED] inactive-active
[18:04:49] [PASSED] inactive-active-inactive
[18:04:49] [PASSED] inactive-inactive-inactive
[18:04:49] ============== [PASSED] xe_rtp_process_tests ===============
[18:04:49] ===================== [PASSED] xe_rtp ======================
[18:04:49] ==================== xe_wa (1 subtest) =====================
[18:04:49] ======================== xe_wa_gt =========================
[18:04:49] [PASSED] TIGERLAKE B0
[18:04:49] [PASSED] DG1 A0
[18:04:49] [PASSED] DG1 B0
[18:04:49] [PASSED] ALDERLAKE_S A0
[18:04:49] [PASSED] ALDERLAKE_S B0
[18:04:49] [PASSED] ALDERLAKE_S C0
[18:04:49] [PASSED] ALDERLAKE_S D0
[18:04:49] [PASSED] ALDERLAKE_P A0
[18:04:49] [PASSED] ALDERLAKE_P B0
[18:04:49] [PASSED] ALDERLAKE_P C0
[18:04:49] [PASSED] ALDERLAKE_S RPLS D0
[18:04:49] [PASSED] ALDERLAKE_P RPLU E0
[18:04:49] [PASSED] DG2 G10 C0
[18:04:49] [PASSED] DG2 G11 B1
[18:04:49] [PASSED] DG2 G12 A1
[18:04:49] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[18:04:49] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[18:04:49] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[18:04:49] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[18:04:49] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[18:04:49] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[18:04:49] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[18:04:49] ==================== [PASSED] xe_wa_gt =====================
[18:04:49] ====================== [PASSED] xe_wa ======================
[18:04:49] ============================================================
[18:04:49] Testing complete. Ran 742 tests: passed: 724, skipped: 18
[18:04:49] Elapsed time: 36.563s total, 4.368s configuring, 31.528s building, 0.644s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[18:04:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:04:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:05:15] Starting KUnit Kernel (1/1)...
[18:05:15] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:05:15] ============ drm_test_pick_cmdline (2 subtests) ============
[18:05:15] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[18:05:15] =============== drm_test_pick_cmdline_named ===============
[18:05:15] [PASSED] NTSC
[18:05:15] [PASSED] NTSC-J
[18:05:15] [PASSED] PAL
[18:05:15] [PASSED] PAL-M
[18:05:15] =========== [PASSED] drm_test_pick_cmdline_named ===========
[18:05:15] ============== [PASSED] drm_test_pick_cmdline ==============
[18:05:15] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[18:05:15] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[18:05:15] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[18:05:15] =========== drm_validate_clone_mode (2 subtests) ===========
[18:05:15] ============== drm_test_check_in_clone_mode ===============
[18:05:15] [PASSED] in_clone_mode
[18:05:15] [PASSED] not_in_clone_mode
[18:05:15] ========== [PASSED] drm_test_check_in_clone_mode ===========
[18:05:15] =============== drm_test_check_valid_clones ===============
[18:05:15] [PASSED] not_in_clone_mode
[18:05:15] [PASSED] valid_clone
[18:05:15] [PASSED] invalid_clone
[18:05:15] =========== [PASSED] drm_test_check_valid_clones ===========
[18:05:15] ============= [PASSED] drm_validate_clone_mode =============
[18:05:15] ============= drm_validate_modeset (1 subtest) =============
[18:05:15] [PASSED] drm_test_check_connector_changed_modeset
[18:05:15] ============== [PASSED] drm_validate_modeset ===============
[18:05:15] ====== drm_test_bridge_get_current_state (1 subtest) =======
[18:05:15] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[18:05:15] ======== [PASSED] drm_test_bridge_get_current_state ========
[18:05:15] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[18:05:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[18:05:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[18:05:15] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[18:05:15] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[18:05:15] ============== drm_bridge_alloc (2 subtests) ===============
[18:05:15] [PASSED] drm_test_drm_bridge_alloc_basic
[18:05:15] [PASSED] drm_test_drm_bridge_alloc_get_put
[18:05:15] ================ [PASSED] drm_bridge_alloc =================
[18:05:15] ============= drm_bridge_bus_fmt (5 subtests) ==============
[18:05:15] [PASSED] drm_test_bridge_rgb_yuv_rgb
[18:05:15] [PASSED] drm_test_bridge_must_convert_to_yuv444
[18:05:15] [PASSED] drm_test_bridge_hdmi_auto_rgb
[18:05:15] [PASSED] drm_test_bridge_auto_first
[18:05:15] [PASSED] drm_test_bridge_rgb_yuv_no_path
[18:05:15] =============== [PASSED] drm_bridge_bus_fmt ================
[18:05:15] ============= drm_cmdline_parser (40 subtests) =============
[18:05:15] [PASSED] drm_test_cmdline_force_d_only
[18:05:15] [PASSED] drm_test_cmdline_force_D_only_dvi
[18:05:15] [PASSED] drm_test_cmdline_force_D_only_hdmi
[18:05:15] [PASSED] drm_test_cmdline_force_D_only_not_digital
[18:05:15] [PASSED] drm_test_cmdline_force_e_only
[18:05:15] [PASSED] drm_test_cmdline_res
[18:05:15] [PASSED] drm_test_cmdline_res_vesa
[18:05:15] [PASSED] drm_test_cmdline_res_vesa_rblank
[18:05:15] [PASSED] drm_test_cmdline_res_rblank
[18:05:15] [PASSED] drm_test_cmdline_res_bpp
[18:05:15] [PASSED] drm_test_cmdline_res_refresh
[18:05:15] [PASSED] drm_test_cmdline_res_bpp_refresh
[18:05:15] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[18:05:15] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[18:05:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[18:05:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[18:05:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[18:05:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[18:05:15] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[18:05:15] [PASSED] drm_test_cmdline_res_margins_force_on
[18:05:15] [PASSED] drm_test_cmdline_res_vesa_margins
[18:05:15] [PASSED] drm_test_cmdline_name
[18:05:15] [PASSED] drm_test_cmdline_name_bpp
[18:05:15] [PASSED] drm_test_cmdline_name_option
[18:05:15] [PASSED] drm_test_cmdline_name_bpp_option
[18:05:15] [PASSED] drm_test_cmdline_rotate_0
[18:05:15] [PASSED] drm_test_cmdline_rotate_90
[18:05:15] [PASSED] drm_test_cmdline_rotate_180
[18:05:15] [PASSED] drm_test_cmdline_rotate_270
[18:05:15] [PASSED] drm_test_cmdline_hmirror
[18:05:15] [PASSED] drm_test_cmdline_vmirror
[18:05:15] [PASSED] drm_test_cmdline_margin_options
[18:05:15] [PASSED] drm_test_cmdline_multiple_options
[18:05:15] [PASSED] drm_test_cmdline_bpp_extra_and_option
[18:05:15] [PASSED] drm_test_cmdline_extra_and_option
[18:05:15] [PASSED] drm_test_cmdline_freestanding_options
[18:05:15] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[18:05:15] [PASSED] drm_test_cmdline_panel_orientation
[18:05:15] ================ drm_test_cmdline_invalid =================
[18:05:15] [PASSED] margin_only
[18:05:15] [PASSED] interlace_only
[18:05:15] [PASSED] res_missing_x
[18:05:15] [PASSED] res_missing_y
[18:05:15] [PASSED] res_bad_y
[18:05:15] [PASSED] res_missing_y_bpp
[18:05:15] [PASSED] res_bad_bpp
[18:05:15] [PASSED] res_bad_refresh
[18:05:15] [PASSED] res_bpp_refresh_force_on_off
[18:05:15] [PASSED] res_invalid_mode
[18:05:15] [PASSED] res_bpp_wrong_place_mode
[18:05:15] [PASSED] name_bpp_refresh
[18:05:15] [PASSED] name_refresh
[18:05:15] [PASSED] name_refresh_wrong_mode
[18:05:15] [PASSED] name_refresh_invalid_mode
[18:05:15] [PASSED] rotate_multiple
[18:05:15] [PASSED] rotate_invalid_val
[18:05:15] [PASSED] rotate_truncated
[18:05:15] [PASSED] invalid_option
[18:05:15] [PASSED] invalid_tv_option
[18:05:15] [PASSED] truncated_tv_option
[18:05:15] ============ [PASSED] drm_test_cmdline_invalid =============
[18:05:15] =============== drm_test_cmdline_tv_options ===============
[18:05:15] [PASSED] NTSC
[18:05:15] [PASSED] NTSC_443
[18:05:15] [PASSED] NTSC_J
[18:05:15] [PASSED] PAL
[18:05:15] [PASSED] PAL_M
[18:05:15] [PASSED] PAL_N
[18:05:15] [PASSED] SECAM
[18:05:15] [PASSED] MONO_525
[18:05:15] [PASSED] MONO_625
[18:05:15] =========== [PASSED] drm_test_cmdline_tv_options ===========
[18:05:15] =============== [PASSED] drm_cmdline_parser ================
[18:05:15] ========== drmm_connector_hdmi_init (20 subtests) ==========
[18:05:15] [PASSED] drm_test_connector_hdmi_init_valid
[18:05:15] [PASSED] drm_test_connector_hdmi_init_bpc_8
[18:05:15] [PASSED] drm_test_connector_hdmi_init_bpc_10
[18:05:15] [PASSED] drm_test_connector_hdmi_init_bpc_12
[18:05:15] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[18:05:15] [PASSED] drm_test_connector_hdmi_init_bpc_null
[18:05:15] [PASSED] drm_test_connector_hdmi_init_formats_empty
[18:05:15] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[18:05:15] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[18:05:15] [PASSED] supported_formats=0x9 yuv420_allowed=1
[18:05:15] [PASSED] supported_formats=0x9 yuv420_allowed=0
[18:05:15] [PASSED] supported_formats=0x5 yuv420_allowed=1
[18:05:15] [PASSED] supported_formats=0x5 yuv420_allowed=0
[18:05:15] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[18:05:15] [PASSED] drm_test_connector_hdmi_init_null_ddc
[18:05:15] [PASSED] drm_test_connector_hdmi_init_null_product
[18:05:15] [PASSED] drm_test_connector_hdmi_init_null_vendor
[18:05:15] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[18:05:15] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[18:05:15] [PASSED] drm_test_connector_hdmi_init_product_valid
[18:05:15] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[18:05:15] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[18:05:15] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[18:05:15] ========= drm_test_connector_hdmi_init_type_valid =========
[18:05:15] [PASSED] HDMI-A
[18:05:15] [PASSED] HDMI-B
[18:05:15] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[18:05:15] ======== drm_test_connector_hdmi_init_type_invalid ========
[18:05:15] [PASSED] Unknown
[18:05:15] [PASSED] VGA
[18:05:15] [PASSED] DVI-I
[18:05:15] [PASSED] DVI-D
[18:05:15] [PASSED] DVI-A
[18:05:15] [PASSED] Composite
[18:05:15] [PASSED] SVIDEO
[18:05:15] [PASSED] LVDS
[18:05:15] [PASSED] Component
[18:05:15] [PASSED] DIN
[18:05:15] [PASSED] DP
[18:05:15] [PASSED] TV
[18:05:15] [PASSED] eDP
[18:05:15] [PASSED] Virtual
[18:05:15] [PASSED] DSI
[18:05:15] [PASSED] DPI
[18:05:15] [PASSED] Writeback
[18:05:15] [PASSED] SPI
[18:05:15] [PASSED] USB
[18:05:15] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[18:05:15] ============ [PASSED] drmm_connector_hdmi_init =============
[18:05:15] ============= drmm_connector_init (3 subtests) =============
[18:05:15] [PASSED] drm_test_drmm_connector_init
[18:05:15] [PASSED] drm_test_drmm_connector_init_null_ddc
[18:05:15] ========= drm_test_drmm_connector_init_type_valid =========
[18:05:15] [PASSED] Unknown
[18:05:15] [PASSED] VGA
[18:05:15] [PASSED] DVI-I
[18:05:15] [PASSED] DVI-D
[18:05:15] [PASSED] DVI-A
[18:05:15] [PASSED] Composite
[18:05:15] [PASSED] SVIDEO
[18:05:15] [PASSED] LVDS
[18:05:15] [PASSED] Component
[18:05:15] [PASSED] DIN
[18:05:15] [PASSED] DP
[18:05:15] [PASSED] HDMI-A
[18:05:15] [PASSED] HDMI-B
[18:05:15] [PASSED] TV
[18:05:15] [PASSED] eDP
[18:05:15] [PASSED] Virtual
[18:05:15] [PASSED] DSI
[18:05:15] [PASSED] DPI
[18:05:15] [PASSED] Writeback
[18:05:15] [PASSED] SPI
[18:05:15] [PASSED] USB
[18:05:15] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[18:05:15] =============== [PASSED] drmm_connector_init ===============
[18:05:15] ========= drm_connector_dynamic_init (6 subtests) ==========
[18:05:15] [PASSED] drm_test_drm_connector_dynamic_init
[18:05:15] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[18:05:15] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[18:05:15] [PASSED] drm_test_drm_connector_dynamic_init_properties
[18:05:15] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[18:05:15] [PASSED] Unknown
[18:05:15] [PASSED] VGA
[18:05:15] [PASSED] DVI-I
[18:05:15] [PASSED] DVI-D
[18:05:15] [PASSED] DVI-A
[18:05:15] [PASSED] Composite
[18:05:15] [PASSED] SVIDEO
[18:05:15] [PASSED] LVDS
[18:05:15] [PASSED] Component
[18:05:15] [PASSED] DIN
[18:05:15] [PASSED] DP
[18:05:15] [PASSED] HDMI-A
[18:05:15] [PASSED] HDMI-B
[18:05:15] [PASSED] TV
[18:05:15] [PASSED] eDP
[18:05:15] [PASSED] Virtual
[18:05:15] [PASSED] DSI
[18:05:15] [PASSED] DPI
[18:05:15] [PASSED] Writeback
[18:05:15] [PASSED] SPI
[18:05:15] [PASSED] USB
[18:05:15] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[18:05:15] ======== drm_test_drm_connector_dynamic_init_name =========
[18:05:15] [PASSED] Unknown
[18:05:15] [PASSED] VGA
[18:05:15] [PASSED] DVI-I
[18:05:15] [PASSED] DVI-D
[18:05:15] [PASSED] DVI-A
[18:05:15] [PASSED] Composite
[18:05:15] [PASSED] SVIDEO
[18:05:15] [PASSED] LVDS
[18:05:15] [PASSED] Component
[18:05:15] [PASSED] DIN
[18:05:15] [PASSED] DP
[18:05:15] [PASSED] HDMI-A
[18:05:15] [PASSED] HDMI-B
[18:05:15] [PASSED] TV
[18:05:15] [PASSED] eDP
[18:05:15] [PASSED] Virtual
[18:05:15] [PASSED] DSI
[18:05:15] [PASSED] DPI
[18:05:15] [PASSED] Writeback
[18:05:15] [PASSED] SPI
[18:05:15] [PASSED] USB
[18:05:15] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[18:05:15] =========== [PASSED] drm_connector_dynamic_init ============
[18:05:15] ==== drm_connector_dynamic_register_early (4 subtests) =====
[18:05:15] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[18:05:15] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[18:05:15] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[18:05:15] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[18:05:15] ====== [PASSED] drm_connector_dynamic_register_early =======
[18:05:15] ======= drm_connector_dynamic_register (7 subtests) ========
[18:05:15] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[18:05:15] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[18:05:15] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[18:05:15] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[18:05:15] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[18:05:15] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[18:05:15] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[18:05:15] ========= [PASSED] drm_connector_dynamic_register ==========
[18:05:15] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[18:05:15] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[18:05:15] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[18:05:15] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[18:05:15] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[18:05:15] ========== drm_test_get_tv_mode_from_name_valid ===========
[18:05:15] [PASSED] NTSC
[18:05:15] [PASSED] NTSC-443
[18:05:15] [PASSED] NTSC-J
[18:05:15] [PASSED] PAL
[18:05:15] [PASSED] PAL-M
[18:05:15] [PASSED] PAL-N
[18:05:15] [PASSED] SECAM
[18:05:15] [PASSED] Mono
[18:05:15] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[18:05:15] [PASSED] drm_test_get_tv_mode_from_name_truncated
[18:05:15] ============ [PASSED] drm_get_tv_mode_from_name ============
[18:05:15] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[18:05:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[18:05:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[18:05:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[18:05:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[18:05:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[18:05:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[18:05:15] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[18:05:15] [PASSED] VIC 96
[18:05:15] [PASSED] VIC 97
[18:05:15] [PASSED] VIC 101
[18:05:15] [PASSED] VIC 102
[18:05:15] [PASSED] VIC 106
[18:05:15] [PASSED] VIC 107
[18:05:15] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[18:05:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[18:05:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[18:05:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[18:05:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[18:05:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[18:05:15] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[18:05:15] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[18:05:15] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[18:05:15] [PASSED] Automatic
[18:05:15] [PASSED] Full
[18:05:15] [PASSED] Limited 16:235
[18:05:15] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[18:05:15] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[18:05:15] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[18:05:15] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[18:05:15] === drm_test_drm_hdmi_connector_get_output_format_name ====
[18:05:15] [PASSED] RGB
[18:05:15] [PASSED] YUV 4:2:0
[18:05:15] [PASSED] YUV 4:2:2
[18:05:15] [PASSED] YUV 4:4:4
[18:05:15] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[18:05:15] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[18:05:15] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[18:05:15] ============= drm_damage_helper (21 subtests) ==============
[18:05:15] [PASSED] drm_test_damage_iter_no_damage
[18:05:15] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[18:05:15] [PASSED] drm_test_damage_iter_no_damage_src_moved
[18:05:15] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[18:05:15] [PASSED] drm_test_damage_iter_no_damage_not_visible
[18:05:15] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[18:05:15] [PASSED] drm_test_damage_iter_no_damage_no_fb
[18:05:15] [PASSED] drm_test_damage_iter_simple_damage
[18:05:15] [PASSED] drm_test_damage_iter_single_damage
[18:05:15] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[18:05:15] [PASSED] drm_test_damage_iter_single_damage_outside_src
[18:05:15] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[18:05:15] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[18:05:15] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[18:05:15] [PASSED] drm_test_damage_iter_single_damage_src_moved
[18:05:15] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[18:05:15] [PASSED] drm_test_damage_iter_damage
[18:05:15] [PASSED] drm_test_damage_iter_damage_one_intersect
[18:05:15] [PASSED] drm_test_damage_iter_damage_one_outside
[18:05:15] [PASSED] drm_test_damage_iter_damage_src_moved
[18:05:15] [PASSED] drm_test_damage_iter_damage_not_visible
[18:05:15] ================ [PASSED] drm_damage_helper ================
[18:05:15] ============== drm_dp_mst_helper (3 subtests) ==============
[18:05:15] ============== drm_test_dp_mst_calc_pbn_mode ==============
[18:05:15] [PASSED] Clock 154000 BPP 30 DSC disabled
[18:05:15] [PASSED] Clock 234000 BPP 30 DSC disabled
[18:05:15] [PASSED] Clock 297000 BPP 24 DSC disabled
[18:05:15] [PASSED] Clock 332880 BPP 24 DSC enabled
[18:05:15] [PASSED] Clock 324540 BPP 24 DSC enabled
[18:05:15] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[18:05:15] ============== drm_test_dp_mst_calc_pbn_div ===============
[18:05:15] [PASSED] Link rate 2000000 lane count 4
[18:05:15] [PASSED] Link rate 2000000 lane count 2
[18:05:15] [PASSED] Link rate 2000000 lane count 1
[18:05:15] [PASSED] Link rate 1350000 lane count 4
[18:05:15] [PASSED] Link rate 1350000 lane count 2
[18:05:15] [PASSED] Link rate 1350000 lane count 1
[18:05:15] [PASSED] Link rate 1000000 lane count 4
[18:05:15] [PASSED] Link rate 1000000 lane count 2
[18:05:15] [PASSED] Link rate 1000000 lane count 1
[18:05:15] [PASSED] Link rate 810000 lane count 4
[18:05:15] [PASSED] Link rate 810000 lane count 2
[18:05:15] [PASSED] Link rate 810000 lane count 1
[18:05:15] [PASSED] Link rate 540000 lane count 4
[18:05:15] [PASSED] Link rate 540000 lane count 2
[18:05:15] [PASSED] Link rate 540000 lane count 1
[18:05:15] [PASSED] Link rate 270000 lane count 4
[18:05:15] [PASSED] Link rate 270000 lane count 2
[18:05:15] [PASSED] Link rate 270000 lane count 1
[18:05:15] [PASSED] Link rate 162000 lane count 4
[18:05:15] [PASSED] Link rate 162000 lane count 2
[18:05:15] [PASSED] Link rate 162000 lane count 1
[18:05:15] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[18:05:15] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[18:05:15] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[18:05:15] [PASSED] DP_POWER_UP_PHY with port number
[18:05:15] [PASSED] DP_POWER_DOWN_PHY with port number
[18:05:15] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[18:05:15] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[18:05:15] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[18:05:15] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[18:05:15] [PASSED] DP_QUERY_PAYLOAD with port number
[18:05:15] [PASSED] DP_QUERY_PAYLOAD with VCPI
[18:05:15] [PASSED] DP_REMOTE_DPCD_READ with port number
[18:05:15] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[18:05:15] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[18:05:15] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[18:05:15] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[18:05:15] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[18:05:15] [PASSED] DP_REMOTE_I2C_READ with port number
[18:05:15] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[18:05:15] [PASSED] DP_REMOTE_I2C_READ with transactions array
[18:05:15] [PASSED] DP_REMOTE_I2C_WRITE with port number
[18:05:15] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[18:05:15] [PASSED] DP_REMOTE_I2C_WRITE with data array
[18:05:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[18:05:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[18:05:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[18:05:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[18:05:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[18:05:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[18:05:15] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[18:05:15] ================ [PASSED] drm_dp_mst_helper ================
[18:05:15] ================== drm_exec (7 subtests) ===================
[18:05:15] [PASSED] sanitycheck
[18:05:15] [PASSED] test_lock
[18:05:15] [PASSED] test_lock_unlock
[18:05:15] [PASSED] test_duplicates
[18:05:15] [PASSED] test_prepare
[18:05:15] [PASSED] test_prepare_array
[18:05:15] [PASSED] test_multiple_loops
[18:05:15] ==================== [PASSED] drm_exec =====================
[18:05:15] =========== drm_format_helper_test (17 subtests) ===========
[18:05:15] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[18:05:15] [PASSED] single_pixel_source_buffer
[18:05:15] [PASSED] single_pixel_clip_rectangle
[18:05:15] [PASSED] well_known_colors
[18:05:15] [PASSED] destination_pitch
[18:05:15] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[18:05:15] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[18:05:15] [PASSED] single_pixel_source_buffer
[18:05:15] [PASSED] single_pixel_clip_rectangle
[18:05:15] [PASSED] well_known_colors
[18:05:15] [PASSED] destination_pitch
[18:05:15] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[18:05:15] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[18:05:15] [PASSED] single_pixel_source_buffer
[18:05:15] [PASSED] single_pixel_clip_rectangle
[18:05:15] [PASSED] well_known_colors
[18:05:15] [PASSED] destination_pitch
[18:05:15] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[18:05:15] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[18:05:15] [PASSED] single_pixel_source_buffer
[18:05:15] [PASSED] single_pixel_clip_rectangle
[18:05:15] [PASSED] well_known_colors
[18:05:15] [PASSED] destination_pitch
[18:05:15] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[18:05:15] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[18:05:15] [PASSED] single_pixel_source_buffer
[18:05:15] [PASSED] single_pixel_clip_rectangle
[18:05:15] [PASSED] well_known_colors
[18:05:15] [PASSED] destination_pitch
[18:05:15] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[18:05:15] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[18:05:15] [PASSED] single_pixel_source_buffer
[18:05:15] [PASSED] single_pixel_clip_rectangle
[18:05:15] [PASSED] well_known_colors
[18:05:15] [PASSED] destination_pitch
[18:05:15] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[18:05:15] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[18:05:15] [PASSED] single_pixel_source_buffer
[18:05:15] [PASSED] single_pixel_clip_rectangle
[18:05:15] [PASSED] well_known_colors
[18:05:15] [PASSED] destination_pitch
[18:05:15] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[18:05:15] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[18:05:15] [PASSED] single_pixel_source_buffer
[18:05:15] [PASSED] single_pixel_clip_rectangle
[18:05:15] [PASSED] well_known_colors
[18:05:15] [PASSED] destination_pitch
[18:05:15] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[18:05:15] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[18:05:15] [PASSED] single_pixel_source_buffer
[18:05:15] [PASSED] single_pixel_clip_rectangle
[18:05:15] [PASSED] well_known_colors
[18:05:15] [PASSED] destination_pitch
[18:05:15] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[18:05:15] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[18:05:15] [PASSED] single_pixel_source_buffer
[18:05:15] [PASSED] single_pixel_clip_rectangle
[18:05:15] [PASSED] well_known_colors
[18:05:15] [PASSED] destination_pitch
[18:05:15] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[18:05:15] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[18:05:15] [PASSED] single_pixel_source_buffer
[18:05:15] [PASSED] single_pixel_clip_rectangle
[18:05:15] [PASSED] well_known_colors
[18:05:15] [PASSED] destination_pitch
[18:05:15] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[18:05:15] ============== drm_test_fb_xrgb8888_to_mono ===============
[18:05:15] [PASSED] single_pixel_source_buffer
[18:05:15] [PASSED] single_pixel_clip_rectangle
[18:05:15] [PASSED] well_known_colors
[18:05:15] [PASSED] destination_pitch
[18:05:15] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[18:05:15] ==================== drm_test_fb_swab =====================
[18:05:15] [PASSED] single_pixel_source_buffer
[18:05:15] [PASSED] single_pixel_clip_rectangle
[18:05:15] [PASSED] well_known_colors
[18:05:15] [PASSED] destination_pitch
[18:05:15] ================ [PASSED] drm_test_fb_swab =================
[18:05:15] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[18:05:15] [PASSED] single_pixel_source_buffer
[18:05:15] [PASSED] single_pixel_clip_rectangle
[18:05:15] [PASSED] well_known_colors
[18:05:15] [PASSED] destination_pitch
[18:05:15] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[18:05:15] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[18:05:15] [PASSED] single_pixel_source_buffer
[18:05:15] [PASSED] single_pixel_clip_rectangle
[18:05:15] [PASSED] well_known_colors
[18:05:15] [PASSED] destination_pitch
[18:05:15] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[18:05:15] ================= drm_test_fb_clip_offset =================
[18:05:15] [PASSED] pass through
[18:05:15] [PASSED] horizontal offset
[18:05:15] [PASSED] vertical offset
[18:05:15] [PASSED] horizontal and vertical offset
[18:05:15] [PASSED] horizontal offset (custom pitch)
[18:05:15] [PASSED] vertical offset (custom pitch)
[18:05:15] [PASSED] horizontal and vertical offset (custom pitch)
[18:05:15] ============= [PASSED] drm_test_fb_clip_offset =============
[18:05:15] =================== drm_test_fb_memcpy ====================
[18:05:15] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[18:05:15] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[18:05:15] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[18:05:15] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[18:05:15] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[18:05:15] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[18:05:15] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[18:05:15] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[18:05:15] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[18:05:15] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[18:05:15] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[18:05:15] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[18:05:15] =============== [PASSED] drm_test_fb_memcpy ================
[18:05:15] ============= [PASSED] drm_format_helper_test ==============
[18:05:15] ================= drm_format (18 subtests) =================
[18:05:15] [PASSED] drm_test_format_block_width_invalid
[18:05:15] [PASSED] drm_test_format_block_width_one_plane
[18:05:15] [PASSED] drm_test_format_block_width_two_plane
[18:05:15] [PASSED] drm_test_format_block_width_three_plane
[18:05:15] [PASSED] drm_test_format_block_width_tiled
[18:05:15] [PASSED] drm_test_format_block_height_invalid
[18:05:15] [PASSED] drm_test_format_block_height_one_plane
[18:05:15] [PASSED] drm_test_format_block_height_two_plane
[18:05:15] [PASSED] drm_test_format_block_height_three_plane
[18:05:15] [PASSED] drm_test_format_block_height_tiled
[18:05:15] [PASSED] drm_test_format_min_pitch_invalid
[18:05:15] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[18:05:15] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[18:05:15] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[18:05:15] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[18:05:15] [PASSED] drm_test_format_min_pitch_two_plane
[18:05:15] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[18:05:15] [PASSED] drm_test_format_min_pitch_tiled
[18:05:15] =================== [PASSED] drm_format ====================
[18:05:15] ============== drm_framebuffer (10 subtests) ===============
[18:05:15] ========== drm_test_framebuffer_check_src_coords ==========
[18:05:15] [PASSED] Success: source fits into fb
[18:05:15] [PASSED] Fail: overflowing fb with x-axis coordinate
[18:05:15] [PASSED] Fail: overflowing fb with y-axis coordinate
[18:05:15] [PASSED] Fail: overflowing fb with source width
[18:05:15] [PASSED] Fail: overflowing fb with source height
[18:05:15] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[18:05:15] [PASSED] drm_test_framebuffer_cleanup
[18:05:15] =============== drm_test_framebuffer_create ===============
[18:05:15] [PASSED] ABGR8888 normal sizes
[18:05:15] [PASSED] ABGR8888 max sizes
[18:05:15] [PASSED] ABGR8888 pitch greater than min required
[18:05:15] [PASSED] ABGR8888 pitch less than min required
[18:05:15] [PASSED] ABGR8888 Invalid width
[18:05:15] [PASSED] ABGR8888 Invalid buffer handle
[18:05:15] [PASSED] No pixel format
[18:05:15] [PASSED] ABGR8888 Width 0
[18:05:15] [PASSED] ABGR8888 Height 0
[18:05:15] [PASSED] ABGR8888 Out of bound height * pitch combination
[18:05:15] [PASSED] ABGR8888 Large buffer offset
[18:05:15] [PASSED] ABGR8888 Buffer offset for inexistent plane
[18:05:15] [PASSED] ABGR8888 Invalid flag
[18:05:15] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[18:05:15] [PASSED] ABGR8888 Valid buffer modifier
[18:05:15] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[18:05:15] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[18:05:15] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[18:05:15] [PASSED] NV12 Normal sizes
[18:05:15] [PASSED] NV12 Max sizes
[18:05:15] [PASSED] NV12 Invalid pitch
[18:05:15] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[18:05:15] [PASSED] NV12 different modifier per-plane
[18:05:15] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[18:05:15] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[18:05:15] [PASSED] NV12 Modifier for inexistent plane
[18:05:15] [PASSED] NV12 Handle for inexistent plane
[18:05:15] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[18:05:15] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[18:05:15] [PASSED] YVU420 Normal sizes
[18:05:15] [PASSED] YVU420 Max sizes
[18:05:15] [PASSED] YVU420 Invalid pitch
[18:05:15] [PASSED] YVU420 Different pitches
[18:05:15] [PASSED] YVU420 Different buffer offsets/pitches
[18:05:15] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[18:05:15] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[18:05:15] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[18:05:15] [PASSED] YVU420 Valid modifier
[18:05:15] [PASSED] YVU420 Different modifiers per plane
[18:05:15] [PASSED] YVU420 Modifier for inexistent plane
[18:05:15] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[18:05:15] [PASSED] X0L2 Normal sizes
[18:05:15] [PASSED] X0L2 Max sizes
[18:05:15] [PASSED] X0L2 Invalid pitch
[18:05:15] [PASSED] X0L2 Pitch greater than minimum required
[18:05:15] [PASSED] X0L2 Handle for inexistent plane
[18:05:15] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[18:05:15] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[18:05:15] [PASSED] X0L2 Valid modifier
[18:05:15] [PASSED] X0L2 Modifier for inexistent plane
[18:05:15] =========== [PASSED] drm_test_framebuffer_create ===========
[18:05:15] [PASSED] drm_test_framebuffer_free
[18:05:15] [PASSED] drm_test_framebuffer_init
[18:05:15] [PASSED] drm_test_framebuffer_init_bad_format
[18:05:15] [PASSED] drm_test_framebuffer_init_dev_mismatch
[18:05:15] [PASSED] drm_test_framebuffer_lookup
[18:05:15] [PASSED] drm_test_framebuffer_lookup_inexistent
[18:05:15] [PASSED] drm_test_framebuffer_modifiers_not_supported
[18:05:15] ================= [PASSED] drm_framebuffer =================
[18:05:15] ================ drm_gem_shmem (8 subtests) ================
[18:05:15] [PASSED] drm_gem_shmem_test_obj_create
[18:05:15] [PASSED] drm_gem_shmem_test_obj_create_private
[18:05:15] [PASSED] drm_gem_shmem_test_pin_pages
[18:05:15] [PASSED] drm_gem_shmem_test_vmap
[18:05:15] [PASSED] drm_gem_shmem_test_get_sg_table
[18:05:15] [PASSED] drm_gem_shmem_test_get_pages_sgt
[18:05:15] [PASSED] drm_gem_shmem_test_madvise
[18:05:15] [PASSED] drm_gem_shmem_test_purge
[18:05:15] ================== [PASSED] drm_gem_shmem ==================
[18:05:15] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[18:05:15] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[18:05:15] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[18:05:15] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[18:05:15] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[18:05:15] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[18:05:15] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[18:05:15] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[18:05:15] [PASSED] Automatic
[18:05:15] [PASSED] Full
[18:05:15] [PASSED] Limited 16:235
[18:05:15] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[18:05:15] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[18:05:15] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[18:05:15] [PASSED] drm_test_check_disable_connector
[18:05:15] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[18:05:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[18:05:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[18:05:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[18:05:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[18:05:15] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[18:05:15] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[18:05:15] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[18:05:15] [PASSED] drm_test_check_output_bpc_dvi
[18:05:15] [PASSED] drm_test_check_output_bpc_format_vic_1
[18:05:15] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[18:05:15] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[18:05:15] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[18:05:15] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[18:05:15] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[18:05:15] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[18:05:15] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[18:05:15] ============ drm_test_check_hdmi_color_format =============
[18:05:15] [PASSED] AUTO -> RGB
[18:05:15] [PASSED] YCBCR422 -> YUV422
[18:05:15] [PASSED] YCBCR420 -> YUV420
[18:05:15] [PASSED] YCBCR444 -> YUV444
[18:05:15] [PASSED] RGB -> RGB
[18:05:15] ======== [PASSED] drm_test_check_hdmi_color_format =========
[18:05:15] ======== drm_test_check_hdmi_color_format_420_only ========
[18:05:15] [PASSED] RGB should fail
[18:05:15] [PASSED] YUV444 should fail
[18:05:15] [PASSED] YUV422 should fail
[18:05:15] [PASSED] YUV420 should work
[18:05:15] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[18:05:15] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[18:05:15] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[18:05:15] [PASSED] drm_test_check_broadcast_rgb_value
[18:05:15] [PASSED] drm_test_check_bpc_8_value
[18:05:15] [PASSED] drm_test_check_bpc_10_value
[18:05:15] [PASSED] drm_test_check_bpc_12_value
[18:05:15] [PASSED] drm_test_check_format_value
[18:05:15] [PASSED] drm_test_check_tmds_char_value
[18:05:15] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[18:05:15] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[18:05:15] [PASSED] drm_test_check_mode_valid
[18:05:15] [PASSED] drm_test_check_mode_valid_reject
[18:05:15] [PASSED] drm_test_check_mode_valid_reject_rate
[18:05:15] [PASSED] drm_test_check_mode_valid_reject_max_clock
[18:05:15] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[18:05:15] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[18:05:15] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[18:05:15] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[18:05:15] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[18:05:15] [PASSED] drm_test_check_infoframes
[18:05:15] [PASSED] drm_test_check_reject_avi_infoframe
[18:05:15] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[18:05:15] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[18:05:15] [PASSED] drm_test_check_reject_audio_infoframe
[18:05:15] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[18:05:15] ================= drm_managed (2 subtests) =================
[18:05:15] [PASSED] drm_test_managed_release_action
[18:05:15] [PASSED] drm_test_managed_run_action
[18:05:15] =================== [PASSED] drm_managed ===================
[18:05:15] =================== drm_mm (6 subtests) ====================
[18:05:15] [PASSED] drm_test_mm_init
[18:05:15] [PASSED] drm_test_mm_debug
[18:05:15] [PASSED] drm_test_mm_align32
[18:05:15] [PASSED] drm_test_mm_align64
[18:05:15] [PASSED] drm_test_mm_lowest
[18:05:15] [PASSED] drm_test_mm_highest
[18:05:15] ===================== [PASSED] drm_mm ======================
[18:05:15] ============= drm_modes_analog_tv (5 subtests) =============
[18:05:15] [PASSED] drm_test_modes_analog_tv_mono_576i
[18:05:15] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[18:05:15] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[18:05:15] [PASSED] drm_test_modes_analog_tv_pal_576i
[18:05:15] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[18:05:15] =============== [PASSED] drm_modes_analog_tv ===============
[18:05:15] ============== drm_plane_helper (2 subtests) ===============
[18:05:15] =============== drm_test_check_plane_state ================
[18:05:15] [PASSED] clipping_simple
[18:05:15] [PASSED] clipping_rotate_reflect
[18:05:15] [PASSED] positioning_simple
[18:05:15] [PASSED] upscaling
[18:05:15] [PASSED] downscaling
[18:05:15] [PASSED] rounding1
[18:05:15] [PASSED] rounding2
[18:05:15] [PASSED] rounding3
[18:05:15] [PASSED] rounding4
[18:05:15] =========== [PASSED] drm_test_check_plane_state ============
[18:05:15] =========== drm_test_check_invalid_plane_state ============
[18:05:15] [PASSED] positioning_invalid
[18:05:15] [PASSED] upscaling_invalid
[18:05:15] [PASSED] downscaling_invalid
[18:05:15] ======= [PASSED] drm_test_check_invalid_plane_state ========
[18:05:15] ================ [PASSED] drm_plane_helper =================
[18:05:15] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[18:05:15] ====== drm_test_connector_helper_tv_get_modes_check =======
[18:05:15] [PASSED] None
[18:05:15] [PASSED] PAL
[18:05:15] [PASSED] NTSC
[18:05:15] [PASSED] Both, NTSC Default
[18:05:15] [PASSED] Both, PAL Default
[18:05:15] [PASSED] Both, NTSC Default, with PAL on command-line
[18:05:15] [PASSED] Both, PAL Default, with NTSC on command-line
[18:05:15] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[18:05:15] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[18:05:15] ================== drm_rect (9 subtests) ===================
[18:05:15] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[18:05:15] [PASSED] drm_test_rect_clip_scaled_not_clipped
[18:05:15] [PASSED] drm_test_rect_clip_scaled_clipped
[18:05:15] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[18:05:15] ================= drm_test_rect_intersect =================
[18:05:15] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[18:05:15] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[18:05:15] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[18:05:15] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[18:05:15] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[18:05:15] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[18:05:15] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[18:05:15] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[18:05:15] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[18:05:15] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[18:05:15] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[18:05:15] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[18:05:15] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[18:05:15] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[18:05:15] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[18:05:15] ============= [PASSED] drm_test_rect_intersect =============
[18:05:15] ================ drm_test_rect_calc_hscale ================
[18:05:15] [PASSED] normal use
[18:05:15] [PASSED] out of max range
[18:05:15] [PASSED] out of min range
[18:05:15] [PASSED] zero dst
[18:05:15] [PASSED] negative src
[18:05:15] [PASSED] negative dst
[18:05:15] ============ [PASSED] drm_test_rect_calc_hscale ============
[18:05:15] ================ drm_test_rect_calc_vscale ================
[18:05:15] [PASSED] normal use
[18:05:15] [PASSED] out of max range
[18:05:15] [PASSED] out of min range
[18:05:15] [PASSED] zero dst
[18:05:15] [PASSED] negative src
[18:05:15] [PASSED] negative dst
[18:05:15] ============ [PASSED] drm_test_rect_calc_vscale ============
[18:05:15] ================== drm_test_rect_rotate ===================
[18:05:15] [PASSED] reflect-x
[18:05:15] [PASSED] reflect-y
[18:05:15] [PASSED] rotate-0
[18:05:15] [PASSED] rotate-90
[18:05:15] [PASSED] rotate-180
[18:05:15] [PASSED] rotate-270
[18:05:15] ============== [PASSED] drm_test_rect_rotate ===============
[18:05:15] ================ drm_test_rect_rotate_inv =================
[18:05:15] [PASSED] reflect-x
[18:05:15] [PASSED] reflect-y
[18:05:15] [PASSED] rotate-0
[18:05:15] [PASSED] rotate-90
[18:05:15] [PASSED] rotate-180
[18:05:15] [PASSED] rotate-270
[18:05:15] ============ [PASSED] drm_test_rect_rotate_inv =============
[18:05:15] ==================== [PASSED] drm_rect =====================
[18:05:15] ============ drm_sysfb_modeset_test (1 subtest) ============
[18:05:15] ============ drm_test_sysfb_build_fourcc_list =============
[18:05:15] [PASSED] no native formats
[18:05:15] [PASSED] XRGB8888 as native format
[18:05:15] [PASSED] remove duplicates
[18:05:15] [PASSED] convert alpha formats
[18:05:15] [PASSED] random formats
[18:05:15] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[18:05:15] ============= [PASSED] drm_sysfb_modeset_test ==============
[18:05:15] ================== drm_fixp (2 subtests) ===================
[18:05:15] [PASSED] drm_test_int2fixp
[18:05:15] [PASSED] drm_test_sm2fixp
[18:05:15] ==================== [PASSED] drm_fixp =====================
[18:05:15] ============================================================
[18:05:15] Testing complete. Ran 637 tests: passed: 637
[18:05:15] Elapsed time: 26.403s total, 1.788s configuring, 24.448s building, 0.147s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[18:05:15] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:05:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:05:27] Starting KUnit Kernel (1/1)...
[18:05:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:05:27] ================= ttm_device (5 subtests) ==================
[18:05:27] [PASSED] ttm_device_init_basic
[18:05:27] [PASSED] ttm_device_init_multiple
[18:05:27] [PASSED] ttm_device_fini_basic
[18:05:27] [PASSED] ttm_device_init_no_vma_man
[18:05:27] ================== ttm_device_init_pools ==================
[18:05:27] [PASSED] No DMA allocations, no DMA32 required
[18:05:27] [PASSED] DMA allocations, DMA32 required
[18:05:27] [PASSED] No DMA allocations, DMA32 required
[18:05:27] [PASSED] DMA allocations, no DMA32 required
[18:05:27] ============== [PASSED] ttm_device_init_pools ==============
[18:05:27] =================== [PASSED] ttm_device ====================
[18:05:27] ================== ttm_pool (8 subtests) ===================
[18:05:27] ================== ttm_pool_alloc_basic ===================
[18:05:27] [PASSED] One page
[18:05:27] [PASSED] More than one page
[18:05:27] [PASSED] Above the allocation limit
[18:05:27] [PASSED] One page, with coherent DMA mappings enabled
[18:05:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[18:05:27] ============== [PASSED] ttm_pool_alloc_basic ===============
[18:05:27] ============== ttm_pool_alloc_basic_dma_addr ==============
[18:05:27] [PASSED] One page
[18:05:27] [PASSED] More than one page
[18:05:27] [PASSED] Above the allocation limit
[18:05:27] [PASSED] One page, with coherent DMA mappings enabled
[18:05:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[18:05:27] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[18:05:27] [PASSED] ttm_pool_alloc_order_caching_match
[18:05:27] [PASSED] ttm_pool_alloc_caching_mismatch
[18:05:27] [PASSED] ttm_pool_alloc_order_mismatch
[18:05:27] [PASSED] ttm_pool_free_dma_alloc
[18:05:27] [PASSED] ttm_pool_free_no_dma_alloc
[18:05:27] [PASSED] ttm_pool_fini_basic
[18:05:27] ==================== [PASSED] ttm_pool =====================
[18:05:27] ================ ttm_resource (8 subtests) =================
[18:05:27] ================= ttm_resource_init_basic =================
[18:05:27] [PASSED] Init resource in TTM_PL_SYSTEM
[18:05:27] [PASSED] Init resource in TTM_PL_VRAM
[18:05:27] [PASSED] Init resource in a private placement
[18:05:27] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[18:05:27] ============= [PASSED] ttm_resource_init_basic =============
[18:05:27] [PASSED] ttm_resource_init_pinned
[18:05:27] [PASSED] ttm_resource_fini_basic
[18:05:27] [PASSED] ttm_resource_manager_init_basic
[18:05:27] [PASSED] ttm_resource_manager_usage_basic
[18:05:27] [PASSED] ttm_resource_manager_set_used_basic
[18:05:27] [PASSED] ttm_sys_man_alloc_basic
[18:05:27] [PASSED] ttm_sys_man_free_basic
[18:05:27] ================== [PASSED] ttm_resource ===================
[18:05:27] =================== ttm_tt (15 subtests) ===================
[18:05:27] ==================== ttm_tt_init_basic ====================
[18:05:27] [PASSED] Page-aligned size
[18:05:27] [PASSED] Extra pages requested
[18:05:27] ================ [PASSED] ttm_tt_init_basic ================
[18:05:27] [PASSED] ttm_tt_init_misaligned
[18:05:27] [PASSED] ttm_tt_fini_basic
[18:05:27] [PASSED] ttm_tt_fini_sg
[18:05:27] [PASSED] ttm_tt_fini_shmem
[18:05:27] [PASSED] ttm_tt_create_basic
[18:05:27] [PASSED] ttm_tt_create_invalid_bo_type
[18:05:27] [PASSED] ttm_tt_create_ttm_exists
[18:05:27] [PASSED] ttm_tt_create_failed
[18:05:27] [PASSED] ttm_tt_destroy_basic
[18:05:27] [PASSED] ttm_tt_populate_null_ttm
[18:05:27] [PASSED] ttm_tt_populate_populated_ttm
[18:05:27] [PASSED] ttm_tt_unpopulate_basic
[18:05:27] [PASSED] ttm_tt_unpopulate_empty_ttm
[18:05:27] [PASSED] ttm_tt_swapin_basic
[18:05:27] ===================== [PASSED] ttm_tt ======================
[18:05:27] =================== ttm_bo (14 subtests) ===================
[18:05:27] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[18:05:27] [PASSED] Cannot be interrupted and sleeps
[18:05:27] [PASSED] Cannot be interrupted, locks straight away
[18:05:27] [PASSED] Can be interrupted, sleeps
[18:05:27] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[18:05:27] [PASSED] ttm_bo_reserve_locked_no_sleep
[18:05:27] [PASSED] ttm_bo_reserve_no_wait_ticket
[18:05:27] [PASSED] ttm_bo_reserve_double_resv
[18:05:27] [PASSED] ttm_bo_reserve_interrupted
[18:05:27] [PASSED] ttm_bo_reserve_deadlock
[18:05:27] [PASSED] ttm_bo_unreserve_basic
[18:05:27] [PASSED] ttm_bo_unreserve_pinned
[18:05:27] [PASSED] ttm_bo_unreserve_bulk
[18:05:27] [PASSED] ttm_bo_fini_basic
[18:05:27] [PASSED] ttm_bo_fini_shared_resv
[18:05:27] [PASSED] ttm_bo_pin_basic
[18:05:27] [PASSED] ttm_bo_pin_unpin_resource
[18:05:27] [PASSED] ttm_bo_multiple_pin_one_unpin
[18:05:27] ===================== [PASSED] ttm_bo ======================
[18:05:27] ============== ttm_bo_validate (22 subtests) ===============
[18:05:27] ============== ttm_bo_init_reserved_sys_man ===============
[18:05:27] [PASSED] Buffer object for userspace
[18:05:27] [PASSED] Kernel buffer object
[18:05:27] [PASSED] Shared buffer object
[18:05:27] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[18:05:27] ============== ttm_bo_init_reserved_mock_man ==============
[18:05:27] [PASSED] Buffer object for userspace
[18:05:27] [PASSED] Kernel buffer object
[18:05:27] [PASSED] Shared buffer object
[18:05:27] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[18:05:27] [PASSED] ttm_bo_init_reserved_resv
[18:05:27] ================== ttm_bo_validate_basic ==================
[18:05:27] [PASSED] Buffer object for userspace
[18:05:27] [PASSED] Kernel buffer object
[18:05:27] [PASSED] Shared buffer object
[18:05:27] ============== [PASSED] ttm_bo_validate_basic ==============
[18:05:27] [PASSED] ttm_bo_validate_invalid_placement
[18:05:27] ============= ttm_bo_validate_same_placement ==============
[18:05:27] [PASSED] System manager
[18:05:27] [PASSED] VRAM manager
[18:05:27] ========= [PASSED] ttm_bo_validate_same_placement ==========
[18:05:27] [PASSED] ttm_bo_validate_failed_alloc
[18:05:27] [PASSED] ttm_bo_validate_pinned
[18:05:27] [PASSED] ttm_bo_validate_busy_placement
[18:05:27] ================ ttm_bo_validate_multihop =================
[18:05:27] [PASSED] Buffer object for userspace
[18:05:27] [PASSED] Kernel buffer object
[18:05:27] [PASSED] Shared buffer object
[18:05:27] ============ [PASSED] ttm_bo_validate_multihop =============
[18:05:27] ========== ttm_bo_validate_no_placement_signaled ==========
[18:05:27] [PASSED] Buffer object in system domain, no page vector
[18:05:27] [PASSED] Buffer object in system domain with an existing page vector
[18:05:27] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[18:05:27] ======== ttm_bo_validate_no_placement_not_signaled ========
[18:05:27] [PASSED] Buffer object for userspace
[18:05:27] [PASSED] Kernel buffer object
[18:05:27] [PASSED] Shared buffer object
[18:05:27] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[18:05:27] [PASSED] ttm_bo_validate_move_fence_signaled
[18:05:27] ========= ttm_bo_validate_move_fence_not_signaled =========
[18:05:27] [PASSED] Waits for GPU
[18:05:27] [PASSED] Tries to lock straight away
[18:05:27] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[18:05:27] [PASSED] ttm_bo_validate_swapout
[18:05:27] [PASSED] ttm_bo_validate_happy_evict
[18:05:27] [PASSED] ttm_bo_validate_all_pinned_evict
[18:05:27] [PASSED] ttm_bo_validate_allowed_only_evict
[18:05:27] [PASSED] ttm_bo_validate_deleted_evict
[18:05:27] [PASSED] ttm_bo_validate_busy_domain_evict
[18:05:27] [PASSED] ttm_bo_validate_evict_gutting
[18:05:27] [PASSED] ttm_bo_validate_recrusive_evict
[18:05:27] ================= [PASSED] ttm_bo_validate =================
[18:05:27] ============================================================
[18:05:27] Testing complete. Ran 102 tests: passed: 102
[18:05:27] Elapsed time: 11.745s total, 1.759s configuring, 9.771s building, 0.179s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/3] drm/i915/ddi: add helper to compute DDI clock frequency
2026-08-11 17:58 ` [PATCH v2 1/3] drm/i915/ddi: add helper to compute DDI clock frequency Suraj Kandpal
@ 2026-08-12 3:43 ` Nautiyal, Ankit K
0 siblings, 0 replies; 12+ messages in thread
From: Nautiyal, Ankit K @ 2026-08-12 3:43 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
On 8/11/2026 11:28 PM, Suraj Kandpal wrote:
> Add intel_ddi_link_symbol_clock() to return the DDI clock frequency for
> a given port clock:
> DP 8b/10b : rate
> DP 128b/132b (UHBR) : (10 / 32) * rate
> HDMI FRL : (10 / 18) * rate
> HDMI TMDS : rate
>
> The DP case reuses intel_dp_link_symbol_clock().
> This will help in upcoming commits to decide value to be written
> in DDI_CLK_VALFREQ.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> v1 -> v2
> -Update commit message with correct formula (Jani)
>
> drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++++++++
> drivers/gpu/drm/i915/display/intel_ddi.h | 1 +
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bf5788c5bbd3..dd9064592ec9 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1529,6 +1529,17 @@ int intel_ddi_level(struct intel_encoder *encoder,
> return level;
> }
>
> +int intel_ddi_link_symbol_clock(struct intel_encoder *encoder, int clock)
> +{
> + if (intel_encoder_is_dp(encoder))
> + return intel_dp_link_symbol_clock(clock);
> +
> + if (intel_hdmi_is_frl(clock))
> + return DIV_ROUND_CLOSEST(clock * 10, 18);
> +
> + return clock;
> +}
> +
> static void
> hsw_set_signal_levels(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
> index 580ecb09b8b6..239d5a403f91 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -81,6 +81,7 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
> int intel_ddi_level(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> int lane);
> +int intel_ddi_link_symbol_clock(struct intel_encoder *encoder, int clock);
> void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> struct intel_crtc *crtc);
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ with DDI clock frequency
2026-08-11 17:58 ` [PATCH v2 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ with " Suraj Kandpal
@ 2026-08-12 3:49 ` Nautiyal, Ankit K
2026-08-12 4:24 ` Kandpal, Suraj
0 siblings, 1 reply; 12+ messages in thread
From: Nautiyal, Ankit K @ 2026-08-12 3:49 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
On 8/11/2026 11:28 PM, Suraj Kandpal wrote:
> DDI_CLK_VALFREQ is programmed with the port clock, which for DP is the
> symbol clock computed assuming 8b/10b encoding (link_rate / 10). For
> DP 128b/132b (UHBR) rates and for HDMI FRL the port clock needs to
> be modfied.
> On silicon DDI_CLK_VALFREQ is a scratch register with no
> functional impact, so the bug is not observed.
> Use intel_ddi_link_symbol_clock() to write the correct DDI clock in
> kHz.
Perhaps can be re-phrased as :
DDI_CLK_VALFREQ does not configure hardware, it only records the
frequency software intends to set, so there is no functional impact.
Patch LGTM.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> Fixes: 51390cc0e00a ("drm/i915/mtl: Add Support for C10 PHY message bus and pll programming")
> Fixes: 73fc3abcb797 ("drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll")
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 452062417ce9..dbebd7210848 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3233,7 +3233,8 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
> * 8. Program DDI_CLK_VALFREQ to match intended DDI
> * clock frequency.
> */
> - intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
> + intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> + intel_ddi_link_symbol_clock(encoder, port_clock));
>
> /*
> * 9. Set PORT_CLOCK_CTL register PCLK PLL Request
> @@ -3406,7 +3407,7 @@ void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder, int port_cloc
> * clock frequency.
> */
> intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> - port_clock);
> + intel_ddi_link_symbol_clock(encoder, port_clock));
> }
>
> void intel_mtl_pll_enable(struct intel_encoder *encoder,
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/3] drm/i915/lt_phy: program DDI_CLK_VALFREQ with DDI clock frequency
2026-08-11 17:58 ` [PATCH v2 3/3] drm/i915/lt_phy: " Suraj Kandpal
@ 2026-08-12 3:50 ` Nautiyal, Ankit K
2026-08-12 17:26 ` Rodrigo Vivi
0 siblings, 1 reply; 12+ messages in thread
From: Nautiyal, Ankit K @ 2026-08-12 3:50 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
On 8/11/2026 11:28 PM, Suraj Kandpal wrote:
> DDI_CLK_VALFREQ is programmed with the port clock, which for DP is the
> symbol clock computed assuming 8b/10b encoding (link_rate / 10). For
> DP 128b/132b (UHBR) rates and for HDMI FRL the port clock needs to
> be modified.
> On silicon DDI_CLK_VALFREQ is a scratch register with no
> functional impact, so the bug is not observed.
> Use intel_ddi_link_symbol_clock() to write the correct DDI clock in
> kHz
>
> Fixes: 5ec58d714935 ("drm/i915/lt_phy: Add .enable_clock hook on DDI")
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 8fc6d230493f..86492651b01d 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1976,7 +1976,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> * Change. We handle this step in bxt_set_cdclk().
> */
> /* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
> - intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
> + intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> + intel_ddi_link_symbol_clock(encoder, port_clock));
>
> /* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
> intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> @@ -2023,7 +2024,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> lane_phy_pulse_status,
> lane_phy_pulse_status);
> } else {
> - intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
> + intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> + intel_ddi_link_symbol_clock(encoder, port_clock));
> }
>
> /*
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v2 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ with DDI clock frequency
2026-08-12 3:49 ` Nautiyal, Ankit K
@ 2026-08-12 4:24 ` Kandpal, Suraj
2026-08-12 9:03 ` Jani Nikula
0 siblings, 1 reply; 12+ messages in thread
From: Kandpal, Suraj @ 2026-08-12 4:24 UTC (permalink / raw)
To: Nautiyal, Ankit K, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v2 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ with DDI
> clock frequency
>
>
> On 8/11/2026 11:28 PM, Suraj Kandpal wrote:
> > DDI_CLK_VALFREQ is programmed with the port clock, which for DP is the
> > symbol clock computed assuming 8b/10b encoding (link_rate / 10). For
> > DP 128b/132b (UHBR) rates and for HDMI FRL the port clock needs to be
> > modfied.
> > On silicon DDI_CLK_VALFREQ is a scratch register with no functional
> > impact, so the bug is not observed.
> > Use intel_ddi_link_symbol_clock() to write the correct DDI clock in
> > kHz.
>
> Perhaps can be re-phrased as :
>
> DDI_CLK_VALFREQ does not configure hardware, it only records the frequency
> software intends to set, so there is no functional impact.
>
> Patch LGTM.
>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Thanks for the review
Pushed to din with above mentioned changes in commit message
Regards,
Suraj Kandpal
>
>
> >
> > Fixes: 51390cc0e00a ("drm/i915/mtl: Add Support for C10 PHY message
> > bus and pll programming")
> > Fixes: 73fc3abcb797 ("drm/i915/mtl: Enabling/disabling sequence
> > Thunderbolt pll")
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index 452062417ce9..dbebd7210848 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -3233,7 +3233,8 @@ static void intel_cx0pll_enable(struct intel_encoder
> *encoder,
> > * 8. Program DDI_CLK_VALFREQ to match intended DDI
> > * clock frequency.
> > */
> > - intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
> > + intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> > + intel_ddi_link_symbol_clock(encoder, port_clock));
> >
> > /*
> > * 9. Set PORT_CLOCK_CTL register PCLK PLL Request @@ -3406,7
> > +3407,7 @@ void intel_mtl_tbt_pll_enable_clock(struct intel_encoder
> *encoder, int port_cloc
> > * clock frequency.
> > */
> > intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> > - port_clock);
> > + intel_ddi_link_symbol_clock(encoder, port_clock));
> > }
> >
> > void intel_mtl_pll_enable(struct intel_encoder *encoder,
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v2 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ with DDI clock frequency
2026-08-12 4:24 ` Kandpal, Suraj
@ 2026-08-12 9:03 ` Jani Nikula
2026-08-12 9:11 ` Kandpal, Suraj
0 siblings, 1 reply; 12+ messages in thread
From: Jani Nikula @ 2026-08-12 9:03 UTC (permalink / raw)
To: Kandpal, Suraj, Nautiyal, Ankit K, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
On Wed, 12 Aug 2026, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> Subject: Re: [PATCH v2 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ with DDI
>> clock frequency
>>
>>
>> On 8/11/2026 11:28 PM, Suraj Kandpal wrote:
>> > DDI_CLK_VALFREQ is programmed with the port clock, which for DP is the
>> > symbol clock computed assuming 8b/10b encoding (link_rate / 10). For
>> > DP 128b/132b (UHBR) rates and for HDMI FRL the port clock needs to be
>> > modfied.
>> > On silicon DDI_CLK_VALFREQ is a scratch register with no functional
>> > impact, so the bug is not observed.
>> > Use intel_ddi_link_symbol_clock() to write the correct DDI clock in
>> > kHz.
>>
>> Perhaps can be re-phrased as :
>>
>> DDI_CLK_VALFREQ does not configure hardware, it only records the frequency
>> software intends to set, so there is no functional impact.
>>
>> Patch LGTM.
>>
>> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> Thanks for the review
>
> Pushed to din with above mentioned changes in commit message
Process nitpick #1. This series was pushed before there were xe CI
results AFAICS.
I understand the series is the same as v1, with just the commit message
changed. But that's process nitpick #2. Please don't send a v2 to just
change the commit message, on the same day, with no other review
comments in yet. Wait out for the review comments, and if the only thing
that needs changing in the end is the commit message, you don't have to
resend anything at all. Just fix the commit message and push. Ask in the
review thread if you're unsure about the wording.
In this case, going slower would've gone faster, and saved a full v2 CI
round on dozens of machines, just for a commit message wording change.
BR,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v2 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ with DDI clock frequency
2026-08-12 9:03 ` Jani Nikula
@ 2026-08-12 9:11 ` Kandpal, Suraj
0 siblings, 0 replies; 12+ messages in thread
From: Kandpal, Suraj @ 2026-08-12 9:11 UTC (permalink / raw)
To: Jani Nikula, Nautiyal, Ankit K, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
> Subject: RE: [PATCH v2 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ with DDI
> clock frequency
>
> On Wed, 12 Aug 2026, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> >> Subject: Re: [PATCH v2 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ
> >> with DDI clock frequency
> >>
> >>
> >> On 8/11/2026 11:28 PM, Suraj Kandpal wrote:
> >> > DDI_CLK_VALFREQ is programmed with the port clock, which for DP is
> >> > the symbol clock computed assuming 8b/10b encoding (link_rate /
> >> > 10). For DP 128b/132b (UHBR) rates and for HDMI FRL the port clock
> >> > needs to be modfied.
> >> > On silicon DDI_CLK_VALFREQ is a scratch register with no functional
> >> > impact, so the bug is not observed.
> >> > Use intel_ddi_link_symbol_clock() to write the correct DDI clock in
> >> > kHz.
> >>
> >> Perhaps can be re-phrased as :
> >>
> >> DDI_CLK_VALFREQ does not configure hardware, it only records the
> >> frequency software intends to set, so there is no functional impact.
> >>
> >> Patch LGTM.
> >>
> >> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >
> > Thanks for the review
> >
> > Pushed to din with above mentioned changes in commit message
>
> Process nitpick #1. This series was pushed before there were xe CI results
> AFAICS.
>
> I understand the series is the same as v1, with just the commit message
> changed. But that's process nitpick #2. Please don't send a v2 to just change the
> commit message, on the same day, with no other review comments in yet. Wait
> out for the review comments, and if the only thing that needs changing in the
> end is the commit message, you don't have to resend anything at all. Just fix
> the commit message and push. Ask in the review thread if you're unsure about
> the wording.
>
> In this case, going slower would've gone faster, and saved a full v2 CI round on
> dozens of machines, just for a commit message wording change.
>
Sure Jani will keep it in mind going forward
Regards,
Suraj Kandpal
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/3] drm/i915/lt_phy: program DDI_CLK_VALFREQ with DDI clock frequency
2026-08-12 3:50 ` Nautiyal, Ankit K
@ 2026-08-12 17:26 ` Rodrigo Vivi
0 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2026-08-12 17:26 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: Suraj Kandpal, intel-xe, intel-gfx
On Wed, Aug 12, 2026 at 09:20:12AM +0530, Nautiyal, Ankit K wrote:
>
> On 8/11/2026 11:28 PM, Suraj Kandpal wrote:
> > DDI_CLK_VALFREQ is programmed with the port clock, which for DP is the
> > symbol clock computed assuming 8b/10b encoding (link_rate / 10). For
> > DP 128b/132b (UHBR) rates and for HDMI FRL the port clock needs to
> > be modified.
> > On silicon DDI_CLK_VALFREQ is a scratch register with no
> > functional impact, so the bug is not observed.
> > Use intel_ddi_link_symbol_clock() to write the correct DDI clock in
> > kHz
> >
> > Fixes: 5ec58d714935 ("drm/i915/lt_phy: Add .enable_clock hook on DDI")
Next time, please be mindful about the -fixes, stable, and customer trees
and keep new helper in the same patch as the fixes.
Thanks,
Rodrigo.
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
>
> > ---
> > drivers/gpu/drm/i915/display/intel_lt_phy.c | 6 ++++--
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index 8fc6d230493f..86492651b01d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -1976,7 +1976,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> > * Change. We handle this step in bxt_set_cdclk().
> > */
> > /* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
> > - intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
> > + intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> > + intel_ddi_link_symbol_clock(encoder, port_clock));
> > /* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
> > intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> > @@ -2023,7 +2024,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> > lane_phy_pulse_status,
> > lane_phy_pulse_status);
> > } else {
> > - intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
> > + intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> > + intel_ddi_link_symbol_clock(encoder, port_clock));
> > }
> > /*
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2026-08-12 17:26 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-11 17:58 [PATCH v2 0/3] Fix value being written to DDI_CLK_VALFREQ Suraj Kandpal
2026-08-11 17:58 ` [PATCH v2 1/3] drm/i915/ddi: add helper to compute DDI clock frequency Suraj Kandpal
2026-08-12 3:43 ` Nautiyal, Ankit K
2026-08-11 17:58 ` [PATCH v2 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ with " Suraj Kandpal
2026-08-12 3:49 ` Nautiyal, Ankit K
2026-08-12 4:24 ` Kandpal, Suraj
2026-08-12 9:03 ` Jani Nikula
2026-08-12 9:11 ` Kandpal, Suraj
2026-08-11 17:58 ` [PATCH v2 3/3] drm/i915/lt_phy: " Suraj Kandpal
2026-08-12 3:50 ` Nautiyal, Ankit K
2026-08-12 17:26 ` Rodrigo Vivi
2026-08-11 18:05 ` ✓ CI.KUnit: success for Fix value being written to DDI_CLK_VALFREQ (rev2) Patchwork
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