From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Karthik Poosa <karthik.poosa@intel.com>
Cc: <intel-xe@lists.freedesktop.org>, <anshuman.gupta@intel.com>,
<badal.nilawar@intel.com>, <raag.jadav@intel.com>,
<riana.tauro@intel.com>, <sk.anirban@intel.com>,
<mallesh.koujalagi@intel.com>, <soham.purkait@intel.com>
Subject: Re: [PATCH v6 07/13] drm/xe/hwmon: Consolidate temperature sensor availability checks
Date: Mon, 28 Sep 2026 15:39:48 -0400 [thread overview]
Message-ID: <arrChCQJcyRAfpMS@intel.com> (raw)
In-Reply-To: <20260924205429.2846256-8-karthik.poosa@intel.com>
On Fri, Sep 25, 2026 at 02:24:23AM +0530, Karthik Poosa wrote:
> Replace is_vram_ch_available() with a generalized is_temp_available()
> that validates PKG, VRAM, per-channel VRAM, memory controller and PCIe
> sensors using the new validity helpers. Rename the existing callers to
> the new helper.
>
> Use is_temp_available() from xe_hwmon_temp_is_visible() so attributes for
> sensors that are not present are not exposed during hwmon registration.
>
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> Assisted-by: LLM
> ---
> drivers/gpu/drm/xe/xe_hwmon.c | 64 ++++++++++++++++++++++-------------
> 1 file changed, 40 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 4a7cf913e6c8..052b25a233d6 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -1002,19 +1002,39 @@ static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *valu
> *value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);
> }
>
> -static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
> +static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
> {
> struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
> - int vram_id = channel - CHANNEL_VRAM_N;
> - struct xe_reg vram_reg;
> + struct xe_reg reg;
> + u32 reg_val;
>
> - vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> - if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
> - return false;
> + switch (channel) {
> + case CHANNEL_PKG:
> + case CHANNEL_VRAM:
> + case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> + reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> + if (!xe_reg_is_valid(reg))
> + return false;
> +
> + reg_val = xe_mmio_read32(mmio, reg);
> + if (!mmio_temp_valid(hwmon, reg_val)) {
> + drm_dbg(&hwmon->xe->drm,
> + "channel %d temperature unavailable, val 0x%x\n", channel, reg_val);
> + return false;
> + }
> +
> + if (channel >= CHANNEL_VRAM_N)
> + sprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N],
> + "vram_ch_%d", channel - CHANNEL_VRAM_N);
>
> - /* Create label only for available vram channel */
> - sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
> - return true;
> + return true;
> + case CHANNEL_MCTRL:
> + return hwmon->temp.count && !get_mc_temp(hwmon, NULL);
> + case CHANNEL_PCIE:
> + return hwmon->temp.count && !get_pcie_temp(hwmon, NULL);
> + default:
> + return false;
> + }
> }
>
> static umode_t
> @@ -1024,14 +1044,13 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
> case hwmon_temp_emergency:
> switch (channel) {
> case CHANNEL_PKG:
> - return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0;
> - case CHANNEL_VRAM:
> - return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
> case CHANNEL_MCTRL:
> case CHANNEL_PCIE:
> - return hwmon->temp.count ? 0444 : 0;
> + return (is_temp_available(hwmon, channel) &&
> + hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN]) ? 0444 : 0;
> + case CHANNEL_VRAM:
> case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> - return (is_vram_ch_available(hwmon, channel) &&
> + return (is_temp_available(hwmon, channel) &&
> hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0;
> default:
> return 0;
> @@ -1039,14 +1058,13 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
> case hwmon_temp_crit:
> switch (channel) {
> case CHANNEL_PKG:
> - return hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] ? 0444 : 0;
> - case CHANNEL_VRAM:
> - return hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT] ? 0444 : 0;
> case CHANNEL_MCTRL:
> case CHANNEL_PCIE:
> - return hwmon->temp.count ? 0444 : 0;
> + return (is_temp_available(hwmon, channel) &&
> + hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT]) ? 0444 : 0;
> + case CHANNEL_VRAM:
> case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> - return (is_vram_ch_available(hwmon, channel) &&
> + return (is_temp_available(hwmon, channel) &&
> hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0;
> default:
> return 0;
> @@ -1054,7 +1072,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
> case hwmon_temp_max:
> switch (channel) {
> case CHANNEL_PKG:
> - return hwmon->temp.limit[TEMP_LIMIT_PKG_MAX] ? 0444 : 0;
> + return (is_temp_available(hwmon, channel) &&
> + hwmon->temp.limit[TEMP_LIMIT_PKG_MAX]) ? 0444 : 0;
> default:
> return 0;
> }
> @@ -1063,13 +1082,10 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
> switch (channel) {
> case CHANNEL_PKG:
> case CHANNEL_VRAM:
> - return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
> - channel)) ? 0444 : 0;
> case CHANNEL_MCTRL:
> case CHANNEL_PCIE:
> - return hwmon->temp.count ? 0444 : 0;
> case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> - return is_vram_ch_available(hwmon, channel) ? 0444 : 0;
> + return is_temp_available(hwmon, channel) ? 0444 : 0;
now, if temp = 0 at probe, then it won't appear. What made me to question
patch 4 again...
But other then this, this patch looks correct:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> default:
> return 0;
> }
> --
> 2.25.1
>
next prev parent reply other threads:[~2026-09-28 19:40 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
2026-09-24 20:54 ` [PATCH v6 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit Karthik Poosa
2026-09-28 0:11 ` Rodrigo Vivi
2026-09-28 15:32 ` Poosa, Karthik
2026-09-24 20:54 ` [PATCH v6 02/13] drm/xe/hwmon: Decode mailbox temperature as sign-magnitude Karthik Poosa
2026-09-28 0:15 ` Rodrigo Vivi
2026-09-24 20:54 ` [PATCH v6 03/13] drm/xe/hwmon: Fix memory controller thermal data handling Karthik Poosa
2026-09-24 20:54 ` [PATCH v6 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings Karthik Poosa
2026-09-28 0:19 ` Rodrigo Vivi
2026-09-28 16:08 ` Poosa, Karthik
2026-09-28 17:59 ` Rodrigo Vivi
2026-09-28 19:38 ` Rodrigo Vivi
2026-09-29 16:48 ` Poosa, Karthik
2026-09-29 18:26 ` Rodrigo Vivi
2026-09-24 20:54 ` [PATCH v6 05/13] drm/xe/hwmon: Handle unavailable memory controller sensors Karthik Poosa
2026-09-28 16:08 ` Rodrigo Vivi
2026-09-24 20:54 ` [PATCH v6 06/13] drm/xe/hwmon: Detect unavailable PCIe thermal sensors Karthik Poosa
2026-09-28 16:10 ` Rodrigo Vivi
2026-09-24 20:54 ` [PATCH v6 07/13] drm/xe/hwmon: Consolidate temperature sensor availability checks Karthik Poosa
2026-09-28 19:39 ` Rodrigo Vivi [this message]
2026-09-24 20:54 ` [PATCH v6 08/13] drm/xe/hwmon: Cache temperature availability to reduce probe time Karthik Poosa
2026-09-28 21:17 ` Rodrigo Vivi
2026-09-24 20:54 ` [PATCH v6 09/13] drm/xe/hwmon: use CRI-specific package and VRAM temperature registers Karthik Poosa
2026-09-24 20:54 ` [PATCH v6 10/13] drm/xe/hwmon: Add platform-aware VRAM thermal channel support Karthik Poosa
2026-09-29 18:04 ` Rodrigo Vivi
2026-10-01 19:02 ` Poosa, Karthik
2026-09-24 20:54 ` [PATCH v6 11/13] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754 Karthik Poosa
2026-09-29 18:24 ` Rodrigo Vivi
2026-09-24 20:54 ` [PATCH v6 12/13] drm/xe/hwmon: Update memory controller temperature offset for CRI Karthik Poosa
2026-09-29 18:27 ` Rodrigo Vivi
2026-09-24 20:54 ` [PATCH v6 13/13] drm/xe/hwmon: Update PCIE temperature sensor " Karthik Poosa
2026-09-29 18:29 ` Rodrigo Vivi
2026-09-30 17:11 ` Poosa, Karthik
2026-09-24 21:05 ` ✓ CI.KUnit: success for drm/xe/hwmon: Update hwmon thermal mailbox (rev3) Patchwork
2026-09-24 22:34 ` ✓ Xe.CI.BAT: " Patchwork
2026-09-25 11:16 ` ✗ Xe.CI.FULL: failure " Patchwork
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