Re: [PATCH v13 15/16] drm/xe: Validate thermal sensor count before reads

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Wed, Oct 14, 2026 at 05:28:05PM +0530, Karthik Poosa wrote:
> Check that READ_THERMAL_CONFIG reports enough thermal entries for the
> platform-specific MCTRL range and PCIe sensor index before reading
> READ_THERMAL_DATA.
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> ---
> 
> v2:
> - Cap the memory controller sensor range at the PCIe sensor index so the
>   PCIe temperature is not averaged into the memory controller temperature.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
>  drivers/gpu/drm/xe/xe_hwmon.c | 44 ++++++++++++++++++++++++-----------
>  1 file changed, 30 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 4249faf9fb39..4b9c18230ade 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -920,6 +920,17 @@ static int mbx_temp_decode(u8 value)
>  	return (value & TEMP_MBX_SIGN) ? -temp : temp;
>  }
>  
> +static u8 xe_hwmon_pcie_temp_index(const struct xe_hwmon *hwmon)
> +{
> +	if (hwmon->xe->info.platform == XE_CRESCENTISLAND)
> +		return CRI_TEMP_INDEX_PCIE;
> +
> +	if (hwmon->xe->info.subplatform == XE_SUBPLATFORM_BATTLEMAGE_G21)
> +		return BMG_G21_TEMP_INDEX_PCIE;
> +
> +	return TEMP_INDEX_PCIE;
> +}
> +
>  static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  {
>  	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
> @@ -935,7 +946,14 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  		end = CRI_TEMP_INDEX_MCTRL + CRI_TEMP_MCTRL_COUNT;
>  	} else {
>  		start = TEMP_INDEX_MCTRL;
> -		end = hwmon->temp.count - 1;
> +		end = min_t(int, hwmon->temp.count - 1, xe_hwmon_pcie_temp_index(hwmon));
> +	}
> +
> +	if (end <= start || end > hwmon->temp.count) {
> +		drm_warn(&hwmon->xe->drm,
> +			 "memory controller range [%d, %d) is invalid for temperature count %d\n",
> +			 start, end, hwmon->temp.count);
> +		return -ENODATA;
>  	}
>  
>  	for (i = start / sizeof(u32); i < DIV_ROUND_UP(end, sizeof(u32)); i++) {
> @@ -967,30 +985,28 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  	return 0;
>  }
>  
> -static u8 xe_hwmon_pcie_temp_index(const struct xe_hwmon *hwmon)
> -{
> -	if (hwmon->xe->info.platform == XE_CRESCENTISLAND)
> -		return CRI_TEMP_INDEX_PCIE;
> -
> -	if (hwmon->xe->info.subplatform == XE_SUBPLATFORM_BATTLEMAGE_G21)
> -		return BMG_G21_TEMP_INDEX_PCIE;
> -
> -	return TEMP_INDEX_PCIE;
> -}
> -
>  static int get_pcie_temp(const struct xe_hwmon *hwmon, long *val)
>  {
>  	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>  	u32 data = 0;
> +	int index;
>  	int ret;
>  
> +	index = xe_hwmon_pcie_temp_index(hwmon);
> +	if (index >= hwmon->temp.count) {
> +		drm_warn(&hwmon->xe->drm,
> +			 "PCIe temperature index %d out of range for temperature count %d\n",
> +			 index, hwmon->temp.count);
> +		return -ENODATA;
> +	}
> +
>  	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA,
> -						  xe_hwmon_pcie_temp_index(hwmon) / sizeof(data)),
> +						  index / sizeof(data)),
>  						  &data, NULL);
>  	if (ret)
>  		return ret;
>  
> -	data >>= (xe_hwmon_pcie_temp_index(hwmon) % sizeof(data)) * BITS_PER_BYTE;
> +	data >>= (index % sizeof(data)) * BITS_PER_BYTE;
>  	data = REG_FIELD_GET(TEMP_MASK, data);
>  	if (!mbx_temp_valid(hwmon, data)) {
>  		drm_dbg(&hwmon->xe->drm, "PCIe temperature not available\n");
> -- 
> 2.25.1
>