Re: [Intel-xe] [RFC 0/5] PAT and cache coherency support

["Souza, Jose" <jose.souza@intel.com>]

On Tue, 2023-08-29 at 17:28 +0100, Matthew Auld wrote:
> Series still needs bunch of testing, but sending as RFC to get early feedback
> while the IGT bits are being worked on. Note that the series also directly
> depends on the WIP series here: https://patchwork.freedesktop.org/series/122708/

Left some comments in the patches but can't start experimenting because https://patchwork.freedesktop.org/series/122708/ breaks driver load.
xe_pte_encode() calls __pte_encode() with a NULL vma.

> 
> Goal here is to allow userspace to directly control the pat_index when mapping
> memory via the ppGTT, in addtion to the CPU caching mode for system memory. This
> is very much needed on newer igpu platforms which allow incoherent GT access,
> where the choice over the cache level and expected coherency is best left to
> userspace depending on their usecase.  In the future there may also be other
> stuff encoded in the pat_index, so giving userspace direct control will also be
> needed there.
> 
> To support this we added new gem_create uAPI for selecting the CPU cache
> mode to use for system memory, including the expected GPU coherency mode. There
> are various restrictions here for the selected coherency mode and compatible CPU
> cache modes.  With that in place the actual pat_index can now be provided as
> part of vm_bind. The only restriction is that the coherency mode of the
> pat_index must match the gem_create coherency mode. There are also some special
> cases like with userptr and dma-buf.
>