* [PATCH v3 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO
@ 2026-07-22 5:34 Jia Yao
2026-07-22 5:34 ` [PATCH v3 1/1] " Jia Yao
` (5 more replies)
0 siblings, 6 replies; 17+ messages in thread
From: Jia Yao @ 2026-07-22 5:34 UTC (permalink / raw)
To: intel-xe; +Cc: Jia Yao
== Problem ==
On platforms with Unified Shared Memory (USM), the xe driver maintains
three hardware page-fault queues (PAGE_FAULT, PAGE_FAULT_RESPONSE,
ACCESS_COUNTER) inside the GuC Additional Data Structures (ADS) blob.
The ADS blob is mapped WB on the CPU side.
xe_guc_ads_populate() is called on every GT reset to reprogram the ADS
blob; it begins with a full memset() of the blob to zero. The zeroed
cache lines for the UM queue region reside in the CPU cache (LLC, WB)
but are not immediately written back to DRAM.
GAM hardware writes fault descriptors to the queue via DPA - a
non-coherent path that bypasses the CPU cache and writes directly to
memory. GuC reads the queue via GGTT (WB), which hits the CPU cache.
As a result GuC sees the stale zeroed data from the CPU cache instead
of the descriptor written to DRAM by GAM. The driver then receives an
all-zero fault descriptor and returns -EINVAL, causing an unnecessary
engine reset.
This is documented in HSD as:
"When Fault queue is updated by the SW (Buffer zeroed), it can reside
in the CPU cache (L4:WB). A non coherent write from GAM HW would not
consult the CPU cache and it will eventually get written into the
memory (depends upon eviction/flushes) and CPU cache has stale data.
When GUC HW reads the fault queue it gets it from the CPU cache,
which is stale data."
The window is narrow but reliably reproducible: run xe_exec_reset
--run-subtest gt-reset followed immediately by
xe_exec_system_allocator --run-subtest
threads-many-execqueues-mmap-new-race.
== Reproduction ==
# Requires a platform with has_usm (e.g. Xe3 iGFX)
sudo xe_exec_reset --run-subtest gt-reset
sudo xe_exec_system_allocator --run-subtest threads-many-execqueues-mmap-new-race
Symptom in dmesg:
[xe] ASID: 0, Faulted Address: 0x0000000000000000, FaultType: 0
The all-zero fault descriptor is the tell-tale sign of the stale
cache line race.
== Fix ==
Allocate the UM queues in a dedicated UC BO (ads->um_queue_bo). UC
mapping on the CPU side ensures the memset bypasses the cache and the
zeroed data lands in DRAM immediately. GuC's non-coherent read then
goes to DRAM and sees the correct descriptor written by GAM.
A separate BO also eliminates the secondary race where a descriptor
written by the GPU between GDRST and GuC restart could be zeroed by the
next call to xe_guc_ads_populate().
On dGFX, VRAM placement is used so the DPA is derived from
vram_region_gpu_offset, avoiding the IOVA aliasing issue seen on
platforms with limited DRAM (e.g. BMG 4 GB) where a SYSTEM BO's DMA
address can alias a PCI MMIO reserved window.
Why not just flush the cache after memset?
An earlier approach called drm_clflush_virt_range() on the UM queue
region immediately after the memset to evict the stale zero lines from
LLC. This reduces the failure rate significantly but does not fully
eliminate the race for two reasons.
First, the Linux kernel maintains a WB direct mapping (linear map) that
covers all physical memory. Even after flushing the vmap alias, the
CPU can speculatively prefetch the same physical page through the WB
direct-map alias, silently repopulating the cache with zeros. LNL is
known to be particularly susceptible to this speculative prefetch
behaviour. XE_BO_FLAG_NEEDS_UC calls set_memory_uc() which updates
both the vmap PTE and the direct-map PTE to UC, closing this aliasing
window entirely.
Second, the flush approach leaves the memory mapped WB on the CPU side
permanently. Any future SW access - a debug read, a tracing hook, an
inadvertent touch - can re-dirty the cache line and reintroduce the
race. UC mapping makes the correct behaviour unconditional and
self-documenting.
Jia Yao (1):
drm/xe/guc_ads: allocate UM queues in a separate UC BO
drivers/gpu/drm/xe/xe_guc_ads.c | 64 ++++++++++++++++-----------
drivers/gpu/drm/xe/xe_guc_ads_types.h | 8 +++-
2 files changed, 46 insertions(+), 26 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 1/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO
2026-07-22 5:34 [PATCH v3 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO Jia Yao
@ 2026-07-22 5:34 ` Jia Yao
2026-07-22 9:18 ` Matthew Auld
2026-07-22 23:00 ` Gwan-gyeong Mun
2026-07-22 5:41 ` ✗ CI.checkpatch: warning for " Patchwork
` (4 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: Jia Yao @ 2026-07-22 5:34 UTC (permalink / raw)
To: intel-xe; +Cc: Jia Yao, Gwan-gyeong Mun, Matthew Auld, stable
The HW unit that writes to the UM fault queue is not always coherent
with the CPU cache. Ensure the UM queue memory is uncached on the CPU
side so that GuC always reads descriptors from memory rather than a
stale CPU cache line.
Allocate the UM queues in a dedicated UC BO (ads->um_queue_bo) instead
of the main ADS blob. This also prevents xe_guc_ads_populate()'s
memset from zeroing any fault descriptor written between GDRST and GuC
restart. On dGFX, VRAM placement gives a well-defined DPA.
v3: simplify commit message and code comments per reviewer feedback;
add Fixes tag and stable Cc
v2: also fix dGFX (VRAM placement + UC flag); remove now-dead
guc_ads_um_queues_size/offset helpers
Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Jia Yao <jia.yao@intel.com>
---
drivers/gpu/drm/xe/xe_guc_ads.c | 64 ++++++++++++++++-----------
drivers/gpu/drm/xe/xe_guc_ads_types.h | 8 +++-
2 files changed, 46 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index c98454545a85..ec36a5db7fc8 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -155,16 +155,6 @@ static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
return PAGE_ALIGN(ads->capture_size);
}
-static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
-{
- struct xe_device *xe = ads_to_xe(ads);
-
- if (!xe->info.has_usm)
- return 0;
-
- return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX;
-}
-
static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)
{
return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size);
@@ -205,22 +195,12 @@ static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
return PAGE_ALIGN(offset);
}
-static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
-{
- u32 offset;
-
- offset = guc_ads_capture_offset(ads) +
- guc_ads_capture_size(ads);
-
- return PAGE_ALIGN(offset);
-}
-
static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
{
size_t offset;
- offset = guc_ads_um_queues_offset(ads) +
- guc_ads_um_queues_size(ads);
+ offset = guc_ads_capture_offset(ads) +
+ guc_ads_capture_size(ads);
return PAGE_ALIGN(offset);
}
@@ -409,6 +389,30 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
ads->bo = bo;
+ /*
+ * The HW unit that writes to the UM fault queue is not coherent with
+ * the CPU cache. Use a dedicated UC BO to ensure GuC always reads
+ * descriptors from memory rather than a stale CPU cache line. A
+ * separate BO also prevents xe_guc_ads_populate()'s memset from
+ * zeroing descriptors written between GDRST and GuC restart. On
+ * dGFX, VRAM gives a well-defined DPA.
+ */
+ if (xe->info.has_usm) {
+ u32 um_flags = XE_BO_FLAG_GGTT |
+ XE_BO_FLAG_GGTT_INVALIDATE |
+ XE_BO_FLAG_PINNED_NORESTORE |
+ XE_BO_FLAG_NEEDS_UC |
+ XE_BO_FLAG_VRAM_IF_DGFX(tile);
+
+ bo = xe_managed_bo_create_pin_map(xe, tile,
+ GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX,
+ um_flags);
+ if (IS_ERR(bo))
+ return PTR_ERR(bo);
+
+ ads->um_queue_bo = bo;
+ }
+
return 0;
}
ALLOW_ERROR_INJECTION(xe_guc_ads_init, ERRNO); /* See xe_pci_probe() */
@@ -820,9 +824,9 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
static void guc_um_init_params(struct xe_guc_ads *ads)
{
- u32 um_queue_offset = guc_ads_um_queues_offset(ads);
struct xe_guc *guc = ads_to_guc(ads);
struct xe_device *xe = ads_to_xe(ads);
+ struct xe_bo *um_bo = ads->um_queue_bo;
u64 base_dpa;
u32 base_ggtt;
bool with_dpa;
@@ -830,8 +834,14 @@ static void guc_um_init_params(struct xe_guc_ads *ads)
with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
- base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
- base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
+ if (um_bo) {
+ /* All USM platforms: UM queues in dedicated um_queue_bo */
+ base_ggtt = xe_bo_ggtt_addr(um_bo);
+ base_dpa = xe_bo_main_addr(um_bo, PAGE_SIZE);
+ } else {
+ /* Platform does not support USM: no UM queues, nothing to do */
+ return;
+ }
for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
/*
@@ -912,6 +922,10 @@ void xe_guc_ads_populate(struct xe_guc_ads *ads)
xe_gt_assert(gt, ads->bo);
xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, xe_bo_size(ads->bo));
+ /*
+ * um_queue_bo is not zeroed here. GuC resets head/tail via MMIO on
+ * every restart so stale ring contents are never consumed.
+ */
guc_policies_init(ads);
fill_engine_enable_masks(gt, &info_map);
guc_mmio_reg_state_init(ads);
diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h
index 48a8e092023f..a63ef000dc8a 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h
@@ -14,8 +14,14 @@ struct xe_bo;
* struct xe_guc_ads - GuC additional data structures (ADS)
*/
struct xe_guc_ads {
- /** @bo: Xe BO for GuC ads blob */
+ /** @bo: Xe BO for GuC ads blob (WB cached) */
struct xe_bo *bo;
+ /**
+ * @um_queue_bo: Dedicated UC BO for the HW fault ring (UM queues).
+ * The HW unit writing to this ring is not coherent with the CPU cache;
+ * UC ensures GuC reads descriptors from memory. NULL if no USM support.
+ */
+ struct xe_bo *um_queue_bo;
/** @golden_lrc_size: golden LRC size */
size_t golden_lrc_size;
/** @regset_size: size of register set passed to GuC for save/restore */
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* ✗ CI.checkpatch: warning for drm/xe/guc_ads: allocate UM queues in a separate UC BO
2026-07-22 5:34 [PATCH v3 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO Jia Yao
2026-07-22 5:34 ` [PATCH v3 1/1] " Jia Yao
@ 2026-07-22 5:41 ` Patchwork
2026-07-22 5:42 ` ✓ CI.KUnit: success " Patchwork
` (3 subsequent siblings)
5 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2026-07-22 5:41 UTC (permalink / raw)
To: Jia Yao; +Cc: intel-xe
== Series Details ==
Series: drm/xe/guc_ads: allocate UM queues in a separate UC BO
URL : https://patchwork.freedesktop.org/series/170879/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit b19a063d78acc72bfcc507071441e931bb38bdfb
Author: Jia Yao <jia.yao@intel.com>
Date: Wed Jul 22 05:34:10 2026 +0000
drm/xe/guc_ads: allocate UM queues in a separate UC BO
The HW unit that writes to the UM fault queue is not always coherent
with the CPU cache. Ensure the UM queue memory is uncached on the CPU
side so that GuC always reads descriptors from memory rather than a
stale CPU cache line.
Allocate the UM queues in a dedicated UC BO (ads->um_queue_bo) instead
of the main ADS blob. This also prevents xe_guc_ads_populate()'s
memset from zeroing any fault descriptor written between GDRST and GuC
restart. On dGFX, VRAM placement gives a well-defined DPA.
v3: simplify commit message and code comments per reviewer feedback;
add Fixes tag and stable Cc
v2: also fix dGFX (VRAM placement + UC flag); remove now-dead
guc_ads_um_queues_size/offset helpers
Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Jia Yao <jia.yao@intel.com>
+ /mt/dim checkpatch 5726f9c4bde0290e5e60e636b9632bb03a57498c drm-intel
b19a063d78ac drm/xe/guc_ads: allocate UM queues in a separate UC BO
-:94: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#94: FILE: drivers/gpu/drm/xe/xe_guc_ads.c:460:
+ bo = xe_managed_bo_create_pin_map(xe, tile,
+ GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX,
total: 0 errors, 0 warnings, 1 checks, 121 lines checked
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ CI.KUnit: success for drm/xe/guc_ads: allocate UM queues in a separate UC BO
2026-07-22 5:34 [PATCH v3 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO Jia Yao
2026-07-22 5:34 ` [PATCH v3 1/1] " Jia Yao
2026-07-22 5:41 ` ✗ CI.checkpatch: warning for " Patchwork
@ 2026-07-22 5:42 ` Patchwork
2026-07-22 6:17 ` ✓ Xe.CI.BAT: " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2026-07-22 5:42 UTC (permalink / raw)
To: Jia Yao; +Cc: intel-xe
== Series Details ==
Series: drm/xe/guc_ads: allocate UM queues in a separate UC BO
URL : https://patchwork.freedesktop.org/series/170879/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[05:41:03] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:41:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:41:39] Starting KUnit Kernel (1/1)...
[05:41:39] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:41:39] ================== guc_buf (11 subtests) ===================
[05:41:39] [PASSED] test_smallest
[05:41:39] [PASSED] test_largest
[05:41:39] [PASSED] test_granular
[05:41:39] [PASSED] test_unique
[05:41:39] [PASSED] test_overlap
[05:41:39] [PASSED] test_reusable
[05:41:39] [PASSED] test_too_big
[05:41:39] [PASSED] test_flush
[05:41:39] [PASSED] test_lookup
[05:41:39] [PASSED] test_data
[05:41:39] [PASSED] test_class
[05:41:39] ===================== [PASSED] guc_buf =====================
[05:41:39] =================== guc_dbm (7 subtests) ===================
[05:41:39] [PASSED] test_empty
[05:41:39] [PASSED] test_default
[05:41:39] ======================== test_size ========================
[05:41:39] [PASSED] 4
[05:41:39] [PASSED] 8
[05:41:39] [PASSED] 32
[05:41:39] [PASSED] 256
[05:41:39] ==================== [PASSED] test_size ====================
[05:41:39] ======================= test_reuse ========================
[05:41:39] [PASSED] 4
[05:41:39] [PASSED] 8
[05:41:39] [PASSED] 32
[05:41:39] [PASSED] 256
[05:41:39] =================== [PASSED] test_reuse ====================
[05:41:39] =================== test_range_overlap ====================
[05:41:39] [PASSED] 4
[05:41:39] [PASSED] 8
[05:41:39] [PASSED] 32
[05:41:39] [PASSED] 256
[05:41:39] =============== [PASSED] test_range_overlap ================
[05:41:39] =================== test_range_compact ====================
[05:41:39] [PASSED] 4
[05:41:39] [PASSED] 8
[05:41:39] [PASSED] 32
[05:41:39] [PASSED] 256
[05:41:39] =============== [PASSED] test_range_compact ================
[05:41:39] ==================== test_range_spare =====================
[05:41:39] [PASSED] 4
[05:41:39] [PASSED] 8
[05:41:39] [PASSED] 32
[05:41:39] [PASSED] 256
[05:41:39] ================ [PASSED] test_range_spare =================
[05:41:39] ===================== [PASSED] guc_dbm =====================
[05:41:39] =================== guc_idm (6 subtests) ===================
[05:41:39] [PASSED] bad_init
[05:41:39] [PASSED] no_init
[05:41:39] [PASSED] init_fini
[05:41:39] [PASSED] check_used
[05:41:39] [PASSED] check_quota
[05:41:39] [PASSED] check_all
[05:41:39] ===================== [PASSED] guc_idm =====================
[05:41:39] =============== guc_klv_helpers (9 subtests) ===============
[05:41:39] [PASSED] test_count
[05:41:39] [PASSED] test_encode_u32
[05:41:39] [PASSED] test_encode_u64
[05:41:39] [PASSED] test_encode_string
[05:41:39] [PASSED] test_encode_object_raw
[05:41:39] [PASSED] test_encode_object_klv
[05:41:39] [PASSED] test_encode_object_nested
[05:41:39] [PASSED] test_encode_object_basic
[05:41:39] [PASSED] test_print
[05:41:39] ================= [PASSED] guc_klv_helpers =================
[05:41:39] ================== no_relay (3 subtests) ===================
[05:41:39] [PASSED] xe_drops_guc2pf_if_not_ready
[05:41:39] [PASSED] xe_drops_guc2vf_if_not_ready
[05:41:39] [PASSED] xe_rejects_send_if_not_ready
[05:41:39] ==================== [PASSED] no_relay =====================
[05:41:39] ================== pf_relay (14 subtests) ==================
[05:41:39] [PASSED] pf_rejects_guc2pf_too_short
[05:41:39] [PASSED] pf_rejects_guc2pf_too_long
[05:41:39] [PASSED] pf_rejects_guc2pf_no_payload
[05:41:39] [PASSED] pf_fails_no_payload
[05:41:39] [PASSED] pf_fails_bad_origin
[05:41:39] [PASSED] pf_fails_bad_type
[05:41:39] [PASSED] pf_txn_reports_error
[05:41:39] [PASSED] pf_txn_sends_pf2guc
[05:41:39] [PASSED] pf_sends_pf2guc
[05:41:39] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:41:39] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:41:39] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:41:39] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:41:39] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:41:39] ==================== [PASSED] pf_relay =====================
[05:41:39] ================== vf_relay (3 subtests) ===================
[05:41:39] [PASSED] vf_rejects_guc2vf_too_short
[05:41:39] [PASSED] vf_rejects_guc2vf_too_long
[05:41:39] [PASSED] vf_rejects_guc2vf_no_payload
[05:41:39] ==================== [PASSED] vf_relay =====================
[05:41:39] ================ pf_gt_config (9 subtests) =================
[05:41:39] [PASSED] fair_contexts_1vf
[05:41:39] [PASSED] fair_doorbells_1vf
[05:41:39] [PASSED] fair_ggtt_1vf
[05:41:39] ====================== fair_vram_1vf ======================
[05:41:39] [PASSED] 3.50 GiB
[05:41:39] [PASSED] 11.5 GiB
[05:41:39] [PASSED] 15.5 GiB
[05:41:39] [PASSED] 31.5 GiB
[05:41:39] [PASSED] 63.5 GiB
[05:41:39] [PASSED] 1.91 GiB
[05:41:39] ================== [PASSED] fair_vram_1vf ==================
[05:41:39] ================ fair_vram_1vf_admin_only =================
[05:41:39] [PASSED] 3.50 GiB
[05:41:39] [PASSED] 11.5 GiB
[05:41:39] [PASSED] 15.5 GiB
[05:41:39] [PASSED] 31.5 GiB
[05:41:39] [PASSED] 63.5 GiB
[05:41:39] [PASSED] 1.91 GiB
[05:41:39] ============ [PASSED] fair_vram_1vf_admin_only =============
[05:41:39] ====================== fair_contexts ======================
[05:41:39] [PASSED] 1 VF
[05:41:39] [PASSED] 2 VFs
[05:41:39] [PASSED] 3 VFs
[05:41:39] [PASSED] 4 VFs
[05:41:39] [PASSED] 5 VFs
[05:41:39] [PASSED] 6 VFs
[05:41:39] [PASSED] 7 VFs
[05:41:39] [PASSED] 8 VFs
[05:41:39] [PASSED] 9 VFs
[05:41:39] [PASSED] 10 VFs
[05:41:39] [PASSED] 11 VFs
[05:41:39] [PASSED] 12 VFs
[05:41:39] [PASSED] 13 VFs
[05:41:39] [PASSED] 14 VFs
[05:41:39] [PASSED] 15 VFs
[05:41:39] [PASSED] 16 VFs
[05:41:39] [PASSED] 17 VFs
[05:41:39] [PASSED] 18 VFs
[05:41:39] [PASSED] 19 VFs
[05:41:39] [PASSED] 20 VFs
[05:41:39] [PASSED] 21 VFs
[05:41:39] [PASSED] 22 VFs
[05:41:39] [PASSED] 23 VFs
[05:41:39] [PASSED] 24 VFs
[05:41:39] [PASSED] 25 VFs
[05:41:39] [PASSED] 26 VFs
[05:41:39] [PASSED] 27 VFs
[05:41:39] [PASSED] 28 VFs
[05:41:39] [PASSED] 29 VFs
[05:41:39] [PASSED] 30 VFs
[05:41:39] [PASSED] 31 VFs
[05:41:39] [PASSED] 32 VFs
[05:41:39] [PASSED] 33 VFs
[05:41:39] [PASSED] 34 VFs
[05:41:39] [PASSED] 35 VFs
[05:41:39] [PASSED] 36 VFs
[05:41:39] [PASSED] 37 VFs
[05:41:39] [PASSED] 38 VFs
[05:41:39] [PASSED] 39 VFs
[05:41:39] [PASSED] 40 VFs
[05:41:39] [PASSED] 41 VFs
[05:41:39] [PASSED] 42 VFs
[05:41:39] [PASSED] 43 VFs
[05:41:39] [PASSED] 44 VFs
[05:41:39] [PASSED] 45 VFs
[05:41:39] [PASSED] 46 VFs
[05:41:39] [PASSED] 47 VFs
[05:41:39] [PASSED] 48 VFs
[05:41:39] [PASSED] 49 VFs
[05:41:39] [PASSED] 50 VFs
[05:41:39] [PASSED] 51 VFs
[05:41:39] [PASSED] 52 VFs
[05:41:39] [PASSED] 53 VFs
[05:41:39] [PASSED] 54 VFs
[05:41:39] [PASSED] 55 VFs
[05:41:39] [PASSED] 56 VFs
[05:41:39] [PASSED] 57 VFs
[05:41:39] [PASSED] 58 VFs
[05:41:39] [PASSED] 59 VFs
[05:41:39] [PASSED] 60 VFs
[05:41:39] [PASSED] 61 VFs
[05:41:39] [PASSED] 62 VFs
[05:41:39] [PASSED] 63 VFs
[05:41:39] ================== [PASSED] fair_contexts ==================
[05:41:39] ===================== fair_doorbells ======================
[05:41:39] [PASSED] 1 VF
[05:41:39] [PASSED] 2 VFs
[05:41:39] [PASSED] 3 VFs
[05:41:39] [PASSED] 4 VFs
[05:41:39] [PASSED] 5 VFs
[05:41:39] [PASSED] 6 VFs
[05:41:39] [PASSED] 7 VFs
[05:41:39] [PASSED] 8 VFs
[05:41:39] [PASSED] 9 VFs
[05:41:39] [PASSED] 10 VFs
[05:41:39] [PASSED] 11 VFs
[05:41:39] [PASSED] 12 VFs
[05:41:39] [PASSED] 13 VFs
[05:41:39] [PASSED] 14 VFs
[05:41:39] [PASSED] 15 VFs
[05:41:39] [PASSED] 16 VFs
[05:41:39] [PASSED] 17 VFs
[05:41:39] [PASSED] 18 VFs
[05:41:39] [PASSED] 19 VFs
[05:41:39] [PASSED] 20 VFs
[05:41:39] [PASSED] 21 VFs
[05:41:39] [PASSED] 22 VFs
[05:41:39] [PASSED] 23 VFs
[05:41:39] [PASSED] 24 VFs
[05:41:39] [PASSED] 25 VFs
[05:41:39] [PASSED] 26 VFs
[05:41:39] [PASSED] 27 VFs
[05:41:39] [PASSED] 28 VFs
[05:41:39] [PASSED] 29 VFs
[05:41:39] [PASSED] 30 VFs
[05:41:39] [PASSED] 31 VFs
[05:41:39] [PASSED] 32 VFs
[05:41:39] [PASSED] 33 VFs
[05:41:39] [PASSED] 34 VFs
[05:41:39] [PASSED] 35 VFs
[05:41:39] [PASSED] 36 VFs
[05:41:39] [PASSED] 37 VFs
[05:41:39] [PASSED] 38 VFs
[05:41:39] [PASSED] 39 VFs
[05:41:39] [PASSED] 40 VFs
[05:41:39] [PASSED] 41 VFs
[05:41:39] [PASSED] 42 VFs
[05:41:39] [PASSED] 43 VFs
[05:41:39] [PASSED] 44 VFs
[05:41:39] [PASSED] 45 VFs
[05:41:39] [PASSED] 46 VFs
[05:41:39] [PASSED] 47 VFs
[05:41:39] [PASSED] 48 VFs
[05:41:39] [PASSED] 49 VFs
[05:41:39] [PASSED] 50 VFs
[05:41:39] [PASSED] 51 VFs
[05:41:39] [PASSED] 52 VFs
[05:41:39] [PASSED] 53 VFs
[05:41:39] [PASSED] 54 VFs
[05:41:39] [PASSED] 55 VFs
[05:41:39] [PASSED] 56 VFs
[05:41:39] [PASSED] 57 VFs
[05:41:39] [PASSED] 58 VFs
[05:41:39] [PASSED] 59 VFs
[05:41:39] [PASSED] 60 VFs
[05:41:39] [PASSED] 61 VFs
[05:41:39] [PASSED] 62 VFs
[05:41:39] [PASSED] 63 VFs
[05:41:39] ================= [PASSED] fair_doorbells ==================
[05:41:39] ======================== fair_ggtt ========================
[05:41:39] [PASSED] 1 VF
[05:41:39] [PASSED] 2 VFs
[05:41:39] [PASSED] 3 VFs
[05:41:39] [PASSED] 4 VFs
[05:41:39] [PASSED] 5 VFs
[05:41:39] [PASSED] 6 VFs
[05:41:39] [PASSED] 7 VFs
[05:41:39] [PASSED] 8 VFs
[05:41:39] [PASSED] 9 VFs
[05:41:39] [PASSED] 10 VFs
[05:41:39] [PASSED] 11 VFs
[05:41:39] [PASSED] 12 VFs
[05:41:39] [PASSED] 13 VFs
[05:41:39] [PASSED] 14 VFs
[05:41:39] [PASSED] 15 VFs
[05:41:39] [PASSED] 16 VFs
[05:41:39] [PASSED] 17 VFs
[05:41:39] [PASSED] 18 VFs
[05:41:39] [PASSED] 19 VFs
[05:41:39] [PASSED] 20 VFs
[05:41:39] [PASSED] 21 VFs
[05:41:39] [PASSED] 22 VFs
[05:41:39] [PASSED] 23 VFs
[05:41:39] [PASSED] 24 VFs
[05:41:39] [PASSED] 25 VFs
[05:41:39] [PASSED] 26 VFs
[05:41:39] [PASSED] 27 VFs
[05:41:39] [PASSED] 28 VFs
[05:41:39] [PASSED] 29 VFs
[05:41:39] [PASSED] 30 VFs
[05:41:39] [PASSED] 31 VFs
[05:41:39] [PASSED] 32 VFs
[05:41:39] [PASSED] 33 VFs
[05:41:39] [PASSED] 34 VFs
[05:41:39] [PASSED] 35 VFs
[05:41:39] [PASSED] 36 VFs
[05:41:39] [PASSED] 37 VFs
[05:41:39] [PASSED] 38 VFs
[05:41:39] [PASSED] 39 VFs
[05:41:39] [PASSED] 40 VFs
[05:41:40] [PASSED] 41 VFs
[05:41:40] [PASSED] 42 VFs
[05:41:40] [PASSED] 43 VFs
[05:41:40] [PASSED] 44 VFs
[05:41:40] [PASSED] 45 VFs
[05:41:40] [PASSED] 46 VFs
[05:41:40] [PASSED] 47 VFs
[05:41:40] [PASSED] 48 VFs
[05:41:40] [PASSED] 49 VFs
[05:41:40] [PASSED] 50 VFs
[05:41:40] [PASSED] 51 VFs
[05:41:40] [PASSED] 52 VFs
[05:41:40] [PASSED] 53 VFs
[05:41:40] [PASSED] 54 VFs
[05:41:40] [PASSED] 55 VFs
[05:41:40] [PASSED] 56 VFs
[05:41:40] [PASSED] 57 VFs
[05:41:40] [PASSED] 58 VFs
[05:41:40] [PASSED] 59 VFs
[05:41:40] [PASSED] 60 VFs
[05:41:40] [PASSED] 61 VFs
[05:41:40] [PASSED] 62 VFs
[05:41:40] [PASSED] 63 VFs
[05:41:40] ==================== [PASSED] fair_ggtt ====================
[05:41:40] ======================== fair_vram ========================
[05:41:40] [PASSED] 1 VF
[05:41:40] [PASSED] 2 VFs
[05:41:40] [PASSED] 3 VFs
[05:41:40] [PASSED] 4 VFs
[05:41:40] [PASSED] 5 VFs
[05:41:40] [PASSED] 6 VFs
[05:41:40] [PASSED] 7 VFs
[05:41:40] [PASSED] 8 VFs
[05:41:40] [PASSED] 9 VFs
[05:41:40] [PASSED] 10 VFs
[05:41:40] [PASSED] 11 VFs
[05:41:40] [PASSED] 12 VFs
[05:41:40] [PASSED] 13 VFs
[05:41:40] [PASSED] 14 VFs
[05:41:40] [PASSED] 15 VFs
[05:41:40] [PASSED] 16 VFs
[05:41:40] [PASSED] 17 VFs
[05:41:40] [PASSED] 18 VFs
[05:41:40] [PASSED] 19 VFs
[05:41:40] [PASSED] 20 VFs
[05:41:40] [PASSED] 21 VFs
[05:41:40] [PASSED] 22 VFs
[05:41:40] [PASSED] 23 VFs
[05:41:40] [PASSED] 24 VFs
[05:41:40] [PASSED] 25 VFs
[05:41:40] [PASSED] 26 VFs
[05:41:40] [PASSED] 27 VFs
[05:41:40] [PASSED] 28 VFs
[05:41:40] [PASSED] 29 VFs
[05:41:40] [PASSED] 30 VFs
[05:41:40] [PASSED] 31 VFs
[05:41:40] [PASSED] 32 VFs
[05:41:40] [PASSED] 33 VFs
[05:41:40] [PASSED] 34 VFs
[05:41:40] [PASSED] 35 VFs
[05:41:40] [PASSED] 36 VFs
[05:41:40] [PASSED] 37 VFs
[05:41:40] [PASSED] 38 VFs
[05:41:40] [PASSED] 39 VFs
[05:41:40] [PASSED] 40 VFs
[05:41:40] [PASSED] 41 VFs
[05:41:40] [PASSED] 42 VFs
[05:41:40] [PASSED] 43 VFs
[05:41:40] [PASSED] 44 VFs
[05:41:40] [PASSED] 45 VFs
[05:41:40] [PASSED] 46 VFs
[05:41:40] [PASSED] 47 VFs
[05:41:40] [PASSED] 48 VFs
[05:41:40] [PASSED] 49 VFs
[05:41:40] [PASSED] 50 VFs
[05:41:40] [PASSED] 51 VFs
[05:41:40] [PASSED] 52 VFs
[05:41:40] [PASSED] 53 VFs
[05:41:40] [PASSED] 54 VFs
[05:41:40] [PASSED] 55 VFs
[05:41:40] [PASSED] 56 VFs
[05:41:40] [PASSED] 57 VFs
[05:41:40] [PASSED] 58 VFs
[05:41:40] [PASSED] 59 VFs
[05:41:40] [PASSED] 60 VFs
[05:41:40] [PASSED] 61 VFs
[05:41:40] [PASSED] 62 VFs
[05:41:40] [PASSED] 63 VFs
[05:41:40] ==================== [PASSED] fair_vram ====================
[05:41:40] ================== [PASSED] pf_gt_config ===================
[05:41:40] ===================== lmtt (1 subtest) =====================
[05:41:40] ======================== test_ops =========================
[05:41:40] [PASSED] 2-level
[05:41:40] [PASSED] multi-level
[05:41:40] ==================== [PASSED] test_ops =====================
[05:41:40] ====================== [PASSED] lmtt =======================
[05:41:40] ================= sriov_packet (1 subtest) =================
[05:41:40] [PASSED] test_descriptor_init
[05:41:40] ================== [PASSED] sriov_packet ===================
[05:41:40] ================= pf_service (11 subtests) =================
[05:41:40] [PASSED] pf_negotiate_any
[05:41:40] [PASSED] pf_negotiate_base_match
[05:41:40] [PASSED] pf_negotiate_base_newer
[05:41:40] [PASSED] pf_negotiate_base_next
[05:41:40] [SKIPPED] pf_negotiate_base_older (no older minor)
[05:41:40] [PASSED] pf_negotiate_base_prev
[05:41:40] [PASSED] pf_negotiate_latest_match
[05:41:40] [PASSED] pf_negotiate_latest_newer
[05:41:40] [PASSED] pf_negotiate_latest_next
[05:41:40] [SKIPPED] pf_negotiate_latest_older (no older minor)
[05:41:40] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[05:41:40] =================== [PASSED] pf_service ====================
[05:41:40] ================= xe_guc_g2g (2 subtests) ==================
[05:41:40] ============== xe_live_guc_g2g_kunit_default ==============
[05:41:40] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[05:41:40] ============== xe_live_guc_g2g_kunit_allmem ===============
[05:41:40] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[05:41:40] =================== [SKIPPED] xe_guc_g2g ===================
[05:41:40] =================== xe_mocs (2 subtests) ===================
[05:41:40] ================ xe_live_mocs_kernel_kunit ================
[05:41:40] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[05:41:40] ================ xe_live_mocs_reset_kunit =================
[05:41:40] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[05:41:40] ==================== [SKIPPED] xe_mocs =====================
[05:41:40] ================= xe_migrate (2 subtests) ==================
[05:41:40] ================= xe_migrate_sanity_kunit =================
[05:41:40] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[05:41:40] ================== xe_validate_ccs_kunit ==================
[05:41:40] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[05:41:40] =================== [SKIPPED] xe_migrate ===================
[05:41:40] ================== xe_dma_buf (1 subtest) ==================
[05:41:40] ==================== xe_dma_buf_kunit =====================
[05:41:40] ================ [SKIPPED] xe_dma_buf_kunit ================
[05:41:40] =================== [SKIPPED] xe_dma_buf ===================
[05:41:40] ================= xe_bo_shrink (1 subtest) =================
[05:41:40] =================== xe_bo_shrink_kunit ====================
[05:41:40] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[05:41:40] ================== [SKIPPED] xe_bo_shrink ==================
[05:41:40] ==================== xe_bo (2 subtests) ====================
[05:41:40] ================== xe_ccs_migrate_kunit ===================
[05:41:40] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[05:41:40] ==================== xe_bo_evict_kunit ====================
[05:41:40] =============== [SKIPPED] xe_bo_evict_kunit ================
[05:41:40] ===================== [SKIPPED] xe_bo ======================
[05:41:40] ==================== args (13 subtests) ====================
[05:41:40] [PASSED] count_args_test
[05:41:40] [PASSED] call_args_example
[05:41:40] [PASSED] call_args_test
[05:41:40] [PASSED] drop_first_arg_example
[05:41:40] [PASSED] drop_first_arg_test
[05:41:40] [PASSED] first_arg_example
[05:41:40] [PASSED] first_arg_test
[05:41:40] [PASSED] last_arg_example
[05:41:40] [PASSED] last_arg_test
[05:41:40] [PASSED] pick_arg_example
[05:41:40] [PASSED] if_args_example
[05:41:40] [PASSED] if_args_test
[05:41:40] [PASSED] sep_comma_example
[05:41:40] ====================== [PASSED] args =======================
[05:41:40] =================== xe_pci (3 subtests) ====================
[05:41:40] ==================== check_graphics_ip ====================
[05:41:40] [PASSED] 12.00 Xe_LP
[05:41:40] [PASSED] 12.10 Xe_LP+
[05:41:40] [PASSED] 12.55 Xe_HPG
[05:41:40] [PASSED] 12.60 Xe_HPC
[05:41:40] [PASSED] 12.70 Xe_LPG
[05:41:40] [PASSED] 12.71 Xe_LPG
[05:41:40] [PASSED] 12.74 Xe_LPG+
[05:41:40] [PASSED] 20.01 Xe2_HPG
[05:41:40] [PASSED] 20.02 Xe2_HPG
[05:41:40] [PASSED] 20.04 Xe2_LPG
[05:41:40] [PASSED] 30.00 Xe3_LPG
[05:41:40] [PASSED] 30.01 Xe3_LPG
[05:41:40] [PASSED] 30.03 Xe3_LPG
[05:41:40] [PASSED] 30.04 Xe3_LPG
[05:41:40] [PASSED] 30.05 Xe3_LPG
[05:41:40] [PASSED] 35.10 Xe3p_LPG
[05:41:40] [PASSED] 35.11 Xe3p_XPC
[05:41:40] ================ [PASSED] check_graphics_ip ================
[05:41:40] ===================== check_media_ip ======================
[05:41:40] [PASSED] 12.00 Xe_M
[05:41:40] [PASSED] 12.55 Xe_HPM
[05:41:40] [PASSED] 13.00 Xe_LPM+
[05:41:40] [PASSED] 13.01 Xe2_HPM
[05:41:40] [PASSED] 20.00 Xe2_LPM
[05:41:40] [PASSED] 30.00 Xe3_LPM
[05:41:40] [PASSED] 30.02 Xe3_LPM
[05:41:40] [PASSED] 35.00 Xe3p_LPM
[05:41:40] [PASSED] 35.03 Xe3p_HPM
[05:41:40] ================= [PASSED] check_media_ip ==================
[05:41:40] =================== check_platform_desc ===================
[05:41:40] [PASSED] 0x9A60 (TIGERLAKE)
[05:41:40] [PASSED] 0x9A68 (TIGERLAKE)
[05:41:40] [PASSED] 0x9A70 (TIGERLAKE)
[05:41:40] [PASSED] 0x9A40 (TIGERLAKE)
[05:41:40] [PASSED] 0x9A49 (TIGERLAKE)
[05:41:40] [PASSED] 0x9A59 (TIGERLAKE)
[05:41:40] [PASSED] 0x9A78 (TIGERLAKE)
[05:41:40] [PASSED] 0x9AC0 (TIGERLAKE)
[05:41:40] [PASSED] 0x9AC9 (TIGERLAKE)
[05:41:40] [PASSED] 0x9AD9 (TIGERLAKE)
[05:41:40] [PASSED] 0x9AF8 (TIGERLAKE)
[05:41:40] [PASSED] 0x4C80 (ROCKETLAKE)
[05:41:40] [PASSED] 0x4C8A (ROCKETLAKE)
[05:41:40] [PASSED] 0x4C8B (ROCKETLAKE)
[05:41:40] [PASSED] 0x4C8C (ROCKETLAKE)
[05:41:40] [PASSED] 0x4C90 (ROCKETLAKE)
[05:41:40] [PASSED] 0x4C9A (ROCKETLAKE)
[05:41:40] [PASSED] 0x4680 (ALDERLAKE_S)
[05:41:40] [PASSED] 0x4682 (ALDERLAKE_S)
[05:41:40] [PASSED] 0x4688 (ALDERLAKE_S)
[05:41:40] [PASSED] 0x468A (ALDERLAKE_S)
[05:41:40] [PASSED] 0x468B (ALDERLAKE_S)
[05:41:40] [PASSED] 0x4690 (ALDERLAKE_S)
[05:41:40] [PASSED] 0x4692 (ALDERLAKE_S)
[05:41:40] [PASSED] 0x4693 (ALDERLAKE_S)
[05:41:40] [PASSED] 0x46A0 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x46A1 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x46A2 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x46A3 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x46A6 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x46A8 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x46AA (ALDERLAKE_P)
[05:41:40] [PASSED] 0x462A (ALDERLAKE_P)
[05:41:40] [PASSED] 0x4626 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x4628 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x46B0 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x46B1 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x46B2 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x46B3 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x46C0 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x46C1 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x46C2 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x46C3 (ALDERLAKE_P)
[05:41:40] [PASSED] 0x46D0 (ALDERLAKE_N)
[05:41:40] [PASSED] 0x46D1 (ALDERLAKE_N)
[05:41:40] [PASSED] 0x46D2 (ALDERLAKE_N)
[05:41:40] [PASSED] 0x46D3 (ALDERLAKE_N)
[05:41:40] [PASSED] 0x46D4 (ALDERLAKE_N)
[05:41:40] [PASSED] 0xA721 (ALDERLAKE_P)
[05:41:40] [PASSED] 0xA7A1 (ALDERLAKE_P)
[05:41:40] [PASSED] 0xA7A9 (ALDERLAKE_P)
[05:41:40] [PASSED] 0xA7AC (ALDERLAKE_P)
[05:41:40] [PASSED] 0xA7AD (ALDERLAKE_P)
[05:41:40] [PASSED] 0xA720 (ALDERLAKE_P)
[05:41:40] [PASSED] 0xA7A0 (ALDERLAKE_P)
[05:41:40] [PASSED] 0xA7A8 (ALDERLAKE_P)
[05:41:40] [PASSED] 0xA7AA (ALDERLAKE_P)
[05:41:40] [PASSED] 0xA7AB (ALDERLAKE_P)
[05:41:40] [PASSED] 0xA780 (ALDERLAKE_S)
[05:41:40] [PASSED] 0xA781 (ALDERLAKE_S)
[05:41:40] [PASSED] 0xA782 (ALDERLAKE_S)
[05:41:40] [PASSED] 0xA783 (ALDERLAKE_S)
[05:41:40] [PASSED] 0xA788 (ALDERLAKE_S)
[05:41:40] [PASSED] 0xA789 (ALDERLAKE_S)
[05:41:40] [PASSED] 0xA78A (ALDERLAKE_S)
[05:41:40] [PASSED] 0xA78B (ALDERLAKE_S)
[05:41:40] [PASSED] 0x4905 (DG1)
[05:41:40] [PASSED] 0x4906 (DG1)
[05:41:40] [PASSED] 0x4907 (DG1)
[05:41:40] [PASSED] 0x4908 (DG1)
[05:41:40] [PASSED] 0x4909 (DG1)
[05:41:40] [PASSED] 0x56C0 (DG2)
[05:41:40] [PASSED] 0x56C2 (DG2)
[05:41:40] [PASSED] 0x56C1 (DG2)
[05:41:40] [PASSED] 0x7D51 (METEORLAKE)
[05:41:40] [PASSED] 0x7DD1 (METEORLAKE)
[05:41:40] [PASSED] 0x7D41 (METEORLAKE)
[05:41:40] [PASSED] 0x7D67 (METEORLAKE)
[05:41:40] [PASSED] 0xB640 (METEORLAKE)
[05:41:40] [PASSED] 0x56A0 (DG2)
[05:41:40] [PASSED] 0x56A1 (DG2)
[05:41:40] [PASSED] 0x56A2 (DG2)
[05:41:40] [PASSED] 0x56BE (DG2)
[05:41:40] [PASSED] 0x56BF (DG2)
[05:41:40] [PASSED] 0x5690 (DG2)
[05:41:40] [PASSED] 0x5691 (DG2)
[05:41:40] [PASSED] 0x5692 (DG2)
[05:41:40] [PASSED] 0x56A5 (DG2)
[05:41:40] [PASSED] 0x56A6 (DG2)
[05:41:40] [PASSED] 0x56B0 (DG2)
[05:41:40] [PASSED] 0x56B1 (DG2)
[05:41:40] [PASSED] 0x56BA (DG2)
[05:41:40] [PASSED] 0x56BB (DG2)
[05:41:40] [PASSED] 0x56BC (DG2)
[05:41:40] [PASSED] 0x56BD (DG2)
[05:41:40] [PASSED] 0x5693 (DG2)
[05:41:40] [PASSED] 0x5694 (DG2)
[05:41:40] [PASSED] 0x5695 (DG2)
[05:41:40] [PASSED] 0x56A3 (DG2)
[05:41:40] [PASSED] 0x56A4 (DG2)
[05:41:40] [PASSED] 0x56B2 (DG2)
[05:41:40] [PASSED] 0x56B3 (DG2)
[05:41:40] [PASSED] 0x5696 (DG2)
[05:41:40] [PASSED] 0x5697 (DG2)
[05:41:40] [PASSED] 0xB69 (PVC)
[05:41:40] [PASSED] 0xB6E (PVC)
[05:41:40] [PASSED] 0xBD4 (PVC)
[05:41:40] [PASSED] 0xBD5 (PVC)
[05:41:40] [PASSED] 0xBD6 (PVC)
[05:41:40] [PASSED] 0xBD7 (PVC)
[05:41:40] [PASSED] 0xBD8 (PVC)
[05:41:40] [PASSED] 0xBD9 (PVC)
[05:41:40] [PASSED] 0xBDA (PVC)
[05:41:40] [PASSED] 0xBDB (PVC)
[05:41:40] [PASSED] 0xBE0 (PVC)
[05:41:40] [PASSED] 0xBE1 (PVC)
[05:41:40] [PASSED] 0xBE5 (PVC)
[05:41:40] [PASSED] 0x7D40 (METEORLAKE)
[05:41:40] [PASSED] 0x7D45 (METEORLAKE)
[05:41:40] [PASSED] 0x7D55 (METEORLAKE)
[05:41:40] [PASSED] 0x7D60 (METEORLAKE)
[05:41:40] [PASSED] 0x7DD5 (METEORLAKE)
[05:41:40] [PASSED] 0x6420 (LUNARLAKE)
[05:41:40] [PASSED] 0x64A0 (LUNARLAKE)
[05:41:40] [PASSED] 0x64B0 (LUNARLAKE)
[05:41:40] [PASSED] 0xE202 (BATTLEMAGE)
[05:41:40] [PASSED] 0xE209 (BATTLEMAGE)
[05:41:40] [PASSED] 0xE20B (BATTLEMAGE)
[05:41:40] [PASSED] 0xE20C (BATTLEMAGE)
[05:41:40] [PASSED] 0xE20D (BATTLEMAGE)
[05:41:40] [PASSED] 0xE210 (BATTLEMAGE)
[05:41:40] [PASSED] 0xE211 (BATTLEMAGE)
[05:41:40] [PASSED] 0xE212 (BATTLEMAGE)
[05:41:40] [PASSED] 0xE216 (BATTLEMAGE)
[05:41:40] [PASSED] 0xE220 (BATTLEMAGE)
[05:41:40] [PASSED] 0xE221 (BATTLEMAGE)
[05:41:40] [PASSED] 0xE222 (BATTLEMAGE)
[05:41:40] [PASSED] 0xE223 (BATTLEMAGE)
[05:41:40] [PASSED] 0xB080 (PANTHERLAKE)
[05:41:40] [PASSED] 0xB081 (PANTHERLAKE)
[05:41:40] [PASSED] 0xB082 (PANTHERLAKE)
[05:41:40] [PASSED] 0xB083 (PANTHERLAKE)
[05:41:40] [PASSED] 0xB084 (PANTHERLAKE)
[05:41:40] [PASSED] 0xB085 (PANTHERLAKE)
[05:41:40] [PASSED] 0xB086 (PANTHERLAKE)
[05:41:40] [PASSED] 0xB087 (PANTHERLAKE)
[05:41:40] [PASSED] 0xB08F (PANTHERLAKE)
[05:41:40] [PASSED] 0xB090 (PANTHERLAKE)
[05:41:40] [PASSED] 0xB0A0 (PANTHERLAKE)
[05:41:40] [PASSED] 0xB0B0 (PANTHERLAKE)
[05:41:40] [PASSED] 0xFD80 (PANTHERLAKE)
[05:41:40] [PASSED] 0xFD81 (PANTHERLAKE)
[05:41:40] [PASSED] 0xD740 (NOVALAKE_S)
[05:41:40] [PASSED] 0xD741 (NOVALAKE_S)
[05:41:40] [PASSED] 0xD742 (NOVALAKE_S)
[05:41:40] [PASSED] 0xD743 (NOVALAKE_S)
[05:41:40] [PASSED] 0xD745 (NOVALAKE_S)
[05:41:40] [PASSED] 0xD74A (NOVALAKE_S)
[05:41:40] [PASSED] 0xD74B (NOVALAKE_S)
[05:41:40] [PASSED] 0x674C (CRESCENTISLAND)
[05:41:40] [PASSED] 0x674D (CRESCENTISLAND)
[05:41:40] [PASSED] 0x674E (CRESCENTISLAND)
[05:41:40] [PASSED] 0x674F (CRESCENTISLAND)
[05:41:40] [PASSED] 0x6750 (CRESCENTISLAND)
[05:41:40] [PASSED] 0xD750 (NOVALAKE_P)
[05:41:40] [PASSED] 0xD751 (NOVALAKE_P)
[05:41:40] [PASSED] 0xD752 (NOVALAKE_P)
[05:41:40] [PASSED] 0xD753 (NOVALAKE_P)
[05:41:40] [PASSED] 0xD754 (NOVALAKE_P)
[05:41:40] [PASSED] 0xD755 (NOVALAKE_P)
[05:41:40] [PASSED] 0xD756 (NOVALAKE_P)
[05:41:40] [PASSED] 0xD757 (NOVALAKE_P)
[05:41:40] [PASSED] 0xD75F (NOVALAKE_P)
[05:41:40] =============== [PASSED] check_platform_desc ===============
[05:41:40] ===================== [PASSED] xe_pci ======================
[05:41:40] ============= xe_rtp_tables_test (5 subtests) ==============
[05:41:40] ================== xe_rtp_table_gt_test ===================
[05:41:40] [PASSED] gt_was/14011060649
[05:41:40] [PASSED] gt_was/14011059788
[05:41:40] [PASSED] gt_was/14015795083
[05:41:40] [PASSED] gt_was/16021867713
[05:41:40] [PASSED] gt_was/14019449301
[05:41:40] [PASSED] gt_was/16028005424
[05:41:40] [PASSED] gt_was/14026578760
[05:41:40] [PASSED] gt_was/1409420604
[05:41:40] [PASSED] gt_was/1408615072
[05:41:40] [PASSED] gt_was/22010523718
[05:41:40] [PASSED] gt_was/14011006942
[05:41:40] [PASSED] gt_was/14014830051
[05:41:40] [PASSED] gt_was/18018781329
[05:41:40] [PASSED] gt_was/1509235366
[05:41:40] [PASSED] gt_was/18018781329
[05:41:40] [PASSED] gt_was/16016694945
[05:41:40] [PASSED] gt_was/14018575942
[05:41:40] [PASSED] gt_was/22016670082
[05:41:40] [PASSED] gt_was/22016670082
[05:41:40] [PASSED] gt_was/14017421178
[05:41:40] [PASSED] gt_was/16025250150
[05:41:40] [PASSED] gt_was/14021871409
[05:41:40] [PASSED] gt_was/16021865536
[05:41:40] [PASSED] gt_was/14021486841
[05:41:40] [PASSED] gt_was/14025160223
[05:41:40] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[05:41:40] [PASSED] gt_was/14025635424
[05:41:40] [PASSED] gt_was/16028005424
[05:41:40] ============== [PASSED] xe_rtp_table_gt_test ===============
[05:41:40] ================== xe_rtp_table_gt_test ===================
[05:41:40] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[05:41:40] [PASSED] gt_tunings/Tuning: 32B Access Enable
[05:41:40] [PASSED] gt_tunings/Tuning: L3 cache
[05:41:40] [PASSED] gt_tunings/Tuning: L3 cache - media
[05:41:40] [PASSED] gt_tunings/Tuning: Compression Overfetch
[05:41:40] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[05:41:40] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[05:41:40] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[05:41:40] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[05:41:40] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[05:41:40] [PASSED] gt_tunings/Tuning: Stateless compression control
[05:41:40] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[05:41:40] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[05:41:40] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[05:41:40] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[05:41:40] ============== [PASSED] xe_rtp_table_gt_test ===============
[05:41:40] ================== xe_rtp_table_oob_test ==================
[05:41:40] [PASSED] oob_was/1607983814
[05:41:40] [PASSED] oob_was/16010904313
[05:41:40] [PASSED] oob_was/18022495364
[05:41:40] [PASSED] oob_was/22012773006
[05:41:40] [PASSED] oob_was/14014475959
[05:41:40] [PASSED] oob_was/22011391025
[05:41:40] [PASSED] oob_was/22012727170
[05:41:40] [PASSED] oob_was/22012727685
[05:41:40] [PASSED] oob_was/22016596838
[05:41:40] [PASSED] oob_was/18020744125
[05:41:40] [PASSED] oob_was/1409600907
[05:41:40] [PASSED] oob_was/22014953428
[05:41:40] [PASSED] oob_was/16017236439
[05:41:40] [PASSED] oob_was/14019821291
[05:41:40] [PASSED] oob_was/14015076503
[05:41:40] [PASSED] oob_was/14018913170
[05:41:40] [PASSED] oob_was/14018094691
[05:41:40] [PASSED] oob_was/18024947630
[05:41:40] [PASSED] oob_was/16022287689
[05:41:40] [PASSED] oob_was/13011645652
[05:41:40] [PASSED] oob_was/14022293748
[05:41:40] [PASSED] oob_was/22019794406
[05:41:40] [PASSED] oob_was/22019338487
[05:41:40] [PASSED] oob_was/16023588340
[05:41:40] [PASSED] oob_was/14019789679
[05:41:40] [PASSED] oob_was/14022866841
[05:41:40] [PASSED] oob_was/16021333562
[05:41:40] [PASSED] oob_was/14016712196
[05:41:40] [PASSED] oob_was/14015568240
[05:41:40] [PASSED] oob_was/18013179988
[05:41:40] [PASSED] oob_was/1508761755
[05:41:40] [PASSED] oob_was/16023105232
[05:41:40] [PASSED] oob_was/16026508708
[05:41:40] [PASSED] oob_was/14020001231
[05:41:40] [PASSED] oob_was/16023683509
[05:41:40] [PASSED] oob_was/14025515070
[05:41:40] [PASSED] oob_was/15015404425_disable
[05:41:40] [PASSED] oob_was/16026007364
[05:41:40] [PASSED] oob_was/14020316580
[05:41:40] [PASSED] oob_was/14025883347
[05:41:40] [PASSED] oob_was/16029380221
[05:41:40] [PASSED] oob_was/22022079272
[05:41:40] [PASSED] oob_was/16029897822
[05:41:40] ============== [PASSED] xe_rtp_table_oob_test ==============
[05:41:40] ================ xe_rtp_table_dev_oob_test ================
[05:41:40] [PASSED] device_oob_was/22010954014
[05:41:40] [PASSED] device_oob_was/15015404425
[05:41:40] [PASSED] device_oob_was/22019338487_display
[05:41:40] [PASSED] device_oob_was/14022085890
[05:41:40] [PASSED] device_oob_was/14026539277
[05:41:40] [PASSED] device_oob_was/14026633728
[05:41:40] [PASSED] device_oob_was/14026746987
[05:41:40] [PASSED] device_oob_was/14026779378
[05:41:40] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[05:41:40] ========== xe_rtp_table_missing_upper_bound_test ==========
[05:41:40] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[05:41:40] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[05:41:40] [PASSED] register_whitelist/1806527549
[05:41:40] [PASSED] register_whitelist/allow_read_ctx_timestamp
[05:41:40] [PASSED] register_whitelist/allow_read_queue_timestamp
[05:41:40] [PASSED] register_whitelist/16014440446
[05:41:40] [PASSED] register_whitelist/16017236439
[05:41:40] [PASSED] register_whitelist/16020183090
[05:41:40] [PASSED] register_whitelist/14024997852
[05:41:40] [PASSED] register_whitelist/14024997852
[05:41:40] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[05:41:40] =============== [PASSED] xe_rtp_tables_test ================
[05:41:40] =================== xe_rtp (3 subtests) ====================
[05:41:40] =================== xe_rtp_rules_tests ====================
[05:41:40] [PASSED] no
[05:41:40] [PASSED] yes
[05:41:40] [PASSED] no-and-no
[05:41:40] [PASSED] no-and-yes
[05:41:40] [PASSED] yes-and-no
[05:41:40] [PASSED] yes-and-yes
[05:41:40] [PASSED] no-or-no
[05:41:40] [PASSED] no-or-yes
[05:41:40] [PASSED] yes-or-no
[05:41:40] [PASSED] yes-or-yes
[05:41:40] [PASSED] no-yes-or-yes-no
[05:41:40] [PASSED] no-yes-or-yes-yes
[05:41:40] [PASSED] yes-yes-or-no-yes
[05:41:40] [PASSED] yes-yes-or-yes-yes
[05:41:40] [PASSED] no-no-or-yes-or-no
[05:41:40] [PASSED] or
[05:41:40] [PASSED] or-yes
[05:41:40] [PASSED] or-no
[05:41:40] [PASSED] yes-or
[05:41:40] [PASSED] no-or
[05:41:40] [PASSED] no-or-or-yes
[05:41:40] [PASSED] yes-or-or-no
[05:41:40] [PASSED] no-or-or-no
[05:41:40] [PASSED] missing-context-engine-class
[05:41:40] [PASSED] missing-context-engine-class-or-yes
[05:41:40] [PASSED] missing-context-engine-class-or-or-yes
[05:41:40] =============== [PASSED] xe_rtp_rules_tests ================
[05:41:40] =============== xe_rtp_process_to_sr_tests ================
[05:41:40] [PASSED] coalesce-same-reg
[05:41:40] [PASSED] coalesce-same-reg-literal-and-func
[05:41:40] [PASSED] no-match-no-add
[05:41:40] [PASSED] two-regs-two-entries
[05:41:40] [PASSED] clr-one-set-other
[05:41:40] [PASSED] set-field
[05:41:40] [PASSED] conflict-duplicate
[05:41:40] [PASSED] conflict-not-disjoint
[05:41:40] [PASSED] conflict-not-disjoint-literal-and-func
[05:41:40] [PASSED] conflict-reg-type
[05:41:40] [PASSED] bad-mcr-reg-forced-to-regular
[05:41:40] [PASSED] bad-regular-reg-forced-to-mcr
[05:41:40] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[05:41:40] ================== xe_rtp_process_tests ===================
[05:41:40] [PASSED] active1
[05:41:40] [PASSED] active2
[05:41:40] [PASSED] active-inactive
[05:41:40] [PASSED] inactive-active
[05:41:40] [PASSED] inactive-active-inactive
[05:41:40] [PASSED] inactive-inactive-inactive
[05:41:40] ============== [PASSED] xe_rtp_process_tests ===============
[05:41:40] ===================== [PASSED] xe_rtp ======================
[05:41:40] ==================== xe_wa (1 subtest) =====================
[05:41:40] ======================== xe_wa_gt =========================
[05:41:40] [PASSED] TIGERLAKE B0
[05:41:40] [PASSED] DG1 A0
[05:41:40] [PASSED] DG1 B0
[05:41:40] [PASSED] ALDERLAKE_S A0
[05:41:40] [PASSED] ALDERLAKE_S B0
[05:41:40] [PASSED] ALDERLAKE_S C0
[05:41:40] [PASSED] ALDERLAKE_S D0
[05:41:40] [PASSED] ALDERLAKE_P A0
[05:41:40] [PASSED] ALDERLAKE_P B0
[05:41:40] [PASSED] ALDERLAKE_P C0
[05:41:40] [PASSED] ALDERLAKE_S RPLS D0
[05:41:40] [PASSED] ALDERLAKE_P RPLU E0
[05:41:40] [PASSED] DG2 G10 C0
[05:41:40] [PASSED] DG2 G11 B1
[05:41:40] [PASSED] DG2 G12 A1
[05:41:40] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:41:40] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:41:40] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[05:41:40] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[05:41:40] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[05:41:40] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[05:41:40] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[05:41:40] ==================== [PASSED] xe_wa_gt =====================
[05:41:40] ====================== [PASSED] xe_wa ======================
[05:41:40] ============================================================
[05:41:40] Testing complete. Ran 741 tests: passed: 723, skipped: 18
[05:41:40] Elapsed time: 36.599s total, 4.262s configuring, 31.672s building, 0.637s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[05:41:40] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:41:42] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:42:06] Starting KUnit Kernel (1/1)...
[05:42:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:42:07] ============ drm_test_pick_cmdline (2 subtests) ============
[05:42:07] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[05:42:07] =============== drm_test_pick_cmdline_named ===============
[05:42:07] [PASSED] NTSC
[05:42:07] [PASSED] NTSC-J
[05:42:07] [PASSED] PAL
[05:42:07] [PASSED] PAL-M
[05:42:07] =========== [PASSED] drm_test_pick_cmdline_named ===========
[05:42:07] ============== [PASSED] drm_test_pick_cmdline ==============
[05:42:07] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[05:42:07] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[05:42:07] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[05:42:07] =========== drm_validate_clone_mode (2 subtests) ===========
[05:42:07] ============== drm_test_check_in_clone_mode ===============
[05:42:07] [PASSED] in_clone_mode
[05:42:07] [PASSED] not_in_clone_mode
[05:42:07] ========== [PASSED] drm_test_check_in_clone_mode ===========
[05:42:07] =============== drm_test_check_valid_clones ===============
[05:42:07] [PASSED] not_in_clone_mode
[05:42:07] [PASSED] valid_clone
[05:42:07] [PASSED] invalid_clone
[05:42:07] =========== [PASSED] drm_test_check_valid_clones ===========
[05:42:07] ============= [PASSED] drm_validate_clone_mode =============
[05:42:07] ============= drm_validate_modeset (1 subtest) =============
[05:42:07] [PASSED] drm_test_check_connector_changed_modeset
[05:42:07] ============== [PASSED] drm_validate_modeset ===============
[05:42:07] ====== drm_test_bridge_get_current_state (1 subtest) =======
[05:42:07] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[05:42:07] ======== [PASSED] drm_test_bridge_get_current_state ========
[05:42:07] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[05:42:07] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[05:42:07] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[05:42:07] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[05:42:07] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[05:42:07] ============== drm_bridge_alloc (2 subtests) ===============
[05:42:07] [PASSED] drm_test_drm_bridge_alloc_basic
[05:42:07] [PASSED] drm_test_drm_bridge_alloc_get_put
[05:42:07] ================ [PASSED] drm_bridge_alloc =================
[05:42:07] ============= drm_bridge_bus_fmt (5 subtests) ==============
[05:42:07] [PASSED] drm_test_bridge_rgb_yuv_rgb
[05:42:07] [PASSED] drm_test_bridge_must_convert_to_yuv444
[05:42:07] [PASSED] drm_test_bridge_hdmi_auto_rgb
[05:42:07] [PASSED] drm_test_bridge_auto_first
[05:42:07] [PASSED] drm_test_bridge_rgb_yuv_no_path
[05:42:07] =============== [PASSED] drm_bridge_bus_fmt ================
[05:42:07] ============= drm_cmdline_parser (40 subtests) =============
[05:42:07] [PASSED] drm_test_cmdline_force_d_only
[05:42:07] [PASSED] drm_test_cmdline_force_D_only_dvi
[05:42:07] [PASSED] drm_test_cmdline_force_D_only_hdmi
[05:42:07] [PASSED] drm_test_cmdline_force_D_only_not_digital
[05:42:07] [PASSED] drm_test_cmdline_force_e_only
[05:42:07] [PASSED] drm_test_cmdline_res
[05:42:07] [PASSED] drm_test_cmdline_res_vesa
[05:42:07] [PASSED] drm_test_cmdline_res_vesa_rblank
[05:42:07] [PASSED] drm_test_cmdline_res_rblank
[05:42:07] [PASSED] drm_test_cmdline_res_bpp
[05:42:07] [PASSED] drm_test_cmdline_res_refresh
[05:42:07] [PASSED] drm_test_cmdline_res_bpp_refresh
[05:42:07] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[05:42:07] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[05:42:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[05:42:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[05:42:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[05:42:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[05:42:07] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[05:42:07] [PASSED] drm_test_cmdline_res_margins_force_on
[05:42:07] [PASSED] drm_test_cmdline_res_vesa_margins
[05:42:07] [PASSED] drm_test_cmdline_name
[05:42:07] [PASSED] drm_test_cmdline_name_bpp
[05:42:07] [PASSED] drm_test_cmdline_name_option
[05:42:07] [PASSED] drm_test_cmdline_name_bpp_option
[05:42:07] [PASSED] drm_test_cmdline_rotate_0
[05:42:07] [PASSED] drm_test_cmdline_rotate_90
[05:42:07] [PASSED] drm_test_cmdline_rotate_180
[05:42:07] [PASSED] drm_test_cmdline_rotate_270
[05:42:07] [PASSED] drm_test_cmdline_hmirror
[05:42:07] [PASSED] drm_test_cmdline_vmirror
[05:42:07] [PASSED] drm_test_cmdline_margin_options
[05:42:07] [PASSED] drm_test_cmdline_multiple_options
[05:42:07] [PASSED] drm_test_cmdline_bpp_extra_and_option
[05:42:07] [PASSED] drm_test_cmdline_extra_and_option
[05:42:07] [PASSED] drm_test_cmdline_freestanding_options
[05:42:07] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[05:42:07] [PASSED] drm_test_cmdline_panel_orientation
[05:42:07] ================ drm_test_cmdline_invalid =================
[05:42:07] [PASSED] margin_only
[05:42:07] [PASSED] interlace_only
[05:42:07] [PASSED] res_missing_x
[05:42:07] [PASSED] res_missing_y
[05:42:07] [PASSED] res_bad_y
[05:42:07] [PASSED] res_missing_y_bpp
[05:42:07] [PASSED] res_bad_bpp
[05:42:07] [PASSED] res_bad_refresh
[05:42:07] [PASSED] res_bpp_refresh_force_on_off
[05:42:07] [PASSED] res_invalid_mode
[05:42:07] [PASSED] res_bpp_wrong_place_mode
[05:42:07] [PASSED] name_bpp_refresh
[05:42:07] [PASSED] name_refresh
[05:42:07] [PASSED] name_refresh_wrong_mode
[05:42:07] [PASSED] name_refresh_invalid_mode
[05:42:07] [PASSED] rotate_multiple
[05:42:07] [PASSED] rotate_invalid_val
[05:42:07] [PASSED] rotate_truncated
[05:42:07] [PASSED] invalid_option
[05:42:07] [PASSED] invalid_tv_option
[05:42:07] [PASSED] truncated_tv_option
[05:42:07] ============ [PASSED] drm_test_cmdline_invalid =============
[05:42:07] =============== drm_test_cmdline_tv_options ===============
[05:42:07] [PASSED] NTSC
[05:42:07] [PASSED] NTSC_443
[05:42:07] [PASSED] NTSC_J
[05:42:07] [PASSED] PAL
[05:42:07] [PASSED] PAL_M
[05:42:07] [PASSED] PAL_N
[05:42:07] [PASSED] SECAM
[05:42:07] [PASSED] MONO_525
[05:42:07] [PASSED] MONO_625
[05:42:07] =========== [PASSED] drm_test_cmdline_tv_options ===========
[05:42:07] =============== [PASSED] drm_cmdline_parser ================
[05:42:07] ========== drmm_connector_hdmi_init (20 subtests) ==========
[05:42:07] [PASSED] drm_test_connector_hdmi_init_valid
[05:42:07] [PASSED] drm_test_connector_hdmi_init_bpc_8
[05:42:07] [PASSED] drm_test_connector_hdmi_init_bpc_10
[05:42:07] [PASSED] drm_test_connector_hdmi_init_bpc_12
[05:42:07] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[05:42:07] [PASSED] drm_test_connector_hdmi_init_bpc_null
[05:42:07] [PASSED] drm_test_connector_hdmi_init_formats_empty
[05:42:07] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[05:42:07] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[05:42:07] [PASSED] supported_formats=0x9 yuv420_allowed=1
[05:42:07] [PASSED] supported_formats=0x9 yuv420_allowed=0
[05:42:07] [PASSED] supported_formats=0x5 yuv420_allowed=1
[05:42:07] [PASSED] supported_formats=0x5 yuv420_allowed=0
[05:42:07] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[05:42:07] [PASSED] drm_test_connector_hdmi_init_null_ddc
[05:42:07] [PASSED] drm_test_connector_hdmi_init_null_product
[05:42:07] [PASSED] drm_test_connector_hdmi_init_null_vendor
[05:42:07] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[05:42:07] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[05:42:07] [PASSED] drm_test_connector_hdmi_init_product_valid
[05:42:07] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[05:42:07] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[05:42:07] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[05:42:07] ========= drm_test_connector_hdmi_init_type_valid =========
[05:42:07] [PASSED] HDMI-A
[05:42:07] [PASSED] HDMI-B
[05:42:07] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[05:42:07] ======== drm_test_connector_hdmi_init_type_invalid ========
[05:42:07] [PASSED] Unknown
[05:42:07] [PASSED] VGA
[05:42:07] [PASSED] DVI-I
[05:42:07] [PASSED] DVI-D
[05:42:07] [PASSED] DVI-A
[05:42:07] [PASSED] Composite
[05:42:07] [PASSED] SVIDEO
[05:42:07] [PASSED] LVDS
[05:42:07] [PASSED] Component
[05:42:07] [PASSED] DIN
[05:42:07] [PASSED] DP
[05:42:07] [PASSED] TV
[05:42:07] [PASSED] eDP
[05:42:07] [PASSED] Virtual
[05:42:07] [PASSED] DSI
[05:42:07] [PASSED] DPI
[05:42:07] [PASSED] Writeback
[05:42:07] [PASSED] SPI
[05:42:07] [PASSED] USB
[05:42:07] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[05:42:07] ============ [PASSED] drmm_connector_hdmi_init =============
[05:42:07] ============= drmm_connector_init (3 subtests) =============
[05:42:07] [PASSED] drm_test_drmm_connector_init
[05:42:07] [PASSED] drm_test_drmm_connector_init_null_ddc
[05:42:07] ========= drm_test_drmm_connector_init_type_valid =========
[05:42:07] [PASSED] Unknown
[05:42:07] [PASSED] VGA
[05:42:07] [PASSED] DVI-I
[05:42:07] [PASSED] DVI-D
[05:42:07] [PASSED] DVI-A
[05:42:07] [PASSED] Composite
[05:42:07] [PASSED] SVIDEO
[05:42:07] [PASSED] LVDS
[05:42:07] [PASSED] Component
[05:42:07] [PASSED] DIN
[05:42:07] [PASSED] DP
[05:42:07] [PASSED] HDMI-A
[05:42:07] [PASSED] HDMI-B
[05:42:07] [PASSED] TV
[05:42:07] [PASSED] eDP
[05:42:07] [PASSED] Virtual
[05:42:07] [PASSED] DSI
[05:42:07] [PASSED] DPI
[05:42:07] [PASSED] Writeback
[05:42:07] [PASSED] SPI
[05:42:07] [PASSED] USB
[05:42:07] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[05:42:07] =============== [PASSED] drmm_connector_init ===============
[05:42:07] ========= drm_connector_dynamic_init (6 subtests) ==========
[05:42:07] [PASSED] drm_test_drm_connector_dynamic_init
[05:42:07] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[05:42:07] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[05:42:07] [PASSED] drm_test_drm_connector_dynamic_init_properties
[05:42:07] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[05:42:07] [PASSED] Unknown
[05:42:07] [PASSED] VGA
[05:42:07] [PASSED] DVI-I
[05:42:07] [PASSED] DVI-D
[05:42:07] [PASSED] DVI-A
[05:42:07] [PASSED] Composite
[05:42:07] [PASSED] SVIDEO
[05:42:07] [PASSED] LVDS
[05:42:07] [PASSED] Component
[05:42:07] [PASSED] DIN
[05:42:07] [PASSED] DP
[05:42:07] [PASSED] HDMI-A
[05:42:07] [PASSED] HDMI-B
[05:42:07] [PASSED] TV
[05:42:07] [PASSED] eDP
[05:42:07] [PASSED] Virtual
[05:42:07] [PASSED] DSI
[05:42:07] [PASSED] DPI
[05:42:07] [PASSED] Writeback
[05:42:07] [PASSED] SPI
[05:42:07] [PASSED] USB
[05:42:07] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[05:42:07] ======== drm_test_drm_connector_dynamic_init_name =========
[05:42:07] [PASSED] Unknown
[05:42:07] [PASSED] VGA
[05:42:07] [PASSED] DVI-I
[05:42:07] [PASSED] DVI-D
[05:42:07] [PASSED] DVI-A
[05:42:07] [PASSED] Composite
[05:42:07] [PASSED] SVIDEO
[05:42:07] [PASSED] LVDS
[05:42:07] [PASSED] Component
[05:42:07] [PASSED] DIN
[05:42:07] [PASSED] DP
[05:42:07] [PASSED] HDMI-A
[05:42:07] [PASSED] HDMI-B
[05:42:07] [PASSED] TV
[05:42:07] [PASSED] eDP
[05:42:07] [PASSED] Virtual
[05:42:07] [PASSED] DSI
[05:42:07] [PASSED] DPI
[05:42:07] [PASSED] Writeback
[05:42:07] [PASSED] SPI
[05:42:07] [PASSED] USB
[05:42:07] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[05:42:07] =========== [PASSED] drm_connector_dynamic_init ============
[05:42:07] ==== drm_connector_dynamic_register_early (4 subtests) =====
[05:42:07] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[05:42:07] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[05:42:07] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[05:42:07] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[05:42:07] ====== [PASSED] drm_connector_dynamic_register_early =======
[05:42:07] ======= drm_connector_dynamic_register (7 subtests) ========
[05:42:07] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[05:42:07] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[05:42:07] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[05:42:07] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[05:42:07] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[05:42:07] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[05:42:07] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[05:42:07] ========= [PASSED] drm_connector_dynamic_register ==========
[05:42:07] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[05:42:07] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[05:42:07] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[05:42:07] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[05:42:07] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[05:42:07] ========== drm_test_get_tv_mode_from_name_valid ===========
[05:42:07] [PASSED] NTSC
[05:42:07] [PASSED] NTSC-443
[05:42:07] [PASSED] NTSC-J
[05:42:07] [PASSED] PAL
[05:42:07] [PASSED] PAL-M
[05:42:07] [PASSED] PAL-N
[05:42:07] [PASSED] SECAM
[05:42:07] [PASSED] Mono
[05:42:07] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[05:42:07] [PASSED] drm_test_get_tv_mode_from_name_truncated
[05:42:07] ============ [PASSED] drm_get_tv_mode_from_name ============
[05:42:07] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[05:42:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[05:42:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[05:42:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[05:42:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[05:42:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[05:42:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[05:42:07] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[05:42:07] [PASSED] VIC 96
[05:42:07] [PASSED] VIC 97
[05:42:07] [PASSED] VIC 101
[05:42:07] [PASSED] VIC 102
[05:42:07] [PASSED] VIC 106
[05:42:07] [PASSED] VIC 107
[05:42:07] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[05:42:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[05:42:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[05:42:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[05:42:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[05:42:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[05:42:07] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[05:42:07] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[05:42:07] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[05:42:07] [PASSED] Automatic
[05:42:07] [PASSED] Full
[05:42:07] [PASSED] Limited 16:235
[05:42:07] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[05:42:07] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[05:42:07] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[05:42:07] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[05:42:07] === drm_test_drm_hdmi_connector_get_output_format_name ====
[05:42:07] [PASSED] RGB
[05:42:07] [PASSED] YUV 4:2:0
[05:42:07] [PASSED] YUV 4:2:2
[05:42:07] [PASSED] YUV 4:4:4
[05:42:07] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[05:42:07] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[05:42:07] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[05:42:07] ============= drm_damage_helper (21 subtests) ==============
[05:42:07] [PASSED] drm_test_damage_iter_no_damage
[05:42:07] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[05:42:07] [PASSED] drm_test_damage_iter_no_damage_src_moved
[05:42:07] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[05:42:07] [PASSED] drm_test_damage_iter_no_damage_not_visible
[05:42:07] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[05:42:07] [PASSED] drm_test_damage_iter_no_damage_no_fb
[05:42:07] [PASSED] drm_test_damage_iter_simple_damage
[05:42:07] [PASSED] drm_test_damage_iter_single_damage
[05:42:07] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[05:42:07] [PASSED] drm_test_damage_iter_single_damage_outside_src
[05:42:07] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[05:42:07] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[05:42:07] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[05:42:07] [PASSED] drm_test_damage_iter_single_damage_src_moved
[05:42:07] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[05:42:07] [PASSED] drm_test_damage_iter_damage
[05:42:07] [PASSED] drm_test_damage_iter_damage_one_intersect
[05:42:07] [PASSED] drm_test_damage_iter_damage_one_outside
[05:42:07] [PASSED] drm_test_damage_iter_damage_src_moved
[05:42:07] [PASSED] drm_test_damage_iter_damage_not_visible
[05:42:07] ================ [PASSED] drm_damage_helper ================
[05:42:07] ============== drm_dp_mst_helper (3 subtests) ==============
[05:42:07] ============== drm_test_dp_mst_calc_pbn_mode ==============
[05:42:07] [PASSED] Clock 154000 BPP 30 DSC disabled
[05:42:07] [PASSED] Clock 234000 BPP 30 DSC disabled
[05:42:07] [PASSED] Clock 297000 BPP 24 DSC disabled
[05:42:07] [PASSED] Clock 332880 BPP 24 DSC enabled
[05:42:07] [PASSED] Clock 324540 BPP 24 DSC enabled
[05:42:07] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[05:42:07] ============== drm_test_dp_mst_calc_pbn_div ===============
[05:42:07] [PASSED] Link rate 2000000 lane count 4
[05:42:07] [PASSED] Link rate 2000000 lane count 2
[05:42:07] [PASSED] Link rate 2000000 lane count 1
[05:42:07] [PASSED] Link rate 1350000 lane count 4
[05:42:07] [PASSED] Link rate 1350000 lane count 2
[05:42:07] [PASSED] Link rate 1350000 lane count 1
[05:42:07] [PASSED] Link rate 1000000 lane count 4
[05:42:07] [PASSED] Link rate 1000000 lane count 2
[05:42:07] [PASSED] Link rate 1000000 lane count 1
[05:42:07] [PASSED] Link rate 810000 lane count 4
[05:42:07] [PASSED] Link rate 810000 lane count 2
[05:42:07] [PASSED] Link rate 810000 lane count 1
[05:42:07] [PASSED] Link rate 540000 lane count 4
[05:42:07] [PASSED] Link rate 540000 lane count 2
[05:42:07] [PASSED] Link rate 540000 lane count 1
[05:42:07] [PASSED] Link rate 270000 lane count 4
[05:42:07] [PASSED] Link rate 270000 lane count 2
[05:42:07] [PASSED] Link rate 270000 lane count 1
[05:42:07] [PASSED] Link rate 162000 lane count 4
[05:42:07] [PASSED] Link rate 162000 lane count 2
[05:42:07] [PASSED] Link rate 162000 lane count 1
[05:42:07] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[05:42:07] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[05:42:07] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[05:42:07] [PASSED] DP_POWER_UP_PHY with port number
[05:42:07] [PASSED] DP_POWER_DOWN_PHY with port number
[05:42:07] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[05:42:07] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[05:42:07] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[05:42:07] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[05:42:07] [PASSED] DP_QUERY_PAYLOAD with port number
[05:42:07] [PASSED] DP_QUERY_PAYLOAD with VCPI
[05:42:07] [PASSED] DP_REMOTE_DPCD_READ with port number
[05:42:07] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[05:42:07] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[05:42:07] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[05:42:07] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[05:42:07] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[05:42:07] [PASSED] DP_REMOTE_I2C_READ with port number
[05:42:07] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[05:42:07] [PASSED] DP_REMOTE_I2C_READ with transactions array
[05:42:07] [PASSED] DP_REMOTE_I2C_WRITE with port number
[05:42:07] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[05:42:07] [PASSED] DP_REMOTE_I2C_WRITE with data array
[05:42:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[05:42:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[05:42:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[05:42:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[05:42:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[05:42:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[05:42:07] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[05:42:07] ================ [PASSED] drm_dp_mst_helper ================
[05:42:07] ================== drm_exec (7 subtests) ===================
[05:42:07] [PASSED] sanitycheck
[05:42:07] [PASSED] test_lock
[05:42:07] [PASSED] test_lock_unlock
[05:42:07] [PASSED] test_duplicates
[05:42:07] [PASSED] test_prepare
[05:42:07] [PASSED] test_prepare_array
[05:42:07] [PASSED] test_multiple_loops
[05:42:07] ==================== [PASSED] drm_exec =====================
[05:42:07] =========== drm_format_helper_test (17 subtests) ===========
[05:42:07] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[05:42:07] [PASSED] single_pixel_source_buffer
[05:42:07] [PASSED] single_pixel_clip_rectangle
[05:42:07] [PASSED] well_known_colors
[05:42:07] [PASSED] destination_pitch
[05:42:07] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[05:42:07] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[05:42:07] [PASSED] single_pixel_source_buffer
[05:42:07] [PASSED] single_pixel_clip_rectangle
[05:42:07] [PASSED] well_known_colors
[05:42:07] [PASSED] destination_pitch
[05:42:07] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[05:42:07] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[05:42:07] [PASSED] single_pixel_source_buffer
[05:42:07] [PASSED] single_pixel_clip_rectangle
[05:42:07] [PASSED] well_known_colors
[05:42:07] [PASSED] destination_pitch
[05:42:07] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[05:42:07] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[05:42:07] [PASSED] single_pixel_source_buffer
[05:42:07] [PASSED] single_pixel_clip_rectangle
[05:42:07] [PASSED] well_known_colors
[05:42:07] [PASSED] destination_pitch
[05:42:07] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[05:42:07] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[05:42:07] [PASSED] single_pixel_source_buffer
[05:42:07] [PASSED] single_pixel_clip_rectangle
[05:42:07] [PASSED] well_known_colors
[05:42:07] [PASSED] destination_pitch
[05:42:07] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[05:42:07] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[05:42:07] [PASSED] single_pixel_source_buffer
[05:42:07] [PASSED] single_pixel_clip_rectangle
[05:42:07] [PASSED] well_known_colors
[05:42:07] [PASSED] destination_pitch
[05:42:07] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[05:42:07] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[05:42:07] [PASSED] single_pixel_source_buffer
[05:42:07] [PASSED] single_pixel_clip_rectangle
[05:42:07] [PASSED] well_known_colors
[05:42:07] [PASSED] destination_pitch
[05:42:07] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[05:42:07] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[05:42:07] [PASSED] single_pixel_source_buffer
[05:42:07] [PASSED] single_pixel_clip_rectangle
[05:42:07] [PASSED] well_known_colors
[05:42:07] [PASSED] destination_pitch
[05:42:07] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[05:42:07] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[05:42:07] [PASSED] single_pixel_source_buffer
[05:42:07] [PASSED] single_pixel_clip_rectangle
[05:42:07] [PASSED] well_known_colors
[05:42:07] [PASSED] destination_pitch
[05:42:07] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[05:42:07] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[05:42:07] [PASSED] single_pixel_source_buffer
[05:42:07] [PASSED] single_pixel_clip_rectangle
[05:42:07] [PASSED] well_known_colors
[05:42:07] [PASSED] destination_pitch
[05:42:07] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[05:42:07] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[05:42:07] [PASSED] single_pixel_source_buffer
[05:42:07] [PASSED] single_pixel_clip_rectangle
[05:42:07] [PASSED] well_known_colors
[05:42:07] [PASSED] destination_pitch
[05:42:07] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[05:42:07] ============== drm_test_fb_xrgb8888_to_mono ===============
[05:42:07] [PASSED] single_pixel_source_buffer
[05:42:07] [PASSED] single_pixel_clip_rectangle
[05:42:07] [PASSED] well_known_colors
[05:42:07] [PASSED] destination_pitch
[05:42:07] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[05:42:07] ==================== drm_test_fb_swab =====================
[05:42:07] [PASSED] single_pixel_source_buffer
[05:42:07] [PASSED] single_pixel_clip_rectangle
[05:42:07] [PASSED] well_known_colors
[05:42:07] [PASSED] destination_pitch
[05:42:07] ================ [PASSED] drm_test_fb_swab =================
[05:42:07] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[05:42:07] [PASSED] single_pixel_source_buffer
[05:42:07] [PASSED] single_pixel_clip_rectangle
[05:42:07] [PASSED] well_known_colors
[05:42:07] [PASSED] destination_pitch
[05:42:07] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[05:42:07] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[05:42:07] [PASSED] single_pixel_source_buffer
[05:42:07] [PASSED] single_pixel_clip_rectangle
[05:42:07] [PASSED] well_known_colors
[05:42:07] [PASSED] destination_pitch
[05:42:07] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[05:42:07] ================= drm_test_fb_clip_offset =================
[05:42:07] [PASSED] pass through
[05:42:07] [PASSED] horizontal offset
[05:42:07] [PASSED] vertical offset
[05:42:07] [PASSED] horizontal and vertical offset
[05:42:07] [PASSED] horizontal offset (custom pitch)
[05:42:07] [PASSED] vertical offset (custom pitch)
[05:42:07] [PASSED] horizontal and vertical offset (custom pitch)
[05:42:07] ============= [PASSED] drm_test_fb_clip_offset =============
[05:42:07] =================== drm_test_fb_memcpy ====================
[05:42:07] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[05:42:07] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[05:42:07] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[05:42:07] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[05:42:07] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[05:42:07] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[05:42:07] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[05:42:07] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[05:42:07] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[05:42:07] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[05:42:07] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[05:42:07] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[05:42:07] =============== [PASSED] drm_test_fb_memcpy ================
[05:42:07] ============= [PASSED] drm_format_helper_test ==============
[05:42:07] ================= drm_format (18 subtests) =================
[05:42:07] [PASSED] drm_test_format_block_width_invalid
[05:42:07] [PASSED] drm_test_format_block_width_one_plane
[05:42:07] [PASSED] drm_test_format_block_width_two_plane
[05:42:07] [PASSED] drm_test_format_block_width_three_plane
[05:42:07] [PASSED] drm_test_format_block_width_tiled
[05:42:07] [PASSED] drm_test_format_block_height_invalid
[05:42:07] [PASSED] drm_test_format_block_height_one_plane
[05:42:07] [PASSED] drm_test_format_block_height_two_plane
[05:42:07] [PASSED] drm_test_format_block_height_three_plane
[05:42:07] [PASSED] drm_test_format_block_height_tiled
[05:42:07] [PASSED] drm_test_format_min_pitch_invalid
[05:42:07] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[05:42:07] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[05:42:07] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[05:42:07] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[05:42:07] [PASSED] drm_test_format_min_pitch_two_plane
[05:42:07] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[05:42:07] [PASSED] drm_test_format_min_pitch_tiled
[05:42:07] =================== [PASSED] drm_format ====================
[05:42:07] ============== drm_framebuffer (10 subtests) ===============
[05:42:07] ========== drm_test_framebuffer_check_src_coords ==========
[05:42:07] [PASSED] Success: source fits into fb
[05:42:07] [PASSED] Fail: overflowing fb with x-axis coordinate
[05:42:07] [PASSED] Fail: overflowing fb with y-axis coordinate
[05:42:07] [PASSED] Fail: overflowing fb with source width
[05:42:07] [PASSED] Fail: overflowing fb with source height
[05:42:07] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[05:42:07] [PASSED] drm_test_framebuffer_cleanup
[05:42:07] =============== drm_test_framebuffer_create ===============
[05:42:07] [PASSED] ABGR8888 normal sizes
[05:42:07] [PASSED] ABGR8888 max sizes
[05:42:07] [PASSED] ABGR8888 pitch greater than min required
[05:42:07] [PASSED] ABGR8888 pitch less than min required
[05:42:07] [PASSED] ABGR8888 Invalid width
[05:42:07] [PASSED] ABGR8888 Invalid buffer handle
[05:42:07] [PASSED] No pixel format
[05:42:07] [PASSED] ABGR8888 Width 0
[05:42:07] [PASSED] ABGR8888 Height 0
[05:42:07] [PASSED] ABGR8888 Out of bound height * pitch combination
[05:42:07] [PASSED] ABGR8888 Large buffer offset
[05:42:07] [PASSED] ABGR8888 Buffer offset for inexistent plane
[05:42:07] [PASSED] ABGR8888 Invalid flag
[05:42:07] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[05:42:07] [PASSED] ABGR8888 Valid buffer modifier
[05:42:07] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[05:42:07] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[05:42:07] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[05:42:07] [PASSED] NV12 Normal sizes
[05:42:07] [PASSED] NV12 Max sizes
[05:42:07] [PASSED] NV12 Invalid pitch
[05:42:07] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[05:42:07] [PASSED] NV12 different modifier per-plane
[05:42:07] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[05:42:07] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[05:42:07] [PASSED] NV12 Modifier for inexistent plane
[05:42:07] [PASSED] NV12 Handle for inexistent plane
[05:42:07] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[05:42:07] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[05:42:07] [PASSED] YVU420 Normal sizes
[05:42:07] [PASSED] YVU420 Max sizes
[05:42:07] [PASSED] YVU420 Invalid pitch
[05:42:07] [PASSED] YVU420 Different pitches
[05:42:07] [PASSED] YVU420 Different buffer offsets/pitches
[05:42:07] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[05:42:07] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[05:42:07] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[05:42:07] [PASSED] YVU420 Valid modifier
[05:42:07] [PASSED] YVU420 Different modifiers per plane
[05:42:07] [PASSED] YVU420 Modifier for inexistent plane
[05:42:07] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[05:42:07] [PASSED] X0L2 Normal sizes
[05:42:07] [PASSED] X0L2 Max sizes
[05:42:07] [PASSED] X0L2 Invalid pitch
[05:42:07] [PASSED] X0L2 Pitch greater than minimum required
[05:42:07] [PASSED] X0L2 Handle for inexistent plane
[05:42:07] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[05:42:07] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[05:42:07] [PASSED] X0L2 Valid modifier
[05:42:07] [PASSED] X0L2 Modifier for inexistent plane
[05:42:07] =========== [PASSED] drm_test_framebuffer_create ===========
[05:42:07] [PASSED] drm_test_framebuffer_free
[05:42:07] [PASSED] drm_test_framebuffer_init
[05:42:07] [PASSED] drm_test_framebuffer_init_bad_format
[05:42:07] [PASSED] drm_test_framebuffer_init_dev_mismatch
[05:42:07] [PASSED] drm_test_framebuffer_lookup
[05:42:07] [PASSED] drm_test_framebuffer_lookup_inexistent
[05:42:07] [PASSED] drm_test_framebuffer_modifiers_not_supported
[05:42:07] ================= [PASSED] drm_framebuffer =================
[05:42:07] ================ drm_gem_shmem (8 subtests) ================
[05:42:07] [PASSED] drm_gem_shmem_test_obj_create
[05:42:07] [PASSED] drm_gem_shmem_test_obj_create_private
[05:42:07] [PASSED] drm_gem_shmem_test_pin_pages
[05:42:07] [PASSED] drm_gem_shmem_test_vmap
[05:42:07] [PASSED] drm_gem_shmem_test_get_sg_table
[05:42:07] [PASSED] drm_gem_shmem_test_get_pages_sgt
[05:42:07] [PASSED] drm_gem_shmem_test_madvise
[05:42:07] [PASSED] drm_gem_shmem_test_purge
[05:42:07] ================== [PASSED] drm_gem_shmem ==================
[05:42:07] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[05:42:07] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[05:42:07] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[05:42:07] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[05:42:07] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[05:42:07] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[05:42:07] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[05:42:07] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[05:42:07] [PASSED] Automatic
[05:42:07] [PASSED] Full
[05:42:07] [PASSED] Limited 16:235
[05:42:07] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[05:42:07] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[05:42:07] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[05:42:07] [PASSED] drm_test_check_disable_connector
[05:42:07] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[05:42:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[05:42:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[05:42:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[05:42:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[05:42:07] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[05:42:07] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[05:42:07] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[05:42:07] [PASSED] drm_test_check_output_bpc_dvi
[05:42:07] [PASSED] drm_test_check_output_bpc_format_vic_1
[05:42:07] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[05:42:07] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[05:42:07] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[05:42:07] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[05:42:07] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[05:42:07] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[05:42:07] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[05:42:07] ============ drm_test_check_hdmi_color_format =============
[05:42:07] [PASSED] AUTO -> RGB
[05:42:07] [PASSED] YCBCR422 -> YUV422
[05:42:07] [PASSED] YCBCR420 -> YUV420
[05:42:07] [PASSED] YCBCR444 -> YUV444
[05:42:07] [PASSED] RGB -> RGB
[05:42:07] ======== [PASSED] drm_test_check_hdmi_color_format =========
[05:42:07] ======== drm_test_check_hdmi_color_format_420_only ========
[05:42:07] [PASSED] RGB should fail
[05:42:07] [PASSED] YUV444 should fail
[05:42:07] [PASSED] YUV422 should fail
[05:42:07] [PASSED] YUV420 should work
[05:42:07] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[05:42:07] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[05:42:07] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[05:42:07] [PASSED] drm_test_check_broadcast_rgb_value
[05:42:07] [PASSED] drm_test_check_bpc_8_value
[05:42:07] [PASSED] drm_test_check_bpc_10_value
[05:42:07] [PASSED] drm_test_check_bpc_12_value
[05:42:07] [PASSED] drm_test_check_format_value
[05:42:07] [PASSED] drm_test_check_tmds_char_value
[05:42:07] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[05:42:07] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[05:42:07] [PASSED] drm_test_check_mode_valid
[05:42:07] [PASSED] drm_test_check_mode_valid_reject
[05:42:07] [PASSED] drm_test_check_mode_valid_reject_rate
[05:42:07] [PASSED] drm_test_check_mode_valid_reject_max_clock
[05:42:07] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[05:42:07] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[05:42:07] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[05:42:07] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[05:42:07] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[05:42:07] [PASSED] drm_test_check_infoframes
[05:42:07] [PASSED] drm_test_check_reject_avi_infoframe
[05:42:07] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[05:42:07] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[05:42:07] [PASSED] drm_test_check_reject_audio_infoframe
[05:42:07] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[05:42:07] ================= drm_managed (2 subtests) =================
[05:42:07] [PASSED] drm_test_managed_release_action
[05:42:07] [PASSED] drm_test_managed_run_action
[05:42:07] =================== [PASSED] drm_managed ===================
[05:42:07] =================== drm_mm (6 subtests) ====================
[05:42:07] [PASSED] drm_test_mm_init
[05:42:07] [PASSED] drm_test_mm_debug
[05:42:07] [PASSED] drm_test_mm_align32
[05:42:07] [PASSED] drm_test_mm_align64
[05:42:07] [PASSED] drm_test_mm_lowest
[05:42:07] [PASSED] drm_test_mm_highest
[05:42:07] ===================== [PASSED] drm_mm ======================
[05:42:07] ============= drm_modes_analog_tv (5 subtests) =============
[05:42:07] [PASSED] drm_test_modes_analog_tv_mono_576i
[05:42:07] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[05:42:07] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[05:42:07] [PASSED] drm_test_modes_analog_tv_pal_576i
[05:42:07] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[05:42:07] =============== [PASSED] drm_modes_analog_tv ===============
[05:42:07] ============== drm_plane_helper (2 subtests) ===============
[05:42:07] =============== drm_test_check_plane_state ================
[05:42:07] [PASSED] clipping_simple
[05:42:07] [PASSED] clipping_rotate_reflect
[05:42:07] [PASSED] positioning_simple
[05:42:07] [PASSED] upscaling
[05:42:07] [PASSED] downscaling
[05:42:07] [PASSED] rounding1
[05:42:07] [PASSED] rounding2
[05:42:07] [PASSED] rounding3
[05:42:07] [PASSED] rounding4
[05:42:07] =========== [PASSED] drm_test_check_plane_state ============
[05:42:07] =========== drm_test_check_invalid_plane_state ============
[05:42:07] [PASSED] positioning_invalid
[05:42:07] [PASSED] upscaling_invalid
[05:42:07] [PASSED] downscaling_invalid
[05:42:07] ======= [PASSED] drm_test_check_invalid_plane_state ========
[05:42:07] ================ [PASSED] drm_plane_helper =================
[05:42:07] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[05:42:07] ====== drm_test_connector_helper_tv_get_modes_check =======
[05:42:07] [PASSED] None
[05:42:07] [PASSED] PAL
[05:42:07] [PASSED] NTSC
[05:42:07] [PASSED] Both, NTSC Default
[05:42:07] [PASSED] Both, PAL Default
[05:42:07] [PASSED] Both, NTSC Default, with PAL on command-line
[05:42:07] [PASSED] Both, PAL Default, with NTSC on command-line
[05:42:07] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[05:42:07] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[05:42:07] ================== drm_rect (9 subtests) ===================
[05:42:07] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[05:42:07] [PASSED] drm_test_rect_clip_scaled_not_clipped
[05:42:07] [PASSED] drm_test_rect_clip_scaled_clipped
[05:42:07] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[05:42:07] ================= drm_test_rect_intersect =================
[05:42:07] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[05:42:07] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[05:42:07] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[05:42:07] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[05:42:07] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[05:42:07] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[05:42:07] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[05:42:07] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[05:42:07] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[05:42:07] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[05:42:07] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[05:42:07] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[05:42:07] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[05:42:07] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[05:42:07] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[05:42:07] ============= [PASSED] drm_test_rect_intersect =============
[05:42:07] ================ drm_test_rect_calc_hscale ================
[05:42:07] [PASSED] normal use
[05:42:07] [PASSED] out of max range
[05:42:07] [PASSED] out of min range
[05:42:07] [PASSED] zero dst
[05:42:07] [PASSED] negative src
[05:42:07] [PASSED] negative dst
[05:42:07] ============ [PASSED] drm_test_rect_calc_hscale ============
[05:42:07] ================ drm_test_rect_calc_vscale ================
[05:42:07] [PASSED] normal use
[05:42:07] [PASSED] out of max range
[05:42:07] [PASSED] out of min range
[05:42:07] [PASSED] zero dst
[05:42:07] [PASSED] negative src
[05:42:07] [PASSED] negative dst
[05:42:07] ============ [PASSED] drm_test_rect_calc_vscale ============
[05:42:07] ================== drm_test_rect_rotate ===================
[05:42:07] [PASSED] reflect-x
[05:42:07] [PASSED] reflect-y
[05:42:07] [PASSED] rotate-0
[05:42:07] [PASSED] rotate-90
[05:42:07] [PASSED] rotate-180
[05:42:07] [PASSED] rotate-270
[05:42:07] ============== [PASSED] drm_test_rect_rotate ===============
[05:42:07] ================ drm_test_rect_rotate_inv =================
[05:42:07] [PASSED] reflect-x
[05:42:07] [PASSED] reflect-y
[05:42:07] [PASSED] rotate-0
[05:42:07] [PASSED] rotate-90
[05:42:07] [PASSED] rotate-180
[05:42:07] [PASSED] rotate-270
[05:42:07] ============ [PASSED] drm_test_rect_rotate_inv =============
[05:42:07] ==================== [PASSED] drm_rect =====================
[05:42:07] ============ drm_sysfb_modeset_test (1 subtest) ============
[05:42:07] ============ drm_test_sysfb_build_fourcc_list =============
[05:42:07] [PASSED] no native formats
[05:42:07] [PASSED] XRGB8888 as native format
[05:42:07] [PASSED] remove duplicates
[05:42:07] [PASSED] convert alpha formats
[05:42:07] [PASSED] random formats
[05:42:07] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[05:42:07] ============= [PASSED] drm_sysfb_modeset_test ==============
[05:42:07] ================== drm_fixp (2 subtests) ===================
[05:42:07] [PASSED] drm_test_int2fixp
[05:42:07] [PASSED] drm_test_sm2fixp
[05:42:07] ==================== [PASSED] drm_fixp =====================
[05:42:07] ============================================================
[05:42:07] Testing complete. Ran 637 tests: passed: 637
[05:42:07] Elapsed time: 26.793s total, 1.800s configuring, 24.823s building, 0.150s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[05:42:07] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:42:09] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:42:18] Starting KUnit Kernel (1/1)...
[05:42:18] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:42:19] ================= ttm_device (5 subtests) ==================
[05:42:19] [PASSED] ttm_device_init_basic
[05:42:19] [PASSED] ttm_device_init_multiple
[05:42:19] [PASSED] ttm_device_fini_basic
[05:42:19] [PASSED] ttm_device_init_no_vma_man
[05:42:19] ================== ttm_device_init_pools ==================
[05:42:19] [PASSED] No DMA allocations, no DMA32 required
[05:42:19] [PASSED] DMA allocations, DMA32 required
[05:42:19] [PASSED] No DMA allocations, DMA32 required
[05:42:19] [PASSED] DMA allocations, no DMA32 required
[05:42:19] ============== [PASSED] ttm_device_init_pools ==============
[05:42:19] =================== [PASSED] ttm_device ====================
[05:42:19] ================== ttm_pool (8 subtests) ===================
[05:42:19] ================== ttm_pool_alloc_basic ===================
[05:42:19] [PASSED] One page
[05:42:19] [PASSED] More than one page
[05:42:19] [PASSED] Above the allocation limit
[05:42:19] [PASSED] One page, with coherent DMA mappings enabled
[05:42:19] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:42:19] ============== [PASSED] ttm_pool_alloc_basic ===============
[05:42:19] ============== ttm_pool_alloc_basic_dma_addr ==============
[05:42:19] [PASSED] One page
[05:42:19] [PASSED] More than one page
[05:42:19] [PASSED] Above the allocation limit
[05:42:19] [PASSED] One page, with coherent DMA mappings enabled
[05:42:19] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:42:19] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[05:42:19] [PASSED] ttm_pool_alloc_order_caching_match
[05:42:19] [PASSED] ttm_pool_alloc_caching_mismatch
[05:42:19] [PASSED] ttm_pool_alloc_order_mismatch
[05:42:19] [PASSED] ttm_pool_free_dma_alloc
[05:42:19] [PASSED] ttm_pool_free_no_dma_alloc
[05:42:19] [PASSED] ttm_pool_fini_basic
[05:42:19] ==================== [PASSED] ttm_pool =====================
[05:42:19] ================ ttm_resource (8 subtests) =================
[05:42:19] ================= ttm_resource_init_basic =================
[05:42:19] [PASSED] Init resource in TTM_PL_SYSTEM
[05:42:19] [PASSED] Init resource in TTM_PL_VRAM
[05:42:19] [PASSED] Init resource in a private placement
[05:42:19] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[05:42:19] ============= [PASSED] ttm_resource_init_basic =============
[05:42:19] [PASSED] ttm_resource_init_pinned
[05:42:19] [PASSED] ttm_resource_fini_basic
[05:42:19] [PASSED] ttm_resource_manager_init_basic
[05:42:19] [PASSED] ttm_resource_manager_usage_basic
[05:42:19] [PASSED] ttm_resource_manager_set_used_basic
[05:42:19] [PASSED] ttm_sys_man_alloc_basic
[05:42:19] [PASSED] ttm_sys_man_free_basic
[05:42:19] ================== [PASSED] ttm_resource ===================
[05:42:19] =================== ttm_tt (15 subtests) ===================
[05:42:19] ==================== ttm_tt_init_basic ====================
[05:42:19] [PASSED] Page-aligned size
[05:42:19] [PASSED] Extra pages requested
[05:42:19] ================ [PASSED] ttm_tt_init_basic ================
[05:42:19] [PASSED] ttm_tt_init_misaligned
[05:42:19] [PASSED] ttm_tt_fini_basic
[05:42:19] [PASSED] ttm_tt_fini_sg
[05:42:19] [PASSED] ttm_tt_fini_shmem
[05:42:19] [PASSED] ttm_tt_create_basic
[05:42:19] [PASSED] ttm_tt_create_invalid_bo_type
[05:42:19] [PASSED] ttm_tt_create_ttm_exists
[05:42:19] [PASSED] ttm_tt_create_failed
[05:42:19] [PASSED] ttm_tt_destroy_basic
[05:42:19] [PASSED] ttm_tt_populate_null_ttm
[05:42:19] [PASSED] ttm_tt_populate_populated_ttm
[05:42:19] [PASSED] ttm_tt_unpopulate_basic
[05:42:19] [PASSED] ttm_tt_unpopulate_empty_ttm
[05:42:19] [PASSED] ttm_tt_swapin_basic
[05:42:19] ===================== [PASSED] ttm_tt ======================
[05:42:19] =================== ttm_bo (14 subtests) ===================
[05:42:19] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[05:42:19] [PASSED] Cannot be interrupted and sleeps
[05:42:19] [PASSED] Cannot be interrupted, locks straight away
[05:42:19] [PASSED] Can be interrupted, sleeps
[05:42:19] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[05:42:19] [PASSED] ttm_bo_reserve_locked_no_sleep
[05:42:19] [PASSED] ttm_bo_reserve_no_wait_ticket
[05:42:19] [PASSED] ttm_bo_reserve_double_resv
[05:42:19] [PASSED] ttm_bo_reserve_interrupted
[05:42:19] [PASSED] ttm_bo_reserve_deadlock
[05:42:19] [PASSED] ttm_bo_unreserve_basic
[05:42:19] [PASSED] ttm_bo_unreserve_pinned
[05:42:19] [PASSED] ttm_bo_unreserve_bulk
[05:42:19] [PASSED] ttm_bo_fini_basic
[05:42:19] [PASSED] ttm_bo_fini_shared_resv
[05:42:19] [PASSED] ttm_bo_pin_basic
[05:42:19] [PASSED] ttm_bo_pin_unpin_resource
[05:42:19] [PASSED] ttm_bo_multiple_pin_one_unpin
[05:42:19] ===================== [PASSED] ttm_bo ======================
[05:42:19] ============== ttm_bo_validate (22 subtests) ===============
[05:42:19] ============== ttm_bo_init_reserved_sys_man ===============
[05:42:19] [PASSED] Buffer object for userspace
[05:42:19] [PASSED] Kernel buffer object
[05:42:19] [PASSED] Shared buffer object
[05:42:19] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[05:42:19] ============== ttm_bo_init_reserved_mock_man ==============
[05:42:19] [PASSED] Buffer object for userspace
[05:42:19] [PASSED] Kernel buffer object
[05:42:19] [PASSED] Shared buffer object
[05:42:19] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[05:42:19] [PASSED] ttm_bo_init_reserved_resv
[05:42:19] ================== ttm_bo_validate_basic ==================
[05:42:19] [PASSED] Buffer object for userspace
[05:42:19] [PASSED] Kernel buffer object
[05:42:19] [PASSED] Shared buffer object
[05:42:19] ============== [PASSED] ttm_bo_validate_basic ==============
[05:42:19] [PASSED] ttm_bo_validate_invalid_placement
[05:42:19] ============= ttm_bo_validate_same_placement ==============
[05:42:19] [PASSED] System manager
[05:42:19] [PASSED] VRAM manager
[05:42:19] ========= [PASSED] ttm_bo_validate_same_placement ==========
[05:42:19] [PASSED] ttm_bo_validate_failed_alloc
[05:42:19] [PASSED] ttm_bo_validate_pinned
[05:42:19] [PASSED] ttm_bo_validate_busy_placement
[05:42:19] ================ ttm_bo_validate_multihop =================
[05:42:19] [PASSED] Buffer object for userspace
[05:42:19] [PASSED] Kernel buffer object
[05:42:19] [PASSED] Shared buffer object
[05:42:19] ============ [PASSED] ttm_bo_validate_multihop =============
[05:42:19] ========== ttm_bo_validate_no_placement_signaled ==========
[05:42:19] [PASSED] Buffer object in system domain, no page vector
[05:42:19] [PASSED] Buffer object in system domain with an existing page vector
[05:42:19] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[05:42:19] ======== ttm_bo_validate_no_placement_not_signaled ========
[05:42:19] [PASSED] Buffer object for userspace
[05:42:19] [PASSED] Kernel buffer object
[05:42:19] [PASSED] Shared buffer object
[05:42:19] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[05:42:19] [PASSED] ttm_bo_validate_move_fence_signaled
[05:42:19] ========= ttm_bo_validate_move_fence_not_signaled =========
[05:42:19] [PASSED] Waits for GPU
[05:42:19] [PASSED] Tries to lock straight away
[05:42:19] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[05:42:19] [PASSED] ttm_bo_validate_swapout
[05:42:19] [PASSED] ttm_bo_validate_happy_evict
[05:42:19] [PASSED] ttm_bo_validate_all_pinned_evict
[05:42:19] [PASSED] ttm_bo_validate_allowed_only_evict
[05:42:19] [PASSED] ttm_bo_validate_deleted_evict
[05:42:19] [PASSED] ttm_bo_validate_busy_domain_evict
[05:42:19] [PASSED] ttm_bo_validate_evict_gutting
[05:42:19] [PASSED] ttm_bo_validate_recrusive_evict
[05:42:19] ================= [PASSED] ttm_bo_validate =================
[05:42:19] ============================================================
[05:42:19] Testing complete. Ran 102 tests: passed: 102
[05:42:19] Elapsed time: 11.974s total, 1.760s configuring, 9.949s building, 0.225s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Xe.CI.BAT: success for drm/xe/guc_ads: allocate UM queues in a separate UC BO
2026-07-22 5:34 [PATCH v3 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO Jia Yao
` (2 preceding siblings ...)
2026-07-22 5:42 ` ✓ CI.KUnit: success " Patchwork
@ 2026-07-22 6:17 ` Patchwork
2026-07-22 20:20 ` ✓ Xe.CI.FULL: " Patchwork
2026-07-30 0:47 ` [PATCH v4 0/1] " Jia Yao
5 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2026-07-22 6:17 UTC (permalink / raw)
To: Jia Yao; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1015 bytes --]
== Series Details ==
Series: drm/xe/guc_ads: allocate UM queues in a separate UC BO
URL : https://patchwork.freedesktop.org/series/170879/
State : success
== Summary ==
CI Bug Log - changes from xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c_BAT -> xe-pw-170879v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_9017 -> IGT_9018
* Linux: xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c -> xe-pw-170879v1
IGT_9017: 9017
IGT_9018: f4345861cbd5d97fd50b73bf7af5fe3286fca056 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c: 5726f9c4bde0290e5e60e636b9632bb03a57498c
xe-pw-170879v1: 170879v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/index.html
[-- Attachment #2: Type: text/html, Size: 1577 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO
2026-07-22 5:34 ` [PATCH v3 1/1] " Jia Yao
@ 2026-07-22 9:18 ` Matthew Auld
2026-07-22 23:00 ` Gwan-gyeong Mun
1 sibling, 0 replies; 17+ messages in thread
From: Matthew Auld @ 2026-07-22 9:18 UTC (permalink / raw)
To: Jia Yao, intel-xe; +Cc: Gwan-gyeong Mun, stable
On 22/07/2026 06:34, Jia Yao wrote:
> The HW unit that writes to the UM fault queue is not always coherent
> with the CPU cache. Ensure the UM queue memory is uncached on the CPU
> side so that GuC always reads descriptors from memory rather than a
> stale CPU cache line.
>
> Allocate the UM queues in a dedicated UC BO (ads->um_queue_bo) instead
> of the main ADS blob. This also prevents xe_guc_ads_populate()'s
> memset from zeroing any fault descriptor written between GDRST and GuC
> restart. On dGFX, VRAM placement gives a well-defined DPA.
>
> v3: simplify commit message and code comments per reviewer feedback;
> add Fixes tag and stable Cc
>
> v2: also fix dGFX (VRAM placement + UC flag); remove now-dead
> guc_ads_um_queues_size/offset helpers
>
> Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: stable@vger.kernel.org
> Signed-off-by: Jia Yao <jia.yao@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc_ads.c | 64 ++++++++++++++++-----------
> drivers/gpu/drm/xe/xe_guc_ads_types.h | 8 +++-
> 2 files changed, 46 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index c98454545a85..ec36a5db7fc8 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -155,16 +155,6 @@ static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
> return PAGE_ALIGN(ads->capture_size);
> }
>
> -static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
> -{
> - struct xe_device *xe = ads_to_xe(ads);
> -
> - if (!xe->info.has_usm)
> - return 0;
> -
> - return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX;
> -}
> -
> static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)
> {
> return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size);
> @@ -205,22 +195,12 @@ static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
> return PAGE_ALIGN(offset);
> }
>
> -static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
> -{
> - u32 offset;
> -
> - offset = guc_ads_capture_offset(ads) +
> - guc_ads_capture_size(ads);
> -
> - return PAGE_ALIGN(offset);
> -}
> -
> static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
> {
> size_t offset;
>
> - offset = guc_ads_um_queues_offset(ads) +
> - guc_ads_um_queues_size(ads);
> + offset = guc_ads_capture_offset(ads) +
> + guc_ads_capture_size(ads);
>
> return PAGE_ALIGN(offset);
> }
> @@ -409,6 +389,30 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
>
> ads->bo = bo;
>
> + /*
> + * The HW unit that writes to the UM fault queue is not coherent with
> + * the CPU cache. Use a dedicated UC BO to ensure GuC always reads
> + * descriptors from memory rather than a stale CPU cache line. A
> + * separate BO also prevents xe_guc_ads_populate()'s memset from
> + * zeroing descriptors written between GDRST and GuC restart. On
> + * dGFX, VRAM gives a well-defined DPA.
> + */
> + if (xe->info.has_usm) {
> + u32 um_flags = XE_BO_FLAG_GGTT |
> + XE_BO_FLAG_GGTT_INVALIDATE |
> + XE_BO_FLAG_PINNED_NORESTORE |
> + XE_BO_FLAG_NEEDS_UC |
> + XE_BO_FLAG_VRAM_IF_DGFX(tile);
Only slight doubt is the dgpu change here. I don't think there can be a
coherency issue there, since memory access to system memory should just
be like any other PCI transaction, and AFAIK coherency can't be turned
off on current dgpu hw. Just wondering if moving this to VRAM is really
needed for the fix, or whether there are any perf considerations? Not
sure if there is some guidance on where is best to allocate this on
dgpu? Also, perhaps this should be split out into a separate commit,
since change seems orthogonal to the coherency issue?
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> +
> + bo = xe_managed_bo_create_pin_map(xe, tile,
> + GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX,
> + um_flags);
> + if (IS_ERR(bo))
> + return PTR_ERR(bo);
> +
> + ads->um_queue_bo = bo;
> + }
> +
> return 0;
> }
> ALLOW_ERROR_INJECTION(xe_guc_ads_init, ERRNO); /* See xe_pci_probe() */
> @@ -820,9 +824,9 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
>
> static void guc_um_init_params(struct xe_guc_ads *ads)
> {
> - u32 um_queue_offset = guc_ads_um_queues_offset(ads);
> struct xe_guc *guc = ads_to_guc(ads);
> struct xe_device *xe = ads_to_xe(ads);
> + struct xe_bo *um_bo = ads->um_queue_bo;
> u64 base_dpa;
> u32 base_ggtt;
> bool with_dpa;
> @@ -830,8 +834,14 @@ static void guc_um_init_params(struct xe_guc_ads *ads)
>
> with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
>
> - base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
> - base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
> + if (um_bo) {
> + /* All USM platforms: UM queues in dedicated um_queue_bo */
> + base_ggtt = xe_bo_ggtt_addr(um_bo);
> + base_dpa = xe_bo_main_addr(um_bo, PAGE_SIZE);
> + } else {
> + /* Platform does not support USM: no UM queues, nothing to do */
> + return;
> + }
>
> for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
> /*
> @@ -912,6 +922,10 @@ void xe_guc_ads_populate(struct xe_guc_ads *ads)
> xe_gt_assert(gt, ads->bo);
>
> xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, xe_bo_size(ads->bo));
> + /*
> + * um_queue_bo is not zeroed here. GuC resets head/tail via MMIO on
> + * every restart so stale ring contents are never consumed.
> + */
> guc_policies_init(ads);
> fill_engine_enable_masks(gt, &info_map);
> guc_mmio_reg_state_init(ads);
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h
> index 48a8e092023f..a63ef000dc8a 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads_types.h
> +++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h
> @@ -14,8 +14,14 @@ struct xe_bo;
> * struct xe_guc_ads - GuC additional data structures (ADS)
> */
> struct xe_guc_ads {
> - /** @bo: Xe BO for GuC ads blob */
> + /** @bo: Xe BO for GuC ads blob (WB cached) */
> struct xe_bo *bo;
> + /**
> + * @um_queue_bo: Dedicated UC BO for the HW fault ring (UM queues).
> + * The HW unit writing to this ring is not coherent with the CPU cache;
> + * UC ensures GuC reads descriptors from memory. NULL if no USM support.
> + */
> + struct xe_bo *um_queue_bo;
> /** @golden_lrc_size: golden LRC size */
> size_t golden_lrc_size;
> /** @regset_size: size of register set passed to GuC for save/restore */
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Xe.CI.FULL: success for drm/xe/guc_ads: allocate UM queues in a separate UC BO
2026-07-22 5:34 [PATCH v3 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO Jia Yao
` (3 preceding siblings ...)
2026-07-22 6:17 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-07-22 20:20 ` Patchwork
2026-07-30 0:47 ` [PATCH v4 0/1] " Jia Yao
5 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2026-07-22 20:20 UTC (permalink / raw)
To: Jia Yao; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 25733 bytes --]
== Series Details ==
Series: drm/xe/guc_ads: allocate UM queues in a separate UC BO
URL : https://patchwork.freedesktop.org/series/170879/
State : success
== Summary ==
CI Bug Log - changes from xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c_FULL -> xe-pw-170879v1_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-170879v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip:
- shard-bmg: NOTRUN -> [SKIP][1] ([Intel XE#7059] / [Intel XE#7085])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-7/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-bmg: NOTRUN -> [SKIP][2] ([Intel XE#1124]) +6 other tests skip
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-10/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
* igt@kms_bw@connected-linear-tiling-3-displays-target-2160x1440p:
- shard-bmg: NOTRUN -> [SKIP][3] ([Intel XE#7679])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-1/igt@kms_bw@connected-linear-tiling-3-displays-target-2160x1440p.html
* igt@kms_bw@linear-tiling-3-displays-target-2560x1440p:
- shard-bmg: NOTRUN -> [SKIP][4] ([Intel XE#367])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-6/igt@kms_bw@linear-tiling-3-displays-target-2560x1440p.html
* igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][5] ([Intel XE#2887]) +7 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-2/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
- shard-bmg: NOTRUN -> [SKIP][6] ([Intel XE#2652]) +8 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-9/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html
* igt@kms_chamelium_color_pipeline@plane-lut3d-green-only:
- shard-bmg: NOTRUN -> [SKIP][7] ([Intel XE#7358]) +1 other test skip
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-10/igt@kms_chamelium_color_pipeline@plane-lut3d-green-only.html
* igt@kms_chamelium_frames@hdmi-frame-dump:
- shard-bmg: NOTRUN -> [SKIP][8] ([Intel XE#2252]) +4 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-10/igt@kms_chamelium_frames@hdmi-frame-dump.html
* igt@kms_content_protection@dp-mst-type-1-suspend-resume:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#6974])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-6/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html
* igt@kms_content_protection@legacy-hdcp14@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][10] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +3 other tests fail
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-10/igt@kms_content_protection@legacy-hdcp14@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-offscreen-128x42:
- shard-bmg: NOTRUN -> [SKIP][11] ([Intel XE#2320]) +3 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-2/igt@kms_cursor_crc@cursor-offscreen-128x42.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-bmg: NOTRUN -> [SKIP][12] ([Intel XE#2286] / [Intel XE#6035])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#1508])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-8/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dp_link_training@non-uhbr-mst:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#4354] / [Intel XE#5882])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-mst.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#8265]) +1 other test skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-7/igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-lnl: [PASS][16] -> [FAIL][17] ([Intel XE#301]) +1 other test fail
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#7178] / [Intel XE#7349])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
* igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-10/igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#4141]) +5 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#2311]) +33 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrshdr-tiling-y:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#7399]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrshdr-tiling-y.html
* igt@kms_frontbuffer_tracking@hdr-abgr161616f-draw-render:
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#7061]) +2 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-10/igt@kms_frontbuffer_tracking@hdr-abgr161616f-draw-render.html
* igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-pri-shrfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#2313]) +34 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-1/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_hdmi_inject@inject-audio:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#7308])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-6/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [PASS][26] -> [SKIP][27] ([Intel XE#1503])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-7/igt@kms_hdr@invalid-hdr.html
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-3/igt@kms_hdr@invalid-hdr.html
* igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping:
- shard-bmg: NOTRUN -> [SKIP][28] ([Intel XE#7283]) +2 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-6/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#2938] / [Intel XE#7376] / [Intel XE#7760])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-9/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_dc@dc6-dpms:
- shard-lnl: [PASS][30] -> [FAIL][31] ([Intel XE#8399]) +1 other test fail
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-lnl-2/igt@kms_pm_dc@dc6-dpms.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-lnl-3/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#7794])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-6/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_dc@deep-pkgc:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#2505] / [Intel XE#7447])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-7/igt@kms_pm_dc@deep-pkgc.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-bmg: NOTRUN -> [SKIP][34] ([Intel XE#1489]) +5 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-4/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr@fbc-psr-cursor-plane-move:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#2234] / [Intel XE#2850]) +5 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-9/igt@kms_psr@fbc-psr-cursor-plane-move.html
* igt@kms_psr@psr2-primary-render:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#2234])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-3/igt@kms_psr@psr2-primary-render.html
* igt@kms_tv_load_detect@load-detect:
- shard-bmg: NOTRUN -> [SKIP][37] ([Intel XE#2450] / [Intel XE#5857])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-8/igt@kms_tv_load_detect@load-detect.html
* igt@xe_evict@evict-threads-small-multi-queue:
- shard-bmg: NOTRUN -> [SKIP][38] ([Intel XE#8370])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-4/igt@xe_evict@evict-threads-small-multi-queue.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr:
- shard-bmg: NOTRUN -> [SKIP][39] ([Intel XE#2322] / [Intel XE#7372]) +2 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr.html
* igt@xe_exec_fault_mode@many-execqueues-multi-queue-rebind-prefetch:
- shard-bmg: NOTRUN -> [SKIP][40] ([Intel XE#8374]) +6 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-9/igt@xe_exec_fault_mode@many-execqueues-multi-queue-rebind-prefetch.html
* igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-dyn-priority:
- shard-bmg: NOTRUN -> [SKIP][41] ([Intel XE#8364]) +14 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-2/igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-dyn-priority.html
* igt@xe_exec_reset@multi-queue-close-fd:
- shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#8369])
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-9/igt@xe_exec_reset@multi-queue-close-fd.html
* igt@xe_exec_threads@threads-multi-queue-rebind-err:
- shard-bmg: NOTRUN -> [SKIP][43] ([Intel XE#8378]) +4 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-10/igt@xe_exec_threads@threads-multi-queue-rebind-err.html
* igt@xe_multigpu_svm@mgpu-xgpu-access-basic:
- shard-bmg: NOTRUN -> [SKIP][44] ([Intel XE#6964])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-3/igt@xe_multigpu_svm@mgpu-xgpu-access-basic.html
* igt@xe_oa@non-zero-reason-all@oag-0:
- shard-bmg: [PASS][45] -> [FAIL][46] ([Intel XE#7334]) +1 other test fail
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-1/igt@xe_oa@non-zero-reason-all@oag-0.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-9/igt@xe_oa@non-zero-reason-all@oag-0.html
* igt@xe_pm@s3-d3cold-basic-exec:
- shard-bmg: NOTRUN -> [SKIP][47] ([Intel XE#2284] / [Intel XE#7370])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-4/igt@xe_pm@s3-d3cold-basic-exec.html
* igt@xe_pxp@pxp-stale-queue-post-termination-irq:
- shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#4733] / [Intel XE#7417]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-6/igt@xe_pxp@pxp-stale-queue-post-termination-irq.html
* igt@xe_query@multigpu-query-gt-list:
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#944]) +1 other test skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-8/igt@xe_query@multigpu-query-gt-list.html
* igt@xe_sriov_flr@flr-twice:
- shard-bmg: [PASS][50] -> [FAIL][51] ([Intel XE#6569])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-9/igt@xe_sriov_flr@flr-twice.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-1/igt@xe_sriov_flr@flr-twice.html
* igt@xe_sriov_vram@vf-access-after-resize-down:
- shard-bmg: [PASS][52] -> [FAIL][53] ([Intel XE#7992])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-3/igt@xe_sriov_vram@vf-access-after-resize-down.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-4/igt@xe_sriov_vram@vf-access-after-resize-down.html
#### Possible fixes ####
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-bmg: [FAIL][54] ([Intel XE#7571]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-10/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-bmg: [FAIL][56] ([Intel XE#3098]) -> [PASS][57] +1 other test pass
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-1/igt@kms_flip@plain-flip-fb-recreate.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-6/igt@kms_flip@plain-flip-fb-recreate.html
* igt@xe_evict@evict-beng-mixed-many-threads-small:
- shard-bmg: [INCOMPLETE][58] ([Intel XE#6321] / [Intel XE#8355]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-9/igt@xe_evict@evict-beng-mixed-many-threads-small.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-3/igt@xe_evict@evict-beng-mixed-many-threads-small.html
* igt@xe_exec_fault_mode@atomic-many:
- shard-bmg: [FAIL][60] ([Intel XE#8578]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-6/igt@xe_exec_fault_mode@atomic-many.html
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-4/igt@xe_exec_fault_mode@atomic-many.html
* igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init:
- shard-bmg: [ABORT][62] ([Intel XE#8007]) -> [PASS][63] +1 other test pass
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-5/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-8/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init.html
* igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_video_enhance0:
- shard-bmg: [FAIL][64] ([Intel XE#8639]) -> [PASS][65] +1 other test pass
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-2/igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_video_enhance0.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-8/igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_video_enhance0.html
* igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_video_enhance1:
- shard-bmg: [ABORT][66] ([Intel XE#8637]) -> [PASS][67] +1 other test pass
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-2/igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_video_enhance1.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-8/igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_video_enhance1.html
#### Warnings ####
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
- shard-lnl: [SKIP][68] ([Intel XE#309] / [Intel XE#7343] / [Intel XE#7935]) -> [SKIP][69] ([Intel XE#309] / [Intel XE#7343])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-lnl-2/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][70] ([Intel XE#3544]) -> [SKIP][71] ([Intel XE#3374] / [Intel XE#3544])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-6/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [SKIP][72] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][73] ([Intel XE#1729] / [Intel XE#7424])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][74] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][75] ([Intel XE#2426] / [Intel XE#5848])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2450
[Intel XE#2505]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2505
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
[Intel XE#5857]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5857
[Intel XE#5882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5882
[Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
[Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
[Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
[Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
[Intel XE#7308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7308
[Intel XE#7334]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7334
[Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
[Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
[Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
[Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
[Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
[Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
[Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
[Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
[Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
[Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
[Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
[Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
[Intel XE#7447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7447
[Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
[Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
[Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
[Intel XE#7794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7794
[Intel XE#7935]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7935
[Intel XE#7992]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7992
[Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
[Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
[Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
[Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
[Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
[Intel XE#8370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8370
[Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
[Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
[Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399
[Intel XE#8578]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8578
[Intel XE#8637]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8637
[Intel XE#8639]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8639
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* IGT: IGT_9017 -> IGT_9018
* Linux: xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c -> xe-pw-170879v1
IGT_9017: 9017
IGT_9018: f4345861cbd5d97fd50b73bf7af5fe3286fca056 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-5453-5726f9c4bde0290e5e60e636b9632bb03a57498c: 5726f9c4bde0290e5e60e636b9632bb03a57498c
xe-pw-170879v1: 170879v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170879v1/index.html
[-- Attachment #2: Type: text/html, Size: 27924 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO
2026-07-22 5:34 ` [PATCH v3 1/1] " Jia Yao
2026-07-22 9:18 ` Matthew Auld
@ 2026-07-22 23:00 ` Gwan-gyeong Mun
1 sibling, 0 replies; 17+ messages in thread
From: Gwan-gyeong Mun @ 2026-07-22 23:00 UTC (permalink / raw)
To: Jia Yao, intel-xe; +Cc: Matthew Auld, stable
On 7/21/26 10:34 PM, Jia Yao wrote:
> The HW unit that writes to the UM fault queue is not always coherent
> with the CPU cache. Ensure the UM queue memory is uncached on the CPU
> side so that GuC always reads descriptors from memory rather than a
> stale CPU cache line.
>
> Allocate the UM queues in a dedicated UC BO (ads->um_queue_bo) instead
> of the main ADS blob. This also prevents xe_guc_ads_populate()'s
> memset from zeroing any fault descriptor written between GDRST and GuC
> restart. On dGFX, VRAM placement gives a well-defined DPA.
>
> v3: simplify commit message and code comments per reviewer feedback;
> add Fixes tag and stable Cc
>
> v2: also fix dGFX (VRAM placement + UC flag); remove now-dead
> guc_ads_um_queues_size/offset helpers
>
> Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: stable@vger.kernel.org
> Signed-off-by: Jia Yao <jia.yao@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc_ads.c | 64 ++++++++++++++++-----------
> drivers/gpu/drm/xe/xe_guc_ads_types.h | 8 +++-
> 2 files changed, 46 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index c98454545a85..ec36a5db7fc8 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -155,16 +155,6 @@ static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
> return PAGE_ALIGN(ads->capture_size);
> }
>
> -static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
> -{
> - struct xe_device *xe = ads_to_xe(ads);
> -
> - if (!xe->info.has_usm)
> - return 0;
> -
> - return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX;
> -}
> -
> static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)
> {
> return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size);
> @@ -205,22 +195,12 @@ static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
> return PAGE_ALIGN(offset);
> }
>
> -static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
> -{
> - u32 offset;
> -
> - offset = guc_ads_capture_offset(ads) +
> - guc_ads_capture_size(ads);
> -
> - return PAGE_ALIGN(offset);
> -}
> -
> static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
> {
> size_t offset;
>
> - offset = guc_ads_um_queues_offset(ads) +
> - guc_ads_um_queues_size(ads);
> + offset = guc_ads_capture_offset(ads) +
> + guc_ads_capture_size(ads);
>
> return PAGE_ALIGN(offset);
> }
> @@ -409,6 +389,30 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
>
> ads->bo = bo;
>
> + /*
> + * The HW unit that writes to the UM fault queue is not coherent with
> + * the CPU cache. Use a dedicated UC BO to ensure GuC always reads
> + * descriptors from memory rather than a stale CPU cache line. A
> + * separate BO also prevents xe_guc_ads_populate()'s memset from
> + * zeroing descriptors written between GDRST and GuC restart. On
> + * dGFX, VRAM gives a well-defined DPA.
> + */
> + if (xe->info.has_usm) {
> + u32 um_flags = XE_BO_FLAG_GGTT |
> + XE_BO_FLAG_GGTT_INVALIDATE |
> + XE_BO_FLAG_PINNED_NORESTORE |
> + XE_BO_FLAG_NEEDS_UC |
> + XE_BO_FLAG_VRAM_IF_DGFX(tile);
> +
> + bo = xe_managed_bo_create_pin_map(xe, tile,
> + GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX,
> + um_flags);
> + if (IS_ERR(bo))
> + return PTR_ERR(bo);
> +
> + ads->um_queue_bo = bo;
> + }
> +
> return 0;
> }
> ALLOW_ERROR_INJECTION(xe_guc_ads_init, ERRNO); /* See xe_pci_probe() */
> @@ -820,9 +824,9 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
>
> static void guc_um_init_params(struct xe_guc_ads *ads)
> {
> - u32 um_queue_offset = guc_ads_um_queues_offset(ads);
> struct xe_guc *guc = ads_to_guc(ads);
> struct xe_device *xe = ads_to_xe(ads);
> + struct xe_bo *um_bo = ads->um_queue_bo;
> u64 base_dpa;
> u32 base_ggtt;
> bool with_dpa;
> @@ -830,8 +834,14 @@ static void guc_um_init_params(struct xe_guc_ads *ads)
>
> with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
>
> - base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
> - base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
> + if (um_bo) {
> + /* All USM platforms: UM queues in dedicated um_queue_bo */
> + base_ggtt = xe_bo_ggtt_addr(um_bo);
> + base_dpa = xe_bo_main_addr(um_bo, PAGE_SIZE);
> + } else {
> + /* Platform does not support USM: no UM queues, nothing to do */
> + return;
> + }
>
> for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
> /*
> @@ -912,6 +922,10 @@ void xe_guc_ads_populate(struct xe_guc_ads *ads)
> xe_gt_assert(gt, ads->bo);
>
> xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, xe_bo_size(ads->bo));
> + /*
> + * um_queue_bo is not zeroed here. GuC resets head/tail via MMIO on
> + * every restart so stale ring contents are never consumed.
> + */
> guc_policies_init(ads);
> fill_engine_enable_masks(gt, &info_map);
> guc_mmio_reg_state_init(ads);
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h
> index 48a8e092023f..a63ef000dc8a 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads_types.h
> +++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h
> @@ -14,8 +14,14 @@ struct xe_bo;
> * struct xe_guc_ads - GuC additional data structures (ADS)
> */
> struct xe_guc_ads {
> - /** @bo: Xe BO for GuC ads blob */
> + /** @bo: Xe BO for GuC ads blob (WB cached) */
> struct xe_bo *bo;
> + /**
> + * @um_queue_bo: Dedicated UC BO for the HW fault ring (UM queues).
> + * The HW unit writing to this ring is not coherent with the CPU cache;
> + * UC ensures GuC reads descriptors from memory. NULL if no USM support.
> + */
> + struct xe_bo *um_queue_bo;
> /** @golden_lrc_size: golden LRC size */
> size_t golden_lrc_size;
> /** @regset_size: size of register set passed to GuC for save/restore */
Hi Jia,
Regarding the issue mentioned in the cover letter that this patch aims
to fix, wouldn't it be resolved by creating a separate um_queue_bo by
adding XE_BO_FLAG_NEEDS_UC to the (XE_BO_FLAG_SYSTEM | XE_BO_FLAG_GGTT |
XE_BO_FLAG_GGTT_INVALIDATE | XE_BO_FLAG_PINNED_NORESTORE) flags used in
the existing code when generating ads->bo? If so, as Matthew Auld
mentioned, wouldn't it be better to apply this patch as one that creates
an Uncached buffer for um_queue_bo, and then split it into a separate
patch that uses XE_BO_FLAG_VRAM_IF_DGFX(tile) instead of
XE_BO_FLAG_SYSTEM if there is a performance improvement on the dGPU?
And please also update the description section titled "Layout of the ADS
blob allocated for the GuC" in the [drivers/gpu/drm/xe/xe_guc_ads.c] file.
G.G.
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v4 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO
2026-07-22 5:34 [PATCH v3 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO Jia Yao
` (4 preceding siblings ...)
2026-07-22 20:20 ` ✓ Xe.CI.FULL: " Patchwork
@ 2026-07-30 0:47 ` Jia Yao
2026-07-30 0:47 ` [PATCH v4 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO Jia Yao
` (2 more replies)
5 siblings, 3 replies; 17+ messages in thread
From: Jia Yao @ 2026-07-30 0:47 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.auld, gwan-gyeong.mun, stable, Jia Yao
== Problem ==
On platforms with Unified Shared Memory (USM), the xe driver maintains
three hardware page-fault queues (PAGE_FAULT, PAGE_FAULT_RESPONSE,
ACCESS_COUNTER) inside the GuC Additional Data Structures (ADS) blob.
The ADS blob is mapped WB on the CPU side.
xe_guc_ads_populate() is called on every GT reset to reprogram the ADS
blob; it begins with a full memset() of the blob to zero. The zeroed
cache lines for the UM queue region reside in the CPU cache (LLC, WB)
but are not immediately written back to DRAM.
GAM hardware writes fault descriptors to the queue via DPA - a
non-coherent path that bypasses the CPU cache and writes directly to
memory. GuC reads the queue via GGTT (WB), which hits the CPU cache.
As a result GuC sees the stale zeroed data from the CPU cache instead
of the descriptor written to DRAM by GAM. The driver then receives an
all-zero fault descriptor and returns -EINVAL, causing an unnecessary
engine reset.
This is documented in HSD as:
"When Fault queue is updated by the SW (Buffer zeroed), it can reside
in the CPU cache (L4:WB). A non coherent write from GAM HW would not
consult the CPU cache and it will eventually get written into the
memory (depends upon eviction/flushes) and CPU cache has stale data.
When GUC HW reads the fault queue it gets it from the CPU cache,
which is stale data."
The window is narrow but reliably reproducible: run xe_exec_reset
--run-subtest gt-reset followed immediately by
xe_exec_system_allocator --run-subtest
threads-many-execqueues-mmap-new-race.
== Reproduction ==
# Requires a platform with has_usm (e.g. Xe3 iGFX)
sudo xe_exec_reset --run-subtest gt-reset
sudo xe_exec_system_allocator --run-subtest threads-many-execqueues-mmap-new-race
Symptom in dmesg:
[xe] ASID: 0, Faulted Address: 0x0000000000000000, FaultType: 0
The all-zero fault descriptor is the tell-tale sign of the stale
cache line race.
== Fix ==
Allocate the UM queues in a dedicated UC BO (ads->um_queue_bo). UC
mapping on the CPU side ensures the memset bypasses the cache and the
zeroed data lands in DRAM immediately. GuC's non-coherent read then
goes to DRAM and sees the correct descriptor written by GAM.
A separate BO also eliminates the secondary race where a descriptor
written by the GPU between GDRST and GuC restart could be zeroed by the
next call to xe_guc_ads_populate().
On dGFX, VRAM placement is used so that xe_bo_main_addr() returns a
real device-physical address (DPA). The original ADS BO is explicitly
migrated to VRAM by xe_guc_realloc_post_hwconfig(), so its
xe_bo_main_addr() already returns a correct DPA. A separate SYSTEM BO
for the UM queues would not go through that migration path; on systems
where physical pages are allocated above 4 GB the IOMMU assigns an IOVA
that differs from the physical address, so base_dpa would be wrong and
GuC/GAM would access the wrong memory.
Why not just flush the cache after memset?
An earlier approach called drm_clflush_virt_range() on the UM queue
region immediately after the memset to evict the stale zero lines from
LLC. This reduces the failure rate significantly but does not fully
eliminate the race for two reasons.
First, the Linux kernel maintains a WB direct mapping (linear map) that
covers all physical memory. Even after flushing the vmap alias, the
CPU can speculatively prefetch the same physical page through the WB
direct-map alias, silently repopulating the cache with zeros. LNL is
known to be particularly susceptible to this speculative prefetch
behaviour. XE_BO_FLAG_NEEDS_UC calls set_memory_uc() which updates
both the vmap PTE and the direct-map PTE to UC, closing this aliasing
window entirely.
Second, the flush approach leaves the memory mapped WB on the CPU side
permanently. Any future SW access - a debug read, a tracing hook, an
inadvertent touch - can re-dirty the cache line and reintroduce the
race. UC mapping makes the correct behaviour unconditional and
self-documenting.
Changes in v4:
- Split the single v3 patch into three logically independent patches:
1. Separate BO allocation (root fix for the memset-zeroing race)
2. VRAM placement on dGFX (fix incorrect DPA when pages are above 4 GB)
3. UC mapping (close the CPU cache aliasing window on iGFX)
- Corrected the dGFX description: the original ADS BO works because
xe_guc_realloc_post_hwconfig() explicitly migrates it to VRAM; a
separate SYSTEM BO would not be migrated and its IOVA would differ
from the physical address for high-memory pages. The previous
description incorrectly attributed this to IOVA aliasing a PCI MMIO
reserved window.
- Added physical-contiguity verification for no-IOMMU iGFX systems.
- xe_guc.c: removed the post-hwconfig reinit_in_vram call for
um_queue_bo now that dGFX allocates it directly in VRAM.
Jia Yao (3):
drm/xe/guc_ads: allocate UM queues in a separate BO
drm/xe/guc_ads: allocate UM queues in VRAM on dGFX
drm/xe/guc_ads: use uncached mapping for UM queue BO
drivers/gpu/drm/xe/xe_guc_ads.c | 100 +++++++++++++++++++-------
drivers/gpu/drm/xe/xe_guc_ads_types.h | 5 ++
2 files changed, 80 insertions(+), 25 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v4 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO
2026-07-30 0:47 ` [PATCH v4 0/1] " Jia Yao
@ 2026-07-30 0:47 ` Jia Yao
2026-07-30 10:28 ` Matthew Auld
2026-07-30 0:47 ` [PATCH v4 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX Jia Yao
2026-07-30 0:47 ` [PATCH v4 3/3] drm/xe/guc_ads: use uncached mapping for UM queue BO Jia Yao
2 siblings, 1 reply; 17+ messages in thread
From: Jia Yao @ 2026-07-30 0:47 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.auld, gwan-gyeong.mun, stable, Jia Yao
xe_guc_ads_populate() calls xe_map_memset() on the ADS BO on every GT
reset. The UM queue ring buffers were embedded in that same BO, so the
memset discards fault descriptors already written by the GPU, causing
GuC to forward an all-zero descriptor (Faulted Address = 0, ASID = 0).
Move the UM queue ring buffers into a dedicated BO so they are not
affected by the ADS memset.
Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Jia Yao <jia.yao@intel.com>
---
drivers/gpu/drm/xe/xe_guc.c | 6 ++
drivers/gpu/drm/xe/xe_guc_ads.c | 98 ++++++++++++++++++++-------
drivers/gpu/drm/xe/xe_guc_ads_types.h | 5 ++
3 files changed, 84 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 4023700ff2a9..21cf3edef922 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -714,6 +714,12 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
if (ret)
return ret;
+ if (guc->ads.um_queue_bo) {
+ ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index c98454545a85..7f371f9c7268 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -16,6 +16,7 @@
#include "regs/xe_gt_regs.h"
#include "regs/xe_guc_regs.h"
#include "xe_bo.h"
+#include "xe_res_cursor.h"
#include "xe_gt.h"
#include "xe_gt_ccs_mode.h"
#include "xe_gt_mcr.h"
@@ -155,16 +156,6 @@ static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
return PAGE_ALIGN(ads->capture_size);
}
-static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
-{
- struct xe_device *xe = ads_to_xe(ads);
-
- if (!xe->info.has_usm)
- return 0;
-
- return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX;
-}
-
static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)
{
return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size);
@@ -205,22 +196,12 @@ static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
return PAGE_ALIGN(offset);
}
-static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
-{
- u32 offset;
-
- offset = guc_ads_capture_offset(ads) +
- guc_ads_capture_size(ads);
-
- return PAGE_ALIGN(offset);
-}
-
static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
{
size_t offset;
- offset = guc_ads_um_queues_offset(ads) +
- guc_ads_um_queues_size(ads);
+ offset = guc_ads_capture_offset(ads) +
+ guc_ads_capture_size(ads);
return PAGE_ALIGN(offset);
}
@@ -409,6 +390,67 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
ads->bo = bo;
+ if (xe->info.has_usm) {
+ /*
+ * Allocate a separate BO for the HW fault ring (UM queues).
+ *
+ * xe_guc_ads_populate() clears the entire ADS BO via
+ * xe_map_memset() on every GT reset. Keeping the UM queues
+ * in a dedicated BO prevents that memset from discarding fault
+ * descriptors the GPU has already written into the ring,
+ * which would cause GuC to forward an all-zero descriptor to
+ * the driver (Faulted Address = 0, ASID = 0).
+ *
+ * Round the size up to the next power of two so that on iGPU
+ * (system memory, no IOMMU) the TTM pool issues a single
+ * alloc_pages(order=N) call, maximising the chance of getting
+ * a physically contiguous block. GuC requires contiguous DPA.
+ */
+ size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
+ GUC_UM_HW_QUEUE_MAX);
+
+ bo = xe_managed_bo_create_pin_map(xe, tile, um_size,
+ XE_BO_FLAG_SYSTEM |
+ XE_BO_FLAG_GGTT |
+ XE_BO_FLAG_GGTT_INVALIDATE |
+ XE_BO_FLAG_PINNED_NORESTORE);
+ if (IS_ERR(bo))
+ return PTR_ERR(bo);
+
+ /*
+ * On pre-Xe3p platforms, GAM (not GuC) accesses the UM queue
+ * ring via base_dpa, which must be a contiguous device physical
+ * address range. Without IOMMU, DMA addresses equal physical
+ * addresses and the allocator may return non-contiguous pages;
+ * verify contiguity. With IOMMU, the DMA mapping is a single
+ * contiguous IOVA so no check is needed.
+ */
+ if (unlikely(!device_iommu_mapped(xe->drm.dev)) &&
+ !xe_bo_is_vram(bo) &&
+ !xe_guc_using_main_gamctrl_queues(ads_to_guc(ads))) {
+ struct xe_res_cursor cur;
+ int i;
+
+ xe_res_first_sg(xe_bo_sg(bo), 0,
+ GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX, &cur);
+ for (i = 1; i < GUC_UM_HW_QUEUE_MAX; i++) {
+ dma_addr_t expected = xe_res_dma(&cur) +
+ GUC_UM_QUEUE_SIZE;
+
+ xe_res_next(&cur, GUC_UM_QUEUE_SIZE);
+ if (xe_res_dma(&cur) != expected) {
+ drm_err(&xe->drm,
+ "UM fault queue %d is physically non-contiguous (got %pad, expected %pad); GAM requires contiguous DPA. Enable IOMMU (intel_iommu=on) to fix.\n",
+ i, &(dma_addr_t){xe_res_dma(&cur)},
+ &expected);
+ return -ENOMEM;
+ }
+ }
+ }
+
+ ads->um_queue_bo = bo;
+ }
+
return 0;
}
ALLOW_ERROR_INJECTION(xe_guc_ads_init, ERRNO); /* See xe_pci_probe() */
@@ -820,7 +862,7 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
static void guc_um_init_params(struct xe_guc_ads *ads)
{
- u32 um_queue_offset = guc_ads_um_queues_offset(ads);
+ struct xe_bo *um_bo = ads->um_queue_bo;
struct xe_guc *guc = ads_to_guc(ads);
struct xe_device *xe = ads_to_xe(ads);
u64 base_dpa;
@@ -830,8 +872,14 @@ static void guc_um_init_params(struct xe_guc_ads *ads)
with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
- base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
- base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
+ if (um_bo) {
+ /* All USM platforms: UM queues in dedicated um_queue_bo */
+ base_ggtt = xe_bo_ggtt_addr(um_bo);
+ base_dpa = xe_bo_main_addr(um_bo, PAGE_SIZE);
+ } else {
+ /* Platform does not support USM: no UM queues, nothing to do */
+ return;
+ }
for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
/*
diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h
index 48a8e092023f..845c1fbd93a4 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h
@@ -16,6 +16,11 @@ struct xe_bo;
struct xe_guc_ads {
/** @bo: Xe BO for GuC ads blob */
struct xe_bo *bo;
+ /**
+ * @um_queue_bo: Dedicated BO for the HW fault ring (UM queues).
+ * NULL if the platform does not support USM.
+ */
+ struct xe_bo *um_queue_bo;
/** @golden_lrc_size: golden LRC size */
size_t golden_lrc_size;
/** @regset_size: size of register set passed to GuC for save/restore */
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v4 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX
2026-07-30 0:47 ` [PATCH v4 0/1] " Jia Yao
2026-07-30 0:47 ` [PATCH v4 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO Jia Yao
@ 2026-07-30 0:47 ` Jia Yao
2026-07-30 10:51 ` Matthew Auld
2026-07-30 0:47 ` [PATCH v4 3/3] drm/xe/guc_ads: use uncached mapping for UM queue BO Jia Yao
2 siblings, 1 reply; 17+ messages in thread
From: Jia Yao @ 2026-07-30 0:47 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.auld, gwan-gyeong.mun, stable, Jia Yao
On dGFX the original ADS BO is explicitly migrated to VRAM by
xe_guc_realloc_post_hwconfig() so that xe_bo_main_addr() returns a
real device-physical address (DPA) rather than an IOMMU IOVA. A
separate SYSTEM BO for the UM queues would not go through that migration
path, so its IOVA would differ from the physical address on systems
where pages are allocated above 4 GB. GuC/GAM accesses the UM queue
ring via base_dpa (with_dpa=true on pre-Xe3p), so an incorrect DPA
causes all-zero fault descriptors to be forwarded to the driver.
Use XE_BO_FLAG_VRAM_IF_DGFX() for the UM queue BO so that on dGFX the
BO is allocated directly in VRAM and xe_bo_main_addr() returns the
correct DPA without needing a post-hwconfig migration step.
Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Jia Yao <jia.yao@intel.com>
---
drivers/gpu/drm/xe/xe_guc.c | 6 ------
drivers/gpu/drm/xe/xe_guc_ads.c | 11 ++++++-----
2 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 21cf3edef922..4023700ff2a9 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -714,12 +714,6 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
if (ret)
return ret;
- if (guc->ads.um_queue_bo) {
- ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
- if (ret)
- return ret;
- }
-
return 0;
}
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 7f371f9c7268..53636333fb45 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -409,11 +409,12 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
GUC_UM_HW_QUEUE_MAX);
- bo = xe_managed_bo_create_pin_map(xe, tile, um_size,
- XE_BO_FLAG_SYSTEM |
- XE_BO_FLAG_GGTT |
- XE_BO_FLAG_GGTT_INVALIDATE |
- XE_BO_FLAG_PINNED_NORESTORE);
+ u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+ XE_BO_FLAG_GGTT |
+ XE_BO_FLAG_GGTT_INVALIDATE |
+ XE_BO_FLAG_PINNED_NORESTORE;
+
+ bo = xe_managed_bo_create_pin_map(xe, tile, um_size, um_flags);
if (IS_ERR(bo))
return PTR_ERR(bo);
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v4 3/3] drm/xe/guc_ads: use uncached mapping for UM queue BO
2026-07-30 0:47 ` [PATCH v4 0/1] " Jia Yao
2026-07-30 0:47 ` [PATCH v4 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO Jia Yao
2026-07-30 0:47 ` [PATCH v4 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX Jia Yao
@ 2026-07-30 0:47 ` Jia Yao
2026-07-30 9:49 ` Michal Wajdeczko
2026-07-30 11:23 ` Matthew Auld
2 siblings, 2 replies; 17+ messages in thread
From: Jia Yao @ 2026-07-30 0:47 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.auld, gwan-gyeong.mun, stable, Jia Yao
The HW unit that writes fault descriptors into the UM queue ring buffer
may not be coherent with the CPU cache. If a descriptor write is still
sitting in a GPU L3 cache line when GuC reads the slot, GuC sees the
stale (all-zero) content from DRAM and forwards an invalid descriptor to
the driver (Faulted Address = 0, ASID = 0).
Mark the UM queue BO as uncached (XE_BO_FLAG_NEEDS_UC) so that writes
bypass the cache and are immediately visible to GuC.
Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Jia Yao <jia.yao@intel.com>
---
drivers/gpu/drm/xe/xe_guc_ads.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 53636333fb45..76029575aa45 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -412,7 +412,8 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
XE_BO_FLAG_GGTT |
XE_BO_FLAG_GGTT_INVALIDATE |
- XE_BO_FLAG_PINNED_NORESTORE;
+ XE_BO_FLAG_PINNED_NORESTORE |
+ XE_BO_FLAG_NEEDS_UC;
bo = xe_managed_bo_create_pin_map(xe, tile, um_size, um_flags);
if (IS_ERR(bo))
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v4 3/3] drm/xe/guc_ads: use uncached mapping for UM queue BO
2026-07-30 0:47 ` [PATCH v4 3/3] drm/xe/guc_ads: use uncached mapping for UM queue BO Jia Yao
@ 2026-07-30 9:49 ` Michal Wajdeczko
2026-07-30 11:23 ` Matthew Auld
1 sibling, 0 replies; 17+ messages in thread
From: Michal Wajdeczko @ 2026-07-30 9:49 UTC (permalink / raw)
To: Jia Yao, intel-xe; +Cc: matthew.auld, gwan-gyeong.mun, stable
On 7/30/2026 2:47 AM, Jia Yao wrote:
> The HW unit that writes fault descriptors into the UM queue ring buffer
> may not be coherent with the CPU cache. If a descriptor write is still
> sitting in a GPU L3 cache line when GuC reads the slot, GuC sees the
> stale (all-zero) content from DRAM and forwards an invalid descriptor to
> the driver (Faulted Address = 0, ASID = 0).
>
> Mark the UM queue BO as uncached (XE_BO_FLAG_NEEDS_UC) so that writes
> bypass the cache and are immediately visible to GuC.
>
> Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
note that XE_BO_FLAG_NEEDS_UC flag is not available at this point
it was initially added as XE_BO_NEEDS_UC flag in a commit f15de1936f8d
and then renamed to XE_BO_FLAG_NEEDS_UC in commit 62742d126631451
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: stable@vger.kernel.org
> Signed-off-by: Jia Yao <jia.yao@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc_ads.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index 53636333fb45..76029575aa45 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -412,7 +412,8 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
> u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> XE_BO_FLAG_GGTT |
> XE_BO_FLAG_GGTT_INVALIDATE |
> - XE_BO_FLAG_PINNED_NORESTORE;
> + XE_BO_FLAG_PINNED_NORESTORE |
> + XE_BO_FLAG_NEEDS_UC;
>
> bo = xe_managed_bo_create_pin_map(xe, tile, um_size, um_flags);
> if (IS_ERR(bo))
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v4 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO
2026-07-30 0:47 ` [PATCH v4 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO Jia Yao
@ 2026-07-30 10:28 ` Matthew Auld
0 siblings, 0 replies; 17+ messages in thread
From: Matthew Auld @ 2026-07-30 10:28 UTC (permalink / raw)
To: Jia Yao, intel-xe; +Cc: gwan-gyeong.mun, stable
On 30/07/2026 01:47, Jia Yao wrote:
> xe_guc_ads_populate() calls xe_map_memset() on the ADS BO on every GT
> reset. The UM queue ring buffers were embedded in that same BO, so the
> memset discards fault descriptors already written by the GPU, causing
> GuC to forward an all-zero descriptor (Faulted Address = 0, ASID = 0).
>
> Move the UM queue ring buffers into a dedicated BO so they are not
> affected by the ADS memset.
>
> Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: stable@vger.kernel.org
> Signed-off-by: Jia Yao <jia.yao@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc.c | 6 ++
> drivers/gpu/drm/xe/xe_guc_ads.c | 98 ++++++++++++++++++++-------
> drivers/gpu/drm/xe/xe_guc_ads_types.h | 5 ++
> 3 files changed, 84 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 4023700ff2a9..21cf3edef922 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -714,6 +714,12 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
> if (ret)
> return ret;
>
> + if (guc->ads.um_queue_bo) {
> + ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
> + if (ret)
> + return ret;
> + }
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index c98454545a85..7f371f9c7268 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -16,6 +16,7 @@
> #include "regs/xe_gt_regs.h"
> #include "regs/xe_guc_regs.h"
> #include "xe_bo.h"
> +#include "xe_res_cursor.h"
> #include "xe_gt.h"
> #include "xe_gt_ccs_mode.h"
> #include "xe_gt_mcr.h"
> @@ -155,16 +156,6 @@ static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
> return PAGE_ALIGN(ads->capture_size);
> }
>
> -static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
> -{
> - struct xe_device *xe = ads_to_xe(ads);
> -
> - if (!xe->info.has_usm)
> - return 0;
> -
> - return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX;
> -}
> -
> static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)
> {
> return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size);
> @@ -205,22 +196,12 @@ static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
> return PAGE_ALIGN(offset);
> }
>
> -static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
> -{
> - u32 offset;
> -
> - offset = guc_ads_capture_offset(ads) +
> - guc_ads_capture_size(ads);
> -
> - return PAGE_ALIGN(offset);
> -}
> -
> static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
> {
> size_t offset;
>
> - offset = guc_ads_um_queues_offset(ads) +
> - guc_ads_um_queues_size(ads);
> + offset = guc_ads_capture_offset(ads) +
> + guc_ads_capture_size(ads);
>
> return PAGE_ALIGN(offset);
> }
> @@ -409,6 +390,67 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
>
> ads->bo = bo;
>
> + if (xe->info.has_usm) {
> + /*
> + * Allocate a separate BO for the HW fault ring (UM queues).
> + *
> + * xe_guc_ads_populate() clears the entire ADS BO via
> + * xe_map_memset() on every GT reset. Keeping the UM queues
> + * in a dedicated BO prevents that memset from discarding fault
> + * descriptors the GPU has already written into the ring,
> + * which would cause GuC to forward an all-zero descriptor to
> + * the driver (Faulted Address = 0, ASID = 0).
> + *
> + * Round the size up to the next power of two so that on iGPU
> + * (system memory, no IOMMU) the TTM pool issues a single
> + * alloc_pages(order=N) call, maximising the chance of getting
> + * a physically contiguous block. GuC requires contiguous DPA.
> + */
From our offline discussion I think is this is correct, however there
is no mention of this fix/change in the commit message? It only mentions
memset issue.
> + size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
> + GUC_UM_HW_QUEUE_MAX);
> +
> + bo = xe_managed_bo_create_pin_map(xe, tile, um_size,
> + XE_BO_FLAG_SYSTEM |
> + XE_BO_FLAG_GGTT |
> + XE_BO_FLAG_GGTT_INVALIDATE |
> + XE_BO_FLAG_PINNED_NORESTORE);
> + if (IS_ERR(bo))
> + return PTR_ERR(bo);
> +
> + /*
> + * On pre-Xe3p platforms, GAM (not GuC) accesses the UM queue
> + * ring via base_dpa, which must be a contiguous device physical
> + * address range. Without IOMMU, DMA addresses equal physical
> + * addresses and the allocator may return non-contiguous pages;
> + * verify contiguity. With IOMMU, the DMA mapping is a single
> + * contiguous IOVA so no check is needed.
> + */
> + if (unlikely(!device_iommu_mapped(xe->drm.dev)) &&
I think maybe drop the iommu check? Not sure if we can safely assume it
will always give single contig dma blob.
> + !xe_bo_is_vram(bo) &&
> + !xe_guc_using_main_gamctrl_queues(ads_to_guc(ads))) {
> + struct xe_res_cursor cur;
> + int i;
> +
> + xe_res_first_sg(xe_bo_sg(bo), 0,
> + GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX, &cur);
> + for (i = 1; i < GUC_UM_HW_QUEUE_MAX; i++) {
> + dma_addr_t expected = xe_res_dma(&cur) +
> + GUC_UM_QUEUE_SIZE;
I think we can maybe simplify with:
if (drm_prime_get_contiguous_size(xe_bo_sg(bo)) < queue size)
...
> +
> + xe_res_next(&cur, GUC_UM_QUEUE_SIZE);
> + if (xe_res_dma(&cur) != expected) {
> + drm_err(&xe->drm,
> + "UM fault queue %d is physically non-contiguous (got %pad, expected %pad); GAM requires contiguous DPA. Enable IOMMU (intel_iommu=on) to fix.\n",
> + i, &(dma_addr_t){xe_res_dma(&cur)},
> + &expected);
> + return -ENOMEM;
> + }
> + }
> + }
> +
> + ads->um_queue_bo = bo;
> + }
> +
> return 0;
> }
> ALLOW_ERROR_INJECTION(xe_guc_ads_init, ERRNO); /* See xe_pci_probe() */
> @@ -820,7 +862,7 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
>
> static void guc_um_init_params(struct xe_guc_ads *ads)
> {
> - u32 um_queue_offset = guc_ads_um_queues_offset(ads);
> + struct xe_bo *um_bo = ads->um_queue_bo;
> struct xe_guc *guc = ads_to_guc(ads);
> struct xe_device *xe = ads_to_xe(ads);
> u64 base_dpa;
> @@ -830,8 +872,14 @@ static void guc_um_init_params(struct xe_guc_ads *ads)
>
> with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
>
> - base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
> - base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
> + if (um_bo) {
> + /* All USM platforms: UM queues in dedicated um_queue_bo */
> + base_ggtt = xe_bo_ggtt_addr(um_bo);
> + base_dpa = xe_bo_main_addr(um_bo, PAGE_SIZE);
> + } else {
> + /* Platform does not support USM: no UM queues, nothing to do */
> + return;
> + }
>
> for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
> /*
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h
> index 48a8e092023f..845c1fbd93a4 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads_types.h
> +++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h
> @@ -16,6 +16,11 @@ struct xe_bo;
> struct xe_guc_ads {
> /** @bo: Xe BO for GuC ads blob */
> struct xe_bo *bo;
> + /**
> + * @um_queue_bo: Dedicated BO for the HW fault ring (UM queues).
> + * NULL if the platform does not support USM.
> + */
> + struct xe_bo *um_queue_bo;
> /** @golden_lrc_size: golden LRC size */
> size_t golden_lrc_size;
> /** @regset_size: size of register set passed to GuC for save/restore */
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v4 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX
2026-07-30 0:47 ` [PATCH v4 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX Jia Yao
@ 2026-07-30 10:51 ` Matthew Auld
2026-07-30 13:12 ` Matthew Auld
0 siblings, 1 reply; 17+ messages in thread
From: Matthew Auld @ 2026-07-30 10:51 UTC (permalink / raw)
To: Jia Yao, intel-xe; +Cc: gwan-gyeong.mun, stable
On 30/07/2026 01:47, Jia Yao wrote:
> On dGFX the original ADS BO is explicitly migrated to VRAM by
> xe_guc_realloc_post_hwconfig() so that xe_bo_main_addr() returns a
> real device-physical address (DPA) rather than an IOMMU IOVA. A
> separate SYSTEM BO for the UM queues would not go through that migration
> path, so its IOVA would differ from the physical address on systems
> where pages are allocated above 4 GB. GuC/GAM accesses the UM queue
> ring via base_dpa (with_dpa=true on pre-Xe3p), so an incorrect DPA
> causes all-zero fault descriptors to be forwarded to the driver.
I feel like I don't fully understand the explanation here. Is the issue
not just the contig requirement for base_dpa? We now use attempt a best
effort approach for system memory, however for dgpu we can go further
and use VRAM to guarantee that requirement. If that is all this is doing
then commit message can be simplified with something like:
"To fully guarantee the contig requirement for base_dpa, we can instead
just use VRAM for the um queue, on dgpu..."
>
> Use XE_BO_FLAG_VRAM_IF_DGFX() for the UM queue BO so that on dGFX the
> BO is allocated directly in VRAM and xe_bo_main_addr() returns the
> correct DPA without needing a post-hwconfig migration step.
>
> Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: stable@vger.kernel.org
> Signed-off-by: Jia Yao <jia.yao@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc.c | 6 ------
> drivers/gpu/drm/xe/xe_guc_ads.c | 11 ++++++-----
> 2 files changed, 6 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 21cf3edef922..4023700ff2a9 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -714,12 +714,6 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
> if (ret)
> return ret;
>
> - if (guc->ads.um_queue_bo) {
> - ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
> - if (ret)
> - return ret;
> - }
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index 7f371f9c7268..53636333fb45 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -409,11 +409,12 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
> size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
> GUC_UM_HW_QUEUE_MAX);
>
> - bo = xe_managed_bo_create_pin_map(xe, tile, um_size,
> - XE_BO_FLAG_SYSTEM |
> - XE_BO_FLAG_GGTT |
> - XE_BO_FLAG_GGTT_INVALIDATE |
> - XE_BO_FLAG_PINNED_NORESTORE);
> + u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> + XE_BO_FLAG_GGTT |
> + XE_BO_FLAG_GGTT_INVALIDATE |
> + XE_BO_FLAG_PINNED_NORESTORE;
> +
> + bo = xe_managed_bo_create_pin_map(xe, tile, um_size, um_flags);
> if (IS_ERR(bo))
> return PTR_ERR(bo);
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v4 3/3] drm/xe/guc_ads: use uncached mapping for UM queue BO
2026-07-30 0:47 ` [PATCH v4 3/3] drm/xe/guc_ads: use uncached mapping for UM queue BO Jia Yao
2026-07-30 9:49 ` Michal Wajdeczko
@ 2026-07-30 11:23 ` Matthew Auld
1 sibling, 0 replies; 17+ messages in thread
From: Matthew Auld @ 2026-07-30 11:23 UTC (permalink / raw)
To: Jia Yao, intel-xe; +Cc: gwan-gyeong.mun, stable
On 30/07/2026 01:47, Jia Yao wrote:
> The HW unit that writes fault descriptors into the UM queue ring buffer
> may not be coherent with the CPU cache. If a descriptor write is still
> sitting in a GPU L3 cache line when GuC reads the slot, GuC sees the
> stale (all-zero) content from DRAM and forwards an invalid descriptor to
> the driver (Faulted Address = 0, ASID = 0).
>
> Mark the UM queue BO as uncached (XE_BO_FLAG_NEEDS_UC) so that writes
> bypass the cache and are immediately visible to GuC.
>
> Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
As per Michal this is too old. I think we can instead do:
Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
Cc: <stable@vger.kernel.org> # v6.12+
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: stable@vger.kernel.org
> Signed-off-by: Jia Yao <jia.yao@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc_ads.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index 53636333fb45..76029575aa45 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -412,7 +412,8 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
> u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> XE_BO_FLAG_GGTT |
> XE_BO_FLAG_GGTT_INVALIDATE |
> - XE_BO_FLAG_PINNED_NORESTORE;
> + XE_BO_FLAG_PINNED_NORESTORE |
> + XE_BO_FLAG_NEEDS_UC;
>
> bo = xe_managed_bo_create_pin_map(xe, tile, um_size, um_flags);
> if (IS_ERR(bo))
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v4 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX
2026-07-30 10:51 ` Matthew Auld
@ 2026-07-30 13:12 ` Matthew Auld
0 siblings, 0 replies; 17+ messages in thread
From: Matthew Auld @ 2026-07-30 13:12 UTC (permalink / raw)
To: Jia Yao, intel-xe; +Cc: gwan-gyeong.mun, stable
On 30/07/2026 11:51, Matthew Auld wrote:
> On 30/07/2026 01:47, Jia Yao wrote:
>> On dGFX the original ADS BO is explicitly migrated to VRAM by
>> xe_guc_realloc_post_hwconfig() so that xe_bo_main_addr() returns a
>> real device-physical address (DPA) rather than an IOMMU IOVA. A
>> separate SYSTEM BO for the UM queues would not go through that migration
>> path, so its IOVA would differ from the physical address on systems
>> where pages are allocated above 4 GB. GuC/GAM accesses the UM queue
>> ring via base_dpa (with_dpa=true on pre-Xe3p), so an incorrect DPA
>> causes all-zero fault descriptors to be forwarded to the driver.
>
> I feel like I don't fully understand the explanation here. Is the issue
> not just the contig requirement for base_dpa? We now use attempt a best
> effort approach for system memory, however for dgpu we can go further
> and use VRAM to guarantee that requirement. If that is all this is doing
> then commit message can be simplified with something like:
>
> "To fully guarantee the contig requirement for base_dpa, we can instead
> just use VRAM for the um queue, on dgpu..."
Or is the issue that this has to always be in VRAM, since there is no
bit to say whether the DPA is system vs VRAM, like we do for the GGTT
pte? On dgpu, assumption is that this is then always VRAM, if using DPA?
If so, please make that clearer in the commit message.
>
>>
>> Use XE_BO_FLAG_VRAM_IF_DGFX() for the UM queue BO so that on dGFX the
>> BO is allocated directly in VRAM and xe_bo_main_addr() returns the
>> correct DPA without needing a post-hwconfig migration step.
>>
>> Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
>> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> Cc: Matthew Auld <matthew.auld@intel.com>
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Jia Yao <jia.yao@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_guc.c | 6 ------
>> drivers/gpu/drm/xe/xe_guc_ads.c | 11 ++++++-----
>> 2 files changed, 6 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>> index 21cf3edef922..4023700ff2a9 100644
>> --- a/drivers/gpu/drm/xe/xe_guc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>> @@ -714,12 +714,6 @@ static int xe_guc_realloc_post_hwconfig(struct
>> xe_guc *guc)
>> if (ret)
>> return ret;
>> - if (guc->ads.um_queue_bo) {
>> - ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc-
>> >ads.um_queue_bo);
>> - if (ret)
>> - return ret;
>> - }
>> -
>> return 0;
>> }
>> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/
>> xe_guc_ads.c
>> index 7f371f9c7268..53636333fb45 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
>> @@ -409,11 +409,12 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
>> size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
>> GUC_UM_HW_QUEUE_MAX);
>> - bo = xe_managed_bo_create_pin_map(xe, tile, um_size,
>> - XE_BO_FLAG_SYSTEM |
>> - XE_BO_FLAG_GGTT |
>> - XE_BO_FLAG_GGTT_INVALIDATE |
>> - XE_BO_FLAG_PINNED_NORESTORE);
>> + u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
>> + XE_BO_FLAG_GGTT |
>> + XE_BO_FLAG_GGTT_INVALIDATE |
>> + XE_BO_FLAG_PINNED_NORESTORE;
>> +
>> + bo = xe_managed_bo_create_pin_map(xe, tile, um_size, um_flags);
>> if (IS_ERR(bo))
>> return PTR_ERR(bo);
>
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2026-07-30 13:12 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
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2026-07-22 5:34 [PATCH v3 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO Jia Yao
2026-07-22 5:34 ` [PATCH v3 1/1] " Jia Yao
2026-07-22 9:18 ` Matthew Auld
2026-07-22 23:00 ` Gwan-gyeong Mun
2026-07-22 5:41 ` ✗ CI.checkpatch: warning for " Patchwork
2026-07-22 5:42 ` ✓ CI.KUnit: success " Patchwork
2026-07-22 6:17 ` ✓ Xe.CI.BAT: " Patchwork
2026-07-22 20:20 ` ✓ Xe.CI.FULL: " Patchwork
2026-07-30 0:47 ` [PATCH v4 0/1] " Jia Yao
2026-07-30 0:47 ` [PATCH v4 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO Jia Yao
2026-07-30 10:28 ` Matthew Auld
2026-07-30 0:47 ` [PATCH v4 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX Jia Yao
2026-07-30 10:51 ` Matthew Auld
2026-07-30 13:12 ` Matthew Auld
2026-07-30 0:47 ` [PATCH v4 3/3] drm/xe/guc_ads: use uncached mapping for UM queue BO Jia Yao
2026-07-30 9:49 ` Michal Wajdeczko
2026-07-30 11:23 ` Matthew Auld
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