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* [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate
@ 2026-05-11 12:28 Vinod Govindapillai
  2026-05-11 12:28 ` [PATCH v2 01/11] drm/i915/wm: clear the plane ddb_y entries on plane disable Vinod Govindapillai
                   ` (13 more replies)
  0 siblings, 14 replies; 18+ messages in thread
From: Vinod Govindapillai @ 2026-05-11 12:28 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: vinod.govindapillai, ville.syrjala

In xe3+, soc can lower the fabric frequency when the display
needs less bandwidth than the minimum GV point.

v1: pmdemand peak bw is updated to 20GB/s is the required data rate
    is low and less than 20GB/s even though there are no QGV point
    with 20GB/s. Only the peak_ww is changed based on the conditions 

v2: At the time of BW info calculations, a new row is inserted with
    peakbw as 20GB/s and deratebw also to 20GB/s and the required
    pmdemand peakbw is automatically calculated based on the old
    logic.    

Vinod Govindapillai (11):
  drm/i915/wm: clear the plane ddb_y entries on plane disable
  drm/i915/pm_demand: introduce HAS_PMDEMAND macro
  drm/i915/display: sagv pre/post plane calls to check pmdemand support
  drm/i915/bw: Extract icl_init_qgv_info()
  drm/i915/bw: sort the qgv points based on the dclk
  drm/i915/bw: update the routine to get max dclk from qgv points
  drm/i915/bw: update the routine to find the peakbw in MTL
  drm/i915/bw: update the tile-y dependency based on the display version
  drm/i915/bw: consolidate the debug info of bw/dgv/psf data
  drm/i915/bw: extract update_sagv_status()
  drm/i915/bw: insert a sw bw info entry to cater low data rate usecases

 drivers/gpu/drm/i915/display/intel_bw.c       | 215 +++++++++++++-----
 .../drm/i915/display/intel_display_device.h   |   2 +
 .../gpu/drm/i915/display/intel_display_irq.c  |   2 +-
 .../drm/i915/display/intel_display_power.c    |   4 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  12 +-
 drivers/gpu/drm/i915/display/skl_watermark.c  |   8 +-
 6 files changed, 178 insertions(+), 65 deletions(-)

-- 
2.43.0


^ permalink raw reply	[flat|nested] 18+ messages in thread

* [PATCH v2 01/11] drm/i915/wm: clear the plane ddb_y entries on plane disable
  2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
@ 2026-05-11 12:28 ` Vinod Govindapillai
  2026-05-11 12:28 ` [PATCH v2 02/11] drm/i915/pm_demand: introduce HAS_PMDEMAND macro Vinod Govindapillai
                   ` (12 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Vinod Govindapillai @ 2026-05-11 12:28 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: vinod.govindapillai, ville.syrjala

The UV/Y plane DDB entriess are never cleared on
sk_wm_plane_disable_noatomic() and can leave stale DDB state
for NV12 planes on pre-Gen11 devices

Fixes: d34b59d5ba41 ("drm/i915: Add skl_wm_plane_disable_noatomic()")
Assisted-by: Copilot:claude-sonnet-4.6
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 4bffa27ce02c..c942ccfe6897 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3858,7 +3858,7 @@ void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc,
 		return;
 
 	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0);
-	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0);
+	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb_y[plane->id], 0, 0);
 
 	crtc_state->wm.skl.plane_min_ddb[plane->id] = 0;
 	crtc_state->wm.skl.plane_interim_ddb[plane->id] = 0;
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH v2 02/11] drm/i915/pm_demand: introduce HAS_PMDEMAND macro
  2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
  2026-05-11 12:28 ` [PATCH v2 01/11] drm/i915/wm: clear the plane ddb_y entries on plane disable Vinod Govindapillai
@ 2026-05-11 12:28 ` Vinod Govindapillai
  2026-05-11 12:28 ` [PATCH v2 03/11] drm/i915/display: sagv pre/post plane calls to check pmdemand support Vinod Govindapillai
                   ` (11 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Vinod Govindapillai @ 2026-05-11 12:28 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: vinod.govindapillai, ville.syrjala

PM demand feature introduces a new way to set bw, power and
performance requirements to pcode from display version 14 onwards.
Use an identifiable name as a macro to distinguish the pm demand
specific changes in the code.

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c             |  4 ++--
 drivers/gpu/drm/i915/display/intel_display_device.h |  1 +
 drivers/gpu/drm/i915/display/intel_display_irq.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_display_power.c  |  4 ++--
 drivers/gpu/drm/i915/display/intel_pmdemand.c       | 12 ++++++------
 5 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 9c3a9bbb49f6..d99e921df0b9 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -181,7 +181,7 @@ static int icl_pcode_restrict_qgv_points(struct intel_display *display,
 {
 	int ret;
 
-	if (DISPLAY_VER(display) >= 14)
+	if (HAS_PMDEMAND(display))
 		return 0;
 
 	/* bspec says to keep retrying for at least 1 ms */
@@ -1206,7 +1206,7 @@ static int intel_bw_check_qgv_points(struct intel_display *display,
 
 	data_rate = DIV_ROUND_UP(data_rate, 1000);
 
-	if (DISPLAY_VER(display) >= 14)
+	if (HAS_PMDEMAND(display))
 		return mtl_find_qgv_points(display, data_rate, num_active_planes,
 					   new_bw_state);
 	else
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 074e3ba8fb77..65283286771a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -194,6 +194,7 @@ struct intel_display_platforms {
 #define HAS_OVERLAY(__display)		(DISPLAY_INFO(__display)->has_overlay)
 #define HAS_PIPEDMC(__display)		(DISPLAY_VER(__display) >= 12)
 #define HAS_PIXEL_NORMALIZER(__display)	(DISPLAY_VER(__display) >= 35)
+#define HAS_PMDEMAND(__display)		(DISPLAY_VER(__display) >= 14)
 #define HAS_PSR(__display)		(DISPLAY_INFO(__display)->has_psr)
 #define HAS_PSR_HW_TRACKING(__display)	(DISPLAY_INFO(__display)->has_psr_hw_tracking)
 #define HAS_PSR2_SEL_FETCH(__display)	(DISPLAY_VER(__display) >= 12)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 70c1bba7c0a8..69bc9101d21d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1260,7 +1260,7 @@ gen8_de_misc_irq_handler(struct intel_display *display, u32 iir)
 		}
 	}
 
-	if (DISPLAY_VER(display) >= 14) {
+	if (HAS_PMDEMAND(display)) {
 		if (iir & (XELPDP_PMDEMAND_RSP |
 			   XELPDP_PMDEMAND_RSPTOUT_ERR)) {
 			if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 80ecf373fb19..94e025e231d5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1122,7 +1122,7 @@ static void gen9_dbuf_enable(struct intel_display *display)
 
 	slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices;
 
-	if (DISPLAY_VER(display) >= 14)
+	if (HAS_PMDEMAND(display))
 		intel_pmdemand_program_dbuf(display, slices_mask);
 
 	/*
@@ -1136,7 +1136,7 @@ static void gen9_dbuf_disable(struct intel_display *display)
 {
 	gen9_dbuf_slices_update(display, 0);
 
-	if (DISPLAY_VER(display) >= 14)
+	if (HAS_PMDEMAND(display))
 		intel_pmdemand_program_dbuf(display, 0);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index 7819b724795b..3a2e7825eb52 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -152,7 +152,7 @@ intel_pmdemand_update_phys_mask(struct intel_display *display,
 {
 	enum phy phy;
 
-	if (DISPLAY_VER(display) < 14)
+	if (!HAS_PMDEMAND(display))
 		return;
 
 	if (!encoder)
@@ -174,7 +174,7 @@ intel_pmdemand_update_port_clock(struct intel_display *display,
 				 struct intel_pmdemand_state *pmdemand_state,
 				 enum pipe pipe, int port_clock)
 {
-	if (DISPLAY_VER(display) < 14)
+	if (!HAS_PMDEMAND(display))
 		return;
 
 	pmdemand_state->ddi_clocks[pipe] = port_clock;
@@ -326,7 +326,7 @@ int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
 	const struct intel_dbuf_state *new_dbuf_state;
 	struct intel_pmdemand_state *new_pmdemand_state;
 
-	if (DISPLAY_VER(display) < 14)
+	if (!HAS_PMDEMAND(display))
 		return 0;
 
 	if (!intel_pmdemand_needs_update(state))
@@ -406,7 +406,7 @@ intel_pmdemand_init_pmdemand_params(struct intel_display *display,
 {
 	u32 reg1, reg2;
 
-	if (DISPLAY_VER(display) < 14)
+	if (!HAS_PMDEMAND(display))
 		return;
 
 	mutex_lock(&display->pmdemand.lock);
@@ -639,7 +639,7 @@ void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
 	const struct intel_pmdemand_state *old_pmdemand_state =
 		intel_atomic_get_old_pmdemand_state(state);
 
-	if (DISPLAY_VER(display) < 14)
+	if (!HAS_PMDEMAND(display))
 		return;
 
 	if (!new_pmdemand_state ||
@@ -662,7 +662,7 @@ void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
 	const struct intel_pmdemand_state *old_pmdemand_state =
 		intel_atomic_get_old_pmdemand_state(state);
 
-	if (DISPLAY_VER(display) < 14)
+	if (!HAS_PMDEMAND(display))
 		return;
 
 	if (!new_pmdemand_state ||
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH v2 03/11] drm/i915/display: sagv pre/post plane calls to check pmdemand support
  2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
  2026-05-11 12:28 ` [PATCH v2 01/11] drm/i915/wm: clear the plane ddb_y entries on plane disable Vinod Govindapillai
  2026-05-11 12:28 ` [PATCH v2 02/11] drm/i915/pm_demand: introduce HAS_PMDEMAND macro Vinod Govindapillai
@ 2026-05-11 12:28 ` Vinod Govindapillai
  2026-05-11 12:28 ` [PATCH v2 04/11] drm/i915/bw: Extract icl_init_qgv_info() Vinod Govindapillai
                   ` (10 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Vinod Govindapillai @ 2026-05-11 12:28 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: vinod.govindapillai, ville.syrjala

For pmdemand cases, no need to even calculate the masks based
on the qgv points index. Though the current logic avoids setting
the registers based on the pmdemand support, some qgv point masks
are compared in vain and do nothing. So leave early if pmdemand
is supported.

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index c942ccfe6897..30a2031aa613 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -275,6 +275,9 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
 	if (!intel_has_sagv(display))
 		return;
 
+	if (HAS_PMDEMAND(display))
+		return;
+
 	if (DISPLAY_VER(display) >= 11)
 		icl_sagv_pre_plane_update(state);
 	else
@@ -295,6 +298,9 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
 	if (!intel_has_sagv(display))
 		return;
 
+	if (HAS_PMDEMAND(display))
+		return;
+
 	if (DISPLAY_VER(display) >= 11)
 		icl_sagv_post_plane_update(state);
 	else
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH v2 04/11] drm/i915/bw: Extract icl_init_qgv_info()
  2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
                   ` (2 preceding siblings ...)
  2026-05-11 12:28 ` [PATCH v2 03/11] drm/i915/display: sagv pre/post plane calls to check pmdemand support Vinod Govindapillai
@ 2026-05-11 12:28 ` Vinod Govindapillai
  2026-05-11 12:28 ` [PATCH v2 05/11] drm/i915/bw: sort the qgv points based on the dclk Vinod Govindapillai
                   ` (9 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Vinod Govindapillai @ 2026-05-11 12:28 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: vinod.govindapillai, ville.syrjala

Simplify the initialization of qgv points info by extracting
the code to initialize the qgv points info from dram info based
on the memory type.

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 23 +++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index d99e921df0b9..e9cfa3edd09e 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -238,13 +238,11 @@ intel_read_qgv_point_info(struct intel_display *display,
 		return icl_pcode_read_qgv_point_info(display, sp, point);
 }
 
-static int icl_get_qgv_points(struct intel_display *display,
-			      const struct dram_info *dram_info,
-			      struct intel_qgv_info *qi,
-			      bool is_y_tile)
+static int icl_init_qgv_info(struct intel_display *display,
+			     const struct dram_info *dram_info,
+			     struct intel_qgv_info *qi,
+			     bool is_y_tile)
 {
-	int i, ret;
-
 	qi->num_points = dram_info->num_qgv_points;
 	qi->num_psf_points = dram_info->num_psf_gv_points;
 
@@ -316,6 +314,19 @@ static int icl_get_qgv_points(struct intel_display *display,
 		qi->max_numchannels = 1;
 	}
 
+	return 0;
+}
+
+static int icl_get_qgv_points(struct intel_display *display,
+			      const struct dram_info *dram_info,
+			      struct intel_qgv_info *qi,
+			      bool is_y_tile)
+{
+	int i, ret;
+
+	if (icl_init_qgv_info(display, dram_info, qi, is_y_tile))
+		return -EINVAL;
+
 	if (drm_WARN_ON(display->drm,
 			qi->num_points > ARRAY_SIZE(qi->points)))
 		qi->num_points = ARRAY_SIZE(qi->points);
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH v2 05/11] drm/i915/bw: sort the qgv points based on the dclk
  2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
                   ` (3 preceding siblings ...)
  2026-05-11 12:28 ` [PATCH v2 04/11] drm/i915/bw: Extract icl_init_qgv_info() Vinod Govindapillai
@ 2026-05-11 12:28 ` Vinod Govindapillai
  2026-05-11 12:28 ` [PATCH v2 06/11] drm/i915/bw: update the routine to get max dclk from qgv points Vinod Govindapillai
                   ` (8 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Vinod Govindapillai @ 2026-05-11 12:28 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: vinod.govindapillai, ville.syrjala

QGV points reported from BIOS are not in any sorted order. But the
this order cannot be modified as the pcode was expecting the qgv
point index on pre display 14 versions. But after the introduction
of pmdemand, pcode is expecting the peak bw of the selected qgv
point. But because this point is not sorted, we would have to go
through all of these points to find any exact match. So sort the
qgv point based on the dclk and this sorted order will benefit
in all calculations which need to find appropriate qgv point.

Assisted-by: Copilot:claude-sonnet-4.6
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index e9cfa3edd09e..7b8801a88cb2 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -7,6 +7,8 @@
 #include <drm/drm_print.h>
 #include <drm/intel/intel_pcode_regs.h>
 
+#include <linux/sort.h>
+
 #include "intel_bw.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
@@ -317,6 +319,20 @@ static int icl_init_qgv_info(struct intel_display *display,
 	return 0;
 }
 
+static int qgv_point_cmp(const void *a, const void *b)
+{
+	const struct intel_qgv_point *pa = a;
+	const struct intel_qgv_point *pb = b;
+
+	return pa->dclk - pb->dclk;
+}
+
+static void intel_sort_qgv_points(struct intel_qgv_info *qi)
+{
+	sort(qi->points, qi->num_points, sizeof(*qi->points),
+	     qgv_point_cmp, NULL);
+}
+
 static int icl_get_qgv_points(struct intel_display *display,
 			      const struct dram_info *dram_info,
 			      struct intel_qgv_info *qi,
@@ -346,6 +362,9 @@ static int icl_get_qgv_points(struct intel_display *display,
 			    sp->t_rcd, sp->t_rc);
 	}
 
+	if (HAS_PMDEMAND(display))
+		intel_sort_qgv_points(qi);
+
 	if (qi->num_psf_points > 0) {
 		ret = adls_pcode_read_psf_gv_point_info(display, qi->psf_points);
 		if (ret) {
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH v2 06/11] drm/i915/bw: update the routine to get max dclk from qgv points
  2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
                   ` (4 preceding siblings ...)
  2026-05-11 12:28 ` [PATCH v2 05/11] drm/i915/bw: sort the qgv points based on the dclk Vinod Govindapillai
@ 2026-05-11 12:28 ` Vinod Govindapillai
  2026-05-11 12:28 ` [PATCH v2 07/11] drm/i915/bw: update the routine to find the peakbw in MTL Vinod Govindapillai
                   ` (7 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Vinod Govindapillai @ 2026-05-11 12:28 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: vinod.govindapillai, ville.syrjala

As the qgv points are in the sorted order in pmdemand supported
versions, get the dclk from last qgv point.

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 7b8801a88cb2..f05fdb5f24c9 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -391,11 +391,19 @@ static int adl_calc_psf_bw(int clk)
 	return DIV_ROUND_CLOSEST(64 * clk * 100, 6);
 }
 
-static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
+static int icl_sagv_max_dclk(struct intel_display *display,
+			     const struct intel_qgv_info *qi)
 {
 	u16 dclk = 0;
 	int i;
 
+	/* QGV points are in sorted order in pmdemand supported versions */
+	if (HAS_PMDEMAND(display)) {
+		int max_point = max(0, qi->num_points - 1);
+
+		return qi->points[max_point].dclk;
+	}
+
 	for (i = 0; i < qi->num_points; i++)
 		dclk = max(dclk, qi->points[i].dclk);
 
@@ -495,7 +503,7 @@ static int icl_get_bw_info(struct intel_display *display,
 		return ret;
 	}
 
-	dclk_max = icl_sagv_max_dclk(&qi);
+	dclk_max = icl_sagv_max_dclk(display, &qi);
 	maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
 	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
 	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
@@ -581,7 +589,7 @@ static int tgl_get_bw_info(struct intel_display *display,
 	if (qi.max_numchannels != 0)
 		num_channels = min_t(u8, num_channels, qi.max_numchannels);
 
-	dclk_max = icl_sagv_max_dclk(&qi);
+	dclk_max = icl_sagv_max_dclk(display, &qi);
 
 	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
 	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
@@ -705,7 +713,7 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
 		return ret;
 	}
 
-	peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
+	peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(display, &qi);
 	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
 
 	for (i = 0; i < qi.num_points; i++) {
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH v2 07/11] drm/i915/bw: update the routine to find the peakbw in MTL
  2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
                   ` (5 preceding siblings ...)
  2026-05-11 12:28 ` [PATCH v2 06/11] drm/i915/bw: update the routine to get max dclk from qgv points Vinod Govindapillai
@ 2026-05-11 12:28 ` Vinod Govindapillai
  2026-05-11 12:28 ` [PATCH v2 08/11] drm/i915/bw: update the tile-y dependency based on the display version Vinod Govindapillai
                   ` (6 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Vinod Govindapillai @ 2026-05-11 12:28 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: vinod.govindapillai, ville.syrjala

As the QGV points are sorted based on dclk for pmdemand cases,
there is no need to go through the entire QGV points to find
out the acceptable peak bw. We could break the loop as soon as
we find out the first QGV point with the acceptable deratedbw
for the current display required bw.

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index f05fdb5f24c9..177c3fd8f74a 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -1080,10 +1080,8 @@ static int mtl_find_qgv_points(struct intel_display *display,
 			       unsigned int num_active_planes,
 			       struct intel_bw_state *new_bw_state)
 {
-	unsigned int best_rate = UINT_MAX;
 	unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;
 	unsigned int qgv_peak_bw  = 0;
-	int i;
 	int ret;
 
 	ret = intel_atomic_lock_global_state(&new_bw_state->base);
@@ -1105,7 +1103,7 @@ static int mtl_find_qgv_points(struct intel_display *display,
 	 * Find the best QGV point by comparing the data_rate with max data rate
 	 * offered per plane group
 	 */
-	for (i = 0; i < num_qgv_points; i++) {
+	for (int i = 0; i < num_qgv_points; i++) {
 		unsigned int bw_index =
 			tgl_max_bw_index(display, num_active_planes, i);
 		unsigned int max_data_rate;
@@ -1118,13 +1116,8 @@ static int mtl_find_qgv_points(struct intel_display *display,
 		if (max_data_rate < data_rate)
 			continue;
 
-		if (max_data_rate - data_rate < best_rate) {
-			best_rate = max_data_rate - data_rate;
-			qgv_peak_bw = display->bw.max[bw_index].peakbw[i];
-		}
-
-		drm_dbg_kms(display->drm, "QGV point %d: max bw %d required %d qgv_peak_bw: %d\n",
-			    i, max_data_rate, data_rate, qgv_peak_bw);
+		qgv_peak_bw = display->bw.max[bw_index].peakbw[i];
+		break;
 	}
 
 	drm_dbg_kms(display->drm, "Matching peaks QGV bw: %d for required data rate: %d\n",
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH v2 08/11] drm/i915/bw: update the tile-y dependency based on the display version
  2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
                   ` (6 preceding siblings ...)
  2026-05-11 12:28 ` [PATCH v2 07/11] drm/i915/bw: update the routine to find the peakbw in MTL Vinod Govindapillai
@ 2026-05-11 12:28 ` Vinod Govindapillai
  2026-05-11 12:28 ` [PATCH v2 09/11] drm/i915/bw: consolidate the debug info of bw/dgv/psf data Vinod Govindapillai
                   ` (5 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Vinod Govindapillai @ 2026-05-11 12:28 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: vinod.govindapillai, ville.syrjala

Consolidate the tile-y dependency into a separate function and
use it to determine whether tile-y need to take into account for
the bw calculations. Especially for post MTL cases, as per the
bspec, no need to take the tile_y into account for the
de interleave values.

Bspec: 64631, 68859
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 177c3fd8f74a..858da1710a61 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -483,12 +483,21 @@ static const struct intel_sa_info xe3lpd_3002_sa_info = {
 	.derating = 10,
 };
 
+static bool is_tile_y_factored(struct intel_display *display)
+{
+	/* TGL supports Y-tile for LPDDR4/5, but not for DDR4 */
+	if (DISPLAY_VER(display) >= 14)
+		return false;
+
+	return true;
+}
+
 static int icl_get_bw_info(struct intel_display *display,
 			   const struct dram_info *dram_info,
 			   const struct intel_sa_info *sa)
 {
 	struct intel_qgv_info qi = {};
-	bool is_y_tile = true; /* assume y tile may be used */
+	bool is_y_tile = is_tile_y_factored(display);
 	int num_channels = max_t(u8, 1, dram_info->num_channels);
 	int ipqdepth, ipqdepthpch = 16;
 	int dclk_max;
@@ -559,7 +568,7 @@ static int tgl_get_bw_info(struct intel_display *display,
 			   const struct intel_sa_info *sa)
 {
 	struct intel_qgv_info qi = {};
-	bool is_y_tile = true; /* assume y tile may be used */
+	bool is_y_tile = is_tile_y_factored(display);
 	int num_channels = max_t(u8, 1, dram_info->num_channels);
 	int ipqdepth, ipqdepthpch = 16;
 	int dclk_max;
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH v2 09/11] drm/i915/bw: consolidate the debug info of bw/dgv/psf data
  2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
                   ` (7 preceding siblings ...)
  2026-05-11 12:28 ` [PATCH v2 08/11] drm/i915/bw: update the tile-y dependency based on the display version Vinod Govindapillai
@ 2026-05-11 12:28 ` Vinod Govindapillai
  2026-05-12 11:49   ` Jani Nikula
  2026-05-11 12:28 ` [PATCH v2 10/11] drm/i915/bw: extract update_sagv_status() Vinod Govindapillai
                   ` (4 subsequent siblings)
  13 siblings, 1 reply; 18+ messages in thread
From: Vinod Govindapillai @ 2026-05-11 12:28 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: vinod.govindapillai, ville.syrjala

Consolidate all the detaills about the bw, gqv and psf gv into
a common function and present it in an organised format

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 40 +++++++++++++++++--------
 1 file changed, 27 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 858da1710a61..0bda13a3e31b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -483,6 +483,28 @@ static const struct intel_sa_info xe3lpd_3002_sa_info = {
 	.derating = 10,
 };
 
+static void debug_print_bw_info(struct intel_display *display)
+{
+	int num_groups = ARRAY_SIZE(display->bw.max);
+	int i;
+
+	for (i = 0; i < num_groups; i++) {
+		struct intel_bw_info *bi = &display->bw.max[i];
+		int j;
+
+		drm_dbg_kms(display->drm, "BW%d: num_planes=%d num_qgv_points:%d\n",
+			    i, bi->num_planes, bi->num_qgv_points);
+
+		for (j = 0; j < bi->num_qgv_points; j++)
+			drm_dbg_kms(display->drm, "\tQGV %d: deratedbw=%u peakbw=%u\n",
+				    j,  bi->deratedbw[j], bi->peakbw[j]);
+
+		for (j = 0; j < bi->num_psf_gv_points; j++)
+			drm_dbg_kms(display->drm, "\tPSF GV %d bw=%u\n",
+				    j, bi->psf_bw[j]);
+	}
+}
+
 static bool is_tile_y_factored(struct intel_display *display)
 {
 	/* TGL supports Y-tile for LPDDR4/5, but not for DDR4 */
@@ -544,12 +566,11 @@ static int icl_get_bw_info(struct intel_display *display,
 
 			bi->deratedbw[j] = min(maxdebw,
 					       bw * (100 - sa->derating) / 100);
-
-			drm_dbg_kms(display->drm,
-				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
-				    i, j, bi->num_planes, bi->deratedbw[j]);
 		}
 	}
+
+	debug_print_bw_info(display);
+
 	/*
 	 * In case if SAGV is disabled in BIOS, we always get 1
 	 * SAGV point, but we can't send PCode commands to restrict it
@@ -650,24 +671,17 @@ static int tgl_get_bw_info(struct intel_display *display,
 			bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
 							  num_channels *
 							  qi.channel_width, 8);
-
-			drm_dbg_kms(display->drm,
-				    "BW%d / QGV %d: num_planes=%d deratedbw=%u peakbw: %u\n",
-				    i, j, bi->num_planes, bi->deratedbw[j],
-				    bi->peakbw[j]);
 		}
 
 		for (j = 0; j < qi.num_psf_points; j++) {
 			const struct intel_psf_gv_point *sp = &qi.psf_points[j];
 
 			bi->psf_bw[j] = adl_calc_psf_bw(sp->clk);
-
-			drm_dbg_kms(display->drm,
-				    "BW%d / PSF GV %d: num_planes=%d bw=%u\n",
-				    i, j, bi->num_planes, bi->psf_bw[j]);
 		}
 	}
 
+	debug_print_bw_info(display);
+
 	/*
 	 * In case if SAGV is disabled in BIOS, we always get 1
 	 * SAGV point, but we can't send PCode commands to restrict it
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH v2 10/11] drm/i915/bw: extract update_sagv_status()
  2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
                   ` (8 preceding siblings ...)
  2026-05-11 12:28 ` [PATCH v2 09/11] drm/i915/bw: consolidate the debug info of bw/dgv/psf data Vinod Govindapillai
@ 2026-05-11 12:28 ` Vinod Govindapillai
  2026-05-11 12:28 ` [PATCH v2 11/11] drm/i915/bw: insert a sw bw info entry to cater low data rate usecases Vinod Govindapillai
                   ` (3 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Vinod Govindapillai @ 2026-05-11 12:28 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: vinod.govindapillai, ville.syrjala

Extract the code to update the sagv status based on the number of
QGV points into a separate function and use it.

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 33 +++++++++++--------------
 1 file changed, 15 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 0bda13a3e31b..938c0294c251 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -505,6 +505,19 @@ static void debug_print_bw_info(struct intel_display *display)
 	}
 }
 
+static void update_sagv_status(struct intel_display *display, int qgv_points)
+{
+	/*
+	 * In case if SAGV is disabled in BIOS, we always get 1
+	 * SAGV point, but we can't send PCode commands to restrict it
+	 * as it will fail and pointless anyway.
+	 */
+	if (qgv_points == 1)
+		display->sagv.status = I915_SAGV_NOT_CONTROLLED;
+	else
+		display->sagv.status = I915_SAGV_ENABLED;
+}
+
 static bool is_tile_y_factored(struct intel_display *display)
 {
 	/* TGL supports Y-tile for LPDDR4/5, but not for DDR4 */
@@ -571,15 +584,7 @@ static int icl_get_bw_info(struct intel_display *display,
 
 	debug_print_bw_info(display);
 
-	/*
-	 * In case if SAGV is disabled in BIOS, we always get 1
-	 * SAGV point, but we can't send PCode commands to restrict it
-	 * as it will fail and pointless anyway.
-	 */
-	if (qi.num_points == 1)
-		display->sagv.status = I915_SAGV_NOT_CONTROLLED;
-	else
-		display->sagv.status = I915_SAGV_ENABLED;
+	update_sagv_status(display, qi.num_points);
 
 	return 0;
 }
@@ -682,15 +687,7 @@ static int tgl_get_bw_info(struct intel_display *display,
 
 	debug_print_bw_info(display);
 
-	/*
-	 * In case if SAGV is disabled in BIOS, we always get 1
-	 * SAGV point, but we can't send PCode commands to restrict it
-	 * as it will fail and pointless anyway.
-	 */
-	if (qi.num_points == 1)
-		display->sagv.status = I915_SAGV_NOT_CONTROLLED;
-	else
-		display->sagv.status = I915_SAGV_ENABLED;
+	update_sagv_status(display, qi.num_points);
 
 	return 0;
 }
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH v2 11/11] drm/i915/bw: insert a sw bw info entry to cater low data rate usecases
  2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
                   ` (9 preceding siblings ...)
  2026-05-11 12:28 ` [PATCH v2 10/11] drm/i915/bw: extract update_sagv_status() Vinod Govindapillai
@ 2026-05-11 12:28 ` Vinod Govindapillai
  2026-05-12 11:51   ` Jani Nikula
  2026-05-11 16:28 ` ✓ CI.KUnit: success for drm/i915/display: reduce the pm demand peak bw based on display data rate Patchwork
                   ` (2 subsequent siblings)
  13 siblings, 1 reply; 18+ messages in thread
From: Vinod Govindapillai @ 2026-05-11 12:28 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: vinod.govindapillai, ville.syrjala

In xe3+, soc can lower the fabric frequency when the display
needs less bandwidth than the minimum GV point. This threshold
has been defined as 20GB/s. To enable this,

Add a new low bw info point with this peakbw threshold of 20GB/s
based on the following conditions:
1. Only for xe3+ versions
2. There is at least one QGV point
3. Number QGV points is less than 8
4. Lowest peak bw across all the QGV point is less than 20 GB/s
5. And the derated bw is in the lowest peak bw qgv point is also
   less than this threshold of 20GB/s

This will make the driver to send this new threshold of 20GB/s
as the pmdemand request whenever the bw required for a usecase
is less than 20GB/s. The current pcode can handle this lower
peakbw value and adjust the fabric frequency accordingly.

Bspec: 68880
Assisted-by: Copilot:claude-sonnet-4.6
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c       | 54 +++++++++++++++++++
 .../drm/i915/display/intel_display_device.h   |  1 +
 2 files changed, 55 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 938c0294c251..747279075e29 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -54,6 +54,8 @@ struct intel_qgv_point {
 
 #define DEPROGBWPCLIMIT		60
 
+#define PEAK_BW_THRESHOLD	20000
+
 struct intel_psf_gv_point {
 	u8 clk; /* clock in multiples of 16.6666 MHz */
 };
@@ -589,6 +591,50 @@ static int icl_get_bw_info(struct intel_display *display,
 	return 0;
 }
 
+static bool xe3_check_lower_peakbw(struct intel_display *display,
+				   const struct intel_qgv_info *qi,
+				   int num_channels)
+{
+	unsigned int lowest_peakbw;
+
+	if (!HAS_PEAK_BW_THRESHOLD(display))
+		return false;
+
+	if (qi->num_points >= I915_NUM_QGV_POINTS) {
+		drm_warn(display->drm, "Cannot insert lowest QGV point, not enough space\n");
+		return false;
+	}
+
+	lowest_peakbw = DIV_ROUND_CLOSEST(qi->points[0].dclk *
+					  qi->channel_width * num_channels, 8);
+	if (lowest_peakbw <= PEAK_BW_THRESHOLD) {
+		drm_dbg_kms(display->drm,
+			    "Lowest QGV point has peak BW %u MB/s, no need to insert lower point\n",
+			    lowest_peakbw);
+		return false;
+	}
+
+	return true;
+}
+
+static void xe3_insert_lowest_qgv_point(struct intel_display *display,
+					struct intel_bw_info *bi)
+{
+	if (bi->num_qgv_points >= ARRAY_SIZE(bi->deratedbw))
+		return;
+
+	memmove(&bi->deratedbw[1], &bi->deratedbw[0],
+		bi->num_qgv_points * sizeof(*bi->deratedbw));
+
+	memmove(&bi->peakbw[1], &bi->peakbw[0],
+		bi->num_qgv_points * sizeof(*bi->peakbw));
+
+	/* Keep the derated bandwidth as the threshold*/
+	bi->deratedbw[0] = PEAK_BW_THRESHOLD;
+	bi->peakbw[0] = PEAK_BW_THRESHOLD;
+	bi->num_qgv_points++;
+}
+
 static int tgl_get_bw_info(struct intel_display *display,
 			   const struct dram_info *dram_info,
 			   const struct intel_sa_info *sa)
@@ -598,6 +644,7 @@ static int tgl_get_bw_info(struct intel_display *display,
 	int num_channels = max_t(u8, 1, dram_info->num_channels);
 	int ipqdepth, ipqdepthpch = 16;
 	int dclk_max;
+	bool insert_low_peakbw;
 	int maxdebw, peakbw;
 	int clperchgroup;
 	int num_groups = ARRAY_SIZE(display->bw.max);
@@ -636,6 +683,10 @@ static int tgl_get_bw_info(struct intel_display *display,
 	 */
 	clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * qi.deinterleave;
 
+	insert_low_peakbw = xe3_check_lower_peakbw(display, &qi, num_channels);
+
+	display->bw.max[i].num_planes = 0;
+
 	for (i = 0; i < num_groups; i++) {
 		struct intel_bw_info *bi = &display->bw.max[i];
 		struct intel_bw_info *bi_next;
@@ -678,6 +729,9 @@ static int tgl_get_bw_info(struct intel_display *display,
 							  qi.channel_width, 8);
 		}
 
+		if (insert_low_peakbw)
+			xe3_insert_lowest_qgv_point(display, bi);
+
 		for (j = 0; j < qi.num_psf_points; j++) {
 			const struct intel_psf_gv_point *sp = &qi.psf_points[j];
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 65283286771a..b31ec42c3248 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -192,6 +192,7 @@ struct intel_display_platforms {
 #define HAS_MBUS_JOINING(__display)	((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14)
 #define HAS_MSO(__display)		(DISPLAY_VER(__display) >= 12)
 #define HAS_OVERLAY(__display)		(DISPLAY_INFO(__display)->has_overlay)
+#define HAS_PEAK_BW_THRESHOLD(__display)	(DISPLAY_VER(__display) >= 30)
 #define HAS_PIPEDMC(__display)		(DISPLAY_VER(__display) >= 12)
 #define HAS_PIXEL_NORMALIZER(__display)	(DISPLAY_VER(__display) >= 35)
 #define HAS_PMDEMAND(__display)		(DISPLAY_VER(__display) >= 14)
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* ✓ CI.KUnit: success for drm/i915/display: reduce the pm demand peak bw based on display data rate
  2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
                   ` (10 preceding siblings ...)
  2026-05-11 12:28 ` [PATCH v2 11/11] drm/i915/bw: insert a sw bw info entry to cater low data rate usecases Vinod Govindapillai
@ 2026-05-11 16:28 ` Patchwork
  2026-05-11 17:33 ` ✓ Xe.CI.BAT: " Patchwork
  2026-05-11 19:30 ` ✗ Xe.CI.FULL: failure " Patchwork
  13 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2026-05-11 16:28 UTC (permalink / raw)
  To: Vinod Govindapillai; +Cc: intel-xe

== Series Details ==

Series: drm/i915/display: reduce the pm demand peak bw based on display data rate
URL   : https://patchwork.freedesktop.org/series/166316/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[16:27:12] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:27:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:27:48] Starting KUnit Kernel (1/1)...
[16:27:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:27:48] ================== guc_buf (11 subtests) ===================
[16:27:48] [PASSED] test_smallest
[16:27:48] [PASSED] test_largest
[16:27:48] [PASSED] test_granular
[16:27:48] [PASSED] test_unique
[16:27:48] [PASSED] test_overlap
[16:27:48] [PASSED] test_reusable
[16:27:48] [PASSED] test_too_big
[16:27:48] [PASSED] test_flush
[16:27:48] [PASSED] test_lookup
[16:27:48] [PASSED] test_data
[16:27:48] [PASSED] test_class
[16:27:48] ===================== [PASSED] guc_buf =====================
[16:27:48] =================== guc_dbm (7 subtests) ===================
[16:27:48] [PASSED] test_empty
[16:27:48] [PASSED] test_default
[16:27:48] ======================== test_size  ========================
[16:27:48] [PASSED] 4
[16:27:48] [PASSED] 8
[16:27:48] [PASSED] 32
[16:27:48] [PASSED] 256
[16:27:48] ==================== [PASSED] test_size ====================
[16:27:48] ======================= test_reuse  ========================
[16:27:48] [PASSED] 4
[16:27:48] [PASSED] 8
[16:27:48] [PASSED] 32
[16:27:48] [PASSED] 256
[16:27:48] =================== [PASSED] test_reuse ====================
[16:27:48] =================== test_range_overlap  ====================
[16:27:48] [PASSED] 4
[16:27:48] [PASSED] 8
[16:27:48] [PASSED] 32
[16:27:48] [PASSED] 256
[16:27:48] =============== [PASSED] test_range_overlap ================
[16:27:48] =================== test_range_compact  ====================
[16:27:48] [PASSED] 4
[16:27:48] [PASSED] 8
[16:27:48] [PASSED] 32
[16:27:48] [PASSED] 256
[16:27:48] =============== [PASSED] test_range_compact ================
[16:27:48] ==================== test_range_spare  =====================
[16:27:48] [PASSED] 4
[16:27:48] [PASSED] 8
[16:27:48] [PASSED] 32
[16:27:48] [PASSED] 256
[16:27:48] ================ [PASSED] test_range_spare =================
[16:27:48] ===================== [PASSED] guc_dbm =====================
[16:27:48] =================== guc_idm (6 subtests) ===================
[16:27:48] [PASSED] bad_init
[16:27:48] [PASSED] no_init
[16:27:48] [PASSED] init_fini
[16:27:48] [PASSED] check_used
[16:27:48] [PASSED] check_quota
[16:27:48] [PASSED] check_all
[16:27:48] ===================== [PASSED] guc_idm =====================
[16:27:48] ================== no_relay (3 subtests) ===================
[16:27:48] [PASSED] xe_drops_guc2pf_if_not_ready
[16:27:48] [PASSED] xe_drops_guc2vf_if_not_ready
[16:27:48] [PASSED] xe_rejects_send_if_not_ready
[16:27:48] ==================== [PASSED] no_relay =====================
[16:27:48] ================== pf_relay (14 subtests) ==================
[16:27:48] [PASSED] pf_rejects_guc2pf_too_short
[16:27:48] [PASSED] pf_rejects_guc2pf_too_long
[16:27:48] [PASSED] pf_rejects_guc2pf_no_payload
[16:27:48] [PASSED] pf_fails_no_payload
[16:27:48] [PASSED] pf_fails_bad_origin
[16:27:48] [PASSED] pf_fails_bad_type
[16:27:48] [PASSED] pf_txn_reports_error
[16:27:48] [PASSED] pf_txn_sends_pf2guc
[16:27:48] [PASSED] pf_sends_pf2guc
[16:27:48] [SKIPPED] pf_loopback_nop
[16:27:48] [SKIPPED] pf_loopback_echo
[16:27:48] [SKIPPED] pf_loopback_fail
[16:27:48] [SKIPPED] pf_loopback_busy
[16:27:48] [SKIPPED] pf_loopback_retry
[16:27:48] ==================== [PASSED] pf_relay =====================
[16:27:48] ================== vf_relay (3 subtests) ===================
[16:27:48] [PASSED] vf_rejects_guc2vf_too_short
[16:27:48] [PASSED] vf_rejects_guc2vf_too_long
[16:27:48] [PASSED] vf_rejects_guc2vf_no_payload
[16:27:48] ==================== [PASSED] vf_relay =====================
[16:27:48] ================ pf_gt_config (9 subtests) =================
[16:27:48] [PASSED] fair_contexts_1vf
[16:27:48] [PASSED] fair_doorbells_1vf
[16:27:48] [PASSED] fair_ggtt_1vf
[16:27:48] ====================== fair_vram_1vf  ======================
[16:27:48] [PASSED] 3.50 GiB
[16:27:48] [PASSED] 11.5 GiB
[16:27:48] [PASSED] 15.5 GiB
[16:27:48] [PASSED] 31.5 GiB
[16:27:48] [PASSED] 63.5 GiB
[16:27:48] [PASSED] 1.91 GiB
[16:27:48] ================== [PASSED] fair_vram_1vf ==================
[16:27:48] ================ fair_vram_1vf_admin_only  =================
[16:27:48] [PASSED] 3.50 GiB
[16:27:48] [PASSED] 11.5 GiB
[16:27:48] [PASSED] 15.5 GiB
[16:27:48] [PASSED] 31.5 GiB
[16:27:48] [PASSED] 63.5 GiB
[16:27:48] [PASSED] 1.91 GiB
[16:27:48] ============ [PASSED] fair_vram_1vf_admin_only =============
[16:27:48] ====================== fair_contexts  ======================
[16:27:48] [PASSED] 1 VF
[16:27:48] [PASSED] 2 VFs
[16:27:48] [PASSED] 3 VFs
[16:27:48] [PASSED] 4 VFs
[16:27:48] [PASSED] 5 VFs
[16:27:48] [PASSED] 6 VFs
[16:27:48] [PASSED] 7 VFs
[16:27:48] [PASSED] 8 VFs
[16:27:48] [PASSED] 9 VFs
[16:27:48] [PASSED] 10 VFs
[16:27:48] [PASSED] 11 VFs
[16:27:48] [PASSED] 12 VFs
[16:27:48] [PASSED] 13 VFs
[16:27:48] [PASSED] 14 VFs
[16:27:48] [PASSED] 15 VFs
[16:27:48] [PASSED] 16 VFs
[16:27:48] [PASSED] 17 VFs
[16:27:48] [PASSED] 18 VFs
[16:27:48] [PASSED] 19 VFs
[16:27:48] [PASSED] 20 VFs
[16:27:48] [PASSED] 21 VFs
[16:27:48] [PASSED] 22 VFs
[16:27:48] [PASSED] 23 VFs
[16:27:48] [PASSED] 24 VFs
[16:27:48] [PASSED] 25 VFs
[16:27:48] [PASSED] 26 VFs
[16:27:48] [PASSED] 27 VFs
[16:27:48] [PASSED] 28 VFs
[16:27:48] [PASSED] 29 VFs
[16:27:48] [PASSED] 30 VFs
[16:27:48] [PASSED] 31 VFs
[16:27:48] [PASSED] 32 VFs
[16:27:48] [PASSED] 33 VFs
[16:27:48] [PASSED] 34 VFs
[16:27:48] [PASSED] 35 VFs
[16:27:48] [PASSED] 36 VFs
[16:27:48] [PASSED] 37 VFs
[16:27:48] [PASSED] 38 VFs
[16:27:48] [PASSED] 39 VFs
[16:27:48] [PASSED] 40 VFs
[16:27:48] [PASSED] 41 VFs
[16:27:48] [PASSED] 42 VFs
[16:27:48] [PASSED] 43 VFs
[16:27:48] [PASSED] 44 VFs
[16:27:48] [PASSED] 45 VFs
[16:27:48] [PASSED] 46 VFs
[16:27:48] [PASSED] 47 VFs
[16:27:48] [PASSED] 48 VFs
[16:27:48] [PASSED] 49 VFs
[16:27:48] [PASSED] 50 VFs
[16:27:48] [PASSED] 51 VFs
[16:27:48] [PASSED] 52 VFs
[16:27:48] [PASSED] 53 VFs
[16:27:48] [PASSED] 54 VFs
[16:27:48] [PASSED] 55 VFs
[16:27:48] [PASSED] 56 VFs
[16:27:48] [PASSED] 57 VFs
[16:27:48] [PASSED] 58 VFs
[16:27:48] [PASSED] 59 VFs
[16:27:48] [PASSED] 60 VFs
[16:27:48] [PASSED] 61 VFs
[16:27:48] [PASSED] 62 VFs
[16:27:48] [PASSED] 63 VFs
[16:27:48] ================== [PASSED] fair_contexts ==================
[16:27:48] ===================== fair_doorbells  ======================
[16:27:48] [PASSED] 1 VF
[16:27:48] [PASSED] 2 VFs
[16:27:48] [PASSED] 3 VFs
[16:27:48] [PASSED] 4 VFs
[16:27:48] [PASSED] 5 VFs
[16:27:48] [PASSED] 6 VFs
[16:27:48] [PASSED] 7 VFs
[16:27:48] [PASSED] 8 VFs
[16:27:48] [PASSED] 9 VFs
[16:27:48] [PASSED] 10 VFs
[16:27:48] [PASSED] 11 VFs
[16:27:48] [PASSED] 12 VFs
[16:27:48] [PASSED] 13 VFs
[16:27:48] [PASSED] 14 VFs
[16:27:48] [PASSED] 15 VFs
[16:27:48] [PASSED] 16 VFs
[16:27:48] [PASSED] 17 VFs
[16:27:48] [PASSED] 18 VFs
[16:27:48] [PASSED] 19 VFs
[16:27:48] [PASSED] 20 VFs
[16:27:48] [PASSED] 21 VFs
[16:27:48] [PASSED] 22 VFs
[16:27:48] [PASSED] 23 VFs
[16:27:48] [PASSED] 24 VFs
[16:27:48] [PASSED] 25 VFs
[16:27:48] [PASSED] 26 VFs
[16:27:48] [PASSED] 27 VFs
[16:27:48] [PASSED] 28 VFs
[16:27:48] [PASSED] 29 VFs
[16:27:48] [PASSED] 30 VFs
[16:27:48] [PASSED] 31 VFs
[16:27:48] [PASSED] 32 VFs
[16:27:48] [PASSED] 33 VFs
[16:27:48] [PASSED] 34 VFs
[16:27:48] [PASSED] 35 VFs
[16:27:48] [PASSED] 36 VFs
[16:27:48] [PASSED] 37 VFs
[16:27:48] [PASSED] 38 VFs
[16:27:48] [PASSED] 39 VFs
[16:27:48] [PASSED] 40 VFs
[16:27:48] [PASSED] 41 VFs
[16:27:48] [PASSED] 42 VFs
[16:27:48] [PASSED] 43 VFs
[16:27:48] [PASSED] 44 VFs
[16:27:48] [PASSED] 45 VFs
[16:27:48] [PASSED] 46 VFs
[16:27:48] [PASSED] 47 VFs
[16:27:48] [PASSED] 48 VFs
[16:27:48] [PASSED] 49 VFs
[16:27:48] [PASSED] 50 VFs
[16:27:48] [PASSED] 51 VFs
[16:27:48] [PASSED] 52 VFs
[16:27:48] [PASSED] 53 VFs
[16:27:48] [PASSED] 54 VFs
[16:27:48] [PASSED] 55 VFs
[16:27:48] [PASSED] 56 VFs
[16:27:48] [PASSED] 57 VFs
[16:27:48] [PASSED] 58 VFs
[16:27:48] [PASSED] 59 VFs
[16:27:48] [PASSED] 60 VFs
[16:27:48] [PASSED] 61 VFs
[16:27:48] [PASSED] 62 VFs
[16:27:48] [PASSED] 63 VFs
[16:27:48] ================= [PASSED] fair_doorbells ==================
[16:27:48] ======================== fair_ggtt  ========================
[16:27:48] [PASSED] 1 VF
[16:27:48] [PASSED] 2 VFs
[16:27:48] [PASSED] 3 VFs
[16:27:48] [PASSED] 4 VFs
[16:27:48] [PASSED] 5 VFs
[16:27:48] [PASSED] 6 VFs
[16:27:48] [PASSED] 7 VFs
[16:27:48] [PASSED] 8 VFs
[16:27:48] [PASSED] 9 VFs
[16:27:48] [PASSED] 10 VFs
[16:27:48] [PASSED] 11 VFs
[16:27:48] [PASSED] 12 VFs
[16:27:48] [PASSED] 13 VFs
[16:27:48] [PASSED] 14 VFs
[16:27:48] [PASSED] 15 VFs
[16:27:48] [PASSED] 16 VFs
[16:27:48] [PASSED] 17 VFs
[16:27:48] [PASSED] 18 VFs
[16:27:48] [PASSED] 19 VFs
[16:27:48] [PASSED] 20 VFs
[16:27:48] [PASSED] 21 VFs
[16:27:48] [PASSED] 22 VFs
[16:27:48] [PASSED] 23 VFs
[16:27:48] [PASSED] 24 VFs
[16:27:48] [PASSED] 25 VFs
[16:27:48] [PASSED] 26 VFs
[16:27:48] [PASSED] 27 VFs
[16:27:48] [PASSED] 28 VFs
[16:27:48] [PASSED] 29 VFs
[16:27:48] [PASSED] 30 VFs
[16:27:48] [PASSED] 31 VFs
[16:27:48] [PASSED] 32 VFs
[16:27:48] [PASSED] 33 VFs
[16:27:48] [PASSED] 34 VFs
[16:27:48] [PASSED] 35 VFs
[16:27:48] [PASSED] 36 VFs
[16:27:48] [PASSED] 37 VFs
[16:27:48] [PASSED] 38 VFs
[16:27:48] [PASSED] 39 VFs
[16:27:48] [PASSED] 40 VFs
[16:27:48] [PASSED] 41 VFs
[16:27:48] [PASSED] 42 VFs
[16:27:48] [PASSED] 43 VFs
[16:27:48] [PASSED] 44 VFs
[16:27:48] [PASSED] 45 VFs
[16:27:48] [PASSED] 46 VFs
[16:27:48] [PASSED] 47 VFs
[16:27:48] [PASSED] 48 VFs
[16:27:48] [PASSED] 49 VFs
[16:27:48] [PASSED] 50 VFs
[16:27:48] [PASSED] 51 VFs
[16:27:48] [PASSED] 52 VFs
[16:27:48] [PASSED] 53 VFs
[16:27:48] [PASSED] 54 VFs
[16:27:48] [PASSED] 55 VFs
[16:27:48] [PASSED] 56 VFs
[16:27:48] [PASSED] 57 VFs
[16:27:48] [PASSED] 58 VFs
[16:27:48] [PASSED] 59 VFs
[16:27:48] [PASSED] 60 VFs
[16:27:48] [PASSED] 61 VFs
[16:27:48] [PASSED] 62 VFs
[16:27:48] [PASSED] 63 VFs
[16:27:48] ==================== [PASSED] fair_ggtt ====================
[16:27:48] ======================== fair_vram  ========================
[16:27:48] [PASSED] 1 VF
[16:27:48] [PASSED] 2 VFs
[16:27:48] [PASSED] 3 VFs
[16:27:48] [PASSED] 4 VFs
[16:27:48] [PASSED] 5 VFs
[16:27:48] [PASSED] 6 VFs
[16:27:48] [PASSED] 7 VFs
[16:27:48] [PASSED] 8 VFs
[16:27:48] [PASSED] 9 VFs
[16:27:48] [PASSED] 10 VFs
[16:27:48] [PASSED] 11 VFs
[16:27:48] [PASSED] 12 VFs
[16:27:48] [PASSED] 13 VFs
[16:27:48] [PASSED] 14 VFs
[16:27:48] [PASSED] 15 VFs
[16:27:48] [PASSED] 16 VFs
[16:27:48] [PASSED] 17 VFs
[16:27:48] [PASSED] 18 VFs
[16:27:48] [PASSED] 19 VFs
[16:27:48] [PASSED] 20 VFs
[16:27:48] [PASSED] 21 VFs
[16:27:48] [PASSED] 22 VFs
[16:27:48] [PASSED] 23 VFs
[16:27:48] [PASSED] 24 VFs
[16:27:48] [PASSED] 25 VFs
[16:27:48] [PASSED] 26 VFs
[16:27:48] [PASSED] 27 VFs
[16:27:48] [PASSED] 28 VFs
[16:27:48] [PASSED] 29 VFs
[16:27:48] [PASSED] 30 VFs
[16:27:48] [PASSED] 31 VFs
[16:27:48] [PASSED] 32 VFs
[16:27:48] [PASSED] 33 VFs
[16:27:48] [PASSED] 34 VFs
[16:27:48] [PASSED] 35 VFs
[16:27:48] [PASSED] 36 VFs
[16:27:48] [PASSED] 37 VFs
[16:27:48] [PASSED] 38 VFs
[16:27:48] [PASSED] 39 VFs
[16:27:48] [PASSED] 40 VFs
[16:27:48] [PASSED] 41 VFs
[16:27:48] [PASSED] 42 VFs
[16:27:48] [PASSED] 43 VFs
[16:27:48] [PASSED] 44 VFs
[16:27:48] [PASSED] 45 VFs
[16:27:48] [PASSED] 46 VFs
[16:27:48] [PASSED] 47 VFs
[16:27:48] [PASSED] 48 VFs
[16:27:48] [PASSED] 49 VFs
[16:27:48] [PASSED] 50 VFs
[16:27:48] [PASSED] 51 VFs
[16:27:48] [PASSED] 52 VFs
[16:27:48] [PASSED] 53 VFs
[16:27:48] [PASSED] 54 VFs
[16:27:48] [PASSED] 55 VFs
[16:27:48] [PASSED] 56 VFs
[16:27:48] [PASSED] 57 VFs
[16:27:48] [PASSED] 58 VFs
[16:27:48] [PASSED] 59 VFs
[16:27:48] [PASSED] 60 VFs
[16:27:48] [PASSED] 61 VFs
[16:27:48] [PASSED] 62 VFs
[16:27:48] [PASSED] 63 VFs
[16:27:48] ==================== [PASSED] fair_vram ====================
[16:27:48] ================== [PASSED] pf_gt_config ===================
[16:27:48] ===================== lmtt (1 subtest) =====================
[16:27:48] ======================== test_ops  =========================
[16:27:48] [PASSED] 2-level
[16:27:48] [PASSED] multi-level
[16:27:48] ==================== [PASSED] test_ops =====================
[16:27:48] ====================== [PASSED] lmtt =======================
[16:27:48] ================= pf_service (11 subtests) =================
[16:27:48] [PASSED] pf_negotiate_any
[16:27:48] [PASSED] pf_negotiate_base_match
[16:27:48] [PASSED] pf_negotiate_base_newer
[16:27:48] [PASSED] pf_negotiate_base_next
[16:27:48] [SKIPPED] pf_negotiate_base_older
[16:27:48] [PASSED] pf_negotiate_base_prev
[16:27:48] [PASSED] pf_negotiate_latest_match
[16:27:48] [PASSED] pf_negotiate_latest_newer
[16:27:48] [PASSED] pf_negotiate_latest_next
[16:27:48] [SKIPPED] pf_negotiate_latest_older
[16:27:48] [SKIPPED] pf_negotiate_latest_prev
[16:27:48] =================== [PASSED] pf_service ====================
[16:27:48] ================= xe_guc_g2g (2 subtests) ==================
[16:27:48] ============== xe_live_guc_g2g_kunit_default  ==============
[16:27:48] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[16:27:48] ============== xe_live_guc_g2g_kunit_allmem  ===============
[16:27:48] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[16:27:48] =================== [SKIPPED] xe_guc_g2g ===================
[16:27:48] =================== xe_mocs (2 subtests) ===================
[16:27:48] ================ xe_live_mocs_kernel_kunit  ================
[16:27:48] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[16:27:48] ================ xe_live_mocs_reset_kunit  =================
[16:27:48] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[16:27:48] ==================== [SKIPPED] xe_mocs =====================
[16:27:48] ================= xe_migrate (2 subtests) ==================
[16:27:48] ================= xe_migrate_sanity_kunit  =================
[16:27:48] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[16:27:48] ================== xe_validate_ccs_kunit  ==================
[16:27:48] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[16:27:48] =================== [SKIPPED] xe_migrate ===================
[16:27:48] ================== xe_dma_buf (1 subtest) ==================
[16:27:48] ==================== xe_dma_buf_kunit  =====================
[16:27:48] ================ [SKIPPED] xe_dma_buf_kunit ================
[16:27:48] =================== [SKIPPED] xe_dma_buf ===================
[16:27:48] ================= xe_bo_shrink (1 subtest) =================
[16:27:48] =================== xe_bo_shrink_kunit  ====================
[16:27:48] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[16:27:48] ================== [SKIPPED] xe_bo_shrink ==================
[16:27:48] ==================== xe_bo (2 subtests) ====================
[16:27:48] ================== xe_ccs_migrate_kunit  ===================
[16:27:48] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[16:27:48] ==================== xe_bo_evict_kunit  ====================
[16:27:48] =============== [SKIPPED] xe_bo_evict_kunit ================
[16:27:48] ===================== [SKIPPED] xe_bo ======================
[16:27:48] ==================== args (13 subtests) ====================
[16:27:48] [PASSED] count_args_test
[16:27:48] [PASSED] call_args_example
[16:27:48] [PASSED] call_args_test
[16:27:48] [PASSED] drop_first_arg_example
[16:27:48] [PASSED] drop_first_arg_test
[16:27:48] [PASSED] first_arg_example
[16:27:48] [PASSED] first_arg_test
[16:27:48] [PASSED] last_arg_example
[16:27:48] [PASSED] last_arg_test
[16:27:48] [PASSED] pick_arg_example
[16:27:48] [PASSED] if_args_example
[16:27:48] [PASSED] if_args_test
[16:27:48] [PASSED] sep_comma_example
[16:27:48] ====================== [PASSED] args =======================
[16:27:48] =================== xe_pci (3 subtests) ====================
[16:27:48] ==================== check_graphics_ip  ====================
[16:27:48] [PASSED] 12.00 Xe_LP
[16:27:48] [PASSED] 12.10 Xe_LP+
[16:27:48] [PASSED] 12.55 Xe_HPG
[16:27:48] [PASSED] 12.60 Xe_HPC
[16:27:48] [PASSED] 12.70 Xe_LPG
[16:27:48] [PASSED] 12.71 Xe_LPG
[16:27:48] [PASSED] 12.74 Xe_LPG+
[16:27:48] [PASSED] 20.01 Xe2_HPG
[16:27:48] [PASSED] 20.02 Xe2_HPG
[16:27:48] [PASSED] 20.04 Xe2_LPG
[16:27:48] [PASSED] 30.00 Xe3_LPG
[16:27:48] [PASSED] 30.01 Xe3_LPG
[16:27:48] [PASSED] 30.03 Xe3_LPG
[16:27:48] [PASSED] 30.04 Xe3_LPG
[16:27:48] [PASSED] 30.05 Xe3_LPG
[16:27:48] [PASSED] 35.10 Xe3p_LPG
[16:27:48] [PASSED] 35.11 Xe3p_XPC
[16:27:48] ================ [PASSED] check_graphics_ip ================
[16:27:48] ===================== check_media_ip  ======================
[16:27:48] [PASSED] 12.00 Xe_M
[16:27:48] [PASSED] 12.55 Xe_HPM
[16:27:48] [PASSED] 13.00 Xe_LPM+
[16:27:48] [PASSED] 13.01 Xe2_HPM
[16:27:48] [PASSED] 20.00 Xe2_LPM
[16:27:48] [PASSED] 30.00 Xe3_LPM
[16:27:48] [PASSED] 30.02 Xe3_LPM
[16:27:48] [PASSED] 35.00 Xe3p_LPM
[16:27:48] [PASSED] 35.03 Xe3p_HPM
[16:27:48] ================= [PASSED] check_media_ip ==================
[16:27:48] =================== check_platform_desc  ===================
[16:27:48] [PASSED] 0x9A60 (TIGERLAKE)
[16:27:48] [PASSED] 0x9A68 (TIGERLAKE)
[16:27:48] [PASSED] 0x9A70 (TIGERLAKE)
[16:27:48] [PASSED] 0x9A40 (TIGERLAKE)
[16:27:48] [PASSED] 0x9A49 (TIGERLAKE)
[16:27:48] [PASSED] 0x9A59 (TIGERLAKE)
[16:27:48] [PASSED] 0x9A78 (TIGERLAKE)
[16:27:48] [PASSED] 0x9AC0 (TIGERLAKE)
[16:27:48] [PASSED] 0x9AC9 (TIGERLAKE)
[16:27:48] [PASSED] 0x9AD9 (TIGERLAKE)
[16:27:48] [PASSED] 0x9AF8 (TIGERLAKE)
[16:27:48] [PASSED] 0x4C80 (ROCKETLAKE)
[16:27:48] [PASSED] 0x4C8A (ROCKETLAKE)
[16:27:48] [PASSED] 0x4C8B (ROCKETLAKE)
[16:27:48] [PASSED] 0x4C8C (ROCKETLAKE)
[16:27:48] [PASSED] 0x4C90 (ROCKETLAKE)
[16:27:48] [PASSED] 0x4C9A (ROCKETLAKE)
[16:27:48] [PASSED] 0x4680 (ALDERLAKE_S)
[16:27:48] [PASSED] 0x4682 (ALDERLAKE_S)
[16:27:48] [PASSED] 0x4688 (ALDERLAKE_S)
[16:27:48] [PASSED] 0x468A (ALDERLAKE_S)
[16:27:48] [PASSED] 0x468B (ALDERLAKE_S)
[16:27:48] [PASSED] 0x4690 (ALDERLAKE_S)
[16:27:48] [PASSED] 0x4692 (ALDERLAKE_S)
[16:27:48] [PASSED] 0x4693 (ALDERLAKE_S)
[16:27:48] [PASSED] 0x46A0 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x46A1 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x46A2 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x46A3 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x46A6 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x46A8 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x46AA (ALDERLAKE_P)
[16:27:48] [PASSED] 0x462A (ALDERLAKE_P)
[16:27:48] [PASSED] 0x4626 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x4628 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x46B0 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x46B1 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x46B2 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x46B3 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x46C0 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x46C1 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x46C2 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x46C3 (ALDERLAKE_P)
[16:27:48] [PASSED] 0x46D0 (ALDERLAKE_N)
[16:27:48] [PASSED] 0x46D1 (ALDERLAKE_N)
[16:27:48] [PASSED] 0x46D2 (ALDERLAKE_N)
[16:27:48] [PASSED] 0x46D3 (ALDERLAKE_N)
[16:27:48] [PASSED] 0x46D4 (ALDERLAKE_N)
[16:27:48] [PASSED] 0xA721 (ALDERLAKE_P)
[16:27:48] [PASSED] 0xA7A1 (ALDERLAKE_P)
[16:27:48] [PASSED] 0xA7A9 (ALDERLAKE_P)
[16:27:48] [PASSED] 0xA7AC (ALDERLAKE_P)
[16:27:48] [PASSED] 0xA7AD (ALDERLAKE_P)
[16:27:48] [PASSED] 0xA720 (ALDERLAKE_P)
[16:27:48] [PASSED] 0xA7A0 (ALDERLAKE_P)
[16:27:48] [PASSED] 0xA7A8 (ALDERLAKE_P)
[16:27:48] [PASSED] 0xA7AA (ALDERLAKE_P)
[16:27:48] [PASSED] 0xA7AB (ALDERLAKE_P)
[16:27:48] [PASSED] 0xA780 (ALDERLAKE_S)
[16:27:48] [PASSED] 0xA781 (ALDERLAKE_S)
[16:27:48] [PASSED] 0xA782 (ALDERLAKE_S)
[16:27:48] [PASSED] 0xA783 (ALDERLAKE_S)
[16:27:48] [PASSED] 0xA788 (ALDERLAKE_S)
[16:27:48] [PASSED] 0xA789 (ALDERLAKE_S)
[16:27:48] [PASSED] 0xA78A (ALDERLAKE_S)
[16:27:48] [PASSED] 0xA78B (ALDERLAKE_S)
[16:27:48] [PASSED] 0x4905 (DG1)
[16:27:48] [PASSED] 0x4906 (DG1)
[16:27:48] [PASSED] 0x4907 (DG1)
[16:27:48] [PASSED] 0x4908 (DG1)
[16:27:48] [PASSED] 0x4909 (DG1)
[16:27:48] [PASSED] 0x56C0 (DG2)
[16:27:48] [PASSED] 0x56C2 (DG2)
[16:27:48] [PASSED] 0x56C1 (DG2)
[16:27:48] [PASSED] 0x7D51 (METEORLAKE)
[16:27:48] [PASSED] 0x7DD1 (METEORLAKE)
[16:27:48] [PASSED] 0x7D41 (METEORLAKE)
[16:27:48] [PASSED] 0x7D67 (METEORLAKE)
[16:27:48] [PASSED] 0xB640 (METEORLAKE)
[16:27:48] [PASSED] 0x56A0 (DG2)
[16:27:48] [PASSED] 0x56A1 (DG2)
[16:27:48] [PASSED] 0x56A2 (DG2)
[16:27:48] [PASSED] 0x56BE (DG2)
[16:27:48] [PASSED] 0x56BF (DG2)
[16:27:48] [PASSED] 0x5690 (DG2)
[16:27:48] [PASSED] 0x5691 (DG2)
[16:27:48] [PASSED] 0x5692 (DG2)
[16:27:48] [PASSED] 0x56A5 (DG2)
[16:27:48] [PASSED] 0x56A6 (DG2)
[16:27:48] [PASSED] 0x56B0 (DG2)
[16:27:48] [PASSED] 0x56B1 (DG2)
[16:27:48] [PASSED] 0x56BA (DG2)
[16:27:48] [PASSED] 0x56BB (DG2)
[16:27:48] [PASSED] 0x56BC (DG2)
[16:27:48] [PASSED] 0x56BD (DG2)
[16:27:48] [PASSED] 0x5693 (DG2)
[16:27:48] [PASSED] 0x5694 (DG2)
[16:27:48] [PASSED] 0x5695 (DG2)
[16:27:48] [PASSED] 0x56A3 (DG2)
[16:27:48] [PASSED] 0x56A4 (DG2)
[16:27:48] [PASSED] 0x56B2 (DG2)
[16:27:48] [PASSED] 0x56B3 (DG2)
[16:27:48] [PASSED] 0x5696 (DG2)
[16:27:48] [PASSED] 0x5697 (DG2)
[16:27:48] [PASSED] 0xB69 (PVC)
[16:27:48] [PASSED] 0xB6E (PVC)
[16:27:48] [PASSED] 0xBD4 (PVC)
[16:27:48] [PASSED] 0xBD5 (PVC)
[16:27:48] [PASSED] 0xBD6 (PVC)
[16:27:48] [PASSED] 0xBD7 (PVC)
[16:27:48] [PASSED] 0xBD8 (PVC)
[16:27:48] [PASSED] 0xBD9 (PVC)
[16:27:48] [PASSED] 0xBDA (PVC)
[16:27:48] [PASSED] 0xBDB (PVC)
[16:27:48] [PASSED] 0xBE0 (PVC)
[16:27:48] [PASSED] 0xBE1 (PVC)
[16:27:48] [PASSED] 0xBE5 (PVC)
[16:27:48] [PASSED] 0x7D40 (METEORLAKE)
[16:27:48] [PASSED] 0x7D45 (METEORLAKE)
[16:27:48] [PASSED] 0x7D55 (METEORLAKE)
[16:27:48] [PASSED] 0x7D60 (METEORLAKE)
[16:27:48] [PASSED] 0x7DD5 (METEORLAKE)
[16:27:48] [PASSED] 0x6420 (LUNARLAKE)
[16:27:48] [PASSED] 0x64A0 (LUNARLAKE)
[16:27:48] [PASSED] 0x64B0 (LUNARLAKE)
[16:27:48] [PASSED] 0xE202 (BATTLEMAGE)
[16:27:48] [PASSED] 0xE209 (BATTLEMAGE)
[16:27:48] [PASSED] 0xE20B (BATTLEMAGE)
[16:27:48] [PASSED] 0xE20C (BATTLEMAGE)
[16:27:48] [PASSED] 0xE20D (BATTLEMAGE)
[16:27:48] [PASSED] 0xE210 (BATTLEMAGE)
[16:27:48] [PASSED] 0xE211 (BATTLEMAGE)
[16:27:48] [PASSED] 0xE212 (BATTLEMAGE)
[16:27:48] [PASSED] 0xE216 (BATTLEMAGE)
[16:27:48] [PASSED] 0xE220 (BATTLEMAGE)
[16:27:48] [PASSED] 0xE221 (BATTLEMAGE)
[16:27:48] [PASSED] 0xE222 (BATTLEMAGE)
[16:27:48] [PASSED] 0xE223 (BATTLEMAGE)
[16:27:48] [PASSED] 0xB080 (PANTHERLAKE)
[16:27:48] [PASSED] 0xB081 (PANTHERLAKE)
[16:27:48] [PASSED] 0xB082 (PANTHERLAKE)
[16:27:48] [PASSED] 0xB083 (PANTHERLAKE)
[16:27:48] [PASSED] 0xB084 (PANTHERLAKE)
[16:27:48] [PASSED] 0xB085 (PANTHERLAKE)
[16:27:48] [PASSED] 0xB086 (PANTHERLAKE)
[16:27:48] [PASSED] 0xB087 (PANTHERLAKE)
[16:27:48] [PASSED] 0xB08F (PANTHERLAKE)
[16:27:48] [PASSED] 0xB090 (PANTHERLAKE)
[16:27:48] [PASSED] 0xB0A0 (PANTHERLAKE)
[16:27:48] [PASSED] 0xB0B0 (PANTHERLAKE)
[16:27:48] [PASSED] 0xFD80 (PANTHERLAKE)
[16:27:48] [PASSED] 0xFD81 (PANTHERLAKE)
[16:27:48] [PASSED] 0xD740 (NOVALAKE_S)
[16:27:48] [PASSED] 0xD741 (NOVALAKE_S)
[16:27:48] [PASSED] 0xD742 (NOVALAKE_S)
[16:27:48] [PASSED] 0xD743 (NOVALAKE_S)
[16:27:48] [PASSED] 0xD744 (NOVALAKE_S)
[16:27:48] [PASSED] 0xD745 (NOVALAKE_S)
[16:27:48] [PASSED] 0x674C (CRESCENTISLAND)
[16:27:48] [PASSED] 0x674D (CRESCENTISLAND)
[16:27:48] [PASSED] 0x674E (CRESCENTISLAND)
[16:27:48] [PASSED] 0x674F (CRESCENTISLAND)
[16:27:48] [PASSED] 0x6750 (CRESCENTISLAND)
[16:27:48] [PASSED] 0xD750 (NOVALAKE_P)
[16:27:48] [PASSED] 0xD751 (NOVALAKE_P)
[16:27:48] [PASSED] 0xD752 (NOVALAKE_P)
[16:27:48] [PASSED] 0xD753 (NOVALAKE_P)
[16:27:48] [PASSED] 0xD754 (NOVALAKE_P)
[16:27:48] [PASSED] 0xD755 (NOVALAKE_P)
[16:27:48] [PASSED] 0xD756 (NOVALAKE_P)
[16:27:48] [PASSED] 0xD757 (NOVALAKE_P)
[16:27:48] [PASSED] 0xD75F (NOVALAKE_P)
[16:27:48] =============== [PASSED] check_platform_desc ===============
[16:27:48] ===================== [PASSED] xe_pci ======================
[16:27:48] =================== xe_rtp (2 subtests) ====================
[16:27:48] =============== xe_rtp_process_to_sr_tests  ================
[16:27:48] [PASSED] coalesce-same-reg
[16:27:48] [PASSED] no-match-no-add
[16:27:48] [PASSED] match-or
[16:27:48] [PASSED] match-or-xfail
[16:27:48] [PASSED] no-match-no-add-multiple-rules
[16:27:48] [PASSED] two-regs-two-entries
[16:27:48] [PASSED] clr-one-set-other
[16:27:48] [PASSED] set-field
[16:27:48] [PASSED] conflict-duplicate
[16:27:48] [PASSED] conflict-not-disjoint
[16:27:48] [PASSED] conflict-reg-type
[16:27:48] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[16:27:48] ================== xe_rtp_process_tests  ===================
[16:27:48] [PASSED] active1
[16:27:48] [PASSED] active2
[16:27:48] [PASSED] active-inactive
[16:27:48] [PASSED] inactive-active
[16:27:48] [PASSED] inactive-1st_or_active-inactive
[16:27:48] [PASSED] inactive-2nd_or_active-inactive
[16:27:48] [PASSED] inactive-last_or_active-inactive
[16:27:48] [PASSED] inactive-no_or_active-inactive
[16:27:48] ============== [PASSED] xe_rtp_process_tests ===============
[16:27:48] ===================== [PASSED] xe_rtp ======================
[16:27:48] ==================== xe_wa (1 subtest) =====================
[16:27:48] ======================== xe_wa_gt  =========================
[16:27:48] [PASSED] TIGERLAKE B0
[16:27:48] [PASSED] DG1 A0
[16:27:48] [PASSED] DG1 B0
[16:27:48] [PASSED] ALDERLAKE_S A0
[16:27:48] [PASSED] ALDERLAKE_S B0
[16:27:48] [PASSED] ALDERLAKE_S C0
[16:27:48] [PASSED] ALDERLAKE_S D0
[16:27:48] [PASSED] ALDERLAKE_P A0
[16:27:48] [PASSED] ALDERLAKE_P B0
[16:27:48] [PASSED] ALDERLAKE_P C0
[16:27:48] [PASSED] ALDERLAKE_S RPLS D0
[16:27:48] [PASSED] ALDERLAKE_P RPLU E0
[16:27:48] [PASSED] DG2 G10 C0
[16:27:48] [PASSED] DG2 G11 B1
[16:27:48] [PASSED] DG2 G12 A1
[16:27:48] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[16:27:48] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[16:27:48] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[16:27:48] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[16:27:48] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[16:27:48] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[16:27:48] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[16:27:48] ==================== [PASSED] xe_wa_gt =====================
[16:27:48] ====================== [PASSED] xe_wa ======================
[16:27:48] ============================================================
[16:27:48] Testing complete. Ran 601 tests: passed: 583, skipped: 18
[16:27:48] Elapsed time: 36.056s total, 4.278s configuring, 31.162s building, 0.605s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[16:27:48] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:27:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:28:14] Starting KUnit Kernel (1/1)...
[16:28:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:28:14] ============ drm_test_pick_cmdline (2 subtests) ============
[16:28:14] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[16:28:14] =============== drm_test_pick_cmdline_named  ===============
[16:28:14] [PASSED] NTSC
[16:28:14] [PASSED] NTSC-J
[16:28:14] [PASSED] PAL
[16:28:14] [PASSED] PAL-M
[16:28:14] =========== [PASSED] drm_test_pick_cmdline_named ===========
[16:28:14] ============== [PASSED] drm_test_pick_cmdline ==============
[16:28:14] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[16:28:14] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[16:28:14] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[16:28:14] =========== drm_validate_clone_mode (2 subtests) ===========
[16:28:14] ============== drm_test_check_in_clone_mode  ===============
[16:28:14] [PASSED] in_clone_mode
[16:28:14] [PASSED] not_in_clone_mode
[16:28:14] ========== [PASSED] drm_test_check_in_clone_mode ===========
[16:28:14] =============== drm_test_check_valid_clones  ===============
[16:28:14] [PASSED] not_in_clone_mode
[16:28:14] [PASSED] valid_clone
[16:28:14] [PASSED] invalid_clone
[16:28:14] =========== [PASSED] drm_test_check_valid_clones ===========
[16:28:14] ============= [PASSED] drm_validate_clone_mode =============
[16:28:14] ============= drm_validate_modeset (1 subtest) =============
[16:28:14] [PASSED] drm_test_check_connector_changed_modeset
[16:28:14] ============== [PASSED] drm_validate_modeset ===============
[16:28:14] ====== drm_test_bridge_get_current_state (2 subtests) ======
[16:28:14] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[16:28:14] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[16:28:14] ======== [PASSED] drm_test_bridge_get_current_state ========
[16:28:14] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[16:28:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[16:28:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[16:28:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[16:28:14] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[16:28:14] ============== drm_bridge_alloc (2 subtests) ===============
[16:28:14] [PASSED] drm_test_drm_bridge_alloc_basic
[16:28:14] [PASSED] drm_test_drm_bridge_alloc_get_put
[16:28:14] ================ [PASSED] drm_bridge_alloc =================
[16:28:14] ============= drm_cmdline_parser (40 subtests) =============
[16:28:14] [PASSED] drm_test_cmdline_force_d_only
[16:28:14] [PASSED] drm_test_cmdline_force_D_only_dvi
[16:28:14] [PASSED] drm_test_cmdline_force_D_only_hdmi
[16:28:14] [PASSED] drm_test_cmdline_force_D_only_not_digital
[16:28:14] [PASSED] drm_test_cmdline_force_e_only
[16:28:14] [PASSED] drm_test_cmdline_res
[16:28:14] [PASSED] drm_test_cmdline_res_vesa
[16:28:14] [PASSED] drm_test_cmdline_res_vesa_rblank
[16:28:14] [PASSED] drm_test_cmdline_res_rblank
[16:28:14] [PASSED] drm_test_cmdline_res_bpp
[16:28:14] [PASSED] drm_test_cmdline_res_refresh
[16:28:14] [PASSED] drm_test_cmdline_res_bpp_refresh
[16:28:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[16:28:14] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[16:28:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[16:28:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[16:28:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[16:28:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[16:28:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[16:28:14] [PASSED] drm_test_cmdline_res_margins_force_on
[16:28:14] [PASSED] drm_test_cmdline_res_vesa_margins
[16:28:14] [PASSED] drm_test_cmdline_name
[16:28:14] [PASSED] drm_test_cmdline_name_bpp
[16:28:14] [PASSED] drm_test_cmdline_name_option
[16:28:14] [PASSED] drm_test_cmdline_name_bpp_option
[16:28:14] [PASSED] drm_test_cmdline_rotate_0
[16:28:14] [PASSED] drm_test_cmdline_rotate_90
[16:28:14] [PASSED] drm_test_cmdline_rotate_180
[16:28:14] [PASSED] drm_test_cmdline_rotate_270
[16:28:14] [PASSED] drm_test_cmdline_hmirror
[16:28:14] [PASSED] drm_test_cmdline_vmirror
[16:28:14] [PASSED] drm_test_cmdline_margin_options
[16:28:14] [PASSED] drm_test_cmdline_multiple_options
[16:28:14] [PASSED] drm_test_cmdline_bpp_extra_and_option
[16:28:14] [PASSED] drm_test_cmdline_extra_and_option
[16:28:14] [PASSED] drm_test_cmdline_freestanding_options
[16:28:14] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[16:28:14] [PASSED] drm_test_cmdline_panel_orientation
[16:28:14] ================ drm_test_cmdline_invalid  =================
[16:28:14] [PASSED] margin_only
[16:28:14] [PASSED] interlace_only
[16:28:14] [PASSED] res_missing_x
[16:28:14] [PASSED] res_missing_y
[16:28:14] [PASSED] res_bad_y
[16:28:14] [PASSED] res_missing_y_bpp
[16:28:14] [PASSED] res_bad_bpp
[16:28:14] [PASSED] res_bad_refresh
[16:28:14] [PASSED] res_bpp_refresh_force_on_off
[16:28:14] [PASSED] res_invalid_mode
[16:28:14] [PASSED] res_bpp_wrong_place_mode
[16:28:14] [PASSED] name_bpp_refresh
[16:28:14] [PASSED] name_refresh
[16:28:14] [PASSED] name_refresh_wrong_mode
[16:28:14] [PASSED] name_refresh_invalid_mode
[16:28:14] [PASSED] rotate_multiple
[16:28:14] [PASSED] rotate_invalid_val
[16:28:14] [PASSED] rotate_truncated
[16:28:14] [PASSED] invalid_option
[16:28:14] [PASSED] invalid_tv_option
[16:28:14] [PASSED] truncated_tv_option
[16:28:14] ============ [PASSED] drm_test_cmdline_invalid =============
[16:28:14] =============== drm_test_cmdline_tv_options  ===============
[16:28:14] [PASSED] NTSC
[16:28:14] [PASSED] NTSC_443
[16:28:14] [PASSED] NTSC_J
[16:28:14] [PASSED] PAL
[16:28:14] [PASSED] PAL_M
[16:28:14] [PASSED] PAL_N
[16:28:14] [PASSED] SECAM
[16:28:14] [PASSED] MONO_525
[16:28:14] [PASSED] MONO_625
[16:28:14] =========== [PASSED] drm_test_cmdline_tv_options ===========
[16:28:14] =============== [PASSED] drm_cmdline_parser ================
[16:28:14] ========== drmm_connector_hdmi_init (20 subtests) ==========
[16:28:14] [PASSED] drm_test_connector_hdmi_init_valid
[16:28:14] [PASSED] drm_test_connector_hdmi_init_bpc_8
[16:28:14] [PASSED] drm_test_connector_hdmi_init_bpc_10
[16:28:14] [PASSED] drm_test_connector_hdmi_init_bpc_12
[16:28:14] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[16:28:14] [PASSED] drm_test_connector_hdmi_init_bpc_null
[16:28:14] [PASSED] drm_test_connector_hdmi_init_formats_empty
[16:28:14] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[16:28:14] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[16:28:14] [PASSED] supported_formats=0x9 yuv420_allowed=1
[16:28:14] [PASSED] supported_formats=0x9 yuv420_allowed=0
[16:28:14] [PASSED] supported_formats=0x5 yuv420_allowed=1
[16:28:14] [PASSED] supported_formats=0x5 yuv420_allowed=0
[16:28:14] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[16:28:14] [PASSED] drm_test_connector_hdmi_init_null_ddc
[16:28:14] [PASSED] drm_test_connector_hdmi_init_null_product
[16:28:14] [PASSED] drm_test_connector_hdmi_init_null_vendor
[16:28:14] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[16:28:14] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[16:28:14] [PASSED] drm_test_connector_hdmi_init_product_valid
[16:28:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[16:28:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[16:28:14] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[16:28:14] ========= drm_test_connector_hdmi_init_type_valid  =========
[16:28:14] [PASSED] HDMI-A
[16:28:14] [PASSED] HDMI-B
[16:28:14] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[16:28:14] ======== drm_test_connector_hdmi_init_type_invalid  ========
[16:28:14] [PASSED] Unknown
[16:28:14] [PASSED] VGA
[16:28:14] [PASSED] DVI-I
[16:28:14] [PASSED] DVI-D
[16:28:14] [PASSED] DVI-A
[16:28:14] [PASSED] Composite
[16:28:14] [PASSED] SVIDEO
[16:28:14] [PASSED] LVDS
[16:28:14] [PASSED] Component
[16:28:14] [PASSED] DIN
[16:28:14] [PASSED] DP
[16:28:14] [PASSED] TV
[16:28:14] [PASSED] eDP
[16:28:14] [PASSED] Virtual
[16:28:14] [PASSED] DSI
[16:28:14] [PASSED] DPI
[16:28:14] [PASSED] Writeback
[16:28:14] [PASSED] SPI
[16:28:14] [PASSED] USB
[16:28:14] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[16:28:14] ============ [PASSED] drmm_connector_hdmi_init =============
[16:28:14] ============= drmm_connector_init (3 subtests) =============
[16:28:14] [PASSED] drm_test_drmm_connector_init
[16:28:14] [PASSED] drm_test_drmm_connector_init_null_ddc
[16:28:14] ========= drm_test_drmm_connector_init_type_valid  =========
[16:28:14] [PASSED] Unknown
[16:28:14] [PASSED] VGA
[16:28:14] [PASSED] DVI-I
[16:28:14] [PASSED] DVI-D
[16:28:14] [PASSED] DVI-A
[16:28:14] [PASSED] Composite
[16:28:14] [PASSED] SVIDEO
[16:28:14] [PASSED] LVDS
[16:28:14] [PASSED] Component
[16:28:14] [PASSED] DIN
[16:28:14] [PASSED] DP
[16:28:14] [PASSED] HDMI-A
[16:28:14] [PASSED] HDMI-B
[16:28:14] [PASSED] TV
[16:28:14] [PASSED] eDP
[16:28:14] [PASSED] Virtual
[16:28:14] [PASSED] DSI
[16:28:14] [PASSED] DPI
[16:28:14] [PASSED] Writeback
[16:28:14] [PASSED] SPI
[16:28:14] [PASSED] USB
[16:28:14] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[16:28:14] =============== [PASSED] drmm_connector_init ===============
[16:28:14] ========= drm_connector_dynamic_init (6 subtests) ==========
[16:28:14] [PASSED] drm_test_drm_connector_dynamic_init
[16:28:14] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[16:28:14] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[16:28:14] [PASSED] drm_test_drm_connector_dynamic_init_properties
[16:28:14] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[16:28:14] [PASSED] Unknown
[16:28:14] [PASSED] VGA
[16:28:14] [PASSED] DVI-I
[16:28:14] [PASSED] DVI-D
[16:28:14] [PASSED] DVI-A
[16:28:14] [PASSED] Composite
[16:28:14] [PASSED] SVIDEO
[16:28:14] [PASSED] LVDS
[16:28:14] [PASSED] Component
[16:28:14] [PASSED] DIN
[16:28:14] [PASSED] DP
[16:28:14] [PASSED] HDMI-A
[16:28:14] [PASSED] HDMI-B
[16:28:14] [PASSED] TV
[16:28:14] [PASSED] eDP
[16:28:14] [PASSED] Virtual
[16:28:14] [PASSED] DSI
[16:28:14] [PASSED] DPI
[16:28:14] [PASSED] Writeback
[16:28:14] [PASSED] SPI
[16:28:14] [PASSED] USB
[16:28:14] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[16:28:14] ======== drm_test_drm_connector_dynamic_init_name  =========
[16:28:14] [PASSED] Unknown
[16:28:14] [PASSED] VGA
[16:28:14] [PASSED] DVI-I
[16:28:14] [PASSED] DVI-D
[16:28:14] [PASSED] DVI-A
[16:28:14] [PASSED] Composite
[16:28:14] [PASSED] SVIDEO
[16:28:14] [PASSED] LVDS
[16:28:14] [PASSED] Component
[16:28:14] [PASSED] DIN
[16:28:14] [PASSED] DP
[16:28:14] [PASSED] HDMI-A
[16:28:14] [PASSED] HDMI-B
[16:28:14] [PASSED] TV
[16:28:14] [PASSED] eDP
[16:28:14] [PASSED] Virtual
[16:28:14] [PASSED] DSI
[16:28:14] [PASSED] DPI
[16:28:14] [PASSED] Writeback
[16:28:14] [PASSED] SPI
[16:28:14] [PASSED] USB
[16:28:14] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[16:28:14] =========== [PASSED] drm_connector_dynamic_init ============
[16:28:14] ==== drm_connector_dynamic_register_early (4 subtests) =====
[16:28:14] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[16:28:14] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[16:28:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[16:28:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[16:28:14] ====== [PASSED] drm_connector_dynamic_register_early =======
[16:28:14] ======= drm_connector_dynamic_register (7 subtests) ========
[16:28:14] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[16:28:14] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[16:28:14] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[16:28:14] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[16:28:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[16:28:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[16:28:14] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[16:28:14] ========= [PASSED] drm_connector_dynamic_register ==========
[16:28:14] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[16:28:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[16:28:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[16:28:14] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[16:28:14] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[16:28:14] ========== drm_test_get_tv_mode_from_name_valid  ===========
[16:28:14] [PASSED] NTSC
[16:28:14] [PASSED] NTSC-443
[16:28:14] [PASSED] NTSC-J
[16:28:14] [PASSED] PAL
[16:28:14] [PASSED] PAL-M
[16:28:14] [PASSED] PAL-N
[16:28:14] [PASSED] SECAM
[16:28:14] [PASSED] Mono
[16:28:14] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[16:28:14] [PASSED] drm_test_get_tv_mode_from_name_truncated
[16:28:14] ============ [PASSED] drm_get_tv_mode_from_name ============
[16:28:14] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[16:28:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[16:28:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[16:28:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[16:28:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[16:28:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[16:28:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[16:28:14] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[16:28:14] [PASSED] VIC 96
[16:28:14] [PASSED] VIC 97
[16:28:14] [PASSED] VIC 101
[16:28:14] [PASSED] VIC 102
[16:28:14] [PASSED] VIC 106
[16:28:14] [PASSED] VIC 107
[16:28:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[16:28:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[16:28:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[16:28:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[16:28:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[16:28:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[16:28:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[16:28:14] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[16:28:14] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[16:28:14] [PASSED] Automatic
[16:28:14] [PASSED] Full
[16:28:14] [PASSED] Limited 16:235
[16:28:14] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[16:28:14] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[16:28:14] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[16:28:14] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[16:28:14] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[16:28:14] [PASSED] RGB
[16:28:14] [PASSED] YUV 4:2:0
[16:28:14] [PASSED] YUV 4:2:2
[16:28:14] [PASSED] YUV 4:4:4
[16:28:14] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[16:28:14] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[16:28:14] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[16:28:14] ============= drm_damage_helper (21 subtests) ==============
[16:28:14] [PASSED] drm_test_damage_iter_no_damage
[16:28:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[16:28:14] [PASSED] drm_test_damage_iter_no_damage_src_moved
[16:28:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[16:28:14] [PASSED] drm_test_damage_iter_no_damage_not_visible
[16:28:14] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[16:28:14] [PASSED] drm_test_damage_iter_no_damage_no_fb
[16:28:14] [PASSED] drm_test_damage_iter_simple_damage
[16:28:14] [PASSED] drm_test_damage_iter_single_damage
[16:28:14] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[16:28:14] [PASSED] drm_test_damage_iter_single_damage_outside_src
[16:28:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[16:28:14] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[16:28:14] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[16:28:14] [PASSED] drm_test_damage_iter_single_damage_src_moved
[16:28:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[16:28:14] [PASSED] drm_test_damage_iter_damage
[16:28:14] [PASSED] drm_test_damage_iter_damage_one_intersect
[16:28:14] [PASSED] drm_test_damage_iter_damage_one_outside
[16:28:14] [PASSED] drm_test_damage_iter_damage_src_moved
[16:28:14] [PASSED] drm_test_damage_iter_damage_not_visible
[16:28:14] ================ [PASSED] drm_damage_helper ================
[16:28:14] ============== drm_dp_mst_helper (3 subtests) ==============
[16:28:14] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[16:28:14] [PASSED] Clock 154000 BPP 30 DSC disabled
[16:28:14] [PASSED] Clock 234000 BPP 30 DSC disabled
[16:28:14] [PASSED] Clock 297000 BPP 24 DSC disabled
[16:28:14] [PASSED] Clock 332880 BPP 24 DSC enabled
[16:28:14] [PASSED] Clock 324540 BPP 24 DSC enabled
[16:28:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[16:28:14] ============== drm_test_dp_mst_calc_pbn_div  ===============
[16:28:14] [PASSED] Link rate 2000000 lane count 4
[16:28:14] [PASSED] Link rate 2000000 lane count 2
[16:28:14] [PASSED] Link rate 2000000 lane count 1
[16:28:14] [PASSED] Link rate 1350000 lane count 4
[16:28:14] [PASSED] Link rate 1350000 lane count 2
[16:28:14] [PASSED] Link rate 1350000 lane count 1
[16:28:14] [PASSED] Link rate 1000000 lane count 4
[16:28:14] [PASSED] Link rate 1000000 lane count 2
[16:28:14] [PASSED] Link rate 1000000 lane count 1
[16:28:14] [PASSED] Link rate 810000 lane count 4
[16:28:14] [PASSED] Link rate 810000 lane count 2
[16:28:14] [PASSED] Link rate 810000 lane count 1
[16:28:14] [PASSED] Link rate 540000 lane count 4
[16:28:14] [PASSED] Link rate 540000 lane count 2
[16:28:14] [PASSED] Link rate 540000 lane count 1
[16:28:14] [PASSED] Link rate 270000 lane count 4
[16:28:14] [PASSED] Link rate 270000 lane count 2
[16:28:14] [PASSED] Link rate 270000 lane count 1
[16:28:14] [PASSED] Link rate 162000 lane count 4
[16:28:14] [PASSED] Link rate 162000 lane count 2
[16:28:14] [PASSED] Link rate 162000 lane count 1
[16:28:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[16:28:14] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[16:28:14] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[16:28:14] [PASSED] DP_POWER_UP_PHY with port number
[16:28:14] [PASSED] DP_POWER_DOWN_PHY with port number
[16:28:14] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[16:28:14] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[16:28:14] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[16:28:14] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[16:28:14] [PASSED] DP_QUERY_PAYLOAD with port number
[16:28:14] [PASSED] DP_QUERY_PAYLOAD with VCPI
[16:28:14] [PASSED] DP_REMOTE_DPCD_READ with port number
[16:28:14] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[16:28:14] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[16:28:14] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[16:28:14] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[16:28:14] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[16:28:14] [PASSED] DP_REMOTE_I2C_READ with port number
[16:28:14] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[16:28:14] [PASSED] DP_REMOTE_I2C_READ with transactions array
[16:28:14] [PASSED] DP_REMOTE_I2C_WRITE with port number
[16:28:14] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[16:28:14] [PASSED] DP_REMOTE_I2C_WRITE with data array
[16:28:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[16:28:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[16:28:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[16:28:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[16:28:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[16:28:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[16:28:14] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[16:28:14] ================ [PASSED] drm_dp_mst_helper ================
[16:28:14] ================== drm_exec (7 subtests) ===================
[16:28:14] [PASSED] sanitycheck
[16:28:14] [PASSED] test_lock
[16:28:14] [PASSED] test_lock_unlock
[16:28:14] [PASSED] test_duplicates
[16:28:14] [PASSED] test_prepare
[16:28:14] [PASSED] test_prepare_array
[16:28:14] [PASSED] test_multiple_loops
[16:28:14] ==================== [PASSED] drm_exec =====================
[16:28:14] =========== drm_format_helper_test (17 subtests) ===========
[16:28:14] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[16:28:14] [PASSED] single_pixel_source_buffer
[16:28:14] [PASSED] single_pixel_clip_rectangle
[16:28:14] [PASSED] well_known_colors
[16:28:14] [PASSED] destination_pitch
[16:28:14] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[16:28:14] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[16:28:14] [PASSED] single_pixel_source_buffer
[16:28:14] [PASSED] single_pixel_clip_rectangle
[16:28:14] [PASSED] well_known_colors
[16:28:14] [PASSED] destination_pitch
[16:28:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[16:28:14] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[16:28:14] [PASSED] single_pixel_source_buffer
[16:28:14] [PASSED] single_pixel_clip_rectangle
[16:28:14] [PASSED] well_known_colors
[16:28:14] [PASSED] destination_pitch
[16:28:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[16:28:14] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[16:28:14] [PASSED] single_pixel_source_buffer
[16:28:14] [PASSED] single_pixel_clip_rectangle
[16:28:14] [PASSED] well_known_colors
[16:28:14] [PASSED] destination_pitch
[16:28:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[16:28:14] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[16:28:14] [PASSED] single_pixel_source_buffer
[16:28:14] [PASSED] single_pixel_clip_rectangle
[16:28:14] [PASSED] well_known_colors
[16:28:14] [PASSED] destination_pitch
[16:28:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[16:28:14] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[16:28:14] [PASSED] single_pixel_source_buffer
[16:28:14] [PASSED] single_pixel_clip_rectangle
[16:28:14] [PASSED] well_known_colors
[16:28:14] [PASSED] destination_pitch
[16:28:14] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[16:28:14] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[16:28:14] [PASSED] single_pixel_source_buffer
[16:28:14] [PASSED] single_pixel_clip_rectangle
[16:28:14] [PASSED] well_known_colors
[16:28:14] [PASSED] destination_pitch
[16:28:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[16:28:14] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[16:28:14] [PASSED] single_pixel_source_buffer
[16:28:14] [PASSED] single_pixel_clip_rectangle
[16:28:14] [PASSED] well_known_colors
[16:28:14] [PASSED] destination_pitch
[16:28:14] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[16:28:14] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[16:28:14] [PASSED] single_pixel_source_buffer
[16:28:14] [PASSED] single_pixel_clip_rectangle
[16:28:14] [PASSED] well_known_colors
[16:28:14] [PASSED] destination_pitch
[16:28:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[16:28:14] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[16:28:14] [PASSED] single_pixel_source_buffer
[16:28:14] [PASSED] single_pixel_clip_rectangle
[16:28:14] [PASSED] well_known_colors
[16:28:14] [PASSED] destination_pitch
[16:28:14] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[16:28:14] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[16:28:14] [PASSED] single_pixel_source_buffer
[16:28:14] [PASSED] single_pixel_clip_rectangle
[16:28:14] [PASSED] well_known_colors
[16:28:14] [PASSED] destination_pitch
[16:28:14] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[16:28:14] ============== drm_test_fb_xrgb8888_to_mono  ===============
[16:28:14] [PASSED] single_pixel_source_buffer
[16:28:14] [PASSED] single_pixel_clip_rectangle
[16:28:14] [PASSED] well_known_colors
[16:28:14] [PASSED] destination_pitch
[16:28:14] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[16:28:14] ==================== drm_test_fb_swab  =====================
[16:28:14] [PASSED] single_pixel_source_buffer
[16:28:14] [PASSED] single_pixel_clip_rectangle
[16:28:14] [PASSED] well_known_colors
[16:28:14] [PASSED] destination_pitch
[16:28:14] ================ [PASSED] drm_test_fb_swab =================
[16:28:14] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[16:28:14] [PASSED] single_pixel_source_buffer
[16:28:14] [PASSED] single_pixel_clip_rectangle
[16:28:14] [PASSED] well_known_colors
[16:28:14] [PASSED] destination_pitch
[16:28:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[16:28:14] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[16:28:14] [PASSED] single_pixel_source_buffer
[16:28:14] [PASSED] single_pixel_clip_rectangle
[16:28:14] [PASSED] well_known_colors
[16:28:14] [PASSED] destination_pitch
[16:28:14] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[16:28:14] ================= drm_test_fb_clip_offset  =================
[16:28:14] [PASSED] pass through
[16:28:14] [PASSED] horizontal offset
[16:28:14] [PASSED] vertical offset
[16:28:14] [PASSED] horizontal and vertical offset
[16:28:14] [PASSED] horizontal offset (custom pitch)
[16:28:14] [PASSED] vertical offset (custom pitch)
[16:28:14] [PASSED] horizontal and vertical offset (custom pitch)
[16:28:14] ============= [PASSED] drm_test_fb_clip_offset =============
[16:28:14] =================== drm_test_fb_memcpy  ====================
[16:28:14] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[16:28:14] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[16:28:14] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[16:28:14] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[16:28:14] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[16:28:14] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[16:28:14] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[16:28:14] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[16:28:14] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[16:28:14] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[16:28:14] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[16:28:14] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[16:28:14] =============== [PASSED] drm_test_fb_memcpy ================
[16:28:14] ============= [PASSED] drm_format_helper_test ==============
[16:28:14] ================= drm_format (18 subtests) =================
[16:28:14] [PASSED] drm_test_format_block_width_invalid
[16:28:14] [PASSED] drm_test_format_block_width_one_plane
[16:28:14] [PASSED] drm_test_format_block_width_two_plane
[16:28:14] [PASSED] drm_test_format_block_width_three_plane
[16:28:14] [PASSED] drm_test_format_block_width_tiled
[16:28:14] [PASSED] drm_test_format_block_height_invalid
[16:28:14] [PASSED] drm_test_format_block_height_one_plane
[16:28:14] [PASSED] drm_test_format_block_height_two_plane
[16:28:14] [PASSED] drm_test_format_block_height_three_plane
[16:28:14] [PASSED] drm_test_format_block_height_tiled
[16:28:14] [PASSED] drm_test_format_min_pitch_invalid
[16:28:14] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[16:28:14] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[16:28:14] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[16:28:14] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[16:28:14] [PASSED] drm_test_format_min_pitch_two_plane
[16:28:14] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[16:28:14] [PASSED] drm_test_format_min_pitch_tiled
[16:28:14] =================== [PASSED] drm_format ====================
[16:28:14] ============== drm_framebuffer (10 subtests) ===============
[16:28:14] ========== drm_test_framebuffer_check_src_coords  ==========
[16:28:14] [PASSED] Success: source fits into fb
[16:28:14] [PASSED] Fail: overflowing fb with x-axis coordinate
[16:28:14] [PASSED] Fail: overflowing fb with y-axis coordinate
[16:28:14] [PASSED] Fail: overflowing fb with source width
[16:28:14] [PASSED] Fail: overflowing fb with source height
[16:28:14] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[16:28:14] [PASSED] drm_test_framebuffer_cleanup
[16:28:14] =============== drm_test_framebuffer_create  ===============
[16:28:14] [PASSED] ABGR8888 normal sizes
[16:28:14] [PASSED] ABGR8888 max sizes
[16:28:14] [PASSED] ABGR8888 pitch greater than min required
[16:28:14] [PASSED] ABGR8888 pitch less than min required
[16:28:14] [PASSED] ABGR8888 Invalid width
[16:28:14] [PASSED] ABGR8888 Invalid buffer handle
[16:28:14] [PASSED] No pixel format
[16:28:14] [PASSED] ABGR8888 Width 0
[16:28:14] [PASSED] ABGR8888 Height 0
[16:28:14] [PASSED] ABGR8888 Out of bound height * pitch combination
[16:28:14] [PASSED] ABGR8888 Large buffer offset
[16:28:14] [PASSED] ABGR8888 Buffer offset for inexistent plane
[16:28:14] [PASSED] ABGR8888 Invalid flag
[16:28:14] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[16:28:14] [PASSED] ABGR8888 Valid buffer modifier
[16:28:14] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[16:28:14] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[16:28:14] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[16:28:14] [PASSED] NV12 Normal sizes
[16:28:14] [PASSED] NV12 Max sizes
[16:28:14] [PASSED] NV12 Invalid pitch
[16:28:14] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[16:28:14] [PASSED] NV12 different  modifier per-plane
[16:28:14] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[16:28:14] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[16:28:14] [PASSED] NV12 Modifier for inexistent plane
[16:28:14] [PASSED] NV12 Handle for inexistent plane
[16:28:14] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[16:28:14] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[16:28:14] [PASSED] YVU420 Normal sizes
[16:28:14] [PASSED] YVU420 Max sizes
[16:28:14] [PASSED] YVU420 Invalid pitch
[16:28:14] [PASSED] YVU420 Different pitches
[16:28:14] [PASSED] YVU420 Different buffer offsets/pitches
[16:28:14] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[16:28:14] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[16:28:14] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[16:28:14] [PASSED] YVU420 Valid modifier
[16:28:14] [PASSED] YVU420 Different modifiers per plane
[16:28:14] [PASSED] YVU420 Modifier for inexistent plane
[16:28:14] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[16:28:14] [PASSED] X0L2 Normal sizes
[16:28:14] [PASSED] X0L2 Max sizes
[16:28:14] [PASSED] X0L2 Invalid pitch
[16:28:14] [PASSED] X0L2 Pitch greater than minimum required
[16:28:14] [PASSED] X0L2 Handle for inexistent plane
[16:28:14] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[16:28:14] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[16:28:14] [PASSED] X0L2 Valid modifier
[16:28:14] [PASSED] X0L2 Modifier for inexistent plane
[16:28:14] =========== [PASSED] drm_test_framebuffer_create ===========
[16:28:14] [PASSED] drm_test_framebuffer_free
[16:28:14] [PASSED] drm_test_framebuffer_init
[16:28:14] [PASSED] drm_test_framebuffer_init_bad_format
[16:28:14] [PASSED] drm_test_framebuffer_init_dev_mismatch
[16:28:14] [PASSED] drm_test_framebuffer_lookup
[16:28:14] [PASSED] drm_test_framebuffer_lookup_inexistent
[16:28:14] [PASSED] drm_test_framebuffer_modifiers_not_supported
[16:28:14] ================= [PASSED] drm_framebuffer =================
[16:28:14] ================ drm_gem_shmem (8 subtests) ================
[16:28:14] [PASSED] drm_gem_shmem_test_obj_create
[16:28:14] [PASSED] drm_gem_shmem_test_obj_create_private
[16:28:14] [PASSED] drm_gem_shmem_test_pin_pages
[16:28:14] [PASSED] drm_gem_shmem_test_vmap
[16:28:14] [PASSED] drm_gem_shmem_test_get_sg_table
[16:28:14] [PASSED] drm_gem_shmem_test_get_pages_sgt
[16:28:14] [PASSED] drm_gem_shmem_test_madvise
[16:28:14] [PASSED] drm_gem_shmem_test_purge
[16:28:14] ================== [PASSED] drm_gem_shmem ==================
[16:28:14] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[16:28:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[16:28:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[16:28:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[16:28:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[16:28:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[16:28:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[16:28:14] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[16:28:14] [PASSED] Automatic
[16:28:14] [PASSED] Full
[16:28:14] [PASSED] Limited 16:235
[16:28:14] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[16:28:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[16:28:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[16:28:14] [PASSED] drm_test_check_disable_connector
[16:28:14] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[16:28:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[16:28:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[16:28:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[16:28:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[16:28:14] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[16:28:14] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[16:28:14] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[16:28:14] [PASSED] drm_test_check_output_bpc_dvi
[16:28:14] [PASSED] drm_test_check_output_bpc_format_vic_1
[16:28:14] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[16:28:14] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[16:28:14] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[16:28:14] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[16:28:14] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[16:28:14] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[16:28:14] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[16:28:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[16:28:14] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[16:28:14] [PASSED] drm_test_check_broadcast_rgb_value
[16:28:14] [PASSED] drm_test_check_bpc_8_value
[16:28:14] [PASSED] drm_test_check_bpc_10_value
[16:28:14] [PASSED] drm_test_check_bpc_12_value
[16:28:14] [PASSED] drm_test_check_format_value
[16:28:14] [PASSED] drm_test_check_tmds_char_value
[16:28:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[16:28:14] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[16:28:14] [PASSED] drm_test_check_mode_valid
[16:28:14] [PASSED] drm_test_check_mode_valid_reject
[16:28:14] [PASSED] drm_test_check_mode_valid_reject_rate
[16:28:14] [PASSED] drm_test_check_mode_valid_reject_max_clock
[16:28:14] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[16:28:14] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[16:28:14] [PASSED] drm_test_check_infoframes
[16:28:14] [PASSED] drm_test_check_reject_avi_infoframe
[16:28:14] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[16:28:14] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[16:28:14] [PASSED] drm_test_check_reject_audio_infoframe
[16:28:14] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[16:28:14] ================= drm_managed (2 subtests) =================
[16:28:14] [PASSED] drm_test_managed_release_action
[16:28:14] [PASSED] drm_test_managed_run_action
[16:28:14] =================== [PASSED] drm_managed ===================
[16:28:14] =================== drm_mm (6 subtests) ====================
[16:28:14] [PASSED] drm_test_mm_init
[16:28:14] [PASSED] drm_test_mm_debug
[16:28:14] [PASSED] drm_test_mm_align32
[16:28:14] [PASSED] drm_test_mm_align64
[16:28:14] [PASSED] drm_test_mm_lowest
[16:28:14] [PASSED] drm_test_mm_highest
[16:28:14] ===================== [PASSED] drm_mm ======================
[16:28:14] ============= drm_modes_analog_tv (5 subtests) =============
[16:28:14] [PASSED] drm_test_modes_analog_tv_mono_576i
[16:28:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[16:28:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[16:28:14] [PASSED] drm_test_modes_analog_tv_pal_576i
[16:28:14] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[16:28:14] =============== [PASSED] drm_modes_analog_tv ===============
[16:28:14] ============== drm_plane_helper (2 subtests) ===============
[16:28:14] =============== drm_test_check_plane_state  ================
[16:28:14] [PASSED] clipping_simple
[16:28:14] [PASSED] clipping_rotate_reflect
[16:28:14] [PASSED] positioning_simple
[16:28:14] [PASSED] upscaling
[16:28:14] [PASSED] downscaling
[16:28:14] [PASSED] rounding1
[16:28:14] [PASSED] rounding2
[16:28:14] [PASSED] rounding3
[16:28:14] [PASSED] rounding4
[16:28:14] =========== [PASSED] drm_test_check_plane_state ============
[16:28:14] =========== drm_test_check_invalid_plane_state  ============
[16:28:14] [PASSED] positioning_invalid
[16:28:14] [PASSED] upscaling_invalid
[16:28:14] [PASSED] downscaling_invalid
[16:28:14] ======= [PASSED] drm_test_check_invalid_plane_state ========
[16:28:14] ================ [PASSED] drm_plane_helper =================
[16:28:14] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[16:28:14] ====== drm_test_connector_helper_tv_get_modes_check  =======
[16:28:14] [PASSED] None
[16:28:14] [PASSED] PAL
[16:28:14] [PASSED] NTSC
[16:28:14] [PASSED] Both, NTSC Default
[16:28:14] [PASSED] Both, PAL Default
[16:28:14] [PASSED] Both, NTSC Default, with PAL on command-line
[16:28:14] [PASSED] Both, PAL Default, with NTSC on command-line
[16:28:14] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[16:28:14] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[16:28:14] ================== drm_rect (9 subtests) ===================
[16:28:14] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[16:28:14] [PASSED] drm_test_rect_clip_scaled_not_clipped
[16:28:14] [PASSED] drm_test_rect_clip_scaled_clipped
[16:28:14] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[16:28:14] ================= drm_test_rect_intersect  =================
[16:28:14] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[16:28:14] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[16:28:14] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[16:28:14] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[16:28:14] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[16:28:14] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[16:28:14] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[16:28:14] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[16:28:14] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[16:28:14] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[16:28:14] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[16:28:14] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[16:28:14] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[16:28:14] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[16:28:14] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[16:28:14] ============= [PASSED] drm_test_rect_intersect =============
[16:28:14] ================ drm_test_rect_calc_hscale  ================
[16:28:14] [PASSED] normal use
[16:28:14] [PASSED] out of max range
[16:28:14] [PASSED] out of min range
[16:28:14] [PASSED] zero dst
[16:28:14] [PASSED] negative src
[16:28:14] [PASSED] negative dst
[16:28:14] ============ [PASSED] drm_test_rect_calc_hscale ============
[16:28:14] ================ drm_test_rect_calc_vscale  ================
[16:28:14] [PASSED] normal use
[16:28:14] [PASSED] out of max range
[16:28:14] [PASSED] out of min range
[16:28:14] [PASSED] zero dst
[16:28:14] [PASSED] negative src
[16:28:14] [PASSED] negative dst
[16:28:14] ============ [PASSED] drm_test_rect_calc_vscale ============
[16:28:14] ================== drm_test_rect_rotate  ===================
[16:28:14] [PASSED] reflect-x
[16:28:14] [PASSED] reflect-y
[16:28:14] [PASSED] rotate-0
[16:28:14] [PASSED] rotate-90
[16:28:14] [PASSED] rotate-180
[16:28:14] [PASSED] rotate-270
[16:28:14] ============== [PASSED] drm_test_rect_rotate ===============
[16:28:14] ================ drm_test_rect_rotate_inv  =================
[16:28:14] [PASSED] reflect-x
[16:28:14] [PASSED] reflect-y
[16:28:14] [PASSED] rotate-0
[16:28:14] [PASSED] rotate-90
[16:28:14] [PASSED] rotate-180
[16:28:14] [PASSED] rotate-270
[16:28:14] ============ [PASSED] drm_test_rect_rotate_inv =============
[16:28:14] ==================== [PASSED] drm_rect =====================
[16:28:14] ============ drm_sysfb_modeset_test (1 subtest) ============
[16:28:14] ============ drm_test_sysfb_build_fourcc_list  =============
[16:28:14] [PASSED] no native formats
[16:28:14] [PASSED] XRGB8888 as native format
[16:28:14] [PASSED] remove duplicates
[16:28:14] [PASSED] convert alpha formats
[16:28:14] [PASSED] random formats
[16:28:14] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[16:28:14] ============= [PASSED] drm_sysfb_modeset_test ==============
[16:28:14] ================== drm_fixp (2 subtests) ===================
[16:28:14] [PASSED] drm_test_int2fixp
[16:28:14] [PASSED] drm_test_sm2fixp
[16:28:14] ==================== [PASSED] drm_fixp =====================
[16:28:14] ============================================================
[16:28:14] Testing complete. Ran 621 tests: passed: 621
[16:28:14] Elapsed time: 26.063s total, 1.771s configuring, 24.126s building, 0.132s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[16:28:15] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:28:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:28:26] Starting KUnit Kernel (1/1)...
[16:28:26] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:28:26] ================= ttm_device (5 subtests) ==================
[16:28:26] [PASSED] ttm_device_init_basic
[16:28:26] [PASSED] ttm_device_init_multiple
[16:28:26] [PASSED] ttm_device_fini_basic
[16:28:26] [PASSED] ttm_device_init_no_vma_man
[16:28:26] ================== ttm_device_init_pools  ==================
[16:28:26] [PASSED] No DMA allocations, no DMA32 required
[16:28:26] [PASSED] DMA allocations, DMA32 required
[16:28:26] [PASSED] No DMA allocations, DMA32 required
[16:28:26] [PASSED] DMA allocations, no DMA32 required
[16:28:26] ============== [PASSED] ttm_device_init_pools ==============
[16:28:26] =================== [PASSED] ttm_device ====================
[16:28:26] ================== ttm_pool (8 subtests) ===================
[16:28:26] ================== ttm_pool_alloc_basic  ===================
[16:28:26] [PASSED] One page
[16:28:26] [PASSED] More than one page
[16:28:26] [PASSED] Above the allocation limit
[16:28:26] [PASSED] One page, with coherent DMA mappings enabled
[16:28:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[16:28:26] ============== [PASSED] ttm_pool_alloc_basic ===============
[16:28:26] ============== ttm_pool_alloc_basic_dma_addr  ==============
[16:28:26] [PASSED] One page
[16:28:26] [PASSED] More than one page
[16:28:26] [PASSED] Above the allocation limit
[16:28:26] [PASSED] One page, with coherent DMA mappings enabled
[16:28:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[16:28:26] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[16:28:26] [PASSED] ttm_pool_alloc_order_caching_match
[16:28:26] [PASSED] ttm_pool_alloc_caching_mismatch
[16:28:26] [PASSED] ttm_pool_alloc_order_mismatch
[16:28:26] [PASSED] ttm_pool_free_dma_alloc
[16:28:26] [PASSED] ttm_pool_free_no_dma_alloc
[16:28:26] [PASSED] ttm_pool_fini_basic
[16:28:26] ==================== [PASSED] ttm_pool =====================
[16:28:26] ================ ttm_resource (8 subtests) =================
[16:28:26] ================= ttm_resource_init_basic  =================
[16:28:26] [PASSED] Init resource in TTM_PL_SYSTEM
[16:28:26] [PASSED] Init resource in TTM_PL_VRAM
[16:28:26] [PASSED] Init resource in a private placement
[16:28:26] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[16:28:26] ============= [PASSED] ttm_resource_init_basic =============
[16:28:26] [PASSED] ttm_resource_init_pinned
[16:28:26] [PASSED] ttm_resource_fini_basic
[16:28:26] [PASSED] ttm_resource_manager_init_basic
[16:28:26] [PASSED] ttm_resource_manager_usage_basic
[16:28:26] [PASSED] ttm_resource_manager_set_used_basic
[16:28:26] [PASSED] ttm_sys_man_alloc_basic
[16:28:26] [PASSED] ttm_sys_man_free_basic
[16:28:26] ================== [PASSED] ttm_resource ===================
[16:28:26] =================== ttm_tt (15 subtests) ===================
[16:28:26] ==================== ttm_tt_init_basic  ====================
[16:28:26] [PASSED] Page-aligned size
[16:28:26] [PASSED] Extra pages requested
[16:28:26] ================ [PASSED] ttm_tt_init_basic ================
[16:28:26] [PASSED] ttm_tt_init_misaligned
[16:28:26] [PASSED] ttm_tt_fini_basic
[16:28:26] [PASSED] ttm_tt_fini_sg
[16:28:26] [PASSED] ttm_tt_fini_shmem
[16:28:26] [PASSED] ttm_tt_create_basic
[16:28:26] [PASSED] ttm_tt_create_invalid_bo_type
[16:28:26] [PASSED] ttm_tt_create_ttm_exists
[16:28:26] [PASSED] ttm_tt_create_failed
[16:28:26] [PASSED] ttm_tt_destroy_basic
[16:28:26] [PASSED] ttm_tt_populate_null_ttm
[16:28:26] [PASSED] ttm_tt_populate_populated_ttm
[16:28:26] [PASSED] ttm_tt_unpopulate_basic
[16:28:26] [PASSED] ttm_tt_unpopulate_empty_ttm
[16:28:26] [PASSED] ttm_tt_swapin_basic
[16:28:26] ===================== [PASSED] ttm_tt ======================
[16:28:26] =================== ttm_bo (14 subtests) ===================
[16:28:26] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[16:28:26] [PASSED] Cannot be interrupted and sleeps
[16:28:26] [PASSED] Cannot be interrupted, locks straight away
[16:28:26] [PASSED] Can be interrupted, sleeps
[16:28:26] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[16:28:26] [PASSED] ttm_bo_reserve_locked_no_sleep
[16:28:26] [PASSED] ttm_bo_reserve_no_wait_ticket
[16:28:26] [PASSED] ttm_bo_reserve_double_resv
[16:28:26] [PASSED] ttm_bo_reserve_interrupted
[16:28:26] [PASSED] ttm_bo_reserve_deadlock
[16:28:26] [PASSED] ttm_bo_unreserve_basic
[16:28:26] [PASSED] ttm_bo_unreserve_pinned
[16:28:26] [PASSED] ttm_bo_unreserve_bulk
[16:28:26] [PASSED] ttm_bo_fini_basic
[16:28:26] [PASSED] ttm_bo_fini_shared_resv
[16:28:26] [PASSED] ttm_bo_pin_basic
[16:28:26] [PASSED] ttm_bo_pin_unpin_resource
[16:28:26] [PASSED] ttm_bo_multiple_pin_one_unpin
[16:28:26] ===================== [PASSED] ttm_bo ======================
[16:28:26] ============== ttm_bo_validate (22 subtests) ===============
[16:28:26] ============== ttm_bo_init_reserved_sys_man  ===============
[16:28:26] [PASSED] Buffer object for userspace
[16:28:26] [PASSED] Kernel buffer object
[16:28:26] [PASSED] Shared buffer object
[16:28:26] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[16:28:26] ============== ttm_bo_init_reserved_mock_man  ==============
[16:28:26] [PASSED] Buffer object for userspace
[16:28:26] [PASSED] Kernel buffer object
[16:28:26] [PASSED] Shared buffer object
[16:28:26] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[16:28:26] [PASSED] ttm_bo_init_reserved_resv
[16:28:26] ================== ttm_bo_validate_basic  ==================
[16:28:26] [PASSED] Buffer object for userspace
[16:28:26] [PASSED] Kernel buffer object
[16:28:26] [PASSED] Shared buffer object
[16:28:26] ============== [PASSED] ttm_bo_validate_basic ==============
[16:28:26] [PASSED] ttm_bo_validate_invalid_placement
[16:28:26] ============= ttm_bo_validate_same_placement  ==============
[16:28:26] [PASSED] System manager
[16:28:26] [PASSED] VRAM manager
[16:28:26] ========= [PASSED] ttm_bo_validate_same_placement ==========
[16:28:26] [PASSED] ttm_bo_validate_failed_alloc
[16:28:26] [PASSED] ttm_bo_validate_pinned
[16:28:26] [PASSED] ttm_bo_validate_busy_placement
[16:28:26] ================ ttm_bo_validate_multihop  =================
[16:28:26] [PASSED] Buffer object for userspace
[16:28:26] [PASSED] Kernel buffer object
[16:28:26] [PASSED] Shared buffer object
[16:28:26] ============ [PASSED] ttm_bo_validate_multihop =============
[16:28:26] ========== ttm_bo_validate_no_placement_signaled  ==========
[16:28:26] [PASSED] Buffer object in system domain, no page vector
[16:28:26] [PASSED] Buffer object in system domain with an existing page vector
[16:28:26] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[16:28:26] ======== ttm_bo_validate_no_placement_not_signaled  ========
[16:28:26] [PASSED] Buffer object for userspace
[16:28:26] [PASSED] Kernel buffer object
[16:28:26] [PASSED] Shared buffer object
[16:28:26] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[16:28:26] [PASSED] ttm_bo_validate_move_fence_signaled
[16:28:26] ========= ttm_bo_validate_move_fence_not_signaled  =========
[16:28:26] [PASSED] Waits for GPU
[16:28:26] [PASSED] Tries to lock straight away
[16:28:26] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[16:28:26] [PASSED] ttm_bo_validate_swapout
[16:28:26] [PASSED] ttm_bo_validate_happy_evict
[16:28:26] [PASSED] ttm_bo_validate_all_pinned_evict
[16:28:26] [PASSED] ttm_bo_validate_allowed_only_evict
[16:28:26] [PASSED] ttm_bo_validate_deleted_evict
[16:28:26] [PASSED] ttm_bo_validate_busy_domain_evict
[16:28:26] [PASSED] ttm_bo_validate_evict_gutting
[16:28:26] [PASSED] ttm_bo_validate_recrusive_evict
[16:28:26] ================= [PASSED] ttm_bo_validate =================
[16:28:26] ============================================================
[16:28:26] Testing complete. Ran 102 tests: passed: 102
[16:28:26] Elapsed time: 11.612s total, 1.750s configuring, 9.597s building, 0.227s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 18+ messages in thread

* ✓ Xe.CI.BAT: success for drm/i915/display: reduce the pm demand peak bw based on display data rate
  2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
                   ` (11 preceding siblings ...)
  2026-05-11 16:28 ` ✓ CI.KUnit: success for drm/i915/display: reduce the pm demand peak bw based on display data rate Patchwork
@ 2026-05-11 17:33 ` Patchwork
  2026-05-11 19:30 ` ✗ Xe.CI.FULL: failure " Patchwork
  13 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2026-05-11 17:33 UTC (permalink / raw)
  To: Vinod Govindapillai; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 987 bytes --]

== Series Details ==

Series: drm/i915/display: reduce the pm demand peak bw based on display data rate
URL   : https://patchwork.freedesktop.org/series/166316/
State : success

== Summary ==

CI Bug Log - changes from xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565_BAT -> xe-pw-166316v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565 -> xe-pw-166316v1

  IGT_8902: d28bd0b9e0347c58ca9b012c02de7e2ad5ffe847 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565: f8ee23694aa6be213355905a78f79bb1b0861565
  xe-pw-166316v1: 166316v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/index.html

[-- Attachment #2: Type: text/html, Size: 1535 bytes --]

^ permalink raw reply	[flat|nested] 18+ messages in thread

* ✗ Xe.CI.FULL: failure for drm/i915/display: reduce the pm demand peak bw based on display data rate
  2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
                   ` (12 preceding siblings ...)
  2026-05-11 17:33 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-05-11 19:30 ` Patchwork
  13 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2026-05-11 19:30 UTC (permalink / raw)
  To: Vinod Govindapillai; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 55526 bytes --]

== Series Details ==

Series: drm/i915/display: reduce the pm demand peak bw based on display data rate
URL   : https://patchwork.freedesktop.org/series/166316/
State : failure

== Summary ==

CI Bug Log - changes from xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565_FULL -> xe-pw-166316v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-166316v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-166316v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-166316v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][1] -> [DMESG-FAIL][2] +2 other tests dmesg-fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  
Known issues
------------

  Here are the changes found in xe-pw-166316v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#3279])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_atomic_transition@plane-all-transition:
    - shard-bmg:          [PASS][4] -> [INCOMPLETE][5] ([Intel XE#6819] / [Intel XE#7961])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-8/igt@kms_atomic_transition@plane-all-transition.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-3/igt@kms_atomic_transition@plane-all-transition.html

  * igt@kms_atomic_transition@plane-all-transition@pipe-a-hdmi-a-3:
    - shard-bmg:          [PASS][6] -> [DMESG-WARN][7] ([Intel XE#6819])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-8/igt@kms_atomic_transition@plane-all-transition@pipe-a-hdmi-a-3.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-3/igt@kms_atomic_transition@plane-all-transition@pipe-a-hdmi-a-3.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#1124]) +3 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-target-3840x2160p:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#7679])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-5/igt@kms_bw@connected-linear-tiling-2-displays-target-3840x2160p.html

  * igt@kms_bw@linear-tiling-3-displays-target-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#367])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_bw@linear-tiling-3-displays-target-2160x1440p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#2669] / [Intel XE#7389]) +3 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2887])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][13] ([Intel XE#7084]) +1 other test incomplete
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#3432]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#2887]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#306] / [Intel XE#7358])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_edid@dp-edid-change-during-hibernate:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2252])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html

  * igt@kms_chamelium_hpd@hdmi-hpd-fast:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#373]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_chamelium_hpd@hdmi-hpd-fast.html

  * igt@kms_content_protection@atomic-hdcp14:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#7642]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-5/igt@kms_content_protection@atomic-hdcp14.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#2321] / [Intel XE#7355])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2321] / [Intel XE#7355])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_crc@cursor-random-256x85:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#1424])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_cursor_crc@cursor-random-256x85.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#309] / [Intel XE#7343])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#4354] / [Intel XE#5882])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_feature_discovery@chamelium:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#701] / [Intel XE#7359])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@display-1x:
    - shard-bmg:          [PASS][26] -> [SKIP][27] ([Intel XE#6557] / [Intel XE#6703])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_feature_discovery@display-1x.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_feature_discovery@display-1x.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#1421]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@modeset-vs-vblank-race@a-dp2:
    - shard-bmg:          [PASS][29] -> [FAIL][30] ([Intel XE#3098]) +1 other test fail
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-6/igt@kms_flip@modeset-vs-vblank-race@a-dp2.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@kms_flip@modeset-vs-vblank-race@a-dp2.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#7178] / [Intel XE#7351])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#7178] / [Intel XE#7351])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#7061] / [Intel XE#7356])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrshdr-rgb101010-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#6312]) +7 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_frontbuffer_tracking@drrshdr-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#4141]) +3 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#656] / [Intel XE#7905]) +13 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#7061] / [Intel XE#7356])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2311]) +2 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#6312] / [Intel XE#651]) +4 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-move:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#7865]) +8 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-shrfb-plflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#7905]) +14 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2313]) +4 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html

  * igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010:
    - shard-bmg:          [PASS][43] -> [SKIP][44] ([Intel XE#7915]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-9/igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-1/igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#7591])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#7283]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#7283])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#1489]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#4608])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#4608] / [Intel XE#7304])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#2893] / [Intel XE#7304]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-pr-cursor-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@kms_psr@fbc-pr-cursor-plane-onoff.html

  * igt@kms_psr@fbc-pr-dpms:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#1406])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_psr@fbc-pr-dpms.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@xe_eudebug@basic-vm-bind-ufence-delay-ack:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#7636]) +4 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@xe_eudebug@basic-vm-bind-ufence-delay-ack.html

  * igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-sram:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#7636])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-sram.html

  * igt@xe_eudebug_sriov@deny-sriov:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#4518] / [Intel XE#7404])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-5/igt@xe_eudebug_sriov@deny-sriov.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][59] -> [INCOMPLETE][60] ([Intel XE#6321]) +1 other test incomplete
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-2/igt@xe_evict@evict-mixed-many-threads-small.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-3/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#6540] / [Intel XE#688]) +3 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-5/igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd.html

  * igt@xe_exec_balancer@twice-parallel-basic:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#7482]) +4 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@xe_exec_balancer@twice-parallel-basic.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#2322] / [Intel XE#7372])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][64] ([Intel XE#1392]) +2 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#7136])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@xe_exec_fault_mode@many-execqueues-multi-queue.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-race-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#7136]) +3 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-race-prefetch.html

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-dyn-priority:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#6874]) +9 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-dyn-priority.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-dyn-priority:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#6874])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-dyn-priority.html

  * igt@xe_exec_reset@cm-multi-queue-cat-error-on-secondary:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#7866])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@xe_exec_reset@cm-multi-queue-cat-error-on-secondary.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-wt-multi-vma:
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#6196])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-wt-multi-vma.html

  * igt@xe_exec_system_allocator@threads-many-execqueues-mmap:
    - shard-bmg:          [PASS][71] -> [SKIP][72] ([Intel XE#6703]) +279 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@xe_exec_system_allocator@threads-many-execqueues-mmap.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@xe_exec_system_allocator@threads-many-execqueues-mmap.html

  * igt@xe_exec_threads@threads-multi-queue-fd-basic:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#7138]) +1 other test skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@xe_exec_threads@threads-multi-queue-fd-basic.html

  * igt@xe_exec_threads@threads-multi-queue-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#7138]) +3 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@xe_exec_threads@threads-multi-queue-userptr-rebind.html

  * igt@xe_multigpu_svm@mgpu-pagefault-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][75] ([Intel XE#6964])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@xe_multigpu_svm@mgpu-pagefault-prefetch.html

  * igt@xe_page_reclaim@basic-mixed:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#7793])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-5/igt@xe_page_reclaim@basic-mixed.html

  * igt@xe_pat@pat-index-xelp:
    - shard-lnl:          NOTRUN -> [SKIP][77] ([Intel XE#7590] / [Intel XE#977])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@xe_pat@pat-index-xelp.html

  * igt@xe_peer2peer@write:
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#1061] / [Intel XE#7326] / [Intel XE#7353])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@xe_peer2peer@write.html

  * igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#4733] / [Intel XE#7417])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy.html

  * igt@xe_sriov_admin@preempt-timeout-write-readback-vfs-disabled:
    - shard-lnl:          NOTRUN -> [SKIP][80] ([Intel XE#7174])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@xe_sriov_admin@preempt-timeout-write-readback-vfs-disabled.html

  * igt@xe_sriov_flr@flr-each-isolation:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#3342])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@xe_sriov_flr@flr-each-isolation.html

  * igt@xe_vm@overcommit-nonfault-vram-no-lr:
    - shard-lnl:          NOTRUN -> [SKIP][82] ([Intel XE#7892])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-8/igt@xe_vm@overcommit-nonfault-vram-no-lr.html

  
#### Possible fixes ####

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [FAIL][83] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_hdr@invalid-metadata-sizes@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-bmg:          [SKIP][85] ([Intel XE#7915]) -> [PASS][86] +1 other test pass
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_hdr@invalid-metadata-sizes@pipe-a-hdmi-a-3-xrgb16161616f.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_hdr@invalid-metadata-sizes@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@xe_pat@pt-caching:
    - shard-bmg:          [ABORT][87] ([Intel XE#7893]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-7/igt@xe_pat@pt-caching.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-4/igt@xe_pat@pt-caching.html

  * igt@xe_survivability@runtime-survivability:
    - shard-bmg:          [DMESG-WARN][89] ([Intel XE#6627] / [Intel XE#7419]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-7/igt@xe_survivability@runtime-survivability.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-3/igt@xe_survivability@runtime-survivability.html

  
#### Warnings ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-bmg:          [SKIP][91] ([Intel XE#2370]) -> [SKIP][92] ([Intel XE#6703])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-90:
    - shard-bmg:          [SKIP][93] ([Intel XE#2327]) -> [SKIP][94] ([Intel XE#6703])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-bmg:          [SKIP][95] ([Intel XE#2328] / [Intel XE#7367]) -> [SKIP][96] ([Intel XE#6703])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_big_fb@yf-tiled-addfb.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-bmg:          [SKIP][97] ([Intel XE#1124]) -> [SKIP][98] ([Intel XE#6703]) +4 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_bw@linear-tiling-2-displays-target-2160x1440p:
    - shard-bmg:          [SKIP][99] ([Intel XE#367]) -> [SKIP][100] ([Intel XE#6703]) +1 other test skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_bw@linear-tiling-2-displays-target-2160x1440p.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_bw@linear-tiling-2-displays-target-2160x1440p.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          [SKIP][101] ([Intel XE#2887]) -> [SKIP][102] ([Intel XE#6703]) +5 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs:
    - shard-bmg:          [SKIP][103] ([Intel XE#3432]) -> [SKIP][104] ([Intel XE#6703]) +1 other test skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-bmg:          [SKIP][105] ([Intel XE#2325] / [Intel XE#7358]) -> [SKIP][106] ([Intel XE#6703])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_chamelium_color@ctm-blue-to-red.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_hpd@hdmi-hpd-fast:
    - shard-bmg:          [SKIP][107] ([Intel XE#2252]) -> [SKIP][108] ([Intel XE#6703]) +2 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_chamelium_hpd@hdmi-hpd-fast.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_chamelium_hpd@hdmi-hpd-fast.html

  * igt@kms_content_protection@atomic-dpms-hdcp14:
    - shard-bmg:          [FAIL][109] ([Intel XE#3304] / [Intel XE#7374]) -> [SKIP][110] ([Intel XE#6703])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_content_protection@atomic-dpms-hdcp14.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_content_protection@atomic-dpms-hdcp14.html

  * igt@kms_content_protection@legacy:
    - shard-bmg:          [FAIL][111] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) -> [SKIP][112] ([Intel XE#6703])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_content_protection@legacy.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-bmg:          [SKIP][113] ([Intel XE#2321] / [Intel XE#7355]) -> [SKIP][114] ([Intel XE#6703])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_cursor_crc@cursor-offscreen-512x170.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-random-256x85:
    - shard-bmg:          [SKIP][115] ([Intel XE#2320]) -> [SKIP][116] ([Intel XE#6703]) +1 other test skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_cursor_crc@cursor-random-256x85.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_cursor_crc@cursor-random-256x85.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-bmg:          [SKIP][117] ([Intel XE#4354] / [Intel XE#5882]) -> [SKIP][118] ([Intel XE#6703])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_dp_link_training@non-uhbr-mst.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_fbcon_fbt@psr:
    - shard-bmg:          [SKIP][119] ([Intel XE#6126] / [Intel XE#776]) -> [SKIP][120] ([Intel XE#6703])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_fbcon_fbt@psr.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@chamelium:
    - shard-bmg:          [SKIP][121] ([Intel XE#2372] / [Intel XE#7359]) -> [SKIP][122] ([Intel XE#6703])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_feature_discovery@chamelium.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_feature_discovery@chamelium.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-lnl:          [FAIL][123] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][124] ([Intel XE#301])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
    - shard-bmg:          [SKIP][125] ([Intel XE#7178] / [Intel XE#7351]) -> [SKIP][126] ([Intel XE#6703])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x:
    - shard-bmg:          [SKIP][127] ([Intel XE#7179]) -> [SKIP][128] ([Intel XE#6703])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][129] ([Intel XE#4141]) -> [SKIP][130] ([Intel XE#6703]) +3 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][131] ([Intel XE#2311]) -> [SKIP][132] ([Intel XE#6703]) +25 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-pri-shrfb-draw-blt:
    - shard-bmg:          [SKIP][133] ([Intel XE#2313]) -> [SKIP][134] ([Intel XE#6703]) +24 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-pri-shrfb-draw-blt.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][135] ([Intel XE#3544] / [Intel XE#7916]) -> [SKIP][136] ([Intel XE#3544] / [Intel XE#7915] / [Intel XE#7916])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-3/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-bmg:          [SKIP][137] ([Intel XE#7916]) -> [SKIP][138] ([Intel XE#7915]) +1 other test skip
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-2/igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-3-xrgb16161616f.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-3/igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][139] ([Intel XE#1503]) -> [SKIP][140] ([Intel XE#6703])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_hdr@invalid-hdr.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_hdr@invalid-hdr.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-bmg:          [SKIP][141] ([Intel XE#7591]) -> [SKIP][142] ([Intel XE#6703])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier:
    - shard-bmg:          [SKIP][143] ([Intel XE#7283]) -> [SKIP][144] ([Intel XE#6703])
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-bmg:          [SKIP][145] ([Intel XE#2505] / [Intel XE#7447]) -> [SKIP][146] ([Intel XE#6703])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_pm_dc@deep-pkgc.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-bmg:          [SKIP][147] ([Intel XE#2499]) -> [SKIP][148] ([Intel XE#6703])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@kms_pm_lpsp@kms-lpsp.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf:
    - shard-bmg:          [SKIP][149] ([Intel XE#1489]) -> [SKIP][150] ([Intel XE#6703]) +3 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@psr-basic:
    - shard-bmg:          [SKIP][151] ([Intel XE#2234] / [Intel XE#2850]) -> [SKIP][152] ([Intel XE#6703]) +4 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_psr@psr-basic.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_psr@psr-basic.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-bmg:          [SKIP][153] ([Intel XE#3904] / [Intel XE#7342]) -> [SKIP][154] ([Intel XE#6703])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_scaling_modes@scaling-mode-full-aspect:
    - shard-bmg:          [SKIP][155] ([Intel XE#2413]) -> [SKIP][156] ([Intel XE#6703])
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_scaling_modes@scaling-mode-full-aspect.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_scaling_modes@scaling-mode-full-aspect.html

  * igt@kms_vrr@flip-suspend:
    - shard-bmg:          [SKIP][157] ([Intel XE#1499]) -> [SKIP][158] ([Intel XE#6703])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@kms_vrr@flip-suspend.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@kms_vrr@flip-suspend.html

  * igt@xe_eudebug@basic-vm-bind-ufence-reconnect:
    - shard-bmg:          [SKIP][159] ([Intel XE#7636]) -> [SKIP][160] ([Intel XE#6557] / [Intel XE#6703])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@xe_eudebug@basic-vm-bind-ufence-reconnect.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@xe_eudebug@basic-vm-bind-ufence-reconnect.html

  * igt@xe_eudebug_online@single-step:
    - shard-bmg:          [SKIP][161] ([Intel XE#7636]) -> [SKIP][162] ([Intel XE#6703]) +7 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@xe_eudebug_online@single-step.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@xe_eudebug_online@single-step.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind:
    - shard-bmg:          [SKIP][163] ([Intel XE#2322] / [Intel XE#7372]) -> [SKIP][164] ([Intel XE#6703]) +2 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-race-prefetch:
    - shard-bmg:          [SKIP][165] ([Intel XE#7136]) -> [SKIP][166] ([Intel XE#6703]) +7 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-race-prefetch.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-race-prefetch.html

  * igt@xe_exec_multi_queue@two-queues-basic-smem:
    - shard-bmg:          [SKIP][167] ([Intel XE#6874]) -> [SKIP][168] ([Intel XE#6703]) +12 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@xe_exec_multi_queue@two-queues-basic-smem.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@xe_exec_multi_queue@two-queues-basic-smem.html

  * igt@xe_exec_reset@cm-multi-queue-cat-error-on-secondary:
    - shard-bmg:          [SKIP][169] ([Intel XE#7866]) -> [SKIP][170] ([Intel XE#6703])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@xe_exec_reset@cm-multi-queue-cat-error-on-secondary.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@xe_exec_reset@cm-multi-queue-cat-error-on-secondary.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-rebind:
    - shard-bmg:          [SKIP][171] ([Intel XE#7138]) -> [SKIP][172] ([Intel XE#6703]) +3 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-rebind.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-rebind.html

  * igt@xe_mmap@small-bar:
    - shard-bmg:          [SKIP][173] ([Intel XE#586] / [Intel XE#7323] / [Intel XE#7384]) -> [SKIP][174] ([Intel XE#6703])
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@xe_mmap@small-bar.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@xe_mmap@small-bar.html

  * igt@xe_page_reclaim@many-vma-same-bo:
    - shard-bmg:          [SKIP][175] ([Intel XE#7793]) -> [SKIP][176] ([Intel XE#6703])
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@xe_page_reclaim@many-vma-same-bo.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@xe_page_reclaim@many-vma-same-bo.html

  * igt@xe_pat@pat-index-xelp:
    - shard-bmg:          [SKIP][177] ([Intel XE#2245] / [Intel XE#7590]) -> [SKIP][178] ([Intel XE#6703])
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@xe_pat@pat-index-xelp.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@xe_pat@pat-index-xelp.html

  * igt@xe_peer2peer@write:
    - shard-bmg:          [SKIP][179] ([Intel XE#2427] / [Intel XE#6953] / [Intel XE#7326] / [Intel XE#7353]) -> [SKIP][180] ([Intel XE#6953] / [Intel XE#7326] / [Intel XE#7353])
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@xe_peer2peer@write.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@xe_peer2peer@write.html

  * igt@xe_pm@s4-d3cold-basic-exec:
    - shard-bmg:          [SKIP][181] ([Intel XE#2284] / [Intel XE#7370]) -> [SKIP][182] ([Intel XE#6703])
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-5/igt@xe_pm@s4-d3cold-basic-exec.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@xe_pm@s4-d3cold-basic-exec.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-suspend:
    - shard-bmg:          [SKIP][183] ([Intel XE#4733] / [Intel XE#7417]) -> [SKIP][184] ([Intel XE#6703]) +1 other test skip
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@xe_pxp@pxp-stale-bo-exec-post-suspend.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@xe_pxp@pxp-stale-bo-exec-post-suspend.html

  * igt@xe_sriov_flr@flr-each-isolation:
    - shard-bmg:          [FAIL][185] ([Intel XE#6569]) -> [SKIP][186] ([Intel XE#6557] / [Intel XE#6703])
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565/shard-bmg-1/igt@xe_sriov_flr@flr-each-isolation.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/shard-bmg-2/igt@xe_sriov_flr@flr-each-isolation.html

  
  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
  [Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
  [Intel XE#2372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2372
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2427
  [Intel XE#2499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2499
  [Intel XE#2505]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2505
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3279]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3279
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4518]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4518
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/586
  [Intel XE#5882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5882
  [Intel XE#6126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6126
  [Intel XE#6196]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6196
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#6627]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6627
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6819
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6953
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7323
  [Intel XE#7326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7326
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7353]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7353
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7359
  [Intel XE#7367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7367
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7384]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7384
  [Intel XE#7389]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7389
  [Intel XE#7404]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7404
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7419]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7419
  [Intel XE#7447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7447
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7591]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7591
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7866]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7866
  [Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
  [Intel XE#7893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7893
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7915
  [Intel XE#7916]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7916
  [Intel XE#7961]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7961
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977


Build changes
-------------

  * Linux: xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565 -> xe-pw-166316v1

  IGT_8902: d28bd0b9e0347c58ca9b012c02de7e2ad5ffe847 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5041-f8ee23694aa6be213355905a78f79bb1b0861565: f8ee23694aa6be213355905a78f79bb1b0861565
  xe-pw-166316v1: 166316v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166316v1/index.html

[-- Attachment #2: Type: text/html, Size: 66873 bytes --]

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH v2 09/11] drm/i915/bw: consolidate the debug info of bw/dgv/psf data
  2026-05-11 12:28 ` [PATCH v2 09/11] drm/i915/bw: consolidate the debug info of bw/dgv/psf data Vinod Govindapillai
@ 2026-05-12 11:49   ` Jani Nikula
  0 siblings, 0 replies; 18+ messages in thread
From: Jani Nikula @ 2026-05-12 11:49 UTC (permalink / raw)
  To: Vinod Govindapillai, intel-xe, intel-gfx
  Cc: vinod.govindapillai, ville.syrjala

On Mon, 11 May 2026, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote:
> Consolidate all the detaills about the bw, gqv and psf gv into
> a common function and present it in an organised format
>
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 40 +++++++++++++++++--------
>  1 file changed, 27 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 858da1710a61..0bda13a3e31b 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -483,6 +483,28 @@ static const struct intel_sa_info xe3lpd_3002_sa_info = {
>  	.derating = 10,
>  };
>  
> +static void debug_print_bw_info(struct intel_display *display)
> +{
> +	int num_groups = ARRAY_SIZE(display->bw.max);
> +	int i;
> +
> +	for (i = 0; i < num_groups; i++) {
> +		struct intel_bw_info *bi = &display->bw.max[i];
> +		int j;
> +
> +		drm_dbg_kms(display->drm, "BW%d: num_planes=%d num_qgv_points:%d\n",
> +			    i, bi->num_planes, bi->num_qgv_points);
> +
> +		for (j = 0; j < bi->num_qgv_points; j++)
> +			drm_dbg_kms(display->drm, "\tQGV %d: deratedbw=%u peakbw=%u\n",

Please use a drm_printer, and drm_printf_indent().

> +				    j,  bi->deratedbw[j], bi->peakbw[j]);
> +
> +		for (j = 0; j < bi->num_psf_gv_points; j++)
> +			drm_dbg_kms(display->drm, "\tPSF GV %d bw=%u\n",
> +				    j, bi->psf_bw[j]);
> +	}
> +}
> +
>  static bool is_tile_y_factored(struct intel_display *display)
>  {
>  	/* TGL supports Y-tile for LPDDR4/5, but not for DDR4 */
> @@ -544,12 +566,11 @@ static int icl_get_bw_info(struct intel_display *display,
>  
>  			bi->deratedbw[j] = min(maxdebw,
>  					       bw * (100 - sa->derating) / 100);
> -
> -			drm_dbg_kms(display->drm,
> -				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
> -				    i, j, bi->num_planes, bi->deratedbw[j]);
>  		}
>  	}
> +
> +	debug_print_bw_info(display);
> +
>  	/*
>  	 * In case if SAGV is disabled in BIOS, we always get 1
>  	 * SAGV point, but we can't send PCode commands to restrict it
> @@ -650,24 +671,17 @@ static int tgl_get_bw_info(struct intel_display *display,
>  			bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
>  							  num_channels *
>  							  qi.channel_width, 8);
> -
> -			drm_dbg_kms(display->drm,
> -				    "BW%d / QGV %d: num_planes=%d deratedbw=%u peakbw: %u\n",
> -				    i, j, bi->num_planes, bi->deratedbw[j],
> -				    bi->peakbw[j]);
>  		}
>  
>  		for (j = 0; j < qi.num_psf_points; j++) {
>  			const struct intel_psf_gv_point *sp = &qi.psf_points[j];
>  
>  			bi->psf_bw[j] = adl_calc_psf_bw(sp->clk);
> -
> -			drm_dbg_kms(display->drm,
> -				    "BW%d / PSF GV %d: num_planes=%d bw=%u\n",
> -				    i, j, bi->num_planes, bi->psf_bw[j]);
>  		}
>  	}
>  
> +	debug_print_bw_info(display);
> +
>  	/*
>  	 * In case if SAGV is disabled in BIOS, we always get 1
>  	 * SAGV point, but we can't send PCode commands to restrict it

-- 
Jani Nikula, Intel

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH v2 11/11] drm/i915/bw: insert a sw bw info entry to cater low data rate usecases
  2026-05-11 12:28 ` [PATCH v2 11/11] drm/i915/bw: insert a sw bw info entry to cater low data rate usecases Vinod Govindapillai
@ 2026-05-12 11:51   ` Jani Nikula
  2026-05-12 12:02     ` Govindapillai, Vinod
  0 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2026-05-12 11:51 UTC (permalink / raw)
  To: Vinod Govindapillai, intel-xe, intel-gfx
  Cc: vinod.govindapillai, ville.syrjala

On Mon, 11 May 2026, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote:
> In xe3+, soc can lower the fabric frequency when the display
> needs less bandwidth than the minimum GV point. This threshold
> has been defined as 20GB/s. To enable this,
>
> Add a new low bw info point with this peakbw threshold of 20GB/s
> based on the following conditions:
> 1. Only for xe3+ versions
> 2. There is at least one QGV point
> 3. Number QGV points is less than 8
> 4. Lowest peak bw across all the QGV point is less than 20 GB/s
> 5. And the derated bw is in the lowest peak bw qgv point is also
>    less than this threshold of 20GB/s
>
> This will make the driver to send this new threshold of 20GB/s
> as the pmdemand request whenever the bw required for a usecase
> is less than 20GB/s. The current pcode can handle this lower
> peakbw value and adjust the fabric frequency accordingly.
>
> Bspec: 68880
> Assisted-by: Copilot:claude-sonnet-4.6
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c       | 54 +++++++++++++++++++
>  .../drm/i915/display/intel_display_device.h   |  1 +
>  2 files changed, 55 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 938c0294c251..747279075e29 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -54,6 +54,8 @@ struct intel_qgv_point {
>  
>  #define DEPROGBWPCLIMIT		60
>  
> +#define PEAK_BW_THRESHOLD	20000
> +
>  struct intel_psf_gv_point {
>  	u8 clk; /* clock in multiples of 16.6666 MHz */
>  };
> @@ -589,6 +591,50 @@ static int icl_get_bw_info(struct intel_display *display,
>  	return 0;
>  }
>  
> +static bool xe3_check_lower_peakbw(struct intel_display *display,
> +				   const struct intel_qgv_info *qi,
> +				   int num_channels)

My pet peeve is naming functions with "check". Is it an assert? What
does it do? What does the return value mean?

BR,
Jani.

> +{
> +	unsigned int lowest_peakbw;
> +
> +	if (!HAS_PEAK_BW_THRESHOLD(display))
> +		return false;
> +
> +	if (qi->num_points >= I915_NUM_QGV_POINTS) {
> +		drm_warn(display->drm, "Cannot insert lowest QGV point, not enough space\n");
> +		return false;
> +	}
> +
> +	lowest_peakbw = DIV_ROUND_CLOSEST(qi->points[0].dclk *
> +					  qi->channel_width * num_channels, 8);
> +	if (lowest_peakbw <= PEAK_BW_THRESHOLD) {
> +		drm_dbg_kms(display->drm,
> +			    "Lowest QGV point has peak BW %u MB/s, no need to insert lower point\n",
> +			    lowest_peakbw);
> +		return false;
> +	}
> +
> +	return true;
> +}
> +
> +static void xe3_insert_lowest_qgv_point(struct intel_display *display,
> +					struct intel_bw_info *bi)
> +{
> +	if (bi->num_qgv_points >= ARRAY_SIZE(bi->deratedbw))
> +		return;
> +
> +	memmove(&bi->deratedbw[1], &bi->deratedbw[0],
> +		bi->num_qgv_points * sizeof(*bi->deratedbw));
> +
> +	memmove(&bi->peakbw[1], &bi->peakbw[0],
> +		bi->num_qgv_points * sizeof(*bi->peakbw));
> +
> +	/* Keep the derated bandwidth as the threshold*/
> +	bi->deratedbw[0] = PEAK_BW_THRESHOLD;
> +	bi->peakbw[0] = PEAK_BW_THRESHOLD;
> +	bi->num_qgv_points++;
> +}
> +
>  static int tgl_get_bw_info(struct intel_display *display,
>  			   const struct dram_info *dram_info,
>  			   const struct intel_sa_info *sa)
> @@ -598,6 +644,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>  	int num_channels = max_t(u8, 1, dram_info->num_channels);
>  	int ipqdepth, ipqdepthpch = 16;
>  	int dclk_max;
> +	bool insert_low_peakbw;
>  	int maxdebw, peakbw;
>  	int clperchgroup;
>  	int num_groups = ARRAY_SIZE(display->bw.max);
> @@ -636,6 +683,10 @@ static int tgl_get_bw_info(struct intel_display *display,
>  	 */
>  	clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * qi.deinterleave;
>  
> +	insert_low_peakbw = xe3_check_lower_peakbw(display, &qi, num_channels);
> +
> +	display->bw.max[i].num_planes = 0;
> +
>  	for (i = 0; i < num_groups; i++) {
>  		struct intel_bw_info *bi = &display->bw.max[i];
>  		struct intel_bw_info *bi_next;
> @@ -678,6 +729,9 @@ static int tgl_get_bw_info(struct intel_display *display,
>  							  qi.channel_width, 8);
>  		}
>  
> +		if (insert_low_peakbw)
> +			xe3_insert_lowest_qgv_point(display, bi);
> +
>  		for (j = 0; j < qi.num_psf_points; j++) {
>  			const struct intel_psf_gv_point *sp = &qi.psf_points[j];
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 65283286771a..b31ec42c3248 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -192,6 +192,7 @@ struct intel_display_platforms {
>  #define HAS_MBUS_JOINING(__display)	((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14)
>  #define HAS_MSO(__display)		(DISPLAY_VER(__display) >= 12)
>  #define HAS_OVERLAY(__display)		(DISPLAY_INFO(__display)->has_overlay)
> +#define HAS_PEAK_BW_THRESHOLD(__display)	(DISPLAY_VER(__display) >= 30)
>  #define HAS_PIPEDMC(__display)		(DISPLAY_VER(__display) >= 12)
>  #define HAS_PIXEL_NORMALIZER(__display)	(DISPLAY_VER(__display) >= 35)
>  #define HAS_PMDEMAND(__display)		(DISPLAY_VER(__display) >= 14)

-- 
Jani Nikula, Intel

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH v2 11/11] drm/i915/bw: insert a sw bw info entry to cater low data rate usecases
  2026-05-12 11:51   ` Jani Nikula
@ 2026-05-12 12:02     ` Govindapillai, Vinod
  0 siblings, 0 replies; 18+ messages in thread
From: Govindapillai, Vinod @ 2026-05-12 12:02 UTC (permalink / raw)
  To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	jani.nikula@linux.intel.com
  Cc: ville.syrjala@linux.intel.com

On Tue, 2026-05-12 at 14:51 +0300, Jani Nikula wrote:
> On Mon, 11 May 2026, Vinod Govindapillai
> <vinod.govindapillai@intel.com> wrote:
> > In xe3+, soc can lower the fabric frequency when the display
> > needs less bandwidth than the minimum GV point. This threshold
> > has been defined as 20GB/s. To enable this,
> > 
> > Add a new low bw info point with this peakbw threshold of 20GB/s
> > based on the following conditions:
> > 1. Only for xe3+ versions
> > 2. There is at least one QGV point
> > 3. Number QGV points is less than 8
> > 4. Lowest peak bw across all the QGV point is less than 20 GB/s
> > 5. And the derated bw is in the lowest peak bw qgv point is also
> >    less than this threshold of 20GB/s
> > 
> > This will make the driver to send this new threshold of 20GB/s
> > as the pmdemand request whenever the bw required for a usecase
> > is less than 20GB/s. The current pcode can handle this lower
> > peakbw value and adjust the fabric frequency accordingly.
> > 
> > Bspec: 68880
> > Assisted-by: Copilot:claude-sonnet-4.6
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_bw.c       | 54
> > +++++++++++++++++++
> >  .../drm/i915/display/intel_display_device.h   |  1 +
> >  2 files changed, 55 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 938c0294c251..747279075e29 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -54,6 +54,8 @@ struct intel_qgv_point {
> >  
> >  #define DEPROGBWPCLIMIT		60
> >  
> > +#define PEAK_BW_THRESHOLD	20000
> > +
> >  struct intel_psf_gv_point {
> >  	u8 clk; /* clock in multiples of 16.6666 MHz */
> >  };
> > @@ -589,6 +591,50 @@ static int icl_get_bw_info(struct
> > intel_display *display,
> >  	return 0;
> >  }
> >  
> > +static bool xe3_check_lower_peakbw(struct intel_display *display,
> > +				   const struct intel_qgv_info
> > *qi,
> > +				   int num_channels)
> 
> My pet peeve is naming functions with "check". Is it an assert? What
> does it do? What does the return value mean?
> 
> BR,
> Jani.
> 

hmm.. Intention is that, it should check the conditions for inserting
the low peak bw.. 

May be xe3_needs_lower_peakbw_point() ?

BR
Vinod

> > +{
> > +	unsigned int lowest_peakbw;
> > +
> > +	if (!HAS_PEAK_BW_THRESHOLD(display))
> > +		return false;
> > +
> > +	if (qi->num_points >= I915_NUM_QGV_POINTS) {
> > +		drm_warn(display->drm, "Cannot insert lowest QGV
> > point, not enough space\n");
> > +		return false;
> > +	}
> > +
> > +	lowest_peakbw = DIV_ROUND_CLOSEST(qi->points[0].dclk *
> > +					  qi->channel_width *
> > num_channels, 8);
> > +	if (lowest_peakbw <= PEAK_BW_THRESHOLD) {
> > +		drm_dbg_kms(display->drm,
> > +			    "Lowest QGV point has peak BW %u MB/s,
> > no need to insert lower point\n",
> > +			    lowest_peakbw);
> > +		return false;
> > +	}
> > +
> > +	return true;
> > +}
> > +
> > +static void xe3_insert_lowest_qgv_point(struct intel_display
> > *display,
> > +					struct intel_bw_info *bi)
> > +{
> > +	if (bi->num_qgv_points >= ARRAY_SIZE(bi->deratedbw))
> > +		return;
> > +
> > +	memmove(&bi->deratedbw[1], &bi->deratedbw[0],
> > +		bi->num_qgv_points * sizeof(*bi->deratedbw));
> > +
> > +	memmove(&bi->peakbw[1], &bi->peakbw[0],
> > +		bi->num_qgv_points * sizeof(*bi->peakbw));
> > +
> > +	/* Keep the derated bandwidth as the threshold*/
> > +	bi->deratedbw[0] = PEAK_BW_THRESHOLD;
> > +	bi->peakbw[0] = PEAK_BW_THRESHOLD;
> > +	bi->num_qgv_points++;
> > +}
> > +
> >  static int tgl_get_bw_info(struct intel_display *display,
> >  			   const struct dram_info *dram_info,
> >  			   const struct intel_sa_info *sa)
> > @@ -598,6 +644,7 @@ static int tgl_get_bw_info(struct intel_display
> > *display,
> >  	int num_channels = max_t(u8, 1, dram_info->num_channels);
> >  	int ipqdepth, ipqdepthpch = 16;
> >  	int dclk_max;
> > +	bool insert_low_peakbw;
> >  	int maxdebw, peakbw;
> >  	int clperchgroup;
> >  	int num_groups = ARRAY_SIZE(display->bw.max);
> > @@ -636,6 +683,10 @@ static int tgl_get_bw_info(struct
> > intel_display *display,
> >  	 */
> >  	clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) *
> > qi.deinterleave;
> >  
> > +	insert_low_peakbw = xe3_check_lower_peakbw(display, &qi,
> > num_channels);
> > +
> > +	display->bw.max[i].num_planes = 0;
> > +
> >  	for (i = 0; i < num_groups; i++) {
> >  		struct intel_bw_info *bi = &display->bw.max[i];
> >  		struct intel_bw_info *bi_next;
> > @@ -678,6 +729,9 @@ static int tgl_get_bw_info(struct intel_display
> > *display,
> >  							 
> > qi.channel_width, 8);
> >  		}
> >  
> > +		if (insert_low_peakbw)
> > +			xe3_insert_lowest_qgv_point(display, bi);
> > +
> >  		for (j = 0; j < qi.num_psf_points; j++) {
> >  			const struct intel_psf_gv_point *sp =
> > &qi.psf_points[j];
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> > b/drivers/gpu/drm/i915/display/intel_display_device.h
> > index 65283286771a..b31ec42c3248 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -192,6 +192,7 @@ struct intel_display_platforms {
> >  #define HAS_MBUS_JOINING(__display)	((__display)-
> > >platform.alderlake_p || DISPLAY_VER(__display) >= 14)
> >  #define HAS_MSO(__display)		(DISPLAY_VER(__display) >=
> > 12)
> >  #define HAS_OVERLAY(__display)		(DISPLAY_INFO(__display)-
> > >has_overlay)
> > +#define
> > HAS_PEAK_BW_THRESHOLD(__display)	(DISPLAY_VER(__display) >= 30)
> >  #define HAS_PIPEDMC(__display)		(DISPLAY_VER(__display) >=
> > 12)
> >  #define
> > HAS_PIXEL_NORMALIZER(__display)	(DISPLAY_VER(__display) >= 35)
> >  #define
> > HAS_PMDEMAND(__display)		(DISPLAY_VER(__display) >= 14)
> 


^ permalink raw reply	[flat|nested] 18+ messages in thread

end of thread, other threads:[~2026-05-12 12:03 UTC | newest]

Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 01/11] drm/i915/wm: clear the plane ddb_y entries on plane disable Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 02/11] drm/i915/pm_demand: introduce HAS_PMDEMAND macro Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 03/11] drm/i915/display: sagv pre/post plane calls to check pmdemand support Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 04/11] drm/i915/bw: Extract icl_init_qgv_info() Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 05/11] drm/i915/bw: sort the qgv points based on the dclk Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 06/11] drm/i915/bw: update the routine to get max dclk from qgv points Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 07/11] drm/i915/bw: update the routine to find the peakbw in MTL Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 08/11] drm/i915/bw: update the tile-y dependency based on the display version Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 09/11] drm/i915/bw: consolidate the debug info of bw/dgv/psf data Vinod Govindapillai
2026-05-12 11:49   ` Jani Nikula
2026-05-11 12:28 ` [PATCH v2 10/11] drm/i915/bw: extract update_sagv_status() Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 11/11] drm/i915/bw: insert a sw bw info entry to cater low data rate usecases Vinod Govindapillai
2026-05-12 11:51   ` Jani Nikula
2026-05-12 12:02     ` Govindapillai, Vinod
2026-05-11 16:28 ` ✓ CI.KUnit: success for drm/i915/display: reduce the pm demand peak bw based on display data rate Patchwork
2026-05-11 17:33 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-11 19:30 ` ✗ Xe.CI.FULL: failure " Patchwork

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