public inbox for intel-xe@lists.freedesktop.org
 help / color / mirror / Atom feed
From: "Mallesh, Koujalagi" <mallesh.koujalagi@intel.com>
To: Riana Tauro <riana.tauro@intel.com>
Cc: <anshuman.gupta@intel.com>, <rodrigo.vivi@intel.com>,
	<aravind.iddamsetty@linux.intel.com>, <badal.nilawar@intel.com>,
	<raag.jadav@intel.com>, <ravi.kishore.koppuravuri@intel.com>,
	<soham.purkait@intel.com>, <intel-xe@lists.freedesktop.org>
Subject: Re: [PATCH v3 01/10] drm/xe/xe_survivability: Decouple survivability info from boot survivability
Date: Tue, 14 Apr 2026 17:45:43 +0530	[thread overview]
Message-ID: <e229fb23-e020-4942-9c5f-591e20c11ac3@intel.com> (raw)
In-Reply-To: <20260402070131.1603828-13-riana.tauro@intel.com>


On 02-04-2026 12:31 pm, Riana Tauro wrote:
> On CSC runtime firmware errors that requires firmware flash through SPI,
> PCODE sets the FDO mode bit in the Capability register.
> Currently the survivability_info group is created only for boot
> survivability.
>
> Create survivability_info group even for runtime survivability to allow
> userspace to check FDO mode sysfs.
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
> v2: Fix typo (Mallesh)
> ---
>   drivers/gpu/drm/xe/xe_survivability_mode.c | 12 +++++++++++-
>   1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_survivability_mode.c b/drivers/gpu/drm/xe/xe_survivability_mode.c
> index db64cac39c94..ad51a58831b0 100644
> --- a/drivers/gpu/drm/xe/xe_survivability_mode.c
> +++ b/drivers/gpu/drm/xe/xe_survivability_mode.c
> @@ -98,6 +98,15 @@
>    *	# cat /sys/bus/pci/devices/<device>/survivability_mode
>    *	  Runtime
>    *
> + * On some CSC firmware errors, PCODE sets FDO mode and the only recovery possible is through
> + * firmware flash using SPI driver. Userspace can check if FDO mode is set by checking the below
> + * sysfs entry.
> + *
> + * .. code-block:: shell
> + *
> + *	# cat /sys/bus/pci/devices/<device>/survivability_info/fdo_mode
> + *       enabled

Nit: The indentation of enabled here uses space, however boot and 
Runtime use tab+spaces

Please keep consistency.

With that addressed

Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>

> + *
>    * When such errors occur, userspace is notified with the drm device wedged uevent and runtime
>    * survivability mode. User can then initiate a firmware flash using userspace tools like fwupd
>    * to restore device to normal operation.
> @@ -296,7 +305,8 @@ static int create_survivability_sysfs(struct pci_dev *pdev)
>   	if (ret)
>   		return ret;
>   
> -	if (check_boot_failure(xe)) {
> +	/* Survivability info is not required if enabled via configfs */
> +	if (!xe_configfs_get_survivability_mode(pdev)) {
>   		ret = devm_device_add_group(dev, &survivability_info_group);
>   		if (ret)
>   			return ret;

  reply	other threads:[~2026-04-14 12:16 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-02  7:01 [PATCH v3 00/10] Introduce Xe Uncorrectable Error Handling Riana Tauro
2026-04-02  7:01 ` [PATCH v3 01/10] drm/xe/xe_survivability: Decouple survivability info from boot survivability Riana Tauro
2026-04-14 12:15   ` Mallesh, Koujalagi [this message]
2026-04-02  7:01 ` [PATCH v3 02/10] drm/xe/xe_pci_error: Implement PCI error recovery callbacks Riana Tauro
2026-04-07  4:50   ` Matthew Brost
2026-04-13  9:00     ` Tauro, Riana
2026-04-14 13:29       ` Mallesh, Koujalagi
2026-04-16  4:48         ` Tauro, Riana
2026-04-16  5:33           ` Mallesh, Koujalagi
2026-04-02  7:01 ` [PATCH v3 03/10] drm/xe/xe_pci_error: Group all devres to release them on PCIe slot reset Riana Tauro
2026-04-16 13:07   ` Mallesh, Koujalagi
2026-04-02  7:01 ` [PATCH v3 04/10] drm/xe: Skip device access during PCI error recovery Riana Tauro
2026-04-02  7:01 ` [PATCH v3 05/10] drm/xe/xe_ras: Initialize Uncorrectable AER Registers Riana Tauro
2026-04-07  5:50   ` Raag Jadav
2026-04-02  7:01 ` [PATCH v3 06/10] drm/xe/xe_ras: Add structures and commands for Uncorrectable Core Compute Errors Riana Tauro
2026-04-07  5:59   ` Raag Jadav
2026-04-02  7:01 ` [PATCH v3 07/10] drm/xe/xe_ras: Add support for Uncorrectable Core-Compute errors Riana Tauro
2026-04-08 11:15   ` Raag Jadav
2026-04-13  8:17     ` Tauro, Riana
2026-04-02  7:01 ` [PATCH v3 08/10] drm/xe/xe_ras: Add structures for SoC Internal errors Riana Tauro
2026-04-08 11:18   ` Raag Jadav
2026-04-13  7:55     ` Tauro, Riana
2026-04-02  7:01 ` [PATCH v3 09/10] drm/xe/xe_ras: Handle Uncorrectable " Riana Tauro
2026-04-02  7:01 ` [PATCH v3 10/10] drm/xe/xe_pci_error: Process errors in mmio_enabled Riana Tauro
2026-04-02  8:01 ` ✗ CI.checkpatch: warning for Introduce Xe Uncorrectable Error Handling (rev3) Patchwork
2026-04-02  8:02 ` ✓ CI.KUnit: success " Patchwork
2026-04-02  8:50 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-02 15:08 ` ✓ Xe.CI.FULL: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=e229fb23-e020-4942-9c5f-591e20c11ac3@intel.com \
    --to=mallesh.koujalagi@intel.com \
    --cc=anshuman.gupta@intel.com \
    --cc=aravind.iddamsetty@linux.intel.com \
    --cc=badal.nilawar@intel.com \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=raag.jadav@intel.com \
    --cc=ravi.kishore.koppuravuri@intel.com \
    --cc=riana.tauro@intel.com \
    --cc=rodrigo.vivi@intel.com \
    --cc=soham.purkait@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox