Re: [PATCH v4 06/12] drm/xe/cper: Prepare Intel CPER error info records

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] xe/cper: missing __packed attributes on CPER structs causes ABI breakage and unaligned access
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commit 48cc4e07bb3144fabbe0d059b7aa4e8d590267c1
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/cper: Prepare Intel CPER error info records

This commit prepares xe_cper_sec_intel_error_info records from RAS info
queue data. Depending on the error class type, one or more error info
records may be generated and embedded in the CPER record.

> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> index 1000c78b41e97..7acb503efd118 100644
> --- a/drivers/gpu/drm/xe/xe_cper.c
> +++ b/drivers/gpu/drm/xe/xe_cper.c
[ ... ]
> +static struct xe_cper_sec_intel_error_info *
> +build_einfo(const struct xe_ras_error_log *logs, u32 num_logs,
> +	    const struct xe_ras_error_class *ec, u32 error_count)
> +{
> +	u32 queue_len = num_logs * XE_CPER_RAS_LOG_ENTRY_SIZE;
> +	struct xe_cper_sec_intel_error_info *einfo;
> +	struct xe_intel_priv_event_entry *entry;
> +	u32 i;
> +
> +	einfo = kzalloc_flex(*einfo, event_queue, queue_len);
> +	if (!einfo)
> +		return NULL;
> +
> +	einfo->error_count        = error_count;
> +	einfo->event_queue_length = queue_len;
> +	einfo->event_queue_count  = num_logs;
> +	fill_cper_error_class(&einfo->error_class, ec);
> +
> +	entry = (struct xe_intel_priv_event_entry *)einfo->event_queue;
> +	for (i = 0; i < num_logs; i++) {
> +		entry->entry_length = sizeof_field(struct xe_ras_error_log, error_details);
> +		entry->timestamp    = logs[i].timestamp;

[Severity: High]
Can this assignment cause an alignment fault? 

Because xe_cper_sec_intel_error_info is evaluated as 28 bytes in size,
event_queue starts at offset 28. In xe_intel_priv_event_entry, the
timestamp is at offset 8. The resulting address for the timestamp field is
therefore 36 bytes from the kzalloc base, which is not 8-byte aligned.

Writing a 64-bit value to a 4-byte-aligned address can cause a kernel panic
on architectures that strictly enforce 64-bit alignment.

> +		memcpy(entry->metadata, logs[i].error_details, sizeof(logs[i].error_details));
> +		entry = (void *)entry + XE_CPER_RAS_LOG_ENTRY_SIZE;
> +	}
> +
> +	return einfo;
> +}
[ ... ]
> diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
> index 7612518c9d47b..627c7117f23eb 100644
> --- a/drivers/gpu/drm/xe/xe_cper_types.h
> +++ b/drivers/gpu/drm/xe/xe_cper_types.h
[ ... ]
> +struct xe_cper_sec_intel_error_info {
> +	/** @error_class: Error classification */
> +	struct xe_cper_error_class error_class;
> +	/** @error_count: Total number of errors recorded */
> +	u32 error_count;
> +	/** @event_queue_length: Total byte size of the @event_queue array */
> +	u32 event_queue_length;
> +	/** @event_queue_count: Number of entries in @event_queue */
> +	u32 event_queue_count;
> +	/** @event_queue: Packed array of &xe_intel_priv_event_entry records */
> +	u8 event_queue[];
> +};
> +
> +/**
> + * struct xe_intel_priv_event_entry - Single error event in the event queue
> + *
> + * Each entry is variable-length; @entry_length gives the byte size of
> + * @metadata only (not including @entry_length or @timestamp).
> + */
> +struct xe_intel_priv_event_entry {
> +	/** @entry_length: Byte length of the @metadata payload */
> +	u32 entry_length;
> +	/** @timestamp: Timestamp of this event, in firmware ticks */
> +	u64 timestamp;
> +	/** @metadata: Event-specific payload bytes */
> +	u8  metadata[];
> +};

[Severity: High]
Are these structures missing the __packed attribute?

Without it, the compiler injects a 4-byte hole before the timestamp field,
which also enforces 8-byte alignment for the struct. This implicit padding
corrupts the intended binary CPER layout, potentially leading to ABI
breakage when the records are parsed by external tools. It also causes the
memory alignment issues mentioned above.

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Sashiko AI review · https://sashiko.dev/#/patchset/20261009104602.1075405-14-badal.nilawar@intel.com?part=6