[PATCH 0/9] drm/i915/de: Work towards uncore elimination

[PATCH 0/9] drm/i915/de: Work towards uncore elimination

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move the mmio locking and unclaimed register detection into the
display code. For now both are still i915 only to keep the
number functional changes in check.

Eventually we want to hook up the unclaimed register detection
for xe as well, but might have to think of a way to do it
without the lock to reduce the overhead a bit. Eliminating
the lock would help i915 on modern platforms as well.

Ville Syrjälä (9):
  drm/i915/de: Introduce dislay->mmio and intel_de_init()
  drm/i915/de: Convert intel_de_{read,write}() into vfuncs
  drm/i915/de: Introduce mmio read/write templates
  drm/i915/de: Eliminate runtime overhead from DMC wakelock on pre-LNL
    platforms
  drm/i915/de: Introduce display->mmio.lock
  drm/i915/uncore: Don't meddle with mmio debug upon user forcewake
  drm/i915/de: Move unclaimed mmio detection into display code
  drm/i915/de: Stop using intel_uncore_{read,write}()
  drm/xe: Nuke the intel_uncore_{read,write}() wrappers

 drivers/gpu/drm/i915/display/i9xx_wm.c        |   9 +-
 drivers/gpu/drm/i915/display/intel_de.c       | 331 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_de.h       |  29 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   3 +-
 .../gpu/drm/i915/display/intel_display_core.h |  23 ++
 .../drm/i915/display/intel_display_device.c   |   7 +
 .../drm/i915/display/intel_display_driver.c   |  15 +
 .../drm/i915/display/intel_display_driver.h   |   3 +
 .../drm/i915/display/intel_display_params.c   |   4 +
 .../drm/i915/display/intel_display_params.h   |   1 +
 .../gpu/drm/i915/display/intel_display_regs.h |   8 +
 drivers/gpu/drm/i915/display/intel_vblank.c   |  16 +-
 drivers/gpu/drm/i915/i915_driver.c            |  12 +-
 drivers/gpu/drm/i915/i915_drv.h               |   1 -
 drivers/gpu/drm/i915/i915_params.c            |   4 -
 drivers/gpu/drm/i915/i915_params.h            |   1 -
 drivers/gpu/drm/i915/i915_reg.h               |   7 -
 drivers/gpu/drm/i915/intel_uncore.c           | 239 +------------
 drivers/gpu/drm/i915/intel_uncore.h           |  26 --
 .../drm/xe/compat-i915-headers/intel_uncore.h |  16 -
 20 files changed, 423 insertions(+), 332 deletions(-)

-- 
2.56.0

[PATCH 1/9] drm/i915/de: Introduce dislay->mmio and intel_de_init()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add a place for upcoming mmio stuff in the form of
a display->mmio struct and intel_de_init() to fill it up.
For now we'll just stick the uncore pointer there, but
it'll get replaced by something else eventually.

I originally wanted to call intel_de_init() just after
intel_display_device_probe(), but i915 calls that before
the uncore/mmio setup has been done. Right now that wouldn't
matter since the &i915->uncore is valid nonetheless. But
eventually I think we'll just want to get the 'void __iomem *'
from the core driver and that of course need to be mapped
before intel_de_init() is called. So put the init call into
__intel_display_device_info_runtime_init() which should be the
first place where we call any intel_de_*() stuff

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_de.c             | 5 +++++
 drivers/gpu/drm/i915/display/intel_de.h             | 4 +++-
 drivers/gpu/drm/i915/display/intel_display_core.h   | 5 +++++
 drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++++++
 4 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
index a7417905192d..6b3d06147e58 100644
--- a/drivers/gpu/drm/i915/display/intel_de.c
+++ b/drivers/gpu/drm/i915/display/intel_de.c
@@ -162,3 +162,8 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
 
 	return intel_uncore_read16(__to_uncore(display), reg);
 }
+
+void intel_de_init(struct intel_display *display)
+{
+	display->mmio.uncore = to_intel_uncore(display->drm);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index d0a239a36980..f1135ee5071b 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -14,9 +14,11 @@
 
 static inline struct intel_uncore *__to_uncore(struct intel_display *display)
 {
-	return to_intel_uncore(display->drm);
+	return display->mmio.uncore;
 }
 
+void intel_de_init(struct intel_display *display);
+
 u8 intel_de_read8(struct intel_display *display, intel_reg_t reg);
 void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val);
 u16 intel_de_read16(struct intel_display *display, intel_reg_t reg);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index c80b4a2f74f9..35409f9abb2f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -51,6 +51,7 @@ struct intel_hotplug_irq_funcs;
 struct intel_initial_plane_config;
 struct intel_opregion;
 struct intel_overlay;
+struct intel_uncore;
 struct task_struct;
 
 /* Amount of SAGV/QGV points, BSpec precisely defines this */
@@ -530,6 +531,10 @@ struct intel_display {
 		const struct intel_modeset_funcs *funcs;
 	} modeset;
 
+	struct {
+		struct intel_uncore *uncore;
+	} mmio;
+
 	struct {
 		/* protected by wm.wm_mutex */
 		u16 linetime[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index c74256359c25..f1bd1252a960 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1798,6 +1798,13 @@ static void __intel_display_device_info_runtime_init(struct intel_display *displ
 	struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(display);
 	enum pipe pipe;
 
+	/*
+	 * TODO end of intel_display_device_probe() would be a more
+	 * logical place, but at the moment i915 calls that super
+	 * early when things aren't fully set up yet.
+	 */
+	intel_de_init(display);
+
 	BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES);
 	BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->cpu_transcoder_mask) < I915_MAX_TRANSCODERS);
 	BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS);
-- 
2.56.0

Re: [PATCH 1/9] drm/i915/de: Introduce dislay->mmio and intel_de_init()

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915/de: NULL display->mmio.uncore when intel_de_init() is skipped
--

commit 0c47f694d22974ac99844e39b462f72389dd014b
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>

drm/i915/de: Introduce dislay->mmio and intel_de_init()

This commit adds a display->mmio struct and intel_de_init() to initialize
display->mmio.uncore, and updates __to_uncore() to return display->mmio.uncore
instead of calling to_intel_uncore(display->drm).

[ ... ]

> diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
> index d0a239a369807..f1135ee5071b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -14,9 +14,11 @@
>  
>  static inline struct intel_uncore *__to_uncore(struct intel_display *display)
>  {
> -	return to_intel_uncore(display->drm);
> +	return display->mmio.uncore;
>  }

[ ... ]

> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index c74256359c253..f1bd1252a9602 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -1798,6 +1798,13 @@ static void __intel_display_device_info_runtime_init(struct intel_display *displ
>  	struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(display);
>  	enum pipe pipe;
>  
> +	/*
> +	 * TODO end of intel_display_device_probe() would be a more
> +	 * logical place, but at the moment i915 calls that super
> +	 * early when things aren't fully set up yet.
> +	 */
> +	intel_de_init(display);

[Severity: High]
Can this leave display->mmio.uncore NULL and cause a NULL pointer dereference
when HAS_DISPLAY(display) is already false before runtime init?

In drivers/gpu/drm/i915/display/intel_display_device.c,
intel_display_device_info_runtime_init() only calls
__intel_display_device_info_runtime_init() when HAS_DISPLAY(display) is true:

void intel_display_device_info_runtime_init(struct intel_display *display)
{
	if (HAS_DISPLAY(display))
		__intel_display_device_info_runtime_init(display);

On devices where intel_display_device_probe() sets DISPLAY_INFO() to
no_display—such as Ivybridge Quanta server SKUs (INTEL_IVB_Q_IDS via
has_no_display()), PCI IDs without an entry in intel_display_ids like Arctic
Sound-M (INTEL_ATS_M_IDS where find_platform_desc() returns NULL), or GMD_ID
platforms (INTEL_MTL_IDS / INTEL_ARL_IDS) where probe_gmdid_display() reads 0
from GMD_ID_DISPLAY—HAS_DISPLAY(display) is false and
__intel_display_device_info_runtime_init() is skipped.

Because __to_uncore(display) in drivers/gpu/drm/i915/display/intel_de.h now
returns display->mmio.uncore instead of computing
to_intel_uncore(display->drm), any subsequent unconditional intel_de_*() call
will pass a NULL struct intel_uncore pointer to intel_uncore_read*() or
intel_uncore_write*():

1. On INTEL_IVB_Q_IDS, ilk_irq_handler() in drivers/gpu/drm/i915/i915_irq.c
   unconditionally calls ilk_display_irq_master_disable() and
   ilk_display_irq_master_enable() in
   drivers/gpu/drm/i915/display/intel_display_irq.c on every interrupt, which
   call intel_de_read_fw(display, DEIER) and intel_de_write_fw(display, DEIER,
   ...).

2. On INTEL_ATS_M_IDS and headless GMD_ID platforms, gen11_irq_handler() and
   dg1_irq_handler() unconditionally call gen11_gu_misc_irq_ack() in
   drivers/gpu/drm/i915/display/intel_display_irq.c when GEN11_GU_MISC_IRQ is
   set, which calls intel_de_read_fw(display, GEN11_GU_MISC_IIR) and
   intel_de_write_fw(display, GEN11_GU_MISC_IIR, iir).

3. During system resume, i915_drm_resume() in
   drivers/gpu/drm/i915/i915_driver.c unconditionally calls
   intel_gmbus_reset(display) in drivers/gpu/drm/i915/display/intel_gmbus.c,
   which calls intel_de_write_fw(display, GMBUS0(display), 0) and
   intel_de_write_fw(display, GMBUS4(display), 0).

Should intel_de_init(display) be called unconditionally at the start of
intel_display_device_info_runtime_init() before the HAS_DISPLAY(display)
check?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261104221842.18799-1-ville.syrjala@linux.intel.com?part=1

Re: [PATCH 1/9] drm/i915/de: Introduce dislay->mmio and intel_de_init()

[Jani Nikula]

On Wed, 04 Nov 2026, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] drm/i915/de: NULL display->mmio.uncore when intel_de_init() is skipped
> --
>
> commit 0c47f694d22974ac99844e39b462f72389dd014b
> Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> drm/i915/de: Introduce dislay->mmio and intel_de_init()
>
> This commit adds a display->mmio struct and intel_de_init() to initialize
> display->mmio.uncore, and updates __to_uncore() to return display->mmio.uncore
> instead of calling to_intel_uncore(display->drm).
>
> [ ... ]
>
>> diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
>> index d0a239a369807..f1135ee5071b4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_de.h
>> +++ b/drivers/gpu/drm/i915/display/intel_de.h
>> @@ -14,9 +14,11 @@
>>  
>>  static inline struct intel_uncore *__to_uncore(struct intel_display *display)
>>  {
>> -	return to_intel_uncore(display->drm);
>> +	return display->mmio.uncore;
>>  }
>
> [ ... ]
>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
>> index c74256359c253..f1bd1252a9602 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
>> @@ -1798,6 +1798,13 @@ static void __intel_display_device_info_runtime_init(struct intel_display *displ
>>  	struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(display);
>>  	enum pipe pipe;
>>  
>> +	/*
>> +	 * TODO end of intel_display_device_probe() would be a more
>> +	 * logical place, but at the moment i915 calls that super
>> +	 * early when things aren't fully set up yet.
>> +	 */
>> +	intel_de_init(display);
>
> [Severity: High]
> Can this leave display->mmio.uncore NULL and cause a NULL pointer dereference
> when HAS_DISPLAY(display) is already false before runtime init?
>
> In drivers/gpu/drm/i915/display/intel_display_device.c,
> intel_display_device_info_runtime_init() only calls
> __intel_display_device_info_runtime_init() when HAS_DISPLAY(display) is true:
>
> void intel_display_device_info_runtime_init(struct intel_display *display)
> {
> 	if (HAS_DISPLAY(display))
> 		__intel_display_device_info_runtime_init(display);
>
> On devices where intel_display_device_probe() sets DISPLAY_INFO() to
> no_display—such as Ivybridge Quanta server SKUs (INTEL_IVB_Q_IDS via
> has_no_display()), PCI IDs without an entry in intel_display_ids like Arctic
> Sound-M (INTEL_ATS_M_IDS where find_platform_desc() returns NULL), or GMD_ID
> platforms (INTEL_MTL_IDS / INTEL_ARL_IDS) where probe_gmdid_display() reads 0
> from GMD_ID_DISPLAY—HAS_DISPLAY(display) is false and
> __intel_display_device_info_runtime_init() is skipped.
>
> Because __to_uncore(display) in drivers/gpu/drm/i915/display/intel_de.h now
> returns display->mmio.uncore instead of computing
> to_intel_uncore(display->drm), any subsequent unconditional intel_de_*() call
> will pass a NULL struct intel_uncore pointer to intel_uncore_read*() or
> intel_uncore_write*():
>
> 1. On INTEL_IVB_Q_IDS, ilk_irq_handler() in drivers/gpu/drm/i915/i915_irq.c
>    unconditionally calls ilk_display_irq_master_disable() and
>    ilk_display_irq_master_enable() in
>    drivers/gpu/drm/i915/display/intel_display_irq.c on every interrupt, which
>    call intel_de_read_fw(display, DEIER) and intel_de_write_fw(display, DEIER,
>    ...).
>
> 2. On INTEL_ATS_M_IDS and headless GMD_ID platforms, gen11_irq_handler() and
>    dg1_irq_handler() unconditionally call gen11_gu_misc_irq_ack() in
>    drivers/gpu/drm/i915/display/intel_display_irq.c when GEN11_GU_MISC_IRQ is
>    set, which calls intel_de_read_fw(display, GEN11_GU_MISC_IIR) and
>    intel_de_write_fw(display, GEN11_GU_MISC_IIR, iir).
>
> 3. During system resume, i915_drm_resume() in
>    drivers/gpu/drm/i915/i915_driver.c unconditionally calls
>    intel_gmbus_reset(display) in drivers/gpu/drm/i915/display/intel_gmbus.c,
>    which calls intel_de_write_fw(display, GMBUS0(display), 0) and
>    intel_de_write_fw(display, GMBUS4(display), 0).
>
> Should intel_de_init(display) be called unconditionally at the start of
> intel_display_device_info_runtime_init() before the HAS_DISPLAY(display)
> check?

Seems annoying but valid, at least until we figure something else out.

BR,
Jani.



-- 
Jani Nikula, Intel

Re: [PATCH 1/9] drm/i915/de: Introduce dislay->mmio and intel_de_init()

[Ville Syrjälä]

On Wed, Nov 04, 2026 at 10:31:47PM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] drm/i915/de: NULL display->mmio.uncore when intel_de_init() is skipped
> --
> 
> commit 0c47f694d22974ac99844e39b462f72389dd014b
> Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> drm/i915/de: Introduce dislay->mmio and intel_de_init()
> 
> This commit adds a display->mmio struct and intel_de_init() to initialize
> display->mmio.uncore, and updates __to_uncore() to return display->mmio.uncore
> instead of calling to_intel_uncore(display->drm).
> 
> [ ... ]
> 
> > diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
> > index d0a239a369807..f1135ee5071b4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_de.h
> > +++ b/drivers/gpu/drm/i915/display/intel_de.h
> > @@ -14,9 +14,11 @@
> >  
> >  static inline struct intel_uncore *__to_uncore(struct intel_display *display)
> >  {
> > -	return to_intel_uncore(display->drm);
> > +	return display->mmio.uncore;
> >  }
> 
> [ ... ]
> 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> > index c74256359c253..f1bd1252a9602 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> > @@ -1798,6 +1798,13 @@ static void __intel_display_device_info_runtime_init(struct intel_display *displ
> >  	struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(display);
> >  	enum pipe pipe;
> >  
> > +	/*
> > +	 * TODO end of intel_display_device_probe() would be a more
> > +	 * logical place, but at the moment i915 calls that super
> > +	 * early when things aren't fully set up yet.
> > +	 */
> > +	intel_de_init(display);
> 
> [Severity: High]
> Can this leave display->mmio.uncore NULL and cause a NULL pointer dereference
> when HAS_DISPLAY(display) is already false before runtime init?
> 
> In drivers/gpu/drm/i915/display/intel_display_device.c,
> intel_display_device_info_runtime_init() only calls
> __intel_display_device_info_runtime_init() when HAS_DISPLAY(display) is true:
> 
> void intel_display_device_info_runtime_init(struct intel_display *display)
> {
> 	if (HAS_DISPLAY(display))
> 		__intel_display_device_info_runtime_init(display);
> 
> On devices where intel_display_device_probe() sets DISPLAY_INFO() to
> no_display—such as Ivybridge Quanta server SKUs (INTEL_IVB_Q_IDS via
> has_no_display()), PCI IDs without an entry in intel_display_ids like Arctic
> Sound-M (INTEL_ATS_M_IDS where find_platform_desc() returns NULL), or GMD_ID
> platforms (INTEL_MTL_IDS / INTEL_ARL_IDS) where probe_gmdid_display() reads 0
> from GMD_ID_DISPLAY—HAS_DISPLAY(display) is false and
> __intel_display_device_info_runtime_init() is skipped.
> 
> Because __to_uncore(display) in drivers/gpu/drm/i915/display/intel_de.h now
> returns display->mmio.uncore instead of computing
> to_intel_uncore(display->drm), any subsequent unconditional intel_de_*() call
> will pass a NULL struct intel_uncore pointer to intel_uncore_read*() or
> intel_uncore_write*():
> 
> 1. On INTEL_IVB_Q_IDS, ilk_irq_handler() in drivers/gpu/drm/i915/i915_irq.c
>    unconditionally calls ilk_display_irq_master_disable() and
>    ilk_display_irq_master_enable() in
>    drivers/gpu/drm/i915/display/intel_display_irq.c on every interrupt, which
>    call intel_de_read_fw(display, DEIER) and intel_de_write_fw(display, DEIER,
>    ...).

This one's a bit funny because it uses the 'no_display' device
info, and that one doesn't even populate ip.ver. So once all
the mmio stuff is fully implemented inside the display code
this will fall through the platform if-ladder all the way to
the i9xx mmio funcs. But that should be fine since it only uses
the _fw() stuff anyway and there won't be any difference for
those. Only LNL will need special _fw() stuff due to the
nasty read vs. write ordering workaround.

> 
> 2. On INTEL_ATS_M_IDS and headless GMD_ID platforms, gen11_irq_handler() and
>    dg1_irq_handler() unconditionally call gen11_gu_misc_irq_ack() in
>    drivers/gpu/drm/i915/display/intel_display_irq.c when GEN11_GU_MISC_IRQ is
>    set, which calls intel_de_read_fw(display, GEN11_GU_MISC_IIR) and
>    intel_de_write_fw(display, GEN11_GU_MISC_IIR, iir).

I think I'll just move the irq_ack() part to i915_irq.c where it belongs,
and leave the handler part in the display. The handler should be fine
to call without display since it just calls some opregion thing that
does nothing if opregion wasn't initialized.

Although I suppose we shouldn't even unmask the GSE interrupt 
if the display isn't there. Shouldn't be hard.

> 
> 3. During system resume, i915_drm_resume() in
>    drivers/gpu/drm/i915/i915_driver.c unconditionally calls
>    intel_gmbus_reset(display) in drivers/gpu/drm/i915/display/intel_gmbus.c,
>    which calls intel_de_write_fw(display, GMBUS0(display), 0) and
>    intel_de_write_fw(display, GMBUS4(display), 0).

Yeah, I remember seeing that before and thinking that it's very
much misplaced. I'll look into moving that into the display code.

> 
> Should intel_de_init(display) be called unconditionally at the start of
> intel_display_device_info_runtime_init() before the HAS_DISPLAY(display)
> check?
> 
> -- 
> Sashiko AI review · https://sashiko.dev/#/patchset/20261104221842.18799-1-ville.syrjala@linux.intel.com?part=1

-- 
Ville Syrjälä
Intel

Re: [PATCH 1/9] drm/i915/de: Introduce dislay->mmio and intel_de_init()

[Michał Grzelak]

title: s/dislay/display/

On Thu, Nov 05, 2026 at 12:18:34AM GMT, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add a place for upcoming mmio stuff in the form of
> a display->mmio struct and intel_de_init() to fill it up.
> For now we'll just stick the uncore pointer there, but
> it'll get replaced by something else eventually.
> 
> I originally wanted to call intel_de_init() just after
> intel_display_device_probe(), but i915 calls that before
> the uncore/mmio setup has been done. Right now that wouldn't
> matter since the &i915->uncore is valid nonetheless. But
> eventually I think we'll just want to get the 'void __iomem *'
> from the core driver and that of course need to be mapped
> before intel_de_init() is called. So put the init call into
> __intel_display_device_info_runtime_init() which should be the
> first place where we call any intel_de_*() stuff
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Michał Grzelak <michal.grzelak@linux.intel.com>

BR,
Michał

> ---
>  drivers/gpu/drm/i915/display/intel_de.c             | 5 +++++
>  drivers/gpu/drm/i915/display/intel_de.h             | 4 +++-
>  drivers/gpu/drm/i915/display/intel_display_core.h   | 5 +++++
>  drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++++++
>  4 files changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> index a7417905192d..6b3d06147e58 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.c
> +++ b/drivers/gpu/drm/i915/display/intel_de.c
> @@ -162,3 +162,8 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
>  
>  	return intel_uncore_read16(__to_uncore(display), reg);
>  }
> +
> +void intel_de_init(struct intel_display *display)
> +{
> +	display->mmio.uncore = to_intel_uncore(display->drm);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
> index d0a239a36980..f1135ee5071b 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -14,9 +14,11 @@
>  
>  static inline struct intel_uncore *__to_uncore(struct intel_display *display)
>  {
> -	return to_intel_uncore(display->drm);
> +	return display->mmio.uncore;
>  }
>  
> +void intel_de_init(struct intel_display *display);
> +
>  u8 intel_de_read8(struct intel_display *display, intel_reg_t reg);
>  void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val);
>  u16 intel_de_read16(struct intel_display *display, intel_reg_t reg);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index c80b4a2f74f9..35409f9abb2f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -51,6 +51,7 @@ struct intel_hotplug_irq_funcs;
>  struct intel_initial_plane_config;
>  struct intel_opregion;
>  struct intel_overlay;
> +struct intel_uncore;
>  struct task_struct;
>  
>  /* Amount of SAGV/QGV points, BSpec precisely defines this */
> @@ -530,6 +531,10 @@ struct intel_display {
>  		const struct intel_modeset_funcs *funcs;
>  	} modeset;
>  
> +	struct {
> +		struct intel_uncore *uncore;
> +	} mmio;
> +
>  	struct {
>  		/* protected by wm.wm_mutex */
>  		u16 linetime[I915_MAX_PIPES];
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index c74256359c25..f1bd1252a960 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -1798,6 +1798,13 @@ static void __intel_display_device_info_runtime_init(struct intel_display *displ
>  	struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(display);
>  	enum pipe pipe;
>  
> +	/*
> +	 * TODO end of intel_display_device_probe() would be a more
> +	 * logical place, but at the moment i915 calls that super
> +	 * early when things aren't fully set up yet.
> +	 */
> +	intel_de_init(display);
> +
>  	BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES);
>  	BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->cpu_transcoder_mask) < I915_MAX_TRANSCODERS);
>  	BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS);
> -- 
> 2.56.0
> 

[PATCH 2/9] drm/i915/de: Convert intel_de_{read,write}() into vfuncs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Different platforms will need to do different things in
their mmio accessors. The plan is to trade the overhead
of runtime platform checks into no runtime checks and
the cost of a vfunc call. This seems to provide slightly
better overall performance.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_de.c         | 17 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_de.h         |  9 +++++++--
 .../gpu/drm/i915/display/intel_display_core.h   |  2 ++
 3 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
index 6b3d06147e58..4f423a684ec2 100644
--- a/drivers/gpu/drm/i915/display/intel_de.c
+++ b/drivers/gpu/drm/i915/display/intel_de.c
@@ -163,7 +163,24 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
 	return intel_uncore_read16(__to_uncore(display), reg);
 }
 
+static u32 i9xx_mmio_read(struct intel_display *display, intel_reg_t reg)
+{
+	return intel_uncore_read(__to_uncore(display), reg);
+}
+
+static void i9xx_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
+{
+	intel_uncore_write(__to_uncore(display), reg, val);
+}
+
+static const struct intel_mmio_funcs i9xx_mmio_funcs = {
+	.read = i9xx_mmio_read,
+	.write = i9xx_mmio_write,
+};
+
 void intel_de_init(struct intel_display *display)
 {
 	display->mmio.uncore = to_intel_uncore(display->drm);
+
+	display->mmio.funcs = &i9xx_mmio_funcs;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index f1135ee5071b..63aef17e6ed3 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -12,6 +12,11 @@
 #include "intel_uncore.h"
 #include "intel_uncore_trace.h"
 
+struct intel_mmio_funcs {
+	u32 (*read)(struct intel_display *display, intel_reg_t reg);
+	void (*write)(struct intel_display *display, intel_reg_t reg, u32 val);
+};
+
 static inline struct intel_uncore *__to_uncore(struct intel_display *display)
 {
 	return display->mmio.uncore;
@@ -30,7 +35,7 @@ intel_de_read(struct intel_display *display, intel_reg_t reg)
 
 	intel_dmc_wl_get(display, reg);
 
-	val = intel_uncore_read(__to_uncore(display), reg);
+	val = display->mmio.funcs->read(display, reg);
 
 	intel_dmc_wl_put(display, reg);
 
@@ -60,7 +65,7 @@ intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val)
 {
 	intel_dmc_wl_get(display, reg);
 
-	intel_uncore_write(__to_uncore(display), reg, val);
+	display->mmio.funcs->write(display, reg, val);
 
 	intel_dmc_wl_put(display, reg);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 35409f9abb2f..3a48119f7890 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -49,6 +49,7 @@ struct intel_fbdev;
 struct intel_fdi_funcs;
 struct intel_hotplug_irq_funcs;
 struct intel_initial_plane_config;
+struct intel_mmio_funcs;
 struct intel_opregion;
 struct intel_overlay;
 struct intel_uncore;
@@ -533,6 +534,7 @@ struct intel_display {
 
 	struct {
 		struct intel_uncore *uncore;
+		const struct intel_mmio_funcs *funcs;
 	} mmio;
 
 	struct {
-- 
2.56.0

Re: [PATCH 2/9] drm/i915/de: Convert intel_de_{read,write}() into vfuncs

[Jani Nikula]

On Thu, 05 Nov 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Different platforms will need to do different things in
> their mmio accessors. The plan is to trade the overhead
> of runtime platform checks into no runtime checks and
> the cost of a vfunc call. This seems to provide slightly
> better overall performance.

What's the plan for the 8- and 16-bit counterparts?

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_de.c         | 17 +++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_de.h         |  9 +++++++--
>  .../gpu/drm/i915/display/intel_display_core.h   |  2 ++
>  3 files changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> index 6b3d06147e58..4f423a684ec2 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.c
> +++ b/drivers/gpu/drm/i915/display/intel_de.c
> @@ -163,7 +163,24 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
>  	return intel_uncore_read16(__to_uncore(display), reg);
>  }
>  
> +static u32 i9xx_mmio_read(struct intel_display *display, intel_reg_t reg)
> +{
> +	return intel_uncore_read(__to_uncore(display), reg);
> +}
> +
> +static void i9xx_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
> +{
> +	intel_uncore_write(__to_uncore(display), reg, val);
> +}
> +
> +static const struct intel_mmio_funcs i9xx_mmio_funcs = {
> +	.read = i9xx_mmio_read,
> +	.write = i9xx_mmio_write,
> +};
> +
>  void intel_de_init(struct intel_display *display)
>  {
>  	display->mmio.uncore = to_intel_uncore(display->drm);
> +
> +	display->mmio.funcs = &i9xx_mmio_funcs;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
> index f1135ee5071b..63aef17e6ed3 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -12,6 +12,11 @@
>  #include "intel_uncore.h"
>  #include "intel_uncore_trace.h"
>  
> +struct intel_mmio_funcs {
> +	u32 (*read)(struct intel_display *display, intel_reg_t reg);
> +	void (*write)(struct intel_display *display, intel_reg_t reg, u32 val);
> +};
> +

Wondering if this should be in intel_display_core.h as all the other
ones are. But let's see how it pans out.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>  static inline struct intel_uncore *__to_uncore(struct intel_display *display)
>  {
>  	return display->mmio.uncore;
> @@ -30,7 +35,7 @@ intel_de_read(struct intel_display *display, intel_reg_t reg)
>  
>  	intel_dmc_wl_get(display, reg);
>  
> -	val = intel_uncore_read(__to_uncore(display), reg);
> +	val = display->mmio.funcs->read(display, reg);
>  
>  	intel_dmc_wl_put(display, reg);
>  
> @@ -60,7 +65,7 @@ intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val)
>  {
>  	intel_dmc_wl_get(display, reg);
>  
> -	intel_uncore_write(__to_uncore(display), reg, val);
> +	display->mmio.funcs->write(display, reg, val);
>  
>  	intel_dmc_wl_put(display, reg);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 35409f9abb2f..3a48119f7890 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -49,6 +49,7 @@ struct intel_fbdev;
>  struct intel_fdi_funcs;
>  struct intel_hotplug_irq_funcs;
>  struct intel_initial_plane_config;
> +struct intel_mmio_funcs;
>  struct intel_opregion;
>  struct intel_overlay;
>  struct intel_uncore;
> @@ -533,6 +534,7 @@ struct intel_display {
>  
>  	struct {
>  		struct intel_uncore *uncore;
> +		const struct intel_mmio_funcs *funcs;
>  	} mmio;
>  
>  	struct {

-- 
Jani Nikula, Intel

Re: [PATCH 2/9] drm/i915/de: Convert intel_de_{read,write}() into vfuncs

[Ville Syrjälä]

On Fri, Nov 06, 2026 at 04:50:19PM +0200, Jani Nikula wrote:
> On Thu, 05 Nov 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Different platforms will need to do different things in
> > their mmio accessors. The plan is to trade the overhead
> > of runtime platform checks into no runtime checks and
> > the cost of a vfunc call. This seems to provide slightly
> > better overall performance.
> 
> What's the plan for the 8- and 16-bit counterparts?

Just raw readb/readw.

> 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_de.c         | 17 +++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_de.h         |  9 +++++++--
> >  .../gpu/drm/i915/display/intel_display_core.h   |  2 ++
> >  3 files changed, 26 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> > index 6b3d06147e58..4f423a684ec2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_de.c
> > +++ b/drivers/gpu/drm/i915/display/intel_de.c
> > @@ -163,7 +163,24 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
> >  	return intel_uncore_read16(__to_uncore(display), reg);
> >  }
> >  
> > +static u32 i9xx_mmio_read(struct intel_display *display, intel_reg_t reg)
> > +{
> > +	return intel_uncore_read(__to_uncore(display), reg);
> > +}
> > +
> > +static void i9xx_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
> > +{
> > +	intel_uncore_write(__to_uncore(display), reg, val);
> > +}
> > +
> > +static const struct intel_mmio_funcs i9xx_mmio_funcs = {
> > +	.read = i9xx_mmio_read,
> > +	.write = i9xx_mmio_write,
> > +};
> > +
> >  void intel_de_init(struct intel_display *display)
> >  {
> >  	display->mmio.uncore = to_intel_uncore(display->drm);
> > +
> > +	display->mmio.funcs = &i9xx_mmio_funcs;
> >  }
> > diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
> > index f1135ee5071b..63aef17e6ed3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_de.h
> > +++ b/drivers/gpu/drm/i915/display/intel_de.h
> > @@ -12,6 +12,11 @@
> >  #include "intel_uncore.h"
> >  #include "intel_uncore_trace.h"
> >  
> > +struct intel_mmio_funcs {
> > +	u32 (*read)(struct intel_display *display, intel_reg_t reg);
> > +	void (*write)(struct intel_display *display, intel_reg_t reg, u32 val);
> > +};
> > +
> 
> Wondering if this should be in intel_display_core.h as all the other
> ones are. But let's see how it pans out.

Only intel_de.{c,h} need the definition so seems like it belongs there.

> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> >  static inline struct intel_uncore *__to_uncore(struct intel_display *display)
> >  {
> >  	return display->mmio.uncore;
> > @@ -30,7 +35,7 @@ intel_de_read(struct intel_display *display, intel_reg_t reg)
> >  
> >  	intel_dmc_wl_get(display, reg);
> >  
> > -	val = intel_uncore_read(__to_uncore(display), reg);
> > +	val = display->mmio.funcs->read(display, reg);
> >  
> >  	intel_dmc_wl_put(display, reg);
> >  
> > @@ -60,7 +65,7 @@ intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val)
> >  {
> >  	intel_dmc_wl_get(display, reg);
> >  
> > -	intel_uncore_write(__to_uncore(display), reg, val);
> > +	display->mmio.funcs->write(display, reg, val);
> >  
> >  	intel_dmc_wl_put(display, reg);
> >  }
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> > index 35409f9abb2f..3a48119f7890 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > @@ -49,6 +49,7 @@ struct intel_fbdev;
> >  struct intel_fdi_funcs;
> >  struct intel_hotplug_irq_funcs;
> >  struct intel_initial_plane_config;
> > +struct intel_mmio_funcs;
> >  struct intel_opregion;
> >  struct intel_overlay;
> >  struct intel_uncore;
> > @@ -533,6 +534,7 @@ struct intel_display {
> >  
> >  	struct {
> >  		struct intel_uncore *uncore;
> > +		const struct intel_mmio_funcs *funcs;
> >  	} mmio;
> >  
> >  	struct {
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

[PATCH 3/9] drm/i915/de: Introduce mmio read/write templates

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In order to eliminate runtime platform check overhead from
the mmio read/write functions, we'll need a good way to construct
optimal variants for each platform. Do that in the form of
__intel_de_{read,write}() that can be customized via (compile time
constnt) mmio_flags. The compiler will eliminate all the stuff
we don't want.

For now there is nothing to eliminate but next we'll start
moving more stuff in to make that possible.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_de.c | 26 +++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
index 4f423a684ec2..cde2886fe2ca 100644
--- a/drivers/gpu/drm/i915/display/intel_de.c
+++ b/drivers/gpu/drm/i915/display/intel_de.c
@@ -163,16 +163,38 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
 	return intel_uncore_read16(__to_uncore(display), reg);
 }
 
+static __always_inline u32
+__intel_de_read(struct intel_display *display, intel_reg_t reg,
+		const unsigned int mmio_flags)
+{
+	u32 val;
+
+	val = intel_uncore_read(__to_uncore(display), reg);
+
+	return val;
+}
+
+static __always_inline void
+__intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
+		 const unsigned int mmio_flags)
+{
+	intel_uncore_write(__to_uncore(display), reg, val);
+}
+
+#define I9XX_MMIO_FLAGS 0
+
 static u32 i9xx_mmio_read(struct intel_display *display, intel_reg_t reg)
 {
-	return intel_uncore_read(__to_uncore(display), reg);
+	return __intel_de_read(display, reg, I9XX_MMIO_FLAGS);
 }
 
 static void i9xx_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
 {
-	intel_uncore_write(__to_uncore(display), reg, val);
+	__intel_de_write(display, reg, val, I9XX_MMIO_FLAGS);
 }
 
+#undef I9XX_MMIO_FLAGS
+
 static const struct intel_mmio_funcs i9xx_mmio_funcs = {
 	.read = i9xx_mmio_read,
 	.write = i9xx_mmio_write,
-- 
2.56.0

Re: [PATCH 3/9] drm/i915/de: Introduce mmio read/write templates

[Michał Grzelak]

On Thu, Nov 05, 2026 at 12:18:36AM GMT, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> In order to eliminate runtime platform check overhead from
> the mmio read/write functions, we'll need a good way to construct
> optimal variants for each platform. Do that in the form of
> __intel_de_{read,write}() that can be customized via (compile time
> constnt) mmio_flags. The compiler will eliminate all the stuff

s/constnt/constant/

> we don't want.
> 
> For now there is nothing to eliminate but next we'll start
> moving more stuff in to make that possible.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Michał Grzelak <michal.grzelak@linux.intel.com>

BR,
Michał

> ---
>  drivers/gpu/drm/i915/display/intel_de.c | 26 +++++++++++++++++++++++--
>  1 file changed, 24 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> index 4f423a684ec2..cde2886fe2ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.c
> +++ b/drivers/gpu/drm/i915/display/intel_de.c
> @@ -163,16 +163,38 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
>  	return intel_uncore_read16(__to_uncore(display), reg);
>  }
>  
> +static __always_inline u32
> +__intel_de_read(struct intel_display *display, intel_reg_t reg,
> +		const unsigned int mmio_flags)
> +{
> +	u32 val;
> +
> +	val = intel_uncore_read(__to_uncore(display), reg);
> +
> +	return val;
> +}
> +
> +static __always_inline void
> +__intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
> +		 const unsigned int mmio_flags)
> +{
> +	intel_uncore_write(__to_uncore(display), reg, val);
> +}
> +
> +#define I9XX_MMIO_FLAGS 0
> +
>  static u32 i9xx_mmio_read(struct intel_display *display, intel_reg_t reg)
>  {
> -	return intel_uncore_read(__to_uncore(display), reg);
> +	return __intel_de_read(display, reg, I9XX_MMIO_FLAGS);
>  }
>  
>  static void i9xx_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
>  {
> -	intel_uncore_write(__to_uncore(display), reg, val);
> +	__intel_de_write(display, reg, val, I9XX_MMIO_FLAGS);
>  }
>  
> +#undef I9XX_MMIO_FLAGS
> +
>  static const struct intel_mmio_funcs i9xx_mmio_funcs = {
>  	.read = i9xx_mmio_read,
>  	.write = i9xx_mmio_write,
> -- 
> 2.56.0
> 

Re: [PATCH 3/9] drm/i915/de: Introduce mmio read/write templates

[Jani Nikula]

On Thu, 05 Nov 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In order to eliminate runtime platform check overhead from
> the mmio read/write functions, we'll need a good way to construct
> optimal variants for each platform. Do that in the form of
> __intel_de_{read,write}() that can be customized via (compile time
> constnt) mmio_flags. The compiler will eliminate all the stuff
> we don't want.

Are the __always_inline required?

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> For now there is nothing to eliminate but next we'll start
> moving more stuff in to make that possible.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_de.c | 26 +++++++++++++++++++++++--
>  1 file changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> index 4f423a684ec2..cde2886fe2ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.c
> +++ b/drivers/gpu/drm/i915/display/intel_de.c
> @@ -163,16 +163,38 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
>  	return intel_uncore_read16(__to_uncore(display), reg);
>  }
>  
> +static __always_inline u32
> +__intel_de_read(struct intel_display *display, intel_reg_t reg,
> +		const unsigned int mmio_flags)
> +{
> +	u32 val;
> +
> +	val = intel_uncore_read(__to_uncore(display), reg);
> +
> +	return val;
> +}
> +
> +static __always_inline void
> +__intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
> +		 const unsigned int mmio_flags)
> +{
> +	intel_uncore_write(__to_uncore(display), reg, val);
> +}
> +
> +#define I9XX_MMIO_FLAGS 0
> +
>  static u32 i9xx_mmio_read(struct intel_display *display, intel_reg_t reg)
>  {
> -	return intel_uncore_read(__to_uncore(display), reg);
> +	return __intel_de_read(display, reg, I9XX_MMIO_FLAGS);
>  }
>  
>  static void i9xx_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
>  {
> -	intel_uncore_write(__to_uncore(display), reg, val);
> +	__intel_de_write(display, reg, val, I9XX_MMIO_FLAGS);
>  }
>  
> +#undef I9XX_MMIO_FLAGS
> +
>  static const struct intel_mmio_funcs i9xx_mmio_funcs = {
>  	.read = i9xx_mmio_read,
>  	.write = i9xx_mmio_write,

-- 
Jani Nikula, Intel

Re: [PATCH 3/9] drm/i915/de: Introduce mmio read/write templates

[Ville Syrjälä]

On Fri, Nov 06, 2026 at 04:52:22PM +0200, Jani Nikula wrote:
> On Thu, 05 Nov 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > In order to eliminate runtime platform check overhead from
> > the mmio read/write functions, we'll need a good way to construct
> > optimal variants for each platform. Do that in the form of
> > __intel_de_{read,write}() that can be customized via (compile time
> > constnt) mmio_flags. The compiler will eliminate all the stuff
> > we don't want.
> 
> Are the __always_inline required?

Perhaps not in practice, don't think I actually checked the
generated code without them. I put them there because I really
want to force the compiler to notice that mmio_flags is a
compile time constant and thus there is dead code to eliminate. 
Dunno if I want to rely on compiler inlining heuristics for that.

> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> >
> > For now there is nothing to eliminate but next we'll start
> > moving more stuff in to make that possible.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_de.c | 26 +++++++++++++++++++++++--
> >  1 file changed, 24 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> > index 4f423a684ec2..cde2886fe2ca 100644
> > --- a/drivers/gpu/drm/i915/display/intel_de.c
> > +++ b/drivers/gpu/drm/i915/display/intel_de.c
> > @@ -163,16 +163,38 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
> >  	return intel_uncore_read16(__to_uncore(display), reg);
> >  }
> >  
> > +static __always_inline u32
> > +__intel_de_read(struct intel_display *display, intel_reg_t reg,
> > +		const unsigned int mmio_flags)
> > +{
> > +	u32 val;
> > +
> > +	val = intel_uncore_read(__to_uncore(display), reg);
> > +
> > +	return val;
> > +}
> > +
> > +static __always_inline void
> > +__intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
> > +		 const unsigned int mmio_flags)
> > +{
> > +	intel_uncore_write(__to_uncore(display), reg, val);
> > +}
> > +
> > +#define I9XX_MMIO_FLAGS 0
> > +
> >  static u32 i9xx_mmio_read(struct intel_display *display, intel_reg_t reg)
> >  {
> > -	return intel_uncore_read(__to_uncore(display), reg);
> > +	return __intel_de_read(display, reg, I9XX_MMIO_FLAGS);
> >  }
> >  
> >  static void i9xx_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
> >  {
> > -	intel_uncore_write(__to_uncore(display), reg, val);
> > +	__intel_de_write(display, reg, val, I9XX_MMIO_FLAGS);
> >  }
> >  
> > +#undef I9XX_MMIO_FLAGS
> > +
> >  static const struct intel_mmio_funcs i9xx_mmio_funcs = {
> >  	.read = i9xx_mmio_read,
> >  	.write = i9xx_mmio_write,
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

[PATCH 4/9] drm/i915/de: Eliminate runtime overhead from DMC wakelock on pre-LNL platforms

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that we have the mmio read/write vfuncs we can get rid of
any runtime overhead from the DMC wakelock checks for the
platforms that don't support wakelock (pre-LNL).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_de.c | 50 ++++++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_de.h | 15 +-------
 2 files changed, 50 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
index cde2886fe2ca..66de0d6be569 100644
--- a/drivers/gpu/drm/i915/display/intel_de.c
+++ b/drivers/gpu/drm/i915/display/intel_de.c
@@ -163,14 +163,36 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
 	return intel_uncore_read16(__to_uncore(display), reg);
 }
 
+#define __MMIO_WAKELOCK		BIT(0)
+
+static __always_inline void
+__mmio_wakelock_pre(struct intel_display *display, intel_reg_t reg,
+		    const unsigned int mmio_flags)
+{
+	if (mmio_flags & __MMIO_WAKELOCK)
+		intel_dmc_wl_get(display, reg);
+}
+
+static __always_inline void
+__mmio_wakelock_post(struct intel_display *display, intel_reg_t reg,
+		     const unsigned int mmio_flags)
+{
+	if (mmio_flags & __MMIO_WAKELOCK)
+		intel_dmc_wl_put(display, reg);
+}
+
 static __always_inline u32
 __intel_de_read(struct intel_display *display, intel_reg_t reg,
 		const unsigned int mmio_flags)
 {
 	u32 val;
 
+	__mmio_wakelock_pre(display, reg, mmio_flags);
+
 	val = intel_uncore_read(__to_uncore(display), reg);
 
+	__mmio_wakelock_post(display, reg, mmio_flags);
+
 	return val;
 }
 
@@ -178,7 +200,11 @@ static __always_inline void
 __intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
 		 const unsigned int mmio_flags)
 {
+	__mmio_wakelock_pre(display, reg, mmio_flags);
+
 	intel_uncore_write(__to_uncore(display), reg, val);
+
+	__mmio_wakelock_post(display, reg, mmio_flags);
 }
 
 #define I9XX_MMIO_FLAGS 0
@@ -200,9 +226,31 @@ static const struct intel_mmio_funcs i9xx_mmio_funcs = {
 	.write = i9xx_mmio_write,
 };
 
+#define LNL_MMIO_FLAGS __MMIO_WAKELOCK
+
+static u32 lnl_mmio_read(struct intel_display *display, intel_reg_t reg)
+{
+	return __intel_de_read(display, reg, LNL_MMIO_FLAGS);
+}
+
+static void lnl_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
+{
+	__intel_de_write(display, reg, val, LNL_MMIO_FLAGS);
+}
+
+#undef LNL_MMIO_FLAGS
+
+static const struct intel_mmio_funcs lnl_mmio_funcs = {
+	.read = lnl_mmio_read,
+	.write = lnl_mmio_write,
+};
+
 void intel_de_init(struct intel_display *display)
 {
 	display->mmio.uncore = to_intel_uncore(display->drm);
 
-	display->mmio.funcs = &i9xx_mmio_funcs;
+	if (DISPLAY_VER(display) >= 20)
+		display->mmio.funcs = &lnl_mmio_funcs;
+	else
+		display->mmio.funcs = &i9xx_mmio_funcs;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index 63aef17e6ed3..760b8bc31f9b 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -7,7 +7,6 @@
 #define __INTEL_DE_H__
 
 #include "intel_display_core.h"
-#include "intel_dmc_wl.h"
 #include "intel_dsb.h"
 #include "intel_uncore.h"
 #include "intel_uncore_trace.h"
@@ -31,15 +30,7 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg);
 static inline u32
 intel_de_read(struct intel_display *display, intel_reg_t reg)
 {
-	u32 val;
-
-	intel_dmc_wl_get(display, reg);
-
-	val = display->mmio.funcs->read(display, reg);
-
-	intel_dmc_wl_put(display, reg);
-
-	return val;
+	return display->mmio.funcs->read(display, reg);
 }
 
 static inline u64
@@ -63,11 +54,7 @@ intel_de_posting_read(struct intel_display *display, intel_reg_t reg)
 static inline void
 intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val)
 {
-	intel_dmc_wl_get(display, reg);
-
 	display->mmio.funcs->write(display, reg, val);
-
-	intel_dmc_wl_put(display, reg);
 }
 
 static inline u32
-- 
2.56.0

Re: [PATCH 4/9] drm/i915/de: Eliminate runtime overhead from DMC wakelock on pre-LNL platforms

[Jani Nikula]

On Thu, 05 Nov 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that we have the mmio read/write vfuncs we can get rid of
> any runtime overhead from the DMC wakelock checks for the
> platforms that don't support wakelock (pre-LNL).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_de.c | 50 ++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_de.h | 15 +-------
>  2 files changed, 50 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> index cde2886fe2ca..66de0d6be569 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.c
> +++ b/drivers/gpu/drm/i915/display/intel_de.c
> @@ -163,14 +163,36 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
>  	return intel_uncore_read16(__to_uncore(display), reg);
>  }
>  
> +#define __MMIO_WAKELOCK		BIT(0)
> +
> +static __always_inline void
> +__mmio_wakelock_pre(struct intel_display *display, intel_reg_t reg,
> +		    const unsigned int mmio_flags)
> +{
> +	if (mmio_flags & __MMIO_WAKELOCK)
> +		intel_dmc_wl_get(display, reg);
> +}
> +
> +static __always_inline void
> +__mmio_wakelock_post(struct intel_display *display, intel_reg_t reg,
> +		     const unsigned int mmio_flags)
> +{
> +	if (mmio_flags & __MMIO_WAKELOCK)
> +		intel_dmc_wl_put(display, reg);
> +}
> +
>  static __always_inline u32
>  __intel_de_read(struct intel_display *display, intel_reg_t reg,
>  		const unsigned int mmio_flags)
>  {
>  	u32 val;
>  
> +	__mmio_wakelock_pre(display, reg, mmio_flags);
> +
>  	val = intel_uncore_read(__to_uncore(display), reg);
>  
> +	__mmio_wakelock_post(display, reg, mmio_flags);
> +
>  	return val;
>  }
>  
> @@ -178,7 +200,11 @@ static __always_inline void
>  __intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
>  		 const unsigned int mmio_flags)
>  {
> +	__mmio_wakelock_pre(display, reg, mmio_flags);
> +
>  	intel_uncore_write(__to_uncore(display), reg, val);
> +
> +	__mmio_wakelock_post(display, reg, mmio_flags);
>  }
>  
>  #define I9XX_MMIO_FLAGS 0
> @@ -200,9 +226,31 @@ static const struct intel_mmio_funcs i9xx_mmio_funcs = {
>  	.write = i9xx_mmio_write,
>  };
>  
> +#define LNL_MMIO_FLAGS __MMIO_WAKELOCK
> +
> +static u32 lnl_mmio_read(struct intel_display *display, intel_reg_t reg)
> +{
> +	return __intel_de_read(display, reg, LNL_MMIO_FLAGS);
> +}
> +
> +static void lnl_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
> +{
> +	__intel_de_write(display, reg, val, LNL_MMIO_FLAGS);
> +}
> +
> +#undef LNL_MMIO_FLAGS
> +
> +static const struct intel_mmio_funcs lnl_mmio_funcs = {
> +	.read = lnl_mmio_read,
> +	.write = lnl_mmio_write,
> +};
> +
>  void intel_de_init(struct intel_display *display)
>  {
>  	display->mmio.uncore = to_intel_uncore(display->drm);
>  
> -	display->mmio.funcs = &i9xx_mmio_funcs;
> +	if (DISPLAY_VER(display) >= 20)
> +		display->mmio.funcs = &lnl_mmio_funcs;
> +	else
> +		display->mmio.funcs = &i9xx_mmio_funcs;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
> index 63aef17e6ed3..760b8bc31f9b 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -7,7 +7,6 @@
>  #define __INTEL_DE_H__
>  
>  #include "intel_display_core.h"
> -#include "intel_dmc_wl.h"
>  #include "intel_dsb.h"
>  #include "intel_uncore.h"
>  #include "intel_uncore_trace.h"
> @@ -31,15 +30,7 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg);
>  static inline u32
>  intel_de_read(struct intel_display *display, intel_reg_t reg)
>  {
> -	u32 val;
> -
> -	intel_dmc_wl_get(display, reg);
> -
> -	val = display->mmio.funcs->read(display, reg);
> -
> -	intel_dmc_wl_put(display, reg);
> -
> -	return val;
> +	return display->mmio.funcs->read(display, reg);
>  }
>  
>  static inline u64
> @@ -63,11 +54,7 @@ intel_de_posting_read(struct intel_display *display, intel_reg_t reg)
>  static inline void
>  intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val)
>  {
> -	intel_dmc_wl_get(display, reg);
> -
>  	display->mmio.funcs->write(display, reg, val);
> -
> -	intel_dmc_wl_put(display, reg);
>  }
>  
>  static inline u32

-- 
Jani Nikula, Intel

[PATCH 5/9] drm/i915/de: Introduce display->mmio.lock

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Introduce our own display specific mmio.lock, and wrap
the more expensive non-fw register accesses with it. And
everything that explicitly takes the uncore.lock currently,
switch over to mmio.lock as well.

This will preserve the same serialization behavior between
display registers as the uncore.lock is currently providing.
Once uncore.lock has actually been eliminated from display
registers (not the case yet) display vs. non-display
register accesses could happen in parallel. But that should
be fine since generally the registers for different hardware
units don't live on the same cacheline, so even concerns
about parallel accesses to the same cacheline potentially
hanging the machine (on IVB/HSW) should be assuaged.

Currently uncore.lock usage is limited to SNB+ on i915.
The xe driver, and older platforms on the i915 driver
don't use uncore.lock. Follow the same rule for the mmio.lock
initially.

With this we now end up with a double lock, or even a
triple lock due to i915's mmio debug lock. But we'll eliminate
the extra locks shortly. The end goal is either just mmio.lock
or no locks whatsoever. Well, ignoring the DMC wakelock stuff
that uses an additional lock as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_wm.c        |  9 ++-
 drivers/gpu/drm/i915/display/intel_de.c       | 69 +++++++++++++++++--
 .../gpu/drm/i915/display/intel_display_core.h |  9 +++
 drivers/gpu/drm/i915/display/intel_vblank.c   | 16 ++---
 4 files changed, 83 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 0233f5053d95..46bfada7c060 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -1863,7 +1863,6 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 				   struct intel_crtc *crtc)
 {
 	struct intel_display *display = to_intel_display(crtc);
-	struct intel_uncore *uncore = to_intel_uncore(display->drm);
 	const struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	const struct vlv_fifo_state *fifo_state =
@@ -1884,15 +1883,15 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 	trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
 
 	/*
-	 * uncore.lock serves a double purpose here. It allows us to
-	 * use the less expensive I915_{READ,WRITE}_FW() functions, and
+	 * display->mmio.lock serves a double purpose here. It allows us to
+	 * use the less expensive intel_de_{read,write}_fw() functions, and
 	 * it protects the DSPARB registers from getting clobbered by
 	 * parallel updates from multiple pipes.
 	 *
 	 * intel_pipe_update_start() has already disabled interrupts
 	 * for us, so a plain spin_lock() is sufficient here.
 	 */
-	spin_lock(&uncore->lock);
+	spin_lock(&display->mmio.lock);
 
 	switch (crtc->pipe) {
 	case PIPE_A:
@@ -1952,7 +1951,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 
 	intel_de_read_fw(display, DSPARB(display));
 
-	spin_unlock(&uncore->lock);
+	spin_unlock(&display->mmio.lock);
 }
 
 #undef VLV_FIFO
diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
index 66de0d6be569..8b7a4e696ff9 100644
--- a/drivers/gpu/drm/i915/display/intel_de.c
+++ b/drivers/gpu/drm/i915/display/intel_de.c
@@ -164,6 +164,7 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
 }
 
 #define __MMIO_WAKELOCK		BIT(0)
+#define __MMIO_LOCK		BIT(1)
 
 static __always_inline void
 __mmio_wakelock_pre(struct intel_display *display, intel_reg_t reg,
@@ -181,16 +182,35 @@ __mmio_wakelock_post(struct intel_display *display, intel_reg_t reg,
 		intel_dmc_wl_put(display, reg);
 }
 
+static __always_inline void
+__mmio_lock_pre(struct intel_display *display, unsigned long *irqflags,
+		const unsigned int mmio_flags)
+{
+	if (mmio_flags & __MMIO_LOCK)
+		spin_lock_irqsave(&display->mmio.lock, *irqflags);
+}
+
+static __always_inline void
+__mmio_lock_post(struct intel_display *display, unsigned long irqflags,
+		 const unsigned int mmio_flags)
+{
+	if (mmio_flags & __MMIO_LOCK)
+		spin_unlock_irqrestore(&display->mmio.lock, irqflags);
+}
+
 static __always_inline u32
 __intel_de_read(struct intel_display *display, intel_reg_t reg,
 		const unsigned int mmio_flags)
 {
+	unsigned long irqflags;
 	u32 val;
 
 	__mmio_wakelock_pre(display, reg, mmio_flags);
+	__mmio_lock_pre(display, &irqflags, mmio_flags);
 
 	val = intel_uncore_read(__to_uncore(display), reg);
 
+	__mmio_lock_post(display, irqflags, mmio_flags);
 	__mmio_wakelock_post(display, reg, mmio_flags);
 
 	return val;
@@ -200,10 +220,14 @@ static __always_inline void
 __intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
 		 const unsigned int mmio_flags)
 {
+	unsigned long irqflags;
+
 	__mmio_wakelock_pre(display, reg, mmio_flags);
+	__mmio_lock_pre(display, &irqflags, mmio_flags);
 
 	intel_uncore_write(__to_uncore(display), reg, val);
 
+	__mmio_lock_post(display, irqflags, mmio_flags);
 	__mmio_wakelock_post(display, reg, mmio_flags);
 }
 
@@ -226,6 +250,25 @@ static const struct intel_mmio_funcs i9xx_mmio_funcs = {
 	.write = i9xx_mmio_write,
 };
 
+#define SNB_MMIO_FLAGS __MMIO_LOCK
+
+static u32 snb_mmio_read(struct intel_display *display, intel_reg_t reg)
+{
+	return __intel_de_read(display, reg, SNB_MMIO_FLAGS);
+}
+
+static void snb_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
+{
+	__intel_de_write(display, reg, val, SNB_MMIO_FLAGS);
+}
+
+#undef SNB_MMIO_FLAGS
+
+static const struct intel_mmio_funcs snb_mmio_funcs = {
+	.read = snb_mmio_read,
+	.write = snb_mmio_write,
+};
+
 #define LNL_MMIO_FLAGS __MMIO_WAKELOCK
 
 static u32 lnl_mmio_read(struct intel_display *display, intel_reg_t reg)
@@ -245,12 +288,30 @@ static const struct intel_mmio_funcs lnl_mmio_funcs = {
 	.write = lnl_mmio_write,
 };
 
+static bool driver_is_i915(void)
+{
+#ifdef I915
+	return true;
+#else
+	return false;
+#endif
+}
+
 void intel_de_init(struct intel_display *display)
 {
 	display->mmio.uncore = to_intel_uncore(display->drm);
 
-	if (DISPLAY_VER(display) >= 20)
-		display->mmio.funcs = &lnl_mmio_funcs;
-	else
-		display->mmio.funcs = &i9xx_mmio_funcs;
+	spin_lock_init(&display->mmio.lock);
+
+	if (driver_is_i915()) {
+		if (DISPLAY_VER(display) >= 6)
+			display->mmio.funcs = &snb_mmio_funcs;
+		else
+			display->mmio.funcs = &i9xx_mmio_funcs;
+	} else {
+		if (DISPLAY_VER(display) >= 20)
+			display->mmio.funcs = &lnl_mmio_funcs;
+		else
+			display->mmio.funcs = &i9xx_mmio_funcs;
+	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 3a48119f7890..aded2af8c92a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -533,6 +533,15 @@ struct intel_display {
 	} modeset;
 
 	struct {
+		/*
+		 * Simultaneous accesses to the same cacheline of
+		 * registers may hang IVB/HSW systems. This lock
+		 * serializes all display register accesses done
+		 * using intel_de_{read,write}(), but not those
+		 * done using intel_de_{read,write}_fw().
+		 */
+		spinlock_t lock;
+
 		struct intel_uncore *uncore;
 		const struct intel_mmio_funcs *funcs;
 	} mmio;
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 1d4753605675..fc9d1e14ec87 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -281,10 +281,6 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 }
 
 /*
- * The uncore version of the spin lock functions is used to decide
- * whether we need to lock the uncore lock or not.  This is only
- * needed in i915, not in Xe.
- *
  * This lock in i915 is needed because some old platforms (at least
  * IVB and possibly HSW as well), which are not supported in Xe, need
  * all register accesses to the same cacheline to be serialized,
@@ -292,17 +288,15 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
  */
 #ifdef I915
 static void intel_vblank_section_enter(struct intel_display *display)
-	__acquires(uncore->lock)
+	__acquires(display->mmio.lock)
 {
-	struct intel_uncore *uncore = to_intel_uncore(display->drm);
-	spin_lock(&uncore->lock);
+	spin_lock(&display->mmio.lock);
 }
 
 static void intel_vblank_section_exit(struct intel_display *display)
-	__releases(uncore->lock)
+	__releases(display->mmio.lock)
 {
-	struct intel_uncore *uncore = to_intel_uncore(display->drm);
-	spin_unlock(&uncore->lock);
+	spin_unlock(&display->mmio.lock);
 }
 #else
 static void intel_vblank_section_enter(struct intel_display *display)
@@ -550,7 +544,7 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
 	 * consistent state during fastset seamless refresh rate changes.
 	 *
 	 * vblank_time_lock takes care of all drm_vblank.c stuff, and
-	 * uncore.lock takes care of __intel_get_crtc_scanline() which
+	 * display->mmio.lock takes care of __intel_get_crtc_scanline() which
 	 * may get called elsewhere as well.
 	 *
 	 * TODO maybe just protect everything (including
-- 
2.56.0

Re: [PATCH 5/9] drm/i915/de: Introduce display->mmio.lock

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915/de: intel_de_init() skipped when HAS_DISPLAY() is initially false
--

commit 86812b856eea85785d3fee2a5eb70c5246338748
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>

drm/i915/de: Introduce display->mmio.lock

This commit introduces a display-specific spinlock, display->mmio.lock, to
serialize non-fw display register accesses on SNB+ platforms in i915 and
switches explicit display users of uncore.lock over to display->mmio.lock.

> diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> index 66de0d6be5699..8b7a4e696ff96 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.c
> +++ b/drivers/gpu/drm/i915/display/intel_de.c

[ ... ]

> @@ -245,12 +288,30 @@ static const struct intel_mmio_funcs lnl_mmio_funcs = {
>  	.write = lnl_mmio_write,
>  };
>  
> +static bool driver_is_i915(void)
> +{
> +#ifdef I915
> +	return true;
> +#else
> +	return false;
> +#endif
> +}
> +
>  void intel_de_init(struct intel_display *display)
>  {
>  	display->mmio.uncore = to_intel_uncore(display->drm);
>  
> -	if (DISPLAY_VER(display) >= 20)
> -		display->mmio.funcs = &lnl_mmio_funcs;
> -	else
> -		display->mmio.funcs = &i9xx_mmio_funcs;
> +	spin_lock_init(&display->mmio.lock);

[Severity: High]
Can display->mmio.lock and display->mmio.uncore remain uninitialized when
HAS_DISPLAY(display) is false?

During i915_driver_mmio_probe(), intel_display_device_info_runtime_init()
only calls __intel_display_device_info_runtime_init() -> intel_de_init()
when HAS_DISPLAY(display) is true:

drivers/gpu/drm/i915/display/intel_display_device.c:
intel_display_device_info_runtime_init() {
	if (HAS_DISPLAY(display))
		__intel_display_device_info_runtime_init(display);
    ...
}

When intel_display_device_probe() takes the no_display path (such as on
INTEL_IVB_Q_IDS via has_no_display(), INTEL_ATS_M_IDS via
!find_platform_desc(), or GMD_ID platforms where GMD_ID_DISPLAY reads 0 in
probe_gmdid_display()), pipe_mask is 0, so HAS_DISPLAY(display) is false
and intel_de_init() is skipped.

However, several paths in i915 still access display registers when
HAS_DISPLAY(display) is false:

1. On INTEL_IVB_Q_IDS, ilk_irq_handler() unconditionally calls
   ilk_display_irq_master_disable() and ilk_display_irq_master_enable(),
   which call intel_de_read_fw(display, DEIER) and
   intel_de_write_fw(display, DEIER, ...) and dereference
   display->mmio.uncore while it is NULL.

2. On headless Gen11+ and GMD_ID platforms (such as INTEL_ATS_M_IDS),
   gen11_irq_handler() and dg1_irq_handler() unconditionally call
   gen11_gu_misc_irq_ack(), which calls
   intel_de_read_fw(display, GEN11_GU_MISC_IIR) when GEN11_GU_MISC_IRQ is
   signalled.

3. During resume, i915_drm_resume() unconditionally calls
   intel_gmbus_reset(display), which calls
   intel_de_write_fw(display, GMBUS0(display), 0).

Should intel_de_init() be called unconditionally even when
HAS_DISPLAY(display) is false so that display->mmio.uncore,
display->mmio.lock, and display->mmio.funcs are always initialized?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261104221842.18799-1-ville.syrjala@linux.intel.com?part=5

Re: [PATCH 5/9] drm/i915/de: Introduce display->mmio.lock

[Jani Nikula]

On Thu, 05 Nov 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Introduce our own display specific mmio.lock, and wrap
> the more expensive non-fw register accesses with it. And
> everything that explicitly takes the uncore.lock currently,
> switch over to mmio.lock as well.
>
> This will preserve the same serialization behavior between
> display registers as the uncore.lock is currently providing.
> Once uncore.lock has actually been eliminated from display
> registers (not the case yet) display vs. non-display
> register accesses could happen in parallel. But that should
> be fine since generally the registers for different hardware
> units don't live on the same cacheline, so even concerns
> about parallel accesses to the same cacheline potentially
> hanging the machine (on IVB/HSW) should be assuaged.
>
> Currently uncore.lock usage is limited to SNB+ on i915.
> The xe driver, and older platforms on the i915 driver
> don't use uncore.lock. Follow the same rule for the mmio.lock
> initially.
>
> With this we now end up with a double lock, or even a
> triple lock due to i915's mmio debug lock. But we'll eliminate
> the extra locks shortly. The end goal is either just mmio.lock
> or no locks whatsoever. Well, ignoring the DMC wakelock stuff
> that uses an additional lock as well.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/i9xx_wm.c        |  9 ++-
>  drivers/gpu/drm/i915/display/intel_de.c       | 69 +++++++++++++++++--
>  .../gpu/drm/i915/display/intel_display_core.h |  9 +++
>  drivers/gpu/drm/i915/display/intel_vblank.c   | 16 ++---
>  4 files changed, 83 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 0233f5053d95..46bfada7c060 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -1863,7 +1863,6 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  				   struct intel_crtc *crtc)
>  {
>  	struct intel_display *display = to_intel_display(crtc);
> -	struct intel_uncore *uncore = to_intel_uncore(display->drm);
>  	const struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	const struct vlv_fifo_state *fifo_state =
> @@ -1884,15 +1883,15 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  	trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
>  
>  	/*
> -	 * uncore.lock serves a double purpose here. It allows us to
> -	 * use the less expensive I915_{READ,WRITE}_FW() functions, and
> +	 * display->mmio.lock serves a double purpose here. It allows us to
> +	 * use the less expensive intel_de_{read,write}_fw() functions, and
>  	 * it protects the DSPARB registers from getting clobbered by
>  	 * parallel updates from multiple pipes.
>  	 *
>  	 * intel_pipe_update_start() has already disabled interrupts
>  	 * for us, so a plain spin_lock() is sufficient here.
>  	 */
> -	spin_lock(&uncore->lock);
> +	spin_lock(&display->mmio.lock);
>  
>  	switch (crtc->pipe) {
>  	case PIPE_A:
> @@ -1952,7 +1951,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  
>  	intel_de_read_fw(display, DSPARB(display));
>  
> -	spin_unlock(&uncore->lock);
> +	spin_unlock(&display->mmio.lock);
>  }
>  
>  #undef VLV_FIFO
> diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> index 66de0d6be569..8b7a4e696ff9 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.c
> +++ b/drivers/gpu/drm/i915/display/intel_de.c
> @@ -164,6 +164,7 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
>  }
>  
>  #define __MMIO_WAKELOCK		BIT(0)
> +#define __MMIO_LOCK		BIT(1)
>  
>  static __always_inline void
>  __mmio_wakelock_pre(struct intel_display *display, intel_reg_t reg,
> @@ -181,16 +182,35 @@ __mmio_wakelock_post(struct intel_display *display, intel_reg_t reg,
>  		intel_dmc_wl_put(display, reg);
>  }
>  
> +static __always_inline void
> +__mmio_lock_pre(struct intel_display *display, unsigned long *irqflags,
> +		const unsigned int mmio_flags)
> +{
> +	if (mmio_flags & __MMIO_LOCK)
> +		spin_lock_irqsave(&display->mmio.lock, *irqflags);
> +}
> +
> +static __always_inline void
> +__mmio_lock_post(struct intel_display *display, unsigned long irqflags,
> +		 const unsigned int mmio_flags)
> +{
> +	if (mmio_flags & __MMIO_LOCK)
> +		spin_unlock_irqrestore(&display->mmio.lock, irqflags);
> +}
> +
>  static __always_inline u32
>  __intel_de_read(struct intel_display *display, intel_reg_t reg,
>  		const unsigned int mmio_flags)
>  {
> +	unsigned long irqflags;
>  	u32 val;
>  
>  	__mmio_wakelock_pre(display, reg, mmio_flags);
> +	__mmio_lock_pre(display, &irqflags, mmio_flags);
>  
>  	val = intel_uncore_read(__to_uncore(display), reg);
>  
> +	__mmio_lock_post(display, irqflags, mmio_flags);
>  	__mmio_wakelock_post(display, reg, mmio_flags);
>  
>  	return val;
> @@ -200,10 +220,14 @@ static __always_inline void
>  __intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
>  		 const unsigned int mmio_flags)
>  {
> +	unsigned long irqflags;
> +
>  	__mmio_wakelock_pre(display, reg, mmio_flags);
> +	__mmio_lock_pre(display, &irqflags, mmio_flags);
>  
>  	intel_uncore_write(__to_uncore(display), reg, val);
>  
> +	__mmio_lock_post(display, irqflags, mmio_flags);
>  	__mmio_wakelock_post(display, reg, mmio_flags);
>  }
>  
> @@ -226,6 +250,25 @@ static const struct intel_mmio_funcs i9xx_mmio_funcs = {
>  	.write = i9xx_mmio_write,
>  };
>  
> +#define SNB_MMIO_FLAGS __MMIO_LOCK
> +
> +static u32 snb_mmio_read(struct intel_display *display, intel_reg_t reg)
> +{
> +	return __intel_de_read(display, reg, SNB_MMIO_FLAGS);
> +}
> +
> +static void snb_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
> +{
> +	__intel_de_write(display, reg, val, SNB_MMIO_FLAGS);
> +}
> +
> +#undef SNB_MMIO_FLAGS
> +
> +static const struct intel_mmio_funcs snb_mmio_funcs = {
> +	.read = snb_mmio_read,
> +	.write = snb_mmio_write,
> +};
> +
>  #define LNL_MMIO_FLAGS __MMIO_WAKELOCK
>  
>  static u32 lnl_mmio_read(struct intel_display *display, intel_reg_t reg)
> @@ -245,12 +288,30 @@ static const struct intel_mmio_funcs lnl_mmio_funcs = {
>  	.write = lnl_mmio_write,
>  };
>  
> +static bool driver_is_i915(void)
> +{
> +#ifdef I915
> +	return true;
> +#else
> +	return false;
> +#endif
> +}

Ugh. Can we just not add this, because it needs to go real soon now
anyway? Or do you already have patches in your tree removing this after
some juggle?

> +
>  void intel_de_init(struct intel_display *display)
>  {
>  	display->mmio.uncore = to_intel_uncore(display->drm);
>  
> -	if (DISPLAY_VER(display) >= 20)
> -		display->mmio.funcs = &lnl_mmio_funcs;
> -	else
> -		display->mmio.funcs = &i9xx_mmio_funcs;
> +	spin_lock_init(&display->mmio.lock);
> +
> +	if (driver_is_i915()) {
> +		if (DISPLAY_VER(display) >= 6)
> +			display->mmio.funcs = &snb_mmio_funcs;
> +		else
> +			display->mmio.funcs = &i9xx_mmio_funcs;
> +	} else {
> +		if (DISPLAY_VER(display) >= 20)
> +			display->mmio.funcs = &lnl_mmio_funcs;
> +		else
> +			display->mmio.funcs = &i9xx_mmio_funcs;
> +	}

If we temporarily need driver_is_i915() for the non-functional iterative
approach, seems like a different arrangement of the if ladder would be
benefitial for the eventual removal of driver_is_i915(), maybe something
like:

	if (DISPLAY_VER(display) >= 20)
		display->mmio.funcs = &lnl_mmio_funcs;
	else if (!driver_is_i915())
		display->mmio.funcs = &i9xx_mmio_funcs;
	else if (display->platform.valleyview || display->platform.cherryview)
		display->mmio.funcs = &vlv_mmio_funcs;
	else if (DISPLAY_VER(display) >= 7)
		display->mmio.funcs = &ivb_mmio_funcs;
	else if (DISPLAY_VER(display) >= 6)
		display->mmio.funcs = &snb_mmio_funcs;
	else
		display->mmio.funcs = &i9xx_mmio_funcs;

(This includes changes from later patches.)

I guess I'd like to see the decisions here (and in the vblank code) be
based on platforms rather than driver, even though there's some overlap.

>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 3a48119f7890..aded2af8c92a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -533,6 +533,15 @@ struct intel_display {
>  	} modeset;
>  
>  	struct {
> +		/*
> +		 * Simultaneous accesses to the same cacheline of
> +		 * registers may hang IVB/HSW systems. This lock
> +		 * serializes all display register accesses done
> +		 * using intel_de_{read,write}(), but not those
> +		 * done using intel_de_{read,write}_fw().
> +		 */
> +		spinlock_t lock;
> +

I guess the comment begs the question why are we doing the locking also
on display < 20? Just because the lock is (ab)used for other purposes as
well?

>  		struct intel_uncore *uncore;
>  		const struct intel_mmio_funcs *funcs;
>  	} mmio;
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 1d4753605675..fc9d1e14ec87 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -281,10 +281,6 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>  }
>  
>  /*
> - * The uncore version of the spin lock functions is used to decide
> - * whether we need to lock the uncore lock or not.  This is only
> - * needed in i915, not in Xe.
> - *
>   * This lock in i915 is needed because some old platforms (at least
>   * IVB and possibly HSW as well), which are not supported in Xe, need
>   * all register accesses to the same cacheline to be serialized,
> @@ -292,17 +288,15 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>   */
>  #ifdef I915
>  static void intel_vblank_section_enter(struct intel_display *display)
> -	__acquires(uncore->lock)
> +	__acquires(display->mmio.lock)
>  {
> -	struct intel_uncore *uncore = to_intel_uncore(display->drm);
> -	spin_lock(&uncore->lock);
> +	spin_lock(&display->mmio.lock);
>  }
>  
>  static void intel_vblank_section_exit(struct intel_display *display)
> -	__releases(uncore->lock)
> +	__releases(display->mmio.lock)
>  {
> -	struct intel_uncore *uncore = to_intel_uncore(display->drm);
> -	spin_unlock(&uncore->lock);
> +	spin_unlock(&display->mmio.lock);
>  }
>  #else
>  static void intel_vblank_section_enter(struct intel_display *display)
> @@ -550,7 +544,7 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
>  	 * consistent state during fastset seamless refresh rate changes.
>  	 *
>  	 * vblank_time_lock takes care of all drm_vblank.c stuff, and
> -	 * uncore.lock takes care of __intel_get_crtc_scanline() which
> +	 * display->mmio.lock takes care of __intel_get_crtc_scanline() which
>  	 * may get called elsewhere as well.
>  	 *
>  	 * TODO maybe just protect everything (including

-- 
Jani Nikula, Intel

Re: [PATCH 5/9] drm/i915/de: Introduce display->mmio.lock

[Ville Syrjälä]

On Thu, Nov 05, 2026 at 11:32:25AM +0200, Jani Nikula wrote:
> On Thu, 05 Nov 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Introduce our own display specific mmio.lock, and wrap
> > the more expensive non-fw register accesses with it. And
> > everything that explicitly takes the uncore.lock currently,
> > switch over to mmio.lock as well.
> >
> > This will preserve the same serialization behavior between
> > display registers as the uncore.lock is currently providing.
> > Once uncore.lock has actually been eliminated from display
> > registers (not the case yet) display vs. non-display
> > register accesses could happen in parallel. But that should
> > be fine since generally the registers for different hardware
> > units don't live on the same cacheline, so even concerns
> > about parallel accesses to the same cacheline potentially
> > hanging the machine (on IVB/HSW) should be assuaged.
> >
> > Currently uncore.lock usage is limited to SNB+ on i915.
> > The xe driver, and older platforms on the i915 driver
> > don't use uncore.lock. Follow the same rule for the mmio.lock
> > initially.
> >
> > With this we now end up with a double lock, or even a
> > triple lock due to i915's mmio debug lock. But we'll eliminate
> > the extra locks shortly. The end goal is either just mmio.lock
> > or no locks whatsoever. Well, ignoring the DMC wakelock stuff
> > that uses an additional lock as well.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/i9xx_wm.c        |  9 ++-
> >  drivers/gpu/drm/i915/display/intel_de.c       | 69 +++++++++++++++++--
> >  .../gpu/drm/i915/display/intel_display_core.h |  9 +++
> >  drivers/gpu/drm/i915/display/intel_vblank.c   | 16 ++---
> >  4 files changed, 83 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> > index 0233f5053d95..46bfada7c060 100644
> > --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> > +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> > @@ -1863,7 +1863,6 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
> >  				   struct intel_crtc *crtc)
> >  {
> >  	struct intel_display *display = to_intel_display(crtc);
> > -	struct intel_uncore *uncore = to_intel_uncore(display->drm);
> >  	const struct intel_crtc_state *crtc_state =
> >  		intel_atomic_get_new_crtc_state(state, crtc);
> >  	const struct vlv_fifo_state *fifo_state =
> > @@ -1884,15 +1883,15 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
> >  	trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
> >  
> >  	/*
> > -	 * uncore.lock serves a double purpose here. It allows us to
> > -	 * use the less expensive I915_{READ,WRITE}_FW() functions, and
> > +	 * display->mmio.lock serves a double purpose here. It allows us to
> > +	 * use the less expensive intel_de_{read,write}_fw() functions, and
> >  	 * it protects the DSPARB registers from getting clobbered by
> >  	 * parallel updates from multiple pipes.
> >  	 *
> >  	 * intel_pipe_update_start() has already disabled interrupts
> >  	 * for us, so a plain spin_lock() is sufficient here.
> >  	 */
> > -	spin_lock(&uncore->lock);
> > +	spin_lock(&display->mmio.lock);
> >  
> >  	switch (crtc->pipe) {
> >  	case PIPE_A:
> > @@ -1952,7 +1951,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
> >  
> >  	intel_de_read_fw(display, DSPARB(display));
> >  
> > -	spin_unlock(&uncore->lock);
> > +	spin_unlock(&display->mmio.lock);
> >  }
> >  
> >  #undef VLV_FIFO
> > diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> > index 66de0d6be569..8b7a4e696ff9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_de.c
> > +++ b/drivers/gpu/drm/i915/display/intel_de.c
> > @@ -164,6 +164,7 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
> >  }
> >  
> >  #define __MMIO_WAKELOCK		BIT(0)
> > +#define __MMIO_LOCK		BIT(1)
> >  
> >  static __always_inline void
> >  __mmio_wakelock_pre(struct intel_display *display, intel_reg_t reg,
> > @@ -181,16 +182,35 @@ __mmio_wakelock_post(struct intel_display *display, intel_reg_t reg,
> >  		intel_dmc_wl_put(display, reg);
> >  }
> >  
> > +static __always_inline void
> > +__mmio_lock_pre(struct intel_display *display, unsigned long *irqflags,
> > +		const unsigned int mmio_flags)
> > +{
> > +	if (mmio_flags & __MMIO_LOCK)
> > +		spin_lock_irqsave(&display->mmio.lock, *irqflags);
> > +}
> > +
> > +static __always_inline void
> > +__mmio_lock_post(struct intel_display *display, unsigned long irqflags,
> > +		 const unsigned int mmio_flags)
> > +{
> > +	if (mmio_flags & __MMIO_LOCK)
> > +		spin_unlock_irqrestore(&display->mmio.lock, irqflags);
> > +}
> > +
> >  static __always_inline u32
> >  __intel_de_read(struct intel_display *display, intel_reg_t reg,
> >  		const unsigned int mmio_flags)
> >  {
> > +	unsigned long irqflags;
> >  	u32 val;
> >  
> >  	__mmio_wakelock_pre(display, reg, mmio_flags);
> > +	__mmio_lock_pre(display, &irqflags, mmio_flags);
> >  
> >  	val = intel_uncore_read(__to_uncore(display), reg);
> >  
> > +	__mmio_lock_post(display, irqflags, mmio_flags);
> >  	__mmio_wakelock_post(display, reg, mmio_flags);
> >  
> >  	return val;
> > @@ -200,10 +220,14 @@ static __always_inline void
> >  __intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
> >  		 const unsigned int mmio_flags)
> >  {
> > +	unsigned long irqflags;
> > +
> >  	__mmio_wakelock_pre(display, reg, mmio_flags);
> > +	__mmio_lock_pre(display, &irqflags, mmio_flags);
> >  
> >  	intel_uncore_write(__to_uncore(display), reg, val);
> >  
> > +	__mmio_lock_post(display, irqflags, mmio_flags);
> >  	__mmio_wakelock_post(display, reg, mmio_flags);
> >  }
> >  
> > @@ -226,6 +250,25 @@ static const struct intel_mmio_funcs i9xx_mmio_funcs = {
> >  	.write = i9xx_mmio_write,
> >  };
> >  
> > +#define SNB_MMIO_FLAGS __MMIO_LOCK
> > +
> > +static u32 snb_mmio_read(struct intel_display *display, intel_reg_t reg)
> > +{
> > +	return __intel_de_read(display, reg, SNB_MMIO_FLAGS);
> > +}
> > +
> > +static void snb_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
> > +{
> > +	__intel_de_write(display, reg, val, SNB_MMIO_FLAGS);
> > +}
> > +
> > +#undef SNB_MMIO_FLAGS
> > +
> > +static const struct intel_mmio_funcs snb_mmio_funcs = {
> > +	.read = snb_mmio_read,
> > +	.write = snb_mmio_write,
> > +};
> > +
> >  #define LNL_MMIO_FLAGS __MMIO_WAKELOCK
> >  
> >  static u32 lnl_mmio_read(struct intel_display *display, intel_reg_t reg)
> > @@ -245,12 +288,30 @@ static const struct intel_mmio_funcs lnl_mmio_funcs = {
> >  	.write = lnl_mmio_write,
> >  };
> >  
> > +static bool driver_is_i915(void)
> > +{
> > +#ifdef I915
> > +	return true;
> > +#else
> > +	return false;
> > +#endif
> > +}
> 
> Ugh. Can we just not add this, because it needs to go real soon now
> anyway? Or do you already have patches in your tree removing this after
> some juggle?

One could just kill it now, but that will bring the lock and
unclaimed register detection to xe. I didn't want to do such
a drastic change in this ones series.

> 
> > +
> >  void intel_de_init(struct intel_display *display)
> >  {
> >  	display->mmio.uncore = to_intel_uncore(display->drm);
> >  
> > -	if (DISPLAY_VER(display) >= 20)
> > -		display->mmio.funcs = &lnl_mmio_funcs;
> > -	else
> > -		display->mmio.funcs = &i9xx_mmio_funcs;
> > +	spin_lock_init(&display->mmio.lock);
> > +
> > +	if (driver_is_i915()) {
> > +		if (DISPLAY_VER(display) >= 6)
> > +			display->mmio.funcs = &snb_mmio_funcs;
> > +		else
> > +			display->mmio.funcs = &i9xx_mmio_funcs;
> > +	} else {
> > +		if (DISPLAY_VER(display) >= 20)
> > +			display->mmio.funcs = &lnl_mmio_funcs;
> > +		else
> > +			display->mmio.funcs = &i9xx_mmio_funcs;
> > +	}
> 
> If we temporarily need driver_is_i915() for the non-functional iterative
> approach, seems like a different arrangement of the if ladder would be
> benefitial for the eventual removal of driver_is_i915(), maybe something
> like:
> 
> 	if (DISPLAY_VER(display) >= 20)
> 		display->mmio.funcs = &lnl_mmio_funcs;
> 	else if (!driver_is_i915())
> 		display->mmio.funcs = &i9xx_mmio_funcs;
> 	else if (display->platform.valleyview || display->platform.cherryview)
> 		display->mmio.funcs = &vlv_mmio_funcs;
> 	else if (DISPLAY_VER(display) >= 7)
> 		display->mmio.funcs = &ivb_mmio_funcs;
> 	else if (DISPLAY_VER(display) >= 6)
> 		display->mmio.funcs = &snb_mmio_funcs;
> 	else
> 		display->mmio.funcs = &i9xx_mmio_funcs;
> 
> (This includes changes from later patches.)

Feels like that makes the driver difference really hard to see, so
a casual reading of the code may give one the wrong impression of
what is happening. But I'll not die on that hill, so can go with
the single if ladder if you prefer. It should be a fairly short lived
state of affairs anyway.

> 
> I guess I'd like to see the decisions here (and in the vblank code) be
> based on platforms rather than driver, even though there's some overlap.

The driver difference will go away eventually. That said, I need
to have a real look at the vblank code's use of the lock to figure
out what to about that part. Might be I just end up removing the lock
there.

> 
> >  }
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> > index 3a48119f7890..aded2af8c92a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > @@ -533,6 +533,15 @@ struct intel_display {
> >  	} modeset;
> >  
> >  	struct {
> > +		/*
> > +		 * Simultaneous accesses to the same cacheline of
> > +		 * registers may hang IVB/HSW systems. This lock
> > +		 * serializes all display register accesses done
> > +		 * using intel_de_{read,write}(), but not those
> > +		 * done using intel_de_{read,write}_fw().
> > +		 */
> > +		spinlock_t lock;
> > +
> 
> I guess the comment begs the question why are we doing the locking also
> on display < 20? Just because the lock is (ab)used for other purposes as
> well?

The reason is that i915 has always used the lock on SNB+, so
we simply have no empirical data to tell us whether the more
recent platforms might still suffer from the same issue that
was observed on IVB/HSW before the lock was introduced.

I did a quick test run with the old 'xonotic + old version of
intel_gpu_top' reproducer, and sure enough IVB/HSW hang within
a reasonable amount of time. I also left that running on SNB 
and BDW for most of the day without hitting the hang. So I guess
that might be an indication that the problem is indeed real
but limited to IVB/HSW. Unfortunately the hsd is long gone
so I can't actually check what conclusions they reached there.

So my plan is to start by playing it safe without major
changes to the locking behaviour. And then follow up with
(easily revertable) changes to remove the lock from platforms
that we suspect don't need it.

But I also still need to figure out if making the unclaimed
register detection lockless is feasible. Otherwise we'll
be stuck with the lock for all HSW+ regardless of any
hardware issues.

> 
> >  		struct intel_uncore *uncore;
> >  		const struct intel_mmio_funcs *funcs;
> >  	} mmio;
> > diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> > index 1d4753605675..fc9d1e14ec87 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> > @@ -281,10 +281,6 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
> >  }
> >  
> >  /*
> > - * The uncore version of the spin lock functions is used to decide
> > - * whether we need to lock the uncore lock or not.  This is only
> > - * needed in i915, not in Xe.
> > - *
> >   * This lock in i915 is needed because some old platforms (at least
> >   * IVB and possibly HSW as well), which are not supported in Xe, need
> >   * all register accesses to the same cacheline to be serialized,
> > @@ -292,17 +288,15 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
> >   */
> >  #ifdef I915
> >  static void intel_vblank_section_enter(struct intel_display *display)
> > -	__acquires(uncore->lock)
> > +	__acquires(display->mmio.lock)
> >  {
> > -	struct intel_uncore *uncore = to_intel_uncore(display->drm);
> > -	spin_lock(&uncore->lock);
> > +	spin_lock(&display->mmio.lock);
> >  }
> >  
> >  static void intel_vblank_section_exit(struct intel_display *display)
> > -	__releases(uncore->lock)
> > +	__releases(display->mmio.lock)
> >  {
> > -	struct intel_uncore *uncore = to_intel_uncore(display->drm);
> > -	spin_unlock(&uncore->lock);
> > +	spin_unlock(&display->mmio.lock);
> >  }
> >  #else
> >  static void intel_vblank_section_enter(struct intel_display *display)
> > @@ -550,7 +544,7 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
> >  	 * consistent state during fastset seamless refresh rate changes.
> >  	 *
> >  	 * vblank_time_lock takes care of all drm_vblank.c stuff, and
> > -	 * uncore.lock takes care of __intel_get_crtc_scanline() which
> > +	 * display->mmio.lock takes care of __intel_get_crtc_scanline() which
> >  	 * may get called elsewhere as well.
> >  	 *
> >  	 * TODO maybe just protect everything (including
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH 5/9] drm/i915/de: Introduce display->mmio.lock

[Jani Nikula]

On Thu, 05 Nov 2026, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Nov 05, 2026 at 11:32:25AM +0200, Jani Nikula wrote:
>> On Thu, 05 Nov 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > Introduce our own display specific mmio.lock, and wrap
>> > the more expensive non-fw register accesses with it. And
>> > everything that explicitly takes the uncore.lock currently,
>> > switch over to mmio.lock as well.
>> >
>> > This will preserve the same serialization behavior between
>> > display registers as the uncore.lock is currently providing.
>> > Once uncore.lock has actually been eliminated from display
>> > registers (not the case yet) display vs. non-display
>> > register accesses could happen in parallel. But that should
>> > be fine since generally the registers for different hardware
>> > units don't live on the same cacheline, so even concerns
>> > about parallel accesses to the same cacheline potentially
>> > hanging the machine (on IVB/HSW) should be assuaged.
>> >
>> > Currently uncore.lock usage is limited to SNB+ on i915.
>> > The xe driver, and older platforms on the i915 driver
>> > don't use uncore.lock. Follow the same rule for the mmio.lock
>> > initially.
>> >
>> > With this we now end up with a double lock, or even a
>> > triple lock due to i915's mmio debug lock. But we'll eliminate
>> > the extra locks shortly. The end goal is either just mmio.lock
>> > or no locks whatsoever. Well, ignoring the DMC wakelock stuff
>> > that uses an additional lock as well.
>> >
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/i9xx_wm.c        |  9 ++-
>> >  drivers/gpu/drm/i915/display/intel_de.c       | 69 +++++++++++++++++--
>> >  .../gpu/drm/i915/display/intel_display_core.h |  9 +++
>> >  drivers/gpu/drm/i915/display/intel_vblank.c   | 16 ++---
>> >  4 files changed, 83 insertions(+), 20 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> > index 0233f5053d95..46bfada7c060 100644
>> > --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
>> > +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> > @@ -1863,7 +1863,6 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>> >  				   struct intel_crtc *crtc)
>> >  {
>> >  	struct intel_display *display = to_intel_display(crtc);
>> > -	struct intel_uncore *uncore = to_intel_uncore(display->drm);
>> >  	const struct intel_crtc_state *crtc_state =
>> >  		intel_atomic_get_new_crtc_state(state, crtc);
>> >  	const struct vlv_fifo_state *fifo_state =
>> > @@ -1884,15 +1883,15 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>> >  	trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
>> >  
>> >  	/*
>> > -	 * uncore.lock serves a double purpose here. It allows us to
>> > -	 * use the less expensive I915_{READ,WRITE}_FW() functions, and
>> > +	 * display->mmio.lock serves a double purpose here. It allows us to
>> > +	 * use the less expensive intel_de_{read,write}_fw() functions, and
>> >  	 * it protects the DSPARB registers from getting clobbered by
>> >  	 * parallel updates from multiple pipes.
>> >  	 *
>> >  	 * intel_pipe_update_start() has already disabled interrupts
>> >  	 * for us, so a plain spin_lock() is sufficient here.
>> >  	 */
>> > -	spin_lock(&uncore->lock);
>> > +	spin_lock(&display->mmio.lock);
>> >  
>> >  	switch (crtc->pipe) {
>> >  	case PIPE_A:
>> > @@ -1952,7 +1951,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>> >  
>> >  	intel_de_read_fw(display, DSPARB(display));
>> >  
>> > -	spin_unlock(&uncore->lock);
>> > +	spin_unlock(&display->mmio.lock);
>> >  }
>> >  
>> >  #undef VLV_FIFO
>> > diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
>> > index 66de0d6be569..8b7a4e696ff9 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_de.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_de.c
>> > @@ -164,6 +164,7 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
>> >  }
>> >  
>> >  #define __MMIO_WAKELOCK		BIT(0)
>> > +#define __MMIO_LOCK		BIT(1)
>> >  
>> >  static __always_inline void
>> >  __mmio_wakelock_pre(struct intel_display *display, intel_reg_t reg,
>> > @@ -181,16 +182,35 @@ __mmio_wakelock_post(struct intel_display *display, intel_reg_t reg,
>> >  		intel_dmc_wl_put(display, reg);
>> >  }
>> >  
>> > +static __always_inline void
>> > +__mmio_lock_pre(struct intel_display *display, unsigned long *irqflags,
>> > +		const unsigned int mmio_flags)
>> > +{
>> > +	if (mmio_flags & __MMIO_LOCK)
>> > +		spin_lock_irqsave(&display->mmio.lock, *irqflags);
>> > +}
>> > +
>> > +static __always_inline void
>> > +__mmio_lock_post(struct intel_display *display, unsigned long irqflags,
>> > +		 const unsigned int mmio_flags)
>> > +{
>> > +	if (mmio_flags & __MMIO_LOCK)
>> > +		spin_unlock_irqrestore(&display->mmio.lock, irqflags);
>> > +}
>> > +
>> >  static __always_inline u32
>> >  __intel_de_read(struct intel_display *display, intel_reg_t reg,
>> >  		const unsigned int mmio_flags)
>> >  {
>> > +	unsigned long irqflags;
>> >  	u32 val;
>> >  
>> >  	__mmio_wakelock_pre(display, reg, mmio_flags);
>> > +	__mmio_lock_pre(display, &irqflags, mmio_flags);
>> >  
>> >  	val = intel_uncore_read(__to_uncore(display), reg);
>> >  
>> > +	__mmio_lock_post(display, irqflags, mmio_flags);
>> >  	__mmio_wakelock_post(display, reg, mmio_flags);
>> >  
>> >  	return val;
>> > @@ -200,10 +220,14 @@ static __always_inline void
>> >  __intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
>> >  		 const unsigned int mmio_flags)
>> >  {
>> > +	unsigned long irqflags;
>> > +
>> >  	__mmio_wakelock_pre(display, reg, mmio_flags);
>> > +	__mmio_lock_pre(display, &irqflags, mmio_flags);
>> >  
>> >  	intel_uncore_write(__to_uncore(display), reg, val);
>> >  
>> > +	__mmio_lock_post(display, irqflags, mmio_flags);
>> >  	__mmio_wakelock_post(display, reg, mmio_flags);
>> >  }
>> >  
>> > @@ -226,6 +250,25 @@ static const struct intel_mmio_funcs i9xx_mmio_funcs = {
>> >  	.write = i9xx_mmio_write,
>> >  };
>> >  
>> > +#define SNB_MMIO_FLAGS __MMIO_LOCK
>> > +
>> > +static u32 snb_mmio_read(struct intel_display *display, intel_reg_t reg)
>> > +{
>> > +	return __intel_de_read(display, reg, SNB_MMIO_FLAGS);
>> > +}
>> > +
>> > +static void snb_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
>> > +{
>> > +	__intel_de_write(display, reg, val, SNB_MMIO_FLAGS);
>> > +}
>> > +
>> > +#undef SNB_MMIO_FLAGS
>> > +
>> > +static const struct intel_mmio_funcs snb_mmio_funcs = {
>> > +	.read = snb_mmio_read,
>> > +	.write = snb_mmio_write,
>> > +};
>> > +
>> >  #define LNL_MMIO_FLAGS __MMIO_WAKELOCK
>> >  
>> >  static u32 lnl_mmio_read(struct intel_display *display, intel_reg_t reg)
>> > @@ -245,12 +288,30 @@ static const struct intel_mmio_funcs lnl_mmio_funcs = {
>> >  	.write = lnl_mmio_write,
>> >  };
>> >  
>> > +static bool driver_is_i915(void)
>> > +{
>> > +#ifdef I915
>> > +	return true;
>> > +#else
>> > +	return false;
>> > +#endif
>> > +}
>> 
>> Ugh. Can we just not add this, because it needs to go real soon now
>> anyway? Or do you already have patches in your tree removing this after
>> some juggle?
>
> One could just kill it now, but that will bring the lock and
> unclaimed register detection to xe. I didn't want to do such
> a drastic change in this ones series.
>
>> 
>> > +
>> >  void intel_de_init(struct intel_display *display)
>> >  {
>> >  	display->mmio.uncore = to_intel_uncore(display->drm);
>> >  
>> > -	if (DISPLAY_VER(display) >= 20)
>> > -		display->mmio.funcs = &lnl_mmio_funcs;
>> > -	else
>> > -		display->mmio.funcs = &i9xx_mmio_funcs;
>> > +	spin_lock_init(&display->mmio.lock);
>> > +
>> > +	if (driver_is_i915()) {
>> > +		if (DISPLAY_VER(display) >= 6)
>> > +			display->mmio.funcs = &snb_mmio_funcs;
>> > +		else
>> > +			display->mmio.funcs = &i9xx_mmio_funcs;
>> > +	} else {
>> > +		if (DISPLAY_VER(display) >= 20)
>> > +			display->mmio.funcs = &lnl_mmio_funcs;
>> > +		else
>> > +			display->mmio.funcs = &i9xx_mmio_funcs;
>> > +	}
>> 
>> If we temporarily need driver_is_i915() for the non-functional iterative
>> approach, seems like a different arrangement of the if ladder would be
>> benefitial for the eventual removal of driver_is_i915(), maybe something
>> like:
>> 
>> 	if (DISPLAY_VER(display) >= 20)
>> 		display->mmio.funcs = &lnl_mmio_funcs;
>> 	else if (!driver_is_i915())
>> 		display->mmio.funcs = &i9xx_mmio_funcs;
>> 	else if (display->platform.valleyview || display->platform.cherryview)
>> 		display->mmio.funcs = &vlv_mmio_funcs;
>> 	else if (DISPLAY_VER(display) >= 7)
>> 		display->mmio.funcs = &ivb_mmio_funcs;
>> 	else if (DISPLAY_VER(display) >= 6)
>> 		display->mmio.funcs = &snb_mmio_funcs;
>> 	else
>> 		display->mmio.funcs = &i9xx_mmio_funcs;
>> 
>> (This includes changes from later patches.)
>
> Feels like that makes the driver difference really hard to see, so
> a casual reading of the code may give one the wrong impression of
> what is happening. But I'll not die on that hill, so can go with
> the single if ladder if you prefer. It should be a fairly short lived
> state of affairs anyway.

Okay, thanks for the explanations. This is not the hill I'll die on
either, so up to you. As long as you guarantee it's short lived, and
maybe mention it in the commit message.

BR,
Jani.


>
>> 
>> I guess I'd like to see the decisions here (and in the vblank code) be
>> based on platforms rather than driver, even though there's some overlap.
>
> The driver difference will go away eventually. That said, I need
> to have a real look at the vblank code's use of the lock to figure
> out what to about that part. Might be I just end up removing the lock
> there.
>
>> 
>> >  }
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>> > index 3a48119f7890..aded2af8c92a 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> > @@ -533,6 +533,15 @@ struct intel_display {
>> >  	} modeset;
>> >  
>> >  	struct {
>> > +		/*
>> > +		 * Simultaneous accesses to the same cacheline of
>> > +		 * registers may hang IVB/HSW systems. This lock
>> > +		 * serializes all display register accesses done
>> > +		 * using intel_de_{read,write}(), but not those
>> > +		 * done using intel_de_{read,write}_fw().
>> > +		 */
>> > +		spinlock_t lock;
>> > +
>> 
>> I guess the comment begs the question why are we doing the locking also
>> on display < 20? Just because the lock is (ab)used for other purposes as
>> well?
>
> The reason is that i915 has always used the lock on SNB+, so
> we simply have no empirical data to tell us whether the more
> recent platforms might still suffer from the same issue that
> was observed on IVB/HSW before the lock was introduced.
>
> I did a quick test run with the old 'xonotic + old version of
> intel_gpu_top' reproducer, and sure enough IVB/HSW hang within
> a reasonable amount of time. I also left that running on SNB 
> and BDW for most of the day without hitting the hang. So I guess
> that might be an indication that the problem is indeed real
> but limited to IVB/HSW. Unfortunately the hsd is long gone
> so I can't actually check what conclusions they reached there.
>
> So my plan is to start by playing it safe without major
> changes to the locking behaviour. And then follow up with
> (easily revertable) changes to remove the lock from platforms
> that we suspect don't need it.
>
> But I also still need to figure out if making the unclaimed
> register detection lockless is feasible. Otherwise we'll
> be stuck with the lock for all HSW+ regardless of any
> hardware issues.
>
>> 
>> >  		struct intel_uncore *uncore;
>> >  		const struct intel_mmio_funcs *funcs;
>> >  	} mmio;
>> > diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
>> > index 1d4753605675..fc9d1e14ec87 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_vblank.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
>> > @@ -281,10 +281,6 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>> >  }
>> >  
>> >  /*
>> > - * The uncore version of the spin lock functions is used to decide
>> > - * whether we need to lock the uncore lock or not.  This is only
>> > - * needed in i915, not in Xe.
>> > - *
>> >   * This lock in i915 is needed because some old platforms (at least
>> >   * IVB and possibly HSW as well), which are not supported in Xe, need
>> >   * all register accesses to the same cacheline to be serialized,
>> > @@ -292,17 +288,15 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>> >   */
>> >  #ifdef I915
>> >  static void intel_vblank_section_enter(struct intel_display *display)
>> > -	__acquires(uncore->lock)
>> > +	__acquires(display->mmio.lock)
>> >  {
>> > -	struct intel_uncore *uncore = to_intel_uncore(display->drm);
>> > -	spin_lock(&uncore->lock);
>> > +	spin_lock(&display->mmio.lock);
>> >  }
>> >  
>> >  static void intel_vblank_section_exit(struct intel_display *display)
>> > -	__releases(uncore->lock)
>> > +	__releases(display->mmio.lock)
>> >  {
>> > -	struct intel_uncore *uncore = to_intel_uncore(display->drm);
>> > -	spin_unlock(&uncore->lock);
>> > +	spin_unlock(&display->mmio.lock);
>> >  }
>> >  #else
>> >  static void intel_vblank_section_enter(struct intel_display *display)
>> > @@ -550,7 +544,7 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
>> >  	 * consistent state during fastset seamless refresh rate changes.
>> >  	 *
>> >  	 * vblank_time_lock takes care of all drm_vblank.c stuff, and
>> > -	 * uncore.lock takes care of __intel_get_crtc_scanline() which
>> > +	 * display->mmio.lock takes care of __intel_get_crtc_scanline() which
>> >  	 * may get called elsewhere as well.
>> >  	 *
>> >  	 * TODO maybe just protect everything (including
>> 
>> -- 
>> Jani Nikula, Intel

-- 
Jani Nikula, Intel

Re: [PATCH 5/9] drm/i915/de: Introduce display->mmio.lock

[Jani Nikula]

On Thu, 05 Nov 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Introduce our own display specific mmio.lock, and wrap
> the more expensive non-fw register accesses with it. And
> everything that explicitly takes the uncore.lock currently,
> switch over to mmio.lock as well.
>
> This will preserve the same serialization behavior between
> display registers as the uncore.lock is currently providing.
> Once uncore.lock has actually been eliminated from display
> registers (not the case yet) display vs. non-display
> register accesses could happen in parallel. But that should
> be fine since generally the registers for different hardware
> units don't live on the same cacheline, so even concerns
> about parallel accesses to the same cacheline potentially
> hanging the machine (on IVB/HSW) should be assuaged.
>
> Currently uncore.lock usage is limited to SNB+ on i915.
> The xe driver, and older platforms on the i915 driver
> don't use uncore.lock. Follow the same rule for the mmio.lock
> initially.
>
> With this we now end up with a double lock, or even a
> triple lock due to i915's mmio debug lock. But we'll eliminate
> the extra locks shortly. The end goal is either just mmio.lock
> or no locks whatsoever. Well, ignoring the DMC wakelock stuff
> that uses an additional lock as well.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/i9xx_wm.c        |  9 ++-
>  drivers/gpu/drm/i915/display/intel_de.c       | 69 +++++++++++++++++--
>  .../gpu/drm/i915/display/intel_display_core.h |  9 +++
>  drivers/gpu/drm/i915/display/intel_vblank.c   | 16 ++---
>  4 files changed, 83 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 0233f5053d95..46bfada7c060 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -1863,7 +1863,6 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  				   struct intel_crtc *crtc)
>  {
>  	struct intel_display *display = to_intel_display(crtc);
> -	struct intel_uncore *uncore = to_intel_uncore(display->drm);
>  	const struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	const struct vlv_fifo_state *fifo_state =
> @@ -1884,15 +1883,15 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  	trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
>  
>  	/*
> -	 * uncore.lock serves a double purpose here. It allows us to
> -	 * use the less expensive I915_{READ,WRITE}_FW() functions, and
> +	 * display->mmio.lock serves a double purpose here. It allows us to
> +	 * use the less expensive intel_de_{read,write}_fw() functions, and
>  	 * it protects the DSPARB registers from getting clobbered by
>  	 * parallel updates from multiple pipes.
>  	 *
>  	 * intel_pipe_update_start() has already disabled interrupts
>  	 * for us, so a plain spin_lock() is sufficient here.
>  	 */
> -	spin_lock(&uncore->lock);
> +	spin_lock(&display->mmio.lock);
>  
>  	switch (crtc->pipe) {
>  	case PIPE_A:
> @@ -1952,7 +1951,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  
>  	intel_de_read_fw(display, DSPARB(display));
>  
> -	spin_unlock(&uncore->lock);
> +	spin_unlock(&display->mmio.lock);
>  }
>  
>  #undef VLV_FIFO
> diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> index 66de0d6be569..8b7a4e696ff9 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.c
> +++ b/drivers/gpu/drm/i915/display/intel_de.c
> @@ -164,6 +164,7 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
>  }
>  
>  #define __MMIO_WAKELOCK		BIT(0)
> +#define __MMIO_LOCK		BIT(1)
>  
>  static __always_inline void
>  __mmio_wakelock_pre(struct intel_display *display, intel_reg_t reg,
> @@ -181,16 +182,35 @@ __mmio_wakelock_post(struct intel_display *display, intel_reg_t reg,
>  		intel_dmc_wl_put(display, reg);
>  }
>  
> +static __always_inline void
> +__mmio_lock_pre(struct intel_display *display, unsigned long *irqflags,
> +		const unsigned int mmio_flags)
> +{
> +	if (mmio_flags & __MMIO_LOCK)
> +		spin_lock_irqsave(&display->mmio.lock, *irqflags);
> +}
> +
> +static __always_inline void
> +__mmio_lock_post(struct intel_display *display, unsigned long irqflags,
> +		 const unsigned int mmio_flags)
> +{
> +	if (mmio_flags & __MMIO_LOCK)
> +		spin_unlock_irqrestore(&display->mmio.lock, irqflags);
> +}
> +
>  static __always_inline u32
>  __intel_de_read(struct intel_display *display, intel_reg_t reg,
>  		const unsigned int mmio_flags)
>  {
> +	unsigned long irqflags;
>  	u32 val;
>  
>  	__mmio_wakelock_pre(display, reg, mmio_flags);
> +	__mmio_lock_pre(display, &irqflags, mmio_flags);
>  
>  	val = intel_uncore_read(__to_uncore(display), reg);
>  
> +	__mmio_lock_post(display, irqflags, mmio_flags);
>  	__mmio_wakelock_post(display, reg, mmio_flags);
>  
>  	return val;
> @@ -200,10 +220,14 @@ static __always_inline void
>  __intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
>  		 const unsigned int mmio_flags)
>  {
> +	unsigned long irqflags;
> +
>  	__mmio_wakelock_pre(display, reg, mmio_flags);
> +	__mmio_lock_pre(display, &irqflags, mmio_flags);
>  
>  	intel_uncore_write(__to_uncore(display), reg, val);
>  
> +	__mmio_lock_post(display, irqflags, mmio_flags);
>  	__mmio_wakelock_post(display, reg, mmio_flags);
>  }
>  
> @@ -226,6 +250,25 @@ static const struct intel_mmio_funcs i9xx_mmio_funcs = {
>  	.write = i9xx_mmio_write,
>  };
>  
> +#define SNB_MMIO_FLAGS __MMIO_LOCK
> +
> +static u32 snb_mmio_read(struct intel_display *display, intel_reg_t reg)
> +{
> +	return __intel_de_read(display, reg, SNB_MMIO_FLAGS);
> +}
> +
> +static void snb_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
> +{
> +	__intel_de_write(display, reg, val, SNB_MMIO_FLAGS);
> +}
> +
> +#undef SNB_MMIO_FLAGS
> +
> +static const struct intel_mmio_funcs snb_mmio_funcs = {
> +	.read = snb_mmio_read,
> +	.write = snb_mmio_write,
> +};
> +
>  #define LNL_MMIO_FLAGS __MMIO_WAKELOCK
>  
>  static u32 lnl_mmio_read(struct intel_display *display, intel_reg_t reg)
> @@ -245,12 +288,30 @@ static const struct intel_mmio_funcs lnl_mmio_funcs = {
>  	.write = lnl_mmio_write,
>  };
>  
> +static bool driver_is_i915(void)
> +{
> +#ifdef I915
> +	return true;
> +#else
> +	return false;
> +#endif
> +}
> +
>  void intel_de_init(struct intel_display *display)
>  {
>  	display->mmio.uncore = to_intel_uncore(display->drm);
>  
> -	if (DISPLAY_VER(display) >= 20)
> -		display->mmio.funcs = &lnl_mmio_funcs;
> -	else
> -		display->mmio.funcs = &i9xx_mmio_funcs;
> +	spin_lock_init(&display->mmio.lock);
> +
> +	if (driver_is_i915()) {
> +		if (DISPLAY_VER(display) >= 6)
> +			display->mmio.funcs = &snb_mmio_funcs;
> +		else
> +			display->mmio.funcs = &i9xx_mmio_funcs;
> +	} else {
> +		if (DISPLAY_VER(display) >= 20)
> +			display->mmio.funcs = &lnl_mmio_funcs;
> +		else
> +			display->mmio.funcs = &i9xx_mmio_funcs;
> +	}
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 3a48119f7890..aded2af8c92a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -533,6 +533,15 @@ struct intel_display {
>  	} modeset;
>  
>  	struct {
> +		/*
> +		 * Simultaneous accesses to the same cacheline of
> +		 * registers may hang IVB/HSW systems. This lock
> +		 * serializes all display register accesses done
> +		 * using intel_de_{read,write}(), but not those
> +		 * done using intel_de_{read,write}_fw().
> +		 */
> +		spinlock_t lock;
> +
>  		struct intel_uncore *uncore;
>  		const struct intel_mmio_funcs *funcs;
>  	} mmio;
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 1d4753605675..fc9d1e14ec87 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -281,10 +281,6 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>  }
>  
>  /*
> - * The uncore version of the spin lock functions is used to decide
> - * whether we need to lock the uncore lock or not.  This is only
> - * needed in i915, not in Xe.
> - *
>   * This lock in i915 is needed because some old platforms (at least
>   * IVB and possibly HSW as well), which are not supported in Xe, need
>   * all register accesses to the same cacheline to be serialized,
> @@ -292,17 +288,15 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>   */
>  #ifdef I915
>  static void intel_vblank_section_enter(struct intel_display *display)
> -	__acquires(uncore->lock)
> +	__acquires(display->mmio.lock)
>  {
> -	struct intel_uncore *uncore = to_intel_uncore(display->drm);
> -	spin_lock(&uncore->lock);
> +	spin_lock(&display->mmio.lock);
>  }
>  
>  static void intel_vblank_section_exit(struct intel_display *display)
> -	__releases(uncore->lock)
> +	__releases(display->mmio.lock)
>  {
> -	struct intel_uncore *uncore = to_intel_uncore(display->drm);
> -	spin_unlock(&uncore->lock);
> +	spin_unlock(&display->mmio.lock);
>  }
>  #else
>  static void intel_vblank_section_enter(struct intel_display *display)
> @@ -550,7 +544,7 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
>  	 * consistent state during fastset seamless refresh rate changes.
>  	 *
>  	 * vblank_time_lock takes care of all drm_vblank.c stuff, and
> -	 * uncore.lock takes care of __intel_get_crtc_scanline() which
> +	 * display->mmio.lock takes care of __intel_get_crtc_scanline() which
>  	 * may get called elsewhere as well.
>  	 *
>  	 * TODO maybe just protect everything (including

-- 
Jani Nikula, Intel

[PATCH 6/9] drm/i915/uncore: Don't meddle with mmio debug upon user forcewake

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently when userspace takes the forcewake via debugfs, the
kernel will stop looking for unclaimed mmio accesses. That link
is kinda weird since forcewake is for GT stuff and unclaimed
mmio detection is for display stuff.

Just kill the mmio debug suspend/resume upon user forcewake.
One should almost always use IGT_NO_FORCEWAKE=1 when poking
at display register from userspace anyway so as to not
perturb the rest of the system.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 46 ++---------------------------
 drivers/gpu/drm/i915/intel_uncore.h |  2 --
 2 files changed, 2 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index e360e4f9d9a2..abd695e880c1 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -65,41 +65,6 @@ intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915)
 	i915->uncore.debug = &i915->mmio_debug;
 }
 
-static void mmio_debug_suspend(struct intel_uncore *uncore)
-{
-	if (!uncore->debug)
-		return;
-
-	spin_lock(&uncore->debug->lock);
-
-	/* Save and disable mmio debugging for the user bypass */
-	if (!uncore->debug->suspend_count++) {
-		uncore->debug->saved_mmio_check = uncore->debug->unclaimed_mmio_check;
-		uncore->debug->unclaimed_mmio_check = 0;
-	}
-
-	spin_unlock(&uncore->debug->lock);
-}
-
-static bool check_for_unclaimed_mmio(struct intel_uncore *uncore);
-
-static void mmio_debug_resume(struct intel_uncore *uncore)
-{
-	if (!uncore->debug)
-		return;
-
-	spin_lock(&uncore->debug->lock);
-
-	if (!--uncore->debug->suspend_count)
-		uncore->debug->unclaimed_mmio_check = uncore->debug->saved_mmio_check;
-
-	if (check_for_unclaimed_mmio(uncore))
-		drm_info(&uncore->i915->drm,
-			 "Invalid mmio detected during user access\n");
-
-	spin_unlock(&uncore->debug->lock);
-}
-
 static const char * const forcewake_domain_names[] = {
 	"render",
 	"gt",
@@ -598,9 +563,6 @@ check_for_unclaimed_mmio(struct intel_uncore *uncore)
 
 	lockdep_assert_held(&uncore->debug->lock);
 
-	if (uncore->debug->suspend_count)
-		return false;
-
 	if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
 		ret |= fpga_check_for_unclaimed_mmio(uncore);
 
@@ -733,10 +695,8 @@ void intel_uncore_forcewake_get(struct intel_uncore *uncore,
 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
 {
 	spin_lock_irq(&uncore->lock);
-	if (!uncore->user_forcewake_count++) {
+	if (!uncore->user_forcewake_count++)
 		intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
-		mmio_debug_suspend(uncore);
-	}
 	spin_unlock_irq(&uncore->lock);
 }
 
@@ -750,10 +710,8 @@ void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
 {
 	spin_lock_irq(&uncore->lock);
-	if (!--uncore->user_forcewake_count) {
-		mmio_debug_resume(uncore);
+	if (!--uncore->user_forcewake_count)
 		intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
-	}
 	spin_unlock_irq(&uncore->lock);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index fafc2ca9a237..4ec7c545d04e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -42,8 +42,6 @@ struct intel_gt;
 struct intel_uncore_mmio_debug {
 	spinlock_t lock; /** lock is also taken in irq contexts. */
 	int unclaimed_mmio_check;
-	int saved_mmio_check;
-	u32 suspend_count;
 };
 
 enum forcewake_domain_id {
-- 
2.56.0

Re: [PATCH 6/9] drm/i915/uncore: Don't meddle with mmio debug upon user forcewake

[Jani Nikula]

On Thu, 05 Nov 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently when userspace takes the forcewake via debugfs, the
> kernel will stop looking for unclaimed mmio accesses. That link
> is kinda weird since forcewake is for GT stuff and unclaimed
> mmio detection is for display stuff.
>
> Just kill the mmio debug suspend/resume upon user forcewake.
> One should almost always use IGT_NO_FORCEWAKE=1 when poking
> at display register from userspace anyway so as to not
> perturb the rest of the system.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 46 ++---------------------------
>  drivers/gpu/drm/i915/intel_uncore.h |  2 --
>  2 files changed, 2 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index e360e4f9d9a2..abd695e880c1 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -65,41 +65,6 @@ intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915)
>  	i915->uncore.debug = &i915->mmio_debug;
>  }
>  
> -static void mmio_debug_suspend(struct intel_uncore *uncore)
> -{
> -	if (!uncore->debug)
> -		return;
> -
> -	spin_lock(&uncore->debug->lock);
> -
> -	/* Save and disable mmio debugging for the user bypass */
> -	if (!uncore->debug->suspend_count++) {
> -		uncore->debug->saved_mmio_check = uncore->debug->unclaimed_mmio_check;
> -		uncore->debug->unclaimed_mmio_check = 0;
> -	}
> -
> -	spin_unlock(&uncore->debug->lock);
> -}
> -
> -static bool check_for_unclaimed_mmio(struct intel_uncore *uncore);
> -
> -static void mmio_debug_resume(struct intel_uncore *uncore)
> -{
> -	if (!uncore->debug)
> -		return;
> -
> -	spin_lock(&uncore->debug->lock);
> -
> -	if (!--uncore->debug->suspend_count)
> -		uncore->debug->unclaimed_mmio_check = uncore->debug->saved_mmio_check;
> -
> -	if (check_for_unclaimed_mmio(uncore))
> -		drm_info(&uncore->i915->drm,
> -			 "Invalid mmio detected during user access\n");
> -
> -	spin_unlock(&uncore->debug->lock);
> -}
> -
>  static const char * const forcewake_domain_names[] = {
>  	"render",
>  	"gt",
> @@ -598,9 +563,6 @@ check_for_unclaimed_mmio(struct intel_uncore *uncore)
>  
>  	lockdep_assert_held(&uncore->debug->lock);
>  
> -	if (uncore->debug->suspend_count)
> -		return false;
> -
>  	if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
>  		ret |= fpga_check_for_unclaimed_mmio(uncore);
>  
> @@ -733,10 +695,8 @@ void intel_uncore_forcewake_get(struct intel_uncore *uncore,
>  void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
>  {
>  	spin_lock_irq(&uncore->lock);
> -	if (!uncore->user_forcewake_count++) {
> +	if (!uncore->user_forcewake_count++)
>  		intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
> -		mmio_debug_suspend(uncore);
> -	}
>  	spin_unlock_irq(&uncore->lock);
>  }
>  
> @@ -750,10 +710,8 @@ void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
>  void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
>  {
>  	spin_lock_irq(&uncore->lock);
> -	if (!--uncore->user_forcewake_count) {
> -		mmio_debug_resume(uncore);
> +	if (!--uncore->user_forcewake_count)
>  		intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
> -	}
>  	spin_unlock_irq(&uncore->lock);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index fafc2ca9a237..4ec7c545d04e 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -42,8 +42,6 @@ struct intel_gt;
>  struct intel_uncore_mmio_debug {
>  	spinlock_t lock; /** lock is also taken in irq contexts. */
>  	int unclaimed_mmio_check;
> -	int saved_mmio_check;
> -	u32 suspend_count;
>  };
>  
>  enum forcewake_domain_id {

-- 
Jani Nikula, Intel

[PATCH 7/9] drm/i915/de: Move unclaimed mmio detection into display code

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The FPGA_DBG/CLAIM_ER unclaimed mmio access detection only
works for display registers. Therefore checking it for GT
registers/etc is completely pointless. Hoist the whole thing
into the display code. Eventually we'll also want to hook this
up for xe, but for now we keep it i915 only to avoid too many
functional changes in one go.

Note that i915 used a separate spinlock to protect the
mmio debug tracking. But basically whenever it would grab that
lock it was already holding uncore.lock, so the double locking
was rather pointless. When moving this into the display code
we'll just protect it all with the same display mmio.lock that
already provides any needed serialization of register accesses.

This will of course speed up the non-fw GT register accesses
with mmio debug enabled since we never do the two extra
FPGA_DBG/CLAIM_ER reads for them.

Note that we do lose the FPGA_DBG!=0xffffffff sanity check for
non-display register accesses now. Possibly the GT side should
use some harmless GT register for that instead. But I didn't
bother looking for one at this time.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_de.c       | 175 +++++++++++++++-
 drivers/gpu/drm/i915/display/intel_de.h       |   3 +
 drivers/gpu/drm/i915/display/intel_display.c  |   3 +-
 .../gpu/drm/i915/display/intel_display_core.h |   7 +
 .../drm/i915/display/intel_display_driver.c   |  15 ++
 .../drm/i915/display/intel_display_driver.h   |   3 +
 .../drm/i915/display/intel_display_params.c   |   4 +
 .../drm/i915/display/intel_display_params.h   |   1 +
 .../gpu/drm/i915/display/intel_display_regs.h |   8 +
 drivers/gpu/drm/i915/i915_driver.c            |  12 +-
 drivers/gpu/drm/i915/i915_drv.h               |   1 -
 drivers/gpu/drm/i915/i915_params.c            |   4 -
 drivers/gpu/drm/i915/i915_params.h            |   1 -
 drivers/gpu/drm/i915/i915_reg.h               |   7 -
 drivers/gpu/drm/i915/intel_uncore.c           | 193 +-----------------
 drivers/gpu/drm/i915/intel_uncore.h           |  24 ---
 16 files changed, 222 insertions(+), 239 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
index 8b7a4e696ff9..0a51105e0fba 100644
--- a/drivers/gpu/drm/i915/display/intel_de.c
+++ b/drivers/gpu/drm/i915/display/intel_de.c
@@ -8,6 +8,7 @@
 #include <drm/drm_print.h>
 
 #include "intel_de.h"
+#include "intel_display_regs.h"
 
 static int intel_de_wait_for_register(struct intel_display *display,
 				      intel_reg_t reg, u32 mask, u32 value,
@@ -163,8 +164,127 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
 	return intel_uncore_read16(__to_uncore(display), reg);
 }
 
+static bool ivb_check_for_unclaimed_mmio(struct intel_display *display)
+{
+	u32 dbg;
+
+	dbg = intel_de_read_fw(display, FPGA_DBG);
+	if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
+		return false;
+
+	/*
+	 * Bugs in PCI programming (or failing hardware) can occasionally cause
+	 * us to lose access to the MMIO BAR.  When this happens, register
+	 * reads will come back with 0xFFFFFFFF for every register and things
+	 * go bad very quickly.  Let's try to detect that special case and at
+	 * least try to print a more informative message about what has
+	 * happened.
+	 *
+	 * During normal operation the FPGA_DBG register has several unused
+	 * bits that will always read back as 0's so we can use them as canaries
+	 * to recognize when MMIO accesses are just busted.
+	 */
+	if (unlikely(dbg == ~0))
+		drm_err(display->drm,
+			"Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n");
+
+	intel_de_write_fw(display, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+
+	return true;
+}
+
+static bool vlv_check_for_unclaimed_mmio(struct intel_display *display)
+{
+	u32 cer;
+
+	cer = intel_de_read_fw(display, CLAIM_ER);
+	if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
+		return false;
+
+	intel_de_write_fw(display, CLAIM_ER, CLAIM_ER_CLR);
+
+	return true;
+}
+
+static void check_unclaimed_mmio_pre(struct intel_display *display,
+				     intel_reg_t reg, bool write)
+{
+	lockdep_assert_held(&display->mmio.lock);
+
+	if (!display->params.mmio_debug)
+		return;
+
+	if (display->mmio.funcs->check_for_unclaimed_mmio(display))
+		drm_dbg_kms(display->drm,
+			    "Unclaimed access detected before %s register 0x%x\n",
+			    write ? "write to" : "read from",
+			    i915_mmio_reg_offset(reg));
+}
+
+static void check_unclaimed_mmio_post(struct intel_display *display,
+				      intel_reg_t reg, bool write)
+{
+	lockdep_assert_held(&display->mmio.lock);
+
+	if (!display->params.mmio_debug)
+		return;
+
+	if (drm_WARN(display->drm,
+		     display->mmio.funcs->check_for_unclaimed_mmio(display),
+		     "Unclaimed %s register 0x%x\n",
+		     write ? "write to" : "read from",
+		     i915_mmio_reg_offset(reg)))
+		/* Only report the first N failures */
+		display->params.mmio_debug--;
+}
+
+bool intel_de_unclaimed_mmio_detected(struct intel_display *display)
+{
+	bool ret;
+
+	if (!display->mmio.funcs->check_for_unclaimed_mmio)
+		return false;
+
+	spin_lock_irq(&display->mmio.lock);
+	ret = display->mmio.funcs->check_for_unclaimed_mmio(display);
+	spin_unlock_irq(&display->mmio.lock);
+
+	return ret;
+}
+
+bool intel_de_arm_unclaimed_mmio_detection(struct intel_display *display)
+{
+	bool ret = false;
+
+	if (!display->mmio.funcs->check_for_unclaimed_mmio)
+		return false;
+
+	spin_lock_irq(&display->mmio.lock);
+
+	if (display->mmio.unclaimed_mmio_check <= 0)
+		goto out;
+
+	if (display->mmio.funcs->check_for_unclaimed_mmio(display)) {
+		if (!display->params.mmio_debug) {
+			drm_dbg_kms(display->drm,
+				    "Unclaimed register detected, "
+				    "enabling oneshot unclaimed register reporting. "
+				    "Please use i915.mmio_debug=N for more information.\n");
+			display->params.mmio_debug++;
+		}
+		display->mmio.unclaimed_mmio_check--;
+		ret = true;
+	}
+
+out:
+	spin_unlock_irq(&display->mmio.lock);
+
+	return ret;
+}
+
 #define __MMIO_WAKELOCK		BIT(0)
 #define __MMIO_LOCK		BIT(1)
+#define __MMIO_UNCLAIMED	BIT(2)
 
 static __always_inline void
 __mmio_wakelock_pre(struct intel_display *display, intel_reg_t reg,
@@ -198,6 +318,22 @@ __mmio_lock_post(struct intel_display *display, unsigned long irqflags,
 		spin_unlock_irqrestore(&display->mmio.lock, irqflags);
 }
 
+static __always_inline void
+__mmio_unclaimed_pre(struct intel_display *display, intel_reg_t reg,
+		     const bool write, const unsigned int mmio_flags)
+{
+	if (mmio_flags & __MMIO_UNCLAIMED)
+		check_unclaimed_mmio_pre(display, reg, write);
+}
+
+static __always_inline void
+__mmio_unclaimed_post(struct intel_display *display, intel_reg_t reg,
+		      const bool write, const unsigned int mmio_flags)
+{
+	if (mmio_flags & __MMIO_UNCLAIMED)
+		check_unclaimed_mmio_post(display, reg, write);
+}
+
 static __always_inline u32
 __intel_de_read(struct intel_display *display, intel_reg_t reg,
 		const unsigned int mmio_flags)
@@ -207,9 +343,11 @@ __intel_de_read(struct intel_display *display, intel_reg_t reg,
 
 	__mmio_wakelock_pre(display, reg, mmio_flags);
 	__mmio_lock_pre(display, &irqflags, mmio_flags);
+	__mmio_unclaimed_pre(display, reg, false, mmio_flags);
 
 	val = intel_uncore_read(__to_uncore(display), reg);
 
+	__mmio_unclaimed_post(display, reg, false, mmio_flags);
 	__mmio_lock_post(display, irqflags, mmio_flags);
 	__mmio_wakelock_post(display, reg, mmio_flags);
 
@@ -224,9 +362,11 @@ __intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
 
 	__mmio_wakelock_pre(display, reg, mmio_flags);
 	__mmio_lock_pre(display, &irqflags, mmio_flags);
+	__mmio_unclaimed_pre(display, reg, true, mmio_flags);
 
 	intel_uncore_write(__to_uncore(display), reg, val);
 
+	__mmio_unclaimed_post(display, reg, true, mmio_flags);
 	__mmio_lock_post(display, irqflags, mmio_flags);
 	__mmio_wakelock_post(display, reg, mmio_flags);
 }
@@ -269,6 +409,32 @@ static const struct intel_mmio_funcs snb_mmio_funcs = {
 	.write = snb_mmio_write,
 };
 
+#define IVB_MMIO_FLAGS (__MMIO_LOCK | __MMIO_UNCLAIMED)
+
+static u32 ivb_mmio_read(struct intel_display *display, intel_reg_t reg)
+{
+	return __intel_de_read(display, reg, IVB_MMIO_FLAGS);
+}
+
+static void ivb_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
+{
+	__intel_de_write(display, reg, val, IVB_MMIO_FLAGS);
+}
+
+#undef IVB_MMIO_FLAGS
+
+static const struct intel_mmio_funcs ivb_mmio_funcs = {
+	.read = ivb_mmio_read,
+	.write = ivb_mmio_write,
+	.check_for_unclaimed_mmio = ivb_check_for_unclaimed_mmio,
+};
+
+static const struct intel_mmio_funcs vlv_mmio_funcs = {
+	.read = ivb_mmio_read,
+	.write = ivb_mmio_write,
+	.check_for_unclaimed_mmio = vlv_check_for_unclaimed_mmio,
+};
+
 #define LNL_MMIO_FLAGS __MMIO_WAKELOCK
 
 static u32 lnl_mmio_read(struct intel_display *display, intel_reg_t reg)
@@ -304,7 +470,11 @@ void intel_de_init(struct intel_display *display)
 	spin_lock_init(&display->mmio.lock);
 
 	if (driver_is_i915()) {
-		if (DISPLAY_VER(display) >= 6)
+		if (display->platform.valleyview || display->platform.cherryview)
+			display->mmio.funcs = &vlv_mmio_funcs;
+		else if (DISPLAY_VER(display) >= 7)
+			display->mmio.funcs = &ivb_mmio_funcs;
+		else if (DISPLAY_VER(display) >= 6)
 			display->mmio.funcs = &snb_mmio_funcs;
 		else
 			display->mmio.funcs = &i9xx_mmio_funcs;
@@ -314,4 +484,7 @@ void intel_de_init(struct intel_display *display)
 		else
 			display->mmio.funcs = &i9xx_mmio_funcs;
 	}
+
+	if (display->mmio.funcs->check_for_unclaimed_mmio)
+		display->mmio.unclaimed_mmio_check = 1;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index 760b8bc31f9b..310f81edc09d 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -14,6 +14,7 @@
 struct intel_mmio_funcs {
 	u32 (*read)(struct intel_display *display, intel_reg_t reg);
 	void (*write)(struct intel_display *display, intel_reg_t reg, u32 val);
+	bool (*check_for_unclaimed_mmio)(struct intel_display *display);
 };
 
 static inline struct intel_uncore *__to_uncore(struct intel_display *display)
@@ -22,6 +23,8 @@ static inline struct intel_uncore *__to_uncore(struct intel_display *display)
 }
 
 void intel_de_init(struct intel_display *display);
+bool intel_de_unclaimed_mmio_detected(struct intel_display *display);
+bool intel_de_arm_unclaimed_mmio_detection(struct intel_display *display);
 
 u8 intel_de_read8(struct intel_display *display, intel_reg_t reg);
 void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cf9190969da7..1077cc27052d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7740,7 +7740,6 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 {
 	struct intel_display *display = to_intel_display(state);
-	struct intel_uncore *uncore = to_intel_uncore(display->drm);
 	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
 	struct intel_crtc *crtc;
 	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
@@ -7954,7 +7953,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		 * so enable debugging for the next modeset - and hope we catch
 		 * the culprit.
 		 */
-		intel_uncore_arm_unclaimed_mmio_detection(uncore);
+		intel_de_arm_unclaimed_mmio_detection(display);
 	}
 
 	power_async_delay = intel_display_power_select_target_dc_state(state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index aded2af8c92a..cb18ee040b5d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -539,11 +539,18 @@ struct intel_display {
 		 * serializes all display register accesses done
 		 * using intel_de_{read,write}(), but not those
 		 * done using intel_de_{read,write}_fw().
+		 *
+		 * The lock also protects mmio.mmio_debug and
+		 * mmio.unclaimed_mmio_check.
 		 */
 		spinlock_t lock;
 
 		struct intel_uncore *uncore;
 		const struct intel_mmio_funcs *funcs;
+
+		/* protected by mmio.lock */
+		int mmio_debug;
+		int unclaimed_mmio_check;
 	} mmio;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 0c7bec7d7f01..778d6c7ca4c8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -30,6 +30,7 @@
 #include "intel_crtc.h"
 #include "intel_cursor.h"
 #include "intel_dbuf_bw.h"
+#include "intel_de.h"
 #include "intel_display_clock_gating.h"
 #include "intel_display_core.h"
 #include "intel_display_debugfs.h"
@@ -973,3 +974,17 @@ void intel_display_driver_pm_runtime_resume(struct intel_display *display)
 
 	skl_watermark_ipc_update(display);
 }
+
+void intel_display_driver_mmio_resume_early(struct intel_display *display)
+{
+	if (intel_de_unclaimed_mmio_detected(display))
+		drm_dbg_kms(display->drm,
+			    "Unclaimed access during suspend, bios?\n");
+}
+
+void intel_display_driver_mmio_suspend_late(struct intel_display *display)
+{
+	if (intel_de_arm_unclaimed_mmio_detection(display))
+		drm_err(display->drm,
+			"Unclaimed access detected prior to suspending\n");
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.h b/drivers/gpu/drm/i915/display/intel_display_driver.h
index 1ae2ad7e95f6..6f04a92902fa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.h
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.h
@@ -32,6 +32,9 @@ void intel_display_driver_pm_suspend_late(struct intel_display *display, bool s2
 void intel_display_driver_pm_resume_early(struct intel_display *display);
 void intel_display_driver_pm_resume(struct intel_display *display);
 
+void intel_display_driver_mmio_suspend_late(struct intel_display *display);
+void intel_display_driver_mmio_resume_early(struct intel_display *display);
+
 /* interface for intel_display_reset.c */
 int __intel_display_driver_resume(struct intel_display *display,
 				  struct drm_atomic_commit *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
index ca0ef466bb10..ace3081461de 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -143,6 +143,10 @@ intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
 	"(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) "
 	"Default: -1");
 
+intel_display_param_named(mmio_debug, int, 0400,
+	"Enable the MMIO debug code for the first N failures (default: off). "
+	"This may negatively affect performance.");
+
 __maybe_unused
 static void _param_print_bool(struct drm_printer *p, const char *driver_name,
 			      const char *name, bool val)
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
index 5c5a1a1358c3..bcbca95318d6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -51,6 +51,7 @@ struct drm_printer;
 	param(bool, psr_safest_params, false, 0400) \
 	param(bool, enable_psr2_sel_fetch, true, 0400) \
 	param(int, enable_dmc_wl, -1, 0400) \
+	param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \
 	/*
 	 * Debugfs-only knob (per-device): no matching module_param is registered
 	 * in intel_display_params.c on purpose. Runtime-toggle via debugfs.
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index bbdbc27629d7..f213bdffcc8d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3287,4 +3287,12 @@ enum skl_power_gate {
 #define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
 #define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
 
+#define FPGA_DBG		_MMIO(0x42300)
+#define   FPGA_DBG_RM_NOCLAIM	REG_BIT(31)
+
+#define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
+#define   CLAIM_ER_CLR		REG_BIT(31)
+#define   CLAIM_ER_OVERFLOW	REG_BIT(16)
+#define   CLAIM_ER_CTR_MASK	REG_GENMASK(15, 0)
+
 #endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 5787f40ac62e..923b239714b7 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -238,8 +238,6 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 
 	intel_step_init(dev_priv);
 
-	intel_uncore_mmio_debug_init_early(dev_priv);
-
 	spin_lock_init(&dev_priv->gpu_error.lock);
 
 	intel_sbi_init(display);
@@ -1281,6 +1279,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
 		drm_err(&dev_priv->drm,
 			"Resume prepare failed: %d, continuing anyway\n", ret);
 
+	intel_display_driver_mmio_resume_early(display);
+
 	for_each_gt(gt, dev_priv, i)
 		intel_gt_resume_early(gt);
 
@@ -1546,9 +1546,7 @@ static int i915_pm_runtime_suspend(struct device *kdev)
 	enable_rpm_wakeref_asserts(rpm);
 	intel_runtime_pm_driver_release(rpm);
 
-	if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
-		drm_err(&dev_priv->drm,
-			"Unclaimed access detected prior to suspending\n");
+	intel_display_driver_mmio_suspend_late(display);
 
 	/*
 	 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
@@ -1587,9 +1585,7 @@ static int i915_pm_runtime_resume(struct device *kdev)
 	if (root_pdev)
 		pci_d3cold_enable(root_pdev);
 
-	if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
-		drm_dbg(&dev_priv->drm,
-			"Unclaimed access during suspend, bios?\n");
+	intel_display_driver_mmio_resume_early(display);
 
 	intel_display_driver_pm_runtime_resume_early(display);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dafee3dcd1c5..95637ada00d7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -185,7 +185,6 @@ struct drm_i915_private {
 	struct i915_dsm dsm;
 
 	struct intel_uncore uncore;
-	struct intel_uncore_mmio_debug mmio_debug;
 
 	struct i915_virtual_gpu vgpu;
 
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 34ed82bb1b1a..377d3c005580 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -88,10 +88,6 @@ i915_param_named_unsafe(force_probe, charp, 0400,
 i915_param_named(memtest, bool, 0400,
 	"Perform a read/write test of all device memory on module load (default: off)");
 
-i915_param_named(mmio_debug, int, 0400,
-	"Enable the MMIO debug code for the first N failures (default: off). "
-	"This may negatively affect performance.");
-
 i915_param_named_unsafe(enable_guc, int, 0400,
 	"Enable GuC load for GuC submission and/or HuC load. "
 	"Required functionality can be selected using bitmask values. "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 4d9d4cd3220d..0cb46609f4a3 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -53,7 +53,6 @@ struct drm_printer;
 	param(char *, huc_firmware_path, NULL, 0400) \
 	param(char *, gsc_firmware_path, NULL, 0400) \
 	param(bool, memtest, false, 0400) \
-	param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \
 	param(unsigned int, reset, 3, 0600) \
 	param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
 	param(unsigned int, request_timeout_ms, CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d873072b7a92..806e5a56471d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -325,13 +325,6 @@
 #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
 #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
 
-#define FPGA_DBG		_MMIO(0x42300)
-#define   FPGA_DBG_RM_NOCLAIM	REG_BIT(31)
-
-#define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
-#define   CLAIM_ER_CLR		REG_BIT(31)
-#define   CLAIM_ER_OVERFLOW	REG_BIT(16)
-#define   CLAIM_ER_CTR_MASK	REG_GENMASK(15, 0)
 
 #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
 #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index abd695e880c1..b53059c1a782 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -56,15 +56,6 @@ fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
 	uncore->fw_get_funcs->force_wake_get(uncore, fw_domains);
 }
 
-void
-intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915)
-{
-	spin_lock_init(&i915->mmio_debug.lock);
-	i915->mmio_debug.unclaimed_mmio_check = 1;
-
-	i915->uncore.debug = &i915->mmio_debug;
-}
-
 static const char * const forcewake_domain_names[] = {
 	"render",
 	"gt",
@@ -512,66 +503,6 @@ intel_uncore_forcewake_reset(struct intel_uncore *uncore)
 	return fw; /* track the lost user forcewake domains */
 }
 
-static bool
-fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
-{
-	u32 dbg;
-
-	dbg = __raw_uncore_read32(uncore, FPGA_DBG);
-	if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
-		return false;
-
-	/*
-	 * Bugs in PCI programming (or failing hardware) can occasionally cause
-	 * us to lose access to the MMIO BAR.  When this happens, register
-	 * reads will come back with 0xFFFFFFFF for every register and things
-	 * go bad very quickly.  Let's try to detect that special case and at
-	 * least try to print a more informative message about what has
-	 * happened.
-	 *
-	 * During normal operation the FPGA_DBG register has several unused
-	 * bits that will always read back as 0's so we can use them as canaries
-	 * to recognize when MMIO accesses are just busted.
-	 */
-	if (unlikely(dbg == ~0))
-		drm_err(&uncore->i915->drm,
-			"Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n");
-
-	__raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
-
-	return true;
-}
-
-static bool
-vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
-{
-	u32 cer;
-
-	cer = __raw_uncore_read32(uncore, CLAIM_ER);
-	if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
-		return false;
-
-	__raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
-
-	return true;
-}
-
-static bool
-check_for_unclaimed_mmio(struct intel_uncore *uncore)
-{
-	bool ret = false;
-
-	lockdep_assert_held(&uncore->debug->lock);
-
-	if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
-		ret |= fpga_check_for_unclaimed_mmio(uncore);
-
-	if (intel_uncore_has_dbg_unclaimed(uncore))
-		ret |= vlv_check_for_unclaimed_mmio(uncore);
-
-	return ret;
-}
-
 static void forcewake_early_sanitize(struct intel_uncore *uncore,
 				     unsigned int restore_forcewake)
 {
@@ -617,9 +548,6 @@ void intel_uncore_resume_early(struct intel_uncore *uncore)
 {
 	unsigned int restore_forcewake;
 
-	if (intel_uncore_unclaimed_mmio(uncore))
-		drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n");
-
 	if (!intel_uncore_has_forcewake(uncore))
 		return;
 
@@ -1734,59 +1662,6 @@ ilk_dummy_write(struct intel_uncore *uncore)
 	__raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0);
 }
 
-static void
-__unclaimed_reg_debug(struct intel_uncore *uncore,
-		      const i915_reg_t reg,
-		      const bool read)
-{
-	if (drm_WARN(&uncore->i915->drm,
-		     check_for_unclaimed_mmio(uncore),
-		     "Unclaimed %s register 0x%x\n",
-		     read ? "read from" : "write to",
-		     i915_mmio_reg_offset(reg)))
-		/* Only report the first N failures */
-		uncore->i915->params.mmio_debug--;
-}
-
-static void
-__unclaimed_previous_reg_debug(struct intel_uncore *uncore,
-			       const i915_reg_t reg,
-			       const bool read)
-{
-	if (check_for_unclaimed_mmio(uncore))
-		drm_dbg(&uncore->i915->drm,
-			"Unclaimed access detected before %s register 0x%x\n",
-			read ? "read from" : "write to",
-			i915_mmio_reg_offset(reg));
-}
-
-static inline bool __must_check
-unclaimed_reg_debug_header(struct intel_uncore *uncore,
-			   const i915_reg_t reg, const bool read)
-{
-	if (likely(!uncore->i915->params.mmio_debug) || !uncore->debug)
-		return false;
-
-	/* interrupts are disabled and re-enabled around uncore->lock usage */
-	lockdep_assert_held(&uncore->lock);
-
-	spin_lock(&uncore->debug->lock);
-	__unclaimed_previous_reg_debug(uncore, reg, read);
-
-	return true;
-}
-
-static inline void
-unclaimed_reg_debug_footer(struct intel_uncore *uncore,
-			   const i915_reg_t reg, const bool read)
-{
-	/* interrupts are disabled and re-enabled around uncore->lock usage */
-	lockdep_assert_held(&uncore->lock);
-
-	__unclaimed_reg_debug(uncore, reg, read);
-	spin_unlock(&uncore->debug->lock);
-}
-
 #define __vgpu_read(x) \
 static u##x \
 vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
@@ -1842,15 +1717,11 @@ __gen2_read(64)
 #define GEN6_READ_HEADER(x) \
 	u32 offset = i915_mmio_reg_offset(reg); \
 	unsigned long irqflags; \
-	bool unclaimed_reg_debug; \
 	u##x val = 0; \
 	assert_rpm_wakelock_held(uncore->rpm); \
-	spin_lock_irqsave(&uncore->lock, irqflags); \
-	unclaimed_reg_debug = unclaimed_reg_debug_header(uncore, reg, true)
+	spin_lock_irqsave(&uncore->lock, irqflags)
 
 #define GEN6_READ_FOOTER \
-	if (unclaimed_reg_debug) \
-		unclaimed_reg_debug_footer(uncore, reg, true);	\
 	spin_unlock_irqrestore(&uncore->lock, irqflags); \
 	trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 	return val
@@ -1948,15 +1819,11 @@ __gen2_write(32)
 #define GEN6_WRITE_HEADER \
 	u32 offset = i915_mmio_reg_offset(reg); \
 	unsigned long irqflags; \
-	bool unclaimed_reg_debug; \
 	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 	assert_rpm_wakelock_held(uncore->rpm); \
-	spin_lock_irqsave(&uncore->lock, irqflags); \
-	unclaimed_reg_debug = unclaimed_reg_debug_header(uncore, reg, false)
+	spin_lock_irqsave(&uncore->lock, irqflags)
 
 #define GEN6_WRITE_FOOTER \
-	if (unclaimed_reg_debug) \
-		unclaimed_reg_debug_footer(uncore, reg, false); \
 	spin_unlock_irqrestore(&uncore->lock, irqflags)
 
 #define __gen6_write(x) \
@@ -2490,7 +2357,6 @@ static int sanity_check_mmio_access(struct intel_uncore *uncore)
 int intel_uncore_init_mmio(struct intel_uncore *uncore)
 {
 	struct drm_i915_private *i915 = uncore->i915;
-	struct intel_display *display = i915->display;
 	int ret;
 
 	ret = sanity_check_mmio_access(uncore);
@@ -2525,19 +2391,9 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
 	GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
 	GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
 
-	if (HAS_FPGA_DBG_UNCLAIMED(display))
-		uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
-
-	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
-		uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
-
 	if (IS_GRAPHICS_VER(i915, 6, 7))
 		uncore->flags |= UNCORE_HAS_FIFO;
 
-	/* clear out unclaimed reg detection bit */
-	if (intel_uncore_unclaimed_mmio(uncore))
-		drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n");
-
 	return 0;
 }
 
@@ -2800,51 +2656,6 @@ int __intel_wait_for_register(struct intel_uncore *uncore,
 	return ret;
 }
 
-bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
-{
-	bool ret;
-
-	if (!uncore->debug)
-		return false;
-
-	spin_lock_irq(&uncore->debug->lock);
-	ret = check_for_unclaimed_mmio(uncore);
-	spin_unlock_irq(&uncore->debug->lock);
-
-	return ret;
-}
-
-bool
-intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
-{
-	bool ret = false;
-
-	if (drm_WARN_ON(&uncore->i915->drm, !uncore->debug))
-		return false;
-
-	spin_lock_irq(&uncore->debug->lock);
-
-	if (unlikely(uncore->debug->unclaimed_mmio_check <= 0))
-		goto out;
-
-	if (unlikely(check_for_unclaimed_mmio(uncore))) {
-		if (!uncore->i915->params.mmio_debug) {
-			drm_dbg(&uncore->i915->drm,
-				"Unclaimed register detected, "
-				"enabling oneshot unclaimed register reporting. "
-				"Please use i915.mmio_debug=N for more information.\n");
-			uncore->i915->params.mmio_debug++;
-		}
-		uncore->debug->unclaimed_mmio_check--;
-		ret = true;
-	}
-
-out:
-	spin_unlock_irq(&uncore->debug->lock);
-
-	return ret;
-}
-
 /**
  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
  * 				    a register
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 4ec7c545d04e..9047d7d4d855 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -39,11 +39,6 @@ struct intel_runtime_pm;
 struct intel_uncore;
 struct intel_gt;
 
-struct intel_uncore_mmio_debug {
-	spinlock_t lock; /** lock is also taken in irq contexts. */
-	int unclaimed_mmio_check;
-};
-
 enum forcewake_domain_id {
 	FW_DOMAIN_ID_RENDER = 0,
 	FW_DOMAIN_ID_GT,        /* also includes blitter engine */
@@ -142,8 +137,6 @@ struct intel_uncore {
 
 	unsigned int flags;
 #define UNCORE_HAS_FORCEWAKE		BIT(0)
-#define UNCORE_HAS_FPGA_DBG_UNCLAIMED	BIT(1)
-#define UNCORE_HAS_DBG_UNCLAIMED	BIT(2)
 #define UNCORE_HAS_FIFO			BIT(3)
 #define UNCORE_NEEDS_FLR_ON_FINI	BIT(4)
 
@@ -180,8 +173,6 @@ struct intel_uncore {
 	} *fw_domain[FW_DOMAIN_ID_COUNT];
 
 	unsigned int user_forcewake_count;
-
-	struct intel_uncore_mmio_debug *debug;
 };
 
 /* Iterate over initialised fw domains */
@@ -198,18 +189,6 @@ intel_uncore_has_forcewake(const struct intel_uncore *uncore)
 	return uncore->flags & UNCORE_HAS_FORCEWAKE;
 }
 
-static inline bool
-intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore *uncore)
-{
-	return uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED;
-}
-
-static inline bool
-intel_uncore_has_dbg_unclaimed(const struct intel_uncore *uncore)
-{
-	return uncore->flags & UNCORE_HAS_DBG_UNCLAIMED;
-}
-
 static inline bool
 intel_uncore_has_fifo(const struct intel_uncore *uncore)
 {
@@ -228,15 +207,12 @@ intel_uncore_set_flr_on_fini(struct intel_uncore *uncore)
 	return uncore->flags |= UNCORE_NEEDS_FLR_ON_FINI;
 }
 
-void intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915);
 void intel_uncore_init_early(struct intel_uncore *uncore,
 			     struct intel_gt *gt);
 int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr);
 int intel_uncore_init_mmio(struct intel_uncore *uncore);
 void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
 					  struct intel_gt *gt);
-bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
-bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
 void intel_uncore_cleanup_mmio(struct intel_uncore *uncore);
 void intel_uncore_fini_mmio(struct drm_device *dev, void *data);
 void intel_uncore_suspend(struct intel_uncore *uncore);
-- 
2.56.0

Re: [PATCH 7/9] drm/i915/de: Move unclaimed mmio detection into display code

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] drm/i915/de: NULL deref on displayless devices in unclaimed MMIO checks
- [Medium] drm/i915/de: intel_de_init() enables FPGA_DBG check on Ivy Bridge
- [Medium] drm/i915/de: unclaimed MMIO status is not cleared on initialization
- [Low] drm/i915/display: unused mmio.mmio_debug field in struct intel_display
--

commit 74c572411ef669251a5e2e347d14a7771407e433
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>

drm/i915/de: Move unclaimed mmio detection into display code

This commit moves the FPGA_DBG and CLAIM_ER unclaimed MMIO access detection
from intel_uncore into the display code, protecting the tracking state with
display->mmio.lock.

> diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> index 8b7a4e696ff96..0a51105e0fbad 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.c
> +++ b/drivers/gpu/drm/i915/display/intel_de.c

[ ... ]

> @@ -163,8 +164,127 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)

[ ... ]

> +bool intel_de_unclaimed_mmio_detected(struct intel_display *display)
> +{
> +	bool ret;
> +
> +	if (!display->mmio.funcs->check_for_unclaimed_mmio)
> +		return false;
> +
> +	spin_lock_irq(&display->mmio.lock);
> +	ret = display->mmio.funcs->check_for_unclaimed_mmio(display);
> +	spin_unlock_irq(&display->mmio.lock);
> +
> +	return ret;
> +}
> +
> +bool intel_de_arm_unclaimed_mmio_detection(struct intel_display *display)
> +{
> +	bool ret = false;
> +
> +	if (!display->mmio.funcs->check_for_unclaimed_mmio)
> +		return false;

[Severity: High]
Can intel_de_unclaimed_mmio_detected() and
intel_de_arm_unclaimed_mmio_detection() dereference a NULL display->mmio.funcs
pointer on devices without display?

On displayless devices where intel_display_device_probe() takes the no_display
path (such as INTEL_IVB_Q_IDS, INTEL_ATS_M_IDS, or GMD_ID platforms where
GMD_ID_DISPLAY reads 0), HAS_DISPLAY(display) is false. During probe,
intel_display_device_info_runtime_init() skips
__intel_display_device_info_runtime_init():

drivers/gpu/drm/i915/display/intel_display_device.c:
intel_display_device_info_runtime_init() {
	if (HAS_DISPLAY(display))
		__intel_display_device_info_runtime_init(display);

Because intel_de_init() is only called from
__intel_display_device_info_runtime_init(), display->mmio.funcs remains NULL
and display->mmio.lock is never initialized.

Later, i915_drm_resume_early(), i915_pm_runtime_suspend(), and
i915_pm_runtime_resume() unconditionally call
intel_display_driver_mmio_resume_early() and
intel_display_driver_mmio_suspend_late(), which call
intel_de_unclaimed_mmio_detected() and intel_de_arm_unclaimed_mmio_detection()
and dereference display->mmio.funcs.

Additionally, if HAS_DISPLAY(display) is initially true so intel_de_init()
sets display->mmio.funcs = &ivb_mmio_funcs, and
__intel_display_device_info_runtime_init() subsequently jumps to
display_fused_off, display->mmio.funcs remains set while HAS_DISPLAY(display)
becomes false, causing suspend and resume to access FPGA_DBG even though
display is fused off.

Should intel_de_init() be called unconditionally (or display->mmio.funcs be
checked / reset when display is fused off), and should
intel_display_driver_mmio_suspend_late() and
intel_display_driver_mmio_resume_early() check HAS_DISPLAY(display)?

[ ... ]

> @@ -304,7 +470,11 @@ void intel_de_init(struct intel_display *display)
>  	spin_lock_init(&display->mmio.lock);
>  
>  	if (driver_is_i915()) {
> -		if (display->platform.valleyview || display->platform.cherryview)
> +		if (display->platform.valleyview || display->platform.cherryview)
> +			display->mmio.funcs = &vlv_mmio_funcs;
> +		else if (DISPLAY_VER(display) >= 7)
> +			display->mmio.funcs = &ivb_mmio_funcs;
> +		else if (DISPLAY_VER(display) >= 6)
>  			display->mmio.funcs = &snb_mmio_funcs;
>  		else
>  			display->mmio.funcs = &i9xx_mmio_funcs;

[Severity: Medium]
Does checking DISPLAY_VER(display) >= 7 in intel_de_init() unintentionally
enable FPGA_DBG unclaimed MMIO checks on Ivy Bridge?

Previously, intel_uncore_init_mmio() gated FPGA_DBG unclaimed MMIO detection
on HAS_FPGA_DBG_UNCLAIMED(display). In
drivers/gpu/drm/i915/display/intel_display_device.c, has_fpga_dbg is set on
hsw_desc and bdw_desc onwards, whereas ivb_display has ip.ver = 7 and
has_fpga_dbg = 0. Checking DISPLAY_VER(display) >= 7 assigns ivb_mmio_funcs to
Ivy Bridge as well, and leaves HAS_FPGA_DBG_UNCLAIMED(display) unused.

Should this check HAS_FPGA_DBG_UNCLAIMED(display) instead?

> @@ -314,4 +484,7 @@ void intel_de_init(struct intel_display *display)
>  		else
>  			display->mmio.funcs = &i9xx_mmio_funcs;
>  	}
> +
> +	if (display->mmio.funcs->check_for_unclaimed_mmio)
> +		display->mmio.unclaimed_mmio_check = 1;
>  }

[Severity: Medium]
Previously, intel_uncore_init_mmio() cleared any stale unclaimed MMIO bit left
set by BIOS or pre-boot firmware during initialization:

	/* clear out unclaimed reg detection bit */
	if (intel_uncore_unclaimed_mmio(uncore))
		drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n");

With that removed and not replaced in intel_de_init(), if mmio_debug is
disabled by default, won't a stale FPGA_DBG_RM_NOCLAIM or CLAIM_ER bit from
boot firmware remain latched until intel_de_arm_unclaimed_mmio_detection()
runs at the end of the first modeset or in
intel_display_driver_mmio_suspend_late(), triggering a false-positive error or
falsely arming oneshot mmio_debug reporting?

> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index aded2af8c92a6..cb18ee040b5d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -539,11 +539,18 @@ struct intel_display {
>  		 * serializes all display register accesses done
>  		 * using intel_de_{read,write}(), but not those
>  		 * done using intel_de_{read,write}_fw().
> +		 *
> +		 * The lock also protects mmio.mmio_debug and
> +		 * mmio.unclaimed_mmio_check.
>  		 */
>  		spinlock_t lock;
>  
>  		struct intel_uncore *uncore;
>  		const struct intel_mmio_funcs *funcs;
> +
> +		/* protected by mmio.lock */
> +		int mmio_debug;
> +		int unclaimed_mmio_check;
>  	} mmio;

[Severity: Low]
This isn't a bug, but display->mmio.mmio_debug is never used since
check_unclaimed_mmio_pre(), check_unclaimed_mmio_post(), and
intel_de_arm_unclaimed_mmio_detection() all use display->params.mmio_debug.
Should mmio.mmio_debug be dropped from struct intel_display?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261104221842.18799-1-ville.syrjala@linux.intel.com?part=7

Re: [PATCH 7/9] drm/i915/de: Move unclaimed mmio detection into display code

[Ville Syrjälä]

On Wed, Nov 04, 2026 at 10:36:37PM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
> - [High] drm/i915/de: NULL deref on displayless devices in unclaimed MMIO checks
> - [Medium] drm/i915/de: intel_de_init() enables FPGA_DBG check on Ivy Bridge
> - [Medium] drm/i915/de: unclaimed MMIO status is not cleared on initialization
> - [Low] drm/i915/display: unused mmio.mmio_debug field in struct intel_display
> --
> 
> commit 74c572411ef669251a5e2e347d14a7771407e433
> Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> drm/i915/de: Move unclaimed mmio detection into display code
> 
> This commit moves the FPGA_DBG and CLAIM_ER unclaimed MMIO access detection
> from intel_uncore into the display code, protecting the tracking state with
> display->mmio.lock.
> 
> > diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> > index 8b7a4e696ff96..0a51105e0fbad 100644
> > --- a/drivers/gpu/drm/i915/display/intel_de.c
> > +++ b/drivers/gpu/drm/i915/display/intel_de.c
> 
> [ ... ]
<snip>
> > @@ -304,7 +470,11 @@ void intel_de_init(struct intel_display *display)
> >  	spin_lock_init(&display->mmio.lock);
> >  
> >  	if (driver_is_i915()) {
> > -		if (display->platform.valleyview || display->platform.cherryview)
> > +		if (display->platform.valleyview || display->platform.cherryview)
> > +			display->mmio.funcs = &vlv_mmio_funcs;
> > +		else if (DISPLAY_VER(display) >= 7)
> > +			display->mmio.funcs = &ivb_mmio_funcs;
> > +		else if (DISPLAY_VER(display) >= 6)
> >  			display->mmio.funcs = &snb_mmio_funcs;
> >  		else
> >  			display->mmio.funcs = &i9xx_mmio_funcs;
> 
> [Severity: Medium]
> Does checking DISPLAY_VER(display) >= 7 in intel_de_init() unintentionally
> enable FPGA_DBG unclaimed MMIO checks on Ivy Bridge?

Yes, but only because I misremembered that IVB has the feature already.
IVB does have the FPGA_DBG register already (which is the part I
remembered correctly), but the unclaimed register access bit is not
there until HSW. I guess that makes perfect since since HSW is the
one that also introduced us to power wells. So I'll need to
s/ivb/hsw/ here.

> 
> Previously, intel_uncore_init_mmio() gated FPGA_DBG unclaimed MMIO detection
> on HAS_FPGA_DBG_UNCLAIMED(display). In
> drivers/gpu/drm/i915/display/intel_display_device.c, has_fpga_dbg is set on
> hsw_desc and bdw_desc onwards, whereas ivb_display has ip.ver = 7 and
> has_fpga_dbg = 0. Checking DISPLAY_VER(display) >= 7 assigns ivb_mmio_funcs to
> Ivy Bridge as well, and leaves HAS_FPGA_DBG_UNCLAIMED(display) unused.
> 
> Should this check HAS_FPGA_DBG_UNCLAIMED(display) instead?
> 
> > @@ -314,4 +484,7 @@ void intel_de_init(struct intel_display *display)
> >  		else
> >  			display->mmio.funcs = &i9xx_mmio_funcs;
> >  	}
> > +
> > +	if (display->mmio.funcs->check_for_unclaimed_mmio)
> > +		display->mmio.unclaimed_mmio_check = 1;
> >  }
> 
> [Severity: Medium]
> Previously, intel_uncore_init_mmio() cleared any stale unclaimed MMIO bit left
> set by BIOS or pre-boot firmware during initialization:
> 
> 	/* clear out unclaimed reg detection bit */
> 	if (intel_uncore_unclaimed_mmio(uncore))
> 		drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n");
> 
> With that removed and not replaced in intel_de_init(), if mmio_debug is

Hmm. I thought I took care of that, but looks like I only adjusted the
resume path, not the init path.

> disabled by default, won't a stale FPGA_DBG_RM_NOCLAIM or CLAIM_ER bit from
> boot firmware remain latched until intel_de_arm_unclaimed_mmio_detection()
> runs at the end of the first modeset or in
> intel_display_driver_mmio_suspend_late(), triggering a false-positive error or
> falsely arming oneshot mmio_debug reporting?
> 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> > index aded2af8c92a6..cb18ee040b5d6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > @@ -539,11 +539,18 @@ struct intel_display {
> >  		 * serializes all display register accesses done
> >  		 * using intel_de_{read,write}(), but not those
> >  		 * done using intel_de_{read,write}_fw().
> > +		 *
> > +		 * The lock also protects mmio.mmio_debug and
> > +		 * mmio.unclaimed_mmio_check.
> >  		 */
> >  		spinlock_t lock;
> >  
> >  		struct intel_uncore *uncore;
> >  		const struct intel_mmio_funcs *funcs;
> > +
> > +		/* protected by mmio.lock */
> > +		int mmio_debug;
> > +		int unclaimed_mmio_check;
> >  	} mmio;
> 
> [Severity: Low]
> This isn't a bug, but display->mmio.mmio_debug is never used since
> check_unclaimed_mmio_pre(), check_unclaimed_mmio_post(), and
> intel_de_arm_unclaimed_mmio_detection() all use display->params.mmio_debug.
> Should mmio.mmio_debug be dropped from struct intel_display?

Aye. Looks like some crap I accidentally left in.

-- 
Ville Syrjälä
Intel

Re: [PATCH 7/9] drm/i915/de: Move unclaimed mmio detection into display code

[Jani Nikula]

On Thu, 05 Nov 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The FPGA_DBG/CLAIM_ER unclaimed mmio access detection only
> works for display registers. Therefore checking it for GT
> registers/etc is completely pointless. Hoist the whole thing
> into the display code. Eventually we'll also want to hook this
> up for xe, but for now we keep it i915 only to avoid too many
> functional changes in one go.
>
> Note that i915 used a separate spinlock to protect the
> mmio debug tracking. But basically whenever it would grab that
> lock it was already holding uncore.lock, so the double locking
> was rather pointless. When moving this into the display code
> we'll just protect it all with the same display mmio.lock that
> already provides any needed serialization of register accesses.
>
> This will of course speed up the non-fw GT register accesses
> with mmio debug enabled since we never do the two extra
> FPGA_DBG/CLAIM_ER reads for them.
>
> Note that we do lose the FPGA_DBG!=0xffffffff sanity check for
> non-display register accesses now. Possibly the GT side should
> use some harmless GT register for that instead. But I didn't
> bother looking for one at this time.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Some commentary inline, but didn't spot anything wrong, really.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_de.c       | 175 +++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_de.h       |   3 +
>  drivers/gpu/drm/i915/display/intel_display.c  |   3 +-
>  .../gpu/drm/i915/display/intel_display_core.h |   7 +
>  .../drm/i915/display/intel_display_driver.c   |  15 ++
>  .../drm/i915/display/intel_display_driver.h   |   3 +
>  .../drm/i915/display/intel_display_params.c   |   4 +
>  .../drm/i915/display/intel_display_params.h   |   1 +
>  .../gpu/drm/i915/display/intel_display_regs.h |   8 +
>  drivers/gpu/drm/i915/i915_driver.c            |  12 +-
>  drivers/gpu/drm/i915/i915_drv.h               |   1 -
>  drivers/gpu/drm/i915/i915_params.c            |   4 -
>  drivers/gpu/drm/i915/i915_params.h            |   1 -
>  drivers/gpu/drm/i915/i915_reg.h               |   7 -
>  drivers/gpu/drm/i915/intel_uncore.c           | 193 +-----------------
>  drivers/gpu/drm/i915/intel_uncore.h           |  24 ---
>  16 files changed, 222 insertions(+), 239 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> index 8b7a4e696ff9..0a51105e0fba 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.c
> +++ b/drivers/gpu/drm/i915/display/intel_de.c
> @@ -8,6 +8,7 @@
>  #include <drm/drm_print.h>
>  
>  #include "intel_de.h"
> +#include "intel_display_regs.h"
>  
>  static int intel_de_wait_for_register(struct intel_display *display,
>  				      intel_reg_t reg, u32 mask, u32 value,
> @@ -163,8 +164,127 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
>  	return intel_uncore_read16(__to_uncore(display), reg);
>  }
>  
> +static bool ivb_check_for_unclaimed_mmio(struct intel_display *display)
> +{
> +	u32 dbg;
> +
> +	dbg = intel_de_read_fw(display, FPGA_DBG);
> +	if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
> +		return false;
> +
> +	/*
> +	 * Bugs in PCI programming (or failing hardware) can occasionally cause
> +	 * us to lose access to the MMIO BAR.  When this happens, register
> +	 * reads will come back with 0xFFFFFFFF for every register and things
> +	 * go bad very quickly.  Let's try to detect that special case and at
> +	 * least try to print a more informative message about what has
> +	 * happened.
> +	 *
> +	 * During normal operation the FPGA_DBG register has several unused
> +	 * bits that will always read back as 0's so we can use them as canaries
> +	 * to recognize when MMIO accesses are just busted.
> +	 */
> +	if (unlikely(dbg == ~0))
> +		drm_err(display->drm,
> +			"Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n");
> +
> +	intel_de_write_fw(display, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
> +
> +	return true;
> +}
> +
> +static bool vlv_check_for_unclaimed_mmio(struct intel_display *display)
> +{
> +	u32 cer;
> +
> +	cer = intel_de_read_fw(display, CLAIM_ER);
> +	if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
> +		return false;
> +
> +	intel_de_write_fw(display, CLAIM_ER, CLAIM_ER_CLR);
> +
> +	return true;
> +}
> +
> +static void check_unclaimed_mmio_pre(struct intel_display *display,
> +				     intel_reg_t reg, bool write)
> +{
> +	lockdep_assert_held(&display->mmio.lock);
> +
> +	if (!display->params.mmio_debug)
> +		return;
> +
> +	if (display->mmio.funcs->check_for_unclaimed_mmio(display))
> +		drm_dbg_kms(display->drm,
> +			    "Unclaimed access detected before %s register 0x%x\n",
> +			    write ? "write to" : "read from",
> +			    i915_mmio_reg_offset(reg));
> +}
> +
> +static void check_unclaimed_mmio_post(struct intel_display *display,
> +				      intel_reg_t reg, bool write)
> +{
> +	lockdep_assert_held(&display->mmio.lock);
> +
> +	if (!display->params.mmio_debug)
> +		return;
> +
> +	if (drm_WARN(display->drm,
> +		     display->mmio.funcs->check_for_unclaimed_mmio(display),
> +		     "Unclaimed %s register 0x%x\n",
> +		     write ? "write to" : "read from",
> +		     i915_mmio_reg_offset(reg)))
> +		/* Only report the first N failures */
> +		display->params.mmio_debug--;
> +}
> +
> +bool intel_de_unclaimed_mmio_detected(struct intel_display *display)
> +{
> +	bool ret;
> +
> +	if (!display->mmio.funcs->check_for_unclaimed_mmio)
> +		return false;
> +
> +	spin_lock_irq(&display->mmio.lock);
> +	ret = display->mmio.funcs->check_for_unclaimed_mmio(display);
> +	spin_unlock_irq(&display->mmio.lock);
> +
> +	return ret;
> +}
> +
> +bool intel_de_arm_unclaimed_mmio_detection(struct intel_display *display)
> +{
> +	bool ret = false;
> +
> +	if (!display->mmio.funcs->check_for_unclaimed_mmio)
> +		return false;
> +
> +	spin_lock_irq(&display->mmio.lock);
> +
> +	if (display->mmio.unclaimed_mmio_check <= 0)
> +		goto out;
> +
> +	if (display->mmio.funcs->check_for_unclaimed_mmio(display)) {
> +		if (!display->params.mmio_debug) {
> +			drm_dbg_kms(display->drm,
> +				    "Unclaimed register detected, "
> +				    "enabling oneshot unclaimed register reporting. "
> +				    "Please use i915.mmio_debug=N for more information.\n");
> +			display->params.mmio_debug++;
> +		}
> +		display->mmio.unclaimed_mmio_check--;

Side note, with the current usage (both before and after the patch) this
could be replaced with a bool instead of an int. Maybe there's some idea
behind it being an int.

> +		ret = true;
> +	}
> +
> +out:
> +	spin_unlock_irq(&display->mmio.lock);
> +
> +	return ret;
> +}
> +
>  #define __MMIO_WAKELOCK		BIT(0)
>  #define __MMIO_LOCK		BIT(1)
> +#define __MMIO_UNCLAIMED	BIT(2)
>  
>  static __always_inline void
>  __mmio_wakelock_pre(struct intel_display *display, intel_reg_t reg,
> @@ -198,6 +318,22 @@ __mmio_lock_post(struct intel_display *display, unsigned long irqflags,
>  		spin_unlock_irqrestore(&display->mmio.lock, irqflags);
>  }
>  
> +static __always_inline void
> +__mmio_unclaimed_pre(struct intel_display *display, intel_reg_t reg,
> +		     const bool write, const unsigned int mmio_flags)
> +{
> +	if (mmio_flags & __MMIO_UNCLAIMED)
> +		check_unclaimed_mmio_pre(display, reg, write);
> +}
> +
> +static __always_inline void
> +__mmio_unclaimed_post(struct intel_display *display, intel_reg_t reg,
> +		      const bool write, const unsigned int mmio_flags)
> +{
> +	if (mmio_flags & __MMIO_UNCLAIMED)
> +		check_unclaimed_mmio_post(display, reg, write);
> +}
> +
>  static __always_inline u32
>  __intel_de_read(struct intel_display *display, intel_reg_t reg,
>  		const unsigned int mmio_flags)
> @@ -207,9 +343,11 @@ __intel_de_read(struct intel_display *display, intel_reg_t reg,
>  
>  	__mmio_wakelock_pre(display, reg, mmio_flags);
>  	__mmio_lock_pre(display, &irqflags, mmio_flags);
> +	__mmio_unclaimed_pre(display, reg, false, mmio_flags);
>  
>  	val = intel_uncore_read(__to_uncore(display), reg);
>  
> +	__mmio_unclaimed_post(display, reg, false, mmio_flags);
>  	__mmio_lock_post(display, irqflags, mmio_flags);
>  	__mmio_wakelock_post(display, reg, mmio_flags);
>  
> @@ -224,9 +362,11 @@ __intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
>  
>  	__mmio_wakelock_pre(display, reg, mmio_flags);
>  	__mmio_lock_pre(display, &irqflags, mmio_flags);
> +	__mmio_unclaimed_pre(display, reg, true, mmio_flags);
>  
>  	intel_uncore_write(__to_uncore(display), reg, val);
>  
> +	__mmio_unclaimed_post(display, reg, true, mmio_flags);
>  	__mmio_lock_post(display, irqflags, mmio_flags);
>  	__mmio_wakelock_post(display, reg, mmio_flags);
>  }
> @@ -269,6 +409,32 @@ static const struct intel_mmio_funcs snb_mmio_funcs = {
>  	.write = snb_mmio_write,
>  };
>  
> +#define IVB_MMIO_FLAGS (__MMIO_LOCK | __MMIO_UNCLAIMED)
> +
> +static u32 ivb_mmio_read(struct intel_display *display, intel_reg_t reg)
> +{
> +	return __intel_de_read(display, reg, IVB_MMIO_FLAGS);
> +}
> +
> +static void ivb_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
> +{
> +	__intel_de_write(display, reg, val, IVB_MMIO_FLAGS);
> +}
> +
> +#undef IVB_MMIO_FLAGS
> +
> +static const struct intel_mmio_funcs ivb_mmio_funcs = {
> +	.read = ivb_mmio_read,
> +	.write = ivb_mmio_write,
> +	.check_for_unclaimed_mmio = ivb_check_for_unclaimed_mmio,
> +};
> +
> +static const struct intel_mmio_funcs vlv_mmio_funcs = {
> +	.read = ivb_mmio_read,
> +	.write = ivb_mmio_write,
> +	.check_for_unclaimed_mmio = vlv_check_for_unclaimed_mmio,
> +};
> +
>  #define LNL_MMIO_FLAGS __MMIO_WAKELOCK
>  
>  static u32 lnl_mmio_read(struct intel_display *display, intel_reg_t reg)
> @@ -304,7 +470,11 @@ void intel_de_init(struct intel_display *display)
>  	spin_lock_init(&display->mmio.lock);
>  
>  	if (driver_is_i915()) {
> -		if (DISPLAY_VER(display) >= 6)
> +		if (display->platform.valleyview || display->platform.cherryview)
> +			display->mmio.funcs = &vlv_mmio_funcs;
> +		else if (DISPLAY_VER(display) >= 7)
> +			display->mmio.funcs = &ivb_mmio_funcs;
> +		else if (DISPLAY_VER(display) >= 6)
>  			display->mmio.funcs = &snb_mmio_funcs;
>  		else
>  			display->mmio.funcs = &i9xx_mmio_funcs;
> @@ -314,4 +484,7 @@ void intel_de_init(struct intel_display *display)
>  		else
>  			display->mmio.funcs = &i9xx_mmio_funcs;
>  	}
> +
> +	if (display->mmio.funcs->check_for_unclaimed_mmio)
> +		display->mmio.unclaimed_mmio_check = 1;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
> index 760b8bc31f9b..310f81edc09d 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -14,6 +14,7 @@
>  struct intel_mmio_funcs {
>  	u32 (*read)(struct intel_display *display, intel_reg_t reg);
>  	void (*write)(struct intel_display *display, intel_reg_t reg, u32 val);
> +	bool (*check_for_unclaimed_mmio)(struct intel_display *display);
>  };
>  
>  static inline struct intel_uncore *__to_uncore(struct intel_display *display)
> @@ -22,6 +23,8 @@ static inline struct intel_uncore *__to_uncore(struct intel_display *display)
>  }
>  
>  void intel_de_init(struct intel_display *display);
> +bool intel_de_unclaimed_mmio_detected(struct intel_display *display);
> +bool intel_de_arm_unclaimed_mmio_detection(struct intel_display *display);
>  
>  u8 intel_de_read8(struct intel_display *display, intel_reg_t reg);
>  void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index cf9190969da7..1077cc27052d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7740,7 +7740,6 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>  static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  {
>  	struct intel_display *display = to_intel_display(state);
> -	struct intel_uncore *uncore = to_intel_uncore(display->drm);
>  	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
>  	struct intel_crtc *crtc;
>  	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
> @@ -7954,7 +7953,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		 * so enable debugging for the next modeset - and hope we catch
>  		 * the culprit.
>  		 */
> -		intel_uncore_arm_unclaimed_mmio_detection(uncore);
> +		intel_de_arm_unclaimed_mmio_detection(display);
>  	}
>  
>  	power_async_delay = intel_display_power_select_target_dc_state(state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index aded2af8c92a..cb18ee040b5d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -539,11 +539,18 @@ struct intel_display {
>  		 * serializes all display register accesses done
>  		 * using intel_de_{read,write}(), but not those
>  		 * done using intel_de_{read,write}_fw().
> +		 *
> +		 * The lock also protects mmio.mmio_debug and
> +		 * mmio.unclaimed_mmio_check.
>  		 */
>  		spinlock_t lock;
>  
>  		struct intel_uncore *uncore;
>  		const struct intel_mmio_funcs *funcs;
> +
> +		/* protected by mmio.lock */
> +		int mmio_debug;
> +		int unclaimed_mmio_check;
>  	} mmio;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 0c7bec7d7f01..778d6c7ca4c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -30,6 +30,7 @@
>  #include "intel_crtc.h"
>  #include "intel_cursor.h"
>  #include "intel_dbuf_bw.h"
> +#include "intel_de.h"
>  #include "intel_display_clock_gating.h"
>  #include "intel_display_core.h"
>  #include "intel_display_debugfs.h"
> @@ -973,3 +974,17 @@ void intel_display_driver_pm_runtime_resume(struct intel_display *display)
>  
>  	skl_watermark_ipc_update(display);
>  }
> +
> +void intel_display_driver_mmio_resume_early(struct intel_display *display)
> +{
> +	if (intel_de_unclaimed_mmio_detected(display))
> +		drm_dbg_kms(display->drm,
> +			    "Unclaimed access during suspend, bios?\n");
> +}
> +
> +void intel_display_driver_mmio_suspend_late(struct intel_display *display)
> +{
> +	if (intel_de_arm_unclaimed_mmio_detection(display))
> +		drm_err(display->drm,
> +			"Unclaimed access detected prior to suspending\n");
> +}

Not super thrilled about adding more display hooks for the drivers to
call. Can we move these to existing display hooks in a follow-up?

> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.h b/drivers/gpu/drm/i915/display/intel_display_driver.h
> index 1ae2ad7e95f6..6f04a92902fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.h
> @@ -32,6 +32,9 @@ void intel_display_driver_pm_suspend_late(struct intel_display *display, bool s2
>  void intel_display_driver_pm_resume_early(struct intel_display *display);
>  void intel_display_driver_pm_resume(struct intel_display *display);
>  
> +void intel_display_driver_mmio_suspend_late(struct intel_display *display);
> +void intel_display_driver_mmio_resume_early(struct intel_display *display);
> +
>  /* interface for intel_display_reset.c */
>  int __intel_display_driver_resume(struct intel_display *display,
>  				  struct drm_atomic_commit *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
> index ca0ef466bb10..ace3081461de 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
> @@ -143,6 +143,10 @@ intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
>  	"(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) "
>  	"Default: -1");
>  
> +intel_display_param_named(mmio_debug, int, 0400,
> +	"Enable the MMIO debug code for the first N failures (default: off). "
> +	"This may negatively affect performance.");
> +

Perhaps this should be changed to _unsafe (in a follow-up).

>  __maybe_unused
>  static void _param_print_bool(struct drm_printer *p, const char *driver_name,
>  			      const char *name, bool val)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
> index 5c5a1a1358c3..bcbca95318d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
> @@ -51,6 +51,7 @@ struct drm_printer;
>  	param(bool, psr_safest_params, false, 0400) \
>  	param(bool, enable_psr2_sel_fetch, true, 0400) \
>  	param(int, enable_dmc_wl, -1, 0400) \
> +	param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \
>  	/*
>  	 * Debugfs-only knob (per-device): no matching module_param is registered
>  	 * in intel_display_params.c on purpose. Runtime-toggle via debugfs.
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index bbdbc27629d7..f213bdffcc8d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -3287,4 +3287,12 @@ enum skl_power_gate {
>  #define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
>  #define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
>  
> +#define FPGA_DBG		_MMIO(0x42300)
> +#define   FPGA_DBG_RM_NOCLAIM	REG_BIT(31)
> +
> +#define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
> +#define   CLAIM_ER_CLR		REG_BIT(31)
> +#define   CLAIM_ER_OVERFLOW	REG_BIT(16)
> +#define   CLAIM_ER_CTR_MASK	REG_GENMASK(15, 0)
> +
>  #endif /* __INTEL_DISPLAY_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 5787f40ac62e..923b239714b7 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -238,8 +238,6 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
>  
>  	intel_step_init(dev_priv);
>  
> -	intel_uncore_mmio_debug_init_early(dev_priv);
> -
>  	spin_lock_init(&dev_priv->gpu_error.lock);
>  
>  	intel_sbi_init(display);
> @@ -1281,6 +1279,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
>  		drm_err(&dev_priv->drm,
>  			"Resume prepare failed: %d, continuing anyway\n", ret);
>  
> +	intel_display_driver_mmio_resume_early(display);
> +

There's intel_display_driver_pm_resume_early() just below context here
that could call this.

>  	for_each_gt(gt, dev_priv, i)
>  		intel_gt_resume_early(gt);
>  
> @@ -1546,9 +1546,7 @@ static int i915_pm_runtime_suspend(struct device *kdev)
>  	enable_rpm_wakeref_asserts(rpm);
>  	intel_runtime_pm_driver_release(rpm);
>  
> -	if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
> -		drm_err(&dev_priv->drm,
> -			"Unclaimed access detected prior to suspending\n");
> +	intel_display_driver_mmio_suspend_late(display);

Maybe this could be in intel_display_driver_pm_runtime_suspend_late()?

>  
>  	/*
>  	 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
> @@ -1587,9 +1585,7 @@ static int i915_pm_runtime_resume(struct device *kdev)
>  	if (root_pdev)
>  		pci_d3cold_enable(root_pdev);
>  
> -	if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
> -		drm_dbg(&dev_priv->drm,
> -			"Unclaimed access during suspend, bios?\n");
> +	intel_display_driver_mmio_resume_early(display);

The below could call this.

I guess the juggling could be in a follow-up, since the patch is already
a bit much and hard to review.

>  	intel_display_driver_pm_runtime_resume_early(display);
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index dafee3dcd1c5..95637ada00d7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -185,7 +185,6 @@ struct drm_i915_private {
>  	struct i915_dsm dsm;
>  
>  	struct intel_uncore uncore;
> -	struct intel_uncore_mmio_debug mmio_debug;
>  
>  	struct i915_virtual_gpu vgpu;
>  
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 34ed82bb1b1a..377d3c005580 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -88,10 +88,6 @@ i915_param_named_unsafe(force_probe, charp, 0400,
>  i915_param_named(memtest, bool, 0400,
>  	"Perform a read/write test of all device memory on module load (default: off)");
>  
> -i915_param_named(mmio_debug, int, 0400,
> -	"Enable the MMIO debug code for the first N failures (default: off). "
> -	"This may negatively affect performance.");
> -
>  i915_param_named_unsafe(enable_guc, int, 0400,
>  	"Enable GuC load for GuC submission and/or HuC load. "
>  	"Required functionality can be selected using bitmask values. "
> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> index 4d9d4cd3220d..0cb46609f4a3 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -53,7 +53,6 @@ struct drm_printer;
>  	param(char *, huc_firmware_path, NULL, 0400) \
>  	param(char *, gsc_firmware_path, NULL, 0400) \
>  	param(bool, memtest, false, 0400) \
> -	param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \
>  	param(unsigned int, reset, 3, 0600) \
>  	param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
>  	param(unsigned int, request_timeout_ms, CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d873072b7a92..806e5a56471d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -325,13 +325,6 @@
>  #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
>  #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
>  
> -#define FPGA_DBG		_MMIO(0x42300)
> -#define   FPGA_DBG_RM_NOCLAIM	REG_BIT(31)
> -
> -#define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
> -#define   CLAIM_ER_CLR		REG_BIT(31)
> -#define   CLAIM_ER_OVERFLOW	REG_BIT(16)
> -#define   CLAIM_ER_CTR_MASK	REG_GENMASK(15, 0)
>  
>  #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
>  #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index abd695e880c1..b53059c1a782 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -56,15 +56,6 @@ fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
>  	uncore->fw_get_funcs->force_wake_get(uncore, fw_domains);
>  }
>  
> -void
> -intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915)
> -{
> -	spin_lock_init(&i915->mmio_debug.lock);
> -	i915->mmio_debug.unclaimed_mmio_check = 1;
> -
> -	i915->uncore.debug = &i915->mmio_debug;
> -}
> -
>  static const char * const forcewake_domain_names[] = {
>  	"render",
>  	"gt",
> @@ -512,66 +503,6 @@ intel_uncore_forcewake_reset(struct intel_uncore *uncore)
>  	return fw; /* track the lost user forcewake domains */
>  }
>  
> -static bool
> -fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
> -{
> -	u32 dbg;
> -
> -	dbg = __raw_uncore_read32(uncore, FPGA_DBG);
> -	if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
> -		return false;
> -
> -	/*
> -	 * Bugs in PCI programming (or failing hardware) can occasionally cause
> -	 * us to lose access to the MMIO BAR.  When this happens, register
> -	 * reads will come back with 0xFFFFFFFF for every register and things
> -	 * go bad very quickly.  Let's try to detect that special case and at
> -	 * least try to print a more informative message about what has
> -	 * happened.
> -	 *
> -	 * During normal operation the FPGA_DBG register has several unused
> -	 * bits that will always read back as 0's so we can use them as canaries
> -	 * to recognize when MMIO accesses are just busted.
> -	 */
> -	if (unlikely(dbg == ~0))
> -		drm_err(&uncore->i915->drm,
> -			"Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n");
> -
> -	__raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
> -
> -	return true;
> -}
> -
> -static bool
> -vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
> -{
> -	u32 cer;
> -
> -	cer = __raw_uncore_read32(uncore, CLAIM_ER);
> -	if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
> -		return false;
> -
> -	__raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
> -
> -	return true;
> -}
> -
> -static bool
> -check_for_unclaimed_mmio(struct intel_uncore *uncore)
> -{
> -	bool ret = false;
> -
> -	lockdep_assert_held(&uncore->debug->lock);
> -
> -	if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
> -		ret |= fpga_check_for_unclaimed_mmio(uncore);
> -
> -	if (intel_uncore_has_dbg_unclaimed(uncore))
> -		ret |= vlv_check_for_unclaimed_mmio(uncore);
> -
> -	return ret;
> -}
> -
>  static void forcewake_early_sanitize(struct intel_uncore *uncore,
>  				     unsigned int restore_forcewake)
>  {
> @@ -617,9 +548,6 @@ void intel_uncore_resume_early(struct intel_uncore *uncore)
>  {
>  	unsigned int restore_forcewake;
>  
> -	if (intel_uncore_unclaimed_mmio(uncore))
> -		drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n");
> -
>  	if (!intel_uncore_has_forcewake(uncore))
>  		return;
>  
> @@ -1734,59 +1662,6 @@ ilk_dummy_write(struct intel_uncore *uncore)
>  	__raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0);
>  }
>  
> -static void
> -__unclaimed_reg_debug(struct intel_uncore *uncore,
> -		      const i915_reg_t reg,
> -		      const bool read)
> -{
> -	if (drm_WARN(&uncore->i915->drm,
> -		     check_for_unclaimed_mmio(uncore),
> -		     "Unclaimed %s register 0x%x\n",
> -		     read ? "read from" : "write to",
> -		     i915_mmio_reg_offset(reg)))
> -		/* Only report the first N failures */
> -		uncore->i915->params.mmio_debug--;
> -}
> -
> -static void
> -__unclaimed_previous_reg_debug(struct intel_uncore *uncore,
> -			       const i915_reg_t reg,
> -			       const bool read)
> -{
> -	if (check_for_unclaimed_mmio(uncore))
> -		drm_dbg(&uncore->i915->drm,
> -			"Unclaimed access detected before %s register 0x%x\n",
> -			read ? "read from" : "write to",
> -			i915_mmio_reg_offset(reg));
> -}
> -
> -static inline bool __must_check
> -unclaimed_reg_debug_header(struct intel_uncore *uncore,
> -			   const i915_reg_t reg, const bool read)
> -{
> -	if (likely(!uncore->i915->params.mmio_debug) || !uncore->debug)
> -		return false;
> -
> -	/* interrupts are disabled and re-enabled around uncore->lock usage */
> -	lockdep_assert_held(&uncore->lock);
> -
> -	spin_lock(&uncore->debug->lock);
> -	__unclaimed_previous_reg_debug(uncore, reg, read);
> -
> -	return true;
> -}
> -
> -static inline void
> -unclaimed_reg_debug_footer(struct intel_uncore *uncore,
> -			   const i915_reg_t reg, const bool read)
> -{
> -	/* interrupts are disabled and re-enabled around uncore->lock usage */
> -	lockdep_assert_held(&uncore->lock);
> -
> -	__unclaimed_reg_debug(uncore, reg, read);
> -	spin_unlock(&uncore->debug->lock);
> -}
> -
>  #define __vgpu_read(x) \
>  static u##x \
>  vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
> @@ -1842,15 +1717,11 @@ __gen2_read(64)
>  #define GEN6_READ_HEADER(x) \
>  	u32 offset = i915_mmio_reg_offset(reg); \
>  	unsigned long irqflags; \
> -	bool unclaimed_reg_debug; \
>  	u##x val = 0; \
>  	assert_rpm_wakelock_held(uncore->rpm); \
> -	spin_lock_irqsave(&uncore->lock, irqflags); \
> -	unclaimed_reg_debug = unclaimed_reg_debug_header(uncore, reg, true)
> +	spin_lock_irqsave(&uncore->lock, irqflags)
>  
>  #define GEN6_READ_FOOTER \
> -	if (unclaimed_reg_debug) \
> -		unclaimed_reg_debug_footer(uncore, reg, true);	\
>  	spin_unlock_irqrestore(&uncore->lock, irqflags); \
>  	trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
>  	return val
> @@ -1948,15 +1819,11 @@ __gen2_write(32)
>  #define GEN6_WRITE_HEADER \
>  	u32 offset = i915_mmio_reg_offset(reg); \
>  	unsigned long irqflags; \
> -	bool unclaimed_reg_debug; \
>  	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
>  	assert_rpm_wakelock_held(uncore->rpm); \
> -	spin_lock_irqsave(&uncore->lock, irqflags); \
> -	unclaimed_reg_debug = unclaimed_reg_debug_header(uncore, reg, false)
> +	spin_lock_irqsave(&uncore->lock, irqflags)
>  
>  #define GEN6_WRITE_FOOTER \
> -	if (unclaimed_reg_debug) \
> -		unclaimed_reg_debug_footer(uncore, reg, false); \
>  	spin_unlock_irqrestore(&uncore->lock, irqflags)
>  
>  #define __gen6_write(x) \
> @@ -2490,7 +2357,6 @@ static int sanity_check_mmio_access(struct intel_uncore *uncore)
>  int intel_uncore_init_mmio(struct intel_uncore *uncore)
>  {
>  	struct drm_i915_private *i915 = uncore->i915;
> -	struct intel_display *display = i915->display;
>  	int ret;
>  
>  	ret = sanity_check_mmio_access(uncore);
> @@ -2525,19 +2391,9 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
>  	GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
>  	GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
>  
> -	if (HAS_FPGA_DBG_UNCLAIMED(display))

This macro becomes unused, along with struct intel_display_device_info
.has_fpga_dbg member. I think it's fine to remove this from the device
info, since it's not coming and going, but is fairly stable across
platforms. Again, can be follow-up.

BR,
Jani.

> -		uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
> -
> -	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> -		uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
> -
>  	if (IS_GRAPHICS_VER(i915, 6, 7))
>  		uncore->flags |= UNCORE_HAS_FIFO;
>  
> -	/* clear out unclaimed reg detection bit */
> -	if (intel_uncore_unclaimed_mmio(uncore))
> -		drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n");
> -
>  	return 0;
>  }
>  
> @@ -2800,51 +2656,6 @@ int __intel_wait_for_register(struct intel_uncore *uncore,
>  	return ret;
>  }
>  
> -bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
> -{
> -	bool ret;
> -
> -	if (!uncore->debug)
> -		return false;
> -
> -	spin_lock_irq(&uncore->debug->lock);
> -	ret = check_for_unclaimed_mmio(uncore);
> -	spin_unlock_irq(&uncore->debug->lock);
> -
> -	return ret;
> -}
> -
> -bool
> -intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
> -{
> -	bool ret = false;
> -
> -	if (drm_WARN_ON(&uncore->i915->drm, !uncore->debug))
> -		return false;
> -
> -	spin_lock_irq(&uncore->debug->lock);
> -
> -	if (unlikely(uncore->debug->unclaimed_mmio_check <= 0))
> -		goto out;
> -
> -	if (unlikely(check_for_unclaimed_mmio(uncore))) {
> -		if (!uncore->i915->params.mmio_debug) {
> -			drm_dbg(&uncore->i915->drm,
> -				"Unclaimed register detected, "
> -				"enabling oneshot unclaimed register reporting. "
> -				"Please use i915.mmio_debug=N for more information.\n");
> -			uncore->i915->params.mmio_debug++;
> -		}
> -		uncore->debug->unclaimed_mmio_check--;
> -		ret = true;
> -	}
> -
> -out:
> -	spin_unlock_irq(&uncore->debug->lock);
> -
> -	return ret;
> -}
> -
>  /**
>   * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
>   * 				    a register
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index 4ec7c545d04e..9047d7d4d855 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -39,11 +39,6 @@ struct intel_runtime_pm;
>  struct intel_uncore;
>  struct intel_gt;
>  
> -struct intel_uncore_mmio_debug {
> -	spinlock_t lock; /** lock is also taken in irq contexts. */
> -	int unclaimed_mmio_check;
> -};
> -
>  enum forcewake_domain_id {
>  	FW_DOMAIN_ID_RENDER = 0,
>  	FW_DOMAIN_ID_GT,        /* also includes blitter engine */
> @@ -142,8 +137,6 @@ struct intel_uncore {
>  
>  	unsigned int flags;
>  #define UNCORE_HAS_FORCEWAKE		BIT(0)
> -#define UNCORE_HAS_FPGA_DBG_UNCLAIMED	BIT(1)
> -#define UNCORE_HAS_DBG_UNCLAIMED	BIT(2)
>  #define UNCORE_HAS_FIFO			BIT(3)
>  #define UNCORE_NEEDS_FLR_ON_FINI	BIT(4)
>  
> @@ -180,8 +173,6 @@ struct intel_uncore {
>  	} *fw_domain[FW_DOMAIN_ID_COUNT];
>  
>  	unsigned int user_forcewake_count;
> -
> -	struct intel_uncore_mmio_debug *debug;
>  };
>  
>  /* Iterate over initialised fw domains */
> @@ -198,18 +189,6 @@ intel_uncore_has_forcewake(const struct intel_uncore *uncore)
>  	return uncore->flags & UNCORE_HAS_FORCEWAKE;
>  }
>  
> -static inline bool
> -intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore *uncore)
> -{
> -	return uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED;
> -}
> -
> -static inline bool
> -intel_uncore_has_dbg_unclaimed(const struct intel_uncore *uncore)
> -{
> -	return uncore->flags & UNCORE_HAS_DBG_UNCLAIMED;
> -}
> -
>  static inline bool
>  intel_uncore_has_fifo(const struct intel_uncore *uncore)
>  {
> @@ -228,15 +207,12 @@ intel_uncore_set_flr_on_fini(struct intel_uncore *uncore)
>  	return uncore->flags |= UNCORE_NEEDS_FLR_ON_FINI;
>  }
>  
> -void intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915);
>  void intel_uncore_init_early(struct intel_uncore *uncore,
>  			     struct intel_gt *gt);
>  int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr);
>  int intel_uncore_init_mmio(struct intel_uncore *uncore);
>  void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
>  					  struct intel_gt *gt);
> -bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
> -bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
>  void intel_uncore_cleanup_mmio(struct intel_uncore *uncore);
>  void intel_uncore_fini_mmio(struct drm_device *dev, void *data);
>  void intel_uncore_suspend(struct intel_uncore *uncore);

-- 
Jani Nikula, Intel

Re: [PATCH 7/9] drm/i915/de: Move unclaimed mmio detection into display code

[Ville Syrjälä]

On Fri, Nov 06, 2026 at 06:39:50PM +0200, Jani Nikula wrote:
> On Thu, 05 Nov 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The FPGA_DBG/CLAIM_ER unclaimed mmio access detection only
> > works for display registers. Therefore checking it for GT
> > registers/etc is completely pointless. Hoist the whole thing
> > into the display code. Eventually we'll also want to hook this
> > up for xe, but for now we keep it i915 only to avoid too many
> > functional changes in one go.
> >
> > Note that i915 used a separate spinlock to protect the
> > mmio debug tracking. But basically whenever it would grab that
> > lock it was already holding uncore.lock, so the double locking
> > was rather pointless. When moving this into the display code
> > we'll just protect it all with the same display mmio.lock that
> > already provides any needed serialization of register accesses.
> >
> > This will of course speed up the non-fw GT register accesses
> > with mmio debug enabled since we never do the two extra
> > FPGA_DBG/CLAIM_ER reads for them.
> >
> > Note that we do lose the FPGA_DBG!=0xffffffff sanity check for
> > non-display register accesses now. Possibly the GT side should
> > use some harmless GT register for that instead. But I didn't
> > bother looking for one at this time.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Some commentary inline, but didn't spot anything wrong, really.
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_de.c       | 175 +++++++++++++++-
> >  drivers/gpu/drm/i915/display/intel_de.h       |   3 +
> >  drivers/gpu/drm/i915/display/intel_display.c  |   3 +-
> >  .../gpu/drm/i915/display/intel_display_core.h |   7 +
> >  .../drm/i915/display/intel_display_driver.c   |  15 ++
> >  .../drm/i915/display/intel_display_driver.h   |   3 +
> >  .../drm/i915/display/intel_display_params.c   |   4 +
> >  .../drm/i915/display/intel_display_params.h   |   1 +
> >  .../gpu/drm/i915/display/intel_display_regs.h |   8 +
> >  drivers/gpu/drm/i915/i915_driver.c            |  12 +-
> >  drivers/gpu/drm/i915/i915_drv.h               |   1 -
> >  drivers/gpu/drm/i915/i915_params.c            |   4 -
> >  drivers/gpu/drm/i915/i915_params.h            |   1 -
> >  drivers/gpu/drm/i915/i915_reg.h               |   7 -
> >  drivers/gpu/drm/i915/intel_uncore.c           | 193 +-----------------
> >  drivers/gpu/drm/i915/intel_uncore.h           |  24 ---
> >  16 files changed, 222 insertions(+), 239 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> > index 8b7a4e696ff9..0a51105e0fba 100644
> > --- a/drivers/gpu/drm/i915/display/intel_de.c
> > +++ b/drivers/gpu/drm/i915/display/intel_de.c
> > @@ -8,6 +8,7 @@
> >  #include <drm/drm_print.h>
> >  
> >  #include "intel_de.h"
> > +#include "intel_display_regs.h"
> >  
> >  static int intel_de_wait_for_register(struct intel_display *display,
> >  				      intel_reg_t reg, u32 mask, u32 value,
> > @@ -163,8 +164,127 @@ u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
> >  	return intel_uncore_read16(__to_uncore(display), reg);
> >  }
> >  
> > +static bool ivb_check_for_unclaimed_mmio(struct intel_display *display)
> > +{
> > +	u32 dbg;
> > +
> > +	dbg = intel_de_read_fw(display, FPGA_DBG);
> > +	if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
> > +		return false;
> > +
> > +	/*
> > +	 * Bugs in PCI programming (or failing hardware) can occasionally cause
> > +	 * us to lose access to the MMIO BAR.  When this happens, register
> > +	 * reads will come back with 0xFFFFFFFF for every register and things
> > +	 * go bad very quickly.  Let's try to detect that special case and at
> > +	 * least try to print a more informative message about what has
> > +	 * happened.
> > +	 *
> > +	 * During normal operation the FPGA_DBG register has several unused
> > +	 * bits that will always read back as 0's so we can use them as canaries
> > +	 * to recognize when MMIO accesses are just busted.
> > +	 */
> > +	if (unlikely(dbg == ~0))
> > +		drm_err(display->drm,
> > +			"Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n");
> > +
> > +	intel_de_write_fw(display, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
> > +
> > +	return true;
> > +}
> > +
> > +static bool vlv_check_for_unclaimed_mmio(struct intel_display *display)
> > +{
> > +	u32 cer;
> > +
> > +	cer = intel_de_read_fw(display, CLAIM_ER);
> > +	if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
> > +		return false;
> > +
> > +	intel_de_write_fw(display, CLAIM_ER, CLAIM_ER_CLR);
> > +
> > +	return true;
> > +}
> > +
> > +static void check_unclaimed_mmio_pre(struct intel_display *display,
> > +				     intel_reg_t reg, bool write)
> > +{
> > +	lockdep_assert_held(&display->mmio.lock);
> > +
> > +	if (!display->params.mmio_debug)
> > +		return;
> > +
> > +	if (display->mmio.funcs->check_for_unclaimed_mmio(display))
> > +		drm_dbg_kms(display->drm,
> > +			    "Unclaimed access detected before %s register 0x%x\n",
> > +			    write ? "write to" : "read from",
> > +			    i915_mmio_reg_offset(reg));
> > +}
> > +
> > +static void check_unclaimed_mmio_post(struct intel_display *display,
> > +				      intel_reg_t reg, bool write)
> > +{
> > +	lockdep_assert_held(&display->mmio.lock);
> > +
> > +	if (!display->params.mmio_debug)
> > +		return;
> > +
> > +	if (drm_WARN(display->drm,
> > +		     display->mmio.funcs->check_for_unclaimed_mmio(display),
> > +		     "Unclaimed %s register 0x%x\n",
> > +		     write ? "write to" : "read from",
> > +		     i915_mmio_reg_offset(reg)))
> > +		/* Only report the first N failures */
> > +		display->params.mmio_debug--;
> > +}
> > +
> > +bool intel_de_unclaimed_mmio_detected(struct intel_display *display)
> > +{
> > +	bool ret;
> > +
> > +	if (!display->mmio.funcs->check_for_unclaimed_mmio)
> > +		return false;
> > +
> > +	spin_lock_irq(&display->mmio.lock);
> > +	ret = display->mmio.funcs->check_for_unclaimed_mmio(display);
> > +	spin_unlock_irq(&display->mmio.lock);
> > +
> > +	return ret;
> > +}
> > +
> > +bool intel_de_arm_unclaimed_mmio_detection(struct intel_display *display)
> > +{
> > +	bool ret = false;
> > +
> > +	if (!display->mmio.funcs->check_for_unclaimed_mmio)
> > +		return false;
> > +
> > +	spin_lock_irq(&display->mmio.lock);
> > +
> > +	if (display->mmio.unclaimed_mmio_check <= 0)
> > +		goto out;
> > +
> > +	if (display->mmio.funcs->check_for_unclaimed_mmio(display)) {
> > +		if (!display->params.mmio_debug) {
> > +			drm_dbg_kms(display->drm,
> > +				    "Unclaimed register detected, "
> > +				    "enabling oneshot unclaimed register reporting. "
> > +				    "Please use i915.mmio_debug=N for more information.\n");
> > +			display->params.mmio_debug++;
> > +		}
> > +		display->mmio.unclaimed_mmio_check--;
> 
> Side note, with the current usage (both before and after the patch) this
> could be replaced with a bool instead of an int. Maybe there's some idea
> behind it being an int.

Yeah, that could also help make it lockless since no rmw. But the
rmw with the modparam is still a problem. The use of the modparam
here is of course already racy if anyone changes the value via
debugfs at runtime.

> 
> > +		ret = true;
> > +	}
> > +
> > +out:
> > +	spin_unlock_irq(&display->mmio.lock);
> > +
> > +	return ret;
> > +}
> > +
> >  #define __MMIO_WAKELOCK		BIT(0)
> >  #define __MMIO_LOCK		BIT(1)
> > +#define __MMIO_UNCLAIMED	BIT(2)
> >  
> >  static __always_inline void
> >  __mmio_wakelock_pre(struct intel_display *display, intel_reg_t reg,
> > @@ -198,6 +318,22 @@ __mmio_lock_post(struct intel_display *display, unsigned long irqflags,
> >  		spin_unlock_irqrestore(&display->mmio.lock, irqflags);
> >  }
> >  
> > +static __always_inline void
> > +__mmio_unclaimed_pre(struct intel_display *display, intel_reg_t reg,
> > +		     const bool write, const unsigned int mmio_flags)
> > +{
> > +	if (mmio_flags & __MMIO_UNCLAIMED)
> > +		check_unclaimed_mmio_pre(display, reg, write);
> > +}
> > +
> > +static __always_inline void
> > +__mmio_unclaimed_post(struct intel_display *display, intel_reg_t reg,
> > +		      const bool write, const unsigned int mmio_flags)
> > +{
> > +	if (mmio_flags & __MMIO_UNCLAIMED)
> > +		check_unclaimed_mmio_post(display, reg, write);
> > +}
> > +
> >  static __always_inline u32
> >  __intel_de_read(struct intel_display *display, intel_reg_t reg,
> >  		const unsigned int mmio_flags)
> > @@ -207,9 +343,11 @@ __intel_de_read(struct intel_display *display, intel_reg_t reg,
> >  
> >  	__mmio_wakelock_pre(display, reg, mmio_flags);
> >  	__mmio_lock_pre(display, &irqflags, mmio_flags);
> > +	__mmio_unclaimed_pre(display, reg, false, mmio_flags);
> >  
> >  	val = intel_uncore_read(__to_uncore(display), reg);
> >  
> > +	__mmio_unclaimed_post(display, reg, false, mmio_flags);
> >  	__mmio_lock_post(display, irqflags, mmio_flags);
> >  	__mmio_wakelock_post(display, reg, mmio_flags);
> >  
> > @@ -224,9 +362,11 @@ __intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
> >  
> >  	__mmio_wakelock_pre(display, reg, mmio_flags);
> >  	__mmio_lock_pre(display, &irqflags, mmio_flags);
> > +	__mmio_unclaimed_pre(display, reg, true, mmio_flags);
> >  
> >  	intel_uncore_write(__to_uncore(display), reg, val);
> >  
> > +	__mmio_unclaimed_post(display, reg, true, mmio_flags);
> >  	__mmio_lock_post(display, irqflags, mmio_flags);
> >  	__mmio_wakelock_post(display, reg, mmio_flags);
> >  }
> > @@ -269,6 +409,32 @@ static const struct intel_mmio_funcs snb_mmio_funcs = {
> >  	.write = snb_mmio_write,
> >  };
> >  
> > +#define IVB_MMIO_FLAGS (__MMIO_LOCK | __MMIO_UNCLAIMED)
> > +
> > +static u32 ivb_mmio_read(struct intel_display *display, intel_reg_t reg)
> > +{
> > +	return __intel_de_read(display, reg, IVB_MMIO_FLAGS);
> > +}
> > +
> > +static void ivb_mmio_write(struct intel_display *display, intel_reg_t reg, u32 val)
> > +{
> > +	__intel_de_write(display, reg, val, IVB_MMIO_FLAGS);
> > +}
> > +
> > +#undef IVB_MMIO_FLAGS
> > +
> > +static const struct intel_mmio_funcs ivb_mmio_funcs = {
> > +	.read = ivb_mmio_read,
> > +	.write = ivb_mmio_write,
> > +	.check_for_unclaimed_mmio = ivb_check_for_unclaimed_mmio,
> > +};
> > +
> > +static const struct intel_mmio_funcs vlv_mmio_funcs = {
> > +	.read = ivb_mmio_read,
> > +	.write = ivb_mmio_write,
> > +	.check_for_unclaimed_mmio = vlv_check_for_unclaimed_mmio,
> > +};
> > +
> >  #define LNL_MMIO_FLAGS __MMIO_WAKELOCK
> >  
> >  static u32 lnl_mmio_read(struct intel_display *display, intel_reg_t reg)
> > @@ -304,7 +470,11 @@ void intel_de_init(struct intel_display *display)
> >  	spin_lock_init(&display->mmio.lock);
> >  
> >  	if (driver_is_i915()) {
> > -		if (DISPLAY_VER(display) >= 6)
> > +		if (display->platform.valleyview || display->platform.cherryview)
> > +			display->mmio.funcs = &vlv_mmio_funcs;
> > +		else if (DISPLAY_VER(display) >= 7)
> > +			display->mmio.funcs = &ivb_mmio_funcs;
> > +		else if (DISPLAY_VER(display) >= 6)
> >  			display->mmio.funcs = &snb_mmio_funcs;
> >  		else
> >  			display->mmio.funcs = &i9xx_mmio_funcs;
> > @@ -314,4 +484,7 @@ void intel_de_init(struct intel_display *display)
> >  		else
> >  			display->mmio.funcs = &i9xx_mmio_funcs;
> >  	}
> > +
> > +	if (display->mmio.funcs->check_for_unclaimed_mmio)
> > +		display->mmio.unclaimed_mmio_check = 1;
> >  }
> > diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
> > index 760b8bc31f9b..310f81edc09d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_de.h
> > +++ b/drivers/gpu/drm/i915/display/intel_de.h
> > @@ -14,6 +14,7 @@
> >  struct intel_mmio_funcs {
> >  	u32 (*read)(struct intel_display *display, intel_reg_t reg);
> >  	void (*write)(struct intel_display *display, intel_reg_t reg, u32 val);
> > +	bool (*check_for_unclaimed_mmio)(struct intel_display *display);
> >  };
> >  
> >  static inline struct intel_uncore *__to_uncore(struct intel_display *display)
> > @@ -22,6 +23,8 @@ static inline struct intel_uncore *__to_uncore(struct intel_display *display)
> >  }
> >  
> >  void intel_de_init(struct intel_display *display);
> > +bool intel_de_unclaimed_mmio_detected(struct intel_display *display);
> > +bool intel_de_arm_unclaimed_mmio_detection(struct intel_display *display);
> >  
> >  u8 intel_de_read8(struct intel_display *display, intel_reg_t reg);
> >  void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index cf9190969da7..1077cc27052d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7740,7 +7740,6 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
> >  static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> >  {
> >  	struct intel_display *display = to_intel_display(state);
> > -	struct intel_uncore *uncore = to_intel_uncore(display->drm);
> >  	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> >  	struct intel_crtc *crtc;
> >  	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
> > @@ -7954,7 +7953,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> >  		 * so enable debugging for the next modeset - and hope we catch
> >  		 * the culprit.
> >  		 */
> > -		intel_uncore_arm_unclaimed_mmio_detection(uncore);
> > +		intel_de_arm_unclaimed_mmio_detection(display);
> >  	}
> >  
> >  	power_async_delay = intel_display_power_select_target_dc_state(state);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> > index aded2af8c92a..cb18ee040b5d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > @@ -539,11 +539,18 @@ struct intel_display {
> >  		 * serializes all display register accesses done
> >  		 * using intel_de_{read,write}(), but not those
> >  		 * done using intel_de_{read,write}_fw().
> > +		 *
> > +		 * The lock also protects mmio.mmio_debug and
> > +		 * mmio.unclaimed_mmio_check.
> >  		 */
> >  		spinlock_t lock;
> >  
> >  		struct intel_uncore *uncore;
> >  		const struct intel_mmio_funcs *funcs;
> > +
> > +		/* protected by mmio.lock */
> > +		int mmio_debug;
> > +		int unclaimed_mmio_check;
> >  	} mmio;
> >  
> >  	struct {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > index 0c7bec7d7f01..778d6c7ca4c8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > @@ -30,6 +30,7 @@
> >  #include "intel_crtc.h"
> >  #include "intel_cursor.h"
> >  #include "intel_dbuf_bw.h"
> > +#include "intel_de.h"
> >  #include "intel_display_clock_gating.h"
> >  #include "intel_display_core.h"
> >  #include "intel_display_debugfs.h"
> > @@ -973,3 +974,17 @@ void intel_display_driver_pm_runtime_resume(struct intel_display *display)
> >  
> >  	skl_watermark_ipc_update(display);
> >  }
> > +
> > +void intel_display_driver_mmio_resume_early(struct intel_display *display)
> > +{
> > +	if (intel_de_unclaimed_mmio_detected(display))
> > +		drm_dbg_kms(display->drm,
> > +			    "Unclaimed access during suspend, bios?\n");
> > +}
> > +
> > +void intel_display_driver_mmio_suspend_late(struct intel_display *display)
> > +{
> > +	if (intel_de_arm_unclaimed_mmio_detection(display))
> > +		drm_err(display->drm,
> > +			"Unclaimed access detected prior to suspending\n");
> > +}
> 
> Not super thrilled about adding more display hooks for the drivers to
> call. Can we move these to existing display hooks in a follow-up?
> 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.h b/drivers/gpu/drm/i915/display/intel_display_driver.h
> > index 1ae2ad7e95f6..6f04a92902fa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.h
> > @@ -32,6 +32,9 @@ void intel_display_driver_pm_suspend_late(struct intel_display *display, bool s2
> >  void intel_display_driver_pm_resume_early(struct intel_display *display);
> >  void intel_display_driver_pm_resume(struct intel_display *display);
> >  
> > +void intel_display_driver_mmio_suspend_late(struct intel_display *display);
> > +void intel_display_driver_mmio_resume_early(struct intel_display *display);
> > +
> >  /* interface for intel_display_reset.c */
> >  int __intel_display_driver_resume(struct intel_display *display,
> >  				  struct drm_atomic_commit *state,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
> > index ca0ef466bb10..ace3081461de 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
> > @@ -143,6 +143,10 @@ intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
> >  	"(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) "
> >  	"Default: -1");
> >  
> > +intel_display_param_named(mmio_debug, int, 0400,
> > +	"Enable the MMIO debug code for the first N failures (default: off). "
> > +	"This may negatively affect performance.");
> > +
> 
> Perhaps this should be changed to _unsafe (in a follow-up).
> 
> >  __maybe_unused
> >  static void _param_print_bool(struct drm_printer *p, const char *driver_name,
> >  			      const char *name, bool val)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
> > index 5c5a1a1358c3..bcbca95318d6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_params.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
> > @@ -51,6 +51,7 @@ struct drm_printer;
> >  	param(bool, psr_safest_params, false, 0400) \
> >  	param(bool, enable_psr2_sel_fetch, true, 0400) \
> >  	param(int, enable_dmc_wl, -1, 0400) \
> > +	param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \
> >  	/*
> >  	 * Debugfs-only knob (per-device): no matching module_param is registered
> >  	 * in intel_display_params.c on purpose. Runtime-toggle via debugfs.
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index bbdbc27629d7..f213bdffcc8d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -3287,4 +3287,12 @@ enum skl_power_gate {
> >  #define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
> >  #define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
> >  
> > +#define FPGA_DBG		_MMIO(0x42300)
> > +#define   FPGA_DBG_RM_NOCLAIM	REG_BIT(31)
> > +
> > +#define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
> > +#define   CLAIM_ER_CLR		REG_BIT(31)
> > +#define   CLAIM_ER_OVERFLOW	REG_BIT(16)
> > +#define   CLAIM_ER_CTR_MASK	REG_GENMASK(15, 0)
> > +
> >  #endif /* __INTEL_DISPLAY_REGS_H__ */
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> > index 5787f40ac62e..923b239714b7 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -238,8 +238,6 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
> >  
> >  	intel_step_init(dev_priv);
> >  
> > -	intel_uncore_mmio_debug_init_early(dev_priv);
> > -
> >  	spin_lock_init(&dev_priv->gpu_error.lock);
> >  
> >  	intel_sbi_init(display);
> > @@ -1281,6 +1279,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
> >  		drm_err(&dev_priv->drm,
> >  			"Resume prepare failed: %d, continuing anyway\n", ret);
> >  
> > +	intel_display_driver_mmio_resume_early(display);
> > +
> 
> There's intel_display_driver_pm_resume_early() just below context here
> that could call this.
> 
> >  	for_each_gt(gt, dev_priv, i)
> >  		intel_gt_resume_early(gt);
> >  
> > @@ -1546,9 +1546,7 @@ static int i915_pm_runtime_suspend(struct device *kdev)
> >  	enable_rpm_wakeref_asserts(rpm);
> >  	intel_runtime_pm_driver_release(rpm);
> >  
> > -	if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
> > -		drm_err(&dev_priv->drm,
> > -			"Unclaimed access detected prior to suspending\n");
> > +	intel_display_driver_mmio_suspend_late(display);
> 
> Maybe this could be in intel_display_driver_pm_runtime_suspend_late()?
> 
> >  
> >  	/*
> >  	 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
> > @@ -1587,9 +1585,7 @@ static int i915_pm_runtime_resume(struct device *kdev)
> >  	if (root_pdev)
> >  		pci_d3cold_enable(root_pdev);
> >  
> > -	if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
> > -		drm_dbg(&dev_priv->drm,
> > -			"Unclaimed access during suspend, bios?\n");
> > +	intel_display_driver_mmio_resume_early(display);
> 
> The below could call this.
> 
> I guess the juggling could be in a follow-up, since the patch is already
> a bit much and hard to review.

Yeah, for now I basically wanted to drop these exactly to the same
spot as before (or as close as possible without major surgery).
The entire init/suspend/resume thing is still a huge mess that'll
need some actual thinking to solve.

> 
> >  	intel_display_driver_pm_runtime_resume_early(display);
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index dafee3dcd1c5..95637ada00d7 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -185,7 +185,6 @@ struct drm_i915_private {
> >  	struct i915_dsm dsm;
> >  
> >  	struct intel_uncore uncore;
> > -	struct intel_uncore_mmio_debug mmio_debug;
> >  
> >  	struct i915_virtual_gpu vgpu;
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> > index 34ed82bb1b1a..377d3c005580 100644
> > --- a/drivers/gpu/drm/i915/i915_params.c
> > +++ b/drivers/gpu/drm/i915/i915_params.c
> > @@ -88,10 +88,6 @@ i915_param_named_unsafe(force_probe, charp, 0400,
> >  i915_param_named(memtest, bool, 0400,
> >  	"Perform a read/write test of all device memory on module load (default: off)");
> >  
> > -i915_param_named(mmio_debug, int, 0400,
> > -	"Enable the MMIO debug code for the first N failures (default: off). "
> > -	"This may negatively affect performance.");
> > -
> >  i915_param_named_unsafe(enable_guc, int, 0400,
> >  	"Enable GuC load for GuC submission and/or HuC load. "
> >  	"Required functionality can be selected using bitmask values. "
> > diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> > index 4d9d4cd3220d..0cb46609f4a3 100644
> > --- a/drivers/gpu/drm/i915/i915_params.h
> > +++ b/drivers/gpu/drm/i915/i915_params.h
> > @@ -53,7 +53,6 @@ struct drm_printer;
> >  	param(char *, huc_firmware_path, NULL, 0400) \
> >  	param(char *, gsc_firmware_path, NULL, 0400) \
> >  	param(bool, memtest, false, 0400) \
> > -	param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \
> >  	param(unsigned int, reset, 3, 0600) \
> >  	param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
> >  	param(unsigned int, request_timeout_ms, CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index d873072b7a92..806e5a56471d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -325,13 +325,6 @@
> >  #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
> >  #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
> >  
> > -#define FPGA_DBG		_MMIO(0x42300)
> > -#define   FPGA_DBG_RM_NOCLAIM	REG_BIT(31)
> > -
> > -#define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
> > -#define   CLAIM_ER_CLR		REG_BIT(31)
> > -#define   CLAIM_ER_OVERFLOW	REG_BIT(16)
> > -#define   CLAIM_ER_CTR_MASK	REG_GENMASK(15, 0)
> >  
> >  #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
> >  #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index abd695e880c1..b53059c1a782 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -56,15 +56,6 @@ fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
> >  	uncore->fw_get_funcs->force_wake_get(uncore, fw_domains);
> >  }
> >  
> > -void
> > -intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915)
> > -{
> > -	spin_lock_init(&i915->mmio_debug.lock);
> > -	i915->mmio_debug.unclaimed_mmio_check = 1;
> > -
> > -	i915->uncore.debug = &i915->mmio_debug;
> > -}
> > -
> >  static const char * const forcewake_domain_names[] = {
> >  	"render",
> >  	"gt",
> > @@ -512,66 +503,6 @@ intel_uncore_forcewake_reset(struct intel_uncore *uncore)
> >  	return fw; /* track the lost user forcewake domains */
> >  }
> >  
> > -static bool
> > -fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
> > -{
> > -	u32 dbg;
> > -
> > -	dbg = __raw_uncore_read32(uncore, FPGA_DBG);
> > -	if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
> > -		return false;
> > -
> > -	/*
> > -	 * Bugs in PCI programming (or failing hardware) can occasionally cause
> > -	 * us to lose access to the MMIO BAR.  When this happens, register
> > -	 * reads will come back with 0xFFFFFFFF for every register and things
> > -	 * go bad very quickly.  Let's try to detect that special case and at
> > -	 * least try to print a more informative message about what has
> > -	 * happened.
> > -	 *
> > -	 * During normal operation the FPGA_DBG register has several unused
> > -	 * bits that will always read back as 0's so we can use them as canaries
> > -	 * to recognize when MMIO accesses are just busted.
> > -	 */
> > -	if (unlikely(dbg == ~0))
> > -		drm_err(&uncore->i915->drm,
> > -			"Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n");
> > -
> > -	__raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
> > -
> > -	return true;
> > -}
> > -
> > -static bool
> > -vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
> > -{
> > -	u32 cer;
> > -
> > -	cer = __raw_uncore_read32(uncore, CLAIM_ER);
> > -	if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
> > -		return false;
> > -
> > -	__raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
> > -
> > -	return true;
> > -}
> > -
> > -static bool
> > -check_for_unclaimed_mmio(struct intel_uncore *uncore)
> > -{
> > -	bool ret = false;
> > -
> > -	lockdep_assert_held(&uncore->debug->lock);
> > -
> > -	if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
> > -		ret |= fpga_check_for_unclaimed_mmio(uncore);
> > -
> > -	if (intel_uncore_has_dbg_unclaimed(uncore))
> > -		ret |= vlv_check_for_unclaimed_mmio(uncore);
> > -
> > -	return ret;
> > -}
> > -
> >  static void forcewake_early_sanitize(struct intel_uncore *uncore,
> >  				     unsigned int restore_forcewake)
> >  {
> > @@ -617,9 +548,6 @@ void intel_uncore_resume_early(struct intel_uncore *uncore)
> >  {
> >  	unsigned int restore_forcewake;
> >  
> > -	if (intel_uncore_unclaimed_mmio(uncore))
> > -		drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n");
> > -
> >  	if (!intel_uncore_has_forcewake(uncore))
> >  		return;
> >  
> > @@ -1734,59 +1662,6 @@ ilk_dummy_write(struct intel_uncore *uncore)
> >  	__raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0);
> >  }
> >  
> > -static void
> > -__unclaimed_reg_debug(struct intel_uncore *uncore,
> > -		      const i915_reg_t reg,
> > -		      const bool read)
> > -{
> > -	if (drm_WARN(&uncore->i915->drm,
> > -		     check_for_unclaimed_mmio(uncore),
> > -		     "Unclaimed %s register 0x%x\n",
> > -		     read ? "read from" : "write to",
> > -		     i915_mmio_reg_offset(reg)))
> > -		/* Only report the first N failures */
> > -		uncore->i915->params.mmio_debug--;
> > -}
> > -
> > -static void
> > -__unclaimed_previous_reg_debug(struct intel_uncore *uncore,
> > -			       const i915_reg_t reg,
> > -			       const bool read)
> > -{
> > -	if (check_for_unclaimed_mmio(uncore))
> > -		drm_dbg(&uncore->i915->drm,
> > -			"Unclaimed access detected before %s register 0x%x\n",
> > -			read ? "read from" : "write to",
> > -			i915_mmio_reg_offset(reg));
> > -}
> > -
> > -static inline bool __must_check
> > -unclaimed_reg_debug_header(struct intel_uncore *uncore,
> > -			   const i915_reg_t reg, const bool read)
> > -{
> > -	if (likely(!uncore->i915->params.mmio_debug) || !uncore->debug)
> > -		return false;
> > -
> > -	/* interrupts are disabled and re-enabled around uncore->lock usage */
> > -	lockdep_assert_held(&uncore->lock);
> > -
> > -	spin_lock(&uncore->debug->lock);
> > -	__unclaimed_previous_reg_debug(uncore, reg, read);
> > -
> > -	return true;
> > -}
> > -
> > -static inline void
> > -unclaimed_reg_debug_footer(struct intel_uncore *uncore,
> > -			   const i915_reg_t reg, const bool read)
> > -{
> > -	/* interrupts are disabled and re-enabled around uncore->lock usage */
> > -	lockdep_assert_held(&uncore->lock);
> > -
> > -	__unclaimed_reg_debug(uncore, reg, read);
> > -	spin_unlock(&uncore->debug->lock);
> > -}
> > -
> >  #define __vgpu_read(x) \
> >  static u##x \
> >  vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
> > @@ -1842,15 +1717,11 @@ __gen2_read(64)
> >  #define GEN6_READ_HEADER(x) \
> >  	u32 offset = i915_mmio_reg_offset(reg); \
> >  	unsigned long irqflags; \
> > -	bool unclaimed_reg_debug; \
> >  	u##x val = 0; \
> >  	assert_rpm_wakelock_held(uncore->rpm); \
> > -	spin_lock_irqsave(&uncore->lock, irqflags); \
> > -	unclaimed_reg_debug = unclaimed_reg_debug_header(uncore, reg, true)
> > +	spin_lock_irqsave(&uncore->lock, irqflags)
> >  
> >  #define GEN6_READ_FOOTER \
> > -	if (unclaimed_reg_debug) \
> > -		unclaimed_reg_debug_footer(uncore, reg, true);	\
> >  	spin_unlock_irqrestore(&uncore->lock, irqflags); \
> >  	trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
> >  	return val
> > @@ -1948,15 +1819,11 @@ __gen2_write(32)
> >  #define GEN6_WRITE_HEADER \
> >  	u32 offset = i915_mmio_reg_offset(reg); \
> >  	unsigned long irqflags; \
> > -	bool unclaimed_reg_debug; \
> >  	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
> >  	assert_rpm_wakelock_held(uncore->rpm); \
> > -	spin_lock_irqsave(&uncore->lock, irqflags); \
> > -	unclaimed_reg_debug = unclaimed_reg_debug_header(uncore, reg, false)
> > +	spin_lock_irqsave(&uncore->lock, irqflags)
> >  
> >  #define GEN6_WRITE_FOOTER \
> > -	if (unclaimed_reg_debug) \
> > -		unclaimed_reg_debug_footer(uncore, reg, false); \
> >  	spin_unlock_irqrestore(&uncore->lock, irqflags)
> >  
> >  #define __gen6_write(x) \
> > @@ -2490,7 +2357,6 @@ static int sanity_check_mmio_access(struct intel_uncore *uncore)
> >  int intel_uncore_init_mmio(struct intel_uncore *uncore)
> >  {
> >  	struct drm_i915_private *i915 = uncore->i915;
> > -	struct intel_display *display = i915->display;
> >  	int ret;
> >  
> >  	ret = sanity_check_mmio_access(uncore);
> > @@ -2525,19 +2391,9 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
> >  	GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
> >  	GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
> >  
> > -	if (HAS_FPGA_DBG_UNCLAIMED(display))
> 
> This macro becomes unused, along with struct intel_display_device_info
> .has_fpga_dbg member. I think it's fine to remove this from the device
> info, since it's not coming and going, but is fairly stable across
> platforms. Again, can be follow-up.
> 
> BR,
> Jani.
> 
> > -		uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
> > -
> > -	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > -		uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
> > -
> >  	if (IS_GRAPHICS_VER(i915, 6, 7))
> >  		uncore->flags |= UNCORE_HAS_FIFO;
> >  
> > -	/* clear out unclaimed reg detection bit */
> > -	if (intel_uncore_unclaimed_mmio(uncore))
> > -		drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n");
> > -
> >  	return 0;
> >  }
> >  
> > @@ -2800,51 +2656,6 @@ int __intel_wait_for_register(struct intel_uncore *uncore,
> >  	return ret;
> >  }
> >  
> > -bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
> > -{
> > -	bool ret;
> > -
> > -	if (!uncore->debug)
> > -		return false;
> > -
> > -	spin_lock_irq(&uncore->debug->lock);
> > -	ret = check_for_unclaimed_mmio(uncore);
> > -	spin_unlock_irq(&uncore->debug->lock);
> > -
> > -	return ret;
> > -}
> > -
> > -bool
> > -intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
> > -{
> > -	bool ret = false;
> > -
> > -	if (drm_WARN_ON(&uncore->i915->drm, !uncore->debug))
> > -		return false;
> > -
> > -	spin_lock_irq(&uncore->debug->lock);
> > -
> > -	if (unlikely(uncore->debug->unclaimed_mmio_check <= 0))
> > -		goto out;
> > -
> > -	if (unlikely(check_for_unclaimed_mmio(uncore))) {
> > -		if (!uncore->i915->params.mmio_debug) {
> > -			drm_dbg(&uncore->i915->drm,
> > -				"Unclaimed register detected, "
> > -				"enabling oneshot unclaimed register reporting. "
> > -				"Please use i915.mmio_debug=N for more information.\n");
> > -			uncore->i915->params.mmio_debug++;
> > -		}
> > -		uncore->debug->unclaimed_mmio_check--;
> > -		ret = true;
> > -	}
> > -
> > -out:
> > -	spin_unlock_irq(&uncore->debug->lock);
> > -
> > -	return ret;
> > -}
> > -
> >  /**
> >   * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
> >   * 				    a register
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> > index 4ec7c545d04e..9047d7d4d855 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.h
> > +++ b/drivers/gpu/drm/i915/intel_uncore.h
> > @@ -39,11 +39,6 @@ struct intel_runtime_pm;
> >  struct intel_uncore;
> >  struct intel_gt;
> >  
> > -struct intel_uncore_mmio_debug {
> > -	spinlock_t lock; /** lock is also taken in irq contexts. */
> > -	int unclaimed_mmio_check;
> > -};
> > -
> >  enum forcewake_domain_id {
> >  	FW_DOMAIN_ID_RENDER = 0,
> >  	FW_DOMAIN_ID_GT,        /* also includes blitter engine */
> > @@ -142,8 +137,6 @@ struct intel_uncore {
> >  
> >  	unsigned int flags;
> >  #define UNCORE_HAS_FORCEWAKE		BIT(0)
> > -#define UNCORE_HAS_FPGA_DBG_UNCLAIMED	BIT(1)
> > -#define UNCORE_HAS_DBG_UNCLAIMED	BIT(2)
> >  #define UNCORE_HAS_FIFO			BIT(3)
> >  #define UNCORE_NEEDS_FLR_ON_FINI	BIT(4)
> >  
> > @@ -180,8 +173,6 @@ struct intel_uncore {
> >  	} *fw_domain[FW_DOMAIN_ID_COUNT];
> >  
> >  	unsigned int user_forcewake_count;
> > -
> > -	struct intel_uncore_mmio_debug *debug;
> >  };
> >  
> >  /* Iterate over initialised fw domains */
> > @@ -198,18 +189,6 @@ intel_uncore_has_forcewake(const struct intel_uncore *uncore)
> >  	return uncore->flags & UNCORE_HAS_FORCEWAKE;
> >  }
> >  
> > -static inline bool
> > -intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore *uncore)
> > -{
> > -	return uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED;
> > -}
> > -
> > -static inline bool
> > -intel_uncore_has_dbg_unclaimed(const struct intel_uncore *uncore)
> > -{
> > -	return uncore->flags & UNCORE_HAS_DBG_UNCLAIMED;
> > -}
> > -
> >  static inline bool
> >  intel_uncore_has_fifo(const struct intel_uncore *uncore)
> >  {
> > @@ -228,15 +207,12 @@ intel_uncore_set_flr_on_fini(struct intel_uncore *uncore)
> >  	return uncore->flags |= UNCORE_NEEDS_FLR_ON_FINI;
> >  }
> >  
> > -void intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915);
> >  void intel_uncore_init_early(struct intel_uncore *uncore,
> >  			     struct intel_gt *gt);
> >  int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr);
> >  int intel_uncore_init_mmio(struct intel_uncore *uncore);
> >  void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
> >  					  struct intel_gt *gt);
> > -bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
> > -bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
> >  void intel_uncore_cleanup_mmio(struct intel_uncore *uncore);
> >  void intel_uncore_fini_mmio(struct drm_device *dev, void *data);
> >  void intel_uncore_suspend(struct intel_uncore *uncore);
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

[PATCH 8/9] drm/i915/de: Stop using intel_uncore_{read,write}()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Stop using the heavier intel_uncore_{read,write}() and
just use intel_uncore_{read,write}_fw() for all display
register accesses.

The main functional change here is that we now stop
grabbing uncore.lock for display registers. Its job
is now fully taken over by the display mmio.lock.

The one little thing we want to keep from the uncore
implementation is the runtime pm asserts (sadly xe
doesn't implement them, but i915 does). We have the
parent interface for it, so just use it. That is one
extra vfunc call, but not sure there's any way around
it.

One somewhat unexpected side effect (or bonus) is that
on ILK we also lose ilk_dummy_write(), which is currently
done ahead of all (non-fw) mmio accesses. The only
purpose of the dummy write is to wake the GT from
RC6 ahead of the actual mmio access. Display has
nothing to do with RC6, and I don't think we actually
ever enabled RC6 on ILK, so the whole thing is pointless.

As a result of eliminating ilk_dummy_write() display
register accesses become faster on ILK (numbers in
nanoseconds):
      | fw  |   non-fw   |
read  | 140 | 430 -> 140 |
write | 170 | 470 -> 170 |

Register accesses on TGL also get a bit faster,
compared against the original code before the
display mmio vfuncs were introduced:
      | fw  |   non-fw   | theoretical non-fw(*)
read  | 230 | 970 -> 840 | 2*230+230 = 690
write | 100 | 820 -> 740 | 2*230+100 = 560

(*) two FPGA_DBG reads + the actual register access

I presume the improvement was due to some combination of
eliminating the extra debug lock and just reducing the
runtime overhead in general. The remaining delta between
theory and practice seems to be mostly due to mmio.lock.
We'll probably want to think of ways to eliminate the lock
entirely, on the platforms that don't need it for register
access serialization...

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_de.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
index 0a51105e0fba..397145bc7e5b 100644
--- a/drivers/gpu/drm/i915/display/intel_de.c
+++ b/drivers/gpu/drm/i915/display/intel_de.c
@@ -9,6 +9,7 @@
 
 #include "intel_de.h"
 #include "intel_display_regs.h"
+#include "intel_display_rpm.h"
 
 static int intel_de_wait_for_register(struct intel_display *display,
 				      intel_reg_t reg, u32 mask, u32 value,
@@ -341,11 +342,13 @@ __intel_de_read(struct intel_display *display, intel_reg_t reg,
 	unsigned long irqflags;
 	u32 val;
 
+	assert_display_rpm_held(display);
+
 	__mmio_wakelock_pre(display, reg, mmio_flags);
 	__mmio_lock_pre(display, &irqflags, mmio_flags);
 	__mmio_unclaimed_pre(display, reg, false, mmio_flags);
 
-	val = intel_uncore_read(__to_uncore(display), reg);
+	val = intel_de_read_fw(display, reg);
 
 	__mmio_unclaimed_post(display, reg, false, mmio_flags);
 	__mmio_lock_post(display, irqflags, mmio_flags);
@@ -360,11 +363,13 @@ __intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
 {
 	unsigned long irqflags;
 
+	assert_display_rpm_held(display);
+
 	__mmio_wakelock_pre(display, reg, mmio_flags);
 	__mmio_lock_pre(display, &irqflags, mmio_flags);
 	__mmio_unclaimed_pre(display, reg, true, mmio_flags);
 
-	intel_uncore_write(__to_uncore(display), reg, val);
+	intel_de_write_fw(display, reg, val);
 
 	__mmio_unclaimed_post(display, reg, true, mmio_flags);
 	__mmio_lock_post(display, irqflags, mmio_flags);
-- 
2.56.0

Re: [PATCH 8/9] drm/i915/de: Stop using intel_uncore_{read,write}()

[Jani Nikula]

On Thu, 05 Nov 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Stop using the heavier intel_uncore_{read,write}() and
> just use intel_uncore_{read,write}_fw() for all display
> register accesses.
>
> The main functional change here is that we now stop
> grabbing uncore.lock for display registers. Its job
> is now fully taken over by the display mmio.lock.
>
> The one little thing we want to keep from the uncore
> implementation is the runtime pm asserts (sadly xe
> doesn't implement them, but i915 does). We have the
> parent interface for it, so just use it. That is one
> extra vfunc call, but not sure there's any way around
> it.
>
> One somewhat unexpected side effect (or bonus) is that
> on ILK we also lose ilk_dummy_write(), which is currently
> done ahead of all (non-fw) mmio accesses. The only
> purpose of the dummy write is to wake the GT from
> RC6 ahead of the actual mmio access. Display has
> nothing to do with RC6, and I don't think we actually
> ever enabled RC6 on ILK, so the whole thing is pointless.
>
> As a result of eliminating ilk_dummy_write() display
> register accesses become faster on ILK (numbers in
> nanoseconds):
>       | fw  |   non-fw   |
> read  | 140 | 430 -> 140 |
> write | 170 | 470 -> 170 |
>
> Register accesses on TGL also get a bit faster,
> compared against the original code before the
> display mmio vfuncs were introduced:
>       | fw  |   non-fw   | theoretical non-fw(*)
> read  | 230 | 970 -> 840 | 2*230+230 = 690
> write | 100 | 820 -> 740 | 2*230+100 = 560
>
> (*) two FPGA_DBG reads + the actual register access
>
> I presume the improvement was due to some combination of
> eliminating the extra debug lock and just reducing the
> runtime overhead in general. The remaining delta between
> theory and practice seems to be mostly due to mmio.lock.
> We'll probably want to think of ways to eliminate the lock
> entirely, on the platforms that don't need it for register
> access serialization...
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I guess would like to see mmio tracing pulled into display side too.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_de.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> index 0a51105e0fba..397145bc7e5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.c
> +++ b/drivers/gpu/drm/i915/display/intel_de.c
> @@ -9,6 +9,7 @@
>  
>  #include "intel_de.h"
>  #include "intel_display_regs.h"
> +#include "intel_display_rpm.h"
>  
>  static int intel_de_wait_for_register(struct intel_display *display,
>  				      intel_reg_t reg, u32 mask, u32 value,
> @@ -341,11 +342,13 @@ __intel_de_read(struct intel_display *display, intel_reg_t reg,
>  	unsigned long irqflags;
>  	u32 val;
>  
> +	assert_display_rpm_held(display);
> +
>  	__mmio_wakelock_pre(display, reg, mmio_flags);
>  	__mmio_lock_pre(display, &irqflags, mmio_flags);
>  	__mmio_unclaimed_pre(display, reg, false, mmio_flags);
>  
> -	val = intel_uncore_read(__to_uncore(display), reg);
> +	val = intel_de_read_fw(display, reg);
>  
>  	__mmio_unclaimed_post(display, reg, false, mmio_flags);
>  	__mmio_lock_post(display, irqflags, mmio_flags);
> @@ -360,11 +363,13 @@ __intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
>  {
>  	unsigned long irqflags;
>  
> +	assert_display_rpm_held(display);
> +
>  	__mmio_wakelock_pre(display, reg, mmio_flags);
>  	__mmio_lock_pre(display, &irqflags, mmio_flags);
>  	__mmio_unclaimed_pre(display, reg, true, mmio_flags);
>  
> -	intel_uncore_write(__to_uncore(display), reg, val);
> +	intel_de_write_fw(display, reg, val);
>  
>  	__mmio_unclaimed_post(display, reg, true, mmio_flags);
>  	__mmio_lock_post(display, irqflags, mmio_flags);

-- 
Jani Nikula, Intel

Re: [PATCH 8/9] drm/i915/de: Stop using intel_uncore_{read,write}()

[Ville Syrjälä]

On Fri, Nov 06, 2026 at 05:37:59PM +0200, Jani Nikula wrote:
> On Thu, 05 Nov 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Stop using the heavier intel_uncore_{read,write}() and
> > just use intel_uncore_{read,write}_fw() for all display
> > register accesses.
> >
> > The main functional change here is that we now stop
> > grabbing uncore.lock for display registers. Its job
> > is now fully taken over by the display mmio.lock.
> >
> > The one little thing we want to keep from the uncore
> > implementation is the runtime pm asserts (sadly xe
> > doesn't implement them, but i915 does). We have the
> > parent interface for it, so just use it. That is one
> > extra vfunc call, but not sure there's any way around
> > it.
> >
> > One somewhat unexpected side effect (or bonus) is that
> > on ILK we also lose ilk_dummy_write(), which is currently
> > done ahead of all (non-fw) mmio accesses. The only
> > purpose of the dummy write is to wake the GT from
> > RC6 ahead of the actual mmio access. Display has
> > nothing to do with RC6, and I don't think we actually
> > ever enabled RC6 on ILK, so the whole thing is pointless.
> >
> > As a result of eliminating ilk_dummy_write() display
> > register accesses become faster on ILK (numbers in
> > nanoseconds):
> >       | fw  |   non-fw   |
> > read  | 140 | 430 -> 140 |
> > write | 170 | 470 -> 170 |
> >
> > Register accesses on TGL also get a bit faster,
> > compared against the original code before the
> > display mmio vfuncs were introduced:
> >       | fw  |   non-fw   | theoretical non-fw(*)
> > read  | 230 | 970 -> 840 | 2*230+230 = 690
> > write | 100 | 820 -> 740 | 2*230+100 = 560
> >
> > (*) two FPGA_DBG reads + the actual register access
> >
> > I presume the improvement was due to some combination of
> > eliminating the extra debug lock and just reducing the
> > runtime overhead in general. The remaining delta between
> > theory and practice seems to be mostly due to mmio.lock.
> > We'll probably want to think of ways to eliminate the lock
> > entirely, on the platforms that don't need it for register
> > access serialization...
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> I guess would like to see mmio tracing pulled into display side too.

That'll happen eventually. The current problem is that
(unline i915 core stuff) xe traces even the _fw()
accesses, so if we switch to a display specific
tracepoint right now we'll get double traces on xe
if the xe tracpoint is also enabled. But perhaps
that's fine as a temporary state of affairs?

> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_de.c | 9 +++++++--
> >  1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
> > index 0a51105e0fba..397145bc7e5b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_de.c
> > +++ b/drivers/gpu/drm/i915/display/intel_de.c
> > @@ -9,6 +9,7 @@
> >  
> >  #include "intel_de.h"
> >  #include "intel_display_regs.h"
> > +#include "intel_display_rpm.h"
> >  
> >  static int intel_de_wait_for_register(struct intel_display *display,
> >  				      intel_reg_t reg, u32 mask, u32 value,
> > @@ -341,11 +342,13 @@ __intel_de_read(struct intel_display *display, intel_reg_t reg,
> >  	unsigned long irqflags;
> >  	u32 val;
> >  
> > +	assert_display_rpm_held(display);
> > +
> >  	__mmio_wakelock_pre(display, reg, mmio_flags);
> >  	__mmio_lock_pre(display, &irqflags, mmio_flags);
> >  	__mmio_unclaimed_pre(display, reg, false, mmio_flags);
> >  
> > -	val = intel_uncore_read(__to_uncore(display), reg);
> > +	val = intel_de_read_fw(display, reg);
> >  
> >  	__mmio_unclaimed_post(display, reg, false, mmio_flags);
> >  	__mmio_lock_post(display, irqflags, mmio_flags);
> > @@ -360,11 +363,13 @@ __intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val,
> >  {
> >  	unsigned long irqflags;
> >  
> > +	assert_display_rpm_held(display);
> > +
> >  	__mmio_wakelock_pre(display, reg, mmio_flags);
> >  	__mmio_lock_pre(display, &irqflags, mmio_flags);
> >  	__mmio_unclaimed_pre(display, reg, true, mmio_flags);
> >  
> > -	intel_uncore_write(__to_uncore(display), reg, val);
> > +	intel_de_write_fw(display, reg, val);
> >  
> >  	__mmio_unclaimed_post(display, reg, true, mmio_flags);
> >  	__mmio_lock_post(display, irqflags, mmio_flags);
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

[PATCH 9/9] drm/xe: Nuke the intel_uncore_{read,write}() wrappers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_uncore_{read,write}() are no longer needed by the
display code. Remove them.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/xe/compat-i915-headers/intel_uncore.h    | 16 ----------------
 1 file changed, 16 deletions(-)

diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
index 2f198e2e2fec..238addc1e5fc 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
@@ -23,14 +23,6 @@ static inline struct xe_mmio *__compat_uncore_to_mmio(struct intel_uncore *uncor
 	return xe_root_tile_mmio(xe);
 }
 
-static inline u32 intel_uncore_read(struct intel_uncore *uncore,
-				    i915_reg_t i915_reg)
-{
-	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
-
-	return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);
-}
-
 static inline u8 intel_uncore_read8(struct intel_uncore *uncore,
 				    i915_reg_t i915_reg)
 {
@@ -55,14 +47,6 @@ static inline u16 intel_uncore_read16(struct intel_uncore *uncore,
 	return xe_mmio_read16(__compat_uncore_to_mmio(uncore), reg);
 }
 
-static inline void intel_uncore_write(struct intel_uncore *uncore,
-				      i915_reg_t i915_reg, u32 val)
-{
-	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
-
-	xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val);
-}
-
 static inline u32 intel_uncore_read_fw(struct intel_uncore *uncore,
 				       i915_reg_t i915_reg)
 {
-- 
2.56.0

Re: [PATCH 9/9] drm/xe: Nuke the intel_uncore_{read, write}() wrappers

[Jani Nikula]

On Thu, 05 Nov 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_uncore_{read,write}() are no longer needed by the
> display code. Remove them.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Yay.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  .../drm/xe/compat-i915-headers/intel_uncore.h    | 16 ----------------
>  1 file changed, 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> index 2f198e2e2fec..238addc1e5fc 100644
> --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> +++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> @@ -23,14 +23,6 @@ static inline struct xe_mmio *__compat_uncore_to_mmio(struct intel_uncore *uncor
>  	return xe_root_tile_mmio(xe);
>  }
>  
> -static inline u32 intel_uncore_read(struct intel_uncore *uncore,
> -				    i915_reg_t i915_reg)
> -{
> -	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> -
> -	return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);
> -}
> -
>  static inline u8 intel_uncore_read8(struct intel_uncore *uncore,
>  				    i915_reg_t i915_reg)
>  {
> @@ -55,14 +47,6 @@ static inline u16 intel_uncore_read16(struct intel_uncore *uncore,
>  	return xe_mmio_read16(__compat_uncore_to_mmio(uncore), reg);
>  }
>  
> -static inline void intel_uncore_write(struct intel_uncore *uncore,
> -				      i915_reg_t i915_reg, u32 val)
> -{
> -	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> -
> -	xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val);
> -}
> -
>  static inline u32 intel_uncore_read_fw(struct intel_uncore *uncore,
>  				       i915_reg_t i915_reg)
>  {

-- 
Jani Nikula, Intel

✗ CI.checkpatch: warning for drm/i915/de: Work towards uncore elimination

[Patchwork]

== Series Details ==

Series: drm/i915/de: Work towards uncore elimination
URL   : https://patchwork.freedesktop.org/series/177794/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
3009867cd31863246e4afc138520a7a8bd37bb11
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 9be9b71d8de22845bab7254a252167d077a36c1b
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date:   Thu Nov 5 00:18:42 2026 +0200

    drm/xe: Nuke the intel_uncore_{read,write}() wrappers
    
    intel_uncore_{read,write}() are no longer needed by the
    display code. Remove them.
    
    Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+ /mt/dim checkpatch 3379b0f74f31bfc3746b692822a7700aeeebe15d drm-intel
978ce3ec7cb6 drm/i915/de: Introduce dislay->mmio and intel_de_init()
9d5e0bb0483c drm/i915/de: Convert intel_de_{read,write}() into vfuncs
ffc1b27a5559 drm/i915/de: Introduce mmio read/write templates
3922b9f0f206 drm/i915/de: Eliminate runtime overhead from DMC wakelock on pre-LNL platforms
08645490406e drm/i915/de: Introduce display->mmio.lock
6f48b5e7c935 drm/i915/uncore: Don't meddle with mmio debug upon user forcewake
e9e9a214b0d2 drm/i915/de: Move unclaimed mmio detection into display code
-:393: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#393: FILE: drivers/gpu/drm/i915/display/intel_display_params.c:147:
+intel_display_param_named(mmio_debug, int, 0400,
+	"Enable the MMIO debug code for the first N failures (default: off). "

total: 0 errors, 0 warnings, 1 checks, 730 lines checked
fbbc049c6288 drm/i915/de: Stop using intel_uncore_{read,write}()
9be9b71d8de2 drm/xe: Nuke the intel_uncore_{read,write}() wrappers

✓ CI.KUnit: success for drm/i915/de: Work towards uncore elimination

[Patchwork]

== Series Details ==

Series: drm/i915/de: Work towards uncore elimination
URL   : https://patchwork.freedesktop.org/series/177794/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[00:01:32] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:01:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:01:57] Starting KUnit Kernel (1/1)...
[00:01:57] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:01:57] ================= gpu_buddy (14 subtests) ==================
[00:01:57] [PASSED] gpu_test_buddy_alloc_limit
[00:01:57] [PASSED] gpu_test_buddy_alloc_optimistic
[00:01:57] [PASSED] gpu_test_buddy_alloc_pessimistic
[00:01:57] [PASSED] gpu_test_buddy_alloc_pathological
[00:01:57] [PASSED] gpu_test_buddy_alloc_contiguous
[00:01:57] [PASSED] gpu_test_buddy_alloc_clear
[00:01:57] [PASSED] gpu_test_buddy_alloc_range
[00:01:57] [PASSED] gpu_test_buddy_alloc_range_bias
[00:01:58] [PASSED] gpu_test_buddy_fragmentation_performance
[00:01:59] [PASSED] gpu_test_buddy_dirty_tracker_performance
[00:01:59] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[00:01:59] [PASSED] gpu_test_buddy_offset_aligned_allocation
[00:01:59] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[00:01:59] [PASSED] gpu_test_buddy_addr_to_block
[00:01:59] ==================== [PASSED] gpu_buddy ====================
[00:01:59] ============================================================
[00:01:59] Testing complete. Ran 14 tests: passed: 14
[00:01:59] Elapsed time: 27.175s total, 5.198s configuring, 20.110s building, 1.818s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[00:01:59] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:02:02] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:02:40] Starting KUnit Kernel (1/1)...
[00:02:40] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:02:40] ================== guc_buf (11 subtests) ===================
[00:02:40] [PASSED] test_smallest
[00:02:40] [PASSED] test_largest
[00:02:40] [PASSED] test_granular
[00:02:40] [PASSED] test_unique
[00:02:40] [PASSED] test_overlap
[00:02:40] [PASSED] test_reusable
[00:02:40] [PASSED] test_too_big
[00:02:40] [PASSED] test_flush
[00:02:40] [PASSED] test_lookup
[00:02:40] [PASSED] test_data
[00:02:40] [PASSED] test_class
[00:02:40] ===================== [PASSED] guc_buf =====================
[00:02:40] =================== guc_dbm (7 subtests) ===================
[00:02:40] [PASSED] test_empty
[00:02:40] [PASSED] test_default
[00:02:40] ======================== test_size  ========================
[00:02:40] [PASSED] 4
[00:02:40] [PASSED] 8
[00:02:40] [PASSED] 32
[00:02:40] [PASSED] 256
[00:02:40] ==================== [PASSED] test_size ====================
[00:02:40] ======================= test_reuse  ========================
[00:02:40] [PASSED] 4
[00:02:40] [PASSED] 8
[00:02:40] [PASSED] 32
[00:02:40] [PASSED] 256
[00:02:40] =================== [PASSED] test_reuse ====================
[00:02:40] =================== test_range_overlap  ====================
[00:02:40] [PASSED] 4
[00:02:40] [PASSED] 8
[00:02:40] [PASSED] 32
[00:02:40] [PASSED] 256
[00:02:40] =============== [PASSED] test_range_overlap ================
[00:02:40] =================== test_range_compact  ====================
[00:02:40] [PASSED] 4
[00:02:40] [PASSED] 8
[00:02:40] [PASSED] 32
[00:02:40] [PASSED] 256
[00:02:40] =============== [PASSED] test_range_compact ================
[00:02:40] ==================== test_range_spare  =====================
[00:02:40] [PASSED] 4
[00:02:40] [PASSED] 8
[00:02:40] [PASSED] 32
[00:02:40] [PASSED] 256
[00:02:40] ================ [PASSED] test_range_spare =================
[00:02:40] ===================== [PASSED] guc_dbm =====================
[00:02:40] ================== guc_idm (22 subtests) ===================
[00:02:40] [PASSED] bad_init
[00:02:40] [PASSED] no_init
[00:02:40] [PASSED] init_fini
[00:02:40] [PASSED] check_init_small
[00:02:40] [PASSED] check_init_shared
[00:02:40] [PASSED] check_used
[00:02:40] [PASSED] check_quota
[00:02:40] [PASSED] check_all
[00:02:40] [PASSED] check_limits
[00:02:40] [PASSED] check_overlap
[00:02:40] [PASSED] check_overlap_alloc
[00:02:40] [PASSED] check_overlap_release
[00:02:40] [PASSED] check_overlap_partial_init
[00:02:40] [PASSED] check_overlap_partial_shared_range_blocking
[00:02:40] [PASSED] check_used_usable
[00:02:40] [PASSED] check_used_shareable
[00:02:40] [PASSED] check_used_mixed
[00:02:40] [PASSED] check_release_usable_range
[00:02:40] [PASSED] check_release_shareable_range
[00:02:40] [PASSED] check_split_boundaries
[00:02:40] [PASSED] check_shareable_spare
[00:02:40] [PASSED] check_shareable_spare_fragmented_tail
[00:02:40] ===================== [PASSED] guc_idm =====================
[00:02:40] ============== guc_klv_helpers (13 subtests) ===============
[00:02:40] [PASSED] test_count
[00:02:40] [PASSED] test_encode_u32
[00:02:40] [PASSED] test_encode_u64
[00:02:40] [PASSED] test_encode_string
[00:02:40] [PASSED] test_encode_object_raw
[00:02:40] [PASSED] test_encode_object_klv
[00:02:40] [PASSED] test_encode_object_nested
[00:02:40] [PASSED] test_encode_object_basic
[00:02:40] ===================== test_decode_u16  =====================
[00:02:40] [PASSED] empty
[00:02:40] [PASSED] valid
[00:02:40] [PASSED] max
[00:02:40] [PASSED] big
[00:02:40] [PASSED] long
[00:02:40] ================= [PASSED] test_decode_u16 =================
[00:02:40] ===================== test_decode_u32  =====================
[00:02:40] [PASSED] empty
[00:02:40] [PASSED] valid
[00:02:40] [PASSED] max
[00:02:40] [PASSED] long
[00:02:40] ================= [PASSED] test_decode_u32 =================
[00:02:40] ===================== test_decode_u64  =====================
[00:02:40] [PASSED] empty
[00:02:40] [PASSED] short
[00:02:40] [PASSED] valid
[00:02:40] [PASSED] max
[00:02:40] [PASSED] long
[00:02:40] ================= [PASSED] test_decode_u64 =================
[00:02:40] ===================== test_decode_str  =====================
[00:02:40] [PASSED] empty
[00:02:40] [PASSED] one
[00:02:40] [PASSED] one_trash
[00:02:40] [PASSED] two
[00:02:40] [PASSED] two_trash
[00:02:40] [PASSED] three
[00:02:40] [PASSED] dword
[00:02:40] [PASSED] four
[00:02:40] [PASSED] five
[00:02:40] [PASSED] six
[00:02:40] [PASSED] seven
[00:02:40] [PASSED] qword
[00:02:40] ================= [PASSED] test_decode_str =================
[00:02:40] [PASSED] test_print
[00:02:40] ================= [PASSED] guc_klv_helpers =================
[00:02:40] =================== xe_log (4 subtests) ====================
[00:02:40] [PASSED] demo_cper
[00:02:40] [PASSED] demo_dmesg
[00:02:40] ======================= test_dmesg  ========================
[00:02:40] [PASSED] test_fatal
[00:02:40] [PASSED] test_fatal_tile
[00:02:40] [PASSED] test_fatal_gt
[00:02:40] [PASSED] test_fatal_comp
[00:02:40] [PASSED] test_fatal_comp_tile
[00:02:40] [PASSED] test_fatal_comp_gt
[00:02:40] [PASSED] test_fatal_all
[00:02:40] [PASSED] test_recoverable
[00:02:40] [PASSED] test_recoverable_tile
[00:02:40] [PASSED] test_recoverable_gt
[00:02:40] [PASSED] test_recoverable_comp
[00:02:40] [PASSED] test_recoverable_comp_tile
[00:02:40] [PASSED] test_recoverable_comp_gt
[00:02:40] [PASSED] test_recoverable_all
[00:02:40] [PASSED] test_info
[00:02:40] [PASSED] test_info_tile
[00:02:40] [PASSED] test_info_gt
[00:02:40] [PASSED] test_info_err
[00:02:40] [PASSED] test_info_comp
[00:02:40] [PASSED] test_info_comp_tile
[00:02:40] [PASSED] test_info_comp_gt
[00:02:40] [PASSED] test_info_all
[00:02:40] [PASSED] test_hw_fatal
[00:02:40] [PASSED] test_hw_recoverable
[00:02:40] [PASSED] test_hw_corrected
[00:02:40] [PASSED] test_hw_informational
[00:02:40] =================== [PASSED] test_dmesg ====================
[00:02:40] ====================== test_invalid  =======================
[00:02:40] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[00:02:40] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[00:02:40] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[00:02:40] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[00:02:40] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[00:02:40] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[00:02:40] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[00:02:40] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[00:02:40] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[00:02:40] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[00:02:40] ================== [SKIPPED] test_invalid ==================
[00:02:40] ===================== [PASSED] xe_log ======================
[00:02:40] ================== no_relay (3 subtests) ===================
[00:02:40] [PASSED] xe_drops_guc2pf_if_not_ready
[00:02:40] [PASSED] xe_drops_guc2vf_if_not_ready
[00:02:40] [PASSED] xe_rejects_send_if_not_ready
[00:02:40] ==================== [PASSED] no_relay =====================
[00:02:40] ================== pf_relay (14 subtests) ==================
[00:02:40] [PASSED] pf_rejects_guc2pf_too_short
[00:02:40] [PASSED] pf_rejects_guc2pf_too_long
[00:02:40] [PASSED] pf_rejects_guc2pf_no_payload
[00:02:40] [PASSED] pf_fails_no_payload
[00:02:40] [PASSED] pf_fails_bad_origin
[00:02:40] [PASSED] pf_fails_bad_type
[00:02:40] [PASSED] pf_txn_reports_error
[00:02:40] [PASSED] pf_txn_sends_pf2guc
[00:02:40] [PASSED] pf_sends_pf2guc
[00:02:40] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[00:02:40] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[00:02:40] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[00:02:40] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[00:02:40] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[00:02:40] ==================== [PASSED] pf_relay =====================
[00:02:40] ================== vf_relay (3 subtests) ===================
[00:02:40] [PASSED] vf_rejects_guc2vf_too_short
[00:02:40] [PASSED] vf_rejects_guc2vf_too_long
[00:02:40] [PASSED] vf_rejects_guc2vf_no_payload
[00:02:40] ==================== [PASSED] vf_relay =====================
[00:02:40] ================ pf_gt_config (9 subtests) =================
[00:02:40] [PASSED] fair_contexts_1vf
[00:02:40] [PASSED] fair_doorbells_1vf
[00:02:40] [PASSED] fair_ggtt_1vf
[00:02:40] ====================== fair_vram_1vf  ======================
[00:02:40] [PASSED] 3.50 GiB
[00:02:40] [PASSED] 11.5 GiB
[00:02:40] [PASSED] 15.5 GiB
[00:02:40] [PASSED] 31.5 GiB
[00:02:40] [PASSED] 63.5 GiB
[00:02:40] [PASSED] 1.91 GiB
[00:02:40] ================== [PASSED] fair_vram_1vf ==================
[00:02:40] ================ fair_vram_1vf_admin_only  =================
[00:02:40] [PASSED] 3.50 GiB
[00:02:40] [PASSED] 11.5 GiB
[00:02:40] [PASSED] 15.5 GiB
[00:02:40] [PASSED] 31.5 GiB
[00:02:40] [PASSED] 63.5 GiB
[00:02:40] [PASSED] 1.91 GiB
[00:02:40] ============ [PASSED] fair_vram_1vf_admin_only =============
[00:02:40] ====================== fair_contexts  ======================
[00:02:40] [PASSED] 1 VF
[00:02:40] [PASSED] 2 VFs
[00:02:40] [PASSED] 3 VFs
[00:02:40] [PASSED] 4 VFs
[00:02:40] [PASSED] 5 VFs
[00:02:40] [PASSED] 6 VFs
[00:02:40] [PASSED] 7 VFs
[00:02:40] [PASSED] 8 VFs
[00:02:40] [PASSED] 9 VFs
[00:02:40] [PASSED] 10 VFs
[00:02:40] [PASSED] 11 VFs
[00:02:40] [PASSED] 12 VFs
[00:02:40] [PASSED] 13 VFs
[00:02:40] [PASSED] 14 VFs
[00:02:40] [PASSED] 15 VFs
[00:02:40] [PASSED] 16 VFs
[00:02:40] [PASSED] 17 VFs
[00:02:40] [PASSED] 18 VFs
[00:02:40] [PASSED] 19 VFs
[00:02:40] [PASSED] 20 VFs
[00:02:40] [PASSED] 21 VFs
[00:02:40] [PASSED] 22 VFs
[00:02:40] [PASSED] 23 VFs
[00:02:40] [PASSED] 24 VFs
[00:02:40] [PASSED] 25 VFs
[00:02:40] [PASSED] 26 VFs
[00:02:40] [PASSED] 27 VFs
[00:02:40] [PASSED] 28 VFs
[00:02:40] [PASSED] 29 VFs
[00:02:40] [PASSED] 30 VFs
[00:02:40] [PASSED] 31 VFs
[00:02:40] [PASSED] 32 VFs
[00:02:40] [PASSED] 33 VFs
[00:02:40] [PASSED] 34 VFs
[00:02:40] [PASSED] 35 VFs
[00:02:40] [PASSED] 36 VFs
[00:02:40] [PASSED] 37 VFs
[00:02:40] [PASSED] 38 VFs
[00:02:40] [PASSED] 39 VFs
[00:02:40] [PASSED] 40 VFs
[00:02:40] [PASSED] 41 VFs
[00:02:40] [PASSED] 42 VFs
[00:02:40] [PASSED] 43 VFs
[00:02:40] [PASSED] 44 VFs
[00:02:40] [PASSED] 45 VFs
[00:02:40] [PASSED] 46 VFs
[00:02:40] [PASSED] 47 VFs
[00:02:40] [PASSED] 48 VFs
[00:02:40] [PASSED] 49 VFs
[00:02:40] [PASSED] 50 VFs
[00:02:40] [PASSED] 51 VFs
[00:02:40] [PASSED] 52 VFs
[00:02:40] [PASSED] 53 VFs
[00:02:40] [PASSED] 54 VFs
[00:02:40] [PASSED] 55 VFs
[00:02:40] [PASSED] 56 VFs
[00:02:40] [PASSED] 57 VFs
[00:02:40] [PASSED] 58 VFs
[00:02:40] [PASSED] 59 VFs
[00:02:40] [PASSED] 60 VFs
[00:02:40] [PASSED] 61 VFs
[00:02:40] [PASSED] 62 VFs
[00:02:40] [PASSED] 63 VFs
[00:02:40] ================== [PASSED] fair_contexts ==================
[00:02:40] ===================== fair_doorbells  ======================
[00:02:40] [PASSED] 1 VF
[00:02:40] [PASSED] 2 VFs
[00:02:40] [PASSED] 3 VFs
[00:02:40] [PASSED] 4 VFs
[00:02:40] [PASSED] 5 VFs
[00:02:40] [PASSED] 6 VFs
[00:02:40] [PASSED] 7 VFs
[00:02:40] [PASSED] 8 VFs
[00:02:40] [PASSED] 9 VFs
[00:02:40] [PASSED] 10 VFs
[00:02:40] [PASSED] 11 VFs
[00:02:40] [PASSED] 12 VFs
[00:02:40] [PASSED] 13 VFs
[00:02:40] [PASSED] 14 VFs
[00:02:40] [PASSED] 15 VFs
[00:02:40] [PASSED] 16 VFs
[00:02:40] [PASSED] 17 VFs
[00:02:40] [PASSED] 18 VFs
[00:02:40] [PASSED] 19 VFs
[00:02:40] [PASSED] 20 VFs
[00:02:40] [PASSED] 21 VFs
[00:02:40] [PASSED] 22 VFs
[00:02:40] [PASSED] 23 VFs
[00:02:40] [PASSED] 24 VFs
[00:02:40] [PASSED] 25 VFs
[00:02:40] [PASSED] 26 VFs
[00:02:40] [PASSED] 27 VFs
[00:02:40] [PASSED] 28 VFs
[00:02:40] [PASSED] 29 VFs
[00:02:40] [PASSED] 30 VFs
[00:02:40] [PASSED] 31 VFs
[00:02:40] [PASSED] 32 VFs
[00:02:40] [PASSED] 33 VFs
[00:02:40] [PASSED] 34 VFs
[00:02:40] [PASSED] 35 VFs
[00:02:40] [PASSED] 36 VFs
[00:02:40] [PASSED] 37 VFs
[00:02:40] [PASSED] 38 VFs
[00:02:40] [PASSED] 39 VFs
[00:02:40] [PASSED] 40 VFs
[00:02:40] [PASSED] 41 VFs
[00:02:40] [PASSED] 42 VFs
[00:02:40] [PASSED] 43 VFs
[00:02:40] [PASSED] 44 VFs
[00:02:40] [PASSED] 45 VFs
[00:02:40] [PASSED] 46 VFs
[00:02:40] [PASSED] 47 VFs
[00:02:40] [PASSED] 48 VFs
[00:02:40] [PASSED] 49 VFs
[00:02:40] [PASSED] 50 VFs
[00:02:40] [PASSED] 51 VFs
[00:02:40] [PASSED] 52 VFs
[00:02:40] [PASSED] 53 VFs
[00:02:40] [PASSED] 54 VFs
[00:02:40] [PASSED] 55 VFs
[00:02:40] [PASSED] 56 VFs
[00:02:40] [PASSED] 57 VFs
[00:02:40] [PASSED] 58 VFs
[00:02:40] [PASSED] 59 VFs
[00:02:40] [PASSED] 60 VFs
[00:02:40] [PASSED] 61 VFs
[00:02:40] [PASSED] 62 VFs
[00:02:40] [PASSED] 63 VFs
[00:02:40] ================= [PASSED] fair_doorbells ==================
[00:02:40] ======================== fair_ggtt  ========================
[00:02:40] [PASSED] 1 VF
[00:02:40] [PASSED] 2 VFs
[00:02:40] [PASSED] 3 VFs
[00:02:40] [PASSED] 4 VFs
[00:02:40] [PASSED] 5 VFs
[00:02:40] [PASSED] 6 VFs
[00:02:40] [PASSED] 7 VFs
[00:02:40] [PASSED] 8 VFs
[00:02:40] [PASSED] 9 VFs
[00:02:40] [PASSED] 10 VFs
[00:02:40] [PASSED] 11 VFs
[00:02:40] [PASSED] 12 VFs
[00:02:40] [PASSED] 13 VFs
[00:02:40] [PASSED] 14 VFs
[00:02:40] [PASSED] 15 VFs
[00:02:40] [PASSED] 16 VFs
[00:02:40] [PASSED] 17 VFs
[00:02:40] [PASSED] 18 VFs
[00:02:40] [PASSED] 19 VFs
[00:02:40] [PASSED] 20 VFs
[00:02:40] [PASSED] 21 VFs
[00:02:40] [PASSED] 22 VFs
[00:02:40] [PASSED] 23 VFs
[00:02:40] [PASSED] 24 VFs
[00:02:40] [PASSED] 25 VFs
[00:02:40] [PASSED] 26 VFs
[00:02:40] [PASSED] 27 VFs
[00:02:40] [PASSED] 28 VFs
[00:02:40] [PASSED] 29 VFs
[00:02:40] [PASSED] 30 VFs
[00:02:40] [PASSED] 31 VFs
[00:02:40] [PASSED] 32 VFs
[00:02:40] [PASSED] 33 VFs
[00:02:40] [PASSED] 34 VFs
[00:02:40] [PASSED] 35 VFs
[00:02:40] [PASSED] 36 VFs
[00:02:40] [PASSED] 37 VFs
[00:02:40] [PASSED] 38 VFs
[00:02:40] [PASSED] 39 VFs
[00:02:40] [PASSED] 40 VFs
[00:02:40] [PASSED] 41 VFs
[00:02:40] [PASSED] 42 VFs
[00:02:40] [PASSED] 43 VFs
[00:02:40] [PASSED] 44 VFs
[00:02:40] [PASSED] 45 VFs
[00:02:40] [PASSED] 46 VFs
[00:02:40] [PASSED] 47 VFs
[00:02:40] [PASSED] 48 VFs
[00:02:40] [PASSED] 49 VFs
[00:02:40] [PASSED] 50 VFs
[00:02:40] [PASSED] 51 VFs
[00:02:40] [PASSED] 52 VFs
[00:02:40] [PASSED] 53 VFs
[00:02:40] [PASSED] 54 VFs
[00:02:40] [PASSED] 55 VFs
[00:02:40] [PASSED] 56 VFs
[00:02:40] [PASSED] 57 VFs
[00:02:40] [PASSED] 58 VFs
[00:02:40] [PASSED] 59 VFs
[00:02:40] [PASSED] 60 VFs
[00:02:40] [PASSED] 61 VFs
[00:02:40] [PASSED] 62 VFs
[00:02:40] [PASSED] 63 VFs
[00:02:40] ==================== [PASSED] fair_ggtt ====================
[00:02:40] ======================== fair_vram  ========================
[00:02:40] [PASSED] 1 VF
[00:02:40] [PASSED] 2 VFs
[00:02:40] [PASSED] 3 VFs
[00:02:40] [PASSED] 4 VFs
[00:02:40] [PASSED] 5 VFs
[00:02:40] [PASSED] 6 VFs
[00:02:40] [PASSED] 7 VFs
[00:02:40] [PASSED] 8 VFs
[00:02:40] [PASSED] 9 VFs
[00:02:40] [PASSED] 10 VFs
[00:02:40] [PASSED] 11 VFs
[00:02:40] [PASSED] 12 VFs
[00:02:40] [PASSED] 13 VFs
[00:02:40] [PASSED] 14 VFs
[00:02:40] [PASSED] 15 VFs
[00:02:40] [PASSED] 16 VFs
[00:02:40] [PASSED] 17 VFs
[00:02:40] [PASSED] 18 VFs
[00:02:40] [PASSED] 19 VFs
[00:02:40] [PASSED] 20 VFs
[00:02:40] [PASSED] 21 VFs
[00:02:40] [PASSED] 22 VFs
[00:02:40] [PASSED] 23 VFs
[00:02:40] [PASSED] 24 VFs
[00:02:40] [PASSED] 25 VFs
[00:02:40] [PASSED] 26 VFs
[00:02:40] [PASSED] 27 VFs
[00:02:40] [PASSED] 28 VFs
[00:02:40] [PASSED] 29 VFs
[00:02:40] [PASSED] 30 VFs
[00:02:40] [PASSED] 31 VFs
[00:02:40] [PASSED] 32 VFs
[00:02:40] [PASSED] 33 VFs
[00:02:40] [PASSED] 34 VFs
[00:02:40] [PASSED] 35 VFs
[00:02:40] [PASSED] 36 VFs
[00:02:40] [PASSED] 37 VFs
[00:02:40] [PASSED] 38 VFs
[00:02:40] [PASSED] 39 VFs
[00:02:40] [PASSED] 40 VFs
[00:02:40] [PASSED] 41 VFs
[00:02:40] [PASSED] 42 VFs
[00:02:40] [PASSED] 43 VFs
[00:02:40] [PASSED] 44 VFs
[00:02:40] [PASSED] 45 VFs
[00:02:40] [PASSED] 46 VFs
[00:02:40] [PASSED] 47 VFs
[00:02:40] [PASSED] 48 VFs
[00:02:40] [PASSED] 49 VFs
[00:02:40] [PASSED] 50 VFs
[00:02:40] [PASSED] 51 VFs
[00:02:40] [PASSED] 52 VFs
[00:02:40] [PASSED] 53 VFs
[00:02:40] [PASSED] 54 VFs
[00:02:40] [PASSED] 55 VFs
[00:02:40] [PASSED] 56 VFs
[00:02:40] [PASSED] 57 VFs
[00:02:40] [PASSED] 58 VFs
[00:02:40] [PASSED] 59 VFs
[00:02:40] [PASSED] 60 VFs
[00:02:40] [PASSED] 61 VFs
[00:02:40] [PASSED] 62 VFs
[00:02:40] [PASSED] 63 VFs
[00:02:40] ==================== [PASSED] fair_vram ====================
[00:02:40] ================== [PASSED] pf_gt_config ===================
[00:02:40] ===================== lmtt (1 subtest) =====================
[00:02:40] ======================== test_ops  =========================
[00:02:40] [PASSED] 2-level
[00:02:40] [PASSED] multi-level
[00:02:40] ==================== [PASSED] test_ops =====================
[00:02:40] ====================== [PASSED] lmtt =======================
[00:02:40] ================= sriov_packet (1 subtest) =================
[00:02:40] [PASSED] test_descriptor_init
[00:02:40] ================== [PASSED] sriov_packet ===================
[00:02:40] ================= pf_service (11 subtests) =================
[00:02:40] [PASSED] pf_negotiate_any
[00:02:40] [PASSED] pf_negotiate_base_match
[00:02:40] [PASSED] pf_negotiate_base_newer
[00:02:40] [PASSED] pf_negotiate_base_next
[00:02:40] [SKIPPED] pf_negotiate_base_older (no older minor)
[00:02:40] [PASSED] pf_negotiate_base_prev
[00:02:40] [PASSED] pf_negotiate_latest_match
[00:02:40] [PASSED] pf_negotiate_latest_newer
[00:02:40] [PASSED] pf_negotiate_latest_next
[00:02:40] [SKIPPED] pf_negotiate_latest_older (no older minor)
[00:02:40] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[00:02:40] =================== [PASSED] pf_service ====================
[00:02:40] ================= xe_guc_g2g (2 subtests) ==================
[00:02:40] ============== xe_live_guc_g2g_kunit_default  ==============
[00:02:40] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[00:02:40] ============== xe_live_guc_g2g_kunit_allmem  ===============
[00:02:40] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[00:02:40] =================== [SKIPPED] xe_guc_g2g ===================
[00:02:40] =================== xe_mocs (2 subtests) ===================
[00:02:40] ================ xe_live_mocs_kernel_kunit  ================
[00:02:40] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[00:02:40] ================ xe_live_mocs_reset_kunit  =================
[00:02:40] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[00:02:40] ==================== [SKIPPED] xe_mocs =====================
[00:02:40] ================= xe_migrate (3 subtests) ==================
[00:02:40] ================= xe_migrate_sanity_kunit  =================
[00:02:40] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[00:02:40] ================== xe_validate_ccs_kunit  ==================
[00:02:40] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[00:02:40] ============= xe_migrate_access_memory_kunit  ==============
[00:02:40] ========= [SKIPPED] xe_migrate_access_memory_kunit =========
[00:02:40] =================== [SKIPPED] xe_migrate ===================
[00:02:40] ================== xe_dma_buf (1 subtest) ==================
[00:02:40] ==================== xe_dma_buf_kunit  =====================
[00:02:40] ================ [SKIPPED] xe_dma_buf_kunit ================
[00:02:40] =================== [SKIPPED] xe_dma_buf ===================
[00:02:40] ================= xe_bo_shrink (1 subtest) =================
[00:02:40] =================== xe_bo_shrink_kunit  ====================
[00:02:40] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[00:02:40] ================== [SKIPPED] xe_bo_shrink ==================
[00:02:40] ==================== xe_bo (2 subtests) ====================
[00:02:40] ================== xe_ccs_migrate_kunit  ===================
[00:02:40] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[00:02:40] ==================== xe_bo_evict_kunit  ====================
[00:02:40] =============== [SKIPPED] xe_bo_evict_kunit ================
[00:02:40] ===================== [SKIPPED] xe_bo ======================
[00:02:40] =================== xe_any (9 subtests) ====================
[00:02:40] [PASSED] test_to_xe
[00:02:40] [PASSED] test_to_dev
[00:02:40] [PASSED] test_to_pdev
[00:02:40] [PASSED] test_to_drm
[00:02:40] [PASSED] test_if_pdev
[00:02:40] [PASSED] test_if_xe
[00:02:40] [PASSED] test_if_tile
[00:02:40] [PASSED] test_if_gt
[00:02:40] [PASSED] test_to_id
[00:02:40] ===================== [PASSED] xe_any ======================
[00:02:40] ==================== args (13 subtests) ====================
[00:02:40] [PASSED] count_args_test
[00:02:40] [PASSED] call_args_example
[00:02:40] [PASSED] call_args_test
[00:02:40] [PASSED] drop_first_arg_example
[00:02:40] [PASSED] drop_first_arg_test
[00:02:40] [PASSED] first_arg_example
[00:02:40] [PASSED] first_arg_test
[00:02:40] [PASSED] last_arg_example
[00:02:40] [PASSED] last_arg_test
[00:02:40] [PASSED] pick_arg_example
[00:02:40] [PASSED] if_args_example
[00:02:40] [PASSED] if_args_test
[00:02:40] [PASSED] sep_comma_example
[00:02:40] ====================== [PASSED] args =======================
[00:02:40] =================== xe_pci (3 subtests) ====================
[00:02:40] ==================== check_graphics_ip  ====================
[00:02:40] [PASSED] 12.00 Xe_LP
[00:02:40] [PASSED] 12.10 Xe_LP+
[00:02:40] [PASSED] 12.55 Xe_HPG
[00:02:40] [PASSED] 12.60 Xe_HPC
[00:02:40] [PASSED] 12.70 Xe_LPG
[00:02:40] [PASSED] 12.71 Xe_LPG
[00:02:40] [PASSED] 12.74 Xe_LPG+
[00:02:40] [PASSED] 20.01 Xe2_HPG
[00:02:40] [PASSED] 20.02 Xe2_HPG
[00:02:40] [PASSED] 20.04 Xe2_LPG
[00:02:40] [PASSED] 30.00 Xe3_LPG
[00:02:40] [PASSED] 30.01 Xe3_LPG
[00:02:40] [PASSED] 30.03 Xe3_LPG
[00:02:40] [PASSED] 30.04 Xe3_LPG
[00:02:40] [PASSED] 30.05 Xe3_LPG
[00:02:40] [PASSED] 35.10 Xe3p_LPG
[00:02:40] [PASSED] 35.11 Xe3p_XPC
[00:02:40] ================ [PASSED] check_graphics_ip ================
[00:02:40] ===================== check_media_ip  ======================
[00:02:40] [PASSED] 12.00 Xe_M
[00:02:40] [PASSED] 12.55 Xe_HPM
[00:02:40] [PASSED] 13.00 Xe_LPM+
[00:02:40] [PASSED] 13.01 Xe2_HPM
[00:02:40] [PASSED] 20.00 Xe2_LPM
[00:02:40] [PASSED] 30.00 Xe3_LPM
[00:02:40] [PASSED] 30.02 Xe3_LPM
[00:02:40] [PASSED] 35.00 Xe3p_LPM
[00:02:40] [PASSED] 35.03 Xe3p_HPM
[00:02:40] ================= [PASSED] check_media_ip ==================
[00:02:40] =================== check_platform_desc  ===================
[00:02:40] [PASSED] 0x9A60 (TIGERLAKE)
[00:02:40] [PASSED] 0x9A68 (TIGERLAKE)
[00:02:40] [PASSED] 0x9A70 (TIGERLAKE)
[00:02:40] [PASSED] 0x9A40 (TIGERLAKE)
[00:02:40] [PASSED] 0x9A49 (TIGERLAKE)
[00:02:40] [PASSED] 0x9A59 (TIGERLAKE)
[00:02:40] [PASSED] 0x9A78 (TIGERLAKE)
[00:02:40] [PASSED] 0x9AC0 (TIGERLAKE)
[00:02:40] [PASSED] 0x9AC9 (TIGERLAKE)
[00:02:40] [PASSED] 0x9AD9 (TIGERLAKE)
[00:02:40] [PASSED] 0x9AF8 (TIGERLAKE)
[00:02:40] [PASSED] 0x4C80 (ROCKETLAKE)
[00:02:40] [PASSED] 0x4C8A (ROCKETLAKE)
[00:02:40] [PASSED] 0x4C8B (ROCKETLAKE)
[00:02:40] [PASSED] 0x4C8C (ROCKETLAKE)
[00:02:40] [PASSED] 0x4C90 (ROCKETLAKE)
[00:02:40] [PASSED] 0x4C9A (ROCKETLAKE)
[00:02:40] [PASSED] 0x4680 (ALDERLAKE_S)
[00:02:40] [PASSED] 0x4682 (ALDERLAKE_S)
[00:02:40] [PASSED] 0x4688 (ALDERLAKE_S)
[00:02:40] [PASSED] 0x468A (ALDERLAKE_S)
[00:02:40] [PASSED] 0x468B (ALDERLAKE_S)
[00:02:40] [PASSED] 0x4690 (ALDERLAKE_S)
[00:02:40] [PASSED] 0x4692 (ALDERLAKE_S)
[00:02:40] [PASSED] 0x4693 (ALDERLAKE_S)
[00:02:40] [PASSED] 0x46A0 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x46A1 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x46A2 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x46A3 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x46A6 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x46A8 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x46AA (ALDERLAKE_P)
[00:02:40] [PASSED] 0x462A (ALDERLAKE_P)
[00:02:40] [PASSED] 0x4626 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x4628 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x46B0 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x46B1 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x46B2 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x46B3 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x46C0 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x46C1 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x46C2 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x46C3 (ALDERLAKE_P)
[00:02:40] [PASSED] 0x46D0 (ALDERLAKE_N)
[00:02:40] [PASSED] 0x46D1 (ALDERLAKE_N)
[00:02:40] [PASSED] 0x46D2 (ALDERLAKE_N)
[00:02:40] [PASSED] 0x46D3 (ALDERLAKE_N)
[00:02:40] [PASSED] 0x46D4 (ALDERLAKE_N)
[00:02:40] [PASSED] 0xA721 (ALDERLAKE_P)
[00:02:40] [PASSED] 0xA7A1 (ALDERLAKE_P)
[00:02:40] [PASSED] 0xA7A9 (ALDERLAKE_P)
[00:02:40] [PASSED] 0xA7AC (ALDERLAKE_P)
[00:02:40] [PASSED] 0xA7AD (ALDERLAKE_P)
[00:02:40] [PASSED] 0xA720 (ALDERLAKE_P)
[00:02:40] [PASSED] 0xA7A0 (ALDERLAKE_P)
[00:02:40] [PASSED] 0xA7A8 (ALDERLAKE_P)
[00:02:40] [PASSED] 0xA7AA (ALDERLAKE_P)
[00:02:40] [PASSED] 0xA7AB (ALDERLAKE_P)
[00:02:40] [PASSED] 0xA780 (ALDERLAKE_S)
[00:02:40] [PASSED] 0xA781 (ALDERLAKE_S)
[00:02:40] [PASSED] 0xA782 (ALDERLAKE_S)
[00:02:40] [PASSED] 0xA783 (ALDERLAKE_S)
[00:02:40] [PASSED] 0xA788 (ALDERLAKE_S)
[00:02:40] [PASSED] 0xA789 (ALDERLAKE_S)
[00:02:40] [PASSED] 0xA78A (ALDERLAKE_S)
[00:02:40] [PASSED] 0xA78B (ALDERLAKE_S)
[00:02:40] [PASSED] 0x4905 (DG1)
[00:02:40] [PASSED] 0x4906 (DG1)
[00:02:40] [PASSED] 0x4907 (DG1)
[00:02:40] [PASSED] 0x4908 (DG1)
[00:02:40] [PASSED] 0x4909 (DG1)
[00:02:40] [PASSED] 0x56C0 (DG2)
[00:02:40] [PASSED] 0x56C2 (DG2)
[00:02:40] [PASSED] 0x56C1 (DG2)
[00:02:40] [PASSED] 0x7D51 (METEORLAKE)
[00:02:40] [PASSED] 0x7DD1 (METEORLAKE)
[00:02:40] [PASSED] 0x7D41 (METEORLAKE)
[00:02:40] [PASSED] 0x7D67 (METEORLAKE)
[00:02:40] [PASSED] 0xB640 (METEORLAKE)
[00:02:40] [PASSED] 0x56A0 (DG2)
[00:02:40] [PASSED] 0x56A1 (DG2)
[00:02:40] [PASSED] 0x56A2 (DG2)
[00:02:40] [PASSED] 0x56BE (DG2)
[00:02:40] [PASSED] 0x56BF (DG2)
[00:02:40] [PASSED] 0x5690 (DG2)
[00:02:40] [PASSED] 0x5691 (DG2)
[00:02:40] [PASSED] 0x5692 (DG2)
[00:02:40] [PASSED] 0x56A5 (DG2)
[00:02:40] [PASSED] 0x56A6 (DG2)
[00:02:40] [PASSED] 0x56B0 (DG2)
[00:02:40] [PASSED] 0x56B1 (DG2)
[00:02:40] [PASSED] 0x56BA (DG2)
[00:02:40] [PASSED] 0x56BB (DG2)
[00:02:40] [PASSED] 0x56BC (DG2)
[00:02:40] [PASSED] 0x56BD (DG2)
[00:02:40] [PASSED] 0x5693 (DG2)
[00:02:40] [PASSED] 0x5694 (DG2)
[00:02:40] [PASSED] 0x5695 (DG2)
[00:02:40] [PASSED] 0x56A3 (DG2)
[00:02:40] [PASSED] 0x56A4 (DG2)
[00:02:40] [PASSED] 0x56B2 (DG2)
[00:02:40] [PASSED] 0x56B3 (DG2)
[00:02:40] [PASSED] 0x5696 (DG2)
[00:02:40] [PASSED] 0x5697 (DG2)
[00:02:40] [PASSED] 0xB69 (PVC)
[00:02:40] [PASSED] 0xB6E (PVC)
[00:02:40] [PASSED] 0xBD4 (PVC)
[00:02:40] [PASSED] 0xBD5 (PVC)
[00:02:40] [PASSED] 0xBD6 (PVC)
[00:02:40] [PASSED] 0xBD7 (PVC)
[00:02:40] [PASSED] 0xBD8 (PVC)
[00:02:40] [PASSED] 0xBD9 (PVC)
[00:02:40] [PASSED] 0xBDA (PVC)
[00:02:40] [PASSED] 0xBDB (PVC)
[00:02:40] [PASSED] 0xBE0 (PVC)
[00:02:40] [PASSED] 0xBE1 (PVC)
[00:02:40] [PASSED] 0xBE5 (PVC)
[00:02:40] [PASSED] 0x7D40 (METEORLAKE)
[00:02:40] [PASSED] 0x7D45 (METEORLAKE)
[00:02:40] [PASSED] 0x7D55 (METEORLAKE)
[00:02:40] [PASSED] 0x7D60 (METEORLAKE)
[00:02:40] [PASSED] 0x7DD5 (METEORLAKE)
[00:02:40] [PASSED] 0x6420 (LUNARLAKE)
[00:02:40] [PASSED] 0x64A0 (LUNARLAKE)
[00:02:40] [PASSED] 0x64B0 (LUNARLAKE)
[00:02:40] [PASSED] 0xE202 (BATTLEMAGE)
[00:02:40] [PASSED] 0xE209 (BATTLEMAGE)
[00:02:40] [PASSED] 0xE20B (BATTLEMAGE)
[00:02:40] [PASSED] 0xE20C (BATTLEMAGE)
[00:02:40] [PASSED] 0xE20D (BATTLEMAGE)
[00:02:40] [PASSED] 0xE210 (BATTLEMAGE)
[00:02:40] [PASSED] 0xE211 (BATTLEMAGE)
[00:02:40] [PASSED] 0xE212 (BATTLEMAGE)
[00:02:40] [PASSED] 0xE216 (BATTLEMAGE)
[00:02:40] [PASSED] 0xE220 (BATTLEMAGE)
[00:02:40] [PASSED] 0xE221 (BATTLEMAGE)
[00:02:40] [PASSED] 0xE222 (BATTLEMAGE)
[00:02:40] [PASSED] 0xE223 (BATTLEMAGE)
[00:02:40] [PASSED] 0xB080 (PANTHERLAKE)
[00:02:40] [PASSED] 0xB081 (PANTHERLAKE)
[00:02:40] [PASSED] 0xB082 (PANTHERLAKE)
[00:02:40] [PASSED] 0xB083 (PANTHERLAKE)
[00:02:40] [PASSED] 0xB084 (PANTHERLAKE)
[00:02:40] [PASSED] 0xB085 (PANTHERLAKE)
[00:02:40] [PASSED] 0xB086 (PANTHERLAKE)
[00:02:40] [PASSED] 0xB087 (PANTHERLAKE)
[00:02:40] [PASSED] 0xB08F (PANTHERLAKE)
[00:02:40] [PASSED] 0xB090 (PANTHERLAKE)
[00:02:40] [PASSED] 0xB0A0 (PANTHERLAKE)
[00:02:40] [PASSED] 0xB0A1 (PANTHERLAKE)
[00:02:40] [PASSED] 0xB0B0 (PANTHERLAKE)
[00:02:40] [PASSED] 0xFD80 (PANTHERLAKE)
[00:02:40] [PASSED] 0xFD81 (PANTHERLAKE)
[00:02:40] [PASSED] 0xD740 (NOVALAKE_S)
[00:02:40] [PASSED] 0xD741 (NOVALAKE_S)
[00:02:40] [PASSED] 0xD742 (NOVALAKE_S)
[00:02:40] [PASSED] 0xD743 (NOVALAKE_S)
[00:02:40] [PASSED] 0xD745 (NOVALAKE_S)
[00:02:40] [PASSED] 0xD74A (NOVALAKE_S)
[00:02:40] [PASSED] 0xD74B (NOVALAKE_S)
[00:02:40] [PASSED] 0x674C (CRESCENTISLAND)
[00:02:40] [PASSED] 0x674D (CRESCENTISLAND)
[00:02:40] [PASSED] 0x674E (CRESCENTISLAND)
[00:02:40] [PASSED] 0x674F (CRESCENTISLAND)
[00:02:40] [PASSED] 0x6750 (CRESCENTISLAND)
[00:02:40] [PASSED] 0x6751 (CRESCENTISLAND)
[00:02:40] [PASSED] 0x6752 (CRESCENTISLAND)
[00:02:40] [PASSED] 0xD750 (NOVALAKE_P)
[00:02:40] [PASSED] 0xD751 (NOVALAKE_P)
[00:02:40] [PASSED] 0xD752 (NOVALAKE_P)
[00:02:40] [PASSED] 0xD753 (NOVALAKE_P)
[00:02:40] [PASSED] 0xD754 (NOVALAKE_P)
[00:02:40] [PASSED] 0xD755 (NOVALAKE_P)
[00:02:40] [PASSED] 0xD756 (NOVALAKE_P)
[00:02:40] [PASSED] 0xD757 (NOVALAKE_P)
[00:02:40] [PASSED] 0xD75F (NOVALAKE_P)
[00:02:40] =============== [PASSED] check_platform_desc ===============
[00:02:40] ===================== [PASSED] xe_pci ======================
[00:02:40] ============= xe_rtp_tables_test (5 subtests) ==============
[00:02:40] ================== xe_rtp_table_gt_test  ===================
[00:02:40] [PASSED] gt_was/14011060649
[00:02:40] [PASSED] gt_was/14011059788
[00:02:40] [PASSED] gt_was/14015795083
[00:02:40] [PASSED] gt_was/16021867713
[00:02:40] [PASSED] gt_was/14019449301
[00:02:40] [PASSED] gt_was/16028005424
[00:02:40] [PASSED] gt_was/14026578760
[00:02:40] [PASSED] gt_was/1409420604
[00:02:40] [PASSED] gt_was/1408615072
[00:02:40] [PASSED] gt_was/22010523718
[00:02:40] [PASSED] gt_was/14011006942
[00:02:40] [PASSED] gt_was/14014830051
[00:02:40] [PASSED] gt_was/18018781329
[00:02:40] [PASSED] gt_was/1509235366
[00:02:40] [PASSED] gt_was/18018781329
[00:02:40] [PASSED] gt_was/16016694945
[00:02:40] [PASSED] gt_was/14018575942
[00:02:40] [PASSED] gt_was/22016670082
[00:02:40] [PASSED] gt_was/22016670082
[00:02:40] [PASSED] gt_was/14017421178
[00:02:40] [PASSED] gt_was/16025250150
[00:02:40] [PASSED] gt_was/14021871409
[00:02:40] [PASSED] gt_was/16021865536
[00:02:40] [PASSED] gt_was/14021486841
[00:02:40] [PASSED] gt_was/14025160223
[00:02:40] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[00:02:40] [PASSED] gt_was/14025635424
[00:02:40] [PASSED] gt_was/16028005424
[00:02:40] ============== [PASSED] xe_rtp_table_gt_test ===============
[00:02:40] ================== xe_rtp_table_gt_test  ===================
[00:02:40] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[00:02:40] [PASSED] gt_tunings/Tuning: 32B Access Enable
[00:02:40] [PASSED] gt_tunings/Tuning: L3 cache
[00:02:40] [PASSED] gt_tunings/Tuning: L3 cache - media
[00:02:40] [PASSED] gt_tunings/Tuning: Compression Overfetch
[00:02:40] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[00:02:40] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[00:02:40] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[00:02:40] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[00:02:40] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[00:02:40] [PASSED] gt_tunings/Tuning: Stateless compression control
[00:02:40] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[00:02:40] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[00:02:40] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[00:02:40] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[00:02:40] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[00:02:40] ============== [PASSED] xe_rtp_table_gt_test ===============
[00:02:40] ================== xe_rtp_table_oob_test  ==================
[00:02:40] [PASSED] oob_was/1607983814
[00:02:40] [PASSED] oob_was/16010904313
[00:02:40] [PASSED] oob_was/18022495364
[00:02:40] [PASSED] oob_was/22012773006
[00:02:40] [PASSED] oob_was/14014475959
[00:02:40] [PASSED] oob_was/22011391025
[00:02:40] [PASSED] oob_was/22012727170
[00:02:40] [PASSED] oob_was/22012727685
[00:02:40] [PASSED] oob_was/22016596838
[00:02:40] [PASSED] oob_was/18020744125
[00:02:40] [PASSED] oob_was/1409600907
[00:02:40] [PASSED] oob_was/22014953428
[00:02:40] [PASSED] oob_was/16017236439
[00:02:40] [PASSED] oob_was/14019821291
[00:02:40] [PASSED] oob_was/14015076503
[00:02:40] [PASSED] oob_was/22016122933
[00:02:40] [PASSED] oob_was/14018913170
[00:02:40] [PASSED] oob_was/14018094691
[00:02:40] [PASSED] oob_was/18024947630
[00:02:40] [PASSED] oob_was/16022287689
[00:02:40] [PASSED] oob_was/13011645652
[00:02:40] [PASSED] oob_was/14022293748
[00:02:40] [PASSED] oob_was/22019794406
[00:02:40] [PASSED] oob_was/22019338487
[00:02:40] [PASSED] oob_was/16023588340
[00:02:40] [PASSED] oob_was/14019789679
[00:02:40] [PASSED] oob_was/14022866841
[00:02:40] [PASSED] oob_was/16021333562
[00:02:40] [PASSED] oob_was/14016712196
[00:02:40] [PASSED] oob_was/14015568240
[00:02:40] [PASSED] oob_was/18013179988
[00:02:40] [PASSED] oob_was/1508761755
[00:02:40] [PASSED] oob_was/16023105232
[00:02:40] [PASSED] oob_was/16026508708
[00:02:40] [PASSED] oob_was/14020001231
[00:02:40] [PASSED] oob_was/16023683509
[00:02:40] [PASSED] oob_was/14025515070
[00:02:40] [PASSED] oob_was/15015404425_disable
[00:02:40] [PASSED] oob_was/16026007364
[00:02:40] [PASSED] oob_was/14020316580
[00:02:40] [PASSED] oob_was/14025883347
[00:02:40] [PASSED] oob_was/16029380221
[00:02:40] [PASSED] oob_was/22022079272
[00:02:40] [PASSED] oob_was/16029897822
[00:02:40] [PASSED] oob_was/14026539277
[00:02:40] [PASSED] oob_was/14027054324
[00:02:40] [PASSED] oob_was/14025941587
[00:02:40] [PASSED] oob_was/16030224309
[00:02:40] [PASSED] oob_was/14028709524
[00:02:40] ============== [PASSED] xe_rtp_table_oob_test ==============
[00:02:40] ================ xe_rtp_table_dev_oob_test  ================
[00:02:40] [PASSED] device_oob_was/22010954014
[00:02:40] [PASSED] device_oob_was/15015404425
[00:02:40] [PASSED] device_oob_was/22019338487_display
[00:02:40] [PASSED] device_oob_was/14022085890
[00:02:40] [PASSED] device_oob_was/14026633728
[00:02:40] [PASSED] device_oob_was/14026746987
[00:02:40] [PASSED] device_oob_was/14026779378
[00:02:40] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[00:02:40] ========== xe_rtp_table_missing_upper_bound_test  ==========
[00:02:40] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[00:02:40] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[00:02:40] [PASSED] register_whitelist/1806527549
[00:02:40] [PASSED] register_whitelist/allow_read_ctx_timestamp
[00:02:40] [PASSED] register_whitelist/allow_read_queue_timestamp
[00:02:40] [PASSED] register_whitelist/16014440446
[00:02:40] [PASSED] register_whitelist/16017236439
[00:02:40] [PASSED] register_whitelist/16020183090
[00:02:40] [PASSED] register_whitelist/14024997852
[00:02:40] [PASSED] register_whitelist/14024997852
[00:02:40] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[00:02:40] =============== [PASSED] xe_rtp_tables_test ================
[00:02:40] =================== xe_rtp (3 subtests) ====================
[00:02:40] =================== xe_rtp_rules_tests  ====================
[00:02:40] [PASSED] no
[00:02:40] [PASSED] yes
[00:02:40] [PASSED] no-and-no
[00:02:40] [PASSED] no-and-yes
[00:02:40] [PASSED] yes-and-no
[00:02:40] [PASSED] yes-and-yes
[00:02:40] [PASSED] no-or-no
[00:02:40] [PASSED] no-or-yes
[00:02:40] [PASSED] yes-or-no
[00:02:40] [PASSED] yes-or-yes
[00:02:40] [PASSED] no-yes-or-yes-no
[00:02:40] [PASSED] no-yes-or-yes-yes
[00:02:40] [PASSED] yes-yes-or-no-yes
[00:02:40] [PASSED] yes-yes-or-yes-yes
[00:02:40] [PASSED] no-no-or-yes-or-no
[00:02:40] [PASSED] or
[00:02:40] [PASSED] or-yes
[00:02:40] [PASSED] or-no
[00:02:40] [PASSED] yes-or
[00:02:40] [PASSED] no-or
[00:02:40] [PASSED] no-or-or-yes
[00:02:40] [PASSED] yes-or-or-no
[00:02:40] [PASSED] no-or-or-no
[00:02:40] [PASSED] missing-context-engine-class
[00:02:40] [PASSED] missing-context-engine-class-or-yes
[00:02:40] [PASSED] missing-context-engine-class-or-or-yes
[00:02:40] =============== [PASSED] xe_rtp_rules_tests ================
[00:02:40] =============== xe_rtp_process_to_sr_tests  ================
[00:02:40] [PASSED] coalesce-same-reg
[00:02:40] [PASSED] coalesce-same-reg-literal-and-func
[00:02:40] [PASSED] no-match-no-add
[00:02:40] [PASSED] two-regs-two-entries
[00:02:40] [PASSED] clr-one-set-other
[00:02:40] [PASSED] set-field
[00:02:40] [PASSED] conflict-duplicate
[00:02:40] [PASSED] conflict-not-disjoint
[00:02:40] [PASSED] conflict-not-disjoint-literal-and-func
[00:02:40] [PASSED] conflict-reg-type
[00:02:40] [PASSED] bad-mcr-reg-forced-to-regular
[00:02:40] [PASSED] bad-regular-reg-forced-to-mcr
[00:02:40] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[00:02:40] ================== xe_rtp_process_tests  ===================
[00:02:40] [PASSED] active1
[00:02:40] [PASSED] active2
[00:02:40] [PASSED] active-inactive
[00:02:40] [PASSED] inactive-active
[00:02:40] [PASSED] inactive-active-inactive
[00:02:40] [PASSED] inactive-inactive-inactive
[00:02:40] ============== [PASSED] xe_rtp_process_tests ===============
[00:02:40] ===================== [PASSED] xe_rtp ======================
[00:02:40] ==================== xe_wa (1 subtest) =====================
[00:02:40] ======================== xe_wa_gt  =========================
[00:02:40] [PASSED] TIGERLAKE B0
[00:02:40] [PASSED] DG1 A0
[00:02:40] [PASSED] DG1 B0
[00:02:40] [PASSED] ALDERLAKE_S A0
[00:02:40] [PASSED] ALDERLAKE_S B0
[00:02:40] [PASSED] ALDERLAKE_S C0
[00:02:40] [PASSED] ALDERLAKE_S D0
[00:02:40] [PASSED] ALDERLAKE_P A0
[00:02:40] [PASSED] ALDERLAKE_P B0
[00:02:40] [PASSED] ALDERLAKE_P C0
[00:02:40] [PASSED] ALDERLAKE_S RPLS D0
[00:02:40] [PASSED] ALDERLAKE_P RPLU E0
[00:02:40] [PASSED] DG2 G10 C0
[00:02:40] [PASSED] DG2 G11 B1
[00:02:40] [PASSED] DG2 G12 A1
[00:02:40] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[00:02:40] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[00:02:40] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[00:02:40] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[00:02:40] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[00:02:40] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[00:02:40] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[00:02:40] ==================== [PASSED] xe_wa_gt =====================
[00:02:40] ====================== [PASSED] xe_wa ======================
[00:02:40] ============================================================
[00:02:40] Testing complete. Ran 840 tests: passed: 811, skipped: 29
[00:02:40] Elapsed time: 41.169s total, 2.559s configuring, 37.893s building, 0.707s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[00:02:40] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:02:43] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:03:08] Starting KUnit Kernel (1/1)...
[00:03:08] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:03:08] ============ drm_test_pick_cmdline (2 subtests) ============
[00:03:08] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[00:03:08] =============== drm_test_pick_cmdline_named  ===============
[00:03:08] [PASSED] NTSC
[00:03:08] [PASSED] NTSC-J
[00:03:08] [PASSED] PAL
[00:03:08] [PASSED] PAL-M
[00:03:08] =========== [PASSED] drm_test_pick_cmdline_named ===========
[00:03:08] ============== [PASSED] drm_test_pick_cmdline ==============
[00:03:08] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[00:03:08] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[00:03:08] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[00:03:08] =========== drm_validate_clone_mode (2 subtests) ===========
[00:03:08] ============== drm_test_check_in_clone_mode  ===============
[00:03:08] [PASSED] in_clone_mode
[00:03:08] [PASSED] not_in_clone_mode
[00:03:08] ========== [PASSED] drm_test_check_in_clone_mode ===========
[00:03:08] =============== drm_test_check_valid_clones  ===============
[00:03:08] [PASSED] not_in_clone_mode
[00:03:08] [PASSED] valid_clone
[00:03:08] [PASSED] invalid_clone
[00:03:08] =========== [PASSED] drm_test_check_valid_clones ===========
[00:03:08] ============= [PASSED] drm_validate_clone_mode =============
[00:03:08] ============= drm_validate_modeset (1 subtest) =============
[00:03:08] [PASSED] drm_test_check_connector_changed_modeset
[00:03:08] ============== [PASSED] drm_validate_modeset ===============
[00:03:08] ====== drm_test_bridge_get_current_state (1 subtest) =======
[00:03:08] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[00:03:08] ======== [PASSED] drm_test_bridge_get_current_state ========
[00:03:08] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[00:03:08] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[00:03:08] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[00:03:08] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[00:03:08] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[00:03:08] ============== drm_bridge_alloc (2 subtests) ===============
[00:03:08] [PASSED] drm_test_drm_bridge_alloc_basic
[00:03:08] [PASSED] drm_test_drm_bridge_alloc_get_put
[00:03:08] ================ [PASSED] drm_bridge_alloc =================
[00:03:08] ============= drm_bridge_bus_fmt (5 subtests) ==============
[00:03:08] [PASSED] drm_test_bridge_rgb_yuv_rgb
[00:03:08] [PASSED] drm_test_bridge_must_convert_to_yuv444
[00:03:08] [PASSED] drm_test_bridge_hdmi_auto_rgb
[00:03:08] [PASSED] drm_test_bridge_auto_first
[00:03:08] [PASSED] drm_test_bridge_rgb_yuv_no_path
[00:03:08] =============== [PASSED] drm_bridge_bus_fmt ================
[00:03:08] ============= drm_cmdline_parser (40 subtests) =============
[00:03:08] [PASSED] drm_test_cmdline_force_d_only
[00:03:08] [PASSED] drm_test_cmdline_force_D_only_dvi
[00:03:08] [PASSED] drm_test_cmdline_force_D_only_hdmi
[00:03:08] [PASSED] drm_test_cmdline_force_D_only_not_digital
[00:03:08] [PASSED] drm_test_cmdline_force_e_only
[00:03:08] [PASSED] drm_test_cmdline_res
[00:03:08] [PASSED] drm_test_cmdline_res_vesa
[00:03:08] [PASSED] drm_test_cmdline_res_vesa_rblank
[00:03:08] [PASSED] drm_test_cmdline_res_rblank
[00:03:08] [PASSED] drm_test_cmdline_res_bpp
[00:03:08] [PASSED] drm_test_cmdline_res_refresh
[00:03:08] [PASSED] drm_test_cmdline_res_bpp_refresh
[00:03:08] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[00:03:08] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[00:03:08] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[00:03:08] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[00:03:08] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[00:03:08] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[00:03:08] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[00:03:08] [PASSED] drm_test_cmdline_res_margins_force_on
[00:03:08] [PASSED] drm_test_cmdline_res_vesa_margins
[00:03:08] [PASSED] drm_test_cmdline_name
[00:03:08] [PASSED] drm_test_cmdline_name_bpp
[00:03:08] [PASSED] drm_test_cmdline_name_option
[00:03:08] [PASSED] drm_test_cmdline_name_bpp_option
[00:03:08] [PASSED] drm_test_cmdline_rotate_0
[00:03:08] [PASSED] drm_test_cmdline_rotate_90
[00:03:08] [PASSED] drm_test_cmdline_rotate_180
[00:03:08] [PASSED] drm_test_cmdline_rotate_270
[00:03:08] [PASSED] drm_test_cmdline_hmirror
[00:03:08] [PASSED] drm_test_cmdline_vmirror
[00:03:08] [PASSED] drm_test_cmdline_margin_options
[00:03:08] [PASSED] drm_test_cmdline_multiple_options
[00:03:08] [PASSED] drm_test_cmdline_bpp_extra_and_option
[00:03:08] [PASSED] drm_test_cmdline_extra_and_option
[00:03:08] [PASSED] drm_test_cmdline_freestanding_options
[00:03:08] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[00:03:08] [PASSED] drm_test_cmdline_panel_orientation
[00:03:08] ================ drm_test_cmdline_invalid  =================
[00:03:08] [PASSED] margin_only
[00:03:08] [PASSED] interlace_only
[00:03:08] [PASSED] res_missing_x
[00:03:08] [PASSED] res_missing_y
[00:03:08] [PASSED] res_bad_y
[00:03:08] [PASSED] res_missing_y_bpp
[00:03:08] [PASSED] res_bad_bpp
[00:03:08] [PASSED] res_bad_refresh
[00:03:08] [PASSED] res_bpp_refresh_force_on_off
[00:03:08] [PASSED] res_invalid_mode
[00:03:08] [PASSED] res_bpp_wrong_place_mode
[00:03:08] [PASSED] name_bpp_refresh
[00:03:08] [PASSED] name_refresh
[00:03:08] [PASSED] name_refresh_wrong_mode
[00:03:08] [PASSED] name_refresh_invalid_mode
[00:03:08] [PASSED] rotate_multiple
[00:03:08] [PASSED] rotate_invalid_val
[00:03:08] [PASSED] rotate_truncated
[00:03:08] [PASSED] invalid_option
[00:03:08] [PASSED] invalid_tv_option
[00:03:08] [PASSED] truncated_tv_option
[00:03:08] ============ [PASSED] drm_test_cmdline_invalid =============
[00:03:08] =============== drm_test_cmdline_tv_options  ===============
[00:03:08] [PASSED] NTSC
[00:03:08] [PASSED] NTSC_443
[00:03:08] [PASSED] NTSC_J
[00:03:08] [PASSED] PAL
[00:03:08] [PASSED] PAL_M
[00:03:08] [PASSED] PAL_N
[00:03:08] [PASSED] SECAM
[00:03:08] [PASSED] MONO_525
[00:03:08] [PASSED] MONO_625
[00:03:08] =========== [PASSED] drm_test_cmdline_tv_options ===========
[00:03:08] =============== [PASSED] drm_cmdline_parser ================
[00:03:08] ========== drmm_connector_hdmi_init (20 subtests) ==========
[00:03:08] [PASSED] drm_test_connector_hdmi_init_valid
[00:03:08] [PASSED] drm_test_connector_hdmi_init_bpc_8
[00:03:08] [PASSED] drm_test_connector_hdmi_init_bpc_10
[00:03:08] [PASSED] drm_test_connector_hdmi_init_bpc_12
[00:03:08] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[00:03:08] [PASSED] drm_test_connector_hdmi_init_bpc_null
[00:03:08] [PASSED] drm_test_connector_hdmi_init_formats_empty
[00:03:08] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[00:03:08] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[00:03:08] [PASSED] supported_formats=0x9 yuv420_allowed=1
[00:03:08] [PASSED] supported_formats=0x9 yuv420_allowed=0
[00:03:08] [PASSED] supported_formats=0x5 yuv420_allowed=1
[00:03:08] [PASSED] supported_formats=0x5 yuv420_allowed=0
[00:03:08] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[00:03:08] [PASSED] drm_test_connector_hdmi_init_null_ddc
[00:03:08] [PASSED] drm_test_connector_hdmi_init_null_product
[00:03:08] [PASSED] drm_test_connector_hdmi_init_null_vendor
[00:03:08] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[00:03:08] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[00:03:08] [PASSED] drm_test_connector_hdmi_init_product_valid
[00:03:08] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[00:03:08] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[00:03:08] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[00:03:08] ========= drm_test_connector_hdmi_init_type_valid  =========
[00:03:08] [PASSED] HDMI-A
[00:03:08] [PASSED] HDMI-B
[00:03:08] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[00:03:08] ======== drm_test_connector_hdmi_init_type_invalid  ========
[00:03:08] [PASSED] Unknown
[00:03:08] [PASSED] VGA
[00:03:08] [PASSED] DVI-I
[00:03:08] [PASSED] DVI-D
[00:03:08] [PASSED] DVI-A
[00:03:08] [PASSED] Composite
[00:03:08] [PASSED] SVIDEO
[00:03:08] [PASSED] LVDS
[00:03:08] [PASSED] Component
[00:03:08] [PASSED] DIN
[00:03:08] [PASSED] DP
[00:03:08] [PASSED] TV
[00:03:08] [PASSED] eDP
[00:03:08] [PASSED] Virtual
[00:03:08] [PASSED] DSI
[00:03:08] [PASSED] DPI
[00:03:08] [PASSED] Writeback
[00:03:08] [PASSED] SPI
[00:03:08] [PASSED] USB
[00:03:08] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[00:03:08] ============ [PASSED] drmm_connector_hdmi_init =============
[00:03:08] ============= drmm_connector_init (3 subtests) =============
[00:03:08] [PASSED] drm_test_drmm_connector_init
[00:03:08] [PASSED] drm_test_drmm_connector_init_null_ddc
[00:03:08] ========= drm_test_drmm_connector_init_type_valid  =========
[00:03:08] [PASSED] Unknown
[00:03:08] [PASSED] VGA
[00:03:08] [PASSED] DVI-I
[00:03:08] [PASSED] DVI-D
[00:03:08] [PASSED] DVI-A
[00:03:08] [PASSED] Composite
[00:03:08] [PASSED] SVIDEO
[00:03:08] [PASSED] LVDS
[00:03:08] [PASSED] Component
[00:03:08] [PASSED] DIN
[00:03:08] [PASSED] DP
[00:03:08] [PASSED] HDMI-A
[00:03:08] [PASSED] HDMI-B
[00:03:08] [PASSED] TV
[00:03:08] [PASSED] eDP
[00:03:08] [PASSED] Virtual
[00:03:08] [PASSED] DSI
[00:03:08] [PASSED] DPI
[00:03:08] [PASSED] Writeback
[00:03:08] [PASSED] SPI
[00:03:08] [PASSED] USB
[00:03:08] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[00:03:08] =============== [PASSED] drmm_connector_init ===============
[00:03:08] ========= drm_connector_dynamic_init (6 subtests) ==========
[00:03:08] [PASSED] drm_test_drm_connector_dynamic_init
[00:03:08] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[00:03:08] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[00:03:08] [PASSED] drm_test_drm_connector_dynamic_init_properties
[00:03:08] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[00:03:08] [PASSED] Unknown
[00:03:08] [PASSED] VGA
[00:03:08] [PASSED] DVI-I
[00:03:08] [PASSED] DVI-D
[00:03:08] [PASSED] DVI-A
[00:03:08] [PASSED] Composite
[00:03:08] [PASSED] SVIDEO
[00:03:08] [PASSED] LVDS
[00:03:08] [PASSED] Component
[00:03:08] [PASSED] DIN
[00:03:08] [PASSED] DP
[00:03:08] [PASSED] HDMI-A
[00:03:08] [PASSED] HDMI-B
[00:03:08] [PASSED] TV
[00:03:08] [PASSED] eDP
[00:03:08] [PASSED] Virtual
[00:03:08] [PASSED] DSI
[00:03:08] [PASSED] DPI
[00:03:08] [PASSED] Writeback
[00:03:08] [PASSED] SPI
[00:03:08] [PASSED] USB
[00:03:08] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[00:03:08] ======== drm_test_drm_connector_dynamic_init_name  =========
[00:03:08] [PASSED] Unknown
[00:03:08] [PASSED] VGA
[00:03:08] [PASSED] DVI-I
[00:03:08] [PASSED] DVI-D
[00:03:08] [PASSED] DVI-A
[00:03:08] [PASSED] Composite
[00:03:08] [PASSED] SVIDEO
[00:03:08] [PASSED] LVDS
[00:03:08] [PASSED] Component
[00:03:08] [PASSED] DIN
[00:03:08] [PASSED] DP
[00:03:08] [PASSED] HDMI-A
[00:03:08] [PASSED] HDMI-B
[00:03:08] [PASSED] TV
[00:03:08] [PASSED] eDP
[00:03:08] [PASSED] Virtual
[00:03:08] [PASSED] DSI
[00:03:08] [PASSED] DPI
[00:03:08] [PASSED] Writeback
[00:03:08] [PASSED] SPI
[00:03:08] [PASSED] USB
[00:03:08] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[00:03:08] =========== [PASSED] drm_connector_dynamic_init ============
[00:03:08] ==== drm_connector_dynamic_register_early (4 subtests) =====
[00:03:08] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[00:03:08] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[00:03:08] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[00:03:08] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[00:03:08] ====== [PASSED] drm_connector_dynamic_register_early =======
[00:03:08] ======= drm_connector_dynamic_register (7 subtests) ========
[00:03:08] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[00:03:08] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[00:03:08] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[00:03:08] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[00:03:08] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[00:03:08] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[00:03:08] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[00:03:08] ========= [PASSED] drm_connector_dynamic_register ==========
[00:03:08] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[00:03:08] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[00:03:08] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[00:03:08] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[00:03:08] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[00:03:08] ========== drm_test_get_tv_mode_from_name_valid  ===========
[00:03:08] [PASSED] NTSC
[00:03:08] [PASSED] NTSC-443
[00:03:08] [PASSED] NTSC-J
[00:03:08] [PASSED] PAL
[00:03:08] [PASSED] PAL-M
[00:03:08] [PASSED] PAL-N
[00:03:08] [PASSED] SECAM
[00:03:08] [PASSED] Mono
[00:03:08] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[00:03:08] [PASSED] drm_test_get_tv_mode_from_name_truncated
[00:03:08] ============ [PASSED] drm_get_tv_mode_from_name ============
[00:03:08] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[00:03:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[00:03:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[00:03:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[00:03:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[00:03:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[00:03:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[00:03:08] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[00:03:08] [PASSED] VIC 96
[00:03:08] [PASSED] VIC 97
[00:03:08] [PASSED] VIC 101
[00:03:08] [PASSED] VIC 102
[00:03:08] [PASSED] VIC 106
[00:03:08] [PASSED] VIC 107
[00:03:08] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[00:03:08] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[00:03:08] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[00:03:08] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[00:03:08] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[00:03:08] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[00:03:08] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[00:03:08] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[00:03:08] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[00:03:08] [PASSED] Automatic
[00:03:08] [PASSED] Full
[00:03:08] [PASSED] Limited 16:235
[00:03:08] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[00:03:08] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[00:03:08] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[00:03:08] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[00:03:08] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[00:03:08] [PASSED] RGB
[00:03:08] [PASSED] YUV 4:2:0
[00:03:08] [PASSED] YUV 4:2:2
[00:03:08] [PASSED] YUV 4:4:4
[00:03:08] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[00:03:08] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[00:03:08] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[00:03:08] ============= drm_damage_helper (21 subtests) ==============
[00:03:08] [PASSED] drm_test_damage_iter_no_damage
[00:03:08] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[00:03:08] [PASSED] drm_test_damage_iter_no_damage_src_moved
[00:03:08] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[00:03:08] [PASSED] drm_test_damage_iter_no_damage_not_visible
[00:03:08] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[00:03:08] [PASSED] drm_test_damage_iter_no_damage_no_fb
[00:03:08] [PASSED] drm_test_damage_iter_simple_damage
[00:03:08] [PASSED] drm_test_damage_iter_single_damage
[00:03:08] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[00:03:08] [PASSED] drm_test_damage_iter_single_damage_outside_src
[00:03:08] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[00:03:08] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[00:03:08] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[00:03:08] [PASSED] drm_test_damage_iter_single_damage_src_moved
[00:03:08] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[00:03:08] [PASSED] drm_test_damage_iter_damage
[00:03:08] [PASSED] drm_test_damage_iter_damage_one_intersect
[00:03:08] [PASSED] drm_test_damage_iter_damage_one_outside
[00:03:08] [PASSED] drm_test_damage_iter_damage_src_moved
[00:03:08] [PASSED] drm_test_damage_iter_damage_not_visible
[00:03:08] ================ [PASSED] drm_damage_helper ================
[00:03:08] ============== drm_dp_mst_helper (3 subtests) ==============
[00:03:08] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[00:03:08] [PASSED] Clock 154000 BPP 30 DSC disabled
[00:03:08] [PASSED] Clock 234000 BPP 30 DSC disabled
[00:03:08] [PASSED] Clock 297000 BPP 24 DSC disabled
[00:03:08] [PASSED] Clock 332880 BPP 24 DSC enabled
[00:03:08] [PASSED] Clock 324540 BPP 24 DSC enabled
[00:03:08] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[00:03:08] ============== drm_test_dp_mst_calc_pbn_div  ===============
[00:03:08] [PASSED] Link rate 2000000 lane count 4
[00:03:08] [PASSED] Link rate 2000000 lane count 2
[00:03:08] [PASSED] Link rate 2000000 lane count 1
[00:03:08] [PASSED] Link rate 1350000 lane count 4
[00:03:08] [PASSED] Link rate 1350000 lane count 2
[00:03:08] [PASSED] Link rate 1350000 lane count 1
[00:03:08] [PASSED] Link rate 1000000 lane count 4
[00:03:08] [PASSED] Link rate 1000000 lane count 2
[00:03:08] [PASSED] Link rate 1000000 lane count 1
[00:03:08] [PASSED] Link rate 810000 lane count 4
[00:03:08] [PASSED] Link rate 810000 lane count 2
[00:03:08] [PASSED] Link rate 810000 lane count 1
[00:03:08] [PASSED] Link rate 540000 lane count 4
[00:03:08] [PASSED] Link rate 540000 lane count 2
[00:03:08] [PASSED] Link rate 540000 lane count 1
[00:03:08] [PASSED] Link rate 270000 lane count 4
[00:03:08] [PASSED] Link rate 270000 lane count 2
[00:03:08] [PASSED] Link rate 270000 lane count 1
[00:03:08] [PASSED] Link rate 162000 lane count 4
[00:03:08] [PASSED] Link rate 162000 lane count 2
[00:03:08] [PASSED] Link rate 162000 lane count 1
[00:03:08] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[00:03:08] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[00:03:08] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[00:03:08] [PASSED] DP_POWER_UP_PHY with port number
[00:03:08] [PASSED] DP_POWER_DOWN_PHY with port number
[00:03:08] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[00:03:08] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[00:03:08] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[00:03:08] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[00:03:08] [PASSED] DP_QUERY_PAYLOAD with port number
[00:03:08] [PASSED] DP_QUERY_PAYLOAD with VCPI
[00:03:08] [PASSED] DP_REMOTE_DPCD_READ with port number
[00:03:08] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[00:03:08] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[00:03:08] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[00:03:08] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[00:03:08] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[00:03:08] [PASSED] DP_REMOTE_I2C_READ with port number
[00:03:08] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[00:03:08] [PASSED] DP_REMOTE_I2C_READ with transactions array
[00:03:08] [PASSED] DP_REMOTE_I2C_WRITE with port number
[00:03:08] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[00:03:08] [PASSED] DP_REMOTE_I2C_WRITE with data array
[00:03:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[00:03:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[00:03:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[00:03:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[00:03:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[00:03:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[00:03:08] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[00:03:08] ================ [PASSED] drm_dp_mst_helper ================
[00:03:08] ================== drm_exec (7 subtests) ===================
[00:03:08] [PASSED] sanitycheck
[00:03:08] [PASSED] test_lock
[00:03:08] [PASSED] test_lock_unlock
[00:03:08] [PASSED] test_duplicates
[00:03:08] [PASSED] test_prepare
[00:03:08] [PASSED] test_prepare_array
[00:03:08] [PASSED] test_multiple_loops
[00:03:08] ==================== [PASSED] drm_exec =====================
[00:03:08] =========== drm_format_helper_test (17 subtests) ===========
[00:03:08] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[00:03:08] [PASSED] single_pixel_source_buffer
[00:03:08] [PASSED] single_pixel_clip_rectangle
[00:03:08] [PASSED] well_known_colors
[00:03:08] [PASSED] destination_pitch
[00:03:08] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[00:03:08] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[00:03:08] [PASSED] single_pixel_source_buffer
[00:03:08] [PASSED] single_pixel_clip_rectangle
[00:03:08] [PASSED] well_known_colors
[00:03:08] [PASSED] destination_pitch
[00:03:08] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[00:03:08] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[00:03:08] [PASSED] single_pixel_source_buffer
[00:03:08] [PASSED] single_pixel_clip_rectangle
[00:03:08] [PASSED] well_known_colors
[00:03:08] [PASSED] destination_pitch
[00:03:08] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[00:03:08] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[00:03:08] [PASSED] single_pixel_source_buffer
[00:03:08] [PASSED] single_pixel_clip_rectangle
[00:03:08] [PASSED] well_known_colors
[00:03:08] [PASSED] destination_pitch
[00:03:08] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[00:03:08] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[00:03:08] [PASSED] single_pixel_source_buffer
[00:03:08] [PASSED] single_pixel_clip_rectangle
[00:03:08] [PASSED] well_known_colors
[00:03:08] [PASSED] destination_pitch
[00:03:08] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[00:03:08] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[00:03:08] [PASSED] single_pixel_source_buffer
[00:03:08] [PASSED] single_pixel_clip_rectangle
[00:03:08] [PASSED] well_known_colors
[00:03:08] [PASSED] destination_pitch
[00:03:08] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[00:03:08] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[00:03:08] [PASSED] single_pixel_source_buffer
[00:03:08] [PASSED] single_pixel_clip_rectangle
[00:03:08] [PASSED] well_known_colors
[00:03:08] [PASSED] destination_pitch
[00:03:08] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[00:03:08] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[00:03:08] [PASSED] single_pixel_source_buffer
[00:03:08] [PASSED] single_pixel_clip_rectangle
[00:03:08] [PASSED] well_known_colors
[00:03:08] [PASSED] destination_pitch
[00:03:08] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[00:03:08] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[00:03:08] [PASSED] single_pixel_source_buffer
[00:03:08] [PASSED] single_pixel_clip_rectangle
[00:03:08] [PASSED] well_known_colors
[00:03:08] [PASSED] destination_pitch
[00:03:08] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[00:03:08] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[00:03:08] [PASSED] single_pixel_source_buffer
[00:03:08] [PASSED] single_pixel_clip_rectangle
[00:03:08] [PASSED] well_known_colors
[00:03:08] [PASSED] destination_pitch
[00:03:08] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[00:03:08] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[00:03:08] [PASSED] single_pixel_source_buffer
[00:03:08] [PASSED] single_pixel_clip_rectangle
[00:03:08] [PASSED] well_known_colors
[00:03:08] [PASSED] destination_pitch
[00:03:08] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[00:03:08] ============== drm_test_fb_xrgb8888_to_mono  ===============
[00:03:08] [PASSED] single_pixel_source_buffer
[00:03:08] [PASSED] single_pixel_clip_rectangle
[00:03:08] [PASSED] well_known_colors
[00:03:08] [PASSED] destination_pitch
[00:03:08] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[00:03:08] ==================== drm_test_fb_swab  =====================
[00:03:08] [PASSED] single_pixel_source_buffer
[00:03:08] [PASSED] single_pixel_clip_rectangle
[00:03:08] [PASSED] well_known_colors
[00:03:08] [PASSED] destination_pitch
[00:03:08] ================ [PASSED] drm_test_fb_swab =================
[00:03:08] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[00:03:08] [PASSED] single_pixel_source_buffer
[00:03:08] [PASSED] single_pixel_clip_rectangle
[00:03:08] [PASSED] well_known_colors
[00:03:08] [PASSED] destination_pitch
[00:03:08] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[00:03:08] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[00:03:08] [PASSED] single_pixel_source_buffer
[00:03:08] [PASSED] single_pixel_clip_rectangle
[00:03:08] [PASSED] well_known_colors
[00:03:08] [PASSED] destination_pitch
[00:03:08] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[00:03:08] ================= drm_test_fb_clip_offset  =================
[00:03:08] [PASSED] pass through
[00:03:08] [PASSED] horizontal offset
[00:03:08] [PASSED] vertical offset
[00:03:08] [PASSED] horizontal and vertical offset
[00:03:08] [PASSED] horizontal offset (custom pitch)
[00:03:08] [PASSED] vertical offset (custom pitch)
[00:03:08] [PASSED] horizontal and vertical offset (custom pitch)
[00:03:08] ============= [PASSED] drm_test_fb_clip_offset =============
[00:03:08] =================== drm_test_fb_memcpy  ====================
[00:03:08] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[00:03:08] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[00:03:08] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[00:03:08] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[00:03:08] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[00:03:08] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[00:03:08] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[00:03:08] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[00:03:08] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[00:03:08] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[00:03:08] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[00:03:08] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[00:03:08] =============== [PASSED] drm_test_fb_memcpy ================
[00:03:08] ============= [PASSED] drm_format_helper_test ==============
[00:03:08] ================= drm_format (18 subtests) =================
[00:03:08] [PASSED] drm_test_format_block_width_invalid
[00:03:08] [PASSED] drm_test_format_block_width_one_plane
[00:03:08] [PASSED] drm_test_format_block_width_two_plane
[00:03:08] [PASSED] drm_test_format_block_width_three_plane
[00:03:08] [PASSED] drm_test_format_block_width_tiled
[00:03:08] [PASSED] drm_test_format_block_height_invalid
[00:03:08] [PASSED] drm_test_format_block_height_one_plane
[00:03:08] [PASSED] drm_test_format_block_height_two_plane
[00:03:08] [PASSED] drm_test_format_block_height_three_plane
[00:03:08] [PASSED] drm_test_format_block_height_tiled
[00:03:08] [PASSED] drm_test_format_min_pitch_invalid
[00:03:08] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[00:03:08] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[00:03:08] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[00:03:08] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[00:03:08] [PASSED] drm_test_format_min_pitch_two_plane
[00:03:08] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[00:03:08] [PASSED] drm_test_format_min_pitch_tiled
[00:03:08] =================== [PASSED] drm_format ====================
[00:03:08] ============== drm_framebuffer (10 subtests) ===============
[00:03:08] ========== drm_test_framebuffer_check_src_coords  ==========
[00:03:08] [PASSED] Success: source fits into fb
[00:03:08] [PASSED] Fail: overflowing fb with x-axis coordinate
[00:03:08] [PASSED] Fail: overflowing fb with y-axis coordinate
[00:03:08] [PASSED] Fail: overflowing fb with source width
[00:03:08] [PASSED] Fail: overflowing fb with source height
[00:03:08] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[00:03:08] [PASSED] drm_test_framebuffer_cleanup
[00:03:08] =============== drm_test_framebuffer_create  ===============
[00:03:08] [PASSED] ABGR8888 normal sizes
[00:03:08] [PASSED] ABGR8888 max sizes
[00:03:08] [PASSED] ABGR8888 pitch greater than min required
[00:03:08] [PASSED] ABGR8888 pitch less than min required
[00:03:08] [PASSED] ABGR8888 Invalid width
[00:03:08] [PASSED] ABGR8888 Invalid buffer handle
[00:03:08] [PASSED] No pixel format
[00:03:08] [PASSED] ABGR8888 Width 0
[00:03:08] [PASSED] ABGR8888 Height 0
[00:03:08] [PASSED] ABGR8888 Out of bound height * pitch combination
[00:03:08] [PASSED] ABGR8888 Large buffer offset
[00:03:08] [PASSED] ABGR8888 Buffer offset for inexistent plane
[00:03:08] [PASSED] ABGR8888 Invalid flag
[00:03:08] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[00:03:08] [PASSED] ABGR8888 Valid buffer modifier
[00:03:08] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[00:03:08] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[00:03:08] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[00:03:08] [PASSED] NV12 Normal sizes
[00:03:08] [PASSED] NV12 Max sizes
[00:03:08] [PASSED] NV12 Invalid pitch
[00:03:08] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[00:03:08] [PASSED] NV12 different  modifier per-plane
[00:03:08] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[00:03:08] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[00:03:08] [PASSED] NV12 Modifier for inexistent plane
[00:03:08] [PASSED] NV12 Handle for inexistent plane
[00:03:08] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[00:03:08] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[00:03:08] [PASSED] YVU420 Normal sizes
[00:03:08] [PASSED] YVU420 Max sizes
[00:03:08] [PASSED] YVU420 Invalid pitch
[00:03:08] [PASSED] YVU420 Different pitches
[00:03:08] [PASSED] YVU420 Different buffer offsets/pitches
[00:03:08] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[00:03:08] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[00:03:08] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[00:03:08] [PASSED] YVU420 Valid modifier
[00:03:08] [PASSED] YVU420 Different modifiers per plane
[00:03:08] [PASSED] YVU420 Modifier for inexistent plane
[00:03:08] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[00:03:08] [PASSED] X0L2 Normal sizes
[00:03:08] [PASSED] X0L2 Max sizes
[00:03:08] [PASSED] X0L2 Invalid pitch
[00:03:08] [PASSED] X0L2 Pitch greater than minimum required
[00:03:08] [PASSED] X0L2 Handle for inexistent plane
[00:03:08] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[00:03:08] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[00:03:08] [PASSED] X0L2 Valid modifier
[00:03:08] [PASSED] X0L2 Modifier for inexistent plane
[00:03:08] =========== [PASSED] drm_test_framebuffer_create ===========
[00:03:08] [PASSED] drm_test_framebuffer_free
[00:03:08] [PASSED] drm_test_framebuffer_init
[00:03:08] [PASSED] drm_test_framebuffer_init_bad_format
[00:03:08] [PASSED] drm_test_framebuffer_init_dev_mismatch
[00:03:08] [PASSED] drm_test_framebuffer_lookup
[00:03:08] [PASSED] drm_test_framebuffer_lookup_inexistent
[00:03:08] [PASSED] drm_test_framebuffer_modifiers_not_supported
[00:03:08] ================= [PASSED] drm_framebuffer =================
[00:03:08] ================ drm_gem_shmem (8 subtests) ================
[00:03:08] [PASSED] drm_gem_shmem_test_obj_create
[00:03:08] [PASSED] drm_gem_shmem_test_obj_create_private
[00:03:08] [PASSED] drm_gem_shmem_test_pin_pages
[00:03:08] [PASSED] drm_gem_shmem_test_vmap
[00:03:08] [PASSED] drm_gem_shmem_test_get_sg_table
[00:03:08] [PASSED] drm_gem_shmem_test_get_pages_sgt
[00:03:08] [PASSED] drm_gem_shmem_test_madvise
[00:03:08] [PASSED] drm_gem_shmem_test_purge
[00:03:08] ================== [PASSED] drm_gem_shmem ==================
[00:03:08] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[00:03:08] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[00:03:08] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[00:03:08] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[00:03:08] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[00:03:08] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[00:03:08] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[00:03:08] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[00:03:08] [PASSED] Automatic
[00:03:08] [PASSED] Full
[00:03:08] [PASSED] Limited 16:235
[00:03:08] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[00:03:08] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[00:03:08] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[00:03:08] [PASSED] drm_test_check_disable_connector
[00:03:08] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[00:03:08] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[00:03:08] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[00:03:08] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[00:03:08] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[00:03:08] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[00:03:08] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[00:03:08] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[00:03:08] [PASSED] drm_test_check_output_bpc_dvi
[00:03:08] [PASSED] drm_test_check_output_bpc_format_vic_1
[00:03:08] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[00:03:08] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[00:03:08] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[00:03:08] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[00:03:08] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[00:03:08] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[00:03:08] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[00:03:08] ============ drm_test_check_hdmi_color_format  =============
[00:03:08] [PASSED] AUTO -> RGB
[00:03:08] [PASSED] YCBCR422 -> YUV422
[00:03:08] [PASSED] YCBCR420 -> YUV420
[00:03:08] [PASSED] YCBCR444 -> YUV444
[00:03:08] [PASSED] RGB -> RGB
[00:03:08] ======== [PASSED] drm_test_check_hdmi_color_format =========
[00:03:08] ======== drm_test_check_hdmi_color_format_420_only  ========
[00:03:08] [PASSED] RGB should fail
[00:03:08] [PASSED] YUV444 should fail
[00:03:08] [PASSED] YUV422 should fail
[00:03:08] [PASSED] YUV420 should work
[00:03:08] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[00:03:08] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[00:03:08] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[00:03:08] [PASSED] drm_test_check_broadcast_rgb_value
[00:03:08] [PASSED] drm_test_check_bpc_8_value
[00:03:08] [PASSED] drm_test_check_bpc_10_value
[00:03:08] [PASSED] drm_test_check_bpc_12_value
[00:03:08] [PASSED] drm_test_check_format_value
[00:03:08] [PASSED] drm_test_check_tmds_char_value
[00:03:08] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[00:03:08] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[00:03:08] [PASSED] drm_test_check_mode_valid
[00:03:08] [PASSED] drm_test_check_mode_valid_reject
[00:03:08] [PASSED] drm_test_check_mode_valid_reject_rate
[00:03:08] [PASSED] drm_test_check_mode_valid_reject_max_clock
[00:03:08] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[00:03:08] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[00:03:08] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[00:03:08] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[00:03:08] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[00:03:08] [PASSED] drm_test_check_infoframes
[00:03:08] [PASSED] drm_test_check_reject_avi_infoframe
[00:03:08] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[00:03:08] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[00:03:08] [PASSED] drm_test_check_reject_audio_infoframe
[00:03:08] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[00:03:08] ================= drm_managed (2 subtests) =================
[00:03:08] [PASSED] drm_test_managed_release_action
[00:03:08] [PASSED] drm_test_managed_run_action
[00:03:08] =================== [PASSED] drm_managed ===================
[00:03:08] =================== drm_mm (6 subtests) ====================
[00:03:08] [PASSED] drm_test_mm_init
[00:03:08] [PASSED] drm_test_mm_debug
[00:03:08] [PASSED] drm_test_mm_align32
[00:03:08] [PASSED] drm_test_mm_align64
[00:03:08] [PASSED] drm_test_mm_lowest
[00:03:08] [PASSED] drm_test_mm_highest
[00:03:08] ===================== [PASSED] drm_mm ======================
[00:03:08] ============= drm_modes_analog_tv (5 subtests) =============
[00:03:08] [PASSED] drm_test_modes_analog_tv_mono_576i
[00:03:08] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[00:03:08] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[00:03:08] [PASSED] drm_test_modes_analog_tv_pal_576i
[00:03:08] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[00:03:08] =============== [PASSED] drm_modes_analog_tv ===============
[00:03:08] ============== drm_panic_helper (3 subtests) ===============
[00:03:08] ============= drm_test_panic_screen_user_map  ==============
[00:03:08] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[00:03:08] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[00:03:08] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[00:03:08] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[00:03:08] ========= [PASSED] drm_test_panic_screen_user_map ==========
[00:03:08] ============= drm_test_panic_screen_user_page  =============
[00:03:08] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[00:03:08] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[00:03:08] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[00:03:08] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[00:03:08] ========= [PASSED] drm_test_panic_screen_user_page =========
[00:03:08] ========== drm_test_panic_screen_user_set_pixel  ===========
[00:03:08] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[00:03:08] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[00:03:08] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[00:03:08] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[00:03:08] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[00:03:08] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[00:03:08] ================ [PASSED] drm_panic_helper =================
[00:03:08] ============== drm_plane_helper (2 subtests) ===============
[00:03:08] =============== drm_test_check_plane_state  ================
[00:03:08] [PASSED] clipping_simple
[00:03:08] [PASSED] clipping_rotate_reflect
[00:03:08] [PASSED] positioning_simple
[00:03:08] [PASSED] upscaling
[00:03:08] [PASSED] downscaling
[00:03:08] [PASSED] rounding1
[00:03:08] [PASSED] rounding2
[00:03:08] [PASSED] rounding3
[00:03:08] [PASSED] rounding4
[00:03:08] =========== [PASSED] drm_test_check_plane_state ============
[00:03:08] =========== drm_test_check_invalid_plane_state  ============
[00:03:08] [PASSED] positioning_invalid
[00:03:08] [PASSED] upscaling_invalid
[00:03:08] [PASSED] downscaling_invalid
[00:03:08] ======= [PASSED] drm_test_check_invalid_plane_state ========
[00:03:08] ================ [PASSED] drm_plane_helper =================
[00:03:08] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[00:03:08] ====== drm_test_connector_helper_tv_get_modes_check  =======
[00:03:08] [PASSED] None
[00:03:08] [PASSED] PAL
[00:03:08] [PASSED] NTSC
[00:03:08] [PASSED] Both, NTSC Default
[00:03:08] [PASSED] Both, PAL Default
[00:03:08] [PASSED] Both, NTSC Default, with PAL on command-line
[00:03:08] [PASSED] Both, PAL Default, with NTSC on command-line
[00:03:08] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[00:03:08] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[00:03:08] ================== drm_rect (9 subtests) ===================
[00:03:08] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[00:03:08] [PASSED] drm_test_rect_clip_scaled_not_clipped
[00:03:08] [PASSED] drm_test_rect_clip_scaled_clipped
[00:03:08] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[00:03:08] ================= drm_test_rect_intersect  =================
[00:03:08] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[00:03:08] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[00:03:08] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[00:03:08] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[00:03:08] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[00:03:08] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[00:03:08] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[00:03:08] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[00:03:08] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[00:03:08] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[00:03:08] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[00:03:08] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[00:03:08] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[00:03:08] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[00:03:08] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[00:03:08] ============= [PASSED] drm_test_rect_intersect =============
[00:03:08] ================ drm_test_rect_calc_hscale  ================
[00:03:08] [PASSED] normal use
[00:03:08] [PASSED] out of max range
[00:03:08] [PASSED] out of min range
[00:03:08] [PASSED] zero dst
[00:03:08] [PASSED] negative src
[00:03:08] [PASSED] negative dst
[00:03:08] ============ [PASSED] drm_test_rect_calc_hscale ============
[00:03:08] ================ drm_test_rect_calc_vscale  ================
[00:03:08] [PASSED] normal use
[00:03:08] [PASSED] out of max range
[00:03:08] [PASSED] out of min range
[00:03:08] [PASSED] zero dst
[00:03:08] [PASSED] negative src
[00:03:08] [PASSED] negative dst
[00:03:08] ============ [PASSED] drm_test_rect_calc_vscale ============
[00:03:08] ================== drm_test_rect_rotate  ===================
[00:03:08] [PASSED] reflect-x
[00:03:08] [PASSED] reflect-y
[00:03:08] [PASSED] rotate-0
[00:03:08] [PASSED] rotate-90
[00:03:08] [PASSED] rotate-180
[00:03:08] [PASSED] rotate-270
[00:03:08] ============== [PASSED] drm_test_rect_rotate ===============
[00:03:08] ================ drm_test_rect_rotate_inv  =================
[00:03:08] [PASSED] reflect-x
[00:03:08] [PASSED] reflect-y
[00:03:08] [PASSED] rotate-0
[00:03:08] [PASSED] rotate-90
[00:03:08] [PASSED] rotate-180
[00:03:08] [PASSED] rotate-270
[00:03:08] ============ [PASSED] drm_test_rect_rotate_inv =============
[00:03:08] ==================== [PASSED] drm_rect =====================
[00:03:08] ============ drm_sysfb_modeset_test (1 subtest) ============
[00:03:08] ============ drm_test_sysfb_build_fourcc_list  =============
[00:03:08] [PASSED] no native formats
[00:03:08] [PASSED] XRGB8888 as native format
[00:03:08] [PASSED] remove duplicates
[00:03:08] [PASSED] convert alpha formats
[00:03:08] [PASSED] random formats
[00:03:08] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[00:03:08] ============= [PASSED] drm_sysfb_modeset_test ==============
[00:03:08] ================== drm_fixp (2 subtests) ===================
[00:03:08] [PASSED] drm_test_int2fixp
[00:03:08] [PASSED] drm_test_sm2fixp
[00:03:08] ==================== [PASSED] drm_fixp =====================
[00:03:08] ============================================================
[00:03:08] Testing complete. Ran 667 tests: passed: 667
[00:03:08] Elapsed time: 28.000s total, 2.453s configuring, 25.082s building, 0.443s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[00:03:09] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:03:11] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:03:21] Starting KUnit Kernel (1/1)...
[00:03:21] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:03:21] ================= ttm_device (5 subtests) ==================
[00:03:21] [PASSED] ttm_device_init_basic
[00:03:21] [PASSED] ttm_device_init_multiple
[00:03:21] [PASSED] ttm_device_fini_basic
[00:03:21] [PASSED] ttm_device_init_no_vma_man
[00:03:21] ================== ttm_device_init_pools  ==================
[00:03:21] [PASSED] No DMA allocations, no DMA32 required
[00:03:21] [PASSED] DMA allocations, DMA32 required
[00:03:21] [PASSED] No DMA allocations, DMA32 required
[00:03:21] [PASSED] DMA allocations, no DMA32 required
[00:03:21] ============== [PASSED] ttm_device_init_pools ==============
[00:03:21] =================== [PASSED] ttm_device ====================
[00:03:21] ================== ttm_pool (8 subtests) ===================
[00:03:21] ================== ttm_pool_alloc_basic  ===================
[00:03:21] [PASSED] One page
[00:03:21] [PASSED] More than one page
[00:03:21] [PASSED] Above the allocation limit
[00:03:21] [PASSED] One page, with coherent DMA mappings enabled
[00:03:21] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[00:03:21] ============== [PASSED] ttm_pool_alloc_basic ===============
[00:03:21] ============== ttm_pool_alloc_basic_dma_addr  ==============
[00:03:21] [PASSED] One page
[00:03:21] [PASSED] More than one page
[00:03:21] [PASSED] Above the allocation limit
[00:03:21] [PASSED] One page, with coherent DMA mappings enabled
[00:03:21] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[00:03:21] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[00:03:21] [PASSED] ttm_pool_alloc_order_caching_match
[00:03:21] [PASSED] ttm_pool_alloc_caching_mismatch
[00:03:21] [PASSED] ttm_pool_alloc_order_mismatch
[00:03:21] [PASSED] ttm_pool_free_dma_alloc
[00:03:21] [PASSED] ttm_pool_free_no_dma_alloc
[00:03:21] [PASSED] ttm_pool_fini_basic
[00:03:21] ==================== [PASSED] ttm_pool =====================
[00:03:21] ================ ttm_resource (8 subtests) =================
[00:03:21] ================= ttm_resource_init_basic  =================
[00:03:21] [PASSED] Init resource in TTM_PL_SYSTEM
[00:03:21] [PASSED] Init resource in TTM_PL_VRAM
[00:03:21] [PASSED] Init resource in a private placement
[00:03:21] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[00:03:21] ============= [PASSED] ttm_resource_init_basic =============
[00:03:21] [PASSED] ttm_resource_init_pinned
[00:03:21] [PASSED] ttm_resource_fini_basic
[00:03:21] [PASSED] ttm_resource_manager_init_basic
[00:03:21] [PASSED] ttm_resource_manager_usage_basic
[00:03:21] [PASSED] ttm_resource_manager_set_used_basic
[00:03:21] [PASSED] ttm_sys_man_alloc_basic
[00:03:21] [PASSED] ttm_sys_man_free_basic
[00:03:21] ================== [PASSED] ttm_resource ===================
[00:03:21] =================== ttm_tt (15 subtests) ===================
[00:03:21] ==================== ttm_tt_init_basic  ====================
[00:03:21] [PASSED] Page-aligned size
[00:03:21] [PASSED] Extra pages requested
[00:03:21] ================ [PASSED] ttm_tt_init_basic ================
[00:03:21] [PASSED] ttm_tt_init_misaligned
[00:03:21] [PASSED] ttm_tt_fini_basic
[00:03:21] [PASSED] ttm_tt_fini_sg
[00:03:21] [PASSED] ttm_tt_fini_shmem
[00:03:21] [PASSED] ttm_tt_create_basic
[00:03:21] [PASSED] ttm_tt_create_invalid_bo_type
[00:03:21] [PASSED] ttm_tt_create_ttm_exists
[00:03:21] [PASSED] ttm_tt_create_failed
[00:03:21] [PASSED] ttm_tt_destroy_basic
[00:03:21] [PASSED] ttm_tt_populate_null_ttm
[00:03:21] [PASSED] ttm_tt_populate_populated_ttm
[00:03:21] [PASSED] ttm_tt_unpopulate_basic
[00:03:21] [PASSED] ttm_tt_unpopulate_empty_ttm
[00:03:21] [PASSED] ttm_tt_swapin_basic
[00:03:21] ===================== [PASSED] ttm_tt ======================
[00:03:21] =================== ttm_bo (14 subtests) ===================
[00:03:21] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[00:03:21] [PASSED] Cannot be interrupted and sleeps
[00:03:21] [PASSED] Cannot be interrupted, locks straight away
[00:03:21] [PASSED] Can be interrupted, sleeps
[00:03:21] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[00:03:21] [PASSED] ttm_bo_reserve_locked_no_sleep
[00:03:21] [PASSED] ttm_bo_reserve_no_wait_ticket
[00:03:21] [PASSED] ttm_bo_reserve_double_resv
[00:03:21] [PASSED] ttm_bo_reserve_interrupted
[00:03:21] [PASSED] ttm_bo_reserve_deadlock
[00:03:21] [PASSED] ttm_bo_unreserve_basic
[00:03:21] [PASSED] ttm_bo_unreserve_pinned
[00:03:21] [PASSED] ttm_bo_unreserve_bulk
[00:03:21] [PASSED] ttm_bo_fini_basic
[00:03:21] [PASSED] ttm_bo_fini_shared_resv
[00:03:21] [PASSED] ttm_bo_pin_basic
[00:03:21] [PASSED] ttm_bo_pin_unpin_resource
[00:03:21] [PASSED] ttm_bo_multiple_pin_one_unpin
[00:03:21] ===================== [PASSED] ttm_bo ======================
[00:03:21] ============== ttm_bo_validate (22 subtests) ===============
[00:03:21] ============== ttm_bo_init_reserved_sys_man  ===============
[00:03:21] [PASSED] Buffer object for userspace
[00:03:21] [PASSED] Kernel buffer object
[00:03:21] [PASSED] Shared buffer object
[00:03:21] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[00:03:21] ============== ttm_bo_init_reserved_mock_man  ==============
[00:03:21] [PASSED] Buffer object for userspace
[00:03:21] [PASSED] Kernel buffer object
[00:03:21] [PASSED] Shared buffer object
[00:03:21] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[00:03:21] [PASSED] ttm_bo_init_reserved_resv
[00:03:21] ================== ttm_bo_validate_basic  ==================
[00:03:21] [PASSED] Buffer object for userspace
[00:03:21] [PASSED] Kernel buffer object
[00:03:21] [PASSED] Shared buffer object
[00:03:21] ============== [PASSED] ttm_bo_validate_basic ==============
[00:03:21] [PASSED] ttm_bo_validate_invalid_placement
[00:03:21] ============= ttm_bo_validate_same_placement  ==============
[00:03:21] [PASSED] System manager
[00:03:21] [PASSED] VRAM manager
[00:03:21] ========= [PASSED] ttm_bo_validate_same_placement ==========
[00:03:21] [PASSED] ttm_bo_validate_failed_alloc
[00:03:21] [PASSED] ttm_bo_validate_pinned
[00:03:21] [PASSED] ttm_bo_validate_busy_placement
[00:03:21] ================ ttm_bo_validate_multihop  =================
[00:03:21] [PASSED] Buffer object for userspace
[00:03:21] [PASSED] Kernel buffer object
[00:03:21] [PASSED] Shared buffer object
[00:03:21] ============ [PASSED] ttm_bo_validate_multihop =============
[00:03:21] ========== ttm_bo_validate_no_placement_signaled  ==========
[00:03:21] [PASSED] Buffer object in system domain, no page vector
[00:03:21] [PASSED] Buffer object in system domain with an existing page vector
[00:03:21] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[00:03:21] ======== ttm_bo_validate_no_placement_not_signaled  ========
[00:03:21] [PASSED] Buffer object for userspace
[00:03:21] [PASSED] Kernel buffer object
[00:03:21] [PASSED] Shared buffer object
[00:03:21] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[00:03:21] [PASSED] ttm_bo_validate_move_fence_signaled
[00:03:21] ========= ttm_bo_validate_move_fence_not_signaled  =========
[00:03:21] [PASSED] Waits for GPU
[00:03:21] [PASSED] Tries to lock straight away
[00:03:21] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[00:03:21] [PASSED] ttm_bo_validate_swapout
[00:03:21] [PASSED] ttm_bo_validate_happy_evict
[00:03:21] [PASSED] ttm_bo_validate_all_pinned_evict
[00:03:21] [PASSED] ttm_bo_validate_allowed_only_evict
[00:03:21] [PASSED] ttm_bo_validate_deleted_evict
[00:03:21] [PASSED] ttm_bo_validate_busy_domain_evict
[00:03:21] [PASSED] ttm_bo_validate_evict_gutting
[00:03:21] [PASSED] ttm_bo_validate_recrusive_evict
[00:03:21] ================= [PASSED] ttm_bo_validate =================
[00:03:21] ============================================================
[00:03:21] Testing complete. Ran 102 tests: passed: 102
[00:03:22] Elapsed time: 12.927s total, 2.530s configuring, 10.182s building, 0.179s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[00:03:22] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:03:24] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:03:33] Starting KUnit Kernel (1/1)...
[00:03:33] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:03:33] =============== dma-buf-fence (12 subtests) ================
[00:03:33] [PASSED] test_sanitycheck
[00:03:33] [PASSED] test_signaling
[00:03:33] [PASSED] test_add_callback
[00:03:33] [PASSED] test_late_add_callback
[00:03:33] [PASSED] test_rm_callback
[00:03:33] [PASSED] test_late_rm_callback
[00:03:33] [PASSED] test_status
[00:03:33] [PASSED] test_error
[00:03:33] [PASSED] test_wait
[00:03:33] [PASSED] test_wait_timeout
[00:03:33] [PASSED] test_stub
[00:03:33] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[00:03:33] ================== [PASSED] dma-buf-fence ==================
[00:03:33] ============ dma-buf-fence-chain (11 subtests) =============
[00:03:33] [PASSED] test_sanitycheck
[00:03:33] [PASSED] test_find_seqno
[00:03:33] [PASSED] test_find_signaled
[00:03:33] [PASSED] test_find_out_of_order
[00:03:38] [PASSED] test_find_gap
[00:03:38] [PASSED] test_find_race
[00:03:38] [PASSED] test_signal_forward
[00:03:38] [PASSED] test_signal_backward
[00:03:38] [PASSED] test_wait_forward
[00:03:38] [PASSED] test_wait_backward
[00:03:38] [PASSED] test_wait_random
[00:03:38] =============== [PASSED] dma-buf-fence-chain ===============
[00:03:38] ============ dma-buf-fence-unwrap (11 subtests) ============
[00:03:38] [PASSED] test_sanitycheck
[00:03:38] [PASSED] test_unwrap_array
[00:03:38] [PASSED] test_unwrap_chain
[00:03:38] [PASSED] test_unwrap_chain_array
[00:03:38] [PASSED] test_unwrap_merge
[00:03:38] [PASSED] test_unwrap_merge_duplicate
[00:03:38] [PASSED] test_unwrap_merge_seqno
[00:03:38] [PASSED] test_unwrap_merge_order
[00:03:38] [PASSED] test_unwrap_merge_complex
[00:03:38] [PASSED] test_unwrap_merge_complex_seqno
[00:03:38] [PASSED] test_dedup_empty
[00:03:38] ============== [PASSED] dma-buf-fence-unwrap ===============
[00:03:38] ================ dma-buf-resv (5 subtests) =================
[00:03:38] [PASSED] test_sanitycheck
[00:03:38] ===================== test_signaling  ======================
[00:03:38] [PASSED] kernel
[00:03:38] [PASSED] write
[00:03:38] [PASSED] read
[00:03:38] [PASSED] bookkeep
[00:03:38] ================= [PASSED] test_signaling ==================
[00:03:38] ====================== test_for_each  ======================
[00:03:38] [PASSED] kernel
[00:03:38] [PASSED] write
[00:03:38] [PASSED] read
[00:03:38] [PASSED] bookkeep
[00:03:38] ================== [PASSED] test_for_each ==================
[00:03:38] ================= test_for_each_unlocked  ==================
[00:03:38] [PASSED] kernel
[00:03:38] [PASSED] write
[00:03:38] [PASSED] read
[00:03:38] [PASSED] bookkeep
[00:03:38] ============= [PASSED] test_for_each_unlocked ==============
[00:03:38] ===================== test_get_fences  =====================
[00:03:38] [PASSED] kernel
[00:03:38] [PASSED] write
[00:03:38] [PASSED] read
[00:03:38] [PASSED] bookkeep
[00:03:38] ================= [PASSED] test_get_fences =================
[00:03:38] ================== [PASSED] dma-buf-resv ===================
[00:03:38] ============================================================
[00:03:38] Testing complete. Ran 51 tests: passed: 50, skipped: 1
[00:03:38] Elapsed time: 16.480s total, 2.494s configuring, 8.664s building, 5.275s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/de: Work towards uncore elimination

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 867 bytes --]

== Series Details ==

Series: drm/i915/de: Work towards uncore elimination
URL   : https://patchwork.freedesktop.org/series/177794/
State : success

== Summary ==

CI Bug Log - changes from xe-6062-270a2e118d266160d3c015fc09b0a0804073c143_BAT -> xe-pw-177794v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (15 -> 15)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-6062-270a2e118d266160d3c015fc09b0a0804073c143 -> xe-pw-177794v1

  IGT_9177: 9177
  xe-6062-270a2e118d266160d3c015fc09b0a0804073c143: 270a2e118d266160d3c015fc09b0a0804073c143
  xe-pw-177794v1: 177794v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v1/index.html

[-- Attachment #2: Type: text/html, Size: 1415 bytes --]

✗ CI.checkpatch: warning for drm/i915/de: Work towards uncore elimination (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/de: Work towards uncore elimination (rev2)
URL   : https://patchwork.freedesktop.org/series/177794/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
3009867cd31863246e4afc138520a7a8bd37bb11
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit c3a73d96b22fe0a9807279caf23f5acc7f392cdf
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date:   Thu Nov 5 00:18:42 2026 +0200

    drm/xe: Nuke the intel_uncore_{read,write}() wrappers
    
    intel_uncore_{read,write}() are no longer needed by the
    display code. Remove them.
    
    Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+ /mt/dim checkpatch 558cbd545191410963884b6c303c05a92fb29463 drm-intel
801f2600ab0d drm/i915/de: Introduce dislay->mmio and intel_de_init()
5faa9cc3f945 drm/i915/de: Convert intel_de_{read,write}() into vfuncs
ccaac68ee12f drm/i915/de: Introduce mmio read/write templates
8ebc890a6296 drm/i915/de: Eliminate runtime overhead from DMC wakelock on pre-LNL platforms
3ebd351288dd drm/i915/de: Introduce display->mmio.lock
09cf080ad05a drm/i915/uncore: Don't meddle with mmio debug upon user forcewake
c28ac0bb65ed drm/i915/de: Move unclaimed mmio detection into display code
-:393: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#393: FILE: drivers/gpu/drm/i915/display/intel_display_params.c:147:
+intel_display_param_named(mmio_debug, int, 0400,
+	"Enable the MMIO debug code for the first N failures (default: off). "

total: 0 errors, 0 warnings, 1 checks, 730 lines checked
85fb6e02c8b9 drm/i915/de: Stop using intel_uncore_{read,write}()
c3a73d96b22f drm/xe: Nuke the intel_uncore_{read,write}() wrappers

✓ CI.KUnit: success for drm/i915/de: Work towards uncore elimination (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/de: Work towards uncore elimination (rev2)
URL   : https://patchwork.freedesktop.org/series/177794/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[07:10:59] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:11:04] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:11:24] Starting KUnit Kernel (1/1)...
[07:11:24] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:11:24] ================= gpu_buddy (14 subtests) ==================
[07:11:24] [PASSED] gpu_test_buddy_alloc_limit
[07:11:24] [PASSED] gpu_test_buddy_alloc_optimistic
[07:11:24] [PASSED] gpu_test_buddy_alloc_pessimistic
[07:11:24] [PASSED] gpu_test_buddy_alloc_pathological
[07:11:24] [PASSED] gpu_test_buddy_alloc_contiguous
[07:11:24] [PASSED] gpu_test_buddy_alloc_clear
[07:11:24] [PASSED] gpu_test_buddy_alloc_range
[07:11:25] [PASSED] gpu_test_buddy_alloc_range_bias
[07:11:25] [PASSED] gpu_test_buddy_fragmentation_performance
[07:11:26] [PASSED] gpu_test_buddy_dirty_tracker_performance
[07:11:26] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[07:11:26] [PASSED] gpu_test_buddy_offset_aligned_allocation
[07:11:26] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[07:11:26] [PASSED] gpu_test_buddy_addr_to_block
[07:11:26] ==================== [PASSED] gpu_buddy ====================
[07:11:26] ============================================================
[07:11:26] Testing complete. Ran 14 tests: passed: 14
[07:11:26] Elapsed time: 27.156s total, 5.094s configuring, 20.195s building, 1.823s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[07:11:26] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:11:29] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:12:06] Starting KUnit Kernel (1/1)...
[07:12:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:12:07] ================== guc_buf (11 subtests) ===================
[07:12:07] [PASSED] test_smallest
[07:12:07] [PASSED] test_largest
[07:12:07] [PASSED] test_granular
[07:12:07] [PASSED] test_unique
[07:12:07] [PASSED] test_overlap
[07:12:07] [PASSED] test_reusable
[07:12:07] [PASSED] test_too_big
[07:12:07] [PASSED] test_flush
[07:12:07] [PASSED] test_lookup
[07:12:07] [PASSED] test_data
[07:12:07] [PASSED] test_class
[07:12:07] ===================== [PASSED] guc_buf =====================
[07:12:07] =================== guc_dbm (7 subtests) ===================
[07:12:07] [PASSED] test_empty
[07:12:07] [PASSED] test_default
[07:12:07] ======================== test_size  ========================
[07:12:07] [PASSED] 4
[07:12:07] [PASSED] 8
[07:12:07] [PASSED] 32
[07:12:07] [PASSED] 256
[07:12:07] ==================== [PASSED] test_size ====================
[07:12:07] ======================= test_reuse  ========================
[07:12:07] [PASSED] 4
[07:12:07] [PASSED] 8
[07:12:07] [PASSED] 32
[07:12:07] [PASSED] 256
[07:12:07] =================== [PASSED] test_reuse ====================
[07:12:07] =================== test_range_overlap  ====================
[07:12:07] [PASSED] 4
[07:12:07] [PASSED] 8
[07:12:07] [PASSED] 32
[07:12:07] [PASSED] 256
[07:12:07] =============== [PASSED] test_range_overlap ================
[07:12:07] =================== test_range_compact  ====================
[07:12:07] [PASSED] 4
[07:12:07] [PASSED] 8
[07:12:07] [PASSED] 32
[07:12:07] [PASSED] 256
[07:12:07] =============== [PASSED] test_range_compact ================
[07:12:07] ==================== test_range_spare  =====================
[07:12:07] [PASSED] 4
[07:12:07] [PASSED] 8
[07:12:07] [PASSED] 32
[07:12:07] [PASSED] 256
[07:12:07] ================ [PASSED] test_range_spare =================
[07:12:07] ===================== [PASSED] guc_dbm =====================
[07:12:07] ================== guc_idm (22 subtests) ===================
[07:12:07] [PASSED] bad_init
[07:12:07] [PASSED] no_init
[07:12:07] [PASSED] init_fini
[07:12:07] [PASSED] check_init_small
[07:12:07] [PASSED] check_init_shared
[07:12:07] [PASSED] check_used
[07:12:07] [PASSED] check_quota
[07:12:07] [PASSED] check_all
[07:12:07] [PASSED] check_limits
[07:12:07] [PASSED] check_overlap
[07:12:07] [PASSED] check_overlap_alloc
[07:12:07] [PASSED] check_overlap_release
[07:12:07] [PASSED] check_overlap_partial_init
[07:12:07] [PASSED] check_overlap_partial_shared_range_blocking
[07:12:07] [PASSED] check_used_usable
[07:12:07] [PASSED] check_used_shareable
[07:12:07] [PASSED] check_used_mixed
[07:12:07] [PASSED] check_release_usable_range
[07:12:07] [PASSED] check_release_shareable_range
[07:12:07] [PASSED] check_split_boundaries
[07:12:07] [PASSED] check_shareable_spare
[07:12:07] [PASSED] check_shareable_spare_fragmented_tail
[07:12:07] ===================== [PASSED] guc_idm =====================
[07:12:07] ============== guc_klv_helpers (13 subtests) ===============
[07:12:07] [PASSED] test_count
[07:12:07] [PASSED] test_encode_u32
[07:12:07] [PASSED] test_encode_u64
[07:12:07] [PASSED] test_encode_string
[07:12:07] [PASSED] test_encode_object_raw
[07:12:07] [PASSED] test_encode_object_klv
[07:12:07] [PASSED] test_encode_object_nested
[07:12:07] [PASSED] test_encode_object_basic
[07:12:07] ===================== test_decode_u16  =====================
[07:12:07] [PASSED] empty
[07:12:07] [PASSED] valid
[07:12:07] [PASSED] max
[07:12:07] [PASSED] big
[07:12:07] [PASSED] long
[07:12:07] ================= [PASSED] test_decode_u16 =================
[07:12:07] ===================== test_decode_u32  =====================
[07:12:07] [PASSED] empty
[07:12:07] [PASSED] valid
[07:12:07] [PASSED] max
[07:12:07] [PASSED] long
[07:12:07] ================= [PASSED] test_decode_u32 =================
[07:12:07] ===================== test_decode_u64  =====================
[07:12:07] [PASSED] empty
[07:12:07] [PASSED] short
[07:12:07] [PASSED] valid
[07:12:07] [PASSED] max
[07:12:07] [PASSED] long
[07:12:07] ================= [PASSED] test_decode_u64 =================
[07:12:07] ===================== test_decode_str  =====================
[07:12:07] [PASSED] empty
[07:12:07] [PASSED] one
[07:12:07] [PASSED] one_trash
[07:12:07] [PASSED] two
[07:12:07] [PASSED] two_trash
[07:12:07] [PASSED] three
[07:12:07] [PASSED] dword
[07:12:07] [PASSED] four
[07:12:07] [PASSED] five
[07:12:07] [PASSED] six
[07:12:07] [PASSED] seven
[07:12:07] [PASSED] qword
[07:12:07] ================= [PASSED] test_decode_str =================
[07:12:07] [PASSED] test_print
[07:12:07] ================= [PASSED] guc_klv_helpers =================
[07:12:07] =================== xe_log (4 subtests) ====================
[07:12:07] [PASSED] demo_cper
[07:12:07] [PASSED] demo_dmesg
[07:12:07] ======================= test_dmesg  ========================
[07:12:07] [PASSED] test_fatal
[07:12:07] [PASSED] test_fatal_tile
[07:12:07] [PASSED] test_fatal_gt
[07:12:07] [PASSED] test_fatal_comp
[07:12:07] [PASSED] test_fatal_comp_tile
[07:12:07] [PASSED] test_fatal_comp_gt
[07:12:07] [PASSED] test_fatal_all
[07:12:07] [PASSED] test_recoverable
[07:12:07] [PASSED] test_recoverable_tile
[07:12:07] [PASSED] test_recoverable_gt
[07:12:07] [PASSED] test_recoverable_comp
[07:12:07] [PASSED] test_recoverable_comp_tile
[07:12:07] [PASSED] test_recoverable_comp_gt
[07:12:07] [PASSED] test_recoverable_all
[07:12:07] [PASSED] test_info
[07:12:07] [PASSED] test_info_tile
[07:12:07] [PASSED] test_info_gt
[07:12:07] [PASSED] test_info_err
[07:12:07] [PASSED] test_info_comp
[07:12:07] [PASSED] test_info_comp_tile
[07:12:07] [PASSED] test_info_comp_gt
[07:12:07] [PASSED] test_info_all
[07:12:07] [PASSED] test_hw_fatal
[07:12:07] [PASSED] test_hw_recoverable
[07:12:07] [PASSED] test_hw_corrected
[07:12:07] [PASSED] test_hw_informational
[07:12:07] =================== [PASSED] test_dmesg ====================
[07:12:07] ====================== test_invalid  =======================
[07:12:07] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[07:12:07] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[07:12:07] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[07:12:07] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[07:12:07] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[07:12:07] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[07:12:07] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[07:12:07] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[07:12:07] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[07:12:07] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[07:12:07] ================== [SKIPPED] test_invalid ==================
[07:12:07] ===================== [PASSED] xe_log ======================
[07:12:07] ================== no_relay (3 subtests) ===================
[07:12:07] [PASSED] xe_drops_guc2pf_if_not_ready
[07:12:07] [PASSED] xe_drops_guc2vf_if_not_ready
[07:12:07] [PASSED] xe_rejects_send_if_not_ready
[07:12:07] ==================== [PASSED] no_relay =====================
[07:12:07] ================== pf_relay (14 subtests) ==================
[07:12:07] [PASSED] pf_rejects_guc2pf_too_short
[07:12:07] [PASSED] pf_rejects_guc2pf_too_long
[07:12:07] [PASSED] pf_rejects_guc2pf_no_payload
[07:12:07] [PASSED] pf_fails_no_payload
[07:12:07] [PASSED] pf_fails_bad_origin
[07:12:07] [PASSED] pf_fails_bad_type
[07:12:07] [PASSED] pf_txn_reports_error
[07:12:07] [PASSED] pf_txn_sends_pf2guc
[07:12:07] [PASSED] pf_sends_pf2guc
[07:12:07] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[07:12:07] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[07:12:07] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[07:12:07] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[07:12:07] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[07:12:07] ==================== [PASSED] pf_relay =====================
[07:12:07] ================== vf_relay (3 subtests) ===================
[07:12:07] [PASSED] vf_rejects_guc2vf_too_short
[07:12:07] [PASSED] vf_rejects_guc2vf_too_long
[07:12:07] [PASSED] vf_rejects_guc2vf_no_payload
[07:12:07] ==================== [PASSED] vf_relay =====================
[07:12:07] ================ pf_gt_config (9 subtests) =================
[07:12:07] [PASSED] fair_contexts_1vf
[07:12:07] [PASSED] fair_doorbells_1vf
[07:12:07] [PASSED] fair_ggtt_1vf
[07:12:07] ====================== fair_vram_1vf  ======================
[07:12:07] [PASSED] 3.50 GiB
[07:12:07] [PASSED] 11.5 GiB
[07:12:07] [PASSED] 15.5 GiB
[07:12:07] [PASSED] 31.5 GiB
[07:12:07] [PASSED] 63.5 GiB
[07:12:07] [PASSED] 1.91 GiB
[07:12:07] ================== [PASSED] fair_vram_1vf ==================
[07:12:07] ================ fair_vram_1vf_admin_only  =================
[07:12:07] [PASSED] 3.50 GiB
[07:12:07] [PASSED] 11.5 GiB
[07:12:07] [PASSED] 15.5 GiB
[07:12:07] [PASSED] 31.5 GiB
[07:12:07] [PASSED] 63.5 GiB
[07:12:07] [PASSED] 1.91 GiB
[07:12:07] ============ [PASSED] fair_vram_1vf_admin_only =============
[07:12:07] ====================== fair_contexts  ======================
[07:12:07] [PASSED] 1 VF
[07:12:07] [PASSED] 2 VFs
[07:12:07] [PASSED] 3 VFs
[07:12:07] [PASSED] 4 VFs
[07:12:07] [PASSED] 5 VFs
[07:12:07] [PASSED] 6 VFs
[07:12:07] [PASSED] 7 VFs
[07:12:07] [PASSED] 8 VFs
[07:12:07] [PASSED] 9 VFs
[07:12:07] [PASSED] 10 VFs
[07:12:07] [PASSED] 11 VFs
[07:12:07] [PASSED] 12 VFs
[07:12:07] [PASSED] 13 VFs
[07:12:07] [PASSED] 14 VFs
[07:12:07] [PASSED] 15 VFs
[07:12:07] [PASSED] 16 VFs
[07:12:07] [PASSED] 17 VFs
[07:12:07] [PASSED] 18 VFs
[07:12:07] [PASSED] 19 VFs
[07:12:07] [PASSED] 20 VFs
[07:12:07] [PASSED] 21 VFs
[07:12:07] [PASSED] 22 VFs
[07:12:07] [PASSED] 23 VFs
[07:12:07] [PASSED] 24 VFs
[07:12:07] [PASSED] 25 VFs
[07:12:07] [PASSED] 26 VFs
[07:12:07] [PASSED] 27 VFs
[07:12:07] [PASSED] 28 VFs
[07:12:07] [PASSED] 29 VFs
[07:12:07] [PASSED] 30 VFs
[07:12:07] [PASSED] 31 VFs
[07:12:07] [PASSED] 32 VFs
[07:12:07] [PASSED] 33 VFs
[07:12:07] [PASSED] 34 VFs
[07:12:07] [PASSED] 35 VFs
[07:12:07] [PASSED] 36 VFs
[07:12:07] [PASSED] 37 VFs
[07:12:07] [PASSED] 38 VFs
[07:12:07] [PASSED] 39 VFs
[07:12:07] [PASSED] 40 VFs
[07:12:07] [PASSED] 41 VFs
[07:12:07] [PASSED] 42 VFs
[07:12:07] [PASSED] 43 VFs
[07:12:07] [PASSED] 44 VFs
[07:12:07] [PASSED] 45 VFs
[07:12:07] [PASSED] 46 VFs
[07:12:07] [PASSED] 47 VFs
[07:12:07] [PASSED] 48 VFs
[07:12:07] [PASSED] 49 VFs
[07:12:07] [PASSED] 50 VFs
[07:12:07] [PASSED] 51 VFs
[07:12:07] [PASSED] 52 VFs
[07:12:07] [PASSED] 53 VFs
[07:12:07] [PASSED] 54 VFs
[07:12:07] [PASSED] 55 VFs
[07:12:07] [PASSED] 56 VFs
[07:12:07] [PASSED] 57 VFs
[07:12:07] [PASSED] 58 VFs
[07:12:07] [PASSED] 59 VFs
[07:12:07] [PASSED] 60 VFs
[07:12:07] [PASSED] 61 VFs
[07:12:07] [PASSED] 62 VFs
[07:12:07] [PASSED] 63 VFs
[07:12:07] ================== [PASSED] fair_contexts ==================
[07:12:07] ===================== fair_doorbells  ======================
[07:12:07] [PASSED] 1 VF
[07:12:07] [PASSED] 2 VFs
[07:12:07] [PASSED] 3 VFs
[07:12:07] [PASSED] 4 VFs
[07:12:07] [PASSED] 5 VFs
[07:12:07] [PASSED] 6 VFs
[07:12:07] [PASSED] 7 VFs
[07:12:07] [PASSED] 8 VFs
[07:12:07] [PASSED] 9 VFs
[07:12:07] [PASSED] 10 VFs
[07:12:07] [PASSED] 11 VFs
[07:12:07] [PASSED] 12 VFs
[07:12:07] [PASSED] 13 VFs
[07:12:07] [PASSED] 14 VFs
[07:12:07] [PASSED] 15 VFs
[07:12:07] [PASSED] 16 VFs
[07:12:07] [PASSED] 17 VFs
[07:12:07] [PASSED] 18 VFs
[07:12:07] [PASSED] 19 VFs
[07:12:07] [PASSED] 20 VFs
[07:12:07] [PASSED] 21 VFs
[07:12:07] [PASSED] 22 VFs
[07:12:07] [PASSED] 23 VFs
[07:12:07] [PASSED] 24 VFs
[07:12:07] [PASSED] 25 VFs
[07:12:07] [PASSED] 26 VFs
[07:12:07] [PASSED] 27 VFs
[07:12:07] [PASSED] 28 VFs
[07:12:07] [PASSED] 29 VFs
[07:12:07] [PASSED] 30 VFs
[07:12:07] [PASSED] 31 VFs
[07:12:07] [PASSED] 32 VFs
[07:12:07] [PASSED] 33 VFs
[07:12:07] [PASSED] 34 VFs
[07:12:07] [PASSED] 35 VFs
[07:12:07] [PASSED] 36 VFs
[07:12:07] [PASSED] 37 VFs
[07:12:07] [PASSED] 38 VFs
[07:12:07] [PASSED] 39 VFs
[07:12:07] [PASSED] 40 VFs
[07:12:07] [PASSED] 41 VFs
[07:12:07] [PASSED] 42 VFs
[07:12:07] [PASSED] 43 VFs
[07:12:07] [PASSED] 44 VFs
[07:12:07] [PASSED] 45 VFs
[07:12:07] [PASSED] 46 VFs
[07:12:07] [PASSED] 47 VFs
[07:12:07] [PASSED] 48 VFs
[07:12:07] [PASSED] 49 VFs
[07:12:07] [PASSED] 50 VFs
[07:12:07] [PASSED] 51 VFs
[07:12:07] [PASSED] 52 VFs
[07:12:07] [PASSED] 53 VFs
[07:12:07] [PASSED] 54 VFs
[07:12:07] [PASSED] 55 VFs
[07:12:07] [PASSED] 56 VFs
[07:12:07] [PASSED] 57 VFs
[07:12:07] [PASSED] 58 VFs
[07:12:07] [PASSED] 59 VFs
[07:12:07] [PASSED] 60 VFs
[07:12:07] [PASSED] 61 VFs
[07:12:07] [PASSED] 62 VFs
[07:12:07] [PASSED] 63 VFs
[07:12:07] ================= [PASSED] fair_doorbells ==================
[07:12:07] ======================== fair_ggtt  ========================
[07:12:07] [PASSED] 1 VF
[07:12:07] [PASSED] 2 VFs
[07:12:07] [PASSED] 3 VFs
[07:12:07] [PASSED] 4 VFs
[07:12:07] [PASSED] 5 VFs
[07:12:07] [PASSED] 6 VFs
[07:12:07] [PASSED] 7 VFs
[07:12:07] [PASSED] 8 VFs
[07:12:07] [PASSED] 9 VFs
[07:12:07] [PASSED] 10 VFs
[07:12:07] [PASSED] 11 VFs
[07:12:07] [PASSED] 12 VFs
[07:12:07] [PASSED] 13 VFs
[07:12:07] [PASSED] 14 VFs
[07:12:07] [PASSED] 15 VFs
[07:12:07] [PASSED] 16 VFs
[07:12:07] [PASSED] 17 VFs
[07:12:07] [PASSED] 18 VFs
[07:12:07] [PASSED] 19 VFs
[07:12:07] [PASSED] 20 VFs
[07:12:07] [PASSED] 21 VFs
[07:12:07] [PASSED] 22 VFs
[07:12:07] [PASSED] 23 VFs
[07:12:07] [PASSED] 24 VFs
[07:12:07] [PASSED] 25 VFs
[07:12:07] [PASSED] 26 VFs
[07:12:07] [PASSED] 27 VFs
[07:12:07] [PASSED] 28 VFs
[07:12:07] [PASSED] 29 VFs
[07:12:07] [PASSED] 30 VFs
[07:12:07] [PASSED] 31 VFs
[07:12:07] [PASSED] 32 VFs
[07:12:07] [PASSED] 33 VFs
[07:12:07] [PASSED] 34 VFs
[07:12:07] [PASSED] 35 VFs
[07:12:07] [PASSED] 36 VFs
[07:12:07] [PASSED] 37 VFs
[07:12:07] [PASSED] 38 VFs
[07:12:07] [PASSED] 39 VFs
[07:12:07] [PASSED] 40 VFs
[07:12:07] [PASSED] 41 VFs
[07:12:07] [PASSED] 42 VFs
[07:12:07] [PASSED] 43 VFs
[07:12:07] [PASSED] 44 VFs
[07:12:07] [PASSED] 45 VFs
[07:12:07] [PASSED] 46 VFs
[07:12:07] [PASSED] 47 VFs
[07:12:07] [PASSED] 48 VFs
[07:12:07] [PASSED] 49 VFs
[07:12:07] [PASSED] 50 VFs
[07:12:07] [PASSED] 51 VFs
[07:12:07] [PASSED] 52 VFs
[07:12:07] [PASSED] 53 VFs
[07:12:07] [PASSED] 54 VFs
[07:12:07] [PASSED] 55 VFs
[07:12:07] [PASSED] 56 VFs
[07:12:07] [PASSED] 57 VFs
[07:12:07] [PASSED] 58 VFs
[07:12:07] [PASSED] 59 VFs
[07:12:07] [PASSED] 60 VFs
[07:12:07] [PASSED] 61 VFs
[07:12:07] [PASSED] 62 VFs
[07:12:07] [PASSED] 63 VFs
[07:12:07] ==================== [PASSED] fair_ggtt ====================
[07:12:07] ======================== fair_vram  ========================
[07:12:07] [PASSED] 1 VF
[07:12:07] [PASSED] 2 VFs
[07:12:07] [PASSED] 3 VFs
[07:12:07] [PASSED] 4 VFs
[07:12:07] [PASSED] 5 VFs
[07:12:07] [PASSED] 6 VFs
[07:12:07] [PASSED] 7 VFs
[07:12:07] [PASSED] 8 VFs
[07:12:07] [PASSED] 9 VFs
[07:12:07] [PASSED] 10 VFs
[07:12:07] [PASSED] 11 VFs
[07:12:07] [PASSED] 12 VFs
[07:12:07] [PASSED] 13 VFs
[07:12:07] [PASSED] 14 VFs
[07:12:07] [PASSED] 15 VFs
[07:12:07] [PASSED] 16 VFs
[07:12:07] [PASSED] 17 VFs
[07:12:07] [PASSED] 18 VFs
[07:12:07] [PASSED] 19 VFs
[07:12:07] [PASSED] 20 VFs
[07:12:07] [PASSED] 21 VFs
[07:12:07] [PASSED] 22 VFs
[07:12:07] [PASSED] 23 VFs
[07:12:07] [PASSED] 24 VFs
[07:12:07] [PASSED] 25 VFs
[07:12:07] [PASSED] 26 VFs
[07:12:07] [PASSED] 27 VFs
[07:12:07] [PASSED] 28 VFs
[07:12:07] [PASSED] 29 VFs
[07:12:07] [PASSED] 30 VFs
[07:12:07] [PASSED] 31 VFs
[07:12:07] [PASSED] 32 VFs
[07:12:07] [PASSED] 33 VFs
[07:12:07] [PASSED] 34 VFs
[07:12:07] [PASSED] 35 VFs
[07:12:07] [PASSED] 36 VFs
[07:12:07] [PASSED] 37 VFs
[07:12:07] [PASSED] 38 VFs
[07:12:07] [PASSED] 39 VFs
[07:12:07] [PASSED] 40 VFs
[07:12:07] [PASSED] 41 VFs
[07:12:07] [PASSED] 42 VFs
[07:12:07] [PASSED] 43 VFs
[07:12:07] [PASSED] 44 VFs
[07:12:07] [PASSED] 45 VFs
[07:12:07] [PASSED] 46 VFs
[07:12:07] [PASSED] 47 VFs
[07:12:07] [PASSED] 48 VFs
[07:12:07] [PASSED] 49 VFs
[07:12:07] [PASSED] 50 VFs
[07:12:07] [PASSED] 51 VFs
[07:12:07] [PASSED] 52 VFs
[07:12:07] [PASSED] 53 VFs
[07:12:07] [PASSED] 54 VFs
[07:12:07] [PASSED] 55 VFs
[07:12:07] [PASSED] 56 VFs
[07:12:07] [PASSED] 57 VFs
[07:12:07] [PASSED] 58 VFs
[07:12:07] [PASSED] 59 VFs
[07:12:07] [PASSED] 60 VFs
[07:12:07] [PASSED] 61 VFs
[07:12:07] [PASSED] 62 VFs
[07:12:07] [PASSED] 63 VFs
[07:12:07] ==================== [PASSED] fair_vram ====================
[07:12:07] ================== [PASSED] pf_gt_config ===================
[07:12:07] ===================== lmtt (1 subtest) =====================
[07:12:07] ======================== test_ops  =========================
[07:12:07] [PASSED] 2-level
[07:12:07] [PASSED] multi-level
[07:12:07] ==================== [PASSED] test_ops =====================
[07:12:07] ====================== [PASSED] lmtt =======================
[07:12:07] ================= sriov_packet (1 subtest) =================
[07:12:07] [PASSED] test_descriptor_init
[07:12:07] ================== [PASSED] sriov_packet ===================
[07:12:07] ================= pf_service (11 subtests) =================
[07:12:07] [PASSED] pf_negotiate_any
[07:12:07] [PASSED] pf_negotiate_base_match
[07:12:07] [PASSED] pf_negotiate_base_newer
[07:12:07] [PASSED] pf_negotiate_base_next
[07:12:07] [SKIPPED] pf_negotiate_base_older (no older minor)
[07:12:07] [PASSED] pf_negotiate_base_prev
[07:12:07] [PASSED] pf_negotiate_latest_match
[07:12:07] [PASSED] pf_negotiate_latest_newer
[07:12:07] [PASSED] pf_negotiate_latest_next
[07:12:07] [SKIPPED] pf_negotiate_latest_older (no older minor)
[07:12:07] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[07:12:07] =================== [PASSED] pf_service ====================
[07:12:07] ================= xe_guc_g2g (2 subtests) ==================
[07:12:07] ============== xe_live_guc_g2g_kunit_default  ==============
[07:12:07] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[07:12:07] ============== xe_live_guc_g2g_kunit_allmem  ===============
[07:12:07] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[07:12:07] =================== [SKIPPED] xe_guc_g2g ===================
[07:12:07] =================== xe_mocs (2 subtests) ===================
[07:12:07] ================ xe_live_mocs_kernel_kunit  ================
[07:12:07] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[07:12:07] ================ xe_live_mocs_reset_kunit  =================
[07:12:07] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[07:12:07] ==================== [SKIPPED] xe_mocs =====================
[07:12:07] ================= xe_migrate (3 subtests) ==================
[07:12:07] ================= xe_migrate_sanity_kunit  =================
[07:12:07] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[07:12:07] ================== xe_validate_ccs_kunit  ==================
[07:12:07] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[07:12:07] ============= xe_migrate_access_memory_kunit  ==============
[07:12:07] ========= [SKIPPED] xe_migrate_access_memory_kunit =========
[07:12:07] =================== [SKIPPED] xe_migrate ===================
[07:12:07] ================== xe_dma_buf (1 subtest) ==================
[07:12:07] ==================== xe_dma_buf_kunit  =====================
[07:12:07] ================ [SKIPPED] xe_dma_buf_kunit ================
[07:12:07] =================== [SKIPPED] xe_dma_buf ===================
[07:12:07] ================= xe_bo_shrink (1 subtest) =================
[07:12:07] =================== xe_bo_shrink_kunit  ====================
[07:12:07] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[07:12:07] ================== [SKIPPED] xe_bo_shrink ==================
[07:12:07] ==================== xe_bo (2 subtests) ====================
[07:12:07] ================== xe_ccs_migrate_kunit  ===================
[07:12:07] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[07:12:07] ==================== xe_bo_evict_kunit  ====================
[07:12:07] =============== [SKIPPED] xe_bo_evict_kunit ================
[07:12:07] ===================== [SKIPPED] xe_bo ======================
[07:12:07] =================== xe_any (9 subtests) ====================
[07:12:07] [PASSED] test_to_xe
[07:12:07] [PASSED] test_to_dev
[07:12:07] [PASSED] test_to_pdev
[07:12:07] [PASSED] test_to_drm
[07:12:07] [PASSED] test_if_pdev
[07:12:07] [PASSED] test_if_xe
[07:12:07] [PASSED] test_if_tile
[07:12:07] [PASSED] test_if_gt
[07:12:07] [PASSED] test_to_id
[07:12:07] ===================== [PASSED] xe_any ======================
[07:12:07] ==================== args (13 subtests) ====================
[07:12:07] [PASSED] count_args_test
[07:12:07] [PASSED] call_args_example
[07:12:07] [PASSED] call_args_test
[07:12:07] [PASSED] drop_first_arg_example
[07:12:07] [PASSED] drop_first_arg_test
[07:12:07] [PASSED] first_arg_example
[07:12:07] [PASSED] first_arg_test
[07:12:07] [PASSED] last_arg_example
[07:12:07] [PASSED] last_arg_test
[07:12:07] [PASSED] pick_arg_example
[07:12:07] [PASSED] if_args_example
[07:12:07] [PASSED] if_args_test
[07:12:07] [PASSED] sep_comma_example
[07:12:07] ====================== [PASSED] args =======================
[07:12:07] =================== xe_pci (3 subtests) ====================
[07:12:07] ==================== check_graphics_ip  ====================
[07:12:07] [PASSED] 12.00 Xe_LP
[07:12:07] [PASSED] 12.10 Xe_LP+
[07:12:07] [PASSED] 12.55 Xe_HPG
[07:12:07] [PASSED] 12.60 Xe_HPC
[07:12:07] [PASSED] 12.70 Xe_LPG
[07:12:07] [PASSED] 12.71 Xe_LPG
[07:12:07] [PASSED] 12.74 Xe_LPG+
[07:12:07] [PASSED] 20.01 Xe2_HPG
[07:12:07] [PASSED] 20.02 Xe2_HPG
[07:12:07] [PASSED] 20.04 Xe2_LPG
[07:12:07] [PASSED] 30.00 Xe3_LPG
[07:12:07] [PASSED] 30.01 Xe3_LPG
[07:12:07] [PASSED] 30.03 Xe3_LPG
[07:12:07] [PASSED] 30.04 Xe3_LPG
[07:12:07] [PASSED] 30.05 Xe3_LPG
[07:12:07] [PASSED] 35.10 Xe3p_LPG
[07:12:07] [PASSED] 35.11 Xe3p_XPC
[07:12:07] ================ [PASSED] check_graphics_ip ================
[07:12:07] ===================== check_media_ip  ======================
[07:12:07] [PASSED] 12.00 Xe_M
[07:12:07] [PASSED] 12.55 Xe_HPM
[07:12:07] [PASSED] 13.00 Xe_LPM+
[07:12:07] [PASSED] 13.01 Xe2_HPM
[07:12:07] [PASSED] 20.00 Xe2_LPM
[07:12:07] [PASSED] 30.00 Xe3_LPM
[07:12:07] [PASSED] 30.02 Xe3_LPM
[07:12:07] [PASSED] 35.00 Xe3p_LPM
[07:12:07] [PASSED] 35.03 Xe3p_HPM
[07:12:07] ================= [PASSED] check_media_ip ==================
[07:12:07] =================== check_platform_desc  ===================
[07:12:07] [PASSED] 0x9A60 (TIGERLAKE)
[07:12:07] [PASSED] 0x9A68 (TIGERLAKE)
[07:12:07] [PASSED] 0x9A70 (TIGERLAKE)
[07:12:07] [PASSED] 0x9A40 (TIGERLAKE)
[07:12:07] [PASSED] 0x9A49 (TIGERLAKE)
[07:12:07] [PASSED] 0x9A59 (TIGERLAKE)
[07:12:07] [PASSED] 0x9A78 (TIGERLAKE)
[07:12:07] [PASSED] 0x9AC0 (TIGERLAKE)
[07:12:07] [PASSED] 0x9AC9 (TIGERLAKE)
[07:12:07] [PASSED] 0x9AD9 (TIGERLAKE)
[07:12:07] [PASSED] 0x9AF8 (TIGERLAKE)
[07:12:07] [PASSED] 0x4C80 (ROCKETLAKE)
[07:12:07] [PASSED] 0x4C8A (ROCKETLAKE)
[07:12:07] [PASSED] 0x4C8B (ROCKETLAKE)
[07:12:07] [PASSED] 0x4C8C (ROCKETLAKE)
[07:12:07] [PASSED] 0x4C90 (ROCKETLAKE)
[07:12:07] [PASSED] 0x4C9A (ROCKETLAKE)
[07:12:07] [PASSED] 0x4680 (ALDERLAKE_S)
[07:12:07] [PASSED] 0x4682 (ALDERLAKE_S)
[07:12:07] [PASSED] 0x4688 (ALDERLAKE_S)
[07:12:07] [PASSED] 0x468A (ALDERLAKE_S)
[07:12:07] [PASSED] 0x468B (ALDERLAKE_S)
[07:12:07] [PASSED] 0x4690 (ALDERLAKE_S)
[07:12:07] [PASSED] 0x4692 (ALDERLAKE_S)
[07:12:07] [PASSED] 0x4693 (ALDERLAKE_S)
[07:12:07] [PASSED] 0x46A0 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x46A1 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x46A2 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x46A3 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x46A6 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x46A8 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x46AA (ALDERLAKE_P)
[07:12:07] [PASSED] 0x462A (ALDERLAKE_P)
[07:12:07] [PASSED] 0x4626 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x4628 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x46B0 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x46B1 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x46B2 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x46B3 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x46C0 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x46C1 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x46C2 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x46C3 (ALDERLAKE_P)
[07:12:07] [PASSED] 0x46D0 (ALDERLAKE_N)
[07:12:07] [PASSED] 0x46D1 (ALDERLAKE_N)
[07:12:07] [PASSED] 0x46D2 (ALDERLAKE_N)
[07:12:07] [PASSED] 0x46D3 (ALDERLAKE_N)
[07:12:07] [PASSED] 0x46D4 (ALDERLAKE_N)
[07:12:07] [PASSED] 0xA721 (ALDERLAKE_P)
[07:12:07] [PASSED] 0xA7A1 (ALDERLAKE_P)
[07:12:07] [PASSED] 0xA7A9 (ALDERLAKE_P)
[07:12:07] [PASSED] 0xA7AC (ALDERLAKE_P)
[07:12:07] [PASSED] 0xA7AD (ALDERLAKE_P)
[07:12:07] [PASSED] 0xA720 (ALDERLAKE_P)
[07:12:07] [PASSED] 0xA7A0 (ALDERLAKE_P)
[07:12:07] [PASSED] 0xA7A8 (ALDERLAKE_P)
[07:12:07] [PASSED] 0xA7AA (ALDERLAKE_P)
[07:12:07] [PASSED] 0xA7AB (ALDERLAKE_P)
[07:12:07] [PASSED] 0xA780 (ALDERLAKE_S)
[07:12:07] [PASSED] 0xA781 (ALDERLAKE_S)
[07:12:07] [PASSED] 0xA782 (ALDERLAKE_S)
[07:12:07] [PASSED] 0xA783 (ALDERLAKE_S)
[07:12:07] [PASSED] 0xA788 (ALDERLAKE_S)
[07:12:07] [PASSED] 0xA789 (ALDERLAKE_S)
[07:12:07] [PASSED] 0xA78A (ALDERLAKE_S)
[07:12:07] [PASSED] 0xA78B (ALDERLAKE_S)
[07:12:07] [PASSED] 0x4905 (DG1)
[07:12:07] [PASSED] 0x4906 (DG1)
[07:12:07] [PASSED] 0x4907 (DG1)
[07:12:07] [PASSED] 0x4908 (DG1)
[07:12:07] [PASSED] 0x4909 (DG1)
[07:12:07] [PASSED] 0x56C0 (DG2)
[07:12:07] [PASSED] 0x56C2 (DG2)
[07:12:07] [PASSED] 0x56C1 (DG2)
[07:12:07] [PASSED] 0x7D51 (METEORLAKE)
[07:12:07] [PASSED] 0x7DD1 (METEORLAKE)
[07:12:07] [PASSED] 0x7D41 (METEORLAKE)
[07:12:07] [PASSED] 0x7D67 (METEORLAKE)
[07:12:07] [PASSED] 0xB640 (METEORLAKE)
[07:12:07] [PASSED] 0x56A0 (DG2)
[07:12:07] [PASSED] 0x56A1 (DG2)
[07:12:07] [PASSED] 0x56A2 (DG2)
[07:12:07] [PASSED] 0x56BE (DG2)
[07:12:07] [PASSED] 0x56BF (DG2)
[07:12:07] [PASSED] 0x5690 (DG2)
[07:12:07] [PASSED] 0x5691 (DG2)
[07:12:07] [PASSED] 0x5692 (DG2)
[07:12:07] [PASSED] 0x56A5 (DG2)
[07:12:07] [PASSED] 0x56A6 (DG2)
[07:12:07] [PASSED] 0x56B0 (DG2)
[07:12:07] [PASSED] 0x56B1 (DG2)
[07:12:07] [PASSED] 0x56BA (DG2)
[07:12:07] [PASSED] 0x56BB (DG2)
[07:12:07] [PASSED] 0x56BC (DG2)
[07:12:07] [PASSED] 0x56BD (DG2)
[07:12:07] [PASSED] 0x5693 (DG2)
[07:12:07] [PASSED] 0x5694 (DG2)
[07:12:07] [PASSED] 0x5695 (DG2)
[07:12:07] [PASSED] 0x56A3 (DG2)
[07:12:07] [PASSED] 0x56A4 (DG2)
[07:12:07] [PASSED] 0x56B2 (DG2)
[07:12:07] [PASSED] 0x56B3 (DG2)
[07:12:07] [PASSED] 0x5696 (DG2)
[07:12:07] [PASSED] 0x5697 (DG2)
[07:12:07] [PASSED] 0xB69 (PVC)
[07:12:07] [PASSED] 0xB6E (PVC)
[07:12:07] [PASSED] 0xBD4 (PVC)
[07:12:07] [PASSED] 0xBD5 (PVC)
[07:12:07] [PASSED] 0xBD6 (PVC)
[07:12:07] [PASSED] 0xBD7 (PVC)
[07:12:07] [PASSED] 0xBD8 (PVC)
[07:12:07] [PASSED] 0xBD9 (PVC)
[07:12:07] [PASSED] 0xBDA (PVC)
[07:12:07] [PASSED] 0xBDB (PVC)
[07:12:07] [PASSED] 0xBE0 (PVC)
[07:12:07] [PASSED] 0xBE1 (PVC)
[07:12:07] [PASSED] 0xBE5 (PVC)
[07:12:07] [PASSED] 0x7D40 (METEORLAKE)
[07:12:07] [PASSED] 0x7D45 (METEORLAKE)
[07:12:07] [PASSED] 0x7D55 (METEORLAKE)
[07:12:07] [PASSED] 0x7D60 (METEORLAKE)
[07:12:07] [PASSED] 0x7DD5 (METEORLAKE)
[07:12:07] [PASSED] 0x6420 (LUNARLAKE)
[07:12:07] [PASSED] 0x64A0 (LUNARLAKE)
[07:12:07] [PASSED] 0x64B0 (LUNARLAKE)
[07:12:07] [PASSED] 0xE202 (BATTLEMAGE)
[07:12:07] [PASSED] 0xE209 (BATTLEMAGE)
[07:12:07] [PASSED] 0xE20B (BATTLEMAGE)
[07:12:07] [PASSED] 0xE20C (BATTLEMAGE)
[07:12:07] [PASSED] 0xE20D (BATTLEMAGE)
[07:12:07] [PASSED] 0xE210 (BATTLEMAGE)
[07:12:07] [PASSED] 0xE211 (BATTLEMAGE)
[07:12:07] [PASSED] 0xE212 (BATTLEMAGE)
[07:12:07] [PASSED] 0xE216 (BATTLEMAGE)
[07:12:07] [PASSED] 0xE220 (BATTLEMAGE)
[07:12:07] [PASSED] 0xE221 (BATTLEMAGE)
[07:12:07] [PASSED] 0xE222 (BATTLEMAGE)
[07:12:07] [PASSED] 0xE223 (BATTLEMAGE)
[07:12:07] [PASSED] 0xB080 (PANTHERLAKE)
[07:12:07] [PASSED] 0xB081 (PANTHERLAKE)
[07:12:07] [PASSED] 0xB082 (PANTHERLAKE)
[07:12:07] [PASSED] 0xB083 (PANTHERLAKE)
[07:12:07] [PASSED] 0xB084 (PANTHERLAKE)
[07:12:07] [PASSED] 0xB085 (PANTHERLAKE)
[07:12:07] [PASSED] 0xB086 (PANTHERLAKE)
[07:12:07] [PASSED] 0xB087 (PANTHERLAKE)
[07:12:07] [PASSED] 0xB08F (PANTHERLAKE)
[07:12:07] [PASSED] 0xB090 (PANTHERLAKE)
[07:12:07] [PASSED] 0xB0A0 (PANTHERLAKE)
[07:12:07] [PASSED] 0xB0A1 (PANTHERLAKE)
[07:12:07] [PASSED] 0xB0B0 (PANTHERLAKE)
[07:12:07] [PASSED] 0xFD80 (PANTHERLAKE)
[07:12:07] [PASSED] 0xFD81 (PANTHERLAKE)
[07:12:07] [PASSED] 0xD740 (NOVALAKE_S)
[07:12:07] [PASSED] 0xD741 (NOVALAKE_S)
[07:12:07] [PASSED] 0xD742 (NOVALAKE_S)
[07:12:07] [PASSED] 0xD743 (NOVALAKE_S)
[07:12:07] [PASSED] 0xD745 (NOVALAKE_S)
[07:12:07] [PASSED] 0xD74A (NOVALAKE_S)
[07:12:07] [PASSED] 0xD74B (NOVALAKE_S)
[07:12:07] [PASSED] 0x674C (CRESCENTISLAND)
[07:12:07] [PASSED] 0x674D (CRESCENTISLAND)
[07:12:07] [PASSED] 0x674E (CRESCENTISLAND)
[07:12:07] [PASSED] 0x674F (CRESCENTISLAND)
[07:12:07] [PASSED] 0x6750 (CRESCENTISLAND)
[07:12:07] [PASSED] 0x6751 (CRESCENTISLAND)
[07:12:07] [PASSED] 0x6752 (CRESCENTISLAND)
[07:12:07] [PASSED] 0xD750 (NOVALAKE_P)
[07:12:07] [PASSED] 0xD751 (NOVALAKE_P)
[07:12:07] [PASSED] 0xD752 (NOVALAKE_P)
[07:12:07] [PASSED] 0xD753 (NOVALAKE_P)
[07:12:07] [PASSED] 0xD754 (NOVALAKE_P)
[07:12:07] [PASSED] 0xD755 (NOVALAKE_P)
[07:12:07] [PASSED] 0xD756 (NOVALAKE_P)
[07:12:07] [PASSED] 0xD757 (NOVALAKE_P)
[07:12:07] [PASSED] 0xD75F (NOVALAKE_P)
[07:12:07] =============== [PASSED] check_platform_desc ===============
[07:12:07] ===================== [PASSED] xe_pci ======================
[07:12:07] ============= xe_rtp_tables_test (5 subtests) ==============
[07:12:07] ================== xe_rtp_table_gt_test  ===================
[07:12:07] [PASSED] gt_was/14011060649
[07:12:07] [PASSED] gt_was/14011059788
[07:12:07] [PASSED] gt_was/14015795083
[07:12:07] [PASSED] gt_was/16021867713
[07:12:07] [PASSED] gt_was/14019449301
[07:12:07] [PASSED] gt_was/16028005424
[07:12:07] [PASSED] gt_was/14026578760
[07:12:07] [PASSED] gt_was/1409420604
[07:12:07] [PASSED] gt_was/1408615072
[07:12:07] [PASSED] gt_was/22010523718
[07:12:07] [PASSED] gt_was/14011006942
[07:12:07] [PASSED] gt_was/14014830051
[07:12:07] [PASSED] gt_was/18018781329
[07:12:07] [PASSED] gt_was/1509235366
[07:12:07] [PASSED] gt_was/18018781329
[07:12:07] [PASSED] gt_was/16016694945
[07:12:07] [PASSED] gt_was/14018575942
[07:12:07] [PASSED] gt_was/22016670082
[07:12:07] [PASSED] gt_was/22016670082
[07:12:07] [PASSED] gt_was/14017421178
[07:12:07] [PASSED] gt_was/16025250150
[07:12:07] [PASSED] gt_was/14021871409
[07:12:07] [PASSED] gt_was/16021865536
[07:12:07] [PASSED] gt_was/14021486841
[07:12:07] [PASSED] gt_was/14025160223
[07:12:07] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[07:12:07] [PASSED] gt_was/14025635424
[07:12:07] [PASSED] gt_was/16028005424
[07:12:07] ============== [PASSED] xe_rtp_table_gt_test ===============
[07:12:07] ================== xe_rtp_table_gt_test  ===================
[07:12:07] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[07:12:07] [PASSED] gt_tunings/Tuning: 32B Access Enable
[07:12:07] [PASSED] gt_tunings/Tuning: L3 cache
[07:12:07] [PASSED] gt_tunings/Tuning: L3 cache - media
[07:12:07] [PASSED] gt_tunings/Tuning: Compression Overfetch
[07:12:07] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[07:12:07] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[07:12:07] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[07:12:07] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[07:12:07] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[07:12:07] [PASSED] gt_tunings/Tuning: Stateless compression control
[07:12:07] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[07:12:07] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[07:12:07] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[07:12:07] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[07:12:07] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[07:12:07] ============== [PASSED] xe_rtp_table_gt_test ===============
[07:12:07] ================== xe_rtp_table_oob_test  ==================
[07:12:07] [PASSED] oob_was/1607983814
[07:12:07] [PASSED] oob_was/16010904313
[07:12:07] [PASSED] oob_was/18022495364
[07:12:07] [PASSED] oob_was/22012773006
[07:12:07] [PASSED] oob_was/14014475959
[07:12:07] [PASSED] oob_was/22011391025
[07:12:07] [PASSED] oob_was/22012727170
[07:12:07] [PASSED] oob_was/22012727685
[07:12:07] [PASSED] oob_was/22016596838
[07:12:07] [PASSED] oob_was/18020744125
[07:12:07] [PASSED] oob_was/1409600907
[07:12:07] [PASSED] oob_was/22014953428
[07:12:07] [PASSED] oob_was/16017236439
[07:12:07] [PASSED] oob_was/14019821291
[07:12:07] [PASSED] oob_was/14015076503
[07:12:07] [PASSED] oob_was/22016122933
[07:12:07] [PASSED] oob_was/14018913170
[07:12:07] [PASSED] oob_was/14018094691
[07:12:07] [PASSED] oob_was/18024947630
[07:12:07] [PASSED] oob_was/16022287689
[07:12:07] [PASSED] oob_was/13011645652
[07:12:07] [PASSED] oob_was/14022293748
[07:12:07] [PASSED] oob_was/22019794406
[07:12:07] [PASSED] oob_was/22019338487
[07:12:07] [PASSED] oob_was/16023588340
[07:12:07] [PASSED] oob_was/14019789679
[07:12:07] [PASSED] oob_was/14022866841
[07:12:07] [PASSED] oob_was/16021333562
[07:12:07] [PASSED] oob_was/14016712196
[07:12:07] [PASSED] oob_was/14015568240
[07:12:07] [PASSED] oob_was/18013179988
[07:12:07] [PASSED] oob_was/1508761755
[07:12:07] [PASSED] oob_was/16023105232
[07:12:07] [PASSED] oob_was/16026508708
[07:12:07] [PASSED] oob_was/14020001231
[07:12:07] [PASSED] oob_was/16023683509
[07:12:07] [PASSED] oob_was/14025515070
[07:12:07] [PASSED] oob_was/15015404425_disable
[07:12:07] [PASSED] oob_was/16026007364
[07:12:07] [PASSED] oob_was/14020316580
[07:12:07] [PASSED] oob_was/14025883347
[07:12:07] [PASSED] oob_was/16029380221
[07:12:07] [PASSED] oob_was/22022079272
[07:12:07] [PASSED] oob_was/16029897822
[07:12:07] [PASSED] oob_was/14026539277
[07:12:07] [PASSED] oob_was/14027054324
[07:12:07] [PASSED] oob_was/14025941587
[07:12:07] [PASSED] oob_was/16030224309
[07:12:07] [PASSED] oob_was/14028709524
[07:12:07] ============== [PASSED] xe_rtp_table_oob_test ==============
[07:12:07] ================ xe_rtp_table_dev_oob_test  ================
[07:12:07] [PASSED] device_oob_was/22010954014
[07:12:07] [PASSED] device_oob_was/15015404425
[07:12:07] [PASSED] device_oob_was/22019338487_display
[07:12:07] [PASSED] device_oob_was/14022085890
[07:12:07] [PASSED] device_oob_was/14026633728
[07:12:07] [PASSED] device_oob_was/14026746987
[07:12:07] [PASSED] device_oob_was/14026779378
[07:12:07] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[07:12:07] ========== xe_rtp_table_missing_upper_bound_test  ==========
[07:12:07] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[07:12:07] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[07:12:07] [PASSED] register_whitelist/1806527549
[07:12:07] [PASSED] register_whitelist/allow_read_ctx_timestamp
[07:12:07] [PASSED] register_whitelist/allow_read_queue_timestamp
[07:12:07] [PASSED] register_whitelist/16014440446
[07:12:07] [PASSED] register_whitelist/16017236439
[07:12:07] [PASSED] register_whitelist/16020183090
[07:12:07] [PASSED] register_whitelist/14024997852
[07:12:07] [PASSED] register_whitelist/14024997852
[07:12:07] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[07:12:07] =============== [PASSED] xe_rtp_tables_test ================
[07:12:07] =================== xe_rtp (3 subtests) ====================
[07:12:07] =================== xe_rtp_rules_tests  ====================
[07:12:07] [PASSED] no
[07:12:07] [PASSED] yes
[07:12:07] [PASSED] no-and-no
[07:12:07] [PASSED] no-and-yes
[07:12:07] [PASSED] yes-and-no
[07:12:07] [PASSED] yes-and-yes
[07:12:07] [PASSED] no-or-no
[07:12:07] [PASSED] no-or-yes
[07:12:07] [PASSED] yes-or-no
[07:12:07] [PASSED] yes-or-yes
[07:12:07] [PASSED] no-yes-or-yes-no
[07:12:07] [PASSED] no-yes-or-yes-yes
[07:12:07] [PASSED] yes-yes-or-no-yes
[07:12:07] [PASSED] yes-yes-or-yes-yes
[07:12:07] [PASSED] no-no-or-yes-or-no
[07:12:07] [PASSED] or
[07:12:07] [PASSED] or-yes
[07:12:07] [PASSED] or-no
[07:12:07] [PASSED] yes-or
[07:12:07] [PASSED] no-or
[07:12:07] [PASSED] no-or-or-yes
[07:12:07] [PASSED] yes-or-or-no
[07:12:07] [PASSED] no-or-or-no
[07:12:07] [PASSED] missing-context-engine-class
[07:12:07] [PASSED] missing-context-engine-class-or-yes
[07:12:07] [PASSED] missing-context-engine-class-or-or-yes
[07:12:07] =============== [PASSED] xe_rtp_rules_tests ================
[07:12:07] =============== xe_rtp_process_to_sr_tests  ================
[07:12:07] [PASSED] coalesce-same-reg
[07:12:07] [PASSED] coalesce-same-reg-literal-and-func
[07:12:07] [PASSED] no-match-no-add
[07:12:07] [PASSED] two-regs-two-entries
[07:12:07] [PASSED] clr-one-set-other
[07:12:07] [PASSED] set-field
[07:12:07] [PASSED] conflict-duplicate
[07:12:07] [PASSED] conflict-not-disjoint
[07:12:07] [PASSED] conflict-not-disjoint-literal-and-func
[07:12:07] [PASSED] conflict-reg-type
[07:12:07] [PASSED] bad-mcr-reg-forced-to-regular
[07:12:07] [PASSED] bad-regular-reg-forced-to-mcr
[07:12:07] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[07:12:07] ================== xe_rtp_process_tests  ===================
[07:12:07] [PASSED] active1
[07:12:07] [PASSED] active2
[07:12:07] [PASSED] active-inactive
[07:12:07] [PASSED] inactive-active
[07:12:07] [PASSED] inactive-active-inactive
[07:12:07] [PASSED] inactive-inactive-inactive
[07:12:07] ============== [PASSED] xe_rtp_process_tests ===============
[07:12:07] ===================== [PASSED] xe_rtp ======================
[07:12:07] ==================== xe_wa (1 subtest) =====================
[07:12:07] ======================== xe_wa_gt  =========================
[07:12:07] [PASSED] TIGERLAKE B0
[07:12:07] [PASSED] DG1 A0
[07:12:07] [PASSED] DG1 B0
[07:12:07] [PASSED] ALDERLAKE_S A0
[07:12:07] [PASSED] ALDERLAKE_S B0
[07:12:07] [PASSED] ALDERLAKE_S C0
[07:12:07] [PASSED] ALDERLAKE_S D0
[07:12:07] [PASSED] ALDERLAKE_P A0
[07:12:07] [PASSED] ALDERLAKE_P B0
[07:12:07] [PASSED] ALDERLAKE_P C0
[07:12:07] [PASSED] ALDERLAKE_S RPLS D0
[07:12:07] [PASSED] ALDERLAKE_P RPLU E0
[07:12:07] [PASSED] DG2 G10 C0
[07:12:07] [PASSED] DG2 G11 B1
[07:12:07] [PASSED] DG2 G12 A1
[07:12:07] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:12:07] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:12:07] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[07:12:07] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[07:12:07] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[07:12:07] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[07:12:07] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[07:12:07] ==================== [PASSED] xe_wa_gt =====================
[07:12:07] ====================== [PASSED] xe_wa ======================
[07:12:07] ============================================================
[07:12:07] Testing complete. Ran 840 tests: passed: 811, skipped: 29
[07:12:07] Elapsed time: 40.900s total, 2.452s configuring, 37.731s building, 0.703s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[07:12:07] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:12:10] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:12:35] Starting KUnit Kernel (1/1)...
[07:12:35] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:12:35] ============ drm_test_pick_cmdline (2 subtests) ============
[07:12:35] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[07:12:35] =============== drm_test_pick_cmdline_named  ===============
[07:12:35] [PASSED] NTSC
[07:12:35] [PASSED] NTSC-J
[07:12:35] [PASSED] PAL
[07:12:35] [PASSED] PAL-M
[07:12:35] =========== [PASSED] drm_test_pick_cmdline_named ===========
[07:12:35] ============== [PASSED] drm_test_pick_cmdline ==============
[07:12:35] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[07:12:35] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[07:12:35] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[07:12:35] =========== drm_validate_clone_mode (2 subtests) ===========
[07:12:35] ============== drm_test_check_in_clone_mode  ===============
[07:12:35] [PASSED] in_clone_mode
[07:12:35] [PASSED] not_in_clone_mode
[07:12:35] ========== [PASSED] drm_test_check_in_clone_mode ===========
[07:12:35] =============== drm_test_check_valid_clones  ===============
[07:12:35] [PASSED] not_in_clone_mode
[07:12:35] [PASSED] valid_clone
[07:12:35] [PASSED] invalid_clone
[07:12:35] =========== [PASSED] drm_test_check_valid_clones ===========
[07:12:35] ============= [PASSED] drm_validate_clone_mode =============
[07:12:35] ============= drm_validate_modeset (1 subtest) =============
[07:12:35] [PASSED] drm_test_check_connector_changed_modeset
[07:12:35] ============== [PASSED] drm_validate_modeset ===============
[07:12:35] ====== drm_test_bridge_get_current_state (1 subtest) =======
[07:12:35] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[07:12:35] ======== [PASSED] drm_test_bridge_get_current_state ========
[07:12:35] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[07:12:35] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[07:12:35] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[07:12:35] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[07:12:35] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[07:12:35] ============== drm_bridge_alloc (2 subtests) ===============
[07:12:35] [PASSED] drm_test_drm_bridge_alloc_basic
[07:12:35] [PASSED] drm_test_drm_bridge_alloc_get_put
[07:12:35] ================ [PASSED] drm_bridge_alloc =================
[07:12:35] ============= drm_bridge_bus_fmt (5 subtests) ==============
[07:12:35] [PASSED] drm_test_bridge_rgb_yuv_rgb
[07:12:35] [PASSED] drm_test_bridge_must_convert_to_yuv444
[07:12:35] [PASSED] drm_test_bridge_hdmi_auto_rgb
[07:12:35] [PASSED] drm_test_bridge_auto_first
[07:12:35] [PASSED] drm_test_bridge_rgb_yuv_no_path
[07:12:35] =============== [PASSED] drm_bridge_bus_fmt ================
[07:12:35] ============= drm_cmdline_parser (40 subtests) =============
[07:12:35] [PASSED] drm_test_cmdline_force_d_only
[07:12:35] [PASSED] drm_test_cmdline_force_D_only_dvi
[07:12:35] [PASSED] drm_test_cmdline_force_D_only_hdmi
[07:12:35] [PASSED] drm_test_cmdline_force_D_only_not_digital
[07:12:35] [PASSED] drm_test_cmdline_force_e_only
[07:12:35] [PASSED] drm_test_cmdline_res
[07:12:35] [PASSED] drm_test_cmdline_res_vesa
[07:12:35] [PASSED] drm_test_cmdline_res_vesa_rblank
[07:12:35] [PASSED] drm_test_cmdline_res_rblank
[07:12:35] [PASSED] drm_test_cmdline_res_bpp
[07:12:35] [PASSED] drm_test_cmdline_res_refresh
[07:12:35] [PASSED] drm_test_cmdline_res_bpp_refresh
[07:12:35] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[07:12:35] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[07:12:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[07:12:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[07:12:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[07:12:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[07:12:35] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[07:12:35] [PASSED] drm_test_cmdline_res_margins_force_on
[07:12:35] [PASSED] drm_test_cmdline_res_vesa_margins
[07:12:35] [PASSED] drm_test_cmdline_name
[07:12:35] [PASSED] drm_test_cmdline_name_bpp
[07:12:35] [PASSED] drm_test_cmdline_name_option
[07:12:35] [PASSED] drm_test_cmdline_name_bpp_option
[07:12:35] [PASSED] drm_test_cmdline_rotate_0
[07:12:35] [PASSED] drm_test_cmdline_rotate_90
[07:12:35] [PASSED] drm_test_cmdline_rotate_180
[07:12:35] [PASSED] drm_test_cmdline_rotate_270
[07:12:35] [PASSED] drm_test_cmdline_hmirror
[07:12:35] [PASSED] drm_test_cmdline_vmirror
[07:12:35] [PASSED] drm_test_cmdline_margin_options
[07:12:35] [PASSED] drm_test_cmdline_multiple_options
[07:12:35] [PASSED] drm_test_cmdline_bpp_extra_and_option
[07:12:35] [PASSED] drm_test_cmdline_extra_and_option
[07:12:35] [PASSED] drm_test_cmdline_freestanding_options
[07:12:35] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[07:12:35] [PASSED] drm_test_cmdline_panel_orientation
[07:12:35] ================ drm_test_cmdline_invalid  =================
[07:12:35] [PASSED] margin_only
[07:12:35] [PASSED] interlace_only
[07:12:35] [PASSED] res_missing_x
[07:12:35] [PASSED] res_missing_y
[07:12:35] [PASSED] res_bad_y
[07:12:35] [PASSED] res_missing_y_bpp
[07:12:35] [PASSED] res_bad_bpp
[07:12:35] [PASSED] res_bad_refresh
[07:12:35] [PASSED] res_bpp_refresh_force_on_off
[07:12:35] [PASSED] res_invalid_mode
[07:12:35] [PASSED] res_bpp_wrong_place_mode
[07:12:35] [PASSED] name_bpp_refresh
[07:12:35] [PASSED] name_refresh
[07:12:35] [PASSED] name_refresh_wrong_mode
[07:12:35] [PASSED] name_refresh_invalid_mode
[07:12:35] [PASSED] rotate_multiple
[07:12:35] [PASSED] rotate_invalid_val
[07:12:35] [PASSED] rotate_truncated
[07:12:35] [PASSED] invalid_option
[07:12:35] [PASSED] invalid_tv_option
[07:12:35] [PASSED] truncated_tv_option
[07:12:35] ============ [PASSED] drm_test_cmdline_invalid =============
[07:12:35] =============== drm_test_cmdline_tv_options  ===============
[07:12:35] [PASSED] NTSC
[07:12:35] [PASSED] NTSC_443
[07:12:35] [PASSED] NTSC_J
[07:12:35] [PASSED] PAL
[07:12:35] [PASSED] PAL_M
[07:12:35] [PASSED] PAL_N
[07:12:35] [PASSED] SECAM
[07:12:35] [PASSED] MONO_525
[07:12:35] [PASSED] MONO_625
[07:12:35] =========== [PASSED] drm_test_cmdline_tv_options ===========
[07:12:35] =============== [PASSED] drm_cmdline_parser ================
[07:12:35] ========== drmm_connector_hdmi_init (20 subtests) ==========
[07:12:35] [PASSED] drm_test_connector_hdmi_init_valid
[07:12:35] [PASSED] drm_test_connector_hdmi_init_bpc_8
[07:12:35] [PASSED] drm_test_connector_hdmi_init_bpc_10
[07:12:35] [PASSED] drm_test_connector_hdmi_init_bpc_12
[07:12:35] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[07:12:35] [PASSED] drm_test_connector_hdmi_init_bpc_null
[07:12:35] [PASSED] drm_test_connector_hdmi_init_formats_empty
[07:12:35] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[07:12:35] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[07:12:35] [PASSED] supported_formats=0x9 yuv420_allowed=1
[07:12:35] [PASSED] supported_formats=0x9 yuv420_allowed=0
[07:12:35] [PASSED] supported_formats=0x5 yuv420_allowed=1
[07:12:35] [PASSED] supported_formats=0x5 yuv420_allowed=0
[07:12:35] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[07:12:35] [PASSED] drm_test_connector_hdmi_init_null_ddc
[07:12:35] [PASSED] drm_test_connector_hdmi_init_null_product
[07:12:35] [PASSED] drm_test_connector_hdmi_init_null_vendor
[07:12:35] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[07:12:35] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[07:12:35] [PASSED] drm_test_connector_hdmi_init_product_valid
[07:12:35] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[07:12:35] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[07:12:35] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[07:12:35] ========= drm_test_connector_hdmi_init_type_valid  =========
[07:12:35] [PASSED] HDMI-A
[07:12:35] [PASSED] HDMI-B
[07:12:35] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[07:12:35] ======== drm_test_connector_hdmi_init_type_invalid  ========
[07:12:35] [PASSED] Unknown
[07:12:35] [PASSED] VGA
[07:12:35] [PASSED] DVI-I
[07:12:35] [PASSED] DVI-D
[07:12:35] [PASSED] DVI-A
[07:12:35] [PASSED] Composite
[07:12:35] [PASSED] SVIDEO
[07:12:35] [PASSED] LVDS
[07:12:35] [PASSED] Component
[07:12:35] [PASSED] DIN
[07:12:35] [PASSED] DP
[07:12:35] [PASSED] TV
[07:12:35] [PASSED] eDP
[07:12:35] [PASSED] Virtual
[07:12:35] [PASSED] DSI
[07:12:35] [PASSED] DPI
[07:12:35] [PASSED] Writeback
[07:12:35] [PASSED] SPI
[07:12:35] [PASSED] USB
[07:12:35] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[07:12:35] ============ [PASSED] drmm_connector_hdmi_init =============
[07:12:35] ============= drmm_connector_init (3 subtests) =============
[07:12:35] [PASSED] drm_test_drmm_connector_init
[07:12:35] [PASSED] drm_test_drmm_connector_init_null_ddc
[07:12:35] ========= drm_test_drmm_connector_init_type_valid  =========
[07:12:35] [PASSED] Unknown
[07:12:35] [PASSED] VGA
[07:12:35] [PASSED] DVI-I
[07:12:35] [PASSED] DVI-D
[07:12:35] [PASSED] DVI-A
[07:12:35] [PASSED] Composite
[07:12:35] [PASSED] SVIDEO
[07:12:35] [PASSED] LVDS
[07:12:35] [PASSED] Component
[07:12:35] [PASSED] DIN
[07:12:35] [PASSED] DP
[07:12:35] [PASSED] HDMI-A
[07:12:35] [PASSED] HDMI-B
[07:12:35] [PASSED] TV
[07:12:35] [PASSED] eDP
[07:12:35] [PASSED] Virtual
[07:12:35] [PASSED] DSI
[07:12:35] [PASSED] DPI
[07:12:35] [PASSED] Writeback
[07:12:35] [PASSED] SPI
[07:12:35] [PASSED] USB
[07:12:35] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[07:12:35] =============== [PASSED] drmm_connector_init ===============
[07:12:35] ========= drm_connector_dynamic_init (6 subtests) ==========
[07:12:35] [PASSED] drm_test_drm_connector_dynamic_init
[07:12:35] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[07:12:35] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[07:12:35] [PASSED] drm_test_drm_connector_dynamic_init_properties
[07:12:35] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[07:12:35] [PASSED] Unknown
[07:12:35] [PASSED] VGA
[07:12:35] [PASSED] DVI-I
[07:12:35] [PASSED] DVI-D
[07:12:35] [PASSED] DVI-A
[07:12:35] [PASSED] Composite
[07:12:35] [PASSED] SVIDEO
[07:12:35] [PASSED] LVDS
[07:12:35] [PASSED] Component
[07:12:35] [PASSED] DIN
[07:12:35] [PASSED] DP
[07:12:35] [PASSED] HDMI-A
[07:12:35] [PASSED] HDMI-B
[07:12:35] [PASSED] TV
[07:12:35] [PASSED] eDP
[07:12:35] [PASSED] Virtual
[07:12:35] [PASSED] DSI
[07:12:35] [PASSED] DPI
[07:12:35] [PASSED] Writeback
[07:12:35] [PASSED] SPI
[07:12:35] [PASSED] USB
[07:12:35] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[07:12:35] ======== drm_test_drm_connector_dynamic_init_name  =========
[07:12:35] [PASSED] Unknown
[07:12:35] [PASSED] VGA
[07:12:35] [PASSED] DVI-I
[07:12:35] [PASSED] DVI-D
[07:12:35] [PASSED] DVI-A
[07:12:35] [PASSED] Composite
[07:12:35] [PASSED] SVIDEO
[07:12:35] [PASSED] LVDS
[07:12:35] [PASSED] Component
[07:12:35] [PASSED] DIN
[07:12:35] [PASSED] DP
[07:12:35] [PASSED] HDMI-A
[07:12:35] [PASSED] HDMI-B
[07:12:35] [PASSED] TV
[07:12:35] [PASSED] eDP
[07:12:35] [PASSED] Virtual
[07:12:35] [PASSED] DSI
[07:12:35] [PASSED] DPI
[07:12:35] [PASSED] Writeback
[07:12:35] [PASSED] SPI
[07:12:35] [PASSED] USB
[07:12:35] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[07:12:35] =========== [PASSED] drm_connector_dynamic_init ============
[07:12:35] ==== drm_connector_dynamic_register_early (4 subtests) =====
[07:12:35] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[07:12:35] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[07:12:35] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[07:12:35] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[07:12:35] ====== [PASSED] drm_connector_dynamic_register_early =======
[07:12:35] ======= drm_connector_dynamic_register (7 subtests) ========
[07:12:35] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[07:12:35] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[07:12:35] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[07:12:35] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[07:12:35] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[07:12:35] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[07:12:35] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[07:12:35] ========= [PASSED] drm_connector_dynamic_register ==========
[07:12:35] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[07:12:35] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[07:12:35] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[07:12:35] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[07:12:35] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[07:12:35] ========== drm_test_get_tv_mode_from_name_valid  ===========
[07:12:35] [PASSED] NTSC
[07:12:35] [PASSED] NTSC-443
[07:12:35] [PASSED] NTSC-J
[07:12:35] [PASSED] PAL
[07:12:35] [PASSED] PAL-M
[07:12:35] [PASSED] PAL-N
[07:12:35] [PASSED] SECAM
[07:12:35] [PASSED] Mono
[07:12:35] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[07:12:35] [PASSED] drm_test_get_tv_mode_from_name_truncated
[07:12:35] ============ [PASSED] drm_get_tv_mode_from_name ============
[07:12:35] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[07:12:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[07:12:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[07:12:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[07:12:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[07:12:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[07:12:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[07:12:35] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[07:12:35] [PASSED] VIC 96
[07:12:35] [PASSED] VIC 97
[07:12:35] [PASSED] VIC 101
[07:12:35] [PASSED] VIC 102
[07:12:35] [PASSED] VIC 106
[07:12:35] [PASSED] VIC 107
[07:12:35] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[07:12:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[07:12:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[07:12:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[07:12:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[07:12:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[07:12:35] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[07:12:35] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[07:12:35] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[07:12:35] [PASSED] Automatic
[07:12:35] [PASSED] Full
[07:12:35] [PASSED] Limited 16:235
[07:12:35] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[07:12:35] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[07:12:35] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[07:12:35] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[07:12:35] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[07:12:35] [PASSED] RGB
[07:12:35] [PASSED] YUV 4:2:0
[07:12:35] [PASSED] YUV 4:2:2
[07:12:35] [PASSED] YUV 4:4:4
[07:12:35] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[07:12:35] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[07:12:35] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[07:12:35] ============= drm_damage_helper (21 subtests) ==============
[07:12:35] [PASSED] drm_test_damage_iter_no_damage
[07:12:35] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[07:12:35] [PASSED] drm_test_damage_iter_no_damage_src_moved
[07:12:35] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[07:12:35] [PASSED] drm_test_damage_iter_no_damage_not_visible
[07:12:35] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[07:12:35] [PASSED] drm_test_damage_iter_no_damage_no_fb
[07:12:35] [PASSED] drm_test_damage_iter_simple_damage
[07:12:35] [PASSED] drm_test_damage_iter_single_damage
[07:12:35] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[07:12:35] [PASSED] drm_test_damage_iter_single_damage_outside_src
[07:12:35] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[07:12:35] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[07:12:35] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[07:12:35] [PASSED] drm_test_damage_iter_single_damage_src_moved
[07:12:35] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[07:12:35] [PASSED] drm_test_damage_iter_damage
[07:12:35] [PASSED] drm_test_damage_iter_damage_one_intersect
[07:12:35] [PASSED] drm_test_damage_iter_damage_one_outside
[07:12:35] [PASSED] drm_test_damage_iter_damage_src_moved
[07:12:35] [PASSED] drm_test_damage_iter_damage_not_visible
[07:12:35] ================ [PASSED] drm_damage_helper ================
[07:12:35] ============== drm_dp_mst_helper (3 subtests) ==============
[07:12:35] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[07:12:35] [PASSED] Clock 154000 BPP 30 DSC disabled
[07:12:35] [PASSED] Clock 234000 BPP 30 DSC disabled
[07:12:35] [PASSED] Clock 297000 BPP 24 DSC disabled
[07:12:35] [PASSED] Clock 332880 BPP 24 DSC enabled
[07:12:35] [PASSED] Clock 324540 BPP 24 DSC enabled
[07:12:35] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[07:12:35] ============== drm_test_dp_mst_calc_pbn_div  ===============
[07:12:35] [PASSED] Link rate 2000000 lane count 4
[07:12:35] [PASSED] Link rate 2000000 lane count 2
[07:12:35] [PASSED] Link rate 2000000 lane count 1
[07:12:35] [PASSED] Link rate 1350000 lane count 4
[07:12:35] [PASSED] Link rate 1350000 lane count 2
[07:12:35] [PASSED] Link rate 1350000 lane count 1
[07:12:35] [PASSED] Link rate 1000000 lane count 4
[07:12:35] [PASSED] Link rate 1000000 lane count 2
[07:12:35] [PASSED] Link rate 1000000 lane count 1
[07:12:35] [PASSED] Link rate 810000 lane count 4
[07:12:35] [PASSED] Link rate 810000 lane count 2
[07:12:35] [PASSED] Link rate 810000 lane count 1
[07:12:35] [PASSED] Link rate 540000 lane count 4
[07:12:35] [PASSED] Link rate 540000 lane count 2
[07:12:35] [PASSED] Link rate 540000 lane count 1
[07:12:35] [PASSED] Link rate 270000 lane count 4
[07:12:35] [PASSED] Link rate 270000 lane count 2
[07:12:35] [PASSED] Link rate 270000 lane count 1
[07:12:35] [PASSED] Link rate 162000 lane count 4
[07:12:35] [PASSED] Link rate 162000 lane count 2
[07:12:35] [PASSED] Link rate 162000 lane count 1
[07:12:35] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[07:12:35] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[07:12:35] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[07:12:35] [PASSED] DP_POWER_UP_PHY with port number
[07:12:35] [PASSED] DP_POWER_DOWN_PHY with port number
[07:12:35] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[07:12:35] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[07:12:35] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[07:12:35] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[07:12:35] [PASSED] DP_QUERY_PAYLOAD with port number
[07:12:35] [PASSED] DP_QUERY_PAYLOAD with VCPI
[07:12:35] [PASSED] DP_REMOTE_DPCD_READ with port number
[07:12:35] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[07:12:35] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[07:12:35] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[07:12:35] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[07:12:35] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[07:12:35] [PASSED] DP_REMOTE_I2C_READ with port number
[07:12:35] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[07:12:35] [PASSED] DP_REMOTE_I2C_READ with transactions array
[07:12:35] [PASSED] DP_REMOTE_I2C_WRITE with port number
[07:12:35] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[07:12:35] [PASSED] DP_REMOTE_I2C_WRITE with data array
[07:12:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[07:12:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[07:12:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[07:12:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[07:12:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[07:12:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[07:12:35] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[07:12:35] ================ [PASSED] drm_dp_mst_helper ================
[07:12:35] ================== drm_exec (7 subtests) ===================
[07:12:35] [PASSED] sanitycheck
[07:12:35] [PASSED] test_lock
[07:12:35] [PASSED] test_lock_unlock
[07:12:35] [PASSED] test_duplicates
[07:12:35] [PASSED] test_prepare
[07:12:35] [PASSED] test_prepare_array
[07:12:35] [PASSED] test_multiple_loops
[07:12:35] ==================== [PASSED] drm_exec =====================
[07:12:35] =========== drm_format_helper_test (17 subtests) ===========
[07:12:35] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[07:12:35] [PASSED] single_pixel_source_buffer
[07:12:35] [PASSED] single_pixel_clip_rectangle
[07:12:35] [PASSED] well_known_colors
[07:12:35] [PASSED] destination_pitch
[07:12:35] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[07:12:35] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[07:12:35] [PASSED] single_pixel_source_buffer
[07:12:35] [PASSED] single_pixel_clip_rectangle
[07:12:35] [PASSED] well_known_colors
[07:12:35] [PASSED] destination_pitch
[07:12:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[07:12:35] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[07:12:35] [PASSED] single_pixel_source_buffer
[07:12:35] [PASSED] single_pixel_clip_rectangle
[07:12:35] [PASSED] well_known_colors
[07:12:35] [PASSED] destination_pitch
[07:12:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[07:12:35] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[07:12:35] [PASSED] single_pixel_source_buffer
[07:12:35] [PASSED] single_pixel_clip_rectangle
[07:12:35] [PASSED] well_known_colors
[07:12:35] [PASSED] destination_pitch
[07:12:35] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[07:12:35] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[07:12:35] [PASSED] single_pixel_source_buffer
[07:12:35] [PASSED] single_pixel_clip_rectangle
[07:12:35] [PASSED] well_known_colors
[07:12:35] [PASSED] destination_pitch
[07:12:35] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[07:12:35] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[07:12:35] [PASSED] single_pixel_source_buffer
[07:12:35] [PASSED] single_pixel_clip_rectangle
[07:12:35] [PASSED] well_known_colors
[07:12:35] [PASSED] destination_pitch
[07:12:35] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[07:12:35] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[07:12:35] [PASSED] single_pixel_source_buffer
[07:12:35] [PASSED] single_pixel_clip_rectangle
[07:12:35] [PASSED] well_known_colors
[07:12:35] [PASSED] destination_pitch
[07:12:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[07:12:35] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[07:12:35] [PASSED] single_pixel_source_buffer
[07:12:35] [PASSED] single_pixel_clip_rectangle
[07:12:35] [PASSED] well_known_colors
[07:12:35] [PASSED] destination_pitch
[07:12:35] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[07:12:35] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[07:12:35] [PASSED] single_pixel_source_buffer
[07:12:35] [PASSED] single_pixel_clip_rectangle
[07:12:35] [PASSED] well_known_colors
[07:12:35] [PASSED] destination_pitch
[07:12:35] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[07:12:35] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[07:12:35] [PASSED] single_pixel_source_buffer
[07:12:35] [PASSED] single_pixel_clip_rectangle
[07:12:35] [PASSED] well_known_colors
[07:12:35] [PASSED] destination_pitch
[07:12:35] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[07:12:35] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[07:12:35] [PASSED] single_pixel_source_buffer
[07:12:35] [PASSED] single_pixel_clip_rectangle
[07:12:35] [PASSED] well_known_colors
[07:12:35] [PASSED] destination_pitch
[07:12:35] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[07:12:35] ============== drm_test_fb_xrgb8888_to_mono  ===============
[07:12:35] [PASSED] single_pixel_source_buffer
[07:12:35] [PASSED] single_pixel_clip_rectangle
[07:12:35] [PASSED] well_known_colors
[07:12:35] [PASSED] destination_pitch
[07:12:35] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[07:12:35] ==================== drm_test_fb_swab  =====================
[07:12:35] [PASSED] single_pixel_source_buffer
[07:12:35] [PASSED] single_pixel_clip_rectangle
[07:12:35] [PASSED] well_known_colors
[07:12:35] [PASSED] destination_pitch
[07:12:35] ================ [PASSED] drm_test_fb_swab =================
[07:12:35] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[07:12:35] [PASSED] single_pixel_source_buffer
[07:12:35] [PASSED] single_pixel_clip_rectangle
[07:12:35] [PASSED] well_known_colors
[07:12:35] [PASSED] destination_pitch
[07:12:35] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[07:12:35] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[07:12:35] [PASSED] single_pixel_source_buffer
[07:12:35] [PASSED] single_pixel_clip_rectangle
[07:12:35] [PASSED] well_known_colors
[07:12:35] [PASSED] destination_pitch
[07:12:35] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[07:12:35] ================= drm_test_fb_clip_offset  =================
[07:12:35] [PASSED] pass through
[07:12:35] [PASSED] horizontal offset
[07:12:35] [PASSED] vertical offset
[07:12:35] [PASSED] horizontal and vertical offset
[07:12:35] [PASSED] horizontal offset (custom pitch)
[07:12:35] [PASSED] vertical offset (custom pitch)
[07:12:35] [PASSED] horizontal and vertical offset (custom pitch)
[07:12:35] ============= [PASSED] drm_test_fb_clip_offset =============
[07:12:35] =================== drm_test_fb_memcpy  ====================
[07:12:35] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[07:12:35] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[07:12:35] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[07:12:35] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[07:12:35] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[07:12:35] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[07:12:35] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[07:12:35] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[07:12:35] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[07:12:35] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[07:12:35] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[07:12:35] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[07:12:35] =============== [PASSED] drm_test_fb_memcpy ================
[07:12:35] ============= [PASSED] drm_format_helper_test ==============
[07:12:35] ================= drm_format (18 subtests) =================
[07:12:35] [PASSED] drm_test_format_block_width_invalid
[07:12:35] [PASSED] drm_test_format_block_width_one_plane
[07:12:35] [PASSED] drm_test_format_block_width_two_plane
[07:12:35] [PASSED] drm_test_format_block_width_three_plane
[07:12:35] [PASSED] drm_test_format_block_width_tiled
[07:12:35] [PASSED] drm_test_format_block_height_invalid
[07:12:35] [PASSED] drm_test_format_block_height_one_plane
[07:12:35] [PASSED] drm_test_format_block_height_two_plane
[07:12:35] [PASSED] drm_test_format_block_height_three_plane
[07:12:35] [PASSED] drm_test_format_block_height_tiled
[07:12:35] [PASSED] drm_test_format_min_pitch_invalid
[07:12:35] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[07:12:35] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[07:12:35] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[07:12:35] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[07:12:35] [PASSED] drm_test_format_min_pitch_two_plane
[07:12:35] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[07:12:35] [PASSED] drm_test_format_min_pitch_tiled
[07:12:35] =================== [PASSED] drm_format ====================
[07:12:35] ============== drm_framebuffer (10 subtests) ===============
[07:12:35] ========== drm_test_framebuffer_check_src_coords  ==========
[07:12:35] [PASSED] Success: source fits into fb
[07:12:35] [PASSED] Fail: overflowing fb with x-axis coordinate
[07:12:35] [PASSED] Fail: overflowing fb with y-axis coordinate
[07:12:35] [PASSED] Fail: overflowing fb with source width
[07:12:35] [PASSED] Fail: overflowing fb with source height
[07:12:35] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[07:12:35] [PASSED] drm_test_framebuffer_cleanup
[07:12:35] =============== drm_test_framebuffer_create  ===============
[07:12:35] [PASSED] ABGR8888 normal sizes
[07:12:35] [PASSED] ABGR8888 max sizes
[07:12:35] [PASSED] ABGR8888 pitch greater than min required
[07:12:35] [PASSED] ABGR8888 pitch less than min required
[07:12:35] [PASSED] ABGR8888 Invalid width
[07:12:35] [PASSED] ABGR8888 Invalid buffer handle
[07:12:35] [PASSED] No pixel format
[07:12:35] [PASSED] ABGR8888 Width 0
[07:12:35] [PASSED] ABGR8888 Height 0
[07:12:35] [PASSED] ABGR8888 Out of bound height * pitch combination
[07:12:35] [PASSED] ABGR8888 Large buffer offset
[07:12:35] [PASSED] ABGR8888 Buffer offset for inexistent plane
[07:12:35] [PASSED] ABGR8888 Invalid flag
[07:12:35] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[07:12:35] [PASSED] ABGR8888 Valid buffer modifier
[07:12:35] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[07:12:35] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[07:12:35] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[07:12:35] [PASSED] NV12 Normal sizes
[07:12:35] [PASSED] NV12 Max sizes
[07:12:35] [PASSED] NV12 Invalid pitch
[07:12:35] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[07:12:35] [PASSED] NV12 different  modifier per-plane
[07:12:35] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[07:12:35] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[07:12:35] [PASSED] NV12 Modifier for inexistent plane
[07:12:35] [PASSED] NV12 Handle for inexistent plane
[07:12:35] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[07:12:35] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[07:12:35] [PASSED] YVU420 Normal sizes
[07:12:35] [PASSED] YVU420 Max sizes
[07:12:35] [PASSED] YVU420 Invalid pitch
[07:12:35] [PASSED] YVU420 Different pitches
[07:12:35] [PASSED] YVU420 Different buffer offsets/pitches
[07:12:35] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[07:12:35] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[07:12:35] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[07:12:35] [PASSED] YVU420 Valid modifier
[07:12:35] [PASSED] YVU420 Different modifiers per plane
[07:12:35] [PASSED] YVU420 Modifier for inexistent plane
[07:12:35] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[07:12:35] [PASSED] X0L2 Normal sizes
[07:12:35] [PASSED] X0L2 Max sizes
[07:12:35] [PASSED] X0L2 Invalid pitch
[07:12:35] [PASSED] X0L2 Pitch greater than minimum required
[07:12:35] [PASSED] X0L2 Handle for inexistent plane
[07:12:35] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[07:12:35] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[07:12:35] [PASSED] X0L2 Valid modifier
[07:12:35] [PASSED] X0L2 Modifier for inexistent plane
[07:12:35] =========== [PASSED] drm_test_framebuffer_create ===========
[07:12:35] [PASSED] drm_test_framebuffer_free
[07:12:35] [PASSED] drm_test_framebuffer_init
[07:12:35] [PASSED] drm_test_framebuffer_init_bad_format
[07:12:35] [PASSED] drm_test_framebuffer_init_dev_mismatch
[07:12:35] [PASSED] drm_test_framebuffer_lookup
[07:12:35] [PASSED] drm_test_framebuffer_lookup_inexistent
[07:12:35] [PASSED] drm_test_framebuffer_modifiers_not_supported
[07:12:35] ================= [PASSED] drm_framebuffer =================
[07:12:35] ================ drm_gem_shmem (8 subtests) ================
[07:12:35] [PASSED] drm_gem_shmem_test_obj_create
[07:12:35] [PASSED] drm_gem_shmem_test_obj_create_private
[07:12:35] [PASSED] drm_gem_shmem_test_pin_pages
[07:12:35] [PASSED] drm_gem_shmem_test_vmap
[07:12:35] [PASSED] drm_gem_shmem_test_get_sg_table
[07:12:35] [PASSED] drm_gem_shmem_test_get_pages_sgt
[07:12:35] [PASSED] drm_gem_shmem_test_madvise
[07:12:35] [PASSED] drm_gem_shmem_test_purge
[07:12:35] ================== [PASSED] drm_gem_shmem ==================
[07:12:35] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[07:12:35] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[07:12:35] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[07:12:35] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[07:12:35] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[07:12:35] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[07:12:35] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[07:12:35] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[07:12:35] [PASSED] Automatic
[07:12:35] [PASSED] Full
[07:12:35] [PASSED] Limited 16:235
[07:12:35] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[07:12:35] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[07:12:35] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[07:12:35] [PASSED] drm_test_check_disable_connector
[07:12:35] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[07:12:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[07:12:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[07:12:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[07:12:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[07:12:35] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[07:12:35] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[07:12:35] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[07:12:35] [PASSED] drm_test_check_output_bpc_dvi
[07:12:35] [PASSED] drm_test_check_output_bpc_format_vic_1
[07:12:35] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[07:12:35] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[07:12:35] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[07:12:35] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[07:12:35] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[07:12:35] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[07:12:35] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[07:12:35] ============ drm_test_check_hdmi_color_format  =============
[07:12:35] [PASSED] AUTO -> RGB
[07:12:35] [PASSED] YCBCR422 -> YUV422
[07:12:35] [PASSED] YCBCR420 -> YUV420
[07:12:35] [PASSED] YCBCR444 -> YUV444
[07:12:35] [PASSED] RGB -> RGB
[07:12:35] ======== [PASSED] drm_test_check_hdmi_color_format =========
[07:12:35] ======== drm_test_check_hdmi_color_format_420_only  ========
[07:12:35] [PASSED] RGB should fail
[07:12:35] [PASSED] YUV444 should fail
[07:12:35] [PASSED] YUV422 should fail
[07:12:35] [PASSED] YUV420 should work
[07:12:35] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[07:12:35] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[07:12:35] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[07:12:35] [PASSED] drm_test_check_broadcast_rgb_value
[07:12:35] [PASSED] drm_test_check_bpc_8_value
[07:12:35] [PASSED] drm_test_check_bpc_10_value
[07:12:35] [PASSED] drm_test_check_bpc_12_value
[07:12:35] [PASSED] drm_test_check_format_value
[07:12:35] [PASSED] drm_test_check_tmds_char_value
[07:12:35] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[07:12:35] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[07:12:35] [PASSED] drm_test_check_mode_valid
[07:12:35] [PASSED] drm_test_check_mode_valid_reject
[07:12:35] [PASSED] drm_test_check_mode_valid_reject_rate
[07:12:35] [PASSED] drm_test_check_mode_valid_reject_max_clock
[07:12:35] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[07:12:35] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[07:12:35] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[07:12:35] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[07:12:35] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[07:12:35] [PASSED] drm_test_check_infoframes
[07:12:35] [PASSED] drm_test_check_reject_avi_infoframe
[07:12:35] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[07:12:35] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[07:12:35] [PASSED] drm_test_check_reject_audio_infoframe
[07:12:35] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[07:12:35] ================= drm_managed (2 subtests) =================
[07:12:35] [PASSED] drm_test_managed_release_action
[07:12:35] [PASSED] drm_test_managed_run_action
[07:12:35] =================== [PASSED] drm_managed ===================
[07:12:35] =================== drm_mm (6 subtests) ====================
[07:12:35] [PASSED] drm_test_mm_init
[07:12:35] [PASSED] drm_test_mm_debug
[07:12:35] [PASSED] drm_test_mm_align32
[07:12:35] [PASSED] drm_test_mm_align64
[07:12:35] [PASSED] drm_test_mm_lowest
[07:12:35] [PASSED] drm_test_mm_highest
[07:12:35] ===================== [PASSED] drm_mm ======================
[07:12:35] ============= drm_modes_analog_tv (5 subtests) =============
[07:12:35] [PASSED] drm_test_modes_analog_tv_mono_576i
[07:12:35] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[07:12:35] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[07:12:35] [PASSED] drm_test_modes_analog_tv_pal_576i
[07:12:35] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[07:12:35] =============== [PASSED] drm_modes_analog_tv ===============
[07:12:35] ============== drm_panic_helper (3 subtests) ===============
[07:12:35] ============= drm_test_panic_screen_user_map  ==============
[07:12:35] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[07:12:35] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[07:12:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[07:12:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[07:12:35] ========= [PASSED] drm_test_panic_screen_user_map ==========
[07:12:35] ============= drm_test_panic_screen_user_page  =============
[07:12:35] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[07:12:35] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[07:12:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[07:12:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[07:12:35] ========= [PASSED] drm_test_panic_screen_user_page =========
[07:12:35] ========== drm_test_panic_screen_user_set_pixel  ===========
[07:12:35] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[07:12:35] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[07:12:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[07:12:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[07:12:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[07:12:35] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[07:12:35] ================ [PASSED] drm_panic_helper =================
[07:12:35] ============== drm_plane_helper (2 subtests) ===============
[07:12:35] =============== drm_test_check_plane_state  ================
[07:12:35] [PASSED] clipping_simple
[07:12:35] [PASSED] clipping_rotate_reflect
[07:12:35] [PASSED] positioning_simple
[07:12:35] [PASSED] upscaling
[07:12:35] [PASSED] downscaling
[07:12:35] [PASSED] rounding1
[07:12:35] [PASSED] rounding2
[07:12:35] [PASSED] rounding3
[07:12:35] [PASSED] rounding4
[07:12:35] =========== [PASSED] drm_test_check_plane_state ============
[07:12:35] =========== drm_test_check_invalid_plane_state  ============
[07:12:35] [PASSED] positioning_invalid
[07:12:35] [PASSED] upscaling_invalid
[07:12:35] [PASSED] downscaling_invalid
[07:12:35] ======= [PASSED] drm_test_check_invalid_plane_state ========
[07:12:35] ================ [PASSED] drm_plane_helper =================
[07:12:35] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[07:12:35] ====== drm_test_connector_helper_tv_get_modes_check  =======
[07:12:35] [PASSED] None
[07:12:35] [PASSED] PAL
[07:12:35] [PASSED] NTSC
[07:12:35] [PASSED] Both, NTSC Default
[07:12:35] [PASSED] Both, PAL Default
[07:12:35] [PASSED] Both, NTSC Default, with PAL on command-line
[07:12:35] [PASSED] Both, PAL Default, with NTSC on command-line
[07:12:35] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[07:12:35] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[07:12:35] ================== drm_rect (9 subtests) ===================
[07:12:35] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[07:12:35] [PASSED] drm_test_rect_clip_scaled_not_clipped
[07:12:35] [PASSED] drm_test_rect_clip_scaled_clipped
[07:12:35] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[07:12:35] ================= drm_test_rect_intersect  =================
[07:12:35] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[07:12:35] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[07:12:35] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[07:12:35] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[07:12:35] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[07:12:35] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[07:12:35] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[07:12:35] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[07:12:35] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[07:12:35] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[07:12:35] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[07:12:35] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[07:12:35] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[07:12:35] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[07:12:35] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[07:12:35] ============= [PASSED] drm_test_rect_intersect =============
[07:12:35] ================ drm_test_rect_calc_hscale  ================
[07:12:35] [PASSED] normal use
[07:12:35] [PASSED] out of max range
[07:12:35] [PASSED] out of min range
[07:12:35] [PASSED] zero dst
[07:12:35] [PASSED] negative src
[07:12:35] [PASSED] negative dst
[07:12:35] ============ [PASSED] drm_test_rect_calc_hscale ============
[07:12:35] ================ drm_test_rect_calc_vscale  ================
[07:12:35] [PASSED] normal use
[07:12:35] [PASSED] out of max range
[07:12:35] [PASSED] out of min range
[07:12:35] [PASSED] zero dst
[07:12:35] [PASSED] negative src
[07:12:35] [PASSED] negative dst
[07:12:35] ============ [PASSED] drm_test_rect_calc_vscale ============
[07:12:35] ================== drm_test_rect_rotate  ===================
[07:12:35] [PASSED] reflect-x
[07:12:35] [PASSED] reflect-y
[07:12:35] [PASSED] rotate-0
[07:12:35] [PASSED] rotate-90
[07:12:35] [PASSED] rotate-180
[07:12:35] [PASSED] rotate-270
[07:12:35] ============== [PASSED] drm_test_rect_rotate ===============
[07:12:35] ================ drm_test_rect_rotate_inv  =================
[07:12:35] [PASSED] reflect-x
[07:12:35] [PASSED] reflect-y
[07:12:35] [PASSED] rotate-0
[07:12:35] [PASSED] rotate-90
[07:12:35] [PASSED] rotate-180
[07:12:35] [PASSED] rotate-270
[07:12:35] ============ [PASSED] drm_test_rect_rotate_inv =============
[07:12:35] ==================== [PASSED] drm_rect =====================
[07:12:35] ============ drm_sysfb_modeset_test (1 subtest) ============
[07:12:35] ============ drm_test_sysfb_build_fourcc_list  =============
[07:12:35] [PASSED] no native formats
[07:12:35] [PASSED] XRGB8888 as native format
[07:12:35] [PASSED] remove duplicates
[07:12:35] [PASSED] convert alpha formats
[07:12:35] [PASSED] random formats
[07:12:35] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[07:12:35] ============= [PASSED] drm_sysfb_modeset_test ==============
[07:12:35] ================== drm_fixp (2 subtests) ===================
[07:12:35] [PASSED] drm_test_int2fixp
[07:12:35] [PASSED] drm_test_sm2fixp
[07:12:35] ==================== [PASSED] drm_fixp =====================
[07:12:35] ============================================================
[07:12:35] Testing complete. Ran 667 tests: passed: 667
[07:12:35] Elapsed time: 27.926s total, 2.479s configuring, 25.030s building, 0.408s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[07:12:35] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:12:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:12:48] Starting KUnit Kernel (1/1)...
[07:12:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:12:48] ================= ttm_device (5 subtests) ==================
[07:12:48] [PASSED] ttm_device_init_basic
[07:12:48] [PASSED] ttm_device_init_multiple
[07:12:48] [PASSED] ttm_device_fini_basic
[07:12:48] [PASSED] ttm_device_init_no_vma_man
[07:12:48] ================== ttm_device_init_pools  ==================
[07:12:48] [PASSED] No DMA allocations, no DMA32 required
[07:12:48] [PASSED] DMA allocations, DMA32 required
[07:12:48] [PASSED] No DMA allocations, DMA32 required
[07:12:48] [PASSED] DMA allocations, no DMA32 required
[07:12:48] ============== [PASSED] ttm_device_init_pools ==============
[07:12:48] =================== [PASSED] ttm_device ====================
[07:12:48] ================== ttm_pool (8 subtests) ===================
[07:12:48] ================== ttm_pool_alloc_basic  ===================
[07:12:48] [PASSED] One page
[07:12:48] [PASSED] More than one page
[07:12:48] [PASSED] Above the allocation limit
[07:12:48] [PASSED] One page, with coherent DMA mappings enabled
[07:12:48] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:12:48] ============== [PASSED] ttm_pool_alloc_basic ===============
[07:12:48] ============== ttm_pool_alloc_basic_dma_addr  ==============
[07:12:48] [PASSED] One page
[07:12:48] [PASSED] More than one page
[07:12:48] [PASSED] Above the allocation limit
[07:12:48] [PASSED] One page, with coherent DMA mappings enabled
[07:12:48] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:12:48] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[07:12:48] [PASSED] ttm_pool_alloc_order_caching_match
[07:12:48] [PASSED] ttm_pool_alloc_caching_mismatch
[07:12:48] [PASSED] ttm_pool_alloc_order_mismatch
[07:12:48] [PASSED] ttm_pool_free_dma_alloc
[07:12:48] [PASSED] ttm_pool_free_no_dma_alloc
[07:12:48] [PASSED] ttm_pool_fini_basic
[07:12:48] ==================== [PASSED] ttm_pool =====================
[07:12:48] ================ ttm_resource (8 subtests) =================
[07:12:48] ================= ttm_resource_init_basic  =================
[07:12:48] [PASSED] Init resource in TTM_PL_SYSTEM
[07:12:48] [PASSED] Init resource in TTM_PL_VRAM
[07:12:48] [PASSED] Init resource in a private placement
[07:12:48] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[07:12:48] ============= [PASSED] ttm_resource_init_basic =============
[07:12:48] [PASSED] ttm_resource_init_pinned
[07:12:48] [PASSED] ttm_resource_fini_basic
[07:12:48] [PASSED] ttm_resource_manager_init_basic
[07:12:48] [PASSED] ttm_resource_manager_usage_basic
[07:12:48] [PASSED] ttm_resource_manager_set_used_basic
[07:12:48] [PASSED] ttm_sys_man_alloc_basic
[07:12:48] [PASSED] ttm_sys_man_free_basic
[07:12:48] ================== [PASSED] ttm_resource ===================
[07:12:48] =================== ttm_tt (15 subtests) ===================
[07:12:48] ==================== ttm_tt_init_basic  ====================
[07:12:48] [PASSED] Page-aligned size
[07:12:48] [PASSED] Extra pages requested
[07:12:48] ================ [PASSED] ttm_tt_init_basic ================
[07:12:48] [PASSED] ttm_tt_init_misaligned
[07:12:48] [PASSED] ttm_tt_fini_basic
[07:12:48] [PASSED] ttm_tt_fini_sg
[07:12:48] [PASSED] ttm_tt_fini_shmem
[07:12:48] [PASSED] ttm_tt_create_basic
[07:12:48] [PASSED] ttm_tt_create_invalid_bo_type
[07:12:48] [PASSED] ttm_tt_create_ttm_exists
[07:12:48] [PASSED] ttm_tt_create_failed
[07:12:48] [PASSED] ttm_tt_destroy_basic
[07:12:48] [PASSED] ttm_tt_populate_null_ttm
[07:12:48] [PASSED] ttm_tt_populate_populated_ttm
[07:12:48] [PASSED] ttm_tt_unpopulate_basic
[07:12:48] [PASSED] ttm_tt_unpopulate_empty_ttm
[07:12:48] [PASSED] ttm_tt_swapin_basic
[07:12:48] ===================== [PASSED] ttm_tt ======================
[07:12:48] =================== ttm_bo (14 subtests) ===================
[07:12:48] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[07:12:48] [PASSED] Cannot be interrupted and sleeps
[07:12:48] [PASSED] Cannot be interrupted, locks straight away
[07:12:48] [PASSED] Can be interrupted, sleeps
[07:12:48] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[07:12:48] [PASSED] ttm_bo_reserve_locked_no_sleep
[07:12:48] [PASSED] ttm_bo_reserve_no_wait_ticket
[07:12:48] [PASSED] ttm_bo_reserve_double_resv
[07:12:48] [PASSED] ttm_bo_reserve_interrupted
[07:12:48] [PASSED] ttm_bo_reserve_deadlock
[07:12:48] [PASSED] ttm_bo_unreserve_basic
[07:12:48] [PASSED] ttm_bo_unreserve_pinned
[07:12:48] [PASSED] ttm_bo_unreserve_bulk
[07:12:48] [PASSED] ttm_bo_fini_basic
[07:12:48] [PASSED] ttm_bo_fini_shared_resv
[07:12:48] [PASSED] ttm_bo_pin_basic
[07:12:48] [PASSED] ttm_bo_pin_unpin_resource
[07:12:48] [PASSED] ttm_bo_multiple_pin_one_unpin
[07:12:48] ===================== [PASSED] ttm_bo ======================
[07:12:48] ============== ttm_bo_validate (22 subtests) ===============
[07:12:48] ============== ttm_bo_init_reserved_sys_man  ===============
[07:12:48] [PASSED] Buffer object for userspace
[07:12:48] [PASSED] Kernel buffer object
[07:12:48] [PASSED] Shared buffer object
[07:12:48] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[07:12:48] ============== ttm_bo_init_reserved_mock_man  ==============
[07:12:48] [PASSED] Buffer object for userspace
[07:12:48] [PASSED] Kernel buffer object
[07:12:48] [PASSED] Shared buffer object
[07:12:48] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[07:12:48] [PASSED] ttm_bo_init_reserved_resv
[07:12:48] ================== ttm_bo_validate_basic  ==================
[07:12:48] [PASSED] Buffer object for userspace
[07:12:48] [PASSED] Kernel buffer object
[07:12:48] [PASSED] Shared buffer object
[07:12:48] ============== [PASSED] ttm_bo_validate_basic ==============
[07:12:48] [PASSED] ttm_bo_validate_invalid_placement
[07:12:48] ============= ttm_bo_validate_same_placement  ==============
[07:12:48] [PASSED] System manager
[07:12:48] [PASSED] VRAM manager
[07:12:48] ========= [PASSED] ttm_bo_validate_same_placement ==========
[07:12:48] [PASSED] ttm_bo_validate_failed_alloc
[07:12:48] [PASSED] ttm_bo_validate_pinned
[07:12:48] [PASSED] ttm_bo_validate_busy_placement
[07:12:48] ================ ttm_bo_validate_multihop  =================
[07:12:48] [PASSED] Buffer object for userspace
[07:12:48] [PASSED] Kernel buffer object
[07:12:48] [PASSED] Shared buffer object
[07:12:48] ============ [PASSED] ttm_bo_validate_multihop =============
[07:12:48] ========== ttm_bo_validate_no_placement_signaled  ==========
[07:12:48] [PASSED] Buffer object in system domain, no page vector
[07:12:48] [PASSED] Buffer object in system domain with an existing page vector
[07:12:48] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[07:12:48] ======== ttm_bo_validate_no_placement_not_signaled  ========
[07:12:48] [PASSED] Buffer object for userspace
[07:12:48] [PASSED] Kernel buffer object
[07:12:48] [PASSED] Shared buffer object
[07:12:48] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[07:12:48] [PASSED] ttm_bo_validate_move_fence_signaled
[07:12:48] ========= ttm_bo_validate_move_fence_not_signaled  =========
[07:12:48] [PASSED] Waits for GPU
[07:12:48] [PASSED] Tries to lock straight away
[07:12:48] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[07:12:48] [PASSED] ttm_bo_validate_swapout
[07:12:48] [PASSED] ttm_bo_validate_happy_evict
[07:12:48] [PASSED] ttm_bo_validate_all_pinned_evict
[07:12:48] [PASSED] ttm_bo_validate_allowed_only_evict
[07:12:48] [PASSED] ttm_bo_validate_deleted_evict
[07:12:48] [PASSED] ttm_bo_validate_busy_domain_evict
[07:12:48] [PASSED] ttm_bo_validate_evict_gutting
[07:12:48] [PASSED] ttm_bo_validate_recrusive_evict
[07:12:48] ================= [PASSED] ttm_bo_validate =================
[07:12:48] ============================================================
[07:12:48] Testing complete. Ran 102 tests: passed: 102
[07:12:48] Elapsed time: 12.860s total, 2.493s configuring, 10.151s building, 0.177s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[07:12:48] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:12:51] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:13:00] Starting KUnit Kernel (1/1)...
[07:13:00] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:13:00] =============== dma-buf-fence (12 subtests) ================
[07:13:00] [PASSED] test_sanitycheck
[07:13:00] [PASSED] test_signaling
[07:13:00] [PASSED] test_add_callback
[07:13:00] [PASSED] test_late_add_callback
[07:13:00] [PASSED] test_rm_callback
[07:13:00] [PASSED] test_late_rm_callback
[07:13:00] [PASSED] test_status
[07:13:00] [PASSED] test_error
[07:13:00] [PASSED] test_wait
[07:13:00] [PASSED] test_wait_timeout
[07:13:00] [PASSED] test_stub
[07:13:00] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[07:13:00] ================== [PASSED] dma-buf-fence ==================
[07:13:00] ============ dma-buf-fence-chain (11 subtests) =============
[07:13:00] [PASSED] test_sanitycheck
[07:13:00] [PASSED] test_find_seqno
[07:13:00] [PASSED] test_find_signaled
[07:13:00] [PASSED] test_find_out_of_order
[07:13:05] [PASSED] test_find_gap
[07:13:05] [PASSED] test_find_race
[07:13:05] [PASSED] test_signal_forward
[07:13:05] [PASSED] test_signal_backward
[07:13:05] [PASSED] test_wait_forward
[07:13:05] [PASSED] test_wait_backward
[07:13:05] [PASSED] test_wait_random
[07:13:05] =============== [PASSED] dma-buf-fence-chain ===============
[07:13:05] ============ dma-buf-fence-unwrap (11 subtests) ============
[07:13:05] [PASSED] test_sanitycheck
[07:13:05] [PASSED] test_unwrap_array
[07:13:05] [PASSED] test_unwrap_chain
[07:13:05] [PASSED] test_unwrap_chain_array
[07:13:05] [PASSED] test_unwrap_merge
[07:13:05] [PASSED] test_unwrap_merge_duplicate
[07:13:05] [PASSED] test_unwrap_merge_seqno
[07:13:05] [PASSED] test_unwrap_merge_order
[07:13:05] [PASSED] test_unwrap_merge_complex
[07:13:05] [PASSED] test_unwrap_merge_complex_seqno
[07:13:05] [PASSED] test_dedup_empty
[07:13:05] ============== [PASSED] dma-buf-fence-unwrap ===============
[07:13:05] ================ dma-buf-resv (5 subtests) =================
[07:13:05] [PASSED] test_sanitycheck
[07:13:05] ===================== test_signaling  ======================
[07:13:05] [PASSED] kernel
[07:13:05] [PASSED] write
[07:13:05] [PASSED] read
[07:13:05] [PASSED] bookkeep
[07:13:05] ================= [PASSED] test_signaling ==================
[07:13:05] ====================== test_for_each  ======================
[07:13:05] [PASSED] kernel
[07:13:05] [PASSED] write
[07:13:05] [PASSED] read
[07:13:05] [PASSED] bookkeep
[07:13:05] ================== [PASSED] test_for_each ==================
[07:13:05] ================= test_for_each_unlocked  ==================
[07:13:05] [PASSED] kernel
[07:13:05] [PASSED] write
[07:13:05] [PASSED] read
[07:13:05] [PASSED] bookkeep
[07:13:05] ============= [PASSED] test_for_each_unlocked ==============
[07:13:05] ===================== test_get_fences  =====================
[07:13:05] [PASSED] kernel
[07:13:05] [PASSED] write
[07:13:05] [PASSED] read
[07:13:05] [PASSED] bookkeep
[07:13:05] ================= [PASSED] test_get_fences =================
[07:13:05] ================== [PASSED] dma-buf-resv ===================
[07:13:05] ============================================================
[07:13:05] Testing complete. Ran 51 tests: passed: 50, skipped: 1
[07:13:05] Elapsed time: 16.714s total, 2.554s configuring, 8.838s building, 5.283s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/de: Work towards uncore elimination (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1783 bytes --]

== Series Details ==

Series: drm/i915/de: Work towards uncore elimination (rev2)
URL   : https://patchwork.freedesktop.org/series/177794/
State : success

== Summary ==

CI Bug Log - changes from xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3_BAT -> xe-pw-177794v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 15)
------------------------------

  Additional (1): bat-bmg-3 

Known issues
------------

  Here are the changes found in xe-pw-177794v2_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-bmg-2:          [PASS][1] -> [ABORT][2] ([Intel XE#9463])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html

  * igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p:
    - bat-bmg-3:          NOTRUN -> [SKIP][3] ([Intel XE#6566]) +3 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/bat-bmg-3/igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p.html

  
  [Intel XE#6566]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6566
  [Intel XE#9463]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9463


Build changes
-------------

  * Linux: xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3 -> xe-pw-177794v2

  IGT_9177: 9177
  xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3: 39c3efaee12b7c3e5e66247abea832c1986f15e3
  xe-pw-177794v2: 177794v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/index.html

[-- Attachment #2: Type: text/html, Size: 2381 bytes --]

✓ Xe.CI.FULL: success for drm/i915/de: Work towards uncore elimination (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 47901 bytes --]

== Series Details ==

Series: drm/i915/de: Work towards uncore elimination (rev2)
URL   : https://patchwork.freedesktop.org/series/177794/
State : success

== Summary ==

CI Bug Log - changes from xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3_FULL -> xe-pw-177794v2_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (3 -> 3)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-177794v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
    - shard-ptl:          NOTRUN -> [SKIP][1] ([Intel XE#5901])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-ptl:          NOTRUN -> [SKIP][2] ([Intel XE#6925])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#1124]) +1 other test skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#1124]) +2 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-ptl:          NOTRUN -> [SKIP][5] ([Intel XE#5851])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-ptl:          NOTRUN -> [SKIP][6] ([Intel XE#5808]) +5 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-target-1920x1080p:
    - shard-ptl:          NOTRUN -> [SKIP][7] ([Intel XE#7679]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_bw@connected-linear-tiling-2-displays-target-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#7679])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p.html

  * igt@kms_bw@linear-tiling-2-displays-target-1920x1080p:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#367])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_bw@linear-tiling-2-displays-target-1920x1080p.html

  * igt@kms_bw@linear-tiling-4-displays-target-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#367])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@kms_bw@linear-tiling-4-displays-target-3840x2160p.html
    - shard-ptl:          NOTRUN -> [SKIP][11] ([Intel XE#367])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@kms_bw@linear-tiling-4-displays-target-3840x2160p.html

  * igt@kms_ccs@bad-pixel-format-y-tiled-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#2887]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_ccs@bad-pixel-format-y-tiled-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs:
    - shard-ptl:          NOTRUN -> [SKIP][13] ([Intel XE#5822]) +5 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-7/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2887]) +2 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#3432])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs.html

  * igt@kms_chamelium_color@degamma:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#306] / [Intel XE#7358])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_color@gamma:
    - shard-ptl:          NOTRUN -> [SKIP][17] ([Intel XE#5824]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_chamelium_color@gamma.html

  * igt@kms_chamelium_color_pipeline@plane-lut3d-green-only:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#7358])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_chamelium_color_pipeline@plane-lut3d-green-only.html

  * igt@kms_chamelium_frames@hdmi-crc-single:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2252])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_chamelium_frames@hdmi-crc-single.html

  * igt@kms_chamelium_frames@hdmi-frame-dump:
    - shard-ptl:          NOTRUN -> [SKIP][20] ([Intel XE#2252])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_chamelium_frames@hdmi-frame-dump.html

  * igt@kms_chamelium_hpd@hdmi-hpd-after-runtime-suspend-d3hot:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#9671])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@kms_chamelium_hpd@hdmi-hpd-after-runtime-suspend-d3hot.html
    - shard-ptl:          NOTRUN -> [SKIP][22] ([Intel XE#9671])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@kms_chamelium_hpd@hdmi-hpd-after-runtime-suspend-d3hot.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#7642])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@atomic-hdcp14@pipe-a-dp-1:
    - shard-bmg:          NOTRUN -> [FAIL][24] ([Intel XE#3304])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_content_protection@atomic-hdcp14@pipe-a-dp-1.html

  * igt@kms_content_protection@dp-mst-type-1-suspend-resume:
    - shard-ptl:          NOTRUN -> [SKIP][25] ([Intel XE#6974])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html

  * igt@kms_content_protection@lic-type-0:
    - shard-ptl:          NOTRUN -> [SKIP][26] ([Intel XE#7642])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][27] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html

  * igt@kms_content_protection@type1:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#7642])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-ptl:          NOTRUN -> [SKIP][29] ([Intel XE#5900]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-ptl:          NOTRUN -> [SKIP][30] ([Intel XE#5962]) +2 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#309] / [Intel XE#7343])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
    - shard-ptl:          NOTRUN -> [SKIP][32] ([Intel XE#5962] / [Intel XE#7343])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][33] -> [FAIL][34] ([Intel XE#7809])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-9/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#323] / [Intel XE#6035])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dp_link_training@non-uhbr-mst-direct-train:
    - shard-ptl:          NOTRUN -> [SKIP][36] ([Intel XE#9532])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_dp_link_training@non-uhbr-mst-direct-train.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-ptl:          NOTRUN -> [SKIP][37] ([Intel XE#9009])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-7/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc-bigjoiner:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#8265])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_dsc@dsc-fractional-bpp-with-bpc-bigjoiner.html

  * igt@kms_dsc@dsc-with-formats-bigjoiner:
    - shard-ptl:          NOTRUN -> [SKIP][39] ([Intel XE#5907]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_dsc@dsc-with-formats-bigjoiner.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#8265]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#4156] / [Intel XE#7425])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_fbcon_fbt@psr:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#8680])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@kms_fbcon_fbt@psr.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-ptl:          NOTRUN -> [SKIP][43] ([Intel XE#2316]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode:
    - shard-ptl:          NOTRUN -> [SKIP][44] ([Intel XE#5828]) +1 other test skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-ptl:          NOTRUN -> [SKIP][45] ([Intel XE#7178]) +3 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#7178] / [Intel XE#7351])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#6312] / [Intel XE#651]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-blt:
    - shard-ptl:          NOTRUN -> [SKIP][48] ([Intel XE#5800] / [Intel XE#6312]) +3 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrshdr-slowdraw:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#2311]) +21 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrshdr-slowdraw.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#4141]) +3 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-render:
    - shard-ptl:          NOTRUN -> [SKIP][52] ([Intel XE#6312]) +5 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#656] / [Intel XE#7905]) +3 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-pri-indfb-multidraw:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#6312]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-fullscreen:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#7865]) +5 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-indfb-msflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#7905]) +6 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#7061])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-rgb565-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][58] ([Intel XE#7865]) +10 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_frontbuffer_tracking@fbchdr-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt:
    - shard-ptl:          NOTRUN -> [SKIP][59] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-argb161616f-draw-blt:
    - shard-ptl:          NOTRUN -> [SKIP][60] ([Intel XE#7061]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_frontbuffer_tracking@fbcpsrhdr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render:
    - shard-ptl:          NOTRUN -> [SKIP][61] ([Intel XE#5812]) +29 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-pri-shrfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#2313]) +18 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_hdr@static-toggle:
    - shard-ptl:          NOTRUN -> [SKIP][63] ([Intel XE#5917] / [Intel XE#6174])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_hdr@static-toggle.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-lnl:          NOTRUN -> [SKIP][64] ([Intel XE#1503])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-ptl:          NOTRUN -> [SKIP][65] ([Intel XE#6900])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-ptl:          NOTRUN -> [SKIP][66] ([Intel XE#7173])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_mst@mst-suspend-read-crc:
    - shard-bmg:          NOTRUN -> [SKIP][67] ([Intel XE#8348])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_mst@mst-suspend-read-crc.html

  * igt@kms_plane@pixel-format-x-tiled-modifier:
    - shard-ptl:          NOTRUN -> [SKIP][68] ([Intel XE#7283])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_plane@pixel-format-x-tiled-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#7283])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier:
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#7283])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_plane@pixel-format-yf-tiled-modifier.html

  * igt@kms_plane_lowres@tiling-none@pipe-b-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][71] ([Intel XE#5844]) +4 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_plane_lowres@tiling-none@pipe-b-edp-1.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-ptl:          NOTRUN -> [SKIP][72] ([Intel XE#5020])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-7/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#5020] / [Intel XE#7348])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers:
    - shard-ptl:          NOTRUN -> [SKIP][74] ([Intel XE#6886]) +4 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b:
    - shard-lnl:          NOTRUN -> [SKIP][75] ([Intel XE#2763] / [Intel XE#6886]) +3 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b.html

  * igt@kms_pm_dc@dc3co-after-dc6@pr-xrgb8888:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#8395] / [Intel XE#8396]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_pm_dc@dc3co-after-dc6@pr-xrgb8888.html

  * igt@kms_pm_dc@dc3co-after-dc6@psr2-yuv420:
    - shard-lnl:          NOTRUN -> [SKIP][77] ([Intel XE#8396]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_pm_dc@dc3co-after-dc6@psr2-yuv420.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#3309] / [Intel XE#7368])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-lnl:          NOTRUN -> [FAIL][79] ([Intel XE#2029] / [Intel XE#7395])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#1489]) +1 other test skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-a-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][81] ([Intel XE#5858])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-b-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][82] ([Intel XE#5858] / [Intel XE#7304]) +1 other test skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf:
    - shard-lnl:          NOTRUN -> [SKIP][83] ([Intel XE#2893] / [Intel XE#7304])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area:
    - shard-ptl:          NOTRUN -> [SKIP][84] ([Intel XE#7304])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-ptl:          NOTRUN -> [SKIP][85] ([Intel XE#7413])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - shard-bmg:          NOTRUN -> [SKIP][86] ([Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_psr@fbc-psr2-sprite-plane-onoff@edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][87] ([Intel XE#1406] / [Intel XE#5835]) +1 other test skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_psr@fbc-psr2-sprite-plane-onoff@edp-1.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-bmg:          NOTRUN -> [SKIP][88] ([Intel XE#3904] / [Intel XE#7342])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_scaling_modes@scaling-mode-center:
    - shard-bmg:          NOTRUN -> [SKIP][89] ([Intel XE#2413])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@kms_scaling_modes@scaling-mode-center.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-ptl:          NOTRUN -> [SKIP][90] ([Intel XE#5910])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_sharpness_filter@invalid-filter-with-nearest-neighbor:
    - shard-bmg:          NOTRUN -> [SKIP][91] ([Intel XE#6503])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@kms_sharpness_filter@invalid-filter-with-nearest-neighbor.html

  * igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-system-vram01:
    - shard-bmg:          [PASS][92] -> [INCOMPLETE][93] ([Intel XE#9410])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3/shard-bmg-7/igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-system-vram01.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-9/igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-system-vram01.html

  * igt@xe_compute@eu-busy-10s:
    - shard-bmg:          NOTRUN -> [SKIP][94] ([Intel XE#6599])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@xe_compute@eu-busy-10s.html
    - shard-ptl:          NOTRUN -> [SKIP][95] ([Intel XE#6599])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@xe_compute@eu-busy-10s.html

  * igt@xe_create@multigpu-create-massive-size:
    - shard-bmg:          NOTRUN -> [SKIP][96] ([Intel XE#2504] / [Intel XE#7319] / [Intel XE#7350])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@xe_create@multigpu-create-massive-size.html
    - shard-ptl:          NOTRUN -> [SKIP][97] ([Intel XE#5878])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@xe_create@multigpu-create-massive-size.html

  * igt@xe_evict@evict-beng-small-multi-vm:
    - shard-ptl:          NOTRUN -> [SKIP][98] ([Intel XE#5764]) +2 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@xe_evict@evict-beng-small-multi-vm.html

  * igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-reopen:
    - shard-lnl:          NOTRUN -> [SKIP][99] ([Intel XE#6540] / [Intel XE#688]) +1 other test skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-reopen.html

  * igt@xe_exec_balancer@once-parallel-userptr-rebind:
    - shard-ptl:          NOTRUN -> [SKIP][100] ([Intel XE#7482]) +8 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-7/igt@xe_exec_balancer@once-parallel-userptr-rebind.html

  * igt@xe_exec_balancer@twice-cm-virtual-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][101] ([Intel XE#7482]) +3 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@xe_exec_balancer@twice-cm-virtual-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][102] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate.html

  * igt@xe_exec_basic@multigpu-once-basic:
    - shard-lnl:          NOTRUN -> [SKIP][103] ([Intel XE#1392])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@xe_exec_basic@multigpu-once-basic.html

  * igt@xe_exec_basic@multigpu-once-null-defer-bind:
    - shard-ptl:          NOTRUN -> [SKIP][104] ([Intel XE#5575] / [Intel XE#7484]) +2 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@xe_exec_basic@multigpu-once-null-defer-bind.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][105] ([Intel XE#8374])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@many-multi-queue-rebind-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][106] ([Intel XE#8374]) +3 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@xe_exec_fault_mode@many-multi-queue-rebind-prefetch.html

  * igt@xe_exec_fault_mode@many-multi-queue-userptr-prefetch:
    - shard-ptl:          NOTRUN -> [SKIP][107] ([Intel XE#8374]) +6 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@xe_exec_fault_mode@many-multi-queue-userptr-prefetch.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-close-fd:
    - shard-bmg:          NOTRUN -> [SKIP][108] ([Intel XE#8364]) +6 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@xe_exec_multi_queue@many-queues-preempt-mode-close-fd.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-close-fd-smem:
    - shard-lnl:          NOTRUN -> [SKIP][109] ([Intel XE#8364]) +4 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@xe_exec_multi_queue@many-queues-preempt-mode-close-fd-smem.html

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-userptr:
    - shard-ptl:          NOTRUN -> [SKIP][110] ([Intel XE#8364]) +9 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@xe_exec_multi_queue@one-queue-preempt-mode-userptr.html

  * igt@xe_exec_reset@multi-queue-cat-error-on-secondary:
    - shard-ptl:          NOTRUN -> [SKIP][111] ([Intel XE#8369])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@xe_exec_reset@multi-queue-cat-error-on-secondary.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][112] ([Intel XE#8378])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr-invalidate.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-userptr-rebind:
    - shard-ptl:          NOTRUN -> [SKIP][113] ([Intel XE#8378]) +2 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@xe_exec_threads@threads-multi-queue-mixed-userptr-rebind.html

  * igt@xe_exec_threads@threads-multi-queue-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][114] ([Intel XE#8378]) +1 other test skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@xe_exec_threads@threads-multi-queue-rebind.html

  * igt@xe_gpgpu_fill@offset-4x4:
    - shard-bmg:          NOTRUN -> [SKIP][115] ([Intel XE#7954])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@xe_gpgpu_fill@offset-4x4.html
    - shard-ptl:          NOTRUN -> [SKIP][116] ([Intel XE#7954])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@xe_gpgpu_fill@offset-4x4.html

  * igt@xe_madvise@atomic-cpu:
    - shard-ptl:          NOTRUN -> [SKIP][117] ([Intel XE#7980])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@xe_madvise@atomic-cpu.html

  * igt@xe_multigpu_svm@mgpu-atomic-op-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][118] ([Intel XE#6964])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@xe_multigpu_svm@mgpu-atomic-op-prefetch.html

  * igt@xe_multigpu_svm@mgpu-coherency-conflict:
    - shard-bmg:          NOTRUN -> [SKIP][119] ([Intel XE#6964]) +1 other test skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@xe_multigpu_svm@mgpu-coherency-conflict.html

  * igt@xe_multigpu_svm@mgpu-latency-copy-prefetch:
    - shard-ptl:          NOTRUN -> [SKIP][120] ([Intel XE#6964]) +1 other test skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@xe_multigpu_svm@mgpu-latency-copy-prefetch.html

  * igt@xe_page_reclaim@pat-index-xd:
    - shard-ptl:          NOTRUN -> [SKIP][121] ([Intel XE#7793]) +1 other test skip
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@xe_page_reclaim@pat-index-xd.html
    - shard-bmg:          NOTRUN -> [SKIP][122] ([Intel XE#7793])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@xe_page_reclaim@pat-index-xd.html

  * igt@xe_pat@pat-sw-hw-compare:
    - shard-ptl:          NOTRUN -> [FAIL][123] ([Intel XE#7695])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@xe_pat@pat-sw-hw-compare.html
    - shard-bmg:          NOTRUN -> [FAIL][124] ([Intel XE#7695])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@xe_pat@pat-sw-hw-compare.html

  * igt@xe_peer2peer@read:
    - shard-lnl:          NOTRUN -> [SKIP][125] ([Intel XE#1061] / [Intel XE#7326] / [Intel XE#7353])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@xe_peer2peer@read.html

  * igt@xe_pm@s4-d3hot-basic-exec:
    - shard-ptl:          [PASS][126] -> [DMESG-WARN][127] ([Intel XE#7727])
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3/shard-ptl-7/igt@xe_pm@s4-d3hot-basic-exec.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@xe_pm@s4-d3hot-basic-exec.html

  * igt@xe_pm@s4-exec-after:
    - shard-lnl:          [PASS][128] -> [ABORT][129] ([Intel XE#9362])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3/shard-lnl-3/igt@xe_pm@s4-exec-after.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-7/igt@xe_pm@s4-exec-after.html

  * igt@xe_prefetch_fault@prefetch-fault-svm:
    - shard-ptl:          NOTRUN -> [SKIP][130] ([Intel XE#7599])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@xe_prefetch_fault@prefetch-fault-svm.html

  * igt@xe_pxp@regular-src-to-pxp-dest-rendercopy:
    - shard-bmg:          NOTRUN -> [SKIP][131] ([Intel XE#4733] / [Intel XE#7417])
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-7/igt@xe_pxp@regular-src-to-pxp-dest-rendercopy.html

  * igt@xe_query@multigpu-query-uc-fw-version-guc:
    - shard-lnl:          NOTRUN -> [SKIP][132] ([Intel XE#944])
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@xe_query@multigpu-query-uc-fw-version-guc.html

  * igt@xe_sriov_flr@flr-twice:
    - shard-lnl:          NOTRUN -> [SKIP][133] ([Intel XE#4273])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-8/igt@xe_sriov_flr@flr-twice.html

  * igt@xe_survivability@runtime-survivability:
    - shard-ptl:          NOTRUN -> [SKIP][134] ([Intel XE#8415] / [Intel XE#8432])
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-2/igt@xe_survivability@runtime-survivability.html

  * igt@xe_vm@overcommit-fault-vram-lr-no-overcommit:
    - shard-ptl:          NOTRUN -> [SKIP][135] ([Intel XE#9597])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@xe_vm@overcommit-fault-vram-lr-no-overcommit.html

  
#### Possible fixes ####

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [FAIL][136] ([Intel XE#301]) -> [PASS][137] +1 other test pass
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_vrr@flip-basic:
    - shard-ptl:          [FAIL][138] ([Intel XE#4227] / [Intel XE#7397]) -> [PASS][139] +1 other test pass
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3/shard-ptl-1/igt@kms_vrr@flip-basic.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@kms_vrr@flip-basic.html

  * igt@xe_exec_fault_mode@atomic-many:
    - shard-bmg:          [FAIL][140] ([Intel XE#8578]) -> [PASS][141]
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3/shard-bmg-5/igt@xe_exec_fault_mode@atomic-many.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-1/igt@xe_exec_fault_mode@atomic-many.html

  * igt@xe_pm@s4-multiple-execs:
    - shard-lnl:          [DMESG-WARN][142] ([Intel XE#7727]) -> [PASS][143]
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3/shard-lnl-8/igt@xe_pm@s4-multiple-execs.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-lnl-4/igt@xe_pm@s4-multiple-execs.html

  * igt@xe_pm@s4-vm-bind-userptr:
    - shard-ptl:          [ABORT][144] ([Intel XE#9362]) -> [PASS][145] +1 other test pass
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3/shard-ptl-1/igt@xe_pm@s4-vm-bind-userptr.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-ptl-3/igt@xe_pm@s4-vm-bind-userptr.html

  
#### Warnings ####

  * igt@xe_survivability@runtime-survivability:
    - shard-bmg:          [ABORT][146] ([Intel XE#9463]) -> [DMESG-WARN][147] ([Intel XE#9365])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3/shard-bmg-10/igt@xe_survivability@runtime-survivability.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/shard-bmg-6/igt@xe_survivability@runtime-survivability.html

  
  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2029]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2029
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2504
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
  [Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
  [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
  [Intel XE#5800]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5800
  [Intel XE#5808]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5808
  [Intel XE#5812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5812
  [Intel XE#5822]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5822
  [Intel XE#5824]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5824
  [Intel XE#5828]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5828
  [Intel XE#5835]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5835
  [Intel XE#5844]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5844
  [Intel XE#5851]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5851
  [Intel XE#5858]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5858
  [Intel XE#5878]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5878
  [Intel XE#5900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5900
  [Intel XE#5901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5901
  [Intel XE#5907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5907
  [Intel XE#5910]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5910
  [Intel XE#5917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5917
  [Intel XE#5962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5962
  [Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
  [Intel XE#6174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6174
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6599
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
  [Intel XE#6925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6925
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7173
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7319]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7319
  [Intel XE#7326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7326
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7348
  [Intel XE#7350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7350
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7353]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7353
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7368]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7368
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7395
  [Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
  [Intel XE#7413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7413
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7425]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7425
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7484
  [Intel XE#7599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7599
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7695
  [Intel XE#7727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7727
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7809]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7809
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7954]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7954
  [Intel XE#7980]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7980
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8348
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8395
  [Intel XE#8396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8396
  [Intel XE#8415]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8415
  [Intel XE#8432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8432
  [Intel XE#8578]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8578
  [Intel XE#8680]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8680
  [Intel XE#9009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9009
  [Intel XE#9362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9362
  [Intel XE#9365]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9365
  [Intel XE#9410]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9410
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#9463]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9463
  [Intel XE#9532]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9532
  [Intel XE#9597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9597
  [Intel XE#9671]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9671


Build changes
-------------

  * Linux: xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3 -> xe-pw-177794v2

  IGT_9177: 9177
  xe-6065-39c3efaee12b7c3e5e66247abea832c1986f15e3: 39c3efaee12b7c3e5e66247abea832c1986f15e3
  xe-pw-177794v2: 177794v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177794v2/index.html

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