From: Luwei Kang <luwei.kang@intel.com>
To: kvm@vger.kernel.org, x86@kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
hpa@zytor.com, pbonzini@redhat.com, rkrcmar@redhat.com,
joro@8bytes.org, songliubraving@fb.com, peterz@infradead.org,
alexander.shishkin@linux.intel.com, kstewart@linuxfoundation.org,
gregkh@linuxfoundation.org, thomas.lendacky@amd.com,
konrad.wilk@oracle.com, mattst88@gmail.com,
Janakarajan.Natarajan@amd.com, dwmw@amazon.co.uk,
jpoimboe@redhat.com, marcorr@google.com, ubizjak@gmail.com,
sean.j.christopherson@intel.com, jmattson@google.com,
linux-kernel@vger.kernel.org, Luwei Kang <luwei.kang@intel.com>
Subject: [PATCH v13 04/12] perf/x86/intel/pt: Add new bit definitions for PT MSRs
Date: Wed, 24 Oct 2018 16:05:08 +0800 [thread overview]
Message-ID: <1540368316-12998-5-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1540368316-12998-1-git-send-email-luwei.kang@intel.com>
Add bit definitions for Intel PT MSRs to support trace output
directed to the memeory subsystem and holds a count if packet
bytes that have been sent out.
These are required by the upcoming PT support in KVM guests
for MSRs read/write emulation.
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
arch/x86/include/asm/msr-index.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index d3a9eb9..107818e3 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -126,6 +126,7 @@
#define RTIT_CTL_USR BIT(3)
#define RTIT_CTL_PWR_EVT_EN BIT(4)
#define RTIT_CTL_FUP_ON_PTW BIT(5)
+#define RTIT_CTL_FABRIC_EN BIT(6)
#define RTIT_CTL_CR3EN BIT(7)
#define RTIT_CTL_TOPA BIT(8)
#define RTIT_CTL_MTC_EN BIT(9)
@@ -154,6 +155,8 @@
#define RTIT_STATUS_BUFFOVF BIT(3)
#define RTIT_STATUS_ERROR BIT(4)
#define RTIT_STATUS_STOPPED BIT(5)
+#define RTIT_STATUS_BYTECNT_OFFSET 32
+#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET)
#define MSR_IA32_RTIT_ADDR0_A 0x00000580
#define MSR_IA32_RTIT_ADDR0_B 0x00000581
#define MSR_IA32_RTIT_ADDR1_A 0x00000582
--
1.8.3.1
next prev parent reply other threads:[~2018-10-24 8:05 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-24 8:05 [PATCH v13 00/12] Intel Processor Trace virtualization enabling Luwei Kang
2018-10-24 8:05 ` [PATCH v13 01/12] perf/x86/intel/pt: Move Intel PT MSRs bit defines to global header Luwei Kang
2018-10-24 8:05 ` [PATCH v13 02/12] perf/x86/intel/pt: Export pt_cap_get() Luwei Kang
2018-10-24 8:05 ` [PATCH v13 03/12] perf/x86/intel/pt: Introduce intel_pt_validate_cap() Luwei Kang
2018-10-24 8:05 ` Luwei Kang [this message]
2018-10-24 8:05 ` [PATCH v13 05/12] perf/x86/intel/pt: add new capability for Intel PT Luwei Kang
2018-10-30 9:57 ` Thomas Gleixner
2018-10-24 8:05 ` [PATCH v13 06/12] KVM: x86: Add Intel PT virtualization work mode Luwei Kang
2018-10-24 16:18 ` Jim Mattson
2018-10-25 0:35 ` Kang, Luwei
2018-10-30 9:30 ` Thomas Gleixner
2018-10-30 9:49 ` Paolo Bonzini
2018-10-30 10:13 ` Kang, Luwei
2018-10-30 10:23 ` Thomas Gleixner
2018-10-31 0:36 ` Kang, Luwei
2018-10-24 8:05 ` [PATCH v13 07/12] KVM: x86: Add Intel Processor Trace cpuid emulation Luwei Kang
2018-10-24 8:05 ` [PATCH v13 08/12] KVM: x86: Add Intel PT context switch for each vcpu Luwei Kang
2018-10-24 10:13 ` Alexander Shishkin
2018-10-25 0:06 ` Kang, Luwei
2018-10-29 17:48 ` Paolo Bonzini
2018-10-30 10:00 ` Thomas Gleixner
2018-10-31 10:43 ` Paolo Bonzini
2018-10-31 11:46 ` Alexander Shishkin
2018-10-30 11:26 ` Alexander Shishkin
2018-10-31 10:49 ` Paolo Bonzini
2018-10-31 11:38 ` Alexander Shishkin
2018-10-31 12:07 ` Paolo Bonzini
2018-10-31 14:21 ` Alexander Shishkin
2018-10-31 14:43 ` Paolo Bonzini
2018-10-24 8:05 ` [PATCH v13 09/12] KVM: x86: Introduce a function to initialize the PT configuration Luwei Kang
2018-10-24 8:05 ` [PATCH v13 10/12] KVM: x86: Implement Intel PT MSRs read/write emulation Luwei Kang
2018-10-24 8:05 ` [PATCH v13 11/12] KVM: x86: Set intercept for Intel PT MSRs read/write Luwei Kang
2018-10-24 8:05 ` [PATCH v13 12/12] KVM: x86: Disable Intel PT when VMXON in L1 guest Luwei Kang
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