From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
linux-riscv@lists.infradead.org,
Mark Rutland <mark.rutland@arm.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Will Deacon <will@kernel.org>
Subject: [PATCH v5 02/14] perf: RISC-V: Improve privilege mode filtering for perf
Date: Sat, 4 Feb 2023 17:15:03 -0800 [thread overview]
Message-ID: <20230205011515.1284674-3-atishp@rivosinc.com> (raw)
In-Reply-To: <20230205011515.1284674-1-atishp@rivosinc.com>
Currently, the host driver doesn't have any method to identify if the
requested perf event is from kvm or bare metal. As KVM runs in HS
mode, there are no separate hypervisor privilege mode to distinguish
between the attributes for guest/host.
Improve the privilege mode filtering by using the event specific
config1 field.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
drivers/perf/riscv_pmu_sbi.c | 27 ++++++++++++++++++++++-----
include/linux/perf/riscv_pmu.h | 2 ++
2 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 6b53adc..71174fa 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -301,6 +301,27 @@ int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr)
}
EXPORT_SYMBOL_GPL(riscv_pmu_get_hpm_info);
+static unsigned long pmu_sbi_get_filter_flags(struct perf_event *event)
+{
+ unsigned long cflags = 0;
+ bool guest_events = false;
+
+ if (event->attr.config1 & RISCV_PMU_CONFIG1_GUEST_EVENTS)
+ guest_events = true;
+ if (event->attr.exclude_kernel)
+ cflags |= guest_events ? SBI_PMU_CFG_FLAG_SET_VSINH : SBI_PMU_CFG_FLAG_SET_SINH;
+ if (event->attr.exclude_user)
+ cflags |= guest_events ? SBI_PMU_CFG_FLAG_SET_VUINH : SBI_PMU_CFG_FLAG_SET_UINH;
+ if (guest_events && event->attr.exclude_hv)
+ cflags |= SBI_PMU_CFG_FLAG_SET_SINH;
+ if (event->attr.exclude_host)
+ cflags |= SBI_PMU_CFG_FLAG_SET_UINH | SBI_PMU_CFG_FLAG_SET_SINH;
+ if (event->attr.exclude_guest)
+ cflags |= SBI_PMU_CFG_FLAG_SET_VSINH | SBI_PMU_CFG_FLAG_SET_VUINH;
+
+ return cflags;
+}
+
static int pmu_sbi_ctr_get_idx(struct perf_event *event)
{
struct hw_perf_event *hwc = &event->hw;
@@ -311,11 +332,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event)
uint64_t cbase = 0;
unsigned long cflags = 0;
- if (event->attr.exclude_kernel)
- cflags |= SBI_PMU_CFG_FLAG_SET_SINH;
- if (event->attr.exclude_user)
- cflags |= SBI_PMU_CFG_FLAG_SET_UINH;
-
+ cflags = pmu_sbi_get_filter_flags(event);
/* retrieve the available counter index */
#if defined(CONFIG_32BIT)
ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase,
diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h
index a1c3f77..43fc892 100644
--- a/include/linux/perf/riscv_pmu.h
+++ b/include/linux/perf/riscv_pmu.h
@@ -26,6 +26,8 @@
#define RISCV_PMU_STOP_FLAG_RESET 1
+#define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1
+
struct cpu_hw_events {
/* currently enabled events */
int n_events;
--
2.25.1
next prev parent reply other threads:[~2023-02-05 1:15 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-05 1:15 [PATCH v5 00/14] KVM perf support Atish Patra
2023-02-05 1:15 ` [PATCH v5 01/14] perf: RISC-V: Define helper functions expose hpm counter width and count Atish Patra
2023-02-05 1:15 ` Atish Patra [this message]
2023-02-05 1:15 ` [PATCH v5 03/14] RISC-V: Improve SBI PMU extension related definitions Atish Patra
2023-02-05 1:15 ` [PATCH v5 04/14] RISC-V: KVM: Define a probe function for SBI extension data structures Atish Patra
2023-02-05 1:15 ` [PATCH v5 05/14] RISC-V: KVM: Return correct code for hsm stop function Atish Patra
2023-02-05 1:15 ` [PATCH v5 06/14] RISC-V: KVM: Modify SBI extension handler to return SBI error code Atish Patra
2023-02-06 10:27 ` Andrew Jones
2023-02-06 17:08 ` Anup Patel
2023-02-05 1:15 ` [PATCH v5 07/14] RISC-V: KVM: Add skeleton support for perf Atish Patra
2023-02-06 11:45 ` Andrew Jones
2023-02-05 1:15 ` [PATCH v5 08/14] RISC-V: KVM: Add SBI PMU extension support Atish Patra
2023-02-05 10:30 ` Conor Dooley
2023-02-07 6:10 ` Atish Patra
2023-02-07 6:24 ` Conor Dooley
2023-02-06 11:50 ` Andrew Jones
2023-02-05 1:15 ` [PATCH v5 09/14] RISC-V: KVM: Make PMU functionality depend on Sscofpmf Atish Patra
2023-02-05 1:15 ` [PATCH v5 10/14] RISC-V: KVM: Disable all hpmcounter access for VS/VU mode Atish Patra
2023-02-05 1:15 ` [PATCH v5 11/14] RISC-V: KVM: Implement trap & emulate for hpmcounters Atish Patra
2023-02-06 11:54 ` Andrew Jones
2023-02-05 1:15 ` [PATCH v5 12/14] RISC-V: KVM: Implement perf support without sampling Atish Patra
2023-02-05 1:15 ` [PATCH v5 13/14] RISC-V: KVM: Support firmware events Atish Patra
2023-02-06 12:04 ` Andrew Jones
2023-02-05 1:15 ` [PATCH v5 14/14] RISC-V: KVM: Increment firmware pmu events Atish Patra
2023-02-06 17:10 ` [PATCH v5 00/14] KVM perf support Anup Patel
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