From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
Anup Patel <anup@brainfault.org>,
Andrew Jones <ajones@ventanamicro.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
linux-riscv@lists.infradead.org,
Mark Rutland <mark.rutland@arm.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Will Deacon <will@kernel.org>
Subject: [PATCH v5 03/14] RISC-V: Improve SBI PMU extension related definitions
Date: Sat, 4 Feb 2023 17:15:04 -0800 [thread overview]
Message-ID: <20230205011515.1284674-4-atishp@rivosinc.com> (raw)
In-Reply-To: <20230205011515.1284674-1-atishp@rivosinc.com>
This patch fixes/improve few minor things in SBI PMU extension
definition.
1. Align all the firmware event names.
2. Add macros for bit positions in cache event ID & ops.
The changes were small enough to combine them together instead
of creating 1 liner patches.
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/include/asm/sbi.h | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 4ca7fba..945b7be 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -169,9 +169,9 @@ enum sbi_pmu_fw_generic_events_t {
SBI_PMU_FW_ILLEGAL_INSN = 4,
SBI_PMU_FW_SET_TIMER = 5,
SBI_PMU_FW_IPI_SENT = 6,
- SBI_PMU_FW_IPI_RECVD = 7,
+ SBI_PMU_FW_IPI_RCVD = 7,
SBI_PMU_FW_FENCE_I_SENT = 8,
- SBI_PMU_FW_FENCE_I_RECVD = 9,
+ SBI_PMU_FW_FENCE_I_RCVD = 9,
SBI_PMU_FW_SFENCE_VMA_SENT = 10,
SBI_PMU_FW_SFENCE_VMA_RCVD = 11,
SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12,
@@ -215,6 +215,9 @@ enum sbi_pmu_ctr_type {
#define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06
#define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01
+#define SBI_PMU_EVENT_CACHE_ID_SHIFT 3
+#define SBI_PMU_EVENT_CACHE_OP_SHIFT 1
+
#define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
/* Flags defined for config matching function */
--
2.25.1
next prev parent reply other threads:[~2023-02-05 1:15 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-05 1:15 [PATCH v5 00/14] KVM perf support Atish Patra
2023-02-05 1:15 ` [PATCH v5 01/14] perf: RISC-V: Define helper functions expose hpm counter width and count Atish Patra
2023-02-05 1:15 ` [PATCH v5 02/14] perf: RISC-V: Improve privilege mode filtering for perf Atish Patra
2023-02-05 1:15 ` Atish Patra [this message]
2023-02-05 1:15 ` [PATCH v5 04/14] RISC-V: KVM: Define a probe function for SBI extension data structures Atish Patra
2023-02-05 1:15 ` [PATCH v5 05/14] RISC-V: KVM: Return correct code for hsm stop function Atish Patra
2023-02-05 1:15 ` [PATCH v5 06/14] RISC-V: KVM: Modify SBI extension handler to return SBI error code Atish Patra
2023-02-06 10:27 ` Andrew Jones
2023-02-06 17:08 ` Anup Patel
2023-02-05 1:15 ` [PATCH v5 07/14] RISC-V: KVM: Add skeleton support for perf Atish Patra
2023-02-06 11:45 ` Andrew Jones
2023-02-05 1:15 ` [PATCH v5 08/14] RISC-V: KVM: Add SBI PMU extension support Atish Patra
2023-02-05 10:30 ` Conor Dooley
2023-02-07 6:10 ` Atish Patra
2023-02-07 6:24 ` Conor Dooley
2023-02-06 11:50 ` Andrew Jones
2023-02-05 1:15 ` [PATCH v5 09/14] RISC-V: KVM: Make PMU functionality depend on Sscofpmf Atish Patra
2023-02-05 1:15 ` [PATCH v5 10/14] RISC-V: KVM: Disable all hpmcounter access for VS/VU mode Atish Patra
2023-02-05 1:15 ` [PATCH v5 11/14] RISC-V: KVM: Implement trap & emulate for hpmcounters Atish Patra
2023-02-06 11:54 ` Andrew Jones
2023-02-05 1:15 ` [PATCH v5 12/14] RISC-V: KVM: Implement perf support without sampling Atish Patra
2023-02-05 1:15 ` [PATCH v5 13/14] RISC-V: KVM: Support firmware events Atish Patra
2023-02-06 12:04 ` Andrew Jones
2023-02-05 1:15 ` [PATCH v5 14/14] RISC-V: KVM: Increment firmware pmu events Atish Patra
2023-02-06 17:10 ` [PATCH v5 00/14] KVM perf support Anup Patel
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