public inbox for kvm@vger.kernel.org
 help / color / mirror / Atom feed
From: Joey Gouly <joey.gouly@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	kvm@vger.kernel.org, James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Mark Brown <broonie@kernel.org>
Subject: Re: [PATCH v2 12/16] KVM: arm64: Implement AT S1PIE support
Date: Thu, 5 Sep 2024 16:37:34 +0100	[thread overview]
Message-ID: <20240905153734.GA4157679@e124191.cambridge.arm.com> (raw)
In-Reply-To: <86ikvaup12.wl-maz@kernel.org>

On Thu, Sep 05, 2024 at 03:57:13PM +0100, Marc Zyngier wrote:
> Hi Joey,
> 
> Thanks for having a look.
> 
> On Thu, 05 Sep 2024 14:58:20 +0100,
> Joey Gouly <joey.gouly@arm.com> wrote:
> > 
> > Hello Marc!
> > 
> > >  static void compute_s1_permissions(struct kvm_vcpu *vcpu, u32 op,
> > >  				   struct s1_walk_info *wi,
> > >  				   struct s1_walk_result *wr,
> > >  				   struct s1_perms *s1p)
> > >  {
> > > -	compute_s1_direct_permissions(vcpu, wi, wr, s1p);
> > > +	if (!s1pie_enabled(vcpu, wi->regime))
> > > +		compute_s1_direct_permissions(vcpu, wi, wr, s1p);
> > > +	else
> > > +		compute_s1_indirect_permissions(vcpu, wi, wr, s1p);
> > > +
> > >  	compute_s1_hierarchical_permissions(vcpu, wi, wr, s1p);
> > 
> > Is this (and the previous patch to split this up) right?
> > 
> > Looking at this from the ARM ARM (ARM DDI 0487K.a):
> > 
> > 	R JHSVW If Indirect permissions are used, then hierarchical
> > 	permissions are disabled and TCR_ELx.HPDn are RES 1.
> 
> Odd. I was convinced that it was when S1POE is enabled that HPs were
> disabled. But you are absolutely right, and it is once more proven
> that I can't read. Oh well.

For POE there is:

	RBVXDG Hierarchical Permissions are disabled and the TCR_ELx.{HPD0, HPD1} bits are RES1 for stage 1 of a translation
	regime using VMSAv8-64 if one or more of POE and E0POE (for EL1&0, EL2&0) is enabled for that translation
	regime.

> 
> Not to worry, I've since found other issues with this series. I have
> forgotten the patch dealing with the fast path on another branch, and
> since decided that TCR2_EL2 needed extra care to cope with individual
> features being disabled.
> 
> The rework is still useful, as I'm looking at POE as well, but I need
> to hoist the HP stuff up a notch.
> 
> I'll repost things once I've sorted these things up.

I think the rest of this patch looked fine though.

> 
> Thanks again,
> 
> 	M.
> 
> -- 
> Without deviation from the norm, progress is not possible.

  reply	other threads:[~2024-09-05 15:37 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-03 15:38 [PATCH v2 00/16] KVM: arm64: Add EL2 support to FEAT_S1PIE Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 01/16] KVM: arm64: nv: Handle CNTHCTL_EL2 specially Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 02/16] KVM: arm64: nv: Save/Restore vEL2 sysregs Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 03/16] KVM: arm64: Add TCR2_EL2 to the sysreg arrays Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 04/16] KVM: arm64: Add save/restore for TCR2_EL2 Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 05/16] arm64: Add encoding for PIRE0_EL2 Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 06/16] arm64: Remove VNCR definition " Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 07/16] KVM: arm64: Add PIR{,E0}_EL2 to the sysreg arrays Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 08/16] KVM: arm64: Add save/restore for PIR{,E0}_EL2 Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 09/16] KVM: arm64: Handle PIR{,E0}_EL2 traps Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 10/16] KVM: arm64: Sanitise ID_AA64MMFR3_EL1 Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 11/16] KVM: arm64: Split S1 permission evaluation into direct and hierarchical parts Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 12/16] KVM: arm64: Implement AT S1PIE support Marc Zyngier
2024-09-05 13:58   ` Joey Gouly
2024-09-05 14:57     ` Marc Zyngier
2024-09-05 15:37       ` Joey Gouly [this message]
2024-09-06  7:04         ` Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 13/16] KVM: arm64: Define helper for EL2 registers with custom visibility Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 14/16] KVM: arm64: Hide TCR2_EL1 from userspace when disabled for guests Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 15/16] KVM: arm64: Hide S1PIE registers " Marc Zyngier
2024-09-03 15:38 ` [PATCH v2 16/16] KVM: arm64: Rely on visibility to let PIR*_ELx/TCR2_ELx UNDEF Marc Zyngier
2024-09-03 15:58   ` Mark Brown

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240905153734.GA4157679@e124191.cambridge.arm.com \
    --to=joey.gouly@arm.com \
    --cc=alexandru.elisei@arm.com \
    --cc=broonie@kernel.org \
    --cc=james.morse@arm.com \
    --cc=kvm@vger.kernel.org \
    --cc=kvmarm@lists.linux.dev \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=maz@kernel.org \
    --cc=oliver.upton@linux.dev \
    --cc=suzuki.poulose@arm.com \
    --cc=yuzenghui@huawei.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox