[kvm-unit-tests PATCH v11 0/8] riscv: add SBI SSE extension tests

[kvm-unit-tests PATCH v11 0/8] riscv: add SBI SSE extension tests

[Clément Léger]

This series adds tests for SBI SSE extension as well as needed
infrastructure for SSE support. It also adds test specific asm-offsets
generation to use custom OFFSET and DEFINE from the test directory.

These tests can be run using an OpenSBI version that implements latest
specifications modification [1]

Link: https://github.com/rivosinc/opensbi/tree/dev/cleger/sse [1]

---

V11:
 - Use mask inside sbi_impl_opensbi_mk_version()
 - Mask the SBI version with a new mask
 - Use assert inside sbi_get_impl_id/version()
 - Remove sbi_check_impl()
 - Increase completion timeout as events failed completing under 1000
   micros when system is loaded.

V10:
 - Use && instead of || for timeout handling
 - Add SBI patches which introduce function to get implementer ID and
   version as well as implementer ID defines.
 - Skip injection tests in OpenSBI < v1.6

V9:
 - Use __ASSEMBLER__ instead of __ASSEMBLY__
 - Remove extra spaces
 - Use assert to check global event in
   sse_global_event_set_current_hart()
 - Tabulate SSE events names table
 - Use sbi_sse_register() instead of sbi_sse_register_raw() in error
   testing
 - Move a report_pass() out of error path
 - Rework all injection tests with better error handling
 - Use an env var for sse event completion timeout
 - Add timeout for some potentially infinite while() loops

V8:
 - Short circuit current event tests if failure happens
 - Remove SSE from all report strings
 - Indent .prio field
 - Add cpu_relax()/smp_rmb() where needed
 - Add timeout for global event ENABLED state check
 - Added BIT(32) aliases tests for attribute/event_id.

V7:
 - Test ids/attributes/attributes count > 32 bits
 - Rename all SSE function to sbi_sse_*
 - Use event_id instead of event/evt
 - Factorize read/write test
 - Use virt_to_phys() for attributes read/write.
 - Extensively use sbiret_report_error()
 - Change check function return values to bool.
 - Added assert for stack size to be below or equal to PAGE_SIZE
 - Use en env variable for the maximum hart ID
 - Check that individual read from attributes matches the multiple
   attributes read.
 - Added multiple attributes write at once
 - Used READ_ONCE/WRITE_ONCE
 - Inject all local event at once rather than looping fopr each core.
 - Split test_arg for local_dispatch test so that all CPUs can run at
   once.
 - Move SSE entry and generic code to lib/riscv for other tests
 - Fix unmask/mask state checking

V6:
 - Add missing $(generated-file) dependencies for "-deps" objects
 - Split SSE entry from sbi-asm.S to sse-asm.S and all SSE core functions
   since it will be useful for other tests as well (dbltrp).

V5:
 - Update event ranges based on latest spec
 - Rename asm-offset-test.c to sbi-asm-offset.c

V4:
 - Fix typo sbi_ext_ss_fid -> sbi_ext_sse_fid
 - Add proper asm-offset generation for tests
 - Move SSE specific file from lib/riscv to riscv/

V3:
 - Add -deps variable for test specific dependencies
 - Fix formatting errors/typo in sbi.h
 - Add missing double trap event
 - Alphabetize sbi-sse.c includes
 - Fix a6 content after unmasking event
 - Add SSE HART_MASK/UNMASK test
 - Use mv instead of move
 - move sbi_check_sse() definition in sbi.c
 - Remove sbi_sse test from unitests.cfg

V2:
 - Rebased on origin/master and integrate it into sbi.c tests

Clément Léger (8):
  kbuild: Allow multiple asm-offsets file to be generated
  riscv: Set .aux.o files as .PRECIOUS
  riscv: Use asm-offsets to generate SBI_EXT_HSM values
  lib: riscv: Add functions for version checking
  lib: riscv: Add functions to get implementer ID and version
  riscv: lib: Add SBI SSE extension definitions
  lib: riscv: Add SBI SSE support
  riscv: sbi: Add SSE extension tests

 scripts/asm-offsets.mak |   22 +-
 riscv/Makefile          |    5 +-
 lib/riscv/asm/csr.h     |    1 +
 lib/riscv/asm/sbi.h     |  177 +++++-
 lib/riscv/sbi-sse-asm.S |  102 ++++
 lib/riscv/asm-offsets.c |    9 +
 lib/riscv/sbi.c         |  105 +++-
 riscv/sbi-tests.h       |    1 +
 riscv/sbi-asm.S         |    6 +-
 riscv/sbi-asm-offsets.c |   11 +
 riscv/sbi-sse.c         | 1278 +++++++++++++++++++++++++++++++++++++++
 riscv/sbi.c             |    2 +
 riscv/.gitignore        |    1 +
 13 files changed, 1707 insertions(+), 13 deletions(-)
 create mode 100644 lib/riscv/sbi-sse-asm.S
 create mode 100644 riscv/sbi-asm-offsets.c
 create mode 100644 riscv/sbi-sse.c
 create mode 100644 riscv/.gitignore

-- 
2.47.2

[kvm-unit-tests PATCH v11 1/8] kbuild: Allow multiple asm-offsets file to be generated

[Clément Léger]

In order to allow multiple asm-offsets files to generated the include
guard need to be different between these file. Add a asm_offset_name
makefile macro to obtain an uppercase name matching the original asm
offsets file.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Andrew Jones <andrew.jones@linux.dev>
---
 scripts/asm-offsets.mak | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/scripts/asm-offsets.mak b/scripts/asm-offsets.mak
index 7b64162d..a5fdbf5d 100644
--- a/scripts/asm-offsets.mak
+++ b/scripts/asm-offsets.mak
@@ -15,10 +15,14 @@ define sed-y
 	s:->::; p;}'
 endef
 
+define asm_offset_name
+	$(shell echo $(notdir $(1)) | tr [:lower:]- [:upper:]_)
+endef
+
 define make_asm_offsets
 	(set -e; \
-	 echo "#ifndef __ASM_OFFSETS_H__"; \
-	 echo "#define __ASM_OFFSETS_H__"; \
+	 echo "#ifndef __$(strip $(asm_offset_name))_H__"; \
+	 echo "#define __$(strip $(asm_offset_name))_H__"; \
 	 echo "/*"; \
 	 echo " * Generated file. DO NOT MODIFY."; \
 	 echo " *"; \
@@ -29,12 +33,16 @@ define make_asm_offsets
 	 echo "#endif" ) > $@
 endef
 
-$(asm-offsets:.h=.s): $(asm-offsets:.h=.c)
-	$(CC) $(CFLAGS) -fverbose-asm -S -o $@ $<
+define gen_asm_offsets_rules
+$(1).s: $(1).c
+	$(CC) $(CFLAGS) -fverbose-asm -S -o $$@ $$<
+
+$(1).h: $(1).s
+	$$(call make_asm_offsets,$(1))
+	cp -f $$@ lib/generated/
+endef
 
-$(asm-offsets): $(asm-offsets:.h=.s)
-	$(call make_asm_offsets)
-	cp -f $(asm-offsets) lib/generated/
+$(foreach o,$(asm-offsets),$(eval $(call gen_asm_offsets_rules, $(o:.h=))))
 
 OBJDIRS += lib/generated
 
-- 
2.47.2

[kvm-unit-tests PATCH v11 2/8] riscv: Set .aux.o files as .PRECIOUS

[Clément Léger]

When compiling, we need to keep .aux.o file or they will be removed
after the compilation which leads to dependent files to be recompiled.
Set these files as .PRECIOUS to keep them.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Andrew Jones <andrew.jones@linux.dev>
---
 riscv/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/riscv/Makefile b/riscv/Makefile
index 52718f3f..ae9cf02a 100644
--- a/riscv/Makefile
+++ b/riscv/Makefile
@@ -90,6 +90,7 @@ CFLAGS += -I $(SRCDIR)/lib -I $(SRCDIR)/lib/libfdt -I lib -I $(SRCDIR)/riscv
 asm-offsets = lib/riscv/asm-offsets.h
 include $(SRCDIR)/scripts/asm-offsets.mak
 
+.PRECIOUS: %.aux.o
 %.aux.o: $(SRCDIR)/lib/auxinfo.c
 	$(CC) $(CFLAGS) -c -o $@ $< \
 		-DPROGNAME=\"$(notdir $(@:.aux.o=.$(exe)))\" -DAUXFLAGS=$(AUXFLAGS)
-- 
2.47.2

[kvm-unit-tests PATCH v11 3/8] riscv: Use asm-offsets to generate SBI_EXT_HSM values

[Clément Léger]

Replace hardcoded values with generated ones using sbi-asm-offset. This
allows to directly use ASM_SBI_EXT_HSM and ASM_SBI_EXT_HSM_STOP in
assembly.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Andrew Jones <andrew.jones@linux.dev>
---
 riscv/Makefile          |  2 +-
 riscv/sbi-asm.S         |  6 ++++--
 riscv/sbi-asm-offsets.c | 11 +++++++++++
 riscv/.gitignore        |  1 +
 4 files changed, 17 insertions(+), 3 deletions(-)
 create mode 100644 riscv/sbi-asm-offsets.c
 create mode 100644 riscv/.gitignore

diff --git a/riscv/Makefile b/riscv/Makefile
index ae9cf02a..02d2ac39 100644
--- a/riscv/Makefile
+++ b/riscv/Makefile
@@ -87,7 +87,7 @@ CFLAGS += -ffreestanding
 CFLAGS += -O2
 CFLAGS += -I $(SRCDIR)/lib -I $(SRCDIR)/lib/libfdt -I lib -I $(SRCDIR)/riscv
 
-asm-offsets = lib/riscv/asm-offsets.h
+asm-offsets = lib/riscv/asm-offsets.h riscv/sbi-asm-offsets.h
 include $(SRCDIR)/scripts/asm-offsets.mak
 
 .PRECIOUS: %.aux.o
diff --git a/riscv/sbi-asm.S b/riscv/sbi-asm.S
index f4185496..51f46efd 100644
--- a/riscv/sbi-asm.S
+++ b/riscv/sbi-asm.S
@@ -6,6 +6,8 @@
  */
 #include <asm/asm.h>
 #include <asm/csr.h>
+#include <asm/asm-offsets.h>
+#include <generated/sbi-asm-offsets.h>
 
 #include "sbi-tests.h"
 
@@ -57,8 +59,8 @@ sbi_hsm_check:
 7:	lb	t0, 0(t1)
 	pause
 	beqz	t0, 7b
-	li	a7, 0x48534d	/* SBI_EXT_HSM */
-	li	a6, 1		/* SBI_EXT_HSM_HART_STOP */
+	li	a7, ASM_SBI_EXT_HSM
+	li	a6, ASM_SBI_EXT_HSM_HART_STOP
 	ecall
 8:	pause
 	j	8b
diff --git a/riscv/sbi-asm-offsets.c b/riscv/sbi-asm-offsets.c
new file mode 100644
index 00000000..bd37b6a2
--- /dev/null
+++ b/riscv/sbi-asm-offsets.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <kbuild.h>
+#include <asm/sbi.h>
+
+int main(void)
+{
+	DEFINE(ASM_SBI_EXT_HSM, SBI_EXT_HSM);
+	DEFINE(ASM_SBI_EXT_HSM_HART_STOP, SBI_EXT_HSM_HART_STOP);
+
+	return 0;
+}
diff --git a/riscv/.gitignore b/riscv/.gitignore
new file mode 100644
index 00000000..0a8c5a36
--- /dev/null
+++ b/riscv/.gitignore
@@ -0,0 +1 @@
+/*-asm-offsets.[hs]
-- 
2.47.2

Re: [kvm-unit-tests PATCH v11 3/8] riscv: Use asm-offsets to generate SBI_EXT_HSM values

[Andrew Jones]

On Mon, Mar 17, 2025 at 05:46:48PM +0100, Clément Léger wrote:
> Replace hardcoded values with generated ones using sbi-asm-offset. This
> allows to directly use ASM_SBI_EXT_HSM and ASM_SBI_EXT_HSM_STOP in
> assembly.
> 
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> Reviewed-by: Andrew Jones <andrew.jones@linux.dev>
> ---
>  riscv/Makefile          |  2 +-
>  riscv/sbi-asm.S         |  6 ++++--
>  riscv/sbi-asm-offsets.c | 11 +++++++++++
>  riscv/.gitignore        |  1 +
>  4 files changed, 17 insertions(+), 3 deletions(-)
>  create mode 100644 riscv/sbi-asm-offsets.c
>  create mode 100644 riscv/.gitignore
> 
> diff --git a/riscv/Makefile b/riscv/Makefile
> index ae9cf02a..02d2ac39 100644
> --- a/riscv/Makefile
> +++ b/riscv/Makefile
> @@ -87,7 +87,7 @@ CFLAGS += -ffreestanding
>  CFLAGS += -O2
>  CFLAGS += -I $(SRCDIR)/lib -I $(SRCDIR)/lib/libfdt -I lib -I $(SRCDIR)/riscv
>  
> -asm-offsets = lib/riscv/asm-offsets.h
> +asm-offsets = lib/riscv/asm-offsets.h riscv/sbi-asm-offsets.h
>  include $(SRCDIR)/scripts/asm-offsets.mak
>  
>  .PRECIOUS: %.aux.o
> diff --git a/riscv/sbi-asm.S b/riscv/sbi-asm.S
> index f4185496..51f46efd 100644
> --- a/riscv/sbi-asm.S
> +++ b/riscv/sbi-asm.S
> @@ -6,6 +6,8 @@
>   */
>  #include <asm/asm.h>
>  #include <asm/csr.h>
> +#include <asm/asm-offsets.h>
> +#include <generated/sbi-asm-offsets.h>

Doing this causes sbi-asm.o to depend on generated files, so I had to add
the change below to the Makefile in order for 'make -j' to work.

Thanks,
drew


diff --git a/riscv/Makefile b/riscv/Makefile
index 02d2ac392f11..e4dba6772377 100644
--- a/riscv/Makefile
+++ b/riscv/Makefile
@@ -19,6 +19,8 @@ all: $(tests)

 $(TEST_DIR)/sbi-deps = $(TEST_DIR)/sbi-asm.o $(TEST_DIR)/sbi-fwft.o

+all_deps += $($(TEST_DIR)/sbi-deps)
+
 # When built for EFI sieve needs extra memory, run with e.g. '-m 256' on QEMU
 $(TEST_DIR)/sieve.$(exe): AUXFLAGS = 0x1

@@ -134,7 +136,7 @@ else
 endif

 generated-files = $(asm-offsets)
-$(tests:.$(exe)=.o) $(cstart.o) $(cflatobjs): $(generated-files)
+$(tests:.$(exe)=.o) $(cstart.o) $(cflatobjs) $(all_deps): $(generated-files)

 arch_clean: asm_offsets_clean
        $(RM) $(TEST_DIR)/*.{o,flat,elf,so,efi,debug} \

>  
>  #include "sbi-tests.h"
>  
> @@ -57,8 +59,8 @@ sbi_hsm_check:
>  7:	lb	t0, 0(t1)
>  	pause
>  	beqz	t0, 7b
> -	li	a7, 0x48534d	/* SBI_EXT_HSM */
> -	li	a6, 1		/* SBI_EXT_HSM_HART_STOP */
> +	li	a7, ASM_SBI_EXT_HSM
> +	li	a6, ASM_SBI_EXT_HSM_HART_STOP
>  	ecall
>  8:	pause
>  	j	8b
> diff --git a/riscv/sbi-asm-offsets.c b/riscv/sbi-asm-offsets.c
> new file mode 100644
> index 00000000..bd37b6a2
> --- /dev/null
> +++ b/riscv/sbi-asm-offsets.c
> @@ -0,0 +1,11 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +#include <kbuild.h>
> +#include <asm/sbi.h>
> +
> +int main(void)
> +{
> +	DEFINE(ASM_SBI_EXT_HSM, SBI_EXT_HSM);
> +	DEFINE(ASM_SBI_EXT_HSM_HART_STOP, SBI_EXT_HSM_HART_STOP);
> +
> +	return 0;
> +}
> diff --git a/riscv/.gitignore b/riscv/.gitignore
> new file mode 100644
> index 00000000..0a8c5a36
> --- /dev/null
> +++ b/riscv/.gitignore
> @@ -0,0 +1 @@
> +/*-asm-offsets.[hs]
> -- 
> 2.47.2
> 

[kvm-unit-tests PATCH v11 4/8] lib: riscv: Add functions for version checking

[Clément Léger]

Version checking was done using some custom hardcoded values, backport a
few SBI function and defines from Linux to do that cleanly.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 lib/riscv/asm/sbi.h | 15 +++++++++++++++
 lib/riscv/sbi.c     |  9 +++++++--
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h
index 2f4d91ef..ee9d6e50 100644
--- a/lib/riscv/asm/sbi.h
+++ b/lib/riscv/asm/sbi.h
@@ -18,6 +18,13 @@
 #define SBI_ERR_IO			-13
 #define SBI_ERR_DENIED_LOCKED		-14
 
+/* SBI spec version fields */
+#define SBI_SPEC_VERSION_MAJOR_SHIFT	24
+#define SBI_SPEC_VERSION_MAJOR_MASK	0x7f
+#define SBI_SPEC_VERSION_MINOR_MASK	0xffffff
+#define SBI_SPEC_VERSION_MASK		((SBI_SPEC_VERSION_MAJOR_MASK << SBI_SPEC_VERSION_MAJOR_SHIFT) | \
+					SBI_SPEC_VERSION_MINOR_MASK)
+
 #ifndef __ASSEMBLER__
 #include <cpumask.h>
 
@@ -110,6 +117,13 @@ struct sbiret {
 	long value;
 };
 
+/* Make SBI version */
+static inline unsigned long sbi_mk_version(unsigned long major, unsigned long minor)
+{
+	return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << SBI_SPEC_VERSION_MAJOR_SHIFT)
+		| (minor & SBI_SPEC_VERSION_MINOR_MASK);
+}
+
 struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
 			unsigned long arg1, unsigned long arg2,
 			unsigned long arg3, unsigned long arg4,
@@ -124,6 +138,7 @@ struct sbiret sbi_send_ipi_cpu(int cpu);
 struct sbiret sbi_send_ipi_cpumask(const cpumask_t *mask);
 struct sbiret sbi_send_ipi_broadcast(void);
 struct sbiret sbi_set_timer(unsigned long stime_value);
+struct sbiret sbi_get_spec_version(void);
 long sbi_probe(int ext);
 
 #endif /* !__ASSEMBLER__ */
diff --git a/lib/riscv/sbi.c b/lib/riscv/sbi.c
index 02dd338c..9d4eb541 100644
--- a/lib/riscv/sbi.c
+++ b/lib/riscv/sbi.c
@@ -107,12 +107,17 @@ struct sbiret sbi_set_timer(unsigned long stime_value)
 	return sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0, 0, 0, 0, 0);
 }
 
+struct sbiret sbi_get_spec_version(void)
+{
+	return sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0, 0, 0, 0, 0, 0);
+}
+
 long sbi_probe(int ext)
 {
 	struct sbiret ret;
 
-	ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0, 0, 0, 0, 0, 0);
-	assert(!ret.error && (ret.value & 0x7ffffffful) >= 2);
+	ret = sbi_get_spec_version();
+	assert(!ret.error && (ret.value & SBI_SPEC_VERSION_MASK) >= sbi_mk_version(0, 2));
 
 	ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, ext, 0, 0, 0, 0, 0);
 	assert(!ret.error);
-- 
2.47.2

Re: [kvm-unit-tests PATCH v11 4/8] lib: riscv: Add functions for version checking

[Andrew Jones]

On Mon, Mar 17, 2025 at 05:46:49PM +0100, Clément Léger wrote:
> Version checking was done using some custom hardcoded values, backport a
> few SBI function and defines from Linux to do that cleanly.
> 
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> ---
>  lib/riscv/asm/sbi.h | 15 +++++++++++++++
>  lib/riscv/sbi.c     |  9 +++++++--
>  2 files changed, 22 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h
> index 2f4d91ef..ee9d6e50 100644
> --- a/lib/riscv/asm/sbi.h
> +++ b/lib/riscv/asm/sbi.h
> @@ -18,6 +18,13 @@
>  #define SBI_ERR_IO			-13
>  #define SBI_ERR_DENIED_LOCKED		-14
>  
> +/* SBI spec version fields */
> +#define SBI_SPEC_VERSION_MAJOR_SHIFT	24
> +#define SBI_SPEC_VERSION_MAJOR_MASK	0x7f
> +#define SBI_SPEC_VERSION_MINOR_MASK	0xffffff
> +#define SBI_SPEC_VERSION_MASK		((SBI_SPEC_VERSION_MAJOR_MASK << SBI_SPEC_VERSION_MAJOR_SHIFT) | \
> +					SBI_SPEC_VERSION_MINOR_MASK)
                                       ^ needs one more space
> +
>  #ifndef __ASSEMBLER__
>  #include <cpumask.h>
>  
> @@ -110,6 +117,13 @@ struct sbiret {
>  	long value;
>  };
>  
> +/* Make SBI version */

Unnecessary comment, it's the same as the function name.

> +static inline unsigned long sbi_mk_version(unsigned long major, unsigned long minor)
> +{
> +	return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << SBI_SPEC_VERSION_MAJOR_SHIFT)
> +		| (minor & SBI_SPEC_VERSION_MINOR_MASK);
> +}
> +
>  struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
>  			unsigned long arg1, unsigned long arg2,
>  			unsigned long arg3, unsigned long arg4,
> @@ -124,6 +138,7 @@ struct sbiret sbi_send_ipi_cpu(int cpu);
>  struct sbiret sbi_send_ipi_cpumask(const cpumask_t *mask);
>  struct sbiret sbi_send_ipi_broadcast(void);
>  struct sbiret sbi_set_timer(unsigned long stime_value);
> +struct sbiret sbi_get_spec_version(void);
>  long sbi_probe(int ext);
>  
>  #endif /* !__ASSEMBLER__ */
> diff --git a/lib/riscv/sbi.c b/lib/riscv/sbi.c
> index 02dd338c..9d4eb541 100644
> --- a/lib/riscv/sbi.c
> +++ b/lib/riscv/sbi.c
> @@ -107,12 +107,17 @@ struct sbiret sbi_set_timer(unsigned long stime_value)
>  	return sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0, 0, 0, 0, 0);
>  }
>  
> +struct sbiret sbi_get_spec_version(void)
> +{
> +	return sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0, 0, 0, 0, 0, 0);
> +}
> +
>  long sbi_probe(int ext)
>  {
>  	struct sbiret ret;
>  
> -	ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0, 0, 0, 0, 0, 0);
> -	assert(!ret.error && (ret.value & 0x7ffffffful) >= 2);
> +	ret = sbi_get_spec_version();
> +	assert(!ret.error && (ret.value & SBI_SPEC_VERSION_MASK) >= sbi_mk_version(0, 2));
>  
>  	ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, ext, 0, 0, 0, 0, 0);
>  	assert(!ret.error);
> -- 
> 2.47.2
>

I fixed those two things up while applying.

Thanks,
drew

Re: [kvm-unit-tests PATCH v11 4/8] lib: riscv: Add functions for version checking

[Clément Léger]

On 19/03/2025 18:31, Andrew Jones wrote:
> On Mon, Mar 17, 2025 at 05:46:49PM +0100, Clément Léger wrote:
>> Version checking was done using some custom hardcoded values, backport a
>> few SBI function and defines from Linux to do that cleanly.
>>
>> Signed-off-by: Clément Léger <cleger@rivosinc.com>
>> ---
>>  lib/riscv/asm/sbi.h | 15 +++++++++++++++
>>  lib/riscv/sbi.c     |  9 +++++++--
>>  2 files changed, 22 insertions(+), 2 deletions(-)
>>
>> diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h
>> index 2f4d91ef..ee9d6e50 100644
>> --- a/lib/riscv/asm/sbi.h
>> +++ b/lib/riscv/asm/sbi.h
>> @@ -18,6 +18,13 @@
>>  #define SBI_ERR_IO			-13
>>  #define SBI_ERR_DENIED_LOCKED		-14
>>  
>> +/* SBI spec version fields */
>> +#define SBI_SPEC_VERSION_MAJOR_SHIFT	24
>> +#define SBI_SPEC_VERSION_MAJOR_MASK	0x7f
>> +#define SBI_SPEC_VERSION_MINOR_MASK	0xffffff
>> +#define SBI_SPEC_VERSION_MASK		((SBI_SPEC_VERSION_MAJOR_MASK << SBI_SPEC_VERSION_MAJOR_SHIFT) | \
>> +					SBI_SPEC_VERSION_MINOR_MASK)
>                                        ^ needs one more space
>> +
>>  #ifndef __ASSEMBLER__
>>  #include <cpumask.h>
>>  
>> @@ -110,6 +117,13 @@ struct sbiret {
>>  	long value;
>>  };
>>  
>> +/* Make SBI version */
> 
> Unnecessary comment, it's the same as the function name.

Yeah that's a copy/paste from Linux, didn't cleanup.

> 
>> +static inline unsigned long sbi_mk_version(unsigned long major, unsigned long minor)
>> +{
>> +	return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << SBI_SPEC_VERSION_MAJOR_SHIFT)
>> +		| (minor & SBI_SPEC_VERSION_MINOR_MASK);
>> +}
>> +
>>  struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
>>  			unsigned long arg1, unsigned long arg2,
>>  			unsigned long arg3, unsigned long arg4,
>> @@ -124,6 +138,7 @@ struct sbiret sbi_send_ipi_cpu(int cpu);
>>  struct sbiret sbi_send_ipi_cpumask(const cpumask_t *mask);
>>  struct sbiret sbi_send_ipi_broadcast(void);
>>  struct sbiret sbi_set_timer(unsigned long stime_value);
>> +struct sbiret sbi_get_spec_version(void);
>>  long sbi_probe(int ext);
>>  
>>  #endif /* !__ASSEMBLER__ */
>> diff --git a/lib/riscv/sbi.c b/lib/riscv/sbi.c
>> index 02dd338c..9d4eb541 100644
>> --- a/lib/riscv/sbi.c
>> +++ b/lib/riscv/sbi.c
>> @@ -107,12 +107,17 @@ struct sbiret sbi_set_timer(unsigned long stime_value)
>>  	return sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0, 0, 0, 0, 0);
>>  }
>>  
>> +struct sbiret sbi_get_spec_version(void)
>> +{
>> +	return sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0, 0, 0, 0, 0, 0);
>> +}
>> +
>>  long sbi_probe(int ext)
>>  {
>>  	struct sbiret ret;
>>  
>> -	ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0, 0, 0, 0, 0, 0);
>> -	assert(!ret.error && (ret.value & 0x7ffffffful) >= 2);
>> +	ret = sbi_get_spec_version();
>> +	assert(!ret.error && (ret.value & SBI_SPEC_VERSION_MASK) >= sbi_mk_version(0, 2));
>>  
>>  	ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, ext, 0, 0, 0, 0, 0);
>>  	assert(!ret.error);
>> -- 
>> 2.47.2
>>
> 
> I fixed those two things up while applying.

Thanks Andrew,

Clément

> 
> Thanks,
> drew

[kvm-unit-tests PATCH v11 5/8] lib: riscv: Add functions to get implementer ID and version

[Clément Léger]

These functions will be used by SSE tests to check for a specific OpenSBI
version.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 lib/riscv/asm/sbi.h | 20 ++++++++++++++++++++
 lib/riscv/sbi.c     | 20 ++++++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h
index ee9d6e50..90111628 100644
--- a/lib/riscv/asm/sbi.h
+++ b/lib/riscv/asm/sbi.h
@@ -18,6 +18,19 @@
 #define SBI_ERR_IO			-13
 #define SBI_ERR_DENIED_LOCKED		-14
 
+#define SBI_IMPL_BBL		0
+#define SBI_IMPL_OPENSBI	1
+#define SBI_IMPL_XVISOR		2
+#define SBI_IMPL_KVM		3
+#define SBI_IMPL_RUSTSBI	4
+#define SBI_IMPL_DIOSIX		5
+#define SBI_IMPL_COFFER		6
+#define SBI_IMPL_XEN		7
+#define SBI_IMPL_POLARFIRE_HSS	8
+#define SBI_IMPL_COREBOOT	9
+#define SBI_IMPL_OREBOOT	10
+#define SBI_IMPL_BHYVE		11
+
 /* SBI spec version fields */
 #define SBI_SPEC_VERSION_MAJOR_SHIFT	24
 #define SBI_SPEC_VERSION_MAJOR_MASK	0x7f
@@ -124,6 +137,11 @@ static inline unsigned long sbi_mk_version(unsigned long major, unsigned long mi
 		| (minor & SBI_SPEC_VERSION_MINOR_MASK);
 }
 
+static inline unsigned long sbi_impl_opensbi_mk_version(unsigned long major, unsigned long minor)
+{
+	return (((major & 0xffff) << 16) | (minor & 0xffff));
+}
+
 struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
 			unsigned long arg1, unsigned long arg2,
 			unsigned long arg3, unsigned long arg4,
@@ -139,6 +157,8 @@ struct sbiret sbi_send_ipi_cpumask(const cpumask_t *mask);
 struct sbiret sbi_send_ipi_broadcast(void);
 struct sbiret sbi_set_timer(unsigned long stime_value);
 struct sbiret sbi_get_spec_version(void);
+unsigned long sbi_get_imp_version(void);
+unsigned long sbi_get_imp_id(void);
 long sbi_probe(int ext);
 
 #endif /* !__ASSEMBLER__ */
diff --git a/lib/riscv/sbi.c b/lib/riscv/sbi.c
index 9d4eb541..ab032e3e 100644
--- a/lib/riscv/sbi.c
+++ b/lib/riscv/sbi.c
@@ -107,6 +107,26 @@ struct sbiret sbi_set_timer(unsigned long stime_value)
 	return sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0, 0, 0, 0, 0);
 }
 
+unsigned long sbi_get_imp_version(void)
+{
+	struct sbiret ret;
+
+	ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_VERSION, 0, 0, 0, 0, 0, 0);
+	assert(!ret.error);
+
+	return ret.value;
+}
+
+unsigned long sbi_get_imp_id(void)
+{
+	struct sbiret ret;
+
+	ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID, 0, 0, 0, 0, 0, 0);
+	assert(!ret.error);
+
+	return ret.value;
+}
+
 struct sbiret sbi_get_spec_version(void)
 {
 	return sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0, 0, 0, 0, 0, 0);
-- 
2.47.2

Re: [kvm-unit-tests PATCH v11 5/8] lib: riscv: Add functions to get implementer ID and version

[Andrew Jones]

On Mon, Mar 17, 2025 at 05:46:50PM +0100, Clément Léger wrote:
> These functions will be used by SSE tests to check for a specific OpenSBI
> version.
> 
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> ---
>  lib/riscv/asm/sbi.h | 20 ++++++++++++++++++++
>  lib/riscv/sbi.c     | 20 ++++++++++++++++++++
>  2 files changed, 40 insertions(+)
> 
> diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h
> index ee9d6e50..90111628 100644
> --- a/lib/riscv/asm/sbi.h
> +++ b/lib/riscv/asm/sbi.h
> @@ -18,6 +18,19 @@
>  #define SBI_ERR_IO			-13
>  #define SBI_ERR_DENIED_LOCKED		-14
>  
> +#define SBI_IMPL_BBL		0
> +#define SBI_IMPL_OPENSBI	1
> +#define SBI_IMPL_XVISOR		2
> +#define SBI_IMPL_KVM		3
> +#define SBI_IMPL_RUSTSBI	4
> +#define SBI_IMPL_DIOSIX		5
> +#define SBI_IMPL_COFFER		6
> +#define SBI_IMPL_XEN		7
> +#define SBI_IMPL_POLARFIRE_HSS	8
> +#define SBI_IMPL_COREBOOT	9
> +#define SBI_IMPL_OREBOOT	10
> +#define SBI_IMPL_BHYVE		11
> +
>  /* SBI spec version fields */
>  #define SBI_SPEC_VERSION_MAJOR_SHIFT	24
>  #define SBI_SPEC_VERSION_MAJOR_MASK	0x7f
> @@ -124,6 +137,11 @@ static inline unsigned long sbi_mk_version(unsigned long major, unsigned long mi
>  		| (minor & SBI_SPEC_VERSION_MINOR_MASK);
>  }
>  
> +static inline unsigned long sbi_impl_opensbi_mk_version(unsigned long major, unsigned long minor)
> +{
> +	return (((major & 0xffff) << 16) | (minor & 0xffff));
> +}
> +
>  struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
>  			unsigned long arg1, unsigned long arg2,
>  			unsigned long arg3, unsigned long arg4,
> @@ -139,6 +157,8 @@ struct sbiret sbi_send_ipi_cpumask(const cpumask_t *mask);
>  struct sbiret sbi_send_ipi_broadcast(void);
>  struct sbiret sbi_set_timer(unsigned long stime_value);
>  struct sbiret sbi_get_spec_version(void);
> +unsigned long sbi_get_imp_version(void);
> +unsigned long sbi_get_imp_id(void);
>  long sbi_probe(int ext);
>  
>  #endif /* !__ASSEMBLER__ */
> diff --git a/lib/riscv/sbi.c b/lib/riscv/sbi.c
> index 9d4eb541..ab032e3e 100644
> --- a/lib/riscv/sbi.c
> +++ b/lib/riscv/sbi.c
> @@ -107,6 +107,26 @@ struct sbiret sbi_set_timer(unsigned long stime_value)
>  	return sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0, 0, 0, 0, 0);
>  }
>  
> +unsigned long sbi_get_imp_version(void)
> +{
> +	struct sbiret ret;
> +
> +	ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_VERSION, 0, 0, 0, 0, 0, 0);
> +	assert(!ret.error);
> +
> +	return ret.value;
> +}
> +
> +unsigned long sbi_get_imp_id(void)
> +{
> +	struct sbiret ret;
> +
> +	ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID, 0, 0, 0, 0, 0, 0);
> +	assert(!ret.error);
> +
> +	return ret.value;
> +}
> +
>  struct sbiret sbi_get_spec_version(void)
>  {
>  	return sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0, 0, 0, 0, 0, 0);
> -- 
> 2.47.2
>

LGTM

Thanks,
drew

[kvm-unit-tests PATCH v11 6/8] riscv: lib: Add SBI SSE extension definitions

[Clément Léger]

Add SBI SSE extension definitions in sbi.h

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Andrew Jones <andrew.jones@linux.dev>
---
 lib/riscv/asm/sbi.h | 106 +++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 105 insertions(+), 1 deletion(-)

diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h
index 90111628..887a4cd4 100644
--- a/lib/riscv/asm/sbi.h
+++ b/lib/riscv/asm/sbi.h
@@ -50,6 +50,7 @@ enum sbi_ext_id {
 	SBI_EXT_DBCN = 0x4442434E,
 	SBI_EXT_SUSP = 0x53555350,
 	SBI_EXT_FWFT = 0x46574654,
+	SBI_EXT_SSE = 0x535345,
 };
 
 enum sbi_ext_base_fid {
@@ -98,7 +99,6 @@ enum sbi_ext_dbcn_fid {
 	SBI_EXT_DBCN_CONSOLE_WRITE_BYTE,
 };
 
-
 enum sbi_ext_fwft_fid {
 	SBI_EXT_FWFT_SET = 0,
 	SBI_EXT_FWFT_GET,
@@ -125,6 +125,110 @@ enum sbi_ext_fwft_fid {
 
 #define SBI_FWFT_SET_FLAG_LOCK			BIT(0)
 
+enum sbi_ext_sse_fid {
+	SBI_EXT_SSE_READ_ATTRS = 0,
+	SBI_EXT_SSE_WRITE_ATTRS,
+	SBI_EXT_SSE_REGISTER,
+	SBI_EXT_SSE_UNREGISTER,
+	SBI_EXT_SSE_ENABLE,
+	SBI_EXT_SSE_DISABLE,
+	SBI_EXT_SSE_COMPLETE,
+	SBI_EXT_SSE_INJECT,
+	SBI_EXT_SSE_HART_UNMASK,
+	SBI_EXT_SSE_HART_MASK,
+};
+
+/* SBI SSE Event Attributes. */
+enum sbi_sse_attr_id {
+	SBI_SSE_ATTR_STATUS		= 0x00000000,
+	SBI_SSE_ATTR_PRIORITY		= 0x00000001,
+	SBI_SSE_ATTR_CONFIG		= 0x00000002,
+	SBI_SSE_ATTR_PREFERRED_HART	= 0x00000003,
+	SBI_SSE_ATTR_ENTRY_PC		= 0x00000004,
+	SBI_SSE_ATTR_ENTRY_ARG		= 0x00000005,
+	SBI_SSE_ATTR_INTERRUPTED_SEPC	= 0x00000006,
+	SBI_SSE_ATTR_INTERRUPTED_FLAGS	= 0x00000007,
+	SBI_SSE_ATTR_INTERRUPTED_A6	= 0x00000008,
+	SBI_SSE_ATTR_INTERRUPTED_A7	= 0x00000009,
+};
+
+#define SBI_SSE_ATTR_STATUS_STATE_OFFSET	0
+#define SBI_SSE_ATTR_STATUS_STATE_MASK		0x3
+#define SBI_SSE_ATTR_STATUS_PENDING_OFFSET	2
+#define SBI_SSE_ATTR_STATUS_INJECT_OFFSET	3
+
+#define SBI_SSE_ATTR_CONFIG_ONESHOT		BIT(0)
+
+#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SPP	BIT(0)
+#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SPIE	BIT(1)
+#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_HSTATUS_SPV	BIT(2)
+#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_HSTATUS_SPVP	BIT(3)
+#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SPELP	BIT(4)
+#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT	BIT(5)
+
+enum sbi_sse_state {
+	SBI_SSE_STATE_UNUSED		= 0,
+	SBI_SSE_STATE_REGISTERED	= 1,
+	SBI_SSE_STATE_ENABLED		= 2,
+	SBI_SSE_STATE_RUNNING		= 3,
+};
+
+/* SBI SSE Event IDs. */
+/* Range 0x00000000 - 0x0000ffff */
+#define SBI_SSE_EVENT_LOCAL_HIGH_PRIO_RAS	0x00000000
+#define SBI_SSE_EVENT_LOCAL_DOUBLE_TRAP		0x00000001
+#define SBI_SSE_EVENT_LOCAL_RESERVED_0_START	0x00000002
+#define SBI_SSE_EVENT_LOCAL_RESERVED_0_END	0x00003fff
+#define SBI_SSE_EVENT_LOCAL_PLAT_0_START	0x00004000
+#define SBI_SSE_EVENT_LOCAL_PLAT_0_END		0x00007fff
+
+#define SBI_SSE_EVENT_GLOBAL_HIGH_PRIO_RAS	0x00008000
+#define SBI_SSE_EVENT_GLOBAL_RESERVED_0_START	0x00008001
+#define SBI_SSE_EVENT_GLOBAL_RESERVED_0_END	0x0000bfff
+#define SBI_SSE_EVENT_GLOBAL_PLAT_0_START	0x0000c000
+#define SBI_SSE_EVENT_GLOBAL_PLAT_0_END		0x0000ffff
+
+/* Range 0x00010000 - 0x0001ffff */
+#define SBI_SSE_EVENT_LOCAL_PMU_OVERFLOW	0x00010000
+#define SBI_SSE_EVENT_LOCAL_RESERVED_1_START	0x00010001
+#define SBI_SSE_EVENT_LOCAL_RESERVED_1_END	0x00013fff
+#define SBI_SSE_EVENT_LOCAL_PLAT_1_START	0x00014000
+#define SBI_SSE_EVENT_LOCAL_PLAT_1_END		0x00017fff
+
+#define SBI_SSE_EVENT_GLOBAL_RESERVED_1_START	0x00018000
+#define SBI_SSE_EVENT_GLOBAL_RESERVED_1_END	0x0001bfff
+#define SBI_SSE_EVENT_GLOBAL_PLAT_1_START	0x0001c000
+#define SBI_SSE_EVENT_GLOBAL_PLAT_1_END		0x0001ffff
+
+/* Range 0x00100000 - 0x0010ffff */
+#define SBI_SSE_EVENT_LOCAL_LOW_PRIO_RAS	0x00100000
+#define SBI_SSE_EVENT_LOCAL_RESERVED_2_START	0x00100001
+#define SBI_SSE_EVENT_LOCAL_RESERVED_2_END	0x00103fff
+#define SBI_SSE_EVENT_LOCAL_PLAT_2_START	0x00104000
+#define SBI_SSE_EVENT_LOCAL_PLAT_2_END		0x00107fff
+
+#define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS	0x00108000
+#define SBI_SSE_EVENT_GLOBAL_RESERVED_2_START	0x00108001
+#define SBI_SSE_EVENT_GLOBAL_RESERVED_2_END	0x0010bfff
+#define SBI_SSE_EVENT_GLOBAL_PLAT_2_START	0x0010c000
+#define SBI_SSE_EVENT_GLOBAL_PLAT_2_END		0x0010ffff
+
+/* Range 0xffff0000 - 0xffffffff */
+#define SBI_SSE_EVENT_LOCAL_SOFTWARE		0xffff0000
+#define SBI_SSE_EVENT_LOCAL_RESERVED_3_START	0xffff0001
+#define SBI_SSE_EVENT_LOCAL_RESERVED_3_END	0xffff3fff
+#define SBI_SSE_EVENT_LOCAL_PLAT_3_START	0xffff4000
+#define SBI_SSE_EVENT_LOCAL_PLAT_3_END		0xffff7fff
+
+#define SBI_SSE_EVENT_GLOBAL_SOFTWARE		0xffff8000
+#define SBI_SSE_EVENT_GLOBAL_RESERVED_3_START	0xffff8001
+#define SBI_SSE_EVENT_GLOBAL_RESERVED_3_END	0xffffbfff
+#define SBI_SSE_EVENT_GLOBAL_PLAT_3_START	0xffffc000
+#define SBI_SSE_EVENT_GLOBAL_PLAT_3_END		0xffffffff
+
+#define SBI_SSE_EVENT_PLATFORM_BIT		BIT(14)
+#define SBI_SSE_EVENT_GLOBAL_BIT		BIT(15)
+
 struct sbiret {
 	long error;
 	long value;
-- 
2.47.2

[kvm-unit-tests PATCH v11 7/8] lib: riscv: Add SBI SSE support

[Clément Léger]

Add support for registering and handling SSE events. This will be used
for sbi tests as well as upcoming double trap tests.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Andrew Jones <andrew.jones@linux.dev>
---
 riscv/Makefile          |   1 +
 lib/riscv/asm/csr.h     |   1 +
 lib/riscv/asm/sbi.h     |  36 ++++++++++++++
 lib/riscv/sbi-sse-asm.S | 102 ++++++++++++++++++++++++++++++++++++++++
 lib/riscv/asm-offsets.c |   9 ++++
 lib/riscv/sbi.c         |  76 ++++++++++++++++++++++++++++++
 6 files changed, 225 insertions(+)
 create mode 100644 lib/riscv/sbi-sse-asm.S

diff --git a/riscv/Makefile b/riscv/Makefile
index 02d2ac39..16fc125b 100644
--- a/riscv/Makefile
+++ b/riscv/Makefile
@@ -43,6 +43,7 @@ cflatobjs += lib/riscv/setup.o
 cflatobjs += lib/riscv/smp.o
 cflatobjs += lib/riscv/stack.o
 cflatobjs += lib/riscv/timer.o
+cflatobjs += lib/riscv/sbi-sse-asm.o
 ifeq ($(ARCH),riscv32)
 cflatobjs += lib/ldiv32.o
 endif
diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h
index c7fc87a9..3e4b5fca 100644
--- a/lib/riscv/asm/csr.h
+++ b/lib/riscv/asm/csr.h
@@ -17,6 +17,7 @@
 #define CSR_TIME		0xc01
 
 #define SR_SIE			_AC(0x00000002, UL)
+#define SR_SPP			_AC(0x00000100, UL)
 
 /* Exception cause high bit - is an interrupt if set */
 #define CAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h
index 887a4cd4..ad5f50de 100644
--- a/lib/riscv/asm/sbi.h
+++ b/lib/riscv/asm/sbi.h
@@ -265,5 +265,41 @@ unsigned long sbi_get_imp_version(void);
 unsigned long sbi_get_imp_id(void);
 long sbi_probe(int ext);
 
+typedef void (*sbi_sse_handler_fn)(void *data, struct pt_regs *regs, unsigned int hartid);
+
+struct sbi_sse_handler_arg {
+	unsigned long reg_tmp;
+	sbi_sse_handler_fn handler;
+	void *handler_data;
+	void *stack;
+};
+
+extern void sbi_sse_entry(void);
+
+static inline bool sbi_sse_event_is_global(uint32_t event_id)
+{
+	return !!(event_id & SBI_SSE_EVENT_GLOBAL_BIT);
+}
+
+struct sbiret sbi_sse_read_attrs_raw(unsigned long event_id, unsigned long base_attr_id,
+				     unsigned long attr_count, unsigned long phys_lo,
+				     unsigned long phys_hi);
+struct sbiret sbi_sse_read_attrs(unsigned long event_id, unsigned long base_attr_id,
+				 unsigned long attr_count, unsigned long *values);
+struct sbiret sbi_sse_write_attrs_raw(unsigned long event_id, unsigned long base_attr_id,
+				      unsigned long attr_count, unsigned long phys_lo,
+				      unsigned long phys_hi);
+struct sbiret sbi_sse_write_attrs(unsigned long event_id, unsigned long base_attr_id,
+				  unsigned long attr_count, unsigned long *values);
+struct sbiret sbi_sse_register_raw(unsigned long event_id, unsigned long entry_pc,
+				   unsigned long entry_arg);
+struct sbiret sbi_sse_register(unsigned long event_id, struct sbi_sse_handler_arg *arg);
+struct sbiret sbi_sse_unregister(unsigned long event_id);
+struct sbiret sbi_sse_enable(unsigned long event_id);
+struct sbiret sbi_sse_disable(unsigned long event_id);
+struct sbiret sbi_sse_hart_mask(void);
+struct sbiret sbi_sse_hart_unmask(void);
+struct sbiret sbi_sse_inject(unsigned long event_id, unsigned long hart_id);
+
 #endif /* !__ASSEMBLER__ */
 #endif /* _ASMRISCV_SBI_H_ */
diff --git a/lib/riscv/sbi-sse-asm.S b/lib/riscv/sbi-sse-asm.S
new file mode 100644
index 00000000..b9e951f5
--- /dev/null
+++ b/lib/riscv/sbi-sse-asm.S
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * RISC-V SSE events entry point.
+ *
+ * Copyright (C) 2025, Rivos Inc., Clément Léger <cleger@rivosinc.com>
+ */
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/csr.h>
+#include <generated/sbi-asm-offsets.h>
+
+.section .text
+.global sbi_sse_entry
+sbi_sse_entry:
+	/* Save stack temporarily */
+	REG_S	sp, SBI_SSE_REG_TMP(a7)
+	/* Set entry stack */
+	REG_L	sp, SBI_SSE_HANDLER_STACK(a7)
+
+	addi	sp, sp, -(PT_SIZE)
+	REG_S	ra, PT_RA(sp)
+	REG_S	s0, PT_S0(sp)
+	REG_S	s1, PT_S1(sp)
+	REG_S	s2, PT_S2(sp)
+	REG_S	s3, PT_S3(sp)
+	REG_S	s4, PT_S4(sp)
+	REG_S	s5, PT_S5(sp)
+	REG_S	s6, PT_S6(sp)
+	REG_S	s7, PT_S7(sp)
+	REG_S	s8, PT_S8(sp)
+	REG_S	s9, PT_S9(sp)
+	REG_S	s10, PT_S10(sp)
+	REG_S	s11, PT_S11(sp)
+	REG_S	tp, PT_TP(sp)
+	REG_S	t0, PT_T0(sp)
+	REG_S	t1, PT_T1(sp)
+	REG_S	t2, PT_T2(sp)
+	REG_S	t3, PT_T3(sp)
+	REG_S	t4, PT_T4(sp)
+	REG_S	t5, PT_T5(sp)
+	REG_S	t6, PT_T6(sp)
+	REG_S	gp, PT_GP(sp)
+	REG_S	a0, PT_A0(sp)
+	REG_S	a1, PT_A1(sp)
+	REG_S	a2, PT_A2(sp)
+	REG_S	a3, PT_A3(sp)
+	REG_S	a4, PT_A4(sp)
+	REG_S	a5, PT_A5(sp)
+	csrr	a1, CSR_SEPC
+	REG_S	a1, PT_EPC(sp)
+	csrr	a2, CSR_SSTATUS
+	REG_S	a2, PT_STATUS(sp)
+
+	REG_L	a0, SBI_SSE_REG_TMP(a7)
+	REG_S	a0, PT_SP(sp)
+
+	REG_L	t0, SBI_SSE_HANDLER(a7)
+	REG_L	a0, SBI_SSE_HANDLER_DATA(a7)
+	mv	a1, sp
+	mv	a2, a6
+	jalr	t0
+
+	REG_L	a1, PT_EPC(sp)
+	REG_L	a2, PT_STATUS(sp)
+	csrw	CSR_SEPC, a1
+	csrw	CSR_SSTATUS, a2
+
+	REG_L	ra, PT_RA(sp)
+	REG_L	s0, PT_S0(sp)
+	REG_L	s1, PT_S1(sp)
+	REG_L	s2, PT_S2(sp)
+	REG_L	s3, PT_S3(sp)
+	REG_L	s4, PT_S4(sp)
+	REG_L	s5, PT_S5(sp)
+	REG_L	s6, PT_S6(sp)
+	REG_L	s7, PT_S7(sp)
+	REG_L	s8, PT_S8(sp)
+	REG_L	s9, PT_S9(sp)
+	REG_L	s10, PT_S10(sp)
+	REG_L	s11, PT_S11(sp)
+	REG_L	tp, PT_TP(sp)
+	REG_L	t0, PT_T0(sp)
+	REG_L	t1, PT_T1(sp)
+	REG_L	t2, PT_T2(sp)
+	REG_L	t3, PT_T3(sp)
+	REG_L	t4, PT_T4(sp)
+	REG_L	t5, PT_T5(sp)
+	REG_L	t6, PT_T6(sp)
+	REG_L	gp, PT_GP(sp)
+	REG_L	a0, PT_A0(sp)
+	REG_L	a1, PT_A1(sp)
+	REG_L	a2, PT_A2(sp)
+	REG_L	a3, PT_A3(sp)
+	REG_L	a4, PT_A4(sp)
+	REG_L	a5, PT_A5(sp)
+
+	REG_L	sp, PT_SP(sp)
+
+	li	a7, ASM_SBI_EXT_SSE
+	li	a6, ASM_SBI_EXT_SSE_COMPLETE
+	ecall
+
diff --git a/lib/riscv/asm-offsets.c b/lib/riscv/asm-offsets.c
index 6c511c14..a96c6e97 100644
--- a/lib/riscv/asm-offsets.c
+++ b/lib/riscv/asm-offsets.c
@@ -3,6 +3,7 @@
 #include <elf.h>
 #include <asm/processor.h>
 #include <asm/ptrace.h>
+#include <asm/sbi.h>
 #include <asm/smp.h>
 
 int main(void)
@@ -63,5 +64,13 @@ int main(void)
 	OFFSET(THREAD_INFO_HARTID, thread_info, hartid);
 	DEFINE(THREAD_INFO_SIZE, sizeof(struct thread_info));
 
+	DEFINE(ASM_SBI_EXT_SSE, SBI_EXT_SSE);
+	DEFINE(ASM_SBI_EXT_SSE_COMPLETE, SBI_EXT_SSE_COMPLETE);
+
+	OFFSET(SBI_SSE_REG_TMP, sbi_sse_handler_arg, reg_tmp);
+	OFFSET(SBI_SSE_HANDLER, sbi_sse_handler_arg, handler);
+	OFFSET(SBI_SSE_HANDLER_DATA, sbi_sse_handler_arg, handler_data);
+	OFFSET(SBI_SSE_HANDLER_STACK, sbi_sse_handler_arg, stack);
+
 	return 0;
 }
diff --git a/lib/riscv/sbi.c b/lib/riscv/sbi.c
index ab032e3e..53d25489 100644
--- a/lib/riscv/sbi.c
+++ b/lib/riscv/sbi.c
@@ -2,6 +2,7 @@
 #include <libcflat.h>
 #include <cpumask.h>
 #include <limits.h>
+#include <asm/io.h>
 #include <asm/sbi.h>
 #include <asm/setup.h>
 
@@ -31,6 +32,81 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
 	return ret;
 }
 
+struct sbiret sbi_sse_read_attrs_raw(unsigned long event_id, unsigned long base_attr_id,
+				     unsigned long attr_count, unsigned long phys_lo,
+				     unsigned long phys_hi)
+{
+	return sbi_ecall(SBI_EXT_SSE, SBI_EXT_SSE_READ_ATTRS, event_id, base_attr_id, attr_count,
+			 phys_lo, phys_hi, 0);
+}
+
+struct sbiret sbi_sse_read_attrs(unsigned long event_id, unsigned long base_attr_id,
+				 unsigned long attr_count, unsigned long *values)
+{
+	phys_addr_t p = virt_to_phys(values);
+
+	return sbi_sse_read_attrs_raw(event_id, base_attr_id, attr_count, lower_32_bits(p),
+				      upper_32_bits(p));
+}
+
+struct sbiret sbi_sse_write_attrs_raw(unsigned long event_id, unsigned long base_attr_id,
+				      unsigned long attr_count, unsigned long phys_lo,
+				      unsigned long phys_hi)
+{
+	return sbi_ecall(SBI_EXT_SSE, SBI_EXT_SSE_WRITE_ATTRS, event_id, base_attr_id, attr_count,
+			 phys_lo, phys_hi, 0);
+}
+
+struct sbiret sbi_sse_write_attrs(unsigned long event_id, unsigned long base_attr_id,
+				  unsigned long attr_count, unsigned long *values)
+{
+	phys_addr_t p = virt_to_phys(values);
+
+	return sbi_sse_write_attrs_raw(event_id, base_attr_id, attr_count, lower_32_bits(p),
+				       upper_32_bits(p));
+}
+
+struct sbiret sbi_sse_register_raw(unsigned long event_id, unsigned long entry_pc,
+				   unsigned long entry_arg)
+{
+	return sbi_ecall(SBI_EXT_SSE, SBI_EXT_SSE_REGISTER, event_id, entry_pc, entry_arg, 0, 0, 0);
+}
+
+struct sbiret sbi_sse_register(unsigned long event_id, struct sbi_sse_handler_arg *arg)
+{
+	return sbi_sse_register_raw(event_id, (unsigned long)sbi_sse_entry, (unsigned long)arg);
+}
+
+struct sbiret sbi_sse_unregister(unsigned long event_id)
+{
+	return sbi_ecall(SBI_EXT_SSE, SBI_EXT_SSE_UNREGISTER, event_id, 0, 0, 0, 0, 0);
+}
+
+struct sbiret sbi_sse_enable(unsigned long event_id)
+{
+	return sbi_ecall(SBI_EXT_SSE, SBI_EXT_SSE_ENABLE, event_id, 0, 0, 0, 0, 0);
+}
+
+struct sbiret sbi_sse_disable(unsigned long event_id)
+{
+	return sbi_ecall(SBI_EXT_SSE, SBI_EXT_SSE_DISABLE, event_id, 0, 0, 0, 0, 0);
+}
+
+struct sbiret sbi_sse_hart_mask(void)
+{
+	return sbi_ecall(SBI_EXT_SSE, SBI_EXT_SSE_HART_MASK, 0, 0, 0, 0, 0, 0);
+}
+
+struct sbiret sbi_sse_hart_unmask(void)
+{
+	return sbi_ecall(SBI_EXT_SSE, SBI_EXT_SSE_HART_UNMASK, 0, 0, 0, 0, 0, 0);
+}
+
+struct sbiret sbi_sse_inject(unsigned long event_id, unsigned long hart_id)
+{
+	return sbi_ecall(SBI_EXT_SSE, SBI_EXT_SSE_INJECT, event_id, hart_id, 0, 0, 0, 0);
+}
+
 void sbi_shutdown(void)
 {
 	sbi_ecall(SBI_EXT_SRST, 0, 0, 0, 0, 0, 0, 0);
-- 
2.47.2

[kvm-unit-tests PATCH v11 8/8] riscv: sbi: Add SSE extension tests

[Clément Léger]

Add SBI SSE extension tests for the following features:
- Test attributes errors (invalid values, RO, etc)
- Registration errors
- Simple events (register, enable, inject)
- Events with different priorities
- Global events dispatch on different harts
- Local events on all harts
- Hart mask/unmask events

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Andrew Jones <andrew.jones@linux.dev>
---
 riscv/Makefile    |    1 +
 riscv/sbi-tests.h |    1 +
 riscv/sbi-sse.c   | 1278 +++++++++++++++++++++++++++++++++++++++++++++
 riscv/sbi.c       |    2 +
 4 files changed, 1282 insertions(+)
 create mode 100644 riscv/sbi-sse.c

diff --git a/riscv/Makefile b/riscv/Makefile
index 16fc125b..4fe2f1bb 100644
--- a/riscv/Makefile
+++ b/riscv/Makefile
@@ -18,6 +18,7 @@ tests += $(TEST_DIR)/sieve.$(exe)
 all: $(tests)
 
 $(TEST_DIR)/sbi-deps = $(TEST_DIR)/sbi-asm.o $(TEST_DIR)/sbi-fwft.o
+$(TEST_DIR)/sbi-deps += $(TEST_DIR)/sbi-sse.o
 
 # When built for EFI sieve needs extra memory, run with e.g. '-m 256' on QEMU
 $(TEST_DIR)/sieve.$(exe): AUXFLAGS = 0x1
diff --git a/riscv/sbi-tests.h b/riscv/sbi-tests.h
index b081464d..a71da809 100644
--- a/riscv/sbi-tests.h
+++ b/riscv/sbi-tests.h
@@ -71,6 +71,7 @@
 	sbiret_report(ret, expected_error, expected_value, "check sbi.error and sbi.value")
 
 void sbi_bad_fid(int ext);
+void check_sse(void);
 
 #endif /* __ASSEMBLER__ */
 #endif /* _RISCV_SBI_TESTS_H_ */
diff --git a/riscv/sbi-sse.c b/riscv/sbi-sse.c
new file mode 100644
index 00000000..a31c84c3
--- /dev/null
+++ b/riscv/sbi-sse.c
@@ -0,0 +1,1278 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * SBI SSE testsuite
+ *
+ * Copyright (C) 2025, Rivos Inc., Clément Léger <cleger@rivosinc.com>
+ */
+#include <alloc.h>
+#include <alloc_page.h>
+#include <bitops.h>
+#include <cpumask.h>
+#include <libcflat.h>
+#include <on-cpus.h>
+#include <stdlib.h>
+
+#include <asm/barrier.h>
+#include <asm/delay.h>
+#include <asm/io.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+#include <asm/sbi.h>
+#include <asm/setup.h>
+#include <asm/timer.h>
+
+#include "sbi-tests.h"
+
+#define SSE_STACK_SIZE	PAGE_SIZE
+
+struct sse_event_info {
+	uint32_t event_id;
+	const char *name;
+	bool can_inject;
+};
+
+static struct sse_event_info sse_event_infos[] = {
+	{
+		.event_id = SBI_SSE_EVENT_LOCAL_HIGH_PRIO_RAS,
+		.name = "local_high_prio_ras",
+	},
+	{
+		.event_id = SBI_SSE_EVENT_LOCAL_DOUBLE_TRAP,
+		.name = "double_trap",
+	},
+	{
+		.event_id = SBI_SSE_EVENT_GLOBAL_HIGH_PRIO_RAS,
+		.name = "global_high_prio_ras",
+	},
+	{
+		.event_id = SBI_SSE_EVENT_LOCAL_PMU_OVERFLOW,
+		.name = "local_pmu_overflow",
+	},
+	{
+		.event_id = SBI_SSE_EVENT_LOCAL_LOW_PRIO_RAS,
+		.name = "local_low_prio_ras",
+	},
+	{
+		.event_id = SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS,
+		.name = "global_low_prio_ras",
+	},
+	{
+		.event_id = SBI_SSE_EVENT_LOCAL_SOFTWARE,
+		.name = "local_software",
+	},
+	{
+		.event_id = SBI_SSE_EVENT_GLOBAL_SOFTWARE,
+		.name = "global_software",
+	},
+};
+
+static const char *const attr_names[] = {
+	[SBI_SSE_ATTR_STATUS] =			"status",
+	[SBI_SSE_ATTR_PRIORITY] =		"priority",
+	[SBI_SSE_ATTR_CONFIG] =			"config",
+	[SBI_SSE_ATTR_PREFERRED_HART] =		"preferred_hart",
+	[SBI_SSE_ATTR_ENTRY_PC] =		"entry_pc",
+	[SBI_SSE_ATTR_ENTRY_ARG] =		"entry_arg",
+	[SBI_SSE_ATTR_INTERRUPTED_SEPC] =	"interrupted_sepc",
+	[SBI_SSE_ATTR_INTERRUPTED_FLAGS] =	"interrupted_flags",
+	[SBI_SSE_ATTR_INTERRUPTED_A6] =		"interrupted_a6",
+	[SBI_SSE_ATTR_INTERRUPTED_A7] =		"interrupted_a7",
+};
+
+static const unsigned long ro_attrs[] = {
+	SBI_SSE_ATTR_STATUS,
+	SBI_SSE_ATTR_ENTRY_PC,
+	SBI_SSE_ATTR_ENTRY_ARG,
+};
+
+static const unsigned long interrupted_attrs[] = {
+	SBI_SSE_ATTR_INTERRUPTED_SEPC,
+	SBI_SSE_ATTR_INTERRUPTED_FLAGS,
+	SBI_SSE_ATTR_INTERRUPTED_A6,
+	SBI_SSE_ATTR_INTERRUPTED_A7,
+};
+
+static const unsigned long interrupted_flags[] = {
+	SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SPP,
+	SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SPIE,
+	SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SPELP,
+	SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT,
+	SBI_SSE_ATTR_INTERRUPTED_FLAGS_HSTATUS_SPV,
+	SBI_SSE_ATTR_INTERRUPTED_FLAGS_HSTATUS_SPVP,
+};
+
+static struct sse_event_info *sse_event_get_info(uint32_t event_id)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(sse_event_infos); i++) {
+		if (sse_event_infos[i].event_id == event_id)
+			return &sse_event_infos[i];
+	}
+
+	assert_msg(false, "Invalid event id: %d", event_id);
+}
+
+static const char *sse_event_name(uint32_t event_id)
+{
+	return sse_event_get_info(event_id)->name;
+}
+
+static bool sse_event_can_inject(uint32_t event_id)
+{
+	return sse_event_get_info(event_id)->can_inject;
+}
+
+static struct sbiret sse_get_event_status_field(uint32_t event_id, unsigned long mask,
+						unsigned long shift, unsigned long *value)
+{
+	struct sbiret ret;
+	unsigned long status;
+
+	ret = sbi_sse_read_attrs(event_id, SBI_SSE_ATTR_STATUS, 1, &status);
+	if (ret.error) {
+		sbiret_report_error(&ret, SBI_SUCCESS, "Get event status");
+		return ret;
+	}
+
+	*value = (status & mask) >> shift;
+
+	return ret;
+}
+
+static struct sbiret sse_event_get_state(uint32_t event_id, enum sbi_sse_state *state)
+{
+	unsigned long status = 0;
+	struct sbiret ret;
+
+	ret = sse_get_event_status_field(event_id, SBI_SSE_ATTR_STATUS_STATE_MASK,
+					  SBI_SSE_ATTR_STATUS_STATE_OFFSET, &status);
+	*state = status;
+
+	return ret;
+}
+
+static unsigned long sse_global_event_set_current_hart(uint32_t event_id)
+{
+	struct sbiret ret;
+	unsigned long current_hart = current_thread_info()->hartid;
+
+	assert(sbi_sse_event_is_global(event_id));
+
+	ret = sbi_sse_write_attrs(event_id, SBI_SSE_ATTR_PREFERRED_HART, 1, &current_hart);
+	if (sbiret_report_error(&ret, SBI_SUCCESS, "Set preferred hart"))
+		return ret.error;
+
+	return 0;
+}
+
+static bool sse_check_state(uint32_t event_id, unsigned long expected_state)
+{
+	struct sbiret ret;
+	enum sbi_sse_state state;
+
+	ret = sse_event_get_state(event_id, &state);
+	if (ret.error)
+		return false;
+
+	return report(state == expected_state, "event status == %ld", expected_state);
+}
+
+static bool sse_event_pending(uint32_t event_id)
+{
+	bool pending = 0;
+
+	sse_get_event_status_field(event_id, BIT(SBI_SSE_ATTR_STATUS_PENDING_OFFSET),
+		SBI_SSE_ATTR_STATUS_PENDING_OFFSET, (unsigned long *)&pending);
+
+	return pending;
+}
+
+static void *sse_alloc_stack(void)
+{
+	/*
+	 * We assume that SSE_STACK_SIZE always fit in one page. This page will
+	 * always be decremented before storing anything on it in sse-entry.S.
+	 */
+	assert(SSE_STACK_SIZE <= PAGE_SIZE);
+
+	return (alloc_page() + SSE_STACK_SIZE);
+}
+
+static void sse_free_stack(void *stack)
+{
+	free_page(stack - SSE_STACK_SIZE);
+}
+
+static void sse_read_write_test(uint32_t event_id, unsigned long attr, unsigned long attr_count,
+				unsigned long *value, long expected_error, const char *str)
+{
+	struct sbiret ret;
+
+	ret = sbi_sse_read_attrs(event_id, attr, attr_count, value);
+	sbiret_report_error(&ret, expected_error, "Read %s error", str);
+
+	ret = sbi_sse_write_attrs(event_id, attr, attr_count, value);
+	sbiret_report_error(&ret, expected_error, "Write %s error", str);
+}
+
+#define ALL_ATTRS_COUNT	(SBI_SSE_ATTR_INTERRUPTED_A7 + 1)
+
+static void sse_test_attrs(uint32_t event_id)
+{
+	unsigned long value = 0;
+	struct sbiret ret;
+	void *ptr;
+	unsigned long values[ALL_ATTRS_COUNT];
+	unsigned int i;
+	const char *invalid_hart_str;
+	const char *attr_name;
+
+	report_prefix_push("attrs");
+
+	for (i = 0; i < ARRAY_SIZE(ro_attrs); i++) {
+		ret = sbi_sse_write_attrs(event_id, ro_attrs[i], 1, &value);
+		sbiret_report_error(&ret, SBI_ERR_DENIED, "RO attribute %s not writable",
+				    attr_names[ro_attrs[i]]);
+	}
+
+	ret = sbi_sse_read_attrs(event_id, SBI_SSE_ATTR_STATUS, ALL_ATTRS_COUNT, values);
+	sbiret_report_error(&ret, SBI_SUCCESS, "Read multiple attributes");
+
+	for (i = SBI_SSE_ATTR_STATUS; i <= SBI_SSE_ATTR_INTERRUPTED_A7; i++) {
+		ret = sbi_sse_read_attrs(event_id, i, 1, &value);
+		attr_name = attr_names[i];
+
+		sbiret_report_error(&ret, SBI_SUCCESS, "Read single attribute %s", attr_name);
+		if (values[i] != value)
+			report_fail("Attribute 0x%x single value read (0x%lx) differs from the one read with multiple attributes (0x%lx)",
+				    i, value, values[i]);
+		/*
+		 * Preferred hart reset value is defined by SBI vendor
+		 */
+		if (i != SBI_SSE_ATTR_PREFERRED_HART) {
+			/*
+			 * Specification states that injectable bit is implementation dependent
+			 * but other bits are zero-initialized.
+			 */
+			if (i == SBI_SSE_ATTR_STATUS)
+				value &= ~BIT(SBI_SSE_ATTR_STATUS_INJECT_OFFSET);
+			report(value == 0, "Attribute %s reset value is 0, found %lx", attr_name, value);
+		}
+	}
+
+#if __riscv_xlen > 32
+	value = BIT(32);
+	ret = sbi_sse_write_attrs(event_id, SBI_SSE_ATTR_PRIORITY, 1, &value);
+	sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM, "Write invalid prio > 0xFFFFFFFF error");
+#endif
+
+	value = ~SBI_SSE_ATTR_CONFIG_ONESHOT;
+	ret = sbi_sse_write_attrs(event_id, SBI_SSE_ATTR_CONFIG, 1, &value);
+	sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM, "Write invalid config value error");
+
+	if (sbi_sse_event_is_global(event_id)) {
+		invalid_hart_str = getenv("INVALID_HART_ID");
+		if (!invalid_hart_str)
+			value = 0xFFFFFFFFUL;
+		else
+			value = strtoul(invalid_hart_str, NULL, 0);
+
+		ret = sbi_sse_write_attrs(event_id, SBI_SSE_ATTR_PREFERRED_HART, 1, &value);
+		sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM, "Set invalid hart id error");
+	} else {
+		/* Set Hart on local event -> RO */
+		value = current_thread_info()->hartid;
+		ret = sbi_sse_write_attrs(event_id, SBI_SSE_ATTR_PREFERRED_HART, 1, &value);
+		sbiret_report_error(&ret, SBI_ERR_DENIED,
+				    "Set hart id on local event error");
+	}
+
+	/* Set/get flags, sepc, a6, a7 */
+	for (i = 0; i < ARRAY_SIZE(interrupted_attrs); i++) {
+		attr_name = attr_names[interrupted_attrs[i]];
+		ret = sbi_sse_read_attrs(event_id, interrupted_attrs[i], 1, &value);
+		sbiret_report_error(&ret, SBI_SUCCESS, "Get interrupted %s", attr_name);
+
+		value = ARRAY_SIZE(interrupted_attrs) - i;
+		ret = sbi_sse_write_attrs(event_id, interrupted_attrs[i], 1, &value);
+		sbiret_report_error(&ret, SBI_ERR_INVALID_STATE,
+				    "Set attribute %s invalid state error", attr_name);
+	}
+
+	sse_read_write_test(event_id, SBI_SSE_ATTR_STATUS, 0, &value, SBI_ERR_INVALID_PARAM,
+			    "attribute attr_count == 0");
+	sse_read_write_test(event_id, SBI_SSE_ATTR_INTERRUPTED_A7 + 1, 1, &value, SBI_ERR_BAD_RANGE,
+			    "invalid attribute");
+
+	/* Misaligned pointer address */
+	ptr = (void *)&value;
+	ptr += 1;
+	sse_read_write_test(event_id, SBI_SSE_ATTR_STATUS, 1, ptr, SBI_ERR_INVALID_ADDRESS,
+		"attribute with invalid address");
+
+	report_prefix_pop();
+}
+
+static void sse_test_register_error(uint32_t event_id)
+{
+	struct sbiret ret;
+
+	report_prefix_push("register");
+
+	ret = sbi_sse_unregister(event_id);
+	sbiret_report_error(&ret, SBI_ERR_INVALID_STATE, "unregister non-registered event");
+
+	ret = sbi_sse_register_raw(event_id, 0x1, 0);
+	sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM, "register misaligned entry");
+
+	ret = sbi_sse_register(event_id, NULL);
+	sbiret_report_error(&ret, SBI_SUCCESS, "register");
+	if (ret.error)
+		goto done;
+
+	ret = sbi_sse_register(event_id, NULL);
+	sbiret_report_error(&ret, SBI_ERR_INVALID_STATE, "register used event failure");
+
+	ret = sbi_sse_unregister(event_id);
+	sbiret_report_error(&ret, SBI_SUCCESS, "unregister");
+
+done:
+	report_prefix_pop();
+}
+
+struct sse_simple_test_arg {
+	bool done;
+	unsigned long expected_a6;
+	uint32_t event_id;
+};
+
+#if __riscv_xlen > 32
+
+struct alias_test_params {
+	unsigned long event_id;
+	unsigned long attr_id;
+	unsigned long attr_count;
+	const char *str;
+};
+
+static void test_alias(uint32_t event_id)
+{
+	struct alias_test_params *write, *read;
+	unsigned long write_value, read_value;
+	struct sbiret ret;
+	bool err = false;
+	int r, w;
+	struct alias_test_params params[] = {
+		{event_id, SBI_SSE_ATTR_INTERRUPTED_A6, 1, "non aliased"},
+		{BIT(32) + event_id, SBI_SSE_ATTR_INTERRUPTED_A6, 1, "aliased event_id"},
+		{event_id, BIT(32) + SBI_SSE_ATTR_INTERRUPTED_A6, 1, "aliased attr_id"},
+		{event_id, SBI_SSE_ATTR_INTERRUPTED_A6, BIT(32) + 1, "aliased attr_count"},
+	};
+
+	report_prefix_push("alias");
+	for (w = 0; w < ARRAY_SIZE(params); w++) {
+		write = &params[w];
+
+		write_value = 0xDEADBEEF + w;
+		ret = sbi_sse_write_attrs(write->event_id, write->attr_id, write->attr_count, &write_value);
+		if (ret.error)
+			sbiret_report_error(&ret, SBI_SUCCESS, "Write %s, event 0x%lx attr 0x%lx, attr count 0x%lx",
+					    write->str, write->event_id, write->attr_id, write->attr_count);
+
+		for (r = 0; r < ARRAY_SIZE(params); r++) {
+			read = &params[r];
+			read_value = 0;
+			ret = sbi_sse_read_attrs(read->event_id, read->attr_id, read->attr_count, &read_value);
+			if (ret.error)
+				sbiret_report_error(&ret, SBI_SUCCESS,
+						    "Read %s, event 0x%lx attr 0x%lx, attr count 0x%lx",
+						    read->str, read->event_id, read->attr_id, read->attr_count);
+
+			/* Do not spam output with a lot of reports */
+			if (write_value != read_value) {
+				err = true;
+				report_fail("Write %s, event 0x%lx attr 0x%lx, attr count 0x%lx value %lx =="
+					    "Read %s, event 0x%lx attr 0x%lx, attr count 0x%lx value %lx",
+					    write->str, write->event_id, write->attr_id,
+					    write->attr_count, write_value, read->str,
+					    read->event_id, read->attr_id, read->attr_count,
+					    read_value);
+			}
+		}
+	}
+
+	report(!err, "BIT(32) aliasing tests");
+	report_prefix_pop();
+}
+#endif
+
+static void sse_simple_handler(void *data, struct pt_regs *regs, unsigned int hartid)
+{
+	struct sse_simple_test_arg *arg = data;
+	int i;
+	struct sbiret ret;
+	const char *attr_name;
+	uint32_t event_id = READ_ONCE(arg->event_id), attr;
+	unsigned long value, prev_value, flags;
+	unsigned long interrupted_state[ARRAY_SIZE(interrupted_attrs)];
+	unsigned long modified_state[ARRAY_SIZE(interrupted_attrs)] = {4, 3, 2, 1};
+	unsigned long tmp_state[ARRAY_SIZE(interrupted_attrs)];
+
+	report((regs->status & SR_SPP) == SR_SPP, "Interrupted S-mode");
+	report(hartid == current_thread_info()->hartid, "Hartid correctly passed");
+	sse_check_state(event_id, SBI_SSE_STATE_RUNNING);
+	report(!sse_event_pending(event_id), "Event not pending");
+
+	/* Read full interrupted state */
+	ret = sbi_sse_read_attrs(event_id, SBI_SSE_ATTR_INTERRUPTED_SEPC,
+				 ARRAY_SIZE(interrupted_attrs), interrupted_state);
+	sbiret_report_error(&ret, SBI_SUCCESS, "Save full interrupted state from handler");
+
+	/* Write full modified state and read it */
+	ret = sbi_sse_write_attrs(event_id, SBI_SSE_ATTR_INTERRUPTED_SEPC,
+				  ARRAY_SIZE(modified_state), modified_state);
+	sbiret_report_error(&ret, SBI_SUCCESS,
+			    "Write full interrupted state from handler");
+
+	ret = sbi_sse_read_attrs(event_id, SBI_SSE_ATTR_INTERRUPTED_SEPC,
+				ARRAY_SIZE(tmp_state), tmp_state);
+	sbiret_report_error(&ret, SBI_SUCCESS, "Read full modified state from handler");
+
+	report(memcmp(tmp_state, modified_state, sizeof(modified_state)) == 0,
+	       "Full interrupted state successfully written");
+
+#if __riscv_xlen > 32
+	test_alias(event_id);
+#endif
+
+	/* Restore full saved state */
+	ret = sbi_sse_write_attrs(event_id, SBI_SSE_ATTR_INTERRUPTED_SEPC,
+				  ARRAY_SIZE(interrupted_attrs), interrupted_state);
+	sbiret_report_error(&ret, SBI_SUCCESS, "Full interrupted state restore from handler");
+
+	/* We test SBI_SSE_ATTR_INTERRUPTED_FLAGS below with specific flag values */
+	for (i = 0; i < ARRAY_SIZE(interrupted_attrs); i++) {
+		attr = interrupted_attrs[i];
+		if (attr == SBI_SSE_ATTR_INTERRUPTED_FLAGS)
+			continue;
+
+		attr_name = attr_names[attr];
+
+		ret = sbi_sse_read_attrs(event_id, attr, 1, &prev_value);
+		sbiret_report_error(&ret, SBI_SUCCESS, "Get attr %s", attr_name);
+
+		value = 0xDEADBEEF + i;
+		ret = sbi_sse_write_attrs(event_id, attr, 1, &value);
+		sbiret_report_error(&ret, SBI_SUCCESS, "Set attr %s", attr_name);
+
+		ret = sbi_sse_read_attrs(event_id, attr, 1, &value);
+		sbiret_report_error(&ret, SBI_SUCCESS, "Get attr %s", attr_name);
+		report(value == 0xDEADBEEF + i, "Get attr %s, value: 0x%lx", attr_name, value);
+
+		ret = sbi_sse_write_attrs(event_id, attr, 1, &prev_value);
+		sbiret_report_error(&ret, SBI_SUCCESS, "Restore attr %s value", attr_name);
+	}
+
+	/* Test all flags allowed for SBI_SSE_ATTR_INTERRUPTED_FLAGS */
+	attr = SBI_SSE_ATTR_INTERRUPTED_FLAGS;
+	ret = sbi_sse_read_attrs(event_id, attr, 1, &prev_value);
+	sbiret_report_error(&ret, SBI_SUCCESS, "Save interrupted flags");
+
+	for (i = 0; i < ARRAY_SIZE(interrupted_flags); i++) {
+		flags = interrupted_flags[i];
+		ret = sbi_sse_write_attrs(event_id, attr, 1, &flags);
+		sbiret_report_error(&ret, SBI_SUCCESS,
+				    "Set interrupted flags bit 0x%lx value", flags);
+		ret = sbi_sse_read_attrs(event_id, attr, 1, &value);
+		sbiret_report_error(&ret, SBI_SUCCESS, "Get interrupted flags after set");
+		report(value == flags, "interrupted flags modified value: 0x%lx", value);
+	}
+
+	/* Write invalid bit in flag register */
+	flags = SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT << 1;
+	ret = sbi_sse_write_attrs(event_id, attr, 1, &flags);
+	sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM, "Set invalid flags bit 0x%lx value error",
+			    flags);
+
+	flags = BIT(SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT + 1);
+	ret = sbi_sse_write_attrs(event_id, attr, 1, &flags);
+	sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM, "Set invalid flags bit 0x%lx value error",
+			    flags);
+
+	ret = sbi_sse_write_attrs(event_id, attr, 1, &prev_value);
+	sbiret_report_error(&ret, SBI_SUCCESS, "Restore interrupted flags");
+
+	/* Try to change HARTID/Priority while running */
+	if (sbi_sse_event_is_global(event_id)) {
+		value = current_thread_info()->hartid;
+		ret = sbi_sse_write_attrs(event_id, SBI_SSE_ATTR_PREFERRED_HART, 1, &value);
+		sbiret_report_error(&ret, SBI_ERR_INVALID_STATE, "Set hart id while running error");
+	}
+
+	value = 0;
+	ret = sbi_sse_write_attrs(event_id, SBI_SSE_ATTR_PRIORITY, 1, &value);
+	sbiret_report_error(&ret, SBI_ERR_INVALID_STATE, "Set priority while running error");
+
+	value = READ_ONCE(arg->expected_a6);
+	report(interrupted_state[2] == value, "Interrupted state a6, expected 0x%lx, got 0x%lx",
+	       value, interrupted_state[2]);
+
+	report(interrupted_state[3] == SBI_EXT_SSE,
+	       "Interrupted state a7, expected 0x%x, got 0x%lx", SBI_EXT_SSE,
+	       interrupted_state[3]);
+
+	WRITE_ONCE(arg->done, true);
+}
+
+static void sse_test_inject_simple(uint32_t event_id)
+{
+	unsigned long value, error;
+	struct sbiret ret;
+	enum sbi_sse_state state = SBI_SSE_STATE_UNUSED;
+	struct sse_simple_test_arg test_arg = {.event_id = event_id};
+	struct sbi_sse_handler_arg args = {
+		.handler = sse_simple_handler,
+		.handler_data = (void *)&test_arg,
+		.stack = sse_alloc_stack(),
+	};
+
+	report_prefix_push("simple");
+
+	if (!sse_check_state(event_id, SBI_SSE_STATE_UNUSED))
+		goto cleanup;
+
+	ret = sbi_sse_register(event_id, &args);
+	if (!sbiret_report_error(&ret, SBI_SUCCESS, "register"))
+		goto cleanup;
+
+	state = SBI_SSE_STATE_REGISTERED;
+
+	if (!sse_check_state(event_id, SBI_SSE_STATE_REGISTERED))
+		goto cleanup;
+
+	if (sbi_sse_event_is_global(event_id)) {
+		/* Be sure global events are targeting the current hart */
+		error = sse_global_event_set_current_hart(event_id);
+		if (error)
+			goto cleanup;
+	}
+
+	ret = sbi_sse_enable(event_id);
+	if (!sbiret_report_error(&ret, SBI_SUCCESS, "enable"))
+		goto cleanup;
+
+	state = SBI_SSE_STATE_ENABLED;
+	if (!sse_check_state(event_id, SBI_SSE_STATE_ENABLED))
+		goto cleanup;
+
+	ret = sbi_sse_hart_mask();
+	if (!sbiret_report_error(&ret, SBI_SUCCESS, "hart mask"))
+		goto cleanup;
+
+	ret = sbi_sse_inject(event_id, current_thread_info()->hartid);
+	if (!sbiret_report_error(&ret, SBI_SUCCESS, "injection masked")) {
+		sbi_sse_hart_unmask();
+		goto cleanup;
+	}
+
+	report(READ_ONCE(test_arg.done) == 0, "event masked not handled");
+
+	/*
+	 * When unmasking the SSE events, we expect it to be injected
+	 * immediately so a6 should be SBI_EXT_SBI_SSE_HART_UNMASK
+	 */
+	WRITE_ONCE(test_arg.expected_a6, SBI_EXT_SSE_HART_UNMASK);
+	ret = sbi_sse_hart_unmask();
+	if (!sbiret_report_error(&ret, SBI_SUCCESS, "hart unmask"))
+		goto cleanup;
+
+	report(READ_ONCE(test_arg.done) == 1, "event unmasked handled");
+	WRITE_ONCE(test_arg.done, 0);
+	WRITE_ONCE(test_arg.expected_a6, SBI_EXT_SSE_INJECT);
+
+	/* Set as oneshot and verify it is disabled */
+	ret = sbi_sse_disable(event_id);
+	if (!sbiret_report_error(&ret, SBI_SUCCESS, "Disable event")) {
+		/* Nothing we can really do here, event can not be disabled */
+		goto cleanup;
+	}
+	state = SBI_SSE_STATE_REGISTERED;
+
+	value = SBI_SSE_ATTR_CONFIG_ONESHOT;
+	ret = sbi_sse_write_attrs(event_id, SBI_SSE_ATTR_CONFIG, 1, &value);
+	if (!sbiret_report_error(&ret, SBI_SUCCESS, "Set event attribute as ONESHOT"))
+		goto cleanup;
+
+	ret = sbi_sse_enable(event_id);
+	if (!sbiret_report_error(&ret, SBI_SUCCESS, "Enable event"))
+		goto cleanup;
+	state = SBI_SSE_STATE_ENABLED;
+
+	ret = sbi_sse_inject(event_id, current_thread_info()->hartid);
+	if (!sbiret_report_error(&ret, SBI_SUCCESS, "second injection"))
+		goto cleanup;
+
+	report(READ_ONCE(test_arg.done) == 1, "event handled");
+	WRITE_ONCE(test_arg.done, 0);
+
+	if (!sse_check_state(event_id, SBI_SSE_STATE_REGISTERED))
+		goto cleanup;
+	state = SBI_SSE_STATE_REGISTERED;
+
+	/* Clear ONESHOT FLAG */
+	value = 0;
+	ret = sbi_sse_write_attrs(event_id, SBI_SSE_ATTR_CONFIG, 1, &value);
+	if (!sbiret_report_error(&ret, SBI_SUCCESS, "Clear CONFIG.ONESHOT flag"))
+		goto cleanup;
+
+	ret = sbi_sse_unregister(event_id);
+	if (!sbiret_report_error(&ret, SBI_SUCCESS, "unregister"))
+		goto cleanup;
+	state = SBI_SSE_STATE_UNUSED;
+
+	sse_check_state(event_id, SBI_SSE_STATE_UNUSED);
+
+cleanup:
+	switch (state) {
+	case SBI_SSE_STATE_ENABLED:
+		ret = sbi_sse_disable(event_id);
+		if (ret.error) {
+			sbiret_report_error(&ret, SBI_SUCCESS, "disable event 0x%x", event_id);
+			break;
+		}
+	case SBI_SSE_STATE_REGISTERED:
+		sbi_sse_unregister(event_id);
+		if (ret.error)
+			sbiret_report_error(&ret, SBI_SUCCESS, "unregister event 0x%x", event_id);
+	default:
+	}
+
+	sse_free_stack(args.stack);
+	report_prefix_pop();
+}
+
+struct sse_foreign_cpu_test_arg {
+	bool done;
+	unsigned int expected_cpu;
+	uint32_t event_id;
+};
+
+static void sse_foreign_cpu_handler(void *data, struct pt_regs *regs, unsigned int hartid)
+{
+	struct sse_foreign_cpu_test_arg *arg = data;
+	unsigned int expected_cpu;
+
+	/* For arg content to be visible */
+	smp_rmb();
+	expected_cpu = READ_ONCE(arg->expected_cpu);
+	report(expected_cpu == current_thread_info()->cpu,
+	       "Received event on CPU (%d), expected CPU (%d)", current_thread_info()->cpu,
+	       expected_cpu);
+
+	WRITE_ONCE(arg->done, true);
+	/* For arg update to be visible for other CPUs */
+	smp_wmb();
+}
+
+struct sse_local_per_cpu {
+	struct sbi_sse_handler_arg args;
+	struct sbiret ret;
+	struct sse_foreign_cpu_test_arg handler_arg;
+	enum sbi_sse_state state;
+};
+
+static void sse_register_enable_local(void *data)
+{
+	struct sbiret ret;
+	struct sse_local_per_cpu *cpu_args = data;
+	struct sse_local_per_cpu *cpu_arg = &cpu_args[current_thread_info()->cpu];
+	uint32_t event_id = cpu_arg->handler_arg.event_id;
+
+	ret = sbi_sse_register(event_id, &cpu_arg->args);
+	WRITE_ONCE(cpu_arg->ret, ret);
+	if (ret.error)
+		return;
+	cpu_arg->state = SBI_SSE_STATE_REGISTERED;
+
+	ret = sbi_sse_enable(event_id);
+	WRITE_ONCE(cpu_arg->ret, ret);
+	if (ret.error)
+		return;
+	cpu_arg->state = SBI_SSE_STATE_ENABLED;
+}
+
+static void sbi_sse_disable_unregister_local(void *data)
+{
+	struct sbiret ret;
+	struct sse_local_per_cpu *cpu_args = data;
+	struct sse_local_per_cpu *cpu_arg = &cpu_args[current_thread_info()->cpu];
+	uint32_t event_id = cpu_arg->handler_arg.event_id;
+
+	switch (cpu_arg->state) {
+	case SBI_SSE_STATE_ENABLED:
+		ret = sbi_sse_disable(event_id);
+		WRITE_ONCE(cpu_arg->ret, ret);
+		if (ret.error)
+			return;
+	case SBI_SSE_STATE_REGISTERED:
+		ret = sbi_sse_unregister(event_id);
+		WRITE_ONCE(cpu_arg->ret, ret);
+	default:
+	}
+}
+
+static uint64_t sse_event_get_complete_timeout(void)
+{
+	char *event_complete_timeout_str;
+	uint64_t timeout;
+
+	event_complete_timeout_str = getenv("SSE_EVENT_COMPLETE_TIMEOUT");
+	if (!event_complete_timeout_str)
+		timeout = 3000;
+	else
+		timeout = strtoul(event_complete_timeout_str, NULL, 0);
+
+	return timer_get_cycles() + usec_to_cycles(timeout);
+}
+
+static void sse_test_inject_local(uint32_t event_id)
+{
+	int cpu;
+	uint64_t timeout;
+	struct sbiret ret;
+	struct sse_local_per_cpu *cpu_args, *cpu_arg;
+	struct sse_foreign_cpu_test_arg *handler_arg;
+
+	cpu_args = calloc(NR_CPUS, sizeof(struct sbi_sse_handler_arg));
+
+	report_prefix_push("local_dispatch");
+	for_each_online_cpu(cpu) {
+		cpu_arg = &cpu_args[cpu];
+		cpu_arg->handler_arg.event_id = event_id;
+		cpu_arg->args.stack = sse_alloc_stack();
+		cpu_arg->args.handler = sse_foreign_cpu_handler;
+		cpu_arg->args.handler_data = (void *)&cpu_arg->handler_arg;
+		cpu_arg->state = SBI_SSE_STATE_UNUSED;
+	}
+
+	on_cpus(sse_register_enable_local, cpu_args);
+	for_each_online_cpu(cpu) {
+		cpu_arg = &cpu_args[cpu];
+		ret = cpu_arg->ret;
+		if (ret.error) {
+			report_fail("CPU failed to register/enable event: %ld", ret.error);
+			goto cleanup;
+		}
+
+		handler_arg = &cpu_arg->handler_arg;
+		WRITE_ONCE(handler_arg->expected_cpu, cpu);
+		/* For handler_arg content to be visible for other CPUs */
+		smp_wmb();
+		ret = sbi_sse_inject(event_id, cpus[cpu].hartid);
+		if (ret.error) {
+			report_fail("CPU failed to inject event: %ld", ret.error);
+			goto cleanup;
+		}
+	}
+
+	for_each_online_cpu(cpu) {
+		handler_arg = &cpu_args[cpu].handler_arg;
+		smp_rmb();
+
+		timeout = sse_event_get_complete_timeout();
+		while (!READ_ONCE(handler_arg->done) && timer_get_cycles() < timeout) {
+			/* For handler_arg update to be visible */
+			smp_rmb();
+			cpu_relax();
+		}
+		report(READ_ONCE(handler_arg->done), "Event handled");
+		WRITE_ONCE(handler_arg->done, false);
+	}
+
+cleanup:
+	on_cpus(sbi_sse_disable_unregister_local, cpu_args);
+	for_each_online_cpu(cpu) {
+		cpu_arg = &cpu_args[cpu];
+		ret = READ_ONCE(cpu_arg->ret);
+		if (ret.error)
+			report_fail("CPU failed to disable/unregister event: %ld", ret.error);
+	}
+
+	for_each_online_cpu(cpu) {
+		cpu_arg = &cpu_args[cpu];
+		sse_free_stack(cpu_arg->args.stack);
+	}
+
+	report_prefix_pop();
+}
+
+static void sse_test_inject_global_cpu(uint32_t event_id, unsigned int cpu,
+				       struct sse_foreign_cpu_test_arg *test_arg)
+{
+	unsigned long value;
+	struct sbiret ret;
+	uint64_t timeout;
+	enum sbi_sse_state state;
+
+	WRITE_ONCE(test_arg->expected_cpu, cpu);
+	/* For test_arg content to be visible for other CPUs */
+	smp_wmb();
+	value = cpu;
+	ret = sbi_sse_write_attrs(event_id, SBI_SSE_ATTR_PREFERRED_HART, 1, &value);
+	if (!sbiret_report_error(&ret, SBI_SUCCESS, "Set preferred hart"))
+		return;
+
+	ret = sbi_sse_enable(event_id);
+	if (!sbiret_report_error(&ret, SBI_SUCCESS, "Enable event"))
+		return;
+
+	ret = sbi_sse_inject(event_id, cpu);
+	if (!sbiret_report_error(&ret, SBI_SUCCESS, "Inject event"))
+		goto disable;
+
+	smp_rmb();
+	timeout = sse_event_get_complete_timeout();
+	while (!READ_ONCE(test_arg->done) && timer_get_cycles() < timeout) {
+		/* For shared test_arg structure */
+		smp_rmb();
+		cpu_relax();
+	}
+
+	report(READ_ONCE(test_arg->done), "event handler called");
+	WRITE_ONCE(test_arg->done, false);
+
+	timeout = sse_event_get_complete_timeout();
+	/* Wait for event to be back in ENABLED state */
+	do {
+		ret = sse_event_get_state(event_id, &state);
+		if (ret.error)
+			goto disable;
+		cpu_relax();
+	} while (state != SBI_SSE_STATE_ENABLED && timer_get_cycles() < timeout);
+
+	report(state == SBI_SSE_STATE_ENABLED, "Event in enabled state");
+
+disable:
+	ret = sbi_sse_disable(event_id);
+	sbiret_report_error(&ret, SBI_SUCCESS, "Disable event");
+}
+
+static void sse_test_inject_global(uint32_t event_id)
+{
+	struct sbiret ret;
+	unsigned int cpu;
+	struct sse_foreign_cpu_test_arg test_arg = {.event_id = event_id};
+	struct sbi_sse_handler_arg args = {
+		.handler = sse_foreign_cpu_handler,
+		.handler_data = (void *)&test_arg,
+		.stack = sse_alloc_stack(),
+	};
+
+	report_prefix_push("global_dispatch");
+
+	ret = sbi_sse_register(event_id, &args);
+	if (!sbiret_report_error(&ret, SBI_SUCCESS, "Register event"))
+		goto err;
+
+	for_each_online_cpu(cpu)
+		sse_test_inject_global_cpu(event_id, cpu, &test_arg);
+
+	ret = sbi_sse_unregister(event_id);
+	sbiret_report_error(&ret, SBI_SUCCESS, "Unregister event");
+
+err:
+	sse_free_stack(args.stack);
+	report_prefix_pop();
+}
+
+struct priority_test_arg {
+	uint32_t event_id;
+	bool called;
+	u32 prio;
+	enum sbi_sse_state state; /* Used for error handling */
+	struct priority_test_arg *next_event_arg;
+	void (*check_func)(struct priority_test_arg *arg);
+};
+
+static void sse_hi_priority_test_handler(void *arg, struct pt_regs *regs,
+					 unsigned int hartid)
+{
+	struct priority_test_arg *targ = arg;
+	struct priority_test_arg *next = targ->next_event_arg;
+
+	targ->called = true;
+	if (next) {
+		sbi_sse_inject(next->event_id, current_thread_info()->hartid);
+
+		report(!sse_event_pending(next->event_id), "Higher priority event is not pending");
+		report(next->called, "Higher priority event was handled");
+	}
+}
+
+static void sse_low_priority_test_handler(void *arg, struct pt_regs *regs,
+					  unsigned int hartid)
+{
+	struct priority_test_arg *targ = arg;
+	struct priority_test_arg *next = targ->next_event_arg;
+
+	targ->called = true;
+
+	if (next) {
+		sbi_sse_inject(next->event_id, current_thread_info()->hartid);
+
+		report(sse_event_pending(next->event_id), "Lower priority event is pending");
+		report(!next->called, "Lower priority event %s was not handled before %s",
+		       sse_event_name(next->event_id), sse_event_name(targ->event_id));
+	}
+}
+
+static void sse_test_injection_priority_arg(struct priority_test_arg *in_args,
+					    unsigned int in_args_size,
+					    sbi_sse_handler_fn handler,
+					    const char *test_name)
+{
+	unsigned int i;
+	unsigned long value, uret;
+	struct sbiret ret;
+	uint32_t event_id;
+	struct priority_test_arg *arg;
+	unsigned int args_size = 0;
+	struct sbi_sse_handler_arg event_args[in_args_size];
+	struct priority_test_arg *args[in_args_size];
+	void *stack;
+	struct sbi_sse_handler_arg *event_arg;
+
+	report_prefix_push(test_name);
+
+	for (i = 0; i < in_args_size; i++) {
+		arg = &in_args[i];
+		arg->state = SBI_SSE_STATE_UNUSED;
+		event_id = arg->event_id;
+		if (!sse_event_can_inject(event_id))
+			continue;
+
+		args[args_size] = arg;
+		args_size++;
+		event_args->stack = 0;
+	}
+
+	if (!args_size) {
+		report_skip("No injectable events");
+		goto skip;
+	}
+
+	for (i = 0; i < args_size; i++) {
+		arg = args[i];
+		event_id = arg->event_id;
+		stack = sse_alloc_stack();
+
+		event_arg = &event_args[i];
+		event_arg->handler = handler;
+		event_arg->handler_data = (void *)arg;
+		event_arg->stack = stack;
+
+		if (i < (args_size - 1))
+			arg->next_event_arg = args[i + 1];
+		else
+			arg->next_event_arg = NULL;
+
+		/* Be sure global events are targeting the current hart */
+		if (sbi_sse_event_is_global(event_id)) {
+			uret = sse_global_event_set_current_hart(event_id);
+			if (uret)
+				goto err;
+		}
+
+		ret = sbi_sse_register(event_id, event_arg);
+		if (ret.error) {
+			sbiret_report_error(&ret, SBI_SUCCESS, "register event %s",
+					    sse_event_name(event_id));
+			goto err;
+		}
+		arg->state = SBI_SSE_STATE_REGISTERED;
+
+		value = arg->prio;
+		ret = sbi_sse_write_attrs(event_id, SBI_SSE_ATTR_PRIORITY, 1, &value);
+		if (ret.error) {
+			sbiret_report_error(&ret, SBI_SUCCESS, "set event %s priority",
+					    sse_event_name(event_id));
+			goto err;
+		}
+		ret = sbi_sse_enable(event_id);
+		if (ret.error) {
+			sbiret_report_error(&ret, SBI_SUCCESS, "enable event %s",
+					    sse_event_name(event_id));
+			goto err;
+		}
+		arg->state = SBI_SSE_STATE_ENABLED;
+	}
+
+	/* Inject first event */
+	ret = sbi_sse_inject(args[0]->event_id, current_thread_info()->hartid);
+	sbiret_report_error(&ret, SBI_SUCCESS, "injection");
+
+	/* Check that all handlers have been called */
+	for (i = 0; i < args_size; i++)
+		report(arg->called, "Event %s handler called", sse_event_name(args[i]->event_id));
+
+err:
+	for (i = 0; i < args_size; i++) {
+		arg = args[i];
+		event_id = arg->event_id;
+
+		switch (arg->state) {
+		case SBI_SSE_STATE_ENABLED:
+			ret = sbi_sse_disable(event_id);
+			if (ret.error) {
+				sbiret_report_error(&ret, SBI_SUCCESS, "disable event 0x%x",
+						    event_id);
+				break;
+			}
+		case SBI_SSE_STATE_REGISTERED:
+			sbi_sse_unregister(event_id);
+			if (ret.error)
+				sbiret_report_error(&ret, SBI_SUCCESS, "unregister event 0x%x",
+						event_id);
+		default:
+		}
+
+		event_arg = &event_args[i];
+		if (event_arg->stack)
+			sse_free_stack(event_arg->stack);
+	}
+
+skip:
+	report_prefix_pop();
+}
+
+static struct priority_test_arg hi_prio_args[] = {
+	{.event_id = SBI_SSE_EVENT_GLOBAL_SOFTWARE},
+	{.event_id = SBI_SSE_EVENT_LOCAL_SOFTWARE},
+	{.event_id = SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS},
+	{.event_id = SBI_SSE_EVENT_LOCAL_LOW_PRIO_RAS},
+	{.event_id = SBI_SSE_EVENT_LOCAL_PMU_OVERFLOW},
+	{.event_id = SBI_SSE_EVENT_GLOBAL_HIGH_PRIO_RAS},
+	{.event_id = SBI_SSE_EVENT_LOCAL_DOUBLE_TRAP},
+	{.event_id = SBI_SSE_EVENT_LOCAL_HIGH_PRIO_RAS},
+};
+
+static struct priority_test_arg low_prio_args[] = {
+	{.event_id = SBI_SSE_EVENT_LOCAL_HIGH_PRIO_RAS},
+	{.event_id = SBI_SSE_EVENT_LOCAL_DOUBLE_TRAP},
+	{.event_id = SBI_SSE_EVENT_GLOBAL_HIGH_PRIO_RAS},
+	{.event_id = SBI_SSE_EVENT_LOCAL_PMU_OVERFLOW},
+	{.event_id = SBI_SSE_EVENT_LOCAL_LOW_PRIO_RAS},
+	{.event_id = SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS},
+	{.event_id = SBI_SSE_EVENT_LOCAL_SOFTWARE},
+	{.event_id = SBI_SSE_EVENT_GLOBAL_SOFTWARE},
+};
+
+static struct priority_test_arg prio_args[] = {
+	{.event_id = SBI_SSE_EVENT_GLOBAL_SOFTWARE,		.prio = 5},
+	{.event_id = SBI_SSE_EVENT_LOCAL_SOFTWARE,		.prio = 10},
+	{.event_id = SBI_SSE_EVENT_LOCAL_LOW_PRIO_RAS,		.prio = 12},
+	{.event_id = SBI_SSE_EVENT_LOCAL_PMU_OVERFLOW,		.prio = 15},
+	{.event_id = SBI_SSE_EVENT_GLOBAL_HIGH_PRIO_RAS,	.prio = 20},
+	{.event_id = SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS,		.prio = 22},
+	{.event_id = SBI_SSE_EVENT_LOCAL_HIGH_PRIO_RAS,		.prio = 25},
+};
+
+static struct priority_test_arg same_prio_args[] = {
+	{.event_id = SBI_SSE_EVENT_LOCAL_PMU_OVERFLOW,		.prio = 0},
+	{.event_id = SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS,		.prio = 0},
+	{.event_id = SBI_SSE_EVENT_LOCAL_HIGH_PRIO_RAS,		.prio = 10},
+	{.event_id = SBI_SSE_EVENT_LOCAL_SOFTWARE,		.prio = 10},
+	{.event_id = SBI_SSE_EVENT_GLOBAL_SOFTWARE,		.prio = 10},
+	{.event_id = SBI_SSE_EVENT_GLOBAL_HIGH_PRIO_RAS,	.prio = 20},
+	{.event_id = SBI_SSE_EVENT_LOCAL_LOW_PRIO_RAS,		.prio = 20},
+};
+
+static void sse_test_injection_priority(void)
+{
+	report_prefix_push("prio");
+
+	sse_test_injection_priority_arg(hi_prio_args, ARRAY_SIZE(hi_prio_args),
+					sse_hi_priority_test_handler, "high");
+
+	sse_test_injection_priority_arg(low_prio_args, ARRAY_SIZE(low_prio_args),
+					sse_low_priority_test_handler, "low");
+
+	sse_test_injection_priority_arg(prio_args, ARRAY_SIZE(prio_args),
+					sse_low_priority_test_handler, "changed");
+
+	sse_test_injection_priority_arg(same_prio_args, ARRAY_SIZE(same_prio_args),
+					sse_low_priority_test_handler, "same_prio_args");
+
+	report_prefix_pop();
+}
+
+static void test_invalid_event_id(unsigned long event_id)
+{
+	struct sbiret ret;
+	unsigned long value = 0;
+
+	ret = sbi_sse_register_raw(event_id, (unsigned long) sbi_sse_entry, 0);
+	sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM,
+			    "register event_id 0x%lx", event_id);
+
+	ret = sbi_sse_unregister(event_id);
+	sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM,
+			"unregister event_id 0x%lx", event_id);
+
+	ret = sbi_sse_enable(event_id);
+	sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM,
+			    "enable event_id 0x%lx", event_id);
+
+	ret = sbi_sse_disable(event_id);
+	sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM,
+			    "disable event_id 0x%lx", event_id);
+
+	ret = sbi_sse_inject(event_id, 0);
+	sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM,
+			    "inject event_id 0x%lx", event_id);
+
+	ret = sbi_sse_write_attrs(event_id, SBI_SSE_ATTR_PRIORITY, 1, &value);
+	sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM,
+			    "write attr event_id 0x%lx", event_id);
+
+	ret = sbi_sse_read_attrs(event_id, SBI_SSE_ATTR_PRIORITY, 1, &value);
+	sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM,
+			    "read attr event_id 0x%lx", event_id);
+}
+
+static void sse_test_invalid_event_id(void)
+{
+
+	report_prefix_push("event_id");
+
+	test_invalid_event_id(SBI_SSE_EVENT_LOCAL_RESERVED_0_START);
+
+	report_prefix_pop();
+}
+
+static void sse_check_event_availability(uint32_t event_id, bool *can_inject, bool *supported)
+{
+	unsigned long status;
+	struct sbiret ret;
+
+	*can_inject = false;
+	*supported = false;
+
+	ret = sbi_sse_read_attrs(event_id, SBI_SSE_ATTR_STATUS, 1, &status);
+	if (ret.error != SBI_SUCCESS && ret.error != SBI_ERR_NOT_SUPPORTED) {
+		report_fail("Get event status != SBI_SUCCESS && != SBI_ERR_NOT_SUPPORTED: %ld",
+			    ret.error);
+		return;
+	}
+	if (ret.error == SBI_ERR_NOT_SUPPORTED)
+		return;
+
+	*supported = true;
+	*can_inject = (status >> SBI_SSE_ATTR_STATUS_INJECT_OFFSET) & 1;
+}
+
+static void sse_secondary_boot_and_unmask(void *data)
+{
+	sbi_sse_hart_unmask();
+}
+
+static void sse_check_mask(void)
+{
+	struct sbiret ret;
+
+	/* Upon boot, event are masked, check that */
+	ret = sbi_sse_hart_mask();
+	sbiret_report_error(&ret, SBI_ERR_ALREADY_STOPPED, "hart mask at boot time");
+
+	ret = sbi_sse_hart_unmask();
+	sbiret_report_error(&ret, SBI_SUCCESS, "hart unmask");
+	ret = sbi_sse_hart_unmask();
+	sbiret_report_error(&ret, SBI_ERR_ALREADY_STARTED, "hart unmask twice error");
+
+	ret = sbi_sse_hart_mask();
+	sbiret_report_error(&ret, SBI_SUCCESS, "hart mask");
+	ret = sbi_sse_hart_mask();
+	sbiret_report_error(&ret, SBI_ERR_ALREADY_STOPPED, "hart mask twice");
+}
+
+static void run_inject_test(struct sse_event_info *info)
+{
+	unsigned long event_id = info->event_id;
+
+	if (!info->can_inject) {
+		report_skip("Event does not support injection, skipping injection tests");
+		return;
+	}
+
+	sse_test_inject_simple(event_id);
+
+	if (sbi_sse_event_is_global(event_id))
+		sse_test_inject_global(event_id);
+	else
+		sse_test_inject_local(event_id);
+}
+
+void check_sse(void)
+{
+	struct sse_event_info *info;
+	unsigned long i, event_id;
+	bool sbi_skip_inject = false;
+	bool supported;
+
+	report_prefix_push("sse");
+
+	if (!sbi_probe(SBI_EXT_SSE)) {
+		report_skip("extension not available");
+		report_prefix_pop();
+		return;
+	}
+
+	sse_check_mask();
+
+	/*
+	 * Dummy wakeup of all processors since some of them will be targeted
+	 * by global events without going through the wakeup call as well as
+	 * unmasking SSE events on all harts
+	 */
+	on_cpus(sse_secondary_boot_and_unmask, NULL);
+
+	/* Check for OpenSBI to support injection */
+	if (sbi_get_imp_id() == SBI_IMPL_OPENSBI) {
+		if (sbi_get_imp_version() < sbi_impl_opensbi_mk_version(1, 6)) {
+			/*
+			 * OpenSBI < v1.6 crashes kvm-unit-tests upon injection since injection
+			 * arguments (a6/a7) were reversed. Skip injection tests.
+			 */
+			report_skip("OpenSBI < v1.6 detected, skipping injection tests");
+			sbi_skip_inject = true;
+		}
+	}
+
+	sse_test_invalid_event_id();
+
+	for (i = 0; i < ARRAY_SIZE(sse_event_infos); i++) {
+		info = &sse_event_infos[i];
+		event_id = info->event_id;
+		report_prefix_push(info->name);
+		sse_check_event_availability(event_id, &info->can_inject, &supported);
+		if (!supported) {
+			report_skip("Event is not supported, skipping tests");
+			report_prefix_pop();
+			continue;
+		}
+
+		sse_test_attrs(event_id);
+		sse_test_register_error(event_id);
+
+		if (!sbi_skip_inject)
+			run_inject_test(info);
+
+		report_prefix_pop();
+	}
+
+	if (!sbi_skip_inject)
+		sse_test_injection_priority();
+
+	report_prefix_pop();
+}
diff --git a/riscv/sbi.c b/riscv/sbi.c
index 0404bb81..478cb35d 100644
--- a/riscv/sbi.c
+++ b/riscv/sbi.c
@@ -32,6 +32,7 @@
 
 #define	HIGH_ADDR_BOUNDARY	((phys_addr_t)1 << 32)
 
+void check_sse(void);
 void check_fwft(void);
 
 static long __labs(long a)
@@ -1567,6 +1568,7 @@ int main(int argc, char **argv)
 	check_hsm();
 	check_dbcn();
 	check_susp();
+	check_sse();
 	check_fwft();
 
 	return report_summary();
-- 
2.47.2

Re: [kvm-unit-tests PATCH v11 8/8] riscv: sbi: Add SSE extension tests

[Andrew Jones]

On Mon, Mar 17, 2025 at 05:46:53PM +0100, Clément Léger wrote:
...
> +	/* Test all flags allowed for SBI_SSE_ATTR_INTERRUPTED_FLAGS */
> +	attr = SBI_SSE_ATTR_INTERRUPTED_FLAGS;
> +	ret = sbi_sse_read_attrs(event_id, attr, 1, &prev_value);
> +	sbiret_report_error(&ret, SBI_SUCCESS, "Save interrupted flags");
> +
> +	for (i = 0; i < ARRAY_SIZE(interrupted_flags); i++) {
> +		flags = interrupted_flags[i];
> +		ret = sbi_sse_write_attrs(event_id, attr, 1, &flags);
> +		sbiret_report_error(&ret, SBI_SUCCESS,
> +				    "Set interrupted flags bit 0x%lx value", flags);
> +		ret = sbi_sse_read_attrs(event_id, attr, 1, &value);
> +		sbiret_report_error(&ret, SBI_SUCCESS, "Get interrupted flags after set");
> +		report(value == flags, "interrupted flags modified value: 0x%lx", value);
> +	}
> +
> +	/* Write invalid bit in flag register */
> +	flags = SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT << 1;
> +	ret = sbi_sse_write_attrs(event_id, attr, 1, &flags);
> +	sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM, "Set invalid flags bit 0x%lx value error",
> +			    flags);
> +
> +	flags = BIT(SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT + 1);

This broke compiling for rv32, but just changing it to BIT_ULL wouldn't be
right either since SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT is a BIT().
I think the test just above this one is what this test was aiming to do,
making it redundant. Instead of removing it, I changed it as below to get
more coverage, at least on rv64.

Thanks,
drew

diff --git a/riscv/sbi-sse.c b/riscv/sbi-sse.c
index fb4ee7dd44b2..f9e389728616 100644
--- a/riscv/sbi-sse.c
+++ b/riscv/sbi-sse.c
@@ -495,10 +495,12 @@ static void sse_simple_handler(void *data, struct pt_regs *regs, unsigned int ha
        sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM, "Set invalid flags bit 0x%lx value error",
                            flags);

-       flags = BIT(SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT + 1);
+#if __riscv_xlen > 32
+       flags = BIT(32);
        ret = sbi_sse_write_attrs(event_id, attr, 1, &flags);
        sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM, "Set invalid flags bit 0x%lx value error",
                            flags);
+#endif

        ret = sbi_sse_write_attrs(event_id, attr, 1, &prev_value);
        sbiret_report_error(&ret, SBI_SUCCESS, "Restore interrupted flags");

Re: [kvm-unit-tests PATCH v11 8/8] riscv: sbi: Add SSE extension tests

[Clément Léger]

On 20/03/2025 14:40, Andrew Jones wrote:
> On Mon, Mar 17, 2025 at 05:46:53PM +0100, Clément Léger wrote:
> ...
>> +	/* Test all flags allowed for SBI_SSE_ATTR_INTERRUPTED_FLAGS */
>> +	attr = SBI_SSE_ATTR_INTERRUPTED_FLAGS;
>> +	ret = sbi_sse_read_attrs(event_id, attr, 1, &prev_value);
>> +	sbiret_report_error(&ret, SBI_SUCCESS, "Save interrupted flags");
>> +
>> +	for (i = 0; i < ARRAY_SIZE(interrupted_flags); i++) {
>> +		flags = interrupted_flags[i];
>> +		ret = sbi_sse_write_attrs(event_id, attr, 1, &flags);
>> +		sbiret_report_error(&ret, SBI_SUCCESS,
>> +				    "Set interrupted flags bit 0x%lx value", flags);
>> +		ret = sbi_sse_read_attrs(event_id, attr, 1, &value);
>> +		sbiret_report_error(&ret, SBI_SUCCESS, "Get interrupted flags after set");
>> +		report(value == flags, "interrupted flags modified value: 0x%lx", value);
>> +	}
>> +
>> +	/* Write invalid bit in flag register */
>> +	flags = SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT << 1;
>> +	ret = sbi_sse_write_attrs(event_id, attr, 1, &flags);
>> +	sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM, "Set invalid flags bit 0x%lx value error",
>> +			    flags);
>> +
>> +	flags = BIT(SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT + 1);
> 
> This broke compiling for rv32, but just changing it to BIT_ULL wouldn't be
> right either since SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT is a BIT().
> I think the test just above this one is what this test was aiming to do,
> making it redundant. Instead of removing it, I changed it as below to get
> more coverage, at least on rv64.

Hum yeah indeed, that wasn't what was intended to be done. You fix is
correct.

Thanks,

Clément

> 
> Thanks,
> drew
> 
> diff --git a/riscv/sbi-sse.c b/riscv/sbi-sse.c
> index fb4ee7dd44b2..f9e389728616 100644
> --- a/riscv/sbi-sse.c
> +++ b/riscv/sbi-sse.c
> @@ -495,10 +495,12 @@ static void sse_simple_handler(void *data, struct pt_regs *regs, unsigned int ha
>         sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM, "Set invalid flags bit 0x%lx value error",
>                             flags);
> 
> -       flags = BIT(SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT + 1);
> +#if __riscv_xlen > 32
> +       flags = BIT(32);
>         ret = sbi_sse_write_attrs(event_id, attr, 1, &flags);
>         sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM, "Set invalid flags bit 0x%lx value error",
>                             flags);
> +#endif
> 
>         ret = sbi_sse_write_attrs(event_id, attr, 1, &prev_value);
>         sbiret_report_error(&ret, SBI_SUCCESS, "Restore interrupted flags");

Re: [kvm-unit-tests PATCH v11 8/8] riscv: sbi: Add SSE extension tests

[Andrew Jones]

...
> +cleanup:
> +	switch (state) {
> +	case SBI_SSE_STATE_ENABLED:
> +		ret = sbi_sse_disable(event_id);
> +		if (ret.error) {
> +			sbiret_report_error(&ret, SBI_SUCCESS, "disable event 0x%x", event_id);
> +			break;
> +		}
> +	case SBI_SSE_STATE_REGISTERED:
> +		sbi_sse_unregister(event_id);
> +		if (ret.error)
> +			sbiret_report_error(&ret, SBI_SUCCESS, "unregister event 0x%x", event_id);
> +	default:

I had to add break here to make clang happy (and same for the other two
defaults without statements).

Thanks,
drew

Re: [kvm-unit-tests PATCH v11 8/8] riscv: sbi: Add SSE extension tests

[Clément Léger]

On 20/03/2025 14:46, Andrew Jones wrote:
> ...
>> +cleanup:
>> +	switch (state) {
>> +	case SBI_SSE_STATE_ENABLED:
>> +		ret = sbi_sse_disable(event_id);
>> +		if (ret.error) {
>> +			sbiret_report_error(&ret, SBI_SUCCESS, "disable event 0x%x", event_id);
>> +			break;
>> +		}
>> +	case SBI_SSE_STATE_REGISTERED:
>> +		sbi_sse_unregister(event_id);
>> +		if (ret.error)
>> +			sbiret_report_error(&ret, SBI_SUCCESS, "unregister event 0x%x", event_id);
>> +	default:
> 
> I had to add break here to make clang happy (and same for the other two
> defaults without statements).

Ok. Not directly related but I could/should have added "/* passthrough
*/" comments on the two cases above though.

Thanks,

Clément

> 
> Thanks,
> drew

Re: [kvm-unit-tests PATCH v11 0/8] riscv: add SBI SSE extension tests

[Andrew Jones]

Hi Clément,

I'd like to merge this, but we still have 50 failures with the latest
opensbi and over 30 with the opensbi QEMU provides. Testing with [1]
and bumping the timeout to 6000 allowed me to avoid failures, however
we can't count on that for CI.

[1] https://lists.infradead.org/pipermail/opensbi/2025-March/008190.html

I'm thinking about just doing the following. What do you think?

Thanks,
drew

diff --git a/riscv/sbi-sse.c b/riscv/sbi-sse.c
index a31c84c32303..fb4ee7dd44b2 100644
--- a/riscv/sbi-sse.c
+++ b/riscv/sbi-sse.c
@@ -1217,7 +1217,6 @@ void check_sse(void)
 {
        struct sse_event_info *info;
        unsigned long i, event_id;
-       bool sbi_skip_inject = false;
        bool supported;

        report_prefix_push("sse");
@@ -1228,6 +1227,13 @@ void check_sse(void)
                return;
        }

+       if (sbi_get_imp_id() == SBI_IMPL_OPENSBI &&
+           sbi_get_imp_version() < sbi_impl_opensbi_mk_version(1, 7)) {
+               report_skip("OpenSBI < v1.7 detected, skipping tests");
+               report_prefix_pop();
+               return;
+       }
+
        sse_check_mask();

        /*
@@ -1237,18 +1243,6 @@ void check_sse(void)
         */
        on_cpus(sse_secondary_boot_and_unmask, NULL);

-       /* Check for OpenSBI to support injection */
-       if (sbi_get_imp_id() == SBI_IMPL_OPENSBI) {
-               if (sbi_get_imp_version() < sbi_impl_opensbi_mk_version(1, 6)) {
-                       /*
-                        * OpenSBI < v1.6 crashes kvm-unit-tests upon injection since injection
-                        * arguments (a6/a7) were reversed. Skip injection tests.
-                        */
-                       report_skip("OpenSBI < v1.6 detected, skipping injection tests");
-                       sbi_skip_inject = true;
-               }
-       }
-
        sse_test_invalid_event_id();

        for (i = 0; i < ARRAY_SIZE(sse_event_infos); i++) {
@@ -1265,14 +1259,12 @@ void check_sse(void)
                sse_test_attrs(event_id);
                sse_test_register_error(event_id);

-               if (!sbi_skip_inject)
-                       run_inject_test(info);
+               run_inject_test(info);

                report_prefix_pop();
        }

-       if (!sbi_skip_inject)
-               sse_test_injection_priority();
+       sse_test_injection_priority();

        report_prefix_pop();
 }

On Mon, Mar 17, 2025 at 05:46:45PM +0100, Clément Léger wrote:
> This series adds tests for SBI SSE extension as well as needed
> infrastructure for SSE support. It also adds test specific asm-offsets
> generation to use custom OFFSET and DEFINE from the test directory.
> 
> These tests can be run using an OpenSBI version that implements latest
> specifications modification [1]
> 
> Link: https://github.com/rivosinc/opensbi/tree/dev/cleger/sse [1]
> 
> ---
> 
> V11:
>  - Use mask inside sbi_impl_opensbi_mk_version()
>  - Mask the SBI version with a new mask
>  - Use assert inside sbi_get_impl_id/version()
>  - Remove sbi_check_impl()
>  - Increase completion timeout as events failed completing under 1000
>    micros when system is loaded.
> 
> V10:
>  - Use && instead of || for timeout handling
>  - Add SBI patches which introduce function to get implementer ID and
>    version as well as implementer ID defines.
>  - Skip injection tests in OpenSBI < v1.6
> 
> V9:
>  - Use __ASSEMBLER__ instead of __ASSEMBLY__
>  - Remove extra spaces
>  - Use assert to check global event in
>    sse_global_event_set_current_hart()
>  - Tabulate SSE events names table
>  - Use sbi_sse_register() instead of sbi_sse_register_raw() in error
>    testing
>  - Move a report_pass() out of error path
>  - Rework all injection tests with better error handling
>  - Use an env var for sse event completion timeout
>  - Add timeout for some potentially infinite while() loops
> 
> V8:
>  - Short circuit current event tests if failure happens
>  - Remove SSE from all report strings
>  - Indent .prio field
>  - Add cpu_relax()/smp_rmb() where needed
>  - Add timeout for global event ENABLED state check
>  - Added BIT(32) aliases tests for attribute/event_id.
> 
> V7:
>  - Test ids/attributes/attributes count > 32 bits
>  - Rename all SSE function to sbi_sse_*
>  - Use event_id instead of event/evt
>  - Factorize read/write test
>  - Use virt_to_phys() for attributes read/write.
>  - Extensively use sbiret_report_error()
>  - Change check function return values to bool.
>  - Added assert for stack size to be below or equal to PAGE_SIZE
>  - Use en env variable for the maximum hart ID
>  - Check that individual read from attributes matches the multiple
>    attributes read.
>  - Added multiple attributes write at once
>  - Used READ_ONCE/WRITE_ONCE
>  - Inject all local event at once rather than looping fopr each core.
>  - Split test_arg for local_dispatch test so that all CPUs can run at
>    once.
>  - Move SSE entry and generic code to lib/riscv for other tests
>  - Fix unmask/mask state checking
> 
> V6:
>  - Add missing $(generated-file) dependencies for "-deps" objects
>  - Split SSE entry from sbi-asm.S to sse-asm.S and all SSE core functions
>    since it will be useful for other tests as well (dbltrp).
> 
> V5:
>  - Update event ranges based on latest spec
>  - Rename asm-offset-test.c to sbi-asm-offset.c
> 
> V4:
>  - Fix typo sbi_ext_ss_fid -> sbi_ext_sse_fid
>  - Add proper asm-offset generation for tests
>  - Move SSE specific file from lib/riscv to riscv/
> 
> V3:
>  - Add -deps variable for test specific dependencies
>  - Fix formatting errors/typo in sbi.h
>  - Add missing double trap event
>  - Alphabetize sbi-sse.c includes
>  - Fix a6 content after unmasking event
>  - Add SSE HART_MASK/UNMASK test
>  - Use mv instead of move
>  - move sbi_check_sse() definition in sbi.c
>  - Remove sbi_sse test from unitests.cfg
> 
> V2:
>  - Rebased on origin/master and integrate it into sbi.c tests
> 
> Clément Léger (8):
>   kbuild: Allow multiple asm-offsets file to be generated
>   riscv: Set .aux.o files as .PRECIOUS
>   riscv: Use asm-offsets to generate SBI_EXT_HSM values
>   lib: riscv: Add functions for version checking
>   lib: riscv: Add functions to get implementer ID and version
>   riscv: lib: Add SBI SSE extension definitions
>   lib: riscv: Add SBI SSE support
>   riscv: sbi: Add SSE extension tests
> 
>  scripts/asm-offsets.mak |   22 +-
>  riscv/Makefile          |    5 +-
>  lib/riscv/asm/csr.h     |    1 +
>  lib/riscv/asm/sbi.h     |  177 +++++-
>  lib/riscv/sbi-sse-asm.S |  102 ++++
>  lib/riscv/asm-offsets.c |    9 +
>  lib/riscv/sbi.c         |  105 +++-
>  riscv/sbi-tests.h       |    1 +
>  riscv/sbi-asm.S         |    6 +-
>  riscv/sbi-asm-offsets.c |   11 +
>  riscv/sbi-sse.c         | 1278 +++++++++++++++++++++++++++++++++++++++
>  riscv/sbi.c             |    2 +
>  riscv/.gitignore        |    1 +
>  13 files changed, 1707 insertions(+), 13 deletions(-)
>  create mode 100644 lib/riscv/sbi-sse-asm.S
>  create mode 100644 riscv/sbi-asm-offsets.c
>  create mode 100644 riscv/sbi-sse.c
>  create mode 100644 riscv/.gitignore
> 
> -- 
> 2.47.2
> 

Re: [kvm-unit-tests PATCH v11 0/8] riscv: add SBI SSE extension tests

[Clément Léger]

On 19/03/2025 19:01, Andrew Jones wrote:
> Hi Clément,
> 
> I'd like to merge this, but we still have 50 failures with the latest
> opensbi and over 30 with the opensbi QEMU provides. Testing with [1]
> and bumping the timeout to 6000 allowed me to avoid failures, however
> we can't count on that for CI.
> 
> [1] https://lists.infradead.org/pipermail/opensbi/2025-March/008190.html
> 
> I'm thinking about just doing the following. What do you think?

Hi Andrew,

Since the spec isn't even ratified, does it even make sense to test a
version that does not implement the ratified SBI V3.0 spec ? IOW, should
we simply test for SBI version to be >= 3.0 ? This will be correct for
all SBI implementation.

However, If you want that series to be integrated ASAP, I'm ok with your
patch , it seems unlikely that the SSE specification will change in the
upcoming weeks.

Reviewed-by: Clément Léger <cleger@rivosinc.com>

Thanks,

Clément

> 
> Thanks,
> drew
> 
> diff --git a/riscv/sbi-sse.c b/riscv/sbi-sse.c
> index a31c84c32303..fb4ee7dd44b2 100644
> --- a/riscv/sbi-sse.c
> +++ b/riscv/sbi-sse.c
> @@ -1217,7 +1217,6 @@ void check_sse(void)
>  {
>         struct sse_event_info *info;
>         unsigned long i, event_id;
> -       bool sbi_skip_inject = false;
>         bool supported;
> 
>         report_prefix_push("sse");
> @@ -1228,6 +1227,13 @@ void check_sse(void)
>                 return;
>         }
> 
> +       if (sbi_get_imp_id() == SBI_IMPL_OPENSBI &&
> +           sbi_get_imp_version() < sbi_impl_opensbi_mk_version(1, 7)) {
> +               report_skip("OpenSBI < v1.7 detected, skipping tests");
> +               report_prefix_pop();
> +               return;
> +       }
> +
>         sse_check_mask();
> 
>         /*
> @@ -1237,18 +1243,6 @@ void check_sse(void)
>          */
>         on_cpus(sse_secondary_boot_and_unmask, NULL);
> 
> -       /* Check for OpenSBI to support injection */
> -       if (sbi_get_imp_id() == SBI_IMPL_OPENSBI) {
> -               if (sbi_get_imp_version() < sbi_impl_opensbi_mk_version(1, 6)) {
> -                       /*
> -                        * OpenSBI < v1.6 crashes kvm-unit-tests upon injection since injection
> -                        * arguments (a6/a7) were reversed. Skip injection tests.
> -                        */
> -                       report_skip("OpenSBI < v1.6 detected, skipping injection tests");
> -                       sbi_skip_inject = true;
> -               }
> -       }
> -
>         sse_test_invalid_event_id();
> 
>         for (i = 0; i < ARRAY_SIZE(sse_event_infos); i++) {
> @@ -1265,14 +1259,12 @@ void check_sse(void)
>                 sse_test_attrs(event_id);
>                 sse_test_register_error(event_id);
> 
> -               if (!sbi_skip_inject)
> -                       run_inject_test(info);
> +               run_inject_test(info);
> 
>                 report_prefix_pop();
>         }
> 
> -       if (!sbi_skip_inject)
> -               sse_test_injection_priority();
> +       sse_test_injection_priority();
> 
>         report_prefix_pop();
>  }
> 
> On Mon, Mar 17, 2025 at 05:46:45PM +0100, Clément Léger wrote:
>> This series adds tests for SBI SSE extension as well as needed
>> infrastructure for SSE support. It also adds test specific asm-offsets
>> generation to use custom OFFSET and DEFINE from the test directory.
>>
>> These tests can be run using an OpenSBI version that implements latest
>> specifications modification [1]
>>
>> Link: https://github.com/rivosinc/opensbi/tree/dev/cleger/sse [1]
>>
>> ---
>>
>> V11:
>>  - Use mask inside sbi_impl_opensbi_mk_version()
>>  - Mask the SBI version with a new mask
>>  - Use assert inside sbi_get_impl_id/version()
>>  - Remove sbi_check_impl()
>>  - Increase completion timeout as events failed completing under 1000
>>    micros when system is loaded.
>>
>> V10:
>>  - Use && instead of || for timeout handling
>>  - Add SBI patches which introduce function to get implementer ID and
>>    version as well as implementer ID defines.
>>  - Skip injection tests in OpenSBI < v1.6
>>
>> V9:
>>  - Use __ASSEMBLER__ instead of __ASSEMBLY__
>>  - Remove extra spaces
>>  - Use assert to check global event in
>>    sse_global_event_set_current_hart()
>>  - Tabulate SSE events names table
>>  - Use sbi_sse_register() instead of sbi_sse_register_raw() in error
>>    testing
>>  - Move a report_pass() out of error path
>>  - Rework all injection tests with better error handling
>>  - Use an env var for sse event completion timeout
>>  - Add timeout for some potentially infinite while() loops
>>
>> V8:
>>  - Short circuit current event tests if failure happens
>>  - Remove SSE from all report strings
>>  - Indent .prio field
>>  - Add cpu_relax()/smp_rmb() where needed
>>  - Add timeout for global event ENABLED state check
>>  - Added BIT(32) aliases tests for attribute/event_id.
>>
>> V7:
>>  - Test ids/attributes/attributes count > 32 bits
>>  - Rename all SSE function to sbi_sse_*
>>  - Use event_id instead of event/evt
>>  - Factorize read/write test
>>  - Use virt_to_phys() for attributes read/write.
>>  - Extensively use sbiret_report_error()
>>  - Change check function return values to bool.
>>  - Added assert for stack size to be below or equal to PAGE_SIZE
>>  - Use en env variable for the maximum hart ID
>>  - Check that individual read from attributes matches the multiple
>>    attributes read.
>>  - Added multiple attributes write at once
>>  - Used READ_ONCE/WRITE_ONCE
>>  - Inject all local event at once rather than looping fopr each core.
>>  - Split test_arg for local_dispatch test so that all CPUs can run at
>>    once.
>>  - Move SSE entry and generic code to lib/riscv for other tests
>>  - Fix unmask/mask state checking
>>
>> V6:
>>  - Add missing $(generated-file) dependencies for "-deps" objects
>>  - Split SSE entry from sbi-asm.S to sse-asm.S and all SSE core functions
>>    since it will be useful for other tests as well (dbltrp).
>>
>> V5:
>>  - Update event ranges based on latest spec
>>  - Rename asm-offset-test.c to sbi-asm-offset.c
>>
>> V4:
>>  - Fix typo sbi_ext_ss_fid -> sbi_ext_sse_fid
>>  - Add proper asm-offset generation for tests
>>  - Move SSE specific file from lib/riscv to riscv/
>>
>> V3:
>>  - Add -deps variable for test specific dependencies
>>  - Fix formatting errors/typo in sbi.h
>>  - Add missing double trap event
>>  - Alphabetize sbi-sse.c includes
>>  - Fix a6 content after unmasking event
>>  - Add SSE HART_MASK/UNMASK test
>>  - Use mv instead of move
>>  - move sbi_check_sse() definition in sbi.c
>>  - Remove sbi_sse test from unitests.cfg
>>
>> V2:
>>  - Rebased on origin/master and integrate it into sbi.c tests
>>
>> Clément Léger (8):
>>   kbuild: Allow multiple asm-offsets file to be generated
>>   riscv: Set .aux.o files as .PRECIOUS
>>   riscv: Use asm-offsets to generate SBI_EXT_HSM values
>>   lib: riscv: Add functions for version checking
>>   lib: riscv: Add functions to get implementer ID and version
>>   riscv: lib: Add SBI SSE extension definitions
>>   lib: riscv: Add SBI SSE support
>>   riscv: sbi: Add SSE extension tests
>>
>>  scripts/asm-offsets.mak |   22 +-
>>  riscv/Makefile          |    5 +-
>>  lib/riscv/asm/csr.h     |    1 +
>>  lib/riscv/asm/sbi.h     |  177 +++++-
>>  lib/riscv/sbi-sse-asm.S |  102 ++++
>>  lib/riscv/asm-offsets.c |    9 +
>>  lib/riscv/sbi.c         |  105 +++-
>>  riscv/sbi-tests.h       |    1 +
>>  riscv/sbi-asm.S         |    6 +-
>>  riscv/sbi-asm-offsets.c |   11 +
>>  riscv/sbi-sse.c         | 1278 +++++++++++++++++++++++++++++++++++++++
>>  riscv/sbi.c             |    2 +
>>  riscv/.gitignore        |    1 +
>>  13 files changed, 1707 insertions(+), 13 deletions(-)
>>  create mode 100644 lib/riscv/sbi-sse-asm.S
>>  create mode 100644 riscv/sbi-asm-offsets.c
>>  create mode 100644 riscv/sbi-sse.c
>>  create mode 100644 riscv/.gitignore
>>
>> -- 
>> 2.47.2
>>

Re: [kvm-unit-tests PATCH v11 0/8] riscv: add SBI SSE extension tests

[Andrew Jones]

On Mon, Mar 17, 2025 at 05:46:45PM +0100, Clément Léger wrote:
> This series adds tests for SBI SSE extension as well as needed
> infrastructure for SSE support. It also adds test specific asm-offsets
> generation to use custom OFFSET and DEFINE from the test directory.
> 
> These tests can be run using an OpenSBI version that implements latest
> specifications modification [1]
> 
> Link: https://github.com/rivosinc/opensbi/tree/dev/cleger/sse [1]

Applied to riscv/sbi with the fixups pointed out.

https://gitlab.com/jones-drew/kvm-unit-tests/-/commits/riscv/sbi

Thanks,
drew

> 
> ---
> 
> V11:
>  - Use mask inside sbi_impl_opensbi_mk_version()
>  - Mask the SBI version with a new mask
>  - Use assert inside sbi_get_impl_id/version()
>  - Remove sbi_check_impl()
>  - Increase completion timeout as events failed completing under 1000
>    micros when system is loaded.
> 
> V10:
>  - Use && instead of || for timeout handling
>  - Add SBI patches which introduce function to get implementer ID and
>    version as well as implementer ID defines.
>  - Skip injection tests in OpenSBI < v1.6
> 
> V9:
>  - Use __ASSEMBLER__ instead of __ASSEMBLY__
>  - Remove extra spaces
>  - Use assert to check global event in
>    sse_global_event_set_current_hart()
>  - Tabulate SSE events names table
>  - Use sbi_sse_register() instead of sbi_sse_register_raw() in error
>    testing
>  - Move a report_pass() out of error path
>  - Rework all injection tests with better error handling
>  - Use an env var for sse event completion timeout
>  - Add timeout for some potentially infinite while() loops
> 
> V8:
>  - Short circuit current event tests if failure happens
>  - Remove SSE from all report strings
>  - Indent .prio field
>  - Add cpu_relax()/smp_rmb() where needed
>  - Add timeout for global event ENABLED state check
>  - Added BIT(32) aliases tests for attribute/event_id.
> 
> V7:
>  - Test ids/attributes/attributes count > 32 bits
>  - Rename all SSE function to sbi_sse_*
>  - Use event_id instead of event/evt
>  - Factorize read/write test
>  - Use virt_to_phys() for attributes read/write.
>  - Extensively use sbiret_report_error()
>  - Change check function return values to bool.
>  - Added assert for stack size to be below or equal to PAGE_SIZE
>  - Use en env variable for the maximum hart ID
>  - Check that individual read from attributes matches the multiple
>    attributes read.
>  - Added multiple attributes write at once
>  - Used READ_ONCE/WRITE_ONCE
>  - Inject all local event at once rather than looping fopr each core.
>  - Split test_arg for local_dispatch test so that all CPUs can run at
>    once.
>  - Move SSE entry and generic code to lib/riscv for other tests
>  - Fix unmask/mask state checking
> 
> V6:
>  - Add missing $(generated-file) dependencies for "-deps" objects
>  - Split SSE entry from sbi-asm.S to sse-asm.S and all SSE core functions
>    since it will be useful for other tests as well (dbltrp).
> 
> V5:
>  - Update event ranges based on latest spec
>  - Rename asm-offset-test.c to sbi-asm-offset.c
> 
> V4:
>  - Fix typo sbi_ext_ss_fid -> sbi_ext_sse_fid
>  - Add proper asm-offset generation for tests
>  - Move SSE specific file from lib/riscv to riscv/
> 
> V3:
>  - Add -deps variable for test specific dependencies
>  - Fix formatting errors/typo in sbi.h
>  - Add missing double trap event
>  - Alphabetize sbi-sse.c includes
>  - Fix a6 content after unmasking event
>  - Add SSE HART_MASK/UNMASK test
>  - Use mv instead of move
>  - move sbi_check_sse() definition in sbi.c
>  - Remove sbi_sse test from unitests.cfg
> 
> V2:
>  - Rebased on origin/master and integrate it into sbi.c tests
> 
> Clément Léger (8):
>   kbuild: Allow multiple asm-offsets file to be generated
>   riscv: Set .aux.o files as .PRECIOUS
>   riscv: Use asm-offsets to generate SBI_EXT_HSM values
>   lib: riscv: Add functions for version checking
>   lib: riscv: Add functions to get implementer ID and version
>   riscv: lib: Add SBI SSE extension definitions
>   lib: riscv: Add SBI SSE support
>   riscv: sbi: Add SSE extension tests
> 
>  scripts/asm-offsets.mak |   22 +-
>  riscv/Makefile          |    5 +-
>  lib/riscv/asm/csr.h     |    1 +
>  lib/riscv/asm/sbi.h     |  177 +++++-
>  lib/riscv/sbi-sse-asm.S |  102 ++++
>  lib/riscv/asm-offsets.c |    9 +
>  lib/riscv/sbi.c         |  105 +++-
>  riscv/sbi-tests.h       |    1 +
>  riscv/sbi-asm.S         |    6 +-
>  riscv/sbi-asm-offsets.c |   11 +
>  riscv/sbi-sse.c         | 1278 +++++++++++++++++++++++++++++++++++++++
>  riscv/sbi.c             |    2 +
>  riscv/.gitignore        |    1 +
>  13 files changed, 1707 insertions(+), 13 deletions(-)
>  create mode 100644 lib/riscv/sbi-sse-asm.S
>  create mode 100644 riscv/sbi-asm-offsets.c
>  create mode 100644 riscv/sbi-sse.c
>  create mode 100644 riscv/.gitignore
> 
> -- 
> 2.47.2
> 

Re: [kvm-unit-tests PATCH v11 0/8] riscv: add SBI SSE extension tests

[Andrew Jones]

On Mon, Mar 17, 2025 at 05:46:45PM +0100, Clément Léger wrote:
> This series adds tests for SBI SSE extension as well as needed
> infrastructure for SSE support. It also adds test specific asm-offsets
> generation to use custom OFFSET and DEFINE from the test directory.
> 
> These tests can be run using an OpenSBI version that implements latest
> specifications modification [1]
> 
> Link: https://github.com/rivosinc/opensbi/tree/dev/cleger/sse [1]

Merged.

Thanks,
drew