Re: [kvm-unit-tests PATCH v4 01/11] arm64: set SCTLR_EL1 to a known value for secondary cores

[Andrew Jones <andrew.jones@linux.dev>]

On Thu, Dec 04, 2025 at 02:23:28PM +0000, Joey Gouly wrote:
> This ensures that primary and secondary cores will have the same values for
> SCTLR_EL1.

This almost deserves

Fixes: 10b65ce77ae7 ("arm64: Configure SCTLR_EL1 at boot")

> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> ---
>  arm/cstart64.S | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arm/cstart64.S b/arm/cstart64.S
> index 014c9c7b..dcdd1516 100644
> --- a/arm/cstart64.S
> +++ b/arm/cstart64.S
> @@ -185,6 +185,11 @@ get_mmu_off:
>  
>  .globl secondary_entry
>  secondary_entry:
> +	/* set SCTLR_EL1 to a known value */
> +	ldr	x0, =INIT_SCTLR_EL1_MMU_OFF
> +	msr	sctlr_el1, x0
> +	isb

It's indeed good practice to always follow msr with isb. In the past we've
been lazy and allowed subsequent msr writes before issuing the isb when we
knew it'd be issued before it's necessary, e.g. the cpacr_el1 write which
piggybacks on the isb in exceptions_init. But, since that's fragile, I
like the isb here and would even like to see the isb added to cpacr_el1,
and anywhere else we're currently neglecting it, done with a separate
patch.

> +
>  	/* enable FP/ASIMD and SVE */
>  	mov	x0, #(3 << 20)
>  	orr	x0, x0, #(3 << 16)
> -- 
> 2.25.1
>

Reviewed-by: Andrew Jones <andrew.jones@linux.dev>

Thanks,
drew