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* [PATCH v3 00/17] riscv: Generate riscv instruction functions
@ 2026-07-08  3:34 Charlie Jenkins
  2026-07-08  3:34 ` [PATCH v3 01/17] riscv: Introduce instruction table generation Charlie Jenkins
                   ` (17 more replies)
  0 siblings, 18 replies; 35+ messages in thread
From: Charlie Jenkins @ 2026-07-08  3:34 UTC (permalink / raw)
  To: Paul Walmsley, Palmer Dabbelt, Nam Cao, Alexandre Ghiti,
	Anup Patel, Atish Patra, Conor Dooley, Paolo Bonzini,
	Andrew Morton, Shuah Khan, Radim Krčmář,
	Jesse Taube
  Cc: linux-riscv, linux-kernel, kvm, kvm-riscv, linux-kselftest,
	Charlie Jenkins

There is a lot of code that is manually manipulating riscv instructions.
Constructing these headers for new instructions is time consuming and
error prone.

The first patch in this series introduces the instruction definition
table along with a script that runs at compile time to create all of the
associated instruction manipulation functions. The remaining patches
migrate all of the manual instruction code to use these generated
functions.

The instruction definition table is generated from the
riscv-unified-db[1], an open source RVI project for instruction
specifications. I got this table generation merged into
riscv-unified-db, that PR can be accessed on github [2].

After a format update PR is merged [3], I will link the commit hash of
the generated instructions.

A lot of the validation for these changes is from running all possible
32-bit or 16-bit integers through these functions to see that any given
instruction will produce to expected result. I give more detail on the
test cases in the notes of the first couple of patches.

For the KVM patches, I also introduce two test cases to ensure that the
instruction manipulation is working as expected.

[1] https://github.com/riscv/riscv-unified-db
[2] https://github.com/riscv/riscv-unified-db/pull/1780
[3] https://github.com/riscv/riscv-unified-db/pull/1869

Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
---
Changes in v3:
- A lot of Sashiko suggestions
- Introduced new patch "riscv: Maintain epc on misaligned emulation
  error" that will help with error handling
- Use CONFIG_32BIT/CONFIG_64BIT instaed of __riscv_xlen for generated
  instructions
- Link to v2: https://patch.msgid.link/20260621-riscv_insn_table-v2-0-7f0810ee2274@gmail.com

Changes in v2:
- rebased on v7.1
- I dropped the patch fixing the mmio bug in kvm because in the
  meantime that bug has been fixed in a different patch
- Calls to panic() for instructions not support on current hardware have
  been changed into BUG_ON()
- Fixed incorrect handling of branches in simulate_*()
- Added CONFIG_RISCV_KPROBES_SIMULATE_KUNIT for more detailed
  simulate_*() testing
- Updated insn.tbl based on new merged in changes to riscv-unified-db
- Link to v1: https://lore.kernel.org/r/20260407-riscv_insn_table-v1-0-54b4736a1e77@gmail.com

---
Charlie Jenkins (17):
      riscv: Introduce instruction table generation
      riscv: alternatives: Use generated instruction headers for patching code
      riscv: kgdb: Use generated instruction headers
      riscv: Add kprobes instruction simulation KUnit
      riscv: kprobes: Use generated instruction headers
      riscv: cfi: Use generated instruction headers
      riscv: Maintain epc on misaligned emulation error
      riscv: Use generated instruction headers for misaligned loads/stores
      riscv: kvm: Use generated instruction headers for csr code
      KVM: device: Add test device
      KVM: riscv: selftests: Add mmio test
      riscv: kvm: Use generated instruction headers for mmio emulation
      riscv: kvm: Add emulated test csr
      KVM: riscv: selftests: Add csr emulation test
      riscv: kvm: Use generated instruction headers for csr emulation
      riscv: kexec: Use generated instruction headers for kexec relocations
      riscv: Remove unused instruction headers

 arch/riscv/Kconfig.debug                           |    1 +
 arch/riscv/Makefile                                |    3 +
 arch/riscv/include/asm/Kbuild                      |    1 +
 arch/riscv/include/asm/insn.h                      |  563 +-------
 arch/riscv/include/asm/kvm_host.h                  |   10 +
 arch/riscv/include/asm/kvm_vcpu_insn.h             |    5 +-
 arch/riscv/include/asm/kvm_vcpu_test_csr.h         |   15 +
 arch/riscv/kernel/alternative.c                    |   23 +-
 arch/riscv/kernel/cfi.c                            |    6 +-
 arch/riscv/kernel/kgdb.c                           |  102 +-
 arch/riscv/kernel/machine_kexec_file.c             |   55 +-
 arch/riscv/kernel/probes/decode-insn.c             |    7 +-
 arch/riscv/kernel/probes/simulate-insn.c           |  253 ++--
 arch/riscv/kernel/probes/simulate-insn.h           |    7 +-
 arch/riscv/kernel/tests/Kconfig.debug              |   13 +
 arch/riscv/kernel/tests/kprobes/Makefile           |    2 +
 .../kernel/tests/kprobes/test-kprobes-simulate.c   |  250 ++++
 arch/riscv/kernel/tests/kprobes/test-kprobes.h     |    6 +
 arch/riscv/kernel/traps_misaligned.c               |  209 ++-
 arch/riscv/kvm/Kconfig.debug                       |   16 +
 arch/riscv/kvm/Makefile                            |    1 +
 arch/riscv/kvm/vcpu_insn.c                         |  264 ++--
 arch/riscv/kvm/vcpu_test_csr.c                     |   21 +
 arch/riscv/tools/Makefile                          |   22 +
 arch/riscv/tools/insn.tbl                          | 1392 ++++++++++++++++++++
 arch/riscv/tools/insn_tbl.sh                       |  258 ++++
 include/uapi/linux/kvm.h                           |    2 +
 lib/Kconfig.debug                                  |    6 +
 tools/testing/selftests/kvm/Makefile.kvm           |    2 +
 tools/testing/selftests/kvm/riscv/csr_test.c       |  133 ++
 tools/testing/selftests/kvm/riscv/mmio_test.c      |  189 +++
 virt/kvm/Kconfig.debug                             |   16 +
 virt/kvm/Makefile.kvm                              |    1 +
 virt/kvm/kvm_main.c                                |    8 +
 virt/kvm/mmio_test.c                               |  103 ++
 virt/kvm/mmio_test.h                               |   18 +
 36 files changed, 2951 insertions(+), 1032 deletions(-)
---
base-commit: 8cd9520d35a6c38db6567e97dd93b1f11f185dc6
change-id: 20260114-riscv_insn_table-38495495dfd3

Best regards,
--  
- Charlie


^ permalink raw reply	[flat|nested] 35+ messages in thread
end of thread, other threads:[~2026-07-09  6:26 UTC | newest]

Thread overview: 35+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-07-08  3:34 [PATCH v3 00/17] riscv: Generate riscv instruction functions Charlie Jenkins
2026-07-08  3:34 ` [PATCH v3 01/17] riscv: Introduce instruction table generation Charlie Jenkins
2026-07-08  3:50   ` sashiko-bot
2026-07-09  6:23     ` Charlie Jenkins
2026-07-08  3:34 ` [PATCH v3 02/17] riscv: alternatives: Use generated instruction headers for patching code Charlie Jenkins
2026-07-08  3:45   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 03/17] riscv: kgdb: Use generated instruction headers Charlie Jenkins
2026-07-08  3:34 ` [PATCH v3 04/17] riscv: Add kprobes instruction simulation KUnit Charlie Jenkins
2026-07-08  3:51   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 05/17] riscv: kprobes: Use generated instruction headers Charlie Jenkins
2026-07-08  3:52   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 06/17] riscv: cfi: " Charlie Jenkins
2026-07-08  3:34 ` [PATCH v3 07/17] riscv: Maintain epc on misaligned emulation error Charlie Jenkins
2026-07-08  3:55   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 08/17] riscv: Use generated instruction headers for misaligned loads/stores Charlie Jenkins
2026-07-08  3:49   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 09/17] riscv: kvm: Use generated instruction headers for csr code Charlie Jenkins
2026-07-08  3:48   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 10/17] KVM: device: Add test device Charlie Jenkins
2026-07-08  3:48   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 11/17] KVM: riscv: selftests: Add mmio test Charlie Jenkins
2026-07-08  3:59   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 12/17] riscv: kvm: Use generated instruction headers for mmio emulation Charlie Jenkins
2026-07-08  4:01   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 13/17] riscv: kvm: Add emulated test csr Charlie Jenkins
2026-07-08  4:00   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 14/17] KVM: riscv: selftests: Add csr emulation test Charlie Jenkins
2026-07-08  3:58   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 15/17] riscv: kvm: Use generated instruction headers for csr emulation Charlie Jenkins
2026-07-08  4:04   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 16/17] riscv: kexec: Use generated instruction headers for kexec relocations Charlie Jenkins
2026-07-08  4:01   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 17/17] riscv: Remove unused instruction headers Charlie Jenkins
2026-07-08  4:09   ` sashiko-bot
2026-07-09  6:26 ` [syzbot ci] Re: riscv: Generate riscv instruction functions syzbot ci

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