From: sashiko-bot@kernel.org
To: "Sascha Bischoff" <Sascha.Bischoff@arm.com>
Cc: kvm@vger.kernel.org, "Oliver Upton" <oupton@kernel.org>,
kvmarm@lists.linux.dev, "Marc Zyngier" <maz@kernel.org>
Subject: Re: [PATCH v6 14/49] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells
Date: Fri, 04 Sep 2026 12:50:51 +0000 [thread overview]
Message-ID: <20260904125052.4795B1F00A3D@smtp.kernel.org> (raw)
In-Reply-To: <20260904113404.4051341-15-sascha.bischoff@arm.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Guest/Userspace-reachable WARN_ON() in vgic_v5_reset() allows unprivileged Denial of Service
- [High] Concurrent vCPU creation during vgic_v5_init() leads to out-of-bounds IRQ free
- [High] Doorbell LPIs are freed and can be reallocated while still in use by unresponsive hardware
--
commit 44d8f1c654ba05556ff20d22e8e4b8b74f493342
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>
KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells
This commit sets up GICv5 VM table entries and VPE doorbells by allocating
a VM ID and creating a per-VM VPE doorbell IRQ domain. It also provides the
initialization and teardown paths to manage this state.
> diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c
> index 455161e52f81b..5b599821b2da2 100644
> --- a/arch/arm64/kvm/vgic/vgic-v5.c
> +++ b/arch/arm64/kvm/vgic/vgic-v5.c
[ ... ]
> @@ -562,33 +580,122 @@ void vgic_v5_reset(struct kvm_vcpu *vcpu)
> * CPUIF (but potentially fewer in the IRS).
> */
> vcpu->arch.vgic_cpu.num_pri_bits = 5;
> +
> + /* Make the VPE valid in the VPET */
> + if (WARN_ON(vgic_v5_send_command(vcpu, VPE_MAKE_VALID)))
> + return;
> +}
[Severity: High]
Can this WARN_ON be triggered by unprivileged userspace, potentially leading
to a host panic if panic_on_warn is enabled?
If userspace calls KVM_ARM_VCPU_INIT before KVM_DEV_ARM_VGIC_CTRL_INIT has
successfully completed, the reset path reaches vgic_v5_reset() and attempts
to send VPE_MAKE_VALID. Because the VGIC has not been initialized, the
doorbell IRQ is still uninitialized (0). This causes vgic_v5_send_command()
to return -ENXIO, directly hitting this warning.
The KVM subsystem guidelines suggest that userspace-reachable warnings should
be converted to normal error handling or rate-limited prints to avoid a
denial of service.
> +
> +static void vgic_v5_free_doorbells(struct kvm *kvm, unsigned int nr_dbs)
> +{
> + struct vgic_v5_vm *vm = &kvm->arch.vgic.gicv5_vm;
> + struct kvm_vcpu *vcpu;
> + unsigned long i;
> + int db;
> +
> + for (i = 0; i < nr_dbs; i++) {
> + vcpu = kvm_get_vcpu(kvm, i);
> + db = vgic_v5_vpe_db(vcpu);
> + if (!db)
> + continue;
> +
> + free_irq(db, vcpu);
> + vcpu->arch.vgic_cpu.vgic_v5.gicv5_vpe.db = 0;
> + }
> +
> + if (vm->vpe_db_base) {
> + irq_domain_free_irqs(vm->vpe_db_base,
> + atomic_read(&kvm->online_vcpus));
[Severity: High]
Does this free more descriptors than were originally allocated if a vCPU is
created concurrently?
During vgic_v5_init(), the doorbell domain is sized based on a snapshot of
atomic_read(&kvm->online_vcpus). If a userspace thread calls KVM_CREATE_VCPU
concurrently, it increments created_vcpus and blocks on the config_lock.
Initialization then proceeds with the older, smaller online_vcpus count.
Once the vCPU creation completes, online_vcpus is incremented.
When the VM is torn down, this code uses the new, larger online_vcpus count
to free the domain interrupts, which results in an out-of-bounds free that
could corrupt the LPI domain.
> + vm->vpe_db_base = 0;
> + }
> +}
> +
> +void vgic_v5_teardown(struct kvm *kvm)
> +{
> + struct vgic_dist *dist = &kvm->arch.vgic;
> + struct kvm_vcpu *vcpu, *vcpu0;
> + bool release_vm_id = true;
> + unsigned long i;
> + int rc;
> +
> + lockdep_assert_held(&kvm->arch.config_lock);
> +
> + /*
> + * If the VM's ID isn't valid, then we either failed init very early or
> + * we've been called a second time. Nothing to do here in either case.
> + */
> + if (kvm->arch.vgic.gicv5_vm.vm_id == VGIC_V5_VM_ID_INVAL)
> + return;
> +
> + if (kvm->arch.vgic.gicv5_vm.vmte_allocated) {
> + /* Make the VM invalid */
> + vcpu0 = kvm_get_vcpu(kvm, 0);
> + rc = vgic_v5_send_command(vcpu0, VMTE_MAKE_INVALID);
> + if (rc) {
> + kvm_err("could not make VMTE invalid\n");
> + release_vm_id = false;
> + goto out_free_doorbells;
[Severity: High]
If the IRS hardware is wedged and VMTE_MAKE_INVALID fails, does jumping
straight to out_free_doorbells cause a use-after-free of the LPIs?
The error path correctly quarantines the VM ID by clearing release_vm_id to
prevent immediate reuse. However, unconditionally branching to
out_free_doorbells returns the doorbell IRQs to the global allocator. Since
the wedged hardware still considers the VMTE valid, it could continue firing
interrupts using the freed LPI numbers, potentially corrupting state if
those LPIs are reallocated to other devices or VMs.
> + }
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260904113404.4051341-1-sascha.bischoff@arm.com?part=14
next prev parent reply other threads:[~2026-09-04 12:50 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 11:34 [PATCH v6 00/49] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-09-04 11:34 ` [PATCH v6 01/49] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-09-04 11:35 ` [PATCH v6 02/49] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-09-04 11:35 ` [PATCH v6 03/49] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-09-04 11:36 ` [PATCH v6 04/49] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-09-04 12:07 ` sashiko-bot
2026-09-04 12:16 ` Sascha Bischoff
2026-09-04 11:36 ` [PATCH v6 05/49] arm64/sysreg: Add GICv5 GIC VDPEND encoding Sascha Bischoff
2026-09-04 11:37 ` [PATCH v6 06/49] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-09-04 12:14 ` sashiko-bot
2026-09-04 12:21 ` Sascha Bischoff
2026-09-04 11:37 ` [PATCH v6 07/49] KVM: arm64: gic-v5: Cache host IRS ID registers Sascha Bischoff
2026-09-04 12:25 ` sashiko-bot
2026-09-04 12:37 ` Sascha Bischoff
2026-09-04 11:38 ` [PATCH v6 08/49] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-09-04 12:26 ` sashiko-bot
2026-09-04 11:38 ` [PATCH v6 09/49] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-09-04 12:24 ` sashiko-bot
2026-09-04 11:39 ` [PATCH v6 10/49] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-09-04 12:30 ` sashiko-bot
2026-09-04 11:39 ` [PATCH v6 11/49] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-09-04 12:39 ` sashiko-bot
2026-09-04 11:40 ` [PATCH v6 12/49] KVM: arm64: vgic: Enforce model-specific vCPU limits Sascha Bischoff
2026-09-04 11:40 ` [PATCH v6 13/49] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-09-04 12:36 ` sashiko-bot
2026-09-04 11:41 ` [PATCH v6 14/49] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-09-04 12:50 ` sashiko-bot [this message]
2026-09-04 11:41 ` [PATCH v6 15/49] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-09-04 12:42 ` sashiko-bot
2026-09-04 11:42 ` [PATCH v6 16/49] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-09-04 13:08 ` sashiko-bot
2026-09-04 11:42 ` [PATCH v6 17/49] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-09-04 11:43 ` [PATCH v6 18/49] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-09-04 11:43 ` [PATCH v6 19/49] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-09-04 11:44 ` [PATCH v6 20/49] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-09-04 12:59 ` sashiko-bot
2026-09-04 11:44 ` [PATCH v6 21/49] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-09-04 13:00 ` sashiko-bot
2026-09-04 11:45 ` [PATCH v6 22/49] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-09-04 13:10 ` sashiko-bot
2026-09-04 11:45 ` [PATCH v6 23/49] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-09-04 13:05 ` sashiko-bot
2026-09-04 11:46 ` [PATCH v6 24/49] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-09-04 11:46 ` [PATCH v6 25/49] KVM: arm64: gic-v5: Add GIC VDPEND hyp call Sascha Bischoff
2026-09-04 11:47 ` [PATCH v6 26/49] KVM: arm64: gic: Introduce set_pending_state() to irq_ops Sascha Bischoff
2026-09-04 11:47 ` [PATCH v6 27/49] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-09-04 11:48 ` [PATCH v6 28/49] Documentation: KVM: Extend VGICv5 device attribute docs Sascha Bischoff
2026-09-04 13:25 ` sashiko-bot
2026-09-04 11:49 ` [PATCH v6 29/49] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd Sascha Bischoff
2026-09-04 11:49 ` [PATCH v6 30/49] KVM: arm64: gic-v5: Mask per-vCPU PPI state in vgic_v5_finalize_ppi_state() Sascha Bischoff
2026-09-04 11:50 ` [PATCH v6 31/49] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors Sascha Bischoff
2026-09-04 13:27 ` sashiko-bot
2026-09-04 11:50 ` [PATCH v6 32/49] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region Sascha Bischoff
2026-09-04 13:34 ` sashiko-bot
2026-09-04 11:51 ` [PATCH v6 33/49] KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS Sascha Bischoff
2026-09-04 11:51 ` [PATCH v6 34/49] KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI Sascha Bischoff
2026-09-04 11:52 ` [PATCH v6 35/49] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Sascha Bischoff
2026-09-04 13:45 ` sashiko-bot
2026-09-04 11:52 ` [PATCH v6 36/49] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Sascha Bischoff
2026-09-04 11:53 ` [PATCH v6 37/49] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Sascha Bischoff
2026-09-04 11:53 ` [PATCH v6 38/49] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Sascha Bischoff
2026-09-04 11:54 ` [PATCH v6 39/49] Documentation: KVM: Add the VGICv5 IRS save/restore sequences Sascha Bischoff
2026-09-04 11:54 ` [PATCH v6 40/49] KVM: selftests: Add VGICv5 IRS address attribute tests Sascha Bischoff
2026-09-04 11:55 ` [PATCH v6 41/49] KVM: selftests: Add VGICv5 NR_IRQS " Sascha Bischoff
2026-09-04 11:55 ` [PATCH v6 42/49] KVM: selftests: Add VGICv5 IRS_REGS " Sascha Bischoff
2026-09-04 11:56 ` [PATCH v6 43/49] KVM: selftests: Add VGICv5 IST " Sascha Bischoff
2026-09-04 11:56 ` [PATCH v6 44/49] KVM: selftests: Add VGICv5 USERSPACE_PPIS tests Sascha Bischoff
2026-09-04 11:57 ` [PATCH v6 45/49] KVM: selftests: Add VGICv5 CPU sysreg attribute tests Sascha Bischoff
2026-09-04 11:57 ` [PATCH v6 46/49] KVM: selftests: Add VGICv5 SPI injection tests Sascha Bischoff
2026-09-04 11:58 ` [PATCH v6 47/49] KVM: selftests: Add VGICv5 LPI delivery tests Sascha Bischoff
2026-09-04 13:56 ` sashiko-bot
2026-09-04 11:58 ` [PATCH v6 48/49] KVM: selftests: Add VGICv5 IST save/restore coverage Sascha Bischoff
2026-09-04 13:58 ` sashiko-bot
2026-09-04 11:59 ` [PATCH v6 49/49] KVM: selftests: Add VGICv5 sparse vCPU IDs test Sascha Bischoff
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